Silicon carbide epitaxial substrate, method for manufacturing epitaxial substrate, and method for manufacturing silicon carbide semiconductor device

Abstract

This silicon carbide epitaxial substrate comprises a silicon carbide substrate and a silicon carbide epitaxial layer. The silicon carbide epitaxial layer is disposed on the silicon carbide substrate. The silicon carbide epitaxial layer has a boundary layer, a buffer layer, and a drift layer. The boundary layer is disposed on the silicon carbide substrate. The buffer layer is disposed on the boundary layer. The drift layer is disposed on the buffer layer. The concentration of n-type impurities in the buffer layer is at least 3×1018 / cm3. The concentration of n-type impurities in the boundary layer is higher than the concentration of n-type impurities in the buffer layer.

Description

Silicon carbide epitaxial substrate, epitaxial substrate manufacturing method, and silicon carbide semiconductor device manufacturing method

[0001] The present disclosure relates to a silicon carbide epitaxial substrate, a method for manufacturing an epitaxial substrate, and a method for manufacturing a silicon carbide semiconductor device. This application claims priority to Japanese Patent Application No. 2022-145264, filed on September 13, 2022. The entire contents of this Japanese patent application are incorporated herein by reference.

[0002] International Publication No. 2018 / 043300 (Patent Document 1) discloses a method for manufacturing a silicon carbide semiconductor device that includes a step of measuring the thickness of an epitaxial layer using Fourier transform infrared spectroscopy.

[0003] International Publication No. 2018 / 043300

[0004] A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial layer. The silicon carbide epitaxial layer is provided on the silicon carbide substrate. The silicon carbide epitaxial layer includes a boundary layer, a buffer layer, and a drift layer. The boundary layer is provided on the silicon carbide substrate. The buffer layer is provided on the boundary layer. The drift layer is provided on the buffer layer. The buffer layer has an n-type impurity concentration of 3×10 18 / cm 3 The concentration of n-type impurities in the boundary layer is higher than the concentration of n-type impurities in the buffer layer.

[0005] FIG. 1 is a plan view schematic diagram showing the configuration of a silicon carbide epitaxial substrate according to this embodiment. FIG. 2 is a cross-sectional view schematic diagram taken along line II-II in FIG. 1 . FIG. 3 is a cross-sectional view schematic diagram showing the relationship between the concentration of n-type impurities and depth in a silicon carbide epitaxial substrate according to this embodiment. FIG. 4 is a cross-sectional view schematic diagram showing the configuration of an epitaxial substrate according to this embodiment. FIG. 5 is a cross-sectional view schematic diagram showing the configuration of an epitaxial substrate according to a modification of this embodiment. FIG. 6 is a partial cross-sectional view schematic diagram showing the configuration of an epitaxial substrate manufacturing apparatus. FIG. 7 is a flowchart generally showing a method for manufacturing an epitaxial substrate according to this embodiment. FIG. 8 is a cross-sectional view schematic diagram showing a step of measuring a first distance. FIG. 9 is a flowchart generally showing a method for manufacturing a silicon carbide semiconductor device according to this embodiment. FIG. 10 is a cross-sectional view schematic diagram showing a step of forming a body region. FIG. 11 is a cross-sectional view schematic diagram showing a step of forming a source region. FIG. 12 is a cross-sectional view schematic diagram showing a step of forming a trench in a fifth main surface of a second silicon carbide epitaxial layer. Fig. 13 is a cross-sectional view schematically showing a step of forming a gate insulating film. Fig. 14 is a cross-sectional view schematically showing a step of forming a gate electrode and an interlayer insulating film. Fig. 15 is a cross-sectional view schematically showing a configuration of a silicon carbide semiconductor device according to the present embodiment. Fig. 16 is a cross-sectional view schematically showing a step of measuring a first distance in a silicon carbide epitaxial substrate according to a comparative example. Fig. 17 is a graph showing FTIR measurement results for the silicon carbide epitaxial substrate according to Sample 1. Fig. 18 is a graph showing FTIR measurement results for the silicon carbide epitaxial substrate according to Sample 2.

[0006] [Problem to be Solved by the Present Disclosure] An object of the present disclosure is to provide a silicon carbide epitaxial substrate, a method for manufacturing an epitaxial substrate, and a method for manufacturing a silicon carbide semiconductor device, which are capable of improving the accuracy of measuring the thickness of a silicon carbide epitaxial layer. [Advantages of the Present Disclosure] The present disclosure can provide a silicon carbide epitaxial substrate, a method for manufacturing an epitaxial substrate, and a method for manufacturing a silicon carbide semiconductor device, which are capable of improving the accuracy of measuring the thickness of a silicon carbide epitaxial layer.

[0007] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0008] (1) Silicon carbide epitaxial substrate 100 according to the present disclosure includes a first silicon carbide substrate 30 and a first silicon carbide epitaxial layer 40. First silicon carbide epitaxial layer 40 is provided on first silicon carbide substrate 30. First silicon carbide epitaxial layer 40 includes a first boundary layer 41, a first buffer layer 42, and a first drift layer 43. First boundary layer 41 is provided on first silicon carbide substrate 30. First buffer layer 42 is provided on first boundary layer 41. First drift layer 43 is provided on first buffer layer 42. Concentration C2 of n-type impurities in first buffer layer 42 is 3×10 18 / cm 3 The concentration C3 of the n-type impurity in the first boundary layer 41 is higher than the concentration C2 of the n-type impurity in the first buffer layer 42.

[0009] (2) In silicon carbide epitaxial substrate 100 according to (1) above, n-type impurity concentration C3 in first boundary layer 41 may be higher than n-type impurity concentration C4 in first silicon carbide substrate 30 .

[0010] (3) In the silicon carbide epitaxial substrate 100 according to (1) or (2) above, the value obtained by subtracting the n-type impurity concentration C2 in the first buffer layer 42 from the n-type impurity concentration C3 in the first boundary layer 41 is 1×10 18 / cm 3 It may be more than that.

[0011] (4) In silicon carbide epitaxial substrate 100 according to any one of (1) to (3) above, thickness T1 of first boundary layer 41 may be not less than 0.1 μm and not more than 5 μm.

[0012] (5) In silicon carbide epitaxial substrate 100 according to any one of (1) to (4) above, n-type impurity concentration C2 in first buffer layer 42 may be higher than n-type impurity concentration C1 in first drift layer 43.

[0013] (6) In silicon carbide epitaxial substrate 100 according to any one of (1) to (5) above, concentration C3 of n-type impurities in first boundary layer 41 is 5×1018 / cm 3 1x10 or more 20 / cm 3 It may be the following:

[0014] (7) In the silicon carbide epitaxial substrate 100 according to any one of (1) to (6) above, the concentration C2 of the n-type impurity in the first buffer layer 42 is 1×10 19 / cm 3 It may be the following:

[0015] (8) In silicon carbide epitaxial substrate 100 according to any one of (1) to (7) above, concentration C1 of n-type impurities in first drift layer 43 is 1×10 15 / cm 3 5x10 or more 16 / cm 3 It may be the following:

[0016] (9) A method for manufacturing epitaxial substrate 200 according to the present disclosure includes the following steps: Silicon carbide epitaxial substrate 100 according to any one of (1) to (8) above is prepared. Using silicon carbide epitaxial substrate 100, distance E1 from interface 9 between first boundary layer 41 and first buffer layer 42 to the surface (first main surface 1) of silicon carbide epitaxial substrate 100 is measured. Growth conditions are determined based on the measured distance E1. Epitaxial growth is performed using the determined growth conditions.

[0017] (10) A method for manufacturing silicon carbide semiconductor device 400 according to the present disclosure includes the following steps: Epitaxial substrate 200 is manufactured using the method for manufacturing epitaxial substrate 200 described in (9) above; Epitaxial substrate 200 is processed.

[0018] [Details of the Embodiments of the Present Disclosure] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the same or corresponding parts in the following drawings are given the same reference numerals, and their description will not be repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. Furthermore, for negative indices, in crystallography, a "-" (bar) is placed before the number, but in this specification, a negative sign is placed before the number.

[0019] (Silicon Carbide Epitaxial Substrate) FIG. 1 is a plan view schematically showing the configuration of a silicon carbide epitaxial substrate 100 according to this embodiment. FIG. 2 is a cross-sectional view schematically showing the configuration along line II-II in FIG. 1. As shown in FIGS. 1 and 2, the silicon carbide epitaxial substrate 100 according to this embodiment has a first silicon carbide substrate 30 and a first silicon carbide epitaxial layer 40. The first silicon carbide epitaxial layer 40 is provided on the first silicon carbide substrate 30. The first silicon carbide epitaxial layer 40 is in contact with the first silicon carbide substrate 30. The first silicon carbide epitaxial layer 40 has a first main surface 1.

[0020] First silicon carbide epitaxial layer 40 forms the front surface (first main surface 1) of silicon carbide epitaxial substrate 100. First silicon carbide substrate 30 forms the back surface (second main surface 2) of silicon carbide epitaxial substrate 100. As shown in Figure 1, silicon carbide epitaxial substrate 100 has an outer peripheral edge 6. Outer peripheral edge 6 has, for example, an orientation flat 7 and an arc-shaped portion 8.

[0021] 1 , the orientation flat 7 is linear when viewed in a direction perpendicular to the first main surface 1. The orientation flat 7 extends along a first direction 101. The arc-shaped portion 8 is continuous with the orientation flat 7. The arc-shaped portion 8 is arc-shaped when viewed in a direction perpendicular to the first main surface 1.

[0022] 1 , when viewed in a direction perpendicular to the first main surface 1, the first main surface 1 extends along a first direction 101 and a second direction 102. When viewed in a direction perpendicular to the first main surface 1, the second direction 102 is a direction perpendicular to the first direction 101.

[0023] The first direction 101 is, for example, the <11-20> direction. The first direction 101 may be, for example, the [11-20] direction. The first direction 101 may be, for example, a direction obtained by projecting the <11-20> direction onto the first main surface 1. From another perspective, the first direction 101 may be, for example, a direction including a <11-20> direction component.

[0024] The second direction 102 is, for example, the <1-100> direction. The second direction 102 may be, for example, the [1-100] direction. The second direction 102 may be, for example, a direction obtained by projecting the <1-100> direction onto the first main surface 1. From another perspective, the second direction 102 may be, for example, a direction including a <1-100> direction component.

[0025] The first main surface 1 may be a {0001} plane, or may be a plane inclined with respect to the {0001} plane. When the first main surface 1 is inclined with respect to the {0001} plane, the inclination angle (off angle) with respect to the {0001} plane is, for example, greater than 0° and not greater than 8°. When the first main surface 1 is inclined with respect to the {0001} plane, the inclination direction (off direction) of the first main surface 1 is, for example, the <11-20> direction. The off angle may be 2° or greater and 6° or less.

[0026] As shown in FIG. 1 , the maximum diameter W of the first main surface 1 is not particularly limited, but may be, for example, 100 mm (4 inches) or more. The maximum diameter W may be 125 mm (5 inches) or more, 150 mm (6 inches) or more, or 200 mm (8 inches) or more. The maximum diameter W is not particularly limited, but may be, for example, 400 mm (16 inches) or less. When viewed in a direction perpendicular to the first main surface 1, the maximum diameter W is the longest linear distance between two different points on the outer circumferential edge 6.

[0027] In this specification, 4 inches refers to 100 mm or 101.6 mm (4 inches x 25.4 mm / inch). 6 inches refers to 150 mm or 152.4 mm (6 inches x 25.4 mm / inch). 8 inches refers to 200 mm or 203.2 mm (8 inches x 25.4 mm / inch). 16 inches refers to 400 mm or 406.4 mm (16 inches x 25.4 mm / inch).

[0028] 2 , first silicon carbide substrate 30 has second main surface 2 and third main surface 3. Third main surface 3 is opposite second main surface 2. Second main surface 2 is spaced apart from first silicon carbide epitaxial layer 40. Third main surface 3 is in contact with first silicon carbide epitaxial layer 40. The polytype of silicon carbide constituting first silicon carbide substrate 30 is, for example, 4H. Similarly, the polytype of silicon carbide constituting first silicon carbide epitaxial layer 40 is, for example, 4H.

[0029] 2 , first silicon carbide epitaxial layer 40 has a fourth main surface 4. Fourth main surface 4 is opposite first main surface 1. At fourth main surface 4, first silicon carbide epitaxial layer 40 is in contact with first silicon carbide substrate 30. First silicon carbide epitaxial layer 40 has a first boundary layer 41, a first buffer layer 42, and a first drift layer 43. First drift layer 43 may be a single layer or two or more layers.

[0030] The first boundary layer 41 is provided on the first silicon carbide substrate 30. The first boundary layer 41 is in contact with the first silicon carbide substrate 30. The first boundary layer 41 constitutes the fourth main surface 4. The thickness of the first boundary layer 41 is set to a first thickness T1. The first thickness T1 is, for example, 0.1 μm. The first thickness T1 may be, for example, not less than 0.1 μm and not more than 5 μm. The first thickness T1 is not particularly limited, but may be, for example, not less than 0.3 μm, or not less than 0.5 μm. The first thickness T1 is not particularly limited, but may be, for example, not more than 4 μm, or not more than 3 μm.

[0031] The first buffer layer 42 is provided on the first boundary layer 41. The first buffer layer 42 is in contact with the first boundary layer 41. The thickness of the first buffer layer 42 is set to a second thickness T2. The second thickness T2 may be greater than the first thickness T1. The second thickness T2 is, for example, 0.1 μm or more and 10 μm or less. The second thickness T2 is not particularly limited, but may be, for example, 0.2 μm or more, or 0.5 μm or more. The second thickness T2 is not particularly limited, but may be, for example, 5 μm or less, or 2 μm or less.

[0032] The first drift layer 43 is provided on the first buffer layer 42. The first drift layer 43 is in contact with the first buffer layer 42. The first drift layer 43 constitutes the first main surface 1. The thickness of the first drift layer 43 is set to a third thickness T3. The third thickness T3 is greater than the second thickness T2. The third thickness T3 is, for example, 5 μm or more and 100 μm or less. The third thickness T3 is not particularly limited, but may be, for example, 10 μm or more, or 20 μm or more. The third thickness T3 is not particularly limited, but may be, for example, 80 μm or less, or 60 μm or less.

[0033] The thickness of first silicon carbide substrate 30 is set to a fourth thickness T4. Fourth thickness T4 may be greater than third thickness T3. Fourth thickness T4 is, for example, 200 μm or more and 600 μm or less. Fourth thickness T4 is not particularly limited, but may be, for example, 250 μm or more, or 300 μm or more. Fourth thickness T4 is not particularly limited, but may be, for example, 550 μm or less, or 500 μm or less.

[0034] The interface between first boundary layer 41 and first buffer layer 42 is defined as first interface 9. The distance from first interface 9 to the surface (first main surface 1) of first silicon carbide epitaxial layer 40 is defined as first distance E1. In other words, first distance E1 is the thickness of first silicon carbide epitaxial layer 40 excluding first boundary layer 41. First distance E1 is, for example, the sum of second thickness T2 and third thickness T3.

[0035] (Concentration of n-type impurity) Figure 3 is a schematic diagram showing the relationship between the concentration of n-type impurity and depth in silicon carbide epitaxial substrate 100 according to this embodiment. In Figure 3, the vertical axis represents the concentration of n-type impurity, and the horizontal axis represents the depth in the thickness direction. The vertical axis is a common logarithm scale axis. The horizontal axis is a linear scale axis. In this specification, depth means the distance from first main surface 1 in the thickness direction. The depth is defined as 0 at first main surface 1 and increases as it approaches second main surface 2.

[0036] 3 , the position of depth 0 corresponds to the first main surface 1. The region from the first main surface 1 to the first depth D1 corresponds to the first drift layer 43. In other words, the first depth D1 corresponds to the third thickness T3. The region from the first depth D1 to the second depth D2 corresponds to the first buffer layer 42. In other words, the value obtained by subtracting the first depth D1 from the second depth D2 is the second thickness T2. The region from the second depth D2 to the third depth D3 corresponds to the first boundary layer 41. In other words, the value obtained by subtracting the second depth D2 from the third depth D3 is the first thickness T1. The region deeper than the third depth D3 corresponds to the first silicon carbide substrate 30.

[0037] 3, first drift layer 43 contains n-type impurities such as nitrogen (N). The conductivity type of first drift layer 43 is, for example, n-type. The concentration of the n-type impurities in first drift layer 43 is set to a first concentration C1.

[0038] The first concentration C1 is, for example, 2×10 16 / cm 3 The first concentration C1 is, for example, 1×10 15 / cm 3 5x10 or more 16 / cm 3 The first concentration C1 is not particularly limited, but may be, for example, 3×10 15 / cm 3 It may be 5×10 or more. 15 / cm 3 The first concentration C1 is not particularly limited, but may be, for example, 4×10 16 / cm 3It may be 3×10 or less. 16 / cm 3 It may be the following:

[0039] 3, the first buffer layer 42 contains n-type impurities such as nitrogen. The conductivity type of the first buffer layer 42 is, for example, n-type. The concentration of the n-type impurities in the first buffer layer 42 is set to a second concentration C2. The second concentration C2 is higher than the first concentration C1.

[0040] The second concentration C2 is, for example, 7×10 18 / cm 3 The second concentration C2 is 3×10 18 / cm 3 The second concentration C2 is not particularly limited, but may be, for example, 5×10 18 / cm 3 It may be 7×10 or more. 18 / cm 3 The second concentration C2 is not particularly limited, but may be, for example, 1×10 19 / cm 3 It may be 8×10 or less. 18 / cm 3 It may be the following:

[0041] 3, the first boundary layer 41 contains an n-type impurity such as nitrogen. The conductivity type of the first boundary layer 41 is, for example, n-type. The concentration of the n-type impurity in the first boundary layer 41 is set to a third concentration C3.

[0042] The third concentration C3 is, for example, 1×10 19 / cm 3 The third concentration C3 is, for example, 5×10 18 / cm 3 1x10 or more 20 / cm 3 The third concentration C3 is not particularly limited, but may be, for example, 7×10 18 / cm 3 It may be 9×10 or more. 18 / cm 3 The third concentration C3 is not particularly limited, but may be, for example, 7×10 19 / cm 3It may be 3×10 or less. 19 / cm 3 It may be the following:

[0043] The third concentration C3 is higher than the second concentration C2. The value obtained by subtracting the second concentration C2 from the third concentration C3 is, for example, 3×10 18 / cm 3 The value obtained by subtracting the second concentration C2 from the third concentration C3 is, for example, 1×10 18 / cm 3 The value obtained by subtracting the second concentration C2 from the third concentration C3 is not particularly limited, but may be, for example, 3×10 18 / cm 3 It may be 5×10 or more. 18 / cm 3 The value obtained by subtracting the second concentration C2 from the third concentration C3 is not particularly limited, but may be, for example, 1×10 20 / cm 3 It may be 5×10 or less. 19 / cm 3 It may be the following:

[0044] 3 , first silicon carbide substrate 30 contains n-type impurities such as nitrogen. The conductivity type of first silicon carbide substrate 30 is, for example, n-type. The concentration of the n-type impurity in first silicon carbide substrate 30 is set to a fourth concentration C4. Fourth concentration C4 is, for example, 7×10 18 / cm 3 The fourth concentration C4 is, for example, 3×10 18 / cm 3 1x10 or more 19 / cm 3 It may be the following:

[0045] The absolute value of the value obtained by subtracting the second concentration C2 from the fourth concentration C4 is smaller than the value obtained by subtracting the second concentration C2 from the third concentration C3. The absolute value of the value obtained by subtracting the second concentration C2 from the fourth concentration C4 is, for example, 1×10 17 / cm 3 1x10 or more 18 / cm 3The fourth concentration C4 may be substantially the same as the second concentration C2. The fourth concentration C4 is higher than the first concentration C1. The third concentration C3 is higher than the fourth concentration C4.

[0046] The concentration of n-type impurities is measured by, for example, secondary ion mass spectrometry (SIMS). For SIMS, for example, an IMS7f secondary ion mass spectrometer manufactured by Cameca Corporation can be used. The measurement conditions for SIMS are, for example, O primary ions, ２ ＋ The measurement conditions can be such that the primary ion energy is 8 keV.

[0047] (Configuration of Epitaxial Substrate) Next, the configuration of the epitaxial substrate according to this embodiment will be described. FIG. 4 is a cross-sectional schematic diagram showing the configuration of the epitaxial substrate according to this embodiment. As shown in FIG. 4, the epitaxial substrate 200 has a fifth main surface 15 and a sixth main surface 16. The sixth main surface 16 is opposite the fifth main surface 15.

[0048] Epitaxial substrate 200 has second silicon carbide substrate 50 and second silicon carbide epitaxial layer 60. Second silicon carbide substrate 50 has sixth main surface 16 and seventh main surface 17. Seventh main surface 17 is opposite sixth main surface 16. Second silicon carbide substrate 50 has a thickness designated as seventh thickness T7. The polytype of silicon carbide constituting second silicon carbide substrate 50 is, for example, 4H.

[0049] 4 , second silicon carbide epitaxial layer 60 is provided on second silicon carbide substrate 50. Second silicon carbide epitaxial layer 60 is in contact with second silicon carbide substrate 50. Second silicon carbide epitaxial layer 60 has fifth main surface 15 and eighth main surface 18. Second silicon carbide epitaxial layer 60 is in contact with second silicon carbide substrate 50 at eighth main surface 18. The polytype of silicon carbide constituting second silicon carbide epitaxial layer 60 is, for example, 4H.

[0050] The second silicon carbide epitaxial layer 60 has a second buffer layer 62 and a second drift layer 63. The second buffer layer 62 is provided on, for example, the second silicon carbide substrate 50. The second buffer layer 62 is in contact with, for example, the second silicon carbide substrate 50. The thickness of the second buffer layer 62 is set to a fifth thickness T5. The fifth thickness T5 is smaller than the seventh thickness T7.

[0051] The second drift layer 63 is provided on the second buffer layer 62. The second drift layer 63 is in contact with the second buffer layer 62. The second drift layer 63 constitutes the fifth main surface 15. The thickness of the second drift layer 63 is defined as a sixth thickness T6. The sixth thickness T6 is greater than the fifth thickness T5.

[0052] The distance from eighth main surface 18 to fifth main surface 15 is defined as second distance E2. In other words, second distance E2 is the thickness of second silicon carbide epitaxial layer 60. Second distance E2 is, for example, the sum of fifth thickness T5 and sixth thickness T6.

[0053] Although the above description has been given of a configuration in which second silicon carbide epitaxial layer 60 includes second buffer layer 62 and second drift layer 63, the configuration of epitaxial substrate 200 is not limited to the above configuration. FIG. 5 is a cross-sectional schematic diagram showing the configuration of epitaxial substrate 200 according to a modified example of this embodiment. As shown in FIG. 5 , second silicon carbide epitaxial layer 60 may include second boundary layer 61. Second boundary layer 61 is provided between second silicon carbide substrate 50 and second buffer layer 62. The interface between second boundary layer 61 and second buffer layer 62 is defined as second interface 19. The thickness of second boundary layer 61 is defined as eighth thickness T8. Fifth thickness T5 may be greater than eighth thickness T8.

[0054] When epitaxial substrate 200 has second boundary layer 61, second distance E2 is the distance from the interface (second interface 19) between second boundary layer 61 and second buffer layer 62 to the surface (fifth main surface 15) of second silicon carbide epitaxial layer 60. The configuration of epitaxial substrate 200 may be substantially the same as the configuration of silicon carbide epitaxial substrate 100 (see FIG. 2 ).

[0055] The second silicon carbide substrate 50 corresponds to the first silicon carbide substrate 30 (see FIG. 2 ). The second silicon carbide epitaxial layer 60 corresponds to the first silicon carbide epitaxial layer 40 (see FIG. 2 ). The second boundary layer 61 corresponds to the first boundary layer 41 (see FIG. 2 ). The second buffer layer 62 corresponds to the first buffer layer 42 (see FIG. 2 ). The second drift layer 63 corresponds to the first drift layer 43 (see FIG. 2 ). The fifth main surface 15 corresponds to the first main surface 1 (see FIG. 2 ). The sixth main surface 16 corresponds to the second main surface 2 (see FIG. 2 ).

[0056] (Epitaxial Substrate Manufacturing Apparatus) Next, the configuration of an epitaxial substrate manufacturing apparatus will be described. FIG. 6 is a partial cross-sectional schematic diagram showing the configuration of an epitaxial substrate manufacturing apparatus. The epitaxial substrate manufacturing apparatus 300 is, for example, a hot-wall horizontal CVD (Chemical Vapor Deposition) apparatus. As shown in FIG. 6, the epitaxial substrate manufacturing apparatus 300 mainly includes a reaction chamber 201, a gas supply unit 235, a control unit 245, a heating element 203, a quartz tube 204, a heat insulating material (not shown), and an induction heating coil (not shown).

[0057] The heating element 203 has, for example, a cylindrical shape, and defines a reaction chamber 201 therein. The heating element 203 is made of, for example, graphite. The heating element 203 is provided inside a quartz tube 204. A heat insulating material surrounds the outer periphery of the heating element 203. The induction heating coil is wound, for example, along the outer periphery of the quartz tube 204. The induction heating coil is configured so that an alternating current can be supplied to it from an external power source (not shown). This causes the heating element 203 to be induction heated. As a result, the reaction chamber 201 is heated by the heating element 203.

[0058] The reaction chamber 201 is a space surrounded by an inner wall surface 205 of a heating element 203. A susceptor 210 that holds a silicon carbide substrate is provided in the reaction chamber 201. The susceptor 210 is made of silicon carbide. The silicon carbide substrate is placed on the susceptor 210. The susceptor 210 is placed on a stage 202. The stage 202 is rotatably supported by a rotation shaft 209. The rotation of the stage 202 causes the susceptor 210 to rotate.

[0059] Manufacturing apparatus 300 for silicon carbide epitaxial substrate 100 further includes gas inlet 207 and gas outlet 208. Gas outlet 208 is connected to an exhaust pump (not shown). Arrows in FIG. 6 indicate the flow of gas. Gas is introduced into reaction chamber 201 from gas inlet 207 and exhausted from gas exhaust outlet 208. The pressure inside reaction chamber 201 is adjusted by balancing the amount of gas supplied and the amount of gas exhausted.

[0060] The gas supply unit 235 is configured to be able to supply a mixed gas containing a source gas, a dopant gas, and a carrier gas to the reaction chamber 201. Specifically, the gas supply unit 235 includes, for example, a first gas supply unit 231, a second gas supply unit 232, a third gas supply unit 233, and a fourth gas supply unit 234.

[0061] The first gas supply unit 231 is configured to be able to supply a first gas containing, for example, carbon atoms. The first gas supply unit 231 is, for example, a gas cylinder filled with the first gas. The first gas is, for example, propane (C3H8) gas. The first gas may also be, for example, methane (CH4) gas, ethane (C2H6) gas, acetylene (C2H2) gas, etc.

[0062] The second gas supply unit 232 is configured to be able to supply a second gas containing, for example, silicon atoms. The second gas supply unit 232 is, for example, a gas cylinder filled with the second gas. The second gas is, for example, silane (SiH4) gas. The second gas may be a mixed gas of silane gas and a gas other than silane.

[0063] The third gas supply unit 233 is configured to be able to supply a third gas containing, for example, nitrogen atoms. The third gas supply unit 233 is, for example, a gas cylinder filled with the third gas. The third gas is a doping gas. The third gas is, for example, ammonia gas. Ammonia gas is more susceptible to thermal decomposition than nitrogen gas, which has a triple bond.

[0064] The fourth gas supply unit 234 is configured to be able to supply a fourth gas (carrier gas) such as hydrogen. The fourth gas supply unit 234 is, for example, a gas cylinder filled with hydrogen. The fourth gas may be argon gas.

[0065] The control unit 245 is configured to be able to control the flow rate of the mixed gas supplied from the gas supply unit 235 to the reaction chamber 201. Specifically, the control unit 245 may include a first gas flow rate control unit 241, a second gas flow rate control unit 242, a third gas flow rate control unit 243, and a fourth gas flow rate control unit 244. Each control unit may be, for example, an MFC (Mass Flow Controller). The control unit 245 is disposed between the gas supply unit 235 and the gas inlet 207.

[0066] (Method for manufacturing epitaxial substrate) Next, a method for manufacturing epitaxial substrate 200 according to this embodiment will be described. FIG. 7 is a flowchart that schematically shows the method for manufacturing epitaxial substrate 200 according to this embodiment. As shown in FIG. 7, the method for manufacturing epitaxial substrate 200 according to this embodiment mainly includes a step (S10) of preparing a silicon carbide epitaxial substrate, a step (S20) of measuring a first distance, a step (S30) of determining growth conditions, and a step (S40) of performing epitaxial growth on a second silicon carbide substrate.

[0067] First, a step (S10) of preparing a silicon carbide epitaxial substrate is performed. A silicon carbide single crystal of polytype 4H is produced, for example, by sublimation deposition. Next, a first silicon carbide substrate 30 is prepared by slicing the silicon carbide single crystal, for example, by a wire saw. The first silicon carbide substrate 30 contains an n-type impurity, for example, nitrogen. The conductivity type of the first silicon carbide substrate 30 is, for example, n-type. Next, mechanical polishing is performed on the first silicon carbide substrate 30. Next, chemical mechanical polishing is performed on the first silicon carbide substrate 30.

[0068] Next, a first silicon carbide epitaxial layer 40 is formed on the first silicon carbide substrate 30. Specifically, using a hot-wall type horizontal CVD apparatus shown in Fig. 6, the first silicon carbide epitaxial layer 40 is formed by epitaxial growth on the third main surface 3 of the first silicon carbide substrate 30. Specifically, a first boundary layer 41 is formed on the third main surface 3. A first buffer layer 42 is formed on the first boundary layer 41. A first drift layer 43 is formed on the first buffer layer 42.

[0069] In the epitaxial growth, for example, silane (SiH) and propane (C3H8) are used as source gases, and hydrogen (H2) is used as a carrier gas. The temperature of the epitaxial growth is, for example, about 1400° C. or higher and 1700° C. or lower. In the epitaxial growth, an n-type impurity such as nitrogen is introduced into first silicon carbide epitaxial layer 40.

[0070] The conditions of the flow rates of the source gases, the dopant gas, the carrier gas, and the epitaxial growth time when forming first buffer layer 42 and first drift layer 43 are set to be first growth conditions. In this manner, silicon carbide epitaxial substrate 100 is prepared.

[0071] Next, a step (S20) of measuring a first distance is performed. FIG. 8 is a schematic cross-sectional view showing the step of measuring the first distance. In the step (S20) of measuring the first distance, a distance (first distance E1) from the interface (first interface 9) between first boundary layer 41 and first buffer layer 42 to the surface (first main surface 1) of the first silicon carbide epitaxial layer is measured using silicon carbide epitaxial substrate 100. In other words, the sum of thickness T2 of first buffer layer 42 and thickness T3 of first drift layer 43 is measured.

[0072] The first distance E1 is measured using a Fourier Transform InfraRed spectrometer (FTIR). Measurement of the first distance E1 by FTIR is determined by utilizing the difference in optical constants resulting from the difference in carrier concentration between the first buffer layer 42 and the first boundary layer 41. Specifically, as shown in FIG. 8 , infrared light is irradiated onto the first main surface 1. A portion of the infrared light travels along a first arrow 91. Specifically, a portion of the infrared light is reflected at the interface (first interface 9) between the first boundary layer 41 and the first buffer layer 42. The first distance E1 can be measured by measuring and analyzing the infrared light (first arrow 91) reflected at the first interface 9 and the infrared light reflected at the first main surface 1 as reflected light from the silicon carbide epitaxial substrate 100.

[0073] In FTIR, a Fourier transform infrared spectrophotometer (IRPrestige-21) manufactured by Shimadzu Corporation can be used as a measuring device. The measurement wave number range is, for example, 4700 cm -1 From 650 cm -1 The calculation wave number range is, for example, 3400 cm -1 From 2400 cm -1 The wave number interval is, for example, 4 cm -1 The incident angle of the infrared light is, for example, 25°.

[0074] Next, a step (S30) of determining growth conditions is performed. Second growth conditions are determined based on the measured first distance E1. The second growth conditions are used to manufacture epitaxial substrate 200 shown in FIG. 4 . From another perspective, silicon carbide epitaxial substrate 100 is used as a dummy substrate for determining the second growth conditions. Meanwhile, epitaxial substrate 200 is used, for example, in the manufacture of a silicon carbide semiconductor device, and ultimately constitutes a part of the silicon carbide semiconductor device. Note that silicon carbide epitaxial substrate 100 is not usually used as a part of a silicon carbide semiconductor device, but may constitute a part of the silicon carbide semiconductor device.

[0075] In the step (S30) of determining the growth conditions, when it is desired that second distance E2 (see FIG. 4 ) of epitaxial substrate 200 be longer than first distance E1 (see FIG. 2 ) of silicon carbide epitaxial substrate 100, the second growth conditions are determined so that the epitaxial growth time is longer than that under the first growth conditions, for example. On the other hand, when it is desired that second distance E2 be shorter than first distance E1, the second growth conditions are determined so that the epitaxial growth time is shorter than that under the first growth conditions, for example. Note that the second growth conditions may be determined by changing at least one of the flow rate of the source gas, the flow rate of the dopant gas, and the flow rate of the carrier gas from the first growth conditions.

[0076] Next, a step (S40) of performing epitaxial growth on a second silicon carbide substrate is performed. Second silicon carbide substrate 50 is prepared similarly to first silicon carbide substrate 30 in step (S10) of preparing a silicon carbide epitaxial substrate. Epitaxial growth is performed using a hot-wall type horizontal CVD apparatus shown in FIG. 6. In step (S40) of performing epitaxial growth on second silicon carbide substrate, epitaxial growth is performed using second growth conditions. As a result, second silicon carbide epitaxial layer 60 is formed on second silicon carbide substrate 50. In this manner, epitaxial substrate 200 (see FIG. 4) is manufactured.

[0077] (Method of manufacturing silicon carbide semiconductor device) Next, a method of manufacturing silicon carbide semiconductor device 400 according to this embodiment will be described. Fig. 9 is a flowchart that schematically shows the method of manufacturing silicon carbide semiconductor device 400 according to this embodiment. As shown in Fig. 9, the method of manufacturing silicon carbide semiconductor device 400 according to this embodiment mainly includes a step (S1) of preparing an epitaxial substrate and a step (S2) of processing the epitaxial substrate.

[0078] First, the step of preparing an epitaxial substrate (S1) is performed. In the step of preparing an epitaxial substrate (S1), the epitaxial substrate 200 according to this embodiment (see FIG. 4) is manufactured using the method for manufacturing the epitaxial substrate 200 shown in FIG.

[0079] Next, a step (S2) is performed to process epitaxial substrate 200. Specifically, epitaxial substrate 200 is processed as follows: First, ions are implanted into epitaxial substrate 200.

[0080] 10 is a schematic cross-sectional view showing a step of forming a body region. In the step of forming the body region, p-type impurities such as aluminum are ion-implanted into fifth main surface 15 of second silicon carbide epitaxial layer 60. This forms body region 113 having p-type conductivity. Portions where body region 113 is not formed become second drift layer 63 and second buffer layer 62. The thickness of body region 113 is, for example, 0.9 μm. Second silicon carbide epitaxial layer 60 includes second buffer layer 62, second drift layer 63, and body region 113.

[0081] Next, a step of forming a source region is performed. FIG. 11 is a schematic cross-sectional view showing the step of forming the source region. Specifically, n-type impurities such as phosphorus are ion-implanted into the body region 113. This forms a source region 114 having n-type conductivity. The thickness of the source region 114 is, for example, 0.4 μm. The concentration of the n-type impurity contained in the source region 114 is higher than the concentration of the p-type impurity contained in the body region 113.

[0082] Next, a p-type impurity such as aluminum is ion-implanted into the source region 114 to form a contact region 118. The contact region 118 is formed to penetrate the source region 114 and the body region 113 and to be in contact with the second drift layer 63. The concentration of the p-type impurity contained in the contact region 118 is higher than the concentration of the n-type impurity contained in the source region 114.

[0083] Next, activation annealing is performed to activate the implanted impurities. The temperature of the activation annealing is, for example, 1500° C. or higher and 1900° C. or lower. The activation annealing time is, for example, about 30 minutes. The atmosphere of the activation annealing is, for example, an argon atmosphere.

[0084] Next, a step of forming trenches in the fifth main surface 15 of the second silicon carbide epitaxial layer 60 is performed. FIG. 12 is a cross-sectional schematic diagram showing the step of forming trenches in the fifth main surface 15 of the second silicon carbide epitaxial layer 60. A mask 117 having openings is formed on the fifth main surface 15 including the source region 114 and the contact region 118. The source region 114, the body region 113, and a portion of the second drift layer 63 are removed by etching using the mask 117. For example, inductively coupled plasma reactive ion etching can be used as the etching method. Specifically, for example, inductively coupled plasma reactive ion etching using SF or a mixed gas of SF and O as the reactive gas is used. Recesses are formed in the fifth main surface 15 by etching.

[0085] Next, thermal etching is performed on the recesses. Thermal etching can be performed, for example, by heating the mask 117 formed on the fifth main surface 15 in an atmosphere containing a reactive gas having at least one type of halogen atom. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere can include, for example, Cl2, BCl3, SF6, or CF4. For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as the reactive gas, and setting the heat treatment temperature to, for example, 700°C or higher and 1000°C or lower. The reactive gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. Examples of the carrier gas that can be used include nitrogen gas, argon gas, and helium gas.

[0086] 12 , trenches 56 are formed in fifth main surface 15 by thermal etching. Trench 56 is defined by sidewall surfaces 53 and a bottom wall surface 54. Sidewall surface 53 is formed by source region 114, body region 113, and second drift layer 63. Bottom wall surface 54 is formed by second drift layer 63. Next, mask 117 is removed from fifth main surface 15.

[0087] Next, a step of forming a gate insulating film is performed. FIG. 13 is a cross-sectional schematic diagram showing the step of forming a gate insulating film. Specifically, epitaxial substrate 200 having trenches 56 formed in fifth main surface 15 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300° C. or higher and 1400° C. or lower. This forms gate insulating film 115 that is in contact with second drift layer 63 at bottom wall surface 54, in contact with second drift layer 63, body region 113, and source region 114 at sidewall surface 53, and in contact with source region 114 and contact region 118 at fifth main surface 15.

[0088] Next, a step of forming a gate electrode is performed. FIG. 14 is a cross-sectional view showing a step of forming a gate electrode and an interlayer insulating film. The gate electrode 127 is formed inside the trench 56 so as to contact the gate insulating film 115. The gate electrode 127 is disposed inside the trench 56 and is formed on the gate insulating film 115 so as to face each of the sidewall surface 53 and the bottom wall surface 54 of the trench 56. The gate electrode 127 is formed by, for example, a low pressure chemical vapor deposition (LPCVD) method.

[0089] Next, an interlayer insulating film 126 is formed. The interlayer insulating film 126 is formed so as to cover the gate electrode 127 and to be in contact with the gate insulating film 115. The interlayer insulating film 126 is formed by, for example, chemical vapor deposition. The interlayer insulating film 126 is made of, for example, a material containing silicon dioxide. Next, the interlayer insulating film 126 and part of the gate insulating film 115 are etched so as to form openings over the source region 114 and the contact region 118. As a result, the contact region 118 and the source region 114 are exposed from the gate insulating film 115.

[0090] Next, a step of forming a source electrode is performed. The source electrode 116 is formed so as to be in contact with each of the source region 114 and the contact region 118. The source electrode 116 is formed by, for example, a sputtering method. The source electrode 116 is made of, for example, a material containing Ti (titanium), Al (aluminum), and Si (silicon).

[0091] Next, alloying annealing is performed. Specifically, the source electrode 116 in contact with each of the source region 114 and the contact region 118 is maintained at a temperature of, for example, 900° C. or higher and 1100° C. or lower for about 5 minutes. As a result, at least a portion of the source electrode 116 is silicided. This forms the source electrode 116 in ohmic contact with the source region 114. The source electrode 116 may also form an ohmic contact with the contact region 118.

[0092] Next, the source wiring 119 is formed. The source wiring 119 is electrically connected to the source electrode 116. The source wiring 119 is formed so as to cover the source electrode 116 and the interlayer insulating film 126.

[0093] Next, a step of forming a drain electrode is carried out. First, second silicon carbide substrate 50 is polished at sixth main surface 16. This reduces the thickness of second silicon carbide substrate 50. Next, drain electrode 123 is formed. Drain electrode 123 is formed so as to be in contact with sixth main surface 16. In this manner, silicon carbide semiconductor device 400 according to this embodiment is manufactured.

[0094] 15 is a cross-sectional schematic diagram showing the configuration of a silicon carbide semiconductor device according to this embodiment. Silicon carbide semiconductor device 400 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Silicon carbide semiconductor device 400 mainly includes epitaxial substrate 200, gate electrode 127, gate insulating film 115, source electrode 116, drain electrode 123, source wiring 119, and interlayer insulating film 126. Epitaxial substrate 200 includes second buffer layer 62, second drift layer 63, body region 113, source region 114, and contact region 118. Silicon carbide semiconductor device 400 may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or the like.

[0095] Next, the effects of silicon carbide epitaxial substrate 100, the method for manufacturing an epitaxial substrate, and the method for manufacturing a silicon carbide semiconductor device according to this embodiment will be described.

[0096] In epitaxial substrates used in power devices such as MOSFETs, the concentration of n-type impurities in the buffer layer may be increased to suppress hole migration from the buffer layer to the drift layer during operation of the power device. This prevents basal plane dislocations from becoming stacking faults due to holes reaching the drift layer. However, in this case, the difference between the n-type impurity concentration in the buffer layer and the n-type impurity concentration in the silicon carbide substrate becomes small. This reduces the reflectance of infrared light at the interface between the buffer layer and the silicon carbide substrate, reducing the accuracy of measuring the thickness of the silicon carbide epitaxial layer using FTIR.

[0097] Fig. 16 is a cross-sectional schematic view showing a step of measuring first distance E1 in silicon carbide epitaxial substrate 100 according to the comparative example. Silicon carbide epitaxial substrate 100 according to the comparative example shown in Fig. 16 does not have first boundary layer 41. As shown in Fig. 16 , when first boundary layer 41 is not included, first buffer layer 42 is in contact with first silicon carbide substrate 30. In Fig. 16 , second arrow 92 indicates infrared light reflected at the interface between first drift layer 43 and first buffer layer 42.

[0098] When silicon carbide epitaxial substrate 100 does not have first boundary layer 41 and the difference between n-type impurity concentration C2 in first buffer layer 42 and n-type impurity concentration C4 in first silicon carbide substrate 30 is small, the intensity of infrared light (first arrow 91) reflected at the interface between first buffer layer 42 and first silicon carbide substrate 30 decreases. This increases the influence of infrared light (second arrow 92) reflected at the interface between first drift layer 43 and first buffer layer 42 in FTIR. In other words, the intensity of infrared light (first arrow 91) reflected at the interface between first buffer layer 42 and first silicon carbide substrate 30 is smaller than the intensity of infrared light (second arrow 92) reflected at the interface between first drift layer 43 and first buffer layer 42. This reduces the interference between the infrared light reflected at the first main surface 1 and the infrared light (first arrow 91) reflected at the interface between the first buffer layer 42 and the first silicon carbide substrate 30, thereby reducing the measurement accuracy of the first distance E1.

[0099] In the silicon carbide epitaxial substrate 100 according to this embodiment, the first silicon carbide epitaxial layer 40 includes a first boundary layer 41. The concentration of n-type impurities in the first boundary layer 41 is higher than the concentration of n-type impurities in the first buffer layer 42. This improves the reflectivity of infrared light (first arrow 91) at the interface (first interface 9) between the first boundary layer 41 and the first buffer layer 42. Therefore, the intensity of the infrared light (first arrow 91) reflected at the first interface 9 is higher than the intensity of the infrared light (second arrow 92) reflected at the interface between the first drift layer 43 and the first buffer layer 42. This increases the interference between the infrared light reflected at the first main surface 1 and the infrared light (first arrow 91) reflected at the first interface 9, thereby improving the measurement accuracy of the first distance E1. As a result, the measurement accuracy of the thickness of the first silicon carbide epitaxial layer 40 is improved.

[0100] In the silicon carbide epitaxial substrate 100 according to this embodiment, the concentration C2 of the n-type impurity in the first buffer layer 42 is 3×10 18 / cm 3 As described above, even when the concentration C2 of n-type impurities in first buffer layer 42 is high, a decrease in the measurement accuracy of the thickness of first silicon carbide epitaxial layer 40 can be suppressed.

[0101] The greater the value obtained by subtracting the n-type impurity concentration C2 in the first buffer layer 42 from the n-type impurity concentration C3 in the first boundary layer 41, the more the reflectance of infrared light at the interface 9 between the first boundary layer 41 and the first buffer layer 42 can be improved. In the silicon carbide epitaxial substrate 100 according to this embodiment, the value obtained by subtracting the n-type impurity concentration C2 in the first buffer layer 42 from the n-type impurity concentration C3 in the first boundary layer 41 is 1×10 18 / cm 3 As a result, the measurement accuracy of the first distance E1 can be improved.

[0102] If the concentration C3 of n-type impurities in first boundary layer 41 is excessively high and the thickness of first boundary layer 41 is excessively large, there is a risk that stacking faults formed in first silicon carbide epitaxial layer 40 will increase during epitaxial growth. In silicon carbide epitaxial substrate 100 according to the present embodiment, first boundary layer 41 has a thickness of 5 μm or less. This makes it possible to suppress an increase in stacking faults in first silicon carbide epitaxial layer 40.

[0103] The method for manufacturing epitaxial substrate 200 according to this embodiment includes the steps of measuring first distance E1 using silicon carbide epitaxial substrate 100 and determining growth conditions based on first distance E1. This allows the growth conditions for second silicon carbide epitaxial layer 60 to be determined based on first distance E1, thereby improving the accuracy of second distance E2.

[0104] (Sample Preparation) First, silicon carbide epitaxial substrates 100 according to Sample 1 and Sample 2 were prepared. The silicon carbide epitaxial substrate 100 according to Sample 1 is a comparative example. The silicon carbide epitaxial substrate 100 according to Sample 2 is an example. The silicon carbide epitaxial substrate 100 according to Sample 1 had the same configuration as the silicon carbide epitaxial substrate 100 shown in FIG. 16 . The silicon carbide epitaxial substrate 100 according to Sample 2 had the same configuration as the silicon carbide epitaxial substrate 100 shown in FIGS. 1 to 3 . The silicon carbide epitaxial substrate 100 according to Sample 1 does not have a first boundary layer 41. The silicon carbide epitaxial substrate 100 according to Sample 2 has a first boundary layer 41.

[0105] In silicon carbide epitaxial substrates 100 according to Sample 1 and Sample 2, the concentration C1 of n-type impurities in first drift layer 43 is 2×10 16 / cm 3 In the silicon carbide epitaxial substrates 100 according to Sample 1 and Sample 2, the concentration C2 of the n-type impurity in the first buffer layer 42 was about 7×10 18 / cm 3In silicon carbide epitaxial substrates 100 according to Sample 1 and Sample 2, the concentration C4 of n-type impurities in first silicon carbide substrate 30 was about 7×10 18 / cm 3 In silicon carbide epitaxial substrate 100 according to sample 2, the concentration C3 of n-type impurities in first boundary layer 41 was about 1×10 19 / cm 3 It was set at that level.

[0106] (Experimental Method) Using a Fourier transform infrared spectrophotometer (IRPrestige-21) manufactured by Shimadzu Corporation, the silicon carbide epitaxial substrates 100 of Samples 1 and 2 were irradiated with infrared light. The intensity of the infrared light reflected from the silicon carbide epitaxial substrates 100 was measured for each wave number. The measurement wave number range was 4700 cm -1 From 650 cm -1 The calculation wave number range was 3400 cm -1 From 2400 cm -1 The wave number interval was set to 4 cm. -1 The incident angle of the infrared light was set to 25°.

[0107] (Experimental Results) Fig. 17 is a graph showing the results of FTIR measurement of silicon carbide epitaxial substrate 100 according to Sample 1. Fig. 18 is a graph showing the results of FTIR measurement of silicon carbide epitaxial substrate 100 according to Sample 2. In Fig. 17 and Fig. 18, the vertical axis represents the intensity of reflected light, and the horizontal axis represents the wavenumber of reflected light.

[0108] As shown in Figures 17 and 18, it was confirmed that the intensity spectrum of reflected light with respect to wavenumber is more periodic in silicon carbide epitaxial substrate 100 of Sample 2 compared to silicon carbide epitaxial substrate 100 of Sample 1.

[0109] In FTIR, first distance E1 is calculated based on the intensity spectrum of reflected light with respect to wavenumber. Specifically, first distance E1 is calculated based on the number of local maxima of the intensity spectrum within the calculated wavenumber range. Therefore, compared to silicon carbide epitaxial substrate 100 of sample 1, silicon carbide epitaxial substrate 100 of sample 2 allows first distance E1 to be measured with higher accuracy.

[0110] From the above results, it was confirmed that the measurement accuracy of first distance E1 of the silicon carbide epitaxial layer was improved in silicon carbide epitaxial substrate 100 of the example compared to silicon carbide epitaxial substrate 100 of the comparative example.

[0111] The embodiments and examples disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not by the above-described embodiments, and is intended to include meanings equivalent to the claims and all modifications within the scope thereof.

[0112] 1 First main surface, 2 Second main surface, 3 Third main surface, 4 Fourth main surface, 6 Outer periphery, 7 Orientation flat, 8 Arc-shaped portion, 9 First interface (interface), 15 Fifth main surface, 16 Sixth main surface, 17 Seventh main surface, 18 Eighth main surface, 19 Second interface, 30 First silicon carbide substrate, 40 First silicon carbide epitaxial layer, 41 First boundary layer, 42 First buffer layer, 43 First drift layer, 50 Second silicon carbide substrate, 53 Side wall surface, 54 Bottom wall surface, 56 Trench, 60 Second silicon carbide epitaxial layer, 61 Second boundary layer, 62 Second buffer layer, 63 Second drift layer, 91 First arrow, 92 Second arrow, 100 Silicon carbide epitaxial substrate, 101 First direction, 102 Second direction, 113 1. Body region, 114 Source region, 115 Gate insulating film, 116 Source electrode, 117 Mask, 118 Contact region, 119 Source wiring, 123 Drain electrode, 126 Interlayer insulating film, 127 Gate electrode, 200 Epitaxial substrate, 201 Reaction chamber, 202 Stage, 203 Heating element, 204 Quartz tube, 205 Inner wall surface, 207 Gas inlet, 208 Gas exhaust port, 209 Rotation shaft, 210 Susceptor, 231 First gas supply unit, 232 Second gas supply unit, 233 Third gas supply unit, 234 Fourth gas supply unit, 235 Gas supply unit, 241 First gas flow rate control unit, 242 Second gas flow rate control unit, 243 Third gas flow rate control unit, 244 Fourth gas flow rate control unit, 245 Control unit, 300 Manufacturing apparatus, 400 Silicon carbide semiconductor device, C1 First concentration, C2 Second concentration, C3 Third concentration, C4 Fourth concentration, D1 First depth, D2 Second depth, D3 Third depth, E1 First distance, E2 Second distance, T1 First thickness, T2 Second thickness, T3 Third thickness, T4 Fourth thickness, T5 Fifth thickness, T6 Sixth thickness, T7 Seventh thickness, T8 Eighth thickness, W Maximum diameter.

Claims

1. a silicon carbide substrate; a silicon carbide epitaxial layer provided on the silicon carbide substrate; The silicon carbide epitaxial layer is a boundary layer provided on the silicon carbide substrate; a buffer layer disposed on the boundary layer; a drift layer provided on the buffer layer, The concentration of n-type impurities in the buffer layer is 3×10 18 / cm 3 That's all. a concentration of n-type impurities in the boundary layer is higher than a concentration of n-type impurities in the buffer layer.

2. 2 . The silicon carbide epitaxial substrate according to claim 1 , wherein a concentration of n-type impurities in said boundary layer is higher than a concentration of n-type impurities in said silicon carbide substrate.

3. The n-type impurity concentration in the boundary layer minus the n-type impurity concentration in the buffer layer is 1×10 18 / cm 3 The silicon carbide epitaxial substrate according to claim 1 or 2.

4. 3. The silicon carbide epitaxial substrate according to claim 1, wherein the boundary layer has a thickness of 0.1 μm or more and 5 μm or less.

5. 3 . The silicon carbide epitaxial substrate according to claim 1 , wherein a concentration of n-type impurities in said buffer layer is higher than a concentration of n-type impurities in said drift layer. 4 .

6. The concentration of n-type impurities in the boundary layer is 5×10 18 / cm 3 Above 1 x 10 20 / cm 3 3. The silicon carbide epitaxial substrate according to claim 1, wherein:

7. The concentration of n-type impurities in the buffer layer is 1×10 19 / cm 3 3. The silicon carbide epitaxial substrate according to claim 1, wherein:

8. The concentration of n-type impurities in the drift layer is 1×10 15 / cm 3 Above 5 x 10 16 / cm 3 3. The silicon carbide epitaxial substrate according to claim 1, wherein:

9. A step of preparing a silicon carbide epitaxial substrate according to claim 1 or 2; measuring a distance from an interface between the boundary layer and the buffer layer to a surface of the silicon carbide epitaxial layer using the silicon carbide epitaxial substrate; determining growth conditions based on the measured distance; and performing epitaxial growth using the determined growth conditions.

10. A step of manufacturing an epitaxial substrate by using the method for manufacturing an epitaxial substrate according to claim 9; and processing the epitaxial substrate.