Multilayered ceramic electronic component and method for manufacturing same

Abstract

This multilayered ceramic electronic component comprises: a substantially cube-shaped multilayered portion including a plurality of internal electrode layers and a plurality of dielectric layers that are alternately multilayered, and a cover layer provided on the outside in a multilayered direction of the plurality of internal electrode layers and the plurality of dielectric layers; a side margin portion provided on a side face that, among the six faces of the multilayered portion, is oriented in a first direction substantially orthogonal to the multilayered direction; and an external electrode provided on an end face that, among the six faces of the multilayered portion, is oriented in a second direction substantially orthogonal to the first direction and the multilayered direction, the external electrode being connected to the internal electrode layers. In a cross-sectional view of the multilayered portion taken along the multilayered direction and the first direction, a first end portion in the multilayered direction of the side margin portion adjoins a second end portion in the first direction of the cover layer from the multilayered direction at least at one corner of the multilayered portion.　

Description

Multilayer ceramic electronic component and its manufacturing method

[0001] The present invention relates to a multilayer ceramic electronic component and a method for manufacturing the same.

[0002] A multilayer ceramic capacitor includes a laminated portion in which internal electrodes and dielectric layers are alternately stacked, and side margins that cover both side surfaces of the laminated portion (see, for example, Patent Documents 1 to 3). The side margins are sometimes formed after the formation of the laminated portion in order to improve capacitance and eliminate the need for design margins that take into account the printing accuracy of the internal electrodes and the lamination accuracy. One method for forming the side margins is to press the side surfaces of the laminated portion against a green sheet, and then separate a portion of the green sheet attached to the side surface from the rest of the green sheet to form the side margin.

[0003] JP 2020-113575 A JP 2021-108398 A JP 2022-27939 A

[0004] However, when the side margins are formed as described above, they may peel off from the laminate due to stress caused by the difference in thermal shrinkage rate between the side margins and the laminate during the firing process of the multilayer ceramic capacitor. If the side margins peel off, moisture may enter through the gaps created by the peeling, which may cause deterioration of the characteristics of the multilayer ceramic capacitor.

[0005] SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a multilayer ceramic electronic component that can suppress peeling of the side margins, and a method for manufacturing the same.

[0006] The multilayer ceramic electronic component of the present invention includes a substantially rectangular parallelepiped laminated section including a plurality of alternately stacked internal electrode layers and a plurality of dielectric layers, and cover layers provided on the outer sides of the plurality of internal electrode layers and the plurality of dielectric layers in a lamination direction; side margin sections provided on side surfaces of six surfaces of the laminated section facing a first direction substantially perpendicular to the lamination direction; and external electrodes provided on end surfaces of the six surfaces of the laminated section facing a second direction substantially perpendicular to the first direction and the lamination direction, the external electrodes being connected to the internal electrode layers, wherein, when a cross section of the laminated section taken along the lamination direction and the first direction is viewed, at least one corner of the laminated section has a first end portion in the lamination direction of the side margin portion in contact with a second end portion in the first direction of the cover layer from the lamination direction.

[0007] In the above-described multilayer ceramic electronic component, the at least one corner may have an outwardly convex curved surface, and the first end portion may be in contact with the curved surface provided at the second end portion in the stacking direction.

[0008] In the above-described multilayer ceramic electronic component, the ratio of the distance between the tip of the first end of the side margin portion and the side surface in the first direction to the thickness of the cover layer in the stacking direction may be 0.2 or more.

[0009] In the above-described multilayer ceramic electronic component, a ratio of a distance between a tip of the first end of the side margin portion in the first direction and the side surface to a thickness of the cover layer in the stacking direction may be 0.5 or more.

[0010] In the above-described multilayer ceramic electronic component, the ratio of the distance between the tip of the first end of the side margin portion in the first direction and the side surface to the thickness of the cover layer in the stacking direction may be 2.8 or less.

[0011] In the above-described multilayer ceramic electronic component, a ratio of a distance between a tip of the first end of the side margin portion in the first direction and the side surface to a thickness of the cover layer in the stacking direction may be 1.0 or less.

[0012] In the above-described multilayer ceramic electronic component, the distance between the tip of the first end and the side surface in the first direction may be 2.1 to 240.2 μm, and the thickness of the cover layer in the stacking direction may be 11.2 to 85.2 μm.

[0013] In the above-described multilayer ceramic electronic component, the distance between the tip of the first end and the side surface in the first direction may be 5.0 to 200.0 μm, and the thickness of the cover layer in the stacking direction may be 10.0 to 90.0 μm.

[0014] In the above-described multilayer ceramic electronic component, the distance between the tip of the first end and the side surface in the first direction may be 10.0 to 90.0 μm, and the thickness of the cover layer in the stacking direction may be 20.0 to 55.0 μm.

[0015] The method for manufacturing a multilayer ceramic electronic component of the present invention includes the steps of polishing a laminated section having an approximately rectangular parallelepiped shape, the laminated section including a plurality of alternately stacked internal electrode layers and a plurality of dielectric layers, and cover layers provided on the outside of the stacking direction of the plurality of internal electrode layers and the plurality of dielectric layers; forming side margin portions on side surfaces of six surfaces of the laminated section facing a first direction that is approximately perpendicular to the stacking direction; and forming external electrodes connected to the internal electrode layers on end surfaces of six surfaces of the laminated section facing a second direction that is approximately perpendicular to the first direction and the stacking direction, wherein the step of forming the side margin portions is characterized in that, when a cross section of the laminated section is viewed along the stacking direction and the first direction, a first end of the side margin portion in the stacking direction is formed in at least one corner of the laminated section so as to be in contact with a second end of the cover layer in the first direction from the stacking direction.

[0016] In the above manufacturing method, the step of polishing the laminated portion may form a curved surface that is convex outward at at least one corner portion, and the step of forming the side margin portion may form the first end portion so that it contacts the curved surface provided at the second end portion from the laminated direction.

[0017] According to the present invention, peeling of the side margin portion can be suppressed.

[0018] 1 is a perspective view showing an example of a multilayer ceramic capacitor according to an embodiment; FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line A-A in FIG. 1; FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor taken along line B-B in FIG. 1; FIG. 4 is a cross-sectional view of a comparative multilayer ceramic capacitor taken along line B-B in FIG. 1; FIG. 5 is a flowchart showing an example of a manufacturing process of a multilayer ceramic capacitor; FIG. 6 is a cross-sectional view showing an example of a lamination process; FIG. 7 is a side view of a laminated portion 2s showing an example of a polishing process; FIG. 8 is a side view (part 1) showing an example of a side margin forming process when the end face of the laminated portion is viewed from the front; FIG. 9 is a side view (part 2) showing an example of a side margin forming process when the end face of the laminated portion is viewed from the front; and FIG. 10 is a side view (part 3) showing an example of a side margin forming process when the end face of the laminated portion is viewed from the front.

[0019] Fig. 1 is a perspective view showing an example of a multilayer ceramic capacitor 1 according to an embodiment. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line A-A in Fig. 1. Fig. 3A is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line B-B in Fig. 1.

[0020] The multilayer ceramic capacitor 1 is an example of a multilayer ceramic electronic component and includes a laminated chip 2 having a substantially rectangular parallelepiped shape and external electrodes 3 a, 3 b provided on a pair of end faces 2 A, 2 B of the laminated chip 2 that face each other in the longitudinal direction.

[0021] 1, 2, 3A, and 3B show mutually orthogonal X, Y, and Z directions. The X direction is the length (L) direction of the multilayer ceramic capacitor 1 and coincides with the direction in which a pair of end faces of the multilayer chip 2 face each other. The Y direction is the width (W) direction of the multilayer ceramic capacitor 1 and coincides with the direction in which a pair of side faces of the multilayer chip 2 face each other. The Z direction is the height (H) direction of the multilayer ceramic capacitor 1 and coincides with the lamination direction of the multilayer ceramic capacitor 1. The width direction is an example of a first direction, and the length direction is an example of a second direction.

[0022] 3A , the multilayer chip 2 includes a laminated section 2s having a generally rectangular parallelepiped shape and a pair of side margins 40, 41 covering a pair of side surfaces 2E, 2F of the laminated section 2s that face each other in the width direction of the multilayer ceramic capacitor 1. The laminated section 2s includes dielectric layers 22 containing a ceramic material that functions as a dielectric and internal electrode layers 23 that are alternately stacked, and further includes a pair of cover layers 20, 21 stacked to sandwich the dielectric layers 22 and the internal electrode layers 23 from both sides in the stacking direction. The side margins 40, 41 are arranged adjacent to both ends of each internal electrode layer 23 that is drawn out and exposed on the pair of side surfaces 2E, 2F of the laminated section 2s. As a result, the cover layers 20, 21 and the side margins 40, 41 protect the internal electrode layers 23.

[0023] The internal electrode layers 23 are mainly composed of base metals such as Ni (nickel), Cu (copper), Sn (tin), etc. The internal electrode layers 23 may contain Sn or precious metals such as Pt (platinum), Pd (palladium), Ag (silver), Au (gold), etc., or may use an alloy containing these as the main component of the internal electrode layers 23.

[0024] The dielectric layer 22 is, for example, a compound represented by the general formula ABO ３ The main phase is a ceramic material having a perovskite structure represented by the formula: ３－α For example, the ceramic material includes BaTiO ３ (barium titanate), CaZrO ３ (Calcium zirconate), CaTiO ３ (Calcium titanate), SrTiO ３ (strontium titanate), MgTiO ３ (magnesium titanate), Ba that forms a perovskite structure １-ｘ－ｙ Ca ｘ Sr ｙ Ti １－ｚ Zr ｚ O ３ (0≦x≦1, 0≦y≦1, 0≦z≦1) and the like. １-ｘ－ｙ Ca ｘ Sr ｙ Ti１－ｚ Zr ｚ O ３ Examples include barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate, and barium calcium titanate zirconate.

[0025] The cover layers 20 and 21 are primarily made of a ceramic material. For example, the material of the cover layers 20 and 21 has the same primary ceramic component as that of the dielectric layer 22. The cover layers 20 and 21 are provided on the outer sides of the dielectric layers 22 in the stacking direction, and form the upper surface 2C and the lower surface 2D of the laminate portion 2s in the stacking direction.

[0026] The side margins 40, 41 are mainly made of a ceramic material. For example, the material of the side margins 40, 41 has the same main ceramic component as that of the dielectric layer 22. The side margins 40, 41 are formed on the side surfaces 2E, 2F of the laminated portion 2s after the laminated portion 2s is formed.

[0027] The external electrodes 3a, 3b cover the end faces 2A, 2B of the laminated section 2s that face each other in the longitudinal direction. The longitudinal direction is an example of a second direction that is substantially perpendicular to the lamination direction and the width direction, and is the direction in which the internal electrode layers 23 are drawn out. The external electrodes 3a, 3b extend to the top surface 2C, the bottom surface 2D, and the two side surfaces 2E, 2F. However, the external electrodes 3a, 3b are spaced apart from each other on the top surface 2C, the bottom surface 2D, and the two side surfaces 2E, 2F.

[0028] The external electrodes 3a, 3b have a base metal film mainly composed of a metal such as Cu, Ni, Al (aluminum), or Zn (zinc), or an alloy of two or more of these metals (e.g., an alloy of Cu and Ni), and also contain ceramics such as a glass component for densifying the external electrodes 3a, 3b and a co-material for controlling the sinterability of the external electrodes 3a, 3b. The glass component is an oxide of Ba (barium), Sr (strontium), Ca (calcium), Zn (zinc), Al, Si (silicon), B (boron), or the like. The co-material is, for example, a ceramic component mainly composed of the same material as the main component of the dielectric layer 22.

[0029] The external electrodes 3 a, 3 b may also include a plating layer covering the underlying metal film. The plating layer may be mainly composed of a base metal such as Ni, Cu, or Sn. Furthermore, a layer of conductive resin such as epoxy resin or urethane resin may be formed between the underlying metal film and the plating layer.

[0030] 2, the edges of each internal electrode layer 23 in the longitudinal direction are alternately drawn out and exposed to the end face 2A on which the external electrode 3a of the laminated chip 2 is provided and the end face 2B on which the external electrode 3b is provided. As a result, each internal electrode layer 23 is alternately electrically connected to the external electrode 3a and the external electrode 3b in the stacking direction. In other words, the external electrodes 3a and 3b on each end face 2A and 2B are alternately connected to each internal electrode layer 23 along the stacking direction.

[0031] 3A, in a cross section of the laminated chip 2 taken along the stacking direction and width direction, at the four corners 2r of the laminated portion 2s, the ends 4e of the side margins 40, 41 in the stacking direction are in contact with the ends 20e, 21e of the cover layers 20, 21 in the width direction from the stacking direction. As a result, the ends 20e, 21e of the cover layers 20, 21 are covered by the ends 4e of the side margins 40, 41.

[0032] Each end 20e, 21e of the cover layers 20, 21 has a curved surface with rounded corners due to polishing. The end 4e of the side margin portions 40, 41 in the stacking direction extends over the curved surface area so as to overlap the central area in the width direction.

[0033] 3B is a cross-sectional view of the comparative multilayer ceramic capacitor 1a taken along line B-B in FIG. 1. In FIG. 3B, components common to those in FIG. 3A are designated by the same reference numerals, and their description will be omitted. The comparative multilayer ceramic capacitor 1a has side margin portions 40a and 41a instead of the side margin portions 40 and 41, and has cover layers 20a and 21a instead of the cover layers 20 and 21.

[0034] Unlike the multilayer ceramic capacitor 1 of the embodiment, the ends 20ae, 21ae of the cover layers 20a, 21a in the width direction of the laminated chip 2 are not curved but have approximately right-angled corners. Therefore, the boundary between the end 4ae of the side margin portions 40a, 41a in the stacking direction and the end 20ae, 21ae of the cover layers 20a, 21a in the width direction is not curved but is approximately linear along the stacking direction. Therefore, the end 4ae of the side margin portions 40a, 41a contacts the end 20ae, 21ae of the cover layers 20a, 21a in the width direction, not in the stacking direction of the laminated chip 2.

[0035] 3A, in the multilayer ceramic capacitor 1, the ends 4e of the side margins 40, 41 in the stacking direction are in contact with the ends 20e, 21e of the cover layers 20, 21 in the width direction from the stacking direction, which increases the contact area between the side margins 40, 41 and the multilayer portion 2s, thereby increasing the adhesive strength of the side margins 40, 41 to the multilayer portion 2s. This prevents the side margins 40, 41 from peeling off from the multilayer portion 2s.

[0036] Since peeling of the side margins 40, 41 often begins at the end 4e, increasing the adhesion of the end 4e of the side margins 40, 41 using the above structure is an effective anti-peeling measure. It is preferable that the tip P of the end 4e of the side margin 41 be connected to the surface of the cover layer 20 without creating a step, but even if there is a step of, for example, 10 μm or less, peeling is not a problem in suppressing it. The ends 4e of the side margins 40, 41 in the stacking direction of the laminated chip 2 are an example of a first end, and the ends 20e, 21e of the cover layers 20, 21 in the width direction of the laminated part 2s are an example of a second end.

[0037] Each corner 2r of the laminate 2s is formed with an outwardly convex curved surface, for example, by barrel polishing. The end 4e of the side margin 41 contacts the curved surface of the corner 2r provided at each end 20e, 21e of the cover layers 20, 21 in the stacking direction. Therefore, the end 4e of the side margin 40, 41 is formed to extend toward the center in the width direction along the curved surface of the corner 2r. Therefore, the contact area between the side margin 40, 41 and the laminate 2s is increased compared to when the corner 2r is formed with a flat surface rather than a curved surface, making it possible to increase adhesion.

[0038] The greater the degree of bending of the curved surface of the corner 2r, the greater the contact area between the side margins 40, 41 and the laminate 2s. Here, as shown in Figure 3A, the thickness of the cover layer 20 in the lamination direction is b μm, and the distance in the width direction between the tip P of the end 4e of the side margin 41 and the side surfaces 2E, 2F of the laminate 2s is a μm. The ratio of the distance a to the thickness b (a / b) is defined as a parameter R indicating the degree of bending. Parameter R can be adjusted by the conditions (e.g., time) for barrel polishing the laminate 2s and the density of the green sheets of the material for the cover layers 20, 21.

[0039] The parameter R of the multilayer ceramic capacitor 1 of the embodiment is greater than 0. The larger the parameter R, the stronger the adhesion between the side margin portions 40, 41 and the multilayer portion 2s, making them less likely to peel off. Furthermore, the larger the parameter R, the longer the distance from the outside to the internal electrode layer 23 along the boundary between the side margin portions 40, 41 and the multilayer portion 2s. Since moisture easily penetrates into the interior along the boundary between the side margin portions 40, 41 and the multilayer portion 2s, the larger the parameter R, the longer the penetration path, improving the moisture resistance of the multilayer ceramic capacitor 1.

[0040] When the parameter R is 0.2 or more, a sufficiently large adhesion force is obtained between the laminated portion 2s and the side margins 40, 41, so peeling of the side margins 40, 41 can be more effectively suppressed. Furthermore, when the parameter R is 0.5 or more, the moisture penetration path becomes sufficiently long, which is more preferable. Furthermore, when the parameter R is 2.8 or less, the side margins 40, 41 can be easily formed, which is also preferable. Furthermore, when the parameter R is 1.0 or less, the internal electrode layer 23 is less likely to be scraped off even when the laminated portion 2s is polished, which suppresses loss of capacitance, which is more preferable.

[0041] 3A, the distance a between the tip P and the side surfaces 2E and 2F is 2.1 to 240.2 μm, and the thickness b of the cover layer is 11.2 to 85.2 μm. Setting the range of distance a and thickness b in this manner ensures a sufficiently wide area for the side margins 40 and 41 to exert adhesion to the laminated portion 2s, thereby suppressing peeling of the side margins 40 and 41. Furthermore, setting the distance a to 5.0 to 200.0 μm and the thickness b to 10.0 to 90.0 μm is preferable because it provides a sufficiently long path for moisture to penetrate from the outside into the laminated chip 2. More preferably, the distance a may be set to 10.0 to 90.0 μm and the thickness b to 20.0 to 55.0 μm.

[0042] Furthermore, it is desirable to make the distance a appropriately short so that the internal electrode layer 23 is not scraped off even when the laminated portion 2s is polished. Therefore, the distance a is preferably 200 μm or less, and more preferably 90 μm or less. Furthermore, in order to obtain a sufficiently strong adhesive force between the laminated portion 2s and the side margin portions 40, 41, the distance a is preferably 5 μm or more, and more preferably 10 μm or more.

[0043] On the other hand, from the viewpoint of miniaturization of the multilayer ceramic capacitor 1, the distance b is preferably 90 μm or less, and more preferably 55 μm or less. Furthermore, the longer the distance b, the stronger the multilayer ceramic capacitor 1 is against external shocks and the longer the path for moisture penetration. Therefore, the distance b is preferably 10 μm or more, and more preferably 20 μm or more.

[0044] (Method of Manufacturing Multilayer Ceramic Capacitor) Fig. 4 is a flowchart showing an example of a manufacturing process for the multilayer ceramic capacitor 1. This manufacturing process is an example of a method of manufacturing a multilayer ceramic electronic component.

[0045] (Green Sheet Forming Process) First, the green sheet forming process St1 is performed. In this process, a dielectric material obtained by adding various additive compounds (such as sintering aids) to ceramic powder is wet-mixed with a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer. Using the resulting slurry, a dielectric green sheet is coated on a substrate by, for example, a die coater method or a doctor blade method, and then dried. The substrate is, for example, a PET (polyethylene terephthalate) film.

[0046] The additive compounds for the ceramic powder include oxides of Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium), and Yb (ytterbium)), as well as oxides or glasses of Co (cobalt), Ni, Li (lithium), B (boron), Na (sodium), K (potassium), and Si (silicon).

[0047] (Internal electrode printing process) Next, the internal electrode printing process St2 is performed. In this process, a metal conductive paste for forming internal electrodes containing an organic binder is printed by gravure printing on a dielectric green sheet on a substrate, thereby forming a film of a plurality of internal electrode patterns corresponding to the internal electrode layers 23 at intervals from each other. Ceramic particles are added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but is preferably the same as the main component ceramic of the dielectric layer 22.

[0048] (Laminating Step) Next, the laminating step St3 is performed, which will be described below with reference to FIG.

[0049] 5 is a cross-sectional view showing an example of the lamination step St3. In this step, a laminated sheet 5S is formed by laminating dielectric green sheets 5 on which internal electrode patterns 6 that become the internal electrode layers 23 are printed. Dielectric green sheets 5a and 5b corresponding to the cover layers 20 and 21 are laminated on both end faces in the lamination direction of the laminated sheet 5S, respectively.

[0050] (Compression Bonding Step) Next, the compression bonding step St4 is performed. In this step, the laminated sheet 5S is pressed to compress the plurality of dielectric green sheets 5, 5a, 5b together. The compression bonding means may be, for example, a hydrostatic press, but is not limited to this.

[0051] (Cutting Step) Next, the cutting step St5 is performed. In this step, the laminated sheet 5S is cut in the stacking direction along predetermined cutting lines LW using a cutting blade, thereby obtaining a plurality of laminated parts 2s.

[0052] (Polishing Step) Next, the polishing step St6 is performed, which will be described below with reference to FIG.

[0053] FIG. 6 is a side view of the laminated portion 2s showing an example of the polishing step St6. FIG. 6 shows the end surface 2A of the laminated portion 2s before firing. In this step, the laminated portion 2s is polished by a technique such as barrel polishing. This rounds the corners 2r of the laminated portion 2s. At this time, the parameter R can be adjusted within the above range by appropriately setting the execution conditions (e.g., time) of the barrel polishing of the laminated portion 2s. Furthermore, the larger the size of the polishing aid for barrel polishing, the longer the distance a shown in FIG. 3A becomes.

[0054] (Side Margin Forming Step) Next, the side margin forming step St7 is performed, which will be described below with reference to FIGS.

[0055] 7 to 9 are side views showing an example of the side margin forming step St7 when the end surface 2A of the laminate 2s is viewed from the front. In this example, a process of forming a side margin 41 on one side surface 2F is shown, but the process of forming a side margin 40 on the other side surface 2E is also similar.

[0056] 7, a dielectric green sheet 91 is placed on the surface of a flat elastic body 92. One side surface 2E of the laminated portion 2s is fixed with tape 90, and the other side surface 2F of the laminated portion 2s is placed above the dielectric green sheet 91 so that it faces the surface of the dielectric green sheet 91.

[0057] Next, the tape 90 is moved downward by a pressing device (not shown), whereby the laminated portion 2s moves toward the dielectric green sheet 91 as indicated by the symbol D.

[0058] 8, the side surface 2F of the laminated portion 2s is pressed against the surface of the dielectric green sheet 91. At this time, the pressed portion of the dielectric green sheet 91 is depressed by the pressure from the laminated portion 2s, and the elastic body 92 below it is also depressed. The corresponding portion of the dielectric green sheet 91 is pressed against the side surface 2F of the laminated portion 2s by the restoring force from the elastic body 92. As a result, a part of the dielectric green sheet 91 is stuck to the side surface 2F.

[0059] At this time, the dielectric green sheet 91 is attached along the corners 2r of the laminated portion 2s at both ends of the side surface 2F in the lamination direction. After that, when the pressing force of the laminated portion 2s increases, a shear force is generated between the attached portion of the dielectric green sheet 91 and the other portion, and the two portions are separated from each other.

[0060] 9, the tape 90 is moved upward by a pressing device (not shown). As a result, the laminate 2s moves away from the elastic body 92 as indicated by the symbol U. At this time, the cut-off portion of the dielectric green sheet 91 is attached to the side surface 2F of the laminate 2s, forming the side margin portion 41.

[0061] In this way, side margins 41, 40 are formed on the side surfaces 2F, 2E of the laminated part 2s, respectively, and the laminated part 2s is produced before firing. Note that if the parameter R, which indicates the degree of bending of the corner 2r, is too large, sufficient shear force cannot be obtained when pressing the laminated part 2s, and the side margin 41 may not be formed properly. From this perspective, it is preferable to select an elastic body 92 that deforms to a size greater than the size of the corner 2r when subjected to a predetermined pressing force.

[0062] (Re-polishing Step) Next, a re-polishing step St8 is performed. In this step, the laminated portion 2s having the side margin portions 40, 41 formed thereon is polished again by a technique such as barrel polishing. As a result, the corners of the side margin portions 40, 41 are rounded.

[0063] (External Electrode Forming Process) Next, the external electrode forming process St9 is performed. This process is an example of a process for forming a base metal film of a pair of external electrodes 3a, 3b that covers each of the pair of end faces 2A, 2B of the laminated chip 2, including the side margin portions 40, 41, and is alternately connected to the internal electrode layers 23 along the stacking direction. In this process, a conductive paste containing, for example, metal powder, glass frit, binder, and solvent is applied to each end face 2A, 2B, top face 2C, bottom face 2D, and each side face 2E, 2F of the laminated chip 2. After applying the conductive paste, the base metal film of the external electrodes 3a, 3b is formed by baking. The binder and solvent evaporate during baking. Examples of methods for applying the conductive paste include dipping. Alternatively, the base metal film of such external electrodes 3a, 3b may be formed by sputtering.

[0064] (Firing Step) Next, the firing step St10 is carried out. In this step, the laminated chip 2 on which the external electrodes 3a and 3b are formed is heated in a N ２ After the binder is removed in a reducing atmosphere, the multilayer ceramic capacitor 1 is fired for about an hour at 1300 to 1400°C, sintering the particles in the multilayer chip 2. This is how the multilayer ceramic capacitor 1 is manufactured. After the firing process, the underlying metal film of each external electrode 3a, 3b may be plated with multiple layers of metal, such as Cu, Ni, and Sn. For example, the external electrodes 3a, 3b may be formed by forming a Cu-plated layer, a Ni-plated layer, and a Sn-plated layer on an underlying metal film primarily composed of Ni. Alternatively, the external electrodes 3a, 3b may be formed by forming a Ni-plated layer and a Sn-plated layer on an underlying metal film primarily composed of Cu.

[0065] In this embodiment, at all corners 2r of the laminate 2s, the end portions 4e of the side margin portions 40, 41 in the stacking direction extend in the width direction so as to overlap the end portions in the width direction of the cover layers 20, 21, but this configuration may be formed at at least one corner 2r. However, the more corners 2r having the above configuration, the better the effect of suppressing peeling of the side margin portions 40, 41.

[0066] Next, the evaluation results of the multilayer ceramic capacitor 1 of the example will be described.

[0067]

[0068] Table 1 shows the distance a, thickness b, parameter R, presence or absence of manufacturing defects, the number of samples in which the side margin portions 40 and 41 peeled, and the number of samples in which moisture resistance was poor for multilayer ceramic capacitors 1a and 1b, Samples 1a, 1b, 1c, 1d, 1e, 1f ...

[0069] Samples Nos. 1 to 9 differ in the distance a, thickness b, and parameter R. The distance a, thickness b, and parameter R were adjusted in the polishing step St6.

[0070] Samples No. 2 to 9 are multilayer ceramic capacitors 1 according to the embodiment shown in Fig. 3A. All corners 2r of the multilayer portion 2s of Samples No. 2 to 9 were formed with curved surfaces. As a result, at all corners 2r, the ends 20e, 21e of the cover layers 20, 21 were covered with the ends 4e of the side margin portions 40, 41.

[0071] Sample No. 1 is the comparative multilayer ceramic capacitor 1a shown in Fig. 3B. No curved surfaces were formed at the corners of the multilayer portion 2s of Sample No. 1. The evaluation results are described below.

[0072] (Presence or Absence of Manufacturing Defects) After the side margin forming step St7, it was confirmed whether the side margin portions 40, 41 of each of Samples No. 1 to 9 were formed normally. Only the side margin portions 40, 41 of Sample No. 9, which had the largest parameter R, were not formed normally, and the manufacturing defect was determined to be "present." The side margin portions 40a, 41a, 40, 41 of the other Samples No. 1 to 8 were formed normally. The number of samples confirmed was 1,000 for each of Samples No. 1 to 8.

[0073] As described above, the larger the parameter R, the greater the degree of bending of the corner 2r of the laminated portion 2s. Therefore, as described with reference to FIGS. 7 to 9, in the side margin forming step St7, sufficient shear force is not obtained to peel a portion of the dielectric green sheet 91 attached to the side surface 2F of the laminated portion 2s from the remaining portion. Therefore, from the perspective of ease of manufacturing, it is preferable that the parameter R be 2.8 or less. Furthermore, a parameter R of 1.0 or less is even more preferable, since it makes it difficult for the internal electrode layer 23 to be scraped in the polishing step St6, thereby suppressing capacitance loss. Note that, since the side margins 40 and 41 could not be formed properly in Sample No. 9, peeling and moisture resistance were not evaluated.

[0074] (Presence or Absence of Peeling of Side Margin Portions) After the firing step St10, the presence or absence of peeling of the side margin portions 40a, 41a, 40, and 41 of Samples No. 1 to 8 was visually inspected. The number of inspections was 1000 for each of Samples No. 1 to 8.

[0075] For sample No. 1, in which the parameter R was 0, peeling of the side margin portions 40a, 41a was confirmed in two out of 1,000 samples. In contrast, for the other samples No. 2 to 8, peeling of the side margin portions 40, 41 was not confirmed in any of the samples.

[0076] The smaller the parameter R, the smaller the degree of bending of the corner 2r of the laminated portion 2s. Therefore, when the parameter R is 0, as in sample No. 1, a sufficient contact area cannot be ensured between the side margins 40a, 41a and the laminated portion 2s, and the adhesion between the laminated portion 2s and the side margins 40a, 41a becomes insufficient.

[0077] (Evaluation of Moisture Resistance) In the evaluation of moisture resistance, a rated voltage of 10 V was applied to 200 pieces of each of Samples No. 1 to 8 under conditions of a temperature of 45°C and a humidity of 95%, and the samples were maintained for a predetermined time, after which the electrical resistance of each of Samples No. 1 to 7 was measured. Multilayer ceramic capacitors having an electrical resistance of 10 MΩ or more were judged to be "good," and multilayer ceramic capacitors having an electrical resistance of less than 10 MΩ were judged to be "poor."

[0078] As a result of the evaluation of moisture resistance, one out of 200 samples of Sample No. 1, for which the parameter R was 0, was judged to be "fail." In contrast, all 200 samples of the other Samples Nos. 2 to 8 were judged to be "good." The smaller the parameter R, the smaller the degree of bending of the corner 2r of the multilayer portion 2s, and therefore the shorter the distance from the outside to the internal electrode layer 23 along the boundary between the side margin portions 40, 41 and the multilayer portion 2s, and peeling of the side margin portions 40, 41 is likely to allow moisture to penetrate inside, which will affect the characteristics of the multilayer ceramic capacitor 1.

[0079] Thus, from the viewpoint of preventing peeling of the side margins 40, 41 and improving moisture resistance, the parameter R is preferably 0.2 or greater. When the parameter R is 0.2 or greater, a sufficiently large adhesion force is obtained between the laminated portion 2s and the side margins 40, 41, so that peeling of the side margins 40, 41 can be more effectively suppressed. Furthermore, it is even more preferable that the parameter R is 0.3 or greater, because a larger adhesion force can be obtained between the laminated portion 2s and the side margins 40, 41. Furthermore, it is even more preferable that the parameter R is 0.5 or greater, because the path for moisture penetration becomes sufficiently long.

[0080] Furthermore, setting the distance a to 2.1 to 240.2 μm and the thickness b of the cover layer to 11.2 to 85.2 μm ensures a sufficiently wide area for the side margins 40, 41 to adhere to the laminated portion 2s, thereby preventing peeling of the side margins 40, 41. In this case, the moisture penetration path is sufficiently long, improving moisture resistance. Furthermore, setting the distance a to 5.0 to 200.0 μm and the thickness b to 10.0 to 90.0 μm is preferable because it provides a sufficiently long path for moisture to penetrate from the outside into the laminated chip 2. More preferably, the distance a may be set to 10.0 to 90.0 μm and the thickness b to 20.0 to 55.0 μm.

[0081] Here, it is desirable to make the distance a appropriately short so as not to scrape off the internal electrode layer 23 in the polishing step St6. Therefore, the distance a is preferably 200 μm or less, and more preferably 90 μm or less. Furthermore, in order to obtain a sufficiently large adhesion force between the laminated portion 2s and the side margin portions 40, 41, the distance a is preferably 5 μm or more, and more preferably 10 μm or more.

[0082] On the other hand, from the viewpoint of miniaturization of the multilayer ceramic capacitor 1, the distance b is preferably 90 μm or less, and more preferably 55 μm or less. Furthermore, the longer the distance b, the stronger the multilayer ceramic capacitor 1 is against external impacts and the shorter the path for moisture penetration. Therefore, the distance b is preferably 10 μm or more, and more preferably 20 μm or more.

[0083] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention as described in the claims.

[0084] 1, 1a Multilayer ceramic capacitor 2 Multilayer chip 2r Corner portion 2s Multilayer portion 2A, 2B End face 2C Top face 2D Bottom face 2E, 2F Side face 3a, 3b External electrode 4e End portion 40, 41, 40a, 41a Side margin portion 5, 5a, 5b Dielectric green sheet 20, 21, 20a, 21a Cover layer 20e, 21e End portion 22 Dielectric layer 23 Internal electrode layer

Claims

1. a laminated section having a substantially rectangular parallelepiped shape including a plurality of internal electrode layers and a plurality of dielectric layers that are alternately laminated, and a cover layer provided on the outer side of the plurality of internal electrode layers and the plurality of dielectric layers in a lamination direction; A side margin portion is provided on a side surface of the laminated portion that faces a first direction substantially perpendicular to the laminated direction, among the six faces of the laminated portion; an external electrode provided on an end surface of the laminated portion facing a second direction substantially perpendicular to the first direction and the lamination direction, the external electrode being connected to the internal electrode layer; When a cross section of the laminated portion is viewed along the lamination direction and the first direction, at least one corner of the laminated portion has a first end portion of the side margin portion in the lamination direction in contact with a second end portion of the cover layer in the first direction from the lamination direction, a ratio of a distance between a tip of the first end of the side margin portion in the first direction and the side surface to a thickness of the cover layer in the stacking direction is 2.8 or less.

2. The at least one corner has an outwardly convex curved surface, 2. The multilayer ceramic electronic component according to claim 1, wherein the first end portion is in contact with the curved surface provided at the second end portion in the stacking direction.

3. 3. The multilayer ceramic electronic component according to claim 1, wherein a ratio of a distance between a tip of the first end of the side margin portion in the first direction and the side surface to a thickness of the cover layer in the stacking direction is 0.2 or more.

4. 3. The multilayer ceramic electronic component according to claim 1, wherein a ratio of a distance between a tip of the first end of the side margin portion in the first direction and the side surface to a thickness of the cover layer in the stacking direction is 0.5 or more.

5. 3. The multilayer ceramic electronic component according to claim 1, wherein a ratio of a distance between a tip of the first end of the side margin portion in the first direction and the side surface to a thickness of the cover layer in the stacking direction is 1.0 or less.

6. The multilayer ceramic electronic component according to claim 1 or 2, characterized in that a distance between a tip of the first end and the side surface in the first direction is 2.1 to 240.2 μm, and a thickness of the cover layer in the stacking direction is 11.2 to 85.2 μm.

7. The multilayer ceramic electronic component according to claim 1 or 2, characterized in that the distance between the tip of the first end and the side surface in the first direction is 5.0 to 200.0 μm, and the thickness of the cover layer in the stacking direction is 10.0 to 90.0 μm.

8. The multilayer ceramic electronic component according to claim 1 or 2, characterized in that the distance between the tip of the first end and the side surface in the first direction is 10.0 to 90.0 μm, and the thickness of the cover layer in the stacking direction is 20.0 to 55.0 μm.

9. a step of polishing a laminated portion having a substantially rectangular parallelepiped shape including a plurality of internal electrode layers and a plurality of dielectric layers alternately laminated, and a cover layer provided on the outer side of the plurality of internal electrode layers and the plurality of dielectric layers in a lamination direction; forming a side margin portion on a side surface of the laminated portion that faces a first direction substantially perpendicular to the laminated direction, among six surfaces of the laminated portion; and forming an external electrode connected to the internal electrode layer on an end face of the six faces of the laminated portion that faces a second direction substantially perpendicular to the first direction and the lamination direction, The method for manufacturing a multilayer ceramic electronic component is characterized in that the step of forming the side margin portion is formed so that, when viewed in a cross section of the laminated portion along the stacking direction and the first direction, at least one corner of the laminated portion has a first end portion of the side margin portion in the stacking direction in contact with a second end portion of the cover layer in the first direction from the stacking direction, and the ratio of the distance between the tip of the first end portion of the side margin portion in the first direction and the side surface to the thickness of the cover layer in the stacking direction is 2.8 or less.

10. The step of polishing the laminated portion includes forming an outwardly convex curved surface at the at least one corner portion, 10. The method for manufacturing a multilayer ceramic electronic component according to claim 9, wherein in the step of forming the side margin portion, the first end portion is formed so as to be in contact with the curved surface provided at the second end portion from the stacking direction.