Group iii element nitride semiconductor substrate

Abstract

Provided is a group III element nitride semiconductor substrate which includes a first face and a second face and has a large diameter and with which the occurrence of chipping defects is suppressed when manufacturing a device. A group III element nitride semiconductor substrate according to an embodiment of the present invention includes a first face and a second face, and has a thickness of at least 100 μm, wherein: when, on a straight line from a centroid position on the surface of the first face to a centroid position on the surface of the second face, peak wave numbers corresponding to the E2 H phonon modes are measured at intervals of 5 μm from a spot corresponding to 5 μm inward from the surface of the first face to a spot corresponding to half of the thickness of the substrate and from a spot corresponding to 5 μm inward from the surface of the second face to a spot corresponding to half of the thickness of the substrate, and n peak wave numbers obtained through the measurement are B1-Bn (where n is the number of peak wave numbers measured and an integer obtained by rounding up digits after the decimal point of [(thickness (μm) of group III element nitride semiconductor substrate–5 (μm)) / 5 (μm)]), in order from the side of the surface of the first face, the difference (Bmax-Bmin) between the maximum peak wave number Bmax and the minimum peak wave number Bmin among the n measured values is at most 2.0 cm-1.

Description

Group III element nitride semiconductor substrate

[0001] The present invention relates to a Group III element nitride semiconductor substrate, and more particularly to a Group III element nitride semiconductor substrate having a main surface and a back surface that are opposite surfaces, and that suppresses chipping defects during device fabrication.

[0002] BACKGROUND ART Group III element nitride semiconductor substrates such as gallium nitride (GaN) wafers, aluminum nitride (AlN) wafers, and indium nitride (InN) wafers are used as substrates for various semiconductor devices (see, for example, Patent Document 1).

[0003] The semiconductor substrate has a first surface and a second surface. When the first surface is the main surface and the second surface is the back surface, the main surface is typically a Group III element polar surface, and the back surface is typically a nitrogen polar surface. Epitaxial crystals can be grown on the main surface, and various devices can be fabricated on the main surface.

[0004] Group III element nitride semiconductor substrates are used as base substrates for semiconductor devices such as LEDs and LDs.

[0005] Gallium nitride substrates are prone to defects such as cracks, chipping, and chipping during device fabrication. It is known that such defects are more likely to occur the greater the difference in residual stress within the substrate (Patent Documents 2 to 4). Raman spectroscopy is generally used to evaluate the residual stress within such substrates, and E ２ Ｈ Residual stress is evaluated based on the wave number of the peak corresponding to the phonon mode. It is said that the greater the change in wave number, the greater the change in residual stress.

[0006] In Patent Document 2, the area is 10 cm ２ E in the area excluding the area up to 5 mm inside from the periphery of the surface ２ Ｈ The difference between the maximum and minimum values ​​of the Raman shift corresponding to the phonon mode is 0.5 cm －１ Gallium nitride substrates with the following properties have been reported:

[0007] In Patent Document 3, E is provided at a total of five locations, at the center and four locations on the periphery of the surface.２ Ｈ The difference between the maximum and minimum values ​​of the peak wave number corresponding to the phonon mode is 0.1 cm －１ 1cm or more －１ The following gallium nitride substrates with diameters of 150 mm or more have been reported.

[0008] In Patent Document 4, E ２ Ｈ The difference between the center of gravity of the front surface and the center of gravity of the back surface of the Raman shift amount corresponding to the phonon mode is 0.1 cm －１ 0.5cm or more －１ The difference between the center of gravity of the surface and the periphery is 0.1 cm or less. －１ 0.5cm or more －１ The area is less than or equal to 18 cm ２ The above gallium nitride substrates have been reported.

[0009] On the other hand, semiconductor devices fabricated on gallium nitride substrates are subsequently cut out together with the substrates, and if chipping occurs in the gallium nitride substrates during this cutting process, this can result in a problem of reduced device yield.

[0010] Japanese Patent Publication No. 2005-263609 Japanese Patent No. 4386031 Japanese Patent No. 6405767 Japanese Patent No. 6384229

[0011] An object of the present invention is to provide a Group III element nitride semiconductor substrate having a first surface and a second surface, which is a Group III element nitride semiconductor substrate in which the occurrence of chipping defects during device fabrication is suppressed.

[0012] [1] A Group III nitride semiconductor substrate according to an embodiment of the present invention is a Group III nitride semiconductor substrate having a first surface and a second surface, the substrate having a thickness of 100 μm or more, and on a line extending from the center of gravity of the surface of the first surface to the center of gravity of the surface of the second surface, E ２ ＨWhen measuring peak wavenumbers corresponding to phonon modes, n peak wavenumbers are designated B1 to Bn in order from the surface side of the first surface (where n is the number of measured peak wavenumbers, and is an integer obtained by rounding up the decimal point of [(thickness of the Group III element nitride semiconductor substrate (μm)−5 (μm)) / 5 (μm)]), and the maximum peak wavenumber B among the n measured values ​​is ｍａｘ and the minimum peak wave number B ｍｉｎ The difference (B ｍａｘ -B ｍｉｎ ) is 2.0 cm －１ [2] In the above [1], the absolute values ​​are all 1.5 cm －１ [3] In the above [2], the absolute values ​​are all 1.0 cm －１ [4] In any of [1] to [3] above, the n peak wavenumbers vary so as to define a peak-valley variation curve in the thickness direction of the substrate. [5] In any of [1] to [4] above, the Group III element nitride semiconductor substrate has a diameter of 45 mm or more. [6] In any of [1] to [5] above, the thickness is 300 μm or more. [7] According to another aspect of the present invention, there is provided a bonded substrate. The bonded substrate is formed by bonding the Group III element nitride semiconductor substrate of any of [1] to [6] above and a supporting substrate.

[0013] According to an embodiment of the present invention, it is possible to provide a Group III element nitride semiconductor substrate having a first surface and a second surface, in which the occurrence of chipping defects during device fabrication is suppressed.

[0014] 1 is a schematic cross-sectional view of a group III nitride semiconductor substrate according to an embodiment of the present invention; FIG. 2 is an optical microscope photograph of an end face of a chip obtained in Example 3; FIG. 3 is an optical microscope photograph of an end face of a chip obtained in Comparative Example 1; ２ Ｈ 10 is a conceptual graph illustrating the fluctuation state of the peak wave number corresponding to the phonon mode. ２ Ｈ1 is a graph showing the fluctuation state of the peak wave number corresponding to the phonon mode. ２ Ｈ 1 is a graph showing fluctuations in peak wave numbers corresponding to phonon modes.

[0015] When the expression "weight" appears in this specification, it may be read as "mass," which is commonly used as an SI unit indicating weight.

[0016] The Group III nitride semiconductor substrate according to the embodiment of the present invention is typically a free-standing substrate made of Group III nitride crystal. In this specification, the term "free-standing substrate" refers to a substrate that can be handled as a solid object without being deformed or broken by its own weight when handled. The free-standing substrate can be used as a substrate for various semiconductor devices such as light-emitting elements and power control elements.

[0017] The Group III nitride semiconductor substrate according to the embodiment of the present invention is typically in the form of a wafer (approximately a perfect circle), but may be processed into other shapes, such as a rectangle, as necessary.

[0018] The size (diameter) of the Group III nitride semiconductor substrate according to the embodiment of the present invention may be any appropriate size as long as the effects of the embodiment of the present invention are not impaired. Examples of such sizes include 25 mm (approximately 1 inch), 45 to 55 mm (approximately 2 inches), 95 to 105 mm (approximately 4 inches), 145 to 155 mm (approximately 6 inches), 195 to 205 mm (approximately 8 inches), and 295 to 305 mm (approximately 12 inches). The size (diameter) of the Group III nitride semiconductor substrate according to the embodiment of the present invention is preferably 45 mm or more, and more preferably 50 mm or more.

[0019] The Group III nitride semiconductor substrate according to the embodiment of the present invention has a thickness (the maximum thickness if the thickness is not constant) of 100 μm or more, preferably 300 μm to 1000 μm.

[0020] Representative examples of the Group III element nitride include gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and mixed crystals thereof. These may be used alone or in combination of two or more.

[0021] The group III element nitrides are specifically GaN, AlN, InN, Ga ｘ Al １－ｘ N (1>x>0), Ga ｘ In １－ｘ N(1>x>0), Al ｘ In １－ｘ N (1>x>0), Ga ｘ Al ｙ In ｚ N (1>x>0, 1>y>0, x+y+z=1), which may be doped with various n-type or p-type dopants.

[0022] Typical examples of p-type dopants include zinc (Zn), manganese (Mn), iron (Fe), beryllium (Be), magnesium (Mg), strontium (Sr), and cadmium (Cd). These may be used alone or in combination of two or more.

[0023] Typical examples of n-type dopants include silicon (Si), germanium (Ge), tin (Sn), and oxygen (O). These may be used alone or in combination of two or more.

[0024] The plane orientation of the Group III nitride semiconductor substrate can be the c-plane, m-plane, a-plane, or a specific crystal plane tilted from the c-plane, a-plane, or m-plane, and the effects of the embodiments of the present invention are particularly pronounced when the c-plane is used. Examples of specific crystal planes tilted from the c-plane, a-plane, or m-plane include so-called semi-polar planes such as the {11-22} plane and the {20-21} plane. Furthermore, the plane orientation is not limited to so-called just planes perpendicular to the c-plane, a-plane, or m-plane, or specific crystal planes tilted from these planes, and can also include off-angles within a range of ±5°.

[0025] A Group III element nitride semiconductor substrate according to an embodiment of the present invention is a Group III element nitride semiconductor substrate having a first surface and a second surface. When the first surface is the main surface and the second surface is the back surface, if the surface orientation of the Group III element nitride semiconductor substrate is the c-plane, the main surface is typically a Group III element polar surface, and the back surface is typically a nitrogen polar surface. However, the main surface may be a nitrogen polar surface, or the back surface may be a Group III element polar surface. Epitaxial crystals can be grown on the main surface, and various devices can be fabricated. The back surface can be held by a susceptor or the like, allowing the Group III element nitride semiconductor substrate according to an embodiment of the present invention to be transported.

[0026] In the description of the Group III nitride semiconductor substrate according to the embodiment of the present invention, the first surface will be referred to as the main surface and the second surface will be referred to as the back surface. Therefore, in this specification, the "main surface" may be read as the "first surface," the "first surface" may be read as the "main surface," the "back surface" may be read as the "second surface," and the "second surface" may be read as the "back surface."

[0027] The major surfaces may be specular or non-specular. Preferably, the major surfaces are specular.

[0028] From the viewpoint of epitaxially growing a device layer to obtain semiconductor devices with good device characteristics and little variation in device characteristics between devices, it is preferable that the main surface be a surface from which the process-affected layer has been substantially removed and which has small surface roughness in the microscopic region.

[0029] The back surface may be specular or non-specular.

[0030] A mirror surface is a surface that has been mirror-finished, and refers to a surface in which the surface roughness and waviness have been reduced to the point where light can be reflected and the reflection of an object on the mirror-finished surface can be visually confirmed. In other words, it is a surface in which the magnitude of the surface roughness and waviness after mirror-finishing has been reduced to a level that is sufficiently negligible relative to the wavelength of visible light. Epitaxial crystal growth is fully possible on a mirror-finished surface.

[0031] As a mirror-finishing method, any suitable method can be adopted as long as it does not impair the effects of the embodiment of the present invention. Such methods include, for example, a polishing device using tape, a lapping device using diamond abrasive grains, a CMP (Chemical Mechanical Polish) device using a slurry such as colloidal silica and a nonwoven fabric polishing pad, or a mirror-finishing method using one or a combination of these. If a process-affected layer remains on the surface after processing, the process-affected layer is removed. Methods for removing the process-affected layer include, for example, RIE (Reactive Ion Etching) or a method using a chemical solution to remove the process-affected layer, and a method of annealing the substrate.

[0032] A non-mirror surface is a surface that has not been mirror-finished, and a typical example is a rough surface obtained by a surface-roughening treatment.

[0033] Any appropriate method can be used for the surface roughening treatment as long as it does not impair the effects of the embodiment of the present invention, such as grinding using a grindstone, laser texturing, etching using various chemicals or gases, physical or chemical coating, and mechanical texturing.

[0034] 1 is a schematic cross-sectional view of a group III element nitride semiconductor substrate according to an embodiment of the present invention. As shown in FIG. 1, the group III element nitride semiconductor substrate 100 according to the embodiment of the present invention typically has a primary surface (group III element polar surface) 10 and a back surface (nitrogen polar surface) 20. The group III element nitride semiconductor substrate 100 according to the embodiment of the present invention may also have a side surface 30.

[0035] The end portion of the Group III element nitride semiconductor substrate according to the embodiment of the present invention may have any suitable shape as long as the effect of the embodiment of the present invention is not impaired. Examples of the end portion of the Group III element nitride semiconductor substrate according to the embodiment of the present invention include a shape chamfered so that the main surface side and the back surface side are flat, a shape chamfered so that the main surface side and the back surface side are rounded, a shape chamfered so that only the main surface side of the end portion is flat, and a shape chamfered so that only the back surface side of the end portion is flat.

[0036] When the edge of the Group III nitride semiconductor substrate according to the embodiment of the present invention is chamfered, the chamfered portion may be provided along the entire circumference of the outer periphery, or may be provided along only a portion of the outer periphery.

[0037] In the Group III nitride semiconductor substrate according to the embodiment of the present invention, on a straight line from the center of gravity of the surface of the first surface to the center of gravity of the surface of the second surface, E ２ Ｈ When measuring peak wavenumbers corresponding to phonon modes, n peak wavenumbers are designated B1 to Bn in order from the surface side of the first surface (where n is the number of measured peak wavenumbers, and is an integer obtained by rounding up the decimal point of [(thickness of the Group III element nitride semiconductor substrate (μm)−5 (μm)) / 5 (μm)]), and the maximum peak wavenumber B among the n measured values ​​is ｍａｘ and the minimum peak wave number B ｍｉｎ The difference (B ｍａｘ -B ｍｉｎ ) is 2.0 cm －１ less than 1.5 cm, preferably －１ More preferably, it is 1.0 cm or less. －１ If all of the above absolute values ​​are within the above ranges, it is possible to provide a Group III element nitride semiconductor substrate in which chipping defects during device fabrication are suppressed.

[0038] The above n represents the number of peak wave numbers measured.

[0039] For example, when the thickness of the Group III element nitride semiconductor substrate is 300 μm (when the thickness is a multiple of 5 μm), n is 59. Measurement locations are a point 5 μm from the surface of the first side (peak wavenumber B1), a point 10 μm from the surface of the first side (peak wavenumber B2), a point 15 μm from the surface of the first side (peak wavenumber B3), and then, moving inward by 5 μm at a time, up to a point halfway through the thickness of the substrate (a point 150 μm from the surface of the first side) (peak wavenumber B30). Next, there is a point 5 μm inside from the surface of the second surface (peak wavenumber B59), a point 10 μm inside from the surface of the second surface (peak wavenumber B58), a point 15 μm inside from the surface of the second surface (peak wavenumber B57), and then, moving inward by 5 μm, the point at half the thickness of the substrate (a point 150 μm inside from the surface of the second surface) overlaps with the point 150 μm inside from the surface of the first surface, and is B30.

[0040] For example, when the thickness of the Group III nitride semiconductor substrate is 302 μm (not a multiple of 5 μm), n is 60. Measurement locations are a point 5 μm from the surface of the first surface (peak wavenumber B1), a point 10 μm from the surface of the first surface (peak wavenumber B2), a point 15 μm from the surface of the first surface (peak wavenumber B3), and then, moving inward by 5 μm each time, up to a point 150 μm from the surface of the first surface (peak wavenumber B30) that is closest to the point at half the thickness of the substrate (a point 151 μm from the surface of the first surface). Next, measurements are made at a point 5 μm from the surface of the second side (peak wavenumber B60), a point 10 μm from the surface of the second side (peak wavenumber B59), a point 15 μm from the surface of the second side (peak wavenumber B58), and then in 5 μm increments moving inward to a point 150 μm from the surface of the second side (peak wavenumber B31), which is closest to the point at half the thickness of the substrate (a point 151 μm from the surface of the second side). The distance between the point 150 μm from the surface of the first side (peak wavenumber B30) and the point 150 μm from the surface of the second side (peak wavenumber B31) is 2 μm.

[0041] The present inventors have conducted extensive research to solve the conventional problem that, when semiconductor devices fabricated on a Group III element nitride semiconductor substrate are cut out together with the substrate, chipping defects occur in the gallium nitride substrate, resulting in a decrease in device yield. As a result, in a Group III element nitride semiconductor substrate having a first surface and a second surface, on a line from the position of the center of gravity of the surface of the first surface to the position of the center of gravity of the surface of the second surface, E ２ Ｈ When measuring peak wavenumbers corresponding to phonon modes, n peak wavenumbers are designated B1 to Bn in order from the surface side of the first surface (where n is the number of measured peak wavenumbers, and is an integer obtained by rounding up the decimal point of [(thickness of the Group III element nitride semiconductor substrate (μm)−5 (μm)) / 5 (μm)]), and the maximum peak wavenumber B among the n measured values ​​is ｍａｘ and the minimum peak wave number B ｍｉｎ The difference (B ｍａｘ -B ｍｉｎ ) is related to the size of chipping that occurs when cutting a Group III element nitride semiconductor substrate. Considering that large chippings result in chipping defects, the inventors arrived at the technical idea that if a Group III element nitride semiconductor substrate is designed using the above absolute value as an evaluation criterion, it will be possible to provide a Group III element nitride semiconductor substrate in which the occurrence of chipping defects during device fabrication is suppressed, and have completed the present invention.

[0042] Here, E ２ Ｈ Taking wurtzite gallium nitride (GaN) crystal as an example, the phonon mode is a mode in which adjacent N atoms in the GaN crystal vibrate in the in-plane direction within the C-plane. ２ Ｈ The Raman shift corresponding to the phonon mode is expressed as E in the Raman shift spectrum obtained by Raman analysis. ２ ＨIt is specified by the wave number at the time of the maximum peak of the peak corresponding to the phonon mode. ２ Ｈ The wave number of the phonon mode is 567.6 cm －１ And that E ２ Ｈ The wave number at the maximum peak of the peak corresponding to the phonon mode is 567.6 cm －１ It is described that it appears in the vicinity of

[0043] The n peak wavenumbers may vary, typically, in the thickness direction of the substrate, so as to define a variation curve with a peak-valley shape (concave-convex shape). For example, the peak wavenumbers may vary from the main surface to the back surface according to a variation curve as shown in FIG. 4. According to an embodiment of the present invention, the maximum peak wavenumber B ｍａｘ and the minimum peak wave number B ｍｉｎ The difference (B ｍａｘ -B ｍｉｎ ), i.e., by controlling the difference between the maximum peak and the maximum valley in the fluctuation curve to a predetermined value or less, chipping defects during device fabrication can be suppressed. One of the features of the present embodiment is that the difference between the maximum peak and the maximum valley is controlled, rather than the average degree of fluctuation (average deviation from the center value) in the fluctuation curve. The deviation from the center value in the thickness direction stress (peak wavenumber) represents the magnitude of local crystal lattice distortion. When the distortion is large, it becomes a state in which cracks exist at the atomic level. It can be inferred that chipping occurs through a mechanism in which forces are concentrated on atomic-level cracks during the cutting process, which then propagate into macro-level cracks. Therefore, it can be inferred that chipping defects can be suppressed by controlling the difference between the maximum peak and the maximum valley, which allows evaluation of local stress fluctuations, rather than the average degree of fluctuation. However, such a mechanism is merely inferred and is not intended to limit or restrict the embodiments of the present invention.

[0044] The Group III nitride semiconductor substrate according to the embodiment of the present invention can be manufactured by any appropriate method as long as the effects of the embodiment of the present invention are not impaired. In the following, a preferred method for manufacturing the Group III nitride semiconductor substrate according to the embodiment of the present invention will be described in terms of further exhibiting the effects of the embodiment of the present invention.

[0045] A Group III nitride semiconductor substrate according to an embodiment of the present invention is typically produced by forming a seed crystal film on a primary surface of a base substrate, and then forming a Group III nitride layer on the Group III polar surface of the seed crystal film. The Group III nitride layer (seed crystal film + Group III nitride layer) that will become the freestanding substrate is then separated from the base substrate to obtain a freestanding substrate having a primary surface and a back surface.

[0046] Any suitable material can be used as the base substrate as long as it does not impair the effects of the embodiments of the present invention. Examples of such materials include sapphire, crystal-oriented alumina, gallium oxide, and Al. ｘ Ga １－ｘ Examples include N (0≦x≦1), GaAs, and SiC.

[0047] Any appropriate material can be used as the material of the seed crystal film as long as it does not impair the effects of the embodiment of the present invention. ｘ Ga １－ｘ N (0≦x≦1) and In ｘ Ga １－ｘ N (0≦x≦1), preferably gallium nitride.

[0048] As a method for forming the seed crystal film, any appropriate formation method can be adopted as long as the effects of the embodiment of the present invention are not impaired. Examples of such formation methods include vapor phase growth methods, and preferred examples include metal-organic chemical vapor deposition (MOCVD: Metal-Organic Chemical Vapor Deposition), hydride vapor phase epitaxy (HVPE), pulsed excimer deposition (PXD), MBE, and sublimation. Among these, metal-organic chemical vapor deposition (MOCVD: Metal-Organic Chemical Vapor Deposition) is more preferred as a method for forming the seed crystal film.

[0049] The formation of the seed crystal film by the MOCVD method is preferably carried out by, for example, depositing a low-temperature grown buffer layer to a thickness of 20 nm to 50 nm at 450°C to 550°C, and then laminating a film to a thickness of 2 μm to 4 μm at 1000°C to 1200°C.

[0050] The growth direction of the Group III nitride crystal layer may be any appropriate direction as long as it does not impair the effects of the embodiments of the present invention, such as the normal direction to the c-plane of the wurtzite structure, the normal directions to the a-plane and m-plane, and the normal directions to planes inclined from the c-plane, a-plane, and m-plane.

[0051] As a method for forming the Group III element nitride crystal layer, any appropriate method can be adopted as long as it produces a crystal orientation that roughly follows the crystal orientation of the seed crystal film, as long as it does not impair the effects of the embodiment of the present invention. Examples of such a method include vapor phase growth methods such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), pulsed excited deposition (PXD), MBE, and sublimation; liquid phase growth methods such as Na flux, ammonothermal, hydrothermal, and sol-gel; powder growth methods using solid phase growth of powder; and combinations thereof.

[0052] When the Na flux method is employed as a method for forming a Group III element nitride crystal layer, it is preferable to carry out the Na flux method in accordance with the manufacturing method described in Japanese Patent No. 5244628, by appropriately adjusting conditions etc. so as to more effectively exhibit the effects of the embodiments of the present invention.

[0053] Formation of a Group III element nitride crystal layer by the Na flux method is typically preferably carried out in a nitrogen atmosphere by placing a seed crystal substrate (base substrate + seed crystal film) in a crucible serving as a growth vessel, filling the crucible with a melt composition containing a Group III element, metallic Na, and, if necessary, a dopant (for example, an n-type dopant such as germanium (Ge), silicon (Si), or oxygen (O); a p-type dopant such as beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), or cadmium (Cd)), and then covering the crucible with a lid. The crucible with the lid is then placed in an outer vessel, which is then placed in a pressure-resistant vessel, heated and pressurized in a nitrogen atmosphere, and then rotated while maintaining the temperature and pressure.

[0054] The temperature is increased preferably until it reaches a range of 700° C. to 1000° C., more preferably until it reaches a range of 800° C. to 900° C. In this specification, this temperature may be referred to as the final temperature.

[0055] The temperature rise time is preferably 105 minutes or more, more preferably 120 to 250 minutes, even more preferably 140 to 220 minutes, and particularly preferably 160 to 200 minutes. If the temperature rise time is too short and outside the above range, variations in the timing of the start of crystal growth and the growth rate may occur, which may result in the formation of regions with different residual stresses, and may cause chipping defects when semiconductor devices fabricated on the obtained Group III element nitride semiconductor substrate are cut out together with the substrate.

[0056] The temperature rise time until the temperature reaches 400°C is preferably 5 minutes or more, more preferably 10 to 70 minutes, even more preferably 20 to 60 minutes, and particularly preferably 30 to 50 minutes.

[0057] The temperature rise time from 400°C to the final temperature is preferably 100 minutes or longer, more preferably 110 to 210 minutes, even more preferably 120 to 200 minutes, even more preferably 130 to 190 minutes, particularly preferably 140 to 180 minutes, and most preferably 150 to 170 minutes. If the temperature rise time from 400°C to the final temperature is outside the above range, variations in the timing of crystal growth initiation and growth rate may occur, which may result in the formation of regions with different residual stresses, and chipping defects may occur when semiconductor devices fabricated on the resulting Group III element nitride semiconductor substrate are cut out together with the substrate.

[0058] The pressure is preferably in the range of 1 MPa to 7 MPa, more preferably in the range of 2 MPa to 6 MPa.

[0059] Next, the Group III element nitride crystal layer is separated from the base substrate, thereby obtaining a free-standing substrate including the Group III element nitride crystal layer.

[0060] As a method for separating the group III element nitride crystal layer from the starting substrate, any appropriate method can be adopted as long as it does not impair the effects of the embodiments of the present invention. Such methods include, for example, a method in which the group III element nitride crystal layer is spontaneously separated from the starting substrate by utilizing differential thermal contraction in a temperature-lowering step after growth of the group III element nitride crystal layer, a method in which the group III element nitride crystal layer is separated from the starting substrate by chemical etching, a method in which a laser beam is irradiated from the back side of the starting substrate to peel the group III element nitride crystal layer from the starting substrate by laser lift-off, and a method in which the group III element nitride crystal layer is peeled from the starting substrate by grinding. Furthermore, a free-standing substrate including the group III element nitride crystal layer may be obtained by slicing the group III element nitride crystal layer using a wire saw or the like.

[0061] The Group III element nitride crystal layer thus obtained by the Na flux method is preferably ground with a grinding wheel or the like to flatten the plate surface, and then smoothed by lapping using diamond abrasive grains or the like.

[0062] Next, the outer periphery of the free-standing substrate is ground to form a circular shape with a desired diameter.

[0063] The size of the freestanding substrate may be any appropriate size as long as it does not impair the effects of the embodiments of the present invention, such as 25 mm (approximately 1 inch), 45 to 55 mm (approximately 2 inches), 95 to 105 mm (approximately 4 inches), 145 to 155 mm (approximately 6 inches), 195 to 205 mm (approximately 8 inches), and 295 to 305 mm (approximately 12 inches).

[0064] Next, the main surface and / or the back surface are removed by grinding, lapping, polishing, or the like to thin and flatten the substrate to a desired thickness, thereby obtaining a free-standing substrate.

[0065] When performing surface processing such as grinding, lapping, or polishing, the free-standing substrate is usually attached to a processing platen using wax, etc. At this time, the pressure with which the free-standing substrate is attached to the processing platen, specifically, the pressure applied to the free-standing substrate when attaching it to the processing platen, is appropriately adjusted.

[0066] The thickness of the free-standing substrate after polishing (if the thickness is not constant, the thickness at the thickest point) is preferably 300 μm to 1000 μm.

[0067] If necessary, the outer peripheral edge of the free-standing substrate is chamfered by grinding. If a process-affected layer remains on the main surface, the process-affected layer is substantially removed. Furthermore, if residual stress resulting from the process-affected layer remains on the back surface, the residual stress is removed, and finally, a Group III nitride semiconductor substrate according to an embodiment of the present invention is obtained.

[0068] In the Group III nitride semiconductor substrate according to the embodiment of the present invention, chamfering can be performed by any appropriate chamfering method as long as the effects of the embodiment of the present invention are not impaired. Examples of such chamfering methods include grinding using a diamond grindstone, polishing using tape, and chemical mechanical polishing (CMP) using a slurry such as colloidal silica and a nonwoven polishing pad.

[0069] The obtained Group III element nitride semiconductor substrate can have crystals epitaxially grown on its main surface (Group III element polar surface), and functional layers can be formed to obtain functional devices.

[0070] Examples of epitaxial crystals grown on the obtained Group III element nitride semiconductor substrate include gallium nitride, aluminum nitride, indium nitride, and mixed crystals thereof. Specific examples of such epitaxial crystals include GaN, AlN, InN, Ga ｘ Al １－ｘ N (1>x>0), Ga ｘ In １－ｘ N(1>x>0), Al ｘ In １－ｘ N (1>x>0), Ga ｘ Al ｙ In ｚ N (1>x>0, 1>y>0, x+y+z=1). Examples of functional layers provided on the obtained Group III element nitride semiconductor substrate include a rectifying element layer, a switching element, and a power semiconductor layer in addition to a light-emitting layer. After providing a functional layer on the Group III element polarity surface of the obtained Group III element nitride semiconductor substrate, the nitrogen polarity surface can be processed, for example, by grinding or polishing, to reduce the thickness and thickness distribution of the free-standing substrate.

[0071] The obtained Group III element nitride semiconductor substrate and a support substrate can be bonded together to form a bonded substrate according to an embodiment of the present invention. That is, the bonded substrate according to an embodiment of the present invention is formed by bonding the Group III element nitride semiconductor substrate according to an embodiment of the present invention to a support substrate.

[0072] The bonded substrate according to the embodiment of the present invention may further include any appropriate layer within the scope that does not impair the effects of the embodiment of the present invention. The type, function, number, combination, arrangement, etc. of such layers can be appropriately determined depending on the purpose.

[0073] The thickness of the support substrate may be any appropriate thickness as long as it does not impair the effects of the embodiment of the present invention, and may be, for example, 100 μm to 1000 μm.

[0074] As the support substrate, any appropriate substrate can be used as long as the effects of the embodiments of the present invention are not impaired. The support substrate may be made of a single crystal or a polycrystalline material.

[0075] In a bonded substrate according to an embodiment of the present invention, for example, the bonding surface of the Group III nitride semiconductor substrate and the bonding surface of the support substrate are directly bonded. Specifically, for example, the bonding surface of the support substrate and the bonding surface of the Group III nitride semiconductor substrate are placed opposite each other, and the bonding surfaces of the support substrate and the Group III nitride semiconductor substrate are surface-activated, followed by bonding. Thereafter, a desired epitaxial film can be formed on the film-forming surface of the Group III nitride semiconductor substrate.

[0076] A bonded substrate according to an embodiment of the present invention may include, for example, a bonding layer between a Group III nitride semiconductor substrate and a support substrate. Specifically, for example, the bonding surface of the bonding layer on the main surface of the support substrate and the bonding surface of the Group III nitride semiconductor substrate are opposed to each other, the bonding surface of the bonding layer and the bonding surface of the Group III nitride semiconductor substrate are surface-activated, and then the two are bonded to obtain a bonded substrate according to an embodiment of the present invention. A desired epitaxial film can then be formed on the deposition surface of the Group III nitride semiconductor substrate. Alternatively, a bonding layer may be provided on the main surface of the Group III nitride semiconductor substrate, and the bonding surface of the bonding layer may be directly bonded to the bonding surface of the support substrate. Alternatively, a first bonding layer may be provided on the main surface of the Group III nitride semiconductor substrate, and a second bonding layer may be provided on the main surface of the support substrate, and the bonding surface of the first bonding layer may be directly bonded to the bonding surface of the second bonding layer.

[0077] When the bonded substrate according to the embodiment of the present invention is an embodiment in which a bonding layer is provided between the Group III element nitride semiconductor substrate and the support substrate, the bonding layer is made of tantalum pentoxide, alumina, aluminum nitride, silicon carbide, sialon, or Si （１－ｘ） O ｘ (0.008≦x≦0.408) It is preferable that x is at least one selected from the group consisting of (0.008≦x≦0.408), which can further improve the bonding strength between the support substrate and the Group III element nitride semiconductor substrate.

[0078] Sialon is a ceramic material obtained by sintering a mixture of silicon nitride and alumina, and has the following composition: Si ６－ｚ Al ｚ O z N ８－ｚ That is, sialon has a composition in which alumina is mixed in silicon nitride, and z indicates the mixing ratio of alumina. z is more preferably 0.5 or more. z is more preferably 4.0 or less.

[0079] The present invention will be specifically described below using examples, but the present invention is not limited to these examples. The test and evaluation methods used in the examples are as follows. The term "parts" means "parts by weight" unless otherwise specified, and the term "%" means "% by weight" unless otherwise specified.

[0080] <Raman analysis> (Measurement conditions) Apparatus: Microscopic laser Raman spectrometer LabRam ARAMIS (manufactured by Horiba, Ltd.) Light source: Semiconductor pumped solid state laser (520 nm) Spectrometer slit: 100 μm Laser spot diameter: Φ0.8 μm Objective lens: 100x Detector: CCD (1024 × 256 pixels) Diffraction grating: 2400 gr / mm (Correction conditions) 1708 cm of a Ne lamp was used for wave number calibration. －１ The peak of E of the GaN substrate was used. ２ ＨThe peak corresponding to the phonon mode was approximated with a Gauss-Lorentzian function, and the wavenumber at the maximum peak was calculated. (Measurement Method) Laser light was irradiated onto the Ga surface at the center of gravity of the GaN substrate, and the position where the intensity of the reflected light was maximum was determined as the outermost surface on the Ga surface side. From there, the stage was moved up 5 μm, and Raman spectra were acquired. Raman spectra were then acquired while raising the stage in 5 μm increments. The measurement was interrupted when the raised stage height reached half the thickness of the GaN substrate. The substrate was then turned over, and laser light was irradiated onto the N surface at the center of gravity of the GaN substrate, and the position where the intensity of the reflected light was maximum was determined as the outermost surface on the N surface side. As with the measurement from the Ga surface side, spectra were acquired by raising the stage in 5 μm increments up to half the height of the sample thickness. If the Ga and / or N faces of the GaN substrate are roughened, it is preferable to polish the roughened faces before measurement, and more preferably polish them so that the arithmetic mean roughness Ra is 1.0 nm or less. Even without polishing, it is preferable that the surface to be measured has an arithmetic mean roughness Ra of 1.0 nm or less.

[0081] <E ２ Ｈ Measurement of the difference between the maximum and minimum values ​​of the Raman shift corresponding to the phonon mode> E obtained by Raman analysis ２ Ｈ Peak wave number E corresponding to the phonon mode ２ Ｈ Based on the peak wave number corresponding to the phonon mode, (1) on a straight line from the center of gravity of the outermost surface on the Ga surface side to the center of gravity of the outermost surface on the N surface side, E ２ Ｈ When measuring peak wavenumbers corresponding to phonon modes, n peak wavenumbers are designated B1 to Bn in order from the surface side of the first surface (where n is the number of measured peak wavenumbers, and is an integer obtained by rounding up the decimal point of [(thickness of the Group III element nitride semiconductor substrate (μm)−5 (μm)) / 5 (μm)]), (2) the largest peak wavenumber B among the n measured valuesｍａｘ and the minimum peak wave number B ｍｉｎ The difference (B ｍａｘ -B ｍｉｎ ) was sought.

[0082] <Evaluation of the number of chipping defects when cutting the substrate> The obtained GaN substrate was cut into 10 mm square chips, and the edges of the chips were observed using an optical microscope. Of the chippings observed on the edges, those measuring 100 μm or more inward were counted as chipping defects. The "inward size" here was calculated as follows. First, the entire edge of the chip was imaged using an optical microscope at 50x magnification. In each of the N images obtained, two edges where no chipping occurred were connected by a line to determine the normal edge position. For each chipping, a line was drawn from the edge position formed by the chipping to the normal edge position at the shortest distance. The length of this line was determined as the "inward size."

[0083] Example 1: A 2 μm-thick gallium nitride film was formed on a sapphire substrate by MOCVD to prepare a seed crystal substrate. This seed crystal substrate was placed in an alumina crucible in a nitrogen-atmosphere glove box. Next, metallic gallium and metallic sodium were filled into the crucible so that Ga / Ga+Na (mol%) = 15 mol%, and the crucible was covered with an alumina plate. The crucible was then placed in a stainless steel inner container, which was then placed in a stainless steel outer container that could accommodate it and closed with a container lid. This outer container was placed on a turntable installed in the heating section of the crystal manufacturing apparatus, and the pressure-resistant container was sealed with a lid. Next, the pressure-resistant container was evacuated to 0.1 Pa or less using a vacuum pump. Next, the upper, middle, and lower heaters were adjusted to heat the heating space to 870°C. The temperature was raised to 400°C over 60 minutes and then to 870°C over 120 minutes. This state was maintained for 40 hours. During heating, nitrogen gas was introduced from a nitrogen gas cylinder up to 4.0 MPa, and the outer container was rotated clockwise and counterclockwise at a constant rate of 20 rpm around the central axis. After that, it was naturally cooled to room temperature and reduced in pressure to atmospheric pressure, and the lid of the pressure-resistant container was opened and the crucible was removed from inside. The solidified metallic sodium in the crucible was removed, and the gallium nitride crystal grown on the seed crystal substrate was recovered. The gallium nitride crystal thus obtained was separated from the seed substrate and polished and ground to produce a free-standing gallium nitride crystal substrate with a diameter of 50.8 mm and a thickness of 400 μm. Raman analysis of the produced free-standing substrate was performed, and E ２ Ｈ The difference between the maximum and minimum values ​​of the Raman shift corresponding to the phonon mode was measured and found to be 1.70 cm －１ After the measurement, nine chips were cut out from the freestanding substrate, and the edge of each chip was observed under an optical microscope. The observation was performed at 50x magnification, and chipping in the inward direction that was 100 μm or larger was counted as a chipping defect. No chipping defects occurred.

[0084] Example 2 A freestanding gallium nitride crystal substrate was produced in the same manner as in Example 1. However, in the crystal growth process, the temperature was raised to 400°C over 40 minutes, and then from 400°C to 870°C over 140 minutes. Raman analysis was carried out in the same manner as in Example 1, and E２ Ｈ The difference between the maximum and minimum values ​​of the Raman shift corresponding to the phonon mode was measured and found to be 1.48 cm －１ After the measurement, nine chips were cut out from the freestanding substrate, and the edge of each chip was observed under an optical microscope. The observation was performed at 50x magnification, and chipping in the inward direction that was 100 μm or larger was counted as a chipping defect. No chipping defects occurred.

[0085] Example 3 A freestanding gallium nitride crystal substrate was produced in the same manner as in Example 1. However, in the crystal growth process, the temperature was raised to 400°C over 40 minutes, and then from 400°C to 870°C over 160 minutes. Raman analysis was carried out in the same manner as in Example 1, and E ２ Ｈ The difference between the maximum and minimum values ​​of the Raman shift corresponding to the phonon mode was measured and found to be 0.93 cm －１ Furthermore, the fluctuation state of the Raman shift from the main surface to the back surface of the substrate is shown in FIG. 5. In addition, from FIG. 5, the average fluctuation width D ａｖｅ was calculated. ａｖｅ was 0.17. ａｖｅ is the average of the absolute values ​​of the differences between the average values ​​of B1 to Bn and each peak wavenumber. After measurement, nine chips were cut out from the freestanding substrate, and the edge of each chip was observed under an optical microscope. Observation was performed at 50x magnification, and chipping inward that was 100 μm or larger was counted as a chipping defect. No chipping defects occurred. An optical microscope photograph of the edge is shown in Figure 2.

[0086] Comparative Example 1 A freestanding gallium nitride crystal substrate was produced in the same manner as in Example 1. However, in the crystal growth step, the temperature was raised to 400°C over 40 minutes, and then from 400°C to 870°C over 60 minutes. Raman analysis was carried out in the same manner as in Example 1, and E ２ Ｈ The difference between the maximum and minimum values ​​of the Raman shift corresponding to the phonon mode was measured and found to be 2.01 cm －１ Furthermore, the variation of the Raman shift from the main surface to the rear surface of the substrate is shown in FIG. 6.ａｖｅ was calculated. ａｖｅ The value was 0.14. Nine chips were cut out from the freestanding substrate after the measurement, and the edge of each chip was observed under an optical microscope. Observation was performed at 50x magnification, and chipping inward that was 100 μm or larger was counted as a chipping defect. Chipping defects occurred in four of the nine chips, for a total of 10 locations. An optical microscope photograph of the edge where chipping defects occurred is shown in Figure 3.

[0087] [Evaluation] As is clear from the examples and comparative examples, E ２ Ｈ It can be seen that chipping defects can be suppressed by controlling the difference between the maximum and minimum values ​​of the Raman shift (peak wave number) corresponding to the phonon mode to a predetermined value or less. Furthermore, as is clear from a comparison between Example 3 and Comparative Example 1, the average fluctuation width D ａｖｅ It can be seen that even if the difference between the maximum and minimum values ​​of the peak wave number is large, the chipping suppression effect cannot be obtained.

[0088] The group III nitride semiconductor substrate according to the embodiment of the present invention can be used as a substrate for various semiconductor devices.

[0089] 100 Group III element nitride semiconductor substrate 10 Main surface 20 Back surface 30 Side surface

Claims

1. A group-III nitride semiconductor substrate having a first surface and a second surface, with a thickness of 100 μm or more, on a straight line from the center-of-gravity position of the surface of the first surface to the center-of-gravity position of the surface of the second surface, from a point 5 μm inside the surface of the first surface to a point half of the substrate thickness, and from a point 5 μm inside the surface of the second surface to a point half of the substrate thickness, E is measured at 5-μm intervals ２ Ｈ When measuring the n peak frequencies corresponding to the E phonon modes, when the n peak frequencies are B1 to Bn in order from the side of the surface of the first surface (where n is the number of measured peak frequencies, and is the integer obtained by rounding up the decimal part of [(thickness of the group-III nitride semiconductor substrate (μm) - 5 (μm)) / 5 (μm)]), the maximum peak frequency B among the n measured values ｍａｘ and the minimum peak frequency B ｍｉｎ the difference between them (B ｍａｘ - B ｍｉｎ ) is 2.0 cm －１ or less, A group-III nitride semiconductor substrate.

2. The difference (Bmax - Bmin) is all 1.5 cm －１ or less, the group-III nitride semiconductor substrate according to claim 1.

3. The difference (Bmax - Bmin) is all 1.0 cm －１ or less, the group-III nitride semiconductor substrate according to claim 2.

4. The n peak frequencies vary so as to define a valley-shaped variation curve in the thickness direction of the substrate, the group-III nitride semiconductor substrate according to claim 1.

5. The diameter is 45 mm or more, the group-III nitride semiconductor substrate according to claim 1.

6. The thickness is 300 μm or more, the group-III nitride semiconductor substrate according to claim 1.

7. A bonded substrate, wherein a group III nitride semiconductor substrate according to any one of claims 1 to 6 is bonded to a support substrate. The bonded substrate.