High-frequency semiconductor package

Abstract

A ground terminal (11b), first to third ground patterns (11a, 21a, 21b), first and second ground via holes (12b, 22), and a third connection member (25) constitute an electromagnetic shield structure that surrounds a signal terminal (14b), first and second signal patterns (14a, 24), a first signal via hole (12a), a semiconductor chip (103), and first and second connection members (26a, 26b).

Description

High-frequency semiconductor packages

[0001] The present disclosure relates to a high frequency semiconductor package having electromagnetic shielding.

[0002] In recent years, electronic devices have been required to be more compact and have higher functionality, resulting in a demand for higher density mounting of board-mounted components. For wireless front-end components of communication devices such as smartphones, mobile phone base stations, and radar equipment, high density mounting can cause particular problems with electromagnetic interference between high-frequency devices. For this reason, several structures have been proposed that provide electromagnetic shielding for individual high-frequency devices. Specifically, a structure has been proposed in which an electromagnetic shield is formed by forming a metal film on the outside of the sealing resin of a package and electrically connecting the metal film to the ground wiring of the package (see, for example, Patent Document 1).

[0003] Japanese Patent Publication No. 2017-022167

[0004] However, special processes such as sputtering, vapor deposition, and plating are required to form the metal film on the outside of the sealing resin, which results in higher manufacturing costs than conventional resin-sealed packages. Another problem is that the connection area between the metal film and the package ground wiring is small, resulting in low mechanical reliability.

[0005] The present disclosure has been made to solve the above-mentioned problems, and its object is to obtain a semiconductor device that can reduce manufacturing costs and improve mechanical reliability.

[0006] A high frequency semiconductor package according to the present disclosure includes a first substrate having a first base material, a signal terminal and a ground terminal provided on a lower surface of the first base material, a first signal pattern and a first ground pattern provided on an upper surface of the first base material, a first signal via hole penetrating the first base material to electrically connect the signal terminal and the first signal pattern, and a first ground via hole penetrating the first base material to electrically connect the ground terminal and the first ground pattern, a semiconductor chip mounted on the upper surface of the first substrate, a second base material, a second signal pattern and a second ground pattern provided on a lower surface of the second base material, a third ground pattern provided on the entire upper surface of the second base material, and a first via hole penetrating the second base material to electrically connect the second ground pattern and the third ground pattern. the ground terminal, the first to third ground patterns, the first and second ground via holes, and the third connecting member form an electromagnetic shielding structure that surrounds the signal terminal, the first and second signal patterns, the first signal via hole, the semiconductor chip, and the first and second connecting members.

[0007] Another high frequency semiconductor package according to the present disclosure includes a first substrate having a first base material, a signal terminal and a ground terminal provided on a lower surface of the first base material, a first signal pattern and a first ground pattern provided on an upper surface of the first base material, a first signal via hole penetrating the first base material and electrically connecting the signal terminal and the first signal pattern, and a first ground via hole penetrating the first base material and electrically connecting the ground terminal and the first ground pattern, a semiconductor chip mounted on the upper surface of the first substrate, a second base material, a second signal pattern and a second ground pattern provided on a lower surface of the second base material, a third ground pattern provided on the entire upper surface of the second base material, and a second ground via hole penetrating the second base material and electrically connecting the second ground pattern and the third ground pattern. a second substrate having a first signal via hole and a second ground via hole; a first connecting member connecting a signal pad of the semiconductor chip to the second signal pattern; a second connecting member connecting the second signal pattern to the first signal pattern; and a third connecting member connecting the first ground pattern to the second ground pattern, wherein the ground terminal, the first to third ground patterns, the first and second ground via holes, and the third connecting member form an electromagnetic shielding structure that covers the periphery of the signal terminal, the first and second signal patterns, the first signal via hole, the semiconductor chip, and the first and second connecting members, and a cavity is provided on the upper surface of the first substrate, an upper surface of the ground terminal is exposed in the cavity, and the semiconductor chip is mounted on the upper surface of the ground terminal inside the cavity.

[0008] In the high-frequency semiconductor package according to the present disclosure, the ground patterns and ground via holes on the first and second substrates surround the semiconductor chip and other components to form an electromagnetic shielding structure. This allows the electromagnetic shielding to be formed using a standard resin-sealed package manufacturing method without using special processes such as vapor deposition, sputtering, or plating, thereby reducing the manufacturing cost of the high-frequency semiconductor package with electromagnetic shielding. Furthermore, the ground patterns and ground via holes, excluding the ground terminals mounted on the motherboard, are located inside the sealing resin. Therefore, the electromagnetic shielding structure is not exposed to the outside of the sealing resin, improving mechanical reliability.

[0009] In another high-frequency semiconductor package according to the present disclosure, the ground patterns and ground via holes on the first and second substrates surround the semiconductor chip and other components to form an electromagnetic shielding structure. This allows the electromagnetic shielding to be formed using a standard package manufacturing method without using special processes such as vapor deposition, sputtering, or plating, thereby reducing the manufacturing cost of a high-frequency semiconductor package with an electromagnetic shield. Furthermore, the ground patterns and ground via holes, excluding the ground terminals mounted on the motherboard, are located inside the package. Therefore, the electromagnetic shielding structure is not exposed to the outside of the package, improving mechanical reliability. Furthermore, eliminating the need for a molding process contributes to cost reduction. Furthermore, housing the semiconductor chip in a cavity contributes to a low-profile package.

[0010] FIG. 1 is a bottom view showing the mounting surface of a high frequency semiconductor package according to a first embodiment. FIG. 2 is a cross-sectional view taken along the line I-II of FIG. 1. FIG. 3 is a bottom view showing a second substrate of a high frequency semiconductor package according to a first embodiment. FIG. 4 is a top view showing a first substrate of a high frequency semiconductor package according to a first embodiment. FIG. 5 is a cross-sectional view showing an enlarged view of a main part of a high frequency semiconductor package according to a second embodiment. FIG. 6 is a cross-sectional view showing a high frequency semiconductor package according to a third embodiment. FIG. 7 is a plan view showing an inner layer of a second substrate according to a third embodiment. FIG. 8 is a cross-sectional view showing an enlarged view of a main part of a high frequency semiconductor package according to a fourth embodiment. FIG. 9 is a cross-sectional view showing an enlarged view of a main part of the mounting surface of a second substrate of a high frequency semiconductor package according to a fourth embodiment.

[0011] A high frequency semiconductor package according to an embodiment will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and repeated description may be omitted.

[0012] Embodiment 1. Fig. 1 is a bottom view showing the mounting surface of a high-frequency semiconductor package according to embodiment 1. Fig. 2 is a cross-sectional view taken along line I-II in Fig. 1. The high-frequency semiconductor package includes a first substrate 10, a second substrate 20, a semiconductor chip 103, and a sealing resin 101.

[0013] In the first substrate 10, a ground pattern 11a and a signal pattern 14a are provided on the upper surface of the first base material 13. A ground terminal 11b and a signal terminal 14b are provided on the lower surface of the first base material 13. The signal pattern 14a and the signal terminal 14b are electrically connected by a signal via hole 12a that penetrates the first base material 13. The ground pattern 11a and the ground terminal 11b are electrically connected by a ground via hole 12b that penetrates the first base material 13. An opening is provided in the center of the first base material 13 in a plan view. A heat sink 15 is press-fitted into the opening of the first base material 13. The upper surface of the heat sink 15 is exposed on the upper surface of the first base material 13. The lower surface of the heat sink 15 is exposed on the lower surface of the first base material 13.

[0014] In the second substrate 20, a ground pattern 21a and a signal pattern 24 are provided on the lower surface of the second base material 23. A ground pattern 21b covers the entire upper surface of the second base material 23. The ground patterns 21a and 21b are electrically connected by a ground via hole 22 that penetrates the second base material 23. A ground metal pillar 25 is formed on the ground pattern 21a, and signal metal pillars 26a and 26b are formed on the signal pattern 24. Solder 102 is plated on the tips of the ground metal pillar 25 and the signal metal pillars 26a and 26b.

[0015] The second substrate 20 is flip-chip mounted on the first substrate 10. This flip-chip mounting connects the signal metal pillar 26a to the signal pad 103a formed on the top surface of the semiconductor chip 103 with solder 102. Furthermore, the signal metal pillar 26b is connected to the signal pattern 14a of the first substrate 10 with solder 102. As a result, the signal pad 103a is electrically connected to the signal terminal 14b via the signal metal pillar 26a, the signal pattern 24 of the second substrate 20, the signal metal pillar 26b, the signal pattern 14a of the first substrate 10, and the signal via hole 12a. As a result, the semiconductor chip 103 can send and receive signals to and from the outside.

[0016] Furthermore, by flip-chip mounting, the ground metal pillar 25 is electrically connected to the ground pattern 11a by solder 102. This electrically connects the ground pattern 21b, via hole 22, and ground pattern 21a of the second substrate 20 to the ground metal pillar 25, and the ground pattern 11a, ground via hole 12b, and ground terminal 11b of the first substrate 10. As a result, the ground of the first substrate 10 and the ground of the second substrate 20 have a common potential. This common ground of the first substrate 10 and the second substrate 20 covers the periphery of the semiconductor chip 103, the signal metal pillars 26a, 26b, the signal patterns 14a, 24, the signal via hole 12a, and the signal terminal 14b, and forms an electromagnetic shielding structure against external disturbances.

[0017] 3 is a bottom view showing the second substrate of the high-frequency semiconductor package according to embodiment 1. The ground via holes 22 and the ground metal pillars 25 are each arranged in a ring shape on the periphery of the second substrate 20. The signal pattern 24 and the signal metal pillar 26 are arranged inside the ring formed by the ground via holes 22 and the ground metal pillars 25.

[0018] 4 is a top view showing the first substrate of the high-frequency semiconductor package according to embodiment 1. The ground via holes 12b are arranged in a ring shape around the periphery of the first substrate 10. The signal pattern 14a, the signal via holes 12a, and the semiconductor chip 103 are arranged inside the ring formed by the ground via holes 12b.

[0019] As described above, in this embodiment, the ground patterns and ground via holes of the first substrate 10 and the second substrate 20 cover the periphery of the semiconductor chip 103 and the like to form an electromagnetic shield structure. This allows the electromagnetic shield to be formed using a normal resin-sealed package manufacturing method without using special processes such as vapor deposition, sputtering, or plating, thereby reducing the manufacturing cost of a high-frequency semiconductor package with an electromagnetic shield. Furthermore, the ground patterns and ground via holes, excluding the ground terminal 11b mounted on the motherboard, are located inside the sealing resin 101. Therefore, the electromagnetic shield structure is not exposed to the outside of the sealing resin 101, thereby improving mechanical reliability.

[0020] In this embodiment, the heat sink 15 is provided assuming a case where the amount of heat generated by the semiconductor chip 103 is large. However, if the amount of heat generated by the semiconductor chip 103 is not a problem, a general ground via hole and a ground pattern may be provided instead of the heat sink 15.

[0021] Furthermore, by arranging the interval between adjacent ground via holes 22 to be smaller than half the wavelength λ of the desired frequency, better electromagnetic shielding performance can be ensured at the desired frequency. The same applies to the interval between adjacent ground via holes 12b and the interval between adjacent ground metal pillars 25. Note that the wavelength λ inside a dielectric with a relative dielectric constant εr is proportional to the reciprocal of √(εr) with respect to the wavelength λ in free space.

[0022] 5 is an enlarged cross-sectional view of a main part of a high-frequency semiconductor package according to embodiment 2. In place of the signal metal pillars 26a and 26b, the ground metal pillar 25, and the solder 102 of embodiment 1, signal solder balls 102a and 102b and ground solder balls 102c are used.

[0023] By flip-chip mounting, signal solder balls 102a connect signal pads 103a of semiconductor chip 103 to signal pattern 24 on second substrate 20. Signal solder balls 102b connect signal pattern 24 on second substrate 20 to signal pattern 14a on first substrate 10. Ground solder balls 102c connect ground pattern 11a on first substrate 10 to ground pattern 21a on second substrate 20. Other configurations are the same as those in embodiment 1.

[0024] The ground solder balls 102c become part of the electromagnetic shielding structure that surrounds the semiconductor chip 103, etc. This reduces manufacturing costs and improves mechanical reliability, as in the first embodiment. Furthermore, by using the signal solder balls 102a, 102b and the ground solder balls 102c, variations in height of the semiconductor chip 103 and warpage of the substrate due to the thickness of the die bond material can be absorbed. As a result, the mountability of flip-chip mounting is improved.

[0025] 6 is a cross-sectional view showing a high-frequency semiconductor package according to embodiment 3. The second substrate 20 is a multi-layer substrate, and a harmonic processing filter 27, inner-layer signal patterns 28a and 28b, and a ground pattern 21c are provided on the inner layer of the second base material 23. Signal patterns 24a and 24b are provided on the surface of the second substrate 20.

[0026] The signal pattern 24a is electrically connected to a signal pad 103a of the semiconductor chip 103 by a signal metal pillar 26a. The signal pattern 24b is electrically connected to a signal pattern 14a of the first substrate 10 by a signal metal pillar 26b. The signal pattern 24a is electrically connected to an inner layer signal pattern 28a by a signal via hole 22a. The signal pattern 24b is electrically connected to an inner layer signal pattern 28b by a signal via hole 22b. The ground patterns 21a, 21b, and 21c are electrically connected by ground via holes 22.

[0027] 7 is a plan view showing the inner layers of the second substrate according to the third embodiment. Inner-layer signal patterns 28a and 28b are electrically connected to harmonic processing filter 27. Ground via holes 22 are arranged in a ring shape around the periphery of second substrate 20. Harmonic processing filter 27, signal via holes 22a and 22b, and inner-layer signal patterns 24a and 24b are arranged inside the ring formed by ground via holes 22. As a result, the common ground of first substrate 10 and second substrate 20 covers the periphery of harmonic processing filter 27, signal via holes 22a and 22b, and inner-layer signal patterns 24a and 24b, forming an electromagnetic shield structure against external disturbances.

[0028] An output signal from semiconductor chip 103 passes through signal metal pillar 26a, signal pattern 24a, signal via hole 22a, and inner layer signal pattern 28a, and is input to harmonic processing filter 27. An output from harmonic processing filter 27 passes through inner layer signal pattern 28b, signal via hole 22b, signal pattern 24b, signal metal pillar 26b, signal pattern 14a, and via hole 12b, and is output to signal terminal 14b.

[0029] The semiconductor chip 103 is a semiconductor high-frequency amplifier. Generally, semiconductor high-frequency amplifiers generate harmonics, such as second and third harmonics of the operating frequency. To remove these harmonics from the output signal, a harmonic processing filter, such as a low-pass filter or a band-pass filter, is provided on the output side of the semiconductor high-frequency amplifier. Harmonic processing filters are formed using a line pattern. However, at high operating frequencies, the line pattern acts as an antenna, potentially receiving electromagnetic interference or, conversely, radiating signals and causing electromagnetic interference to adjacent elements. Therefore, electromagnetic shielding against external disturbances is necessary. For example, in a semiconductor high-frequency amplifier having a high-frequency semiconductor package mounted on a motherboard with a multilayer substrate, a harmonic processing filter is embedded in an inner layer of the motherboard, and the periphery is surrounded by the motherboard's ground pattern or ground via holes to provide electromagnetic shielding. To achieve electromagnetic shielding, the periphery must be surrounded by a ground pattern or ground via holes, which occupies multiple layers of the board mounting area and affects design flexibility.

[0030] In contrast, the high-frequency semiconductor package according to this embodiment has harmonic processing filter 27 with electromagnetic shielding properties provided on second base material 23. This eliminates the need to incorporate a harmonic processing filter in the inner layer of the motherboard, making it possible to reduce the size of the motherboard and improve the design flexibility of the motherboard.

[0031] Fourth Embodiment Fig. 8 is an enlarged cross-sectional view of a main part of a high-frequency semiconductor package according to a fourth embodiment. Fig. 9 is an enlarged plan view of a main part of the mounting surface of a second substrate of the high-frequency semiconductor package according to the fourth embodiment. A passive component 28 is mounted on the surface of the second substrate 20 and is electrically connected between the signal pattern 24 and the ground pattern 21.

[0032] The passive component 28 is, for example, a capacitor, and serves as a bypass capacitor for the semiconductor chip 103. Note that the passive component 28 is not limited to a capacitor, and may be a passive element such as a resistor or a coil. Furthermore, the connection of the passive component 28 is not necessarily limited to the connection between the signal pattern 24 and the ground pattern 21.

[0033] The first substrate 10 is provided with a large-area semiconductor chip 103, signal via holes, and ground via holes, and there is no room to mount the passive components 28. Therefore, it is difficult to mount the passive components 28 on the first substrate 10 while maintaining the original substrate size.

[0034] In contrast, the second substrate 20 has a high degree of freedom in substrate design, and the passive components 28 can be easily arranged while maintaining the same substrate size. Therefore, in this embodiment, there is no need to mount a bypass capacitor on the first substrate 10, which contributes to a smaller package size. Furthermore, the passive components 28 are surrounded by the common ground of the first substrate 10 and the second substrate 20, and therefore have electromagnetic shielding properties against external disturbances.

[0035] Fifth Embodiment. Figure 10 is a cross-sectional view showing a high-frequency semiconductor package according to a fifth embodiment. A cavity 29 is provided on the upper surface of the first substrate 13. The upper surface of a ground terminal 11b, which is provided in the center of the lower surface of the first substrate 13, is exposed in the cavity 29. A semiconductor chip 103 is mounted on the upper surface of the ground terminal 11b inside the cavity 29. A signal metal pillar 26a is formed on a signal pad 103a of the semiconductor chip 103. By flip-chip mounting, the signal metal pillar 26a is connected to the signal pattern 24 of the second substrate 20 by solder 102. The signal pattern 24 of the second substrate 20 is connected to the signal pattern 14a of the first substrate 10 by solder 102. In addition, the ground pattern 21a of the second substrate 20 is electrically connected to the ground pattern 11a of the first substrate 10 by solder 102. As a result, the ground potential of the first substrate 10 and the ground potential of the second substrate 20 are the same. The common ground of the first substrate 10 and the second substrate 20 covers the semiconductor chip 103, the signal metal pillars 26a, the signal patterns 14a and 24, the signal via holes 12a, and the signal terminals 14b, forming an electromagnetic shield structure against external disturbances. In this embodiment, molding and sealing with the sealing resin 101 is not performed. The other configurations are the same as those of the first embodiment. Note that the configurations of the second to fourth embodiments may be combined with this embodiment.

[0036] In this embodiment, the ground patterns and ground via holes of the first substrate 10 and the second substrate 20 surround the semiconductor chip 103 and other components to form an electromagnetic shielding structure. This allows the electromagnetic shielding to be formed using a standard package manufacturing method without using special processes such as vapor deposition, sputtering, or plating, thereby reducing the manufacturing cost of a high-frequency semiconductor package with an electromagnetic shield. Furthermore, the ground patterns and ground via holes, excluding the ground terminal 11b mounted on the motherboard, are located inside the package. Therefore, the electromagnetic shielding structure is not exposed to the outside of the package, improving mechanical reliability. Furthermore, eliminating the need for a molding process contributes to cost reduction. Furthermore, housing the semiconductor chip 103 in the cavity 29 contributes to a low-profile package.

[0037] REFERENCE SIGNS LIST 10 First substrate, 11a Ground pattern (first ground pattern), 11b Ground terminal, 12a Signal via hole (first signal via hole), 12b Ground via hole (first ground via hole), 13 First base material, 14a Signal pattern (first signal pattern), 14b Signal terminal, 15 Heat sink, 20 Second substrate, 21a Ground pattern (second ground pattern), 21b Ground pattern (third ground pattern), 22 Ground via hole (second ground via hole), 22a Signal via hole (second signal via hole), 22b Signal via hole (third signal via hole), 23 Second base material, 24 Signal pattern (second signal pattern), 24a Signal pattern (third signal pattern), 24b Signal pattern (fourth signal pattern), 25 Ground metal pillar (third connecting member), 26a Signal metal pillar (first connection member), 26b signal metal pillar (second connection member), 27 harmonic processing filter, 28 passive components, 29 cavity, 101 sealing resin, 102a signal solder ball (first connection member), 102b signal solder ball (second connection member), 102c ground solder ball (third connection member), 103 semiconductor chip, 103a signal pad

Claims

1. a first substrate having a first base material, a signal terminal and a ground terminal provided on a lower surface of the first base material, a first signal pattern and a first ground pattern provided on an upper surface of the first base material, a first signal via hole penetrating the first base material and electrically connecting the signal terminal and the first signal pattern, and a first ground via hole penetrating the first base material and electrically connecting the ground terminal and the first ground pattern; a semiconductor chip mounted on an upper surface of the first substrate; a second substrate having a second base material, a second signal pattern and a second ground pattern provided on a lower surface of the second base material, a third ground pattern provided on an entire upper surface of the second base material, and a second ground via hole penetrating the second base material and electrically connecting the second ground pattern and the third ground pattern; a first connection member that connects a signal pad of the semiconductor chip and the second signal pattern; a second connection member that connects the second signal pattern and the first signal pattern; a third connection member that connects the first ground pattern and the second ground pattern; a sealing resin that seals the second substrate, the semiconductor chip, and the first to third connection members; a first signal via hole, a second signal via hole, a first connection member, and a second connection member, which are electrically connected to the first and second ground patterns, and which are electrically connected to the first and second ground patterns, the first and second ground via holes, the first and second connection members, and which form an electromagnetic shielding structure that covers the periphery of the signal terminal, the first and second signal patterns, the first signal via hole, the semiconductor chip, and the first and second connection members.

2. 2. The high frequency semiconductor package according to claim 1, wherein the first to third connection members each have a metal pillar.

3. 2. The high frequency semiconductor package according to claim 1, wherein the first to third connection members are solder balls.

4. the second signal pattern includes a third signal pattern electrically connected to the signal pad of the semiconductor chip by the first connection member, and a fourth signal pattern electrically connected to the first signal pattern by the second connection member; 4. The high frequency semiconductor package according to claim 1, wherein the second substrate has a harmonic processing filter provided in an inner layer of the second base material, a second signal via hole electrically connecting the third signal pattern and the harmonic processing filter, and a third signal via hole electrically connecting the fourth signal pattern and the harmonic processing filter.

5. The high frequency semiconductor package according to any one of claims 1 to 3, further comprising a passive component mounted on the underside of the second substrate and electrically connected between the second signal pattern and the second ground pattern.

6. An opening is provided in a central portion of the first base material, A heat sink is press-fit into the opening; 4. The high frequency semiconductor package according to claim 1, wherein the semiconductor chip is mounted on the heat sink.

7. a first substrate having a first base material, a signal terminal and a ground terminal provided on a lower surface of the first base material, a first signal pattern and a first ground pattern provided on an upper surface of the first base material, a first signal via hole penetrating the first base material and electrically connecting the signal terminal and the first signal pattern, and a first ground via hole penetrating the first base material and electrically connecting the ground terminal and the first ground pattern; a semiconductor chip mounted on an upper surface of the first substrate; a second substrate having a second base material, a second signal pattern and a second ground pattern provided on a lower surface of the second base material, a third ground pattern provided on an entire upper surface of the second base material, and a second ground via hole penetrating the second base material and electrically connecting the second ground pattern and the third ground pattern; a first connection member that connects a signal pad of the semiconductor chip and the second signal pattern; a second connection member that connects the second signal pattern and the first signal pattern; a third connection member that connects the first ground pattern and the second ground pattern, the ground terminal, the first to third ground patterns, the first and second ground via holes, and the third connection member form an electromagnetic shield structure that covers the periphery of the signal terminal, the first and second signal patterns, the first signal via hole, the semiconductor chip, and the first and second connection members; A cavity is provided on an upper surface side of the first base material, an upper surface of the ground terminal is exposed in the cavity; a semiconductor chip mounted on an upper surface of the ground terminal inside the cavity;