Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device comprises a semiconductor element, a support conductor that supports the semiconductor element, a support substrate that supports the support conductor, and a first intermediate bonding material that is interposed between the support conductor and the support substrate. The bond between the support conductor and the intermediate bonding material and the bond between the support substrate and the intermediate bonding material are both solid-phase bonds. One of the bonding interface between the support conductor and the intermediate bonding material and the bonding interface between the support substrate and the intermediate bonding material includes a bonding anomaly region in which the bonding condition is different from that of the surrounding area.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Conventionally, semiconductor devices including power switching elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors) have been known. Such semiconductor devices are mounted in a variety of electronic devices, from industrial equipment to home appliances, information terminals, and automotive equipment. Patent Document 1 discloses a conventional semiconductor device (power module). The power module described in Patent Document 1 includes multiple transistors, a main substrate, a signal substrate, and signal terminals. The multiple transistors are mounted on the main substrate.

[0003] JP 2015-126342 A

[0004] In a power module such as that described in Patent Document 1, solid-state welding is sometimes used to join multiple components. In solid-state welding, an intermediate bonding material is generally interposed between two objects. If the intermediate bonding material is misaligned, it becomes difficult to achieve proper joining.

[0005] An object of the present disclosure is to provide an improved semiconductor device and a method for manufacturing such a semiconductor device. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that can suppress misalignment of an intermediate bonding material and a method for manufacturing such a semiconductor device.

[0006] A semiconductor device provided by a first aspect of the present disclosure includes a semiconductor element, a support conductor supporting the semiconductor element, a support substrate supporting the support conductor, and a first intermediate bonding material interposed between the support conductor and the support substrate. The bonding between the support conductor and the first intermediate bonding material and the bonding between the support substrate and the first intermediate bonding material are both solid-state bonding. Either the bonding interface between the support conductor and the first intermediate bonding material or the bonding interface between the support substrate and the first intermediate bonding material includes a bonding unique region that has a bonding state different from that of surrounding areas.

[0007] A method for manufacturing a semiconductor device provided by a second aspect of the present disclosure includes a step of temporarily bonding a first intermediate bonding material to either a support conductor or a support substrate by applying pressure, and a step of applying pressure while the first intermediate bonding material is sandwiched between the support conductor and the support substrate, thereby solid-state bonding the first intermediate bonding material to the support conductor and solid-state bonding the first intermediate bonding material to the support substrate.

[0008] According to the semiconductor device of the present disclosure, it is possible to suppress misalignment of the intermediate bonding material.

[0009] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a partial perspective view showing a semiconductor device according to the first embodiment of the present disclosure. FIG. 3 is a partial perspective view showing a semiconductor device according to the first embodiment of the present disclosure. FIG. 4 is a plan view showing a semiconductor device according to the first embodiment of the present disclosure. FIG. 5 is a partial plan view showing a semiconductor device according to the first embodiment of the present disclosure. FIG. 6 is a partial right side view showing a semiconductor device according to the first embodiment of the present disclosure. FIG. 7 is a partial left side view showing a semiconductor device according to the first embodiment of the present disclosure. FIG. 8 is a partial plan view showing a semiconductor device according to the first embodiment of the present disclosure. FIG. 9 is a right side view showing a semiconductor device according to the first embodiment of the present disclosure. FIG. 10 is a bottom view showing a semiconductor device according to the first embodiment of the present disclosure. FIG. 11 is a cross-sectional view taken along line XI-XI of FIG. 5. FIG. 12 is a cross-sectional view taken along line XII-XII of FIG. 5. FIG. 13 is a partial enlarged cross-sectional view showing a portion of FIG. 12. FIG. 14 is a partial enlarged cross-sectional view showing an example of a mounting structure according to the first embodiment of the present disclosure. FIG. 15 is a partially enlarged cross-sectional view showing another example of the mounting structure according to the first embodiment of the present disclosure. FIG. 16 is a partially enlarged cross-sectional view enlarging a portion of FIG. 12 . FIG. 17 is a partially enlarged cross-sectional view showing another example of the mounting structure according to the first embodiment of the present disclosure. FIG. 18 is a partially enlarged cross-sectional view showing another example of the mounting structure according to the first embodiment of the present disclosure. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 5 . FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 5 . FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 5 . FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 5 . FIG. 23 is a plan view showing an example of a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 23 . FIG. 25 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 26 is a partially enlarged cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. 27 and 28 are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure.Fig. 29 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. Fig. 30 is a partial plan view showing a first modified example of the semiconductor device according to the first embodiment of the present disclosure. Fig. 31 is a partially enlarged cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure. Fig. 32 is a partially enlarged cross-sectional view showing a semiconductor device according to the second embodiment of the present disclosure. Fig. 33 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment of the present disclosure. Fig. 34 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment of the present disclosure. Fig. 35 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment of the present disclosure.

[0010] Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the drawings. Hereinafter, identical or similar components will be designated by the same reference numerals, and redundant explanations will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely for identification purposes and are not intended to necessarily assign any rank to the objects.

[0011] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an) object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an) object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on (an) object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an) object B" includes "a certain object A is in contact with a certain object B and is located on (an) object B" and "a certain object A is located on (an) object B with another object interposed between the certain object A and the certain object B." Unless otherwise specified, the phrase "when viewed from a certain direction, an object A overlaps an object B" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B."

[0012] In the present disclosure, an example of a certain configuration of an embodiment may be shown in parentheses after the configuration. The parenthesized configuration includes the parenthesized configuration, which is an example. The parenthesized configuration is an example of the parenthesized configuration, and therefore is not limited to the parenthesized configuration.

[0013] In the present disclosure, for names indicated by abbreviations, chemical symbols, etc., parentheses may be placed after the relevant structure, and an alternative name may be indicated within the parentheses. In this case, the name within the parentheses indicates the same thing as the parenthesized name.

[0014] In the present disclosure, the expression "a certain component is composed mainly of a certain metal" includes a configuration in which the certain component is composed only of the certain metal, a configuration in which an additive metal or the like is added to the certain metal, various alloys of the certain metal, etc.

[0015] 1 to 29 show a semiconductor device A1 according to one embodiment of the present disclosure. The semiconductor device A1 may include a plurality of semiconductor elements 1, a support conductor 2, a support substrate 3, a plurality of power terminals 41 to 43, a plurality of control terminals 44, a signal substrate 5, an adhesive layer 6, a first conductive member 71, a second conductive member 72, a plurality of wires 73 to 76, a resin member 8, and a resin filling portion 88.

[0016] The support conductor 2 may include a first conductive portion 2A and a second conductive portion 2B. The plurality of control terminals 44 may include a plurality of first control terminals 45 and a plurality of second control terminals 46. The signal substrate 5 may include a first signal substrate 5A and a second signal substrate 5B. The adhesive layer 6 may include a first adhesive body 6A and a second adhesive body 6B.

[0017] For ease of explanation, the three mutually orthogonal directions are referred to as the x-direction, y-direction, and z-direction. As an example, the z-direction is the thickness direction of the semiconductor device A1. The x-direction and y-direction are directions orthogonal to the z-direction. In the following explanation, "plan view" refers to a view in the z-direction. Note that terms such as "top," "bottom," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each component, etc. in the z-direction, and do not necessarily define the relationship with the direction of gravity.

[0018] Multiple semiconductor elements 1: Each of the multiple semiconductor elements 1 is an electronic component that is central to the function of the semiconductor device A1. The constituent material of each of the multiple semiconductor elements 1 may be a semiconductor material primarily composed of, for example, SiC (silicon carbide). This semiconductor material is not limited to SiC and may be Si (silicon), GaN (gallium nitride), or C (diamond). Each semiconductor element 1 may be, for example, a power semiconductor chip with switching function, such as a metal oxide semiconductor field effect transistor (MOSFET). In this embodiment, each semiconductor element 1 is a MOSFET, but is not limited thereto and may be other transistors such as an insulated gate bipolar transistor (IGBT). Each semiconductor element 1 may be the same type of element. Each semiconductor element 1 is, for example, an n-channel MOSFET, but may also be a p-channel MOSFET. Each semiconductor element 1 may be the same type of element but with different polarities.

[0019] The multiple semiconductor elements 1 may include multiple first switching elements 1A and multiple second switching elements 1B. As shown in FIG. 8 , the semiconductor device A1 may include four first switching elements 1A and four second switching elements 1B, but the number of first switching elements 1A and the number of second switching elements 1B are not limited to this configuration. The number of first switching elements 1A and the number of second switching elements 1B may be changed as appropriate depending on the performance required of the semiconductor device A1. The number of first switching elements 1A and the number of second switching elements 1B may be equal to or different from each other. The number of first switching elements 1A and the number of second switching elements 1B may be determined by the current capacity handled by the semiconductor device A1.

[0020] In the present disclosure, a configuration related to a plurality of first switching elements 1A may be indicated by adding an A to the end of the reference number of a configuration related to a corresponding plurality of semiconductor elements 1. In the present disclosure, a configuration related to a plurality of first switching elements 1A may be indicated within parentheses after a configuration related to a corresponding plurality of semiconductor elements 1. In this case, the configuration within the parentheses may be an example of the configuration before the parentheses. In the present disclosure, a configuration related to a plurality of second switching elements 1B may be indicated by adding a B to the end of the reference number of a configuration related to a corresponding plurality of semiconductor elements 1. In the present disclosure, a configuration related to a plurality of second switching elements 1B may be indicated within parentheses after a configuration related to a corresponding plurality of semiconductor elements 1. In this case, the configuration within the parentheses may be an example of the configuration before the parentheses.

[0021] The semiconductor device A1 may be configured, for example, as a half-bridge switching circuit. In this case, a plurality of first switching elements 1A may form an upper arm circuit of the semiconductor device A1, and a plurality of second switching elements 1B may form a lower arm circuit of the semiconductor device A1. The plurality of first switching elements 1A may be connected in parallel to each other in the upper arm circuit, and the plurality of second switching elements 1B may be connected in parallel to each other in the lower arm circuit. Each first switching element 1A may be connected in series to one of the plurality of second switching elements 1B. Each second switching element 1B may be connected in series to one of the plurality of first switching elements 1A.

[0022] Each of the multiple semiconductor elements 1 (the multiple first switching elements 1A and the multiple second switching elements 1B) may have an element main surface 10a and an element back surface 10b, as shown in Figures 13 and 16. In each semiconductor element 1, the element main surface 10a and the element back surface 10b may be spaced apart in the z direction. The element main surface 10a faces the z2 side, and the element back surface 10b faces the z1 side.

[0023] Each of the multiple first switching elements 1A may be mounted on a support conductor 2 (first conductive portion 2A), as shown in, for example, FIGS. 8 , 12 , 13 , and 21 . In the example shown in FIG. 8 , the multiple first switching elements 1A may be arranged, for example, in the y direction and spaced apart from one another. Each of the multiple first switching elements 1A may be conductively joined to the support conductor 2 (first conductive portion 2A) via a second intermediate bonding material 19a. When each first switching element 1A is joined to the first conductive portion 2A, the element back surface 10b may face the support conductor 2 (first conductive portion 2A).

[0024] As shown in FIGS. 8 , 12 , 16 , and 20 , the multiple second switching elements 1B may be mounted on a support conductor 2 (second conductive portion 2B). In the example shown in FIG. 8 , the multiple second switching elements 1B may be arranged, for example, in the y direction and spaced apart from one another. Each of the multiple second switching elements 1B may be conductively bonded to the support conductor 2 (second conductive portion 2B) via a second intermediate bonding material 19b. When each second switching element 1B is bonded to the second conductive portion 2B, the element back surface 10b may face the support conductor 2 (second conductive portion 2B). As can be seen from FIG. 8 , the multiple first switching elements 1A and the multiple second switching elements 1B overlap when viewed in the x direction. However, the multiple first switching elements 1A and the multiple second switching elements 1B do not have to overlap when viewed in the x direction.

[0025] As shown in FIGS. 8 , 13 , and 16 , each of the semiconductor elements 1 (the first switching elements 1A and the second switching elements 1B) may have a first principal surface electrode 11, a second principal surface electrode 12, a third principal surface electrode 13, and a back surface electrode 15. The configurations of the first principal surface electrode 11, the second principal surface electrode 12, the third principal surface electrode 13, and the back surface electrode 15 described below may be common to all of the semiconductor elements 1. The first principal surface electrode 11, the second principal surface electrode 12, and the third principal surface electrode 13 may be located above the element's main surface 10a. The first principal surface electrode 11, the second principal surface electrode 12, and the third principal surface electrode 13 are insulated by an insulating film (not shown). The back surface electrode 15 may be located above the element's back surface 10b. The back surface electrode 15 covers the entire area (or substantially the entire area) of the element's back surface 10b. The back surface electrode 15 may be formed, for example, by Ag (silver) plating.

[0026] In an example in which each semiconductor element 1 is configured as a MOSFET, the first principal surface electrode 11 may be, for example, a gate electrode and configured to receive a drive signal (e.g., a gate voltage) for driving each semiconductor element 1. The second principal surface electrode 12 may be, for example, a source electrode and configured to allow a source current to flow therethrough. The third principal surface electrode 13 may be, for example, a source sense electrode and may have the same potential as the second principal surface electrode 12. The third principal surface electrode 13 may be configured to allow the same source current as the second principal surface electrode 12 to flow therethrough. The back surface electrode 15 may be, for example, a drain electrode and configured to allow a drain current to flow therethrough.

[0027] Each semiconductor element 1 may be configured to switch between a conductive state and a cutoff state in response to a drive signal (gate voltage) input to the first principal surface electrode 11 (gate electrode). This switching between the conductive state and the cutoff state is called a switching operation. When the semiconductor element 1 is in the conductive state, a forward current may flow from the back surface electrode 15 (drain electrode) to the second principal surface electrode 12 (source electrode). When the semiconductor element 1 is in the cutoff state, this forward current does not flow. The semiconductor device A1 may be configured to convert a first power supply voltage (e.g., a DC voltage) into a second power supply voltage (e.g., an AC voltage) using the function of each semiconductor element 1. The first power supply voltage may be input or applied between the power terminal 41 and two power terminals 42. The second power supply voltage may be input or applied to two power terminals 43.

[0028] 5 and 8, the semiconductor device A1 includes two thermistors 17. Each thermistor 17 can be used as a sensor for detecting temperature.

[0029] Support conductor 2: The support conductor 2 can support multiple semiconductor elements 1 (multiple first switching elements 1A and multiple second switching elements 1B). The support conductor 2 is bonded onto a support substrate 3. The support conductor 2 can have, for example, a rectangular shape in a plan view. The support conductor 2, together with the first conductive member 71 and the second conductive member 72, can form a path for a main circuit current that is switched by the multiple first switching elements 1A and multiple second switching elements 1B.

[0030] The support conductor 2 may include a first conductive portion 2A and a second conductive portion 2B. As shown in FIGS. 14 and 15 , the first conductive portion 2A may include a main body layer 20A, a third bonding layer 21A, and a first bonding layer 22A. As shown in FIGS. 17 and 18 , the second conductive portion 2B may include a main body layer 20B, a third bonding layer 21B, and a first bonding layer 22B. The main body layer 20A and the main body layer 20B may each be a metal plate-shaped member. This metal may be primarily composed of Cu (copper). Examples of a structure primarily composed of Cu include a structure consisting of Cu alone, a structure in which an additive metal or the like is added to Cu, and various Cu alloys. Specific structures of the third bonding layer 21A, the first bonding layer 22A, the third bonding layer 21B, and the first bonding layer 22B will be described later. The first conductive portion 2A and the second conductive portion 2B, together with the plurality of power terminals 41-43, can form conduction paths to the plurality of first switching elements 1A and the plurality of second switching elements 1B. The first conductive portion 2A and the second conductive portion 2B can each be rectangular in plan view, for example. The first conductive portion 2A and the second conductive portion 2B can each have an x-direction dimension of 15 mm to 25 mm, a y-direction dimension of 30 mm to 40 mm, and a z-direction dimension of 1.0 mm to 5.0 mm. The z-direction dimension of the first conductive portion 2A and the second conductive portion 2B is preferably approximately 2.0 mm. The dimensions of the first conductive portion 2A and the second conductive portion 2B are not limited to the above-described numerical example and can be changed as appropriate depending on the specifications of the semiconductor device A1. The dimensions of the first conductive portion 2A and the second conductive portion 2B are not limited to being the same and can be different from each other.

[0031] As shown in FIGS. 11 to 22 , the first conductive portion 2A is bonded to the support substrate 3 via a first intermediate bonding material 29a, and the second conductive portion 2B is bonded to the support substrate 3 via a first intermediate bonding material 29b. A plurality of first switching elements 1A are bonded to the first conductive portion 2A via a second intermediate bonding material 19a. A plurality of second switching elements 1B are bonded to the second conductive portion 2B via a second intermediate bonding material 19b. The first conductive portion 2A and the second conductive portion 2B can be spaced apart in the x-direction as shown in FIGS. 3 , 8 , 11 , 12 , and 19 . In the examples shown in these figures, the first conductive portion 2A can be located closer to the x1 side than the second conductive portion 2B. The first conductive portion 2A and the second conductive portion 2B can overlap when viewed in the x-direction. In addition, the joining of the first switching element 1A to the first conductive portion 2A and the joining of the second switching element 1B to the second conductive portion 2B are not limited to joining via the second intermediate joining material 19a, but may be joining by solder, for example.

[0032] The supporting conductor 2 (each of the first conductive portion 2A and the second conductive portion 2B) may have a main surface 201 and a back surface 202. The main surface 201 and the back surface 202 may be spaced apart in the z direction, as shown in FIGS. 11 to 22 . The main surface 201 faces the z2 side, and the back surface 202 faces the z1 side. The back surface 202 may face the supporting substrate 3.

[0033] 14 , the semiconductor device A1 may have a bonded portion formed by solid-state bonding. This bonded portion is formed by bonding a first switching element 1A and a first conductive portion 2A via a second intermediate bonding material 19a. Solid-state bonding is a bonding technique achieved by applying a predetermined pressure and temperature to two layers made primarily of the same metal in direct contact with each other, and includes, for example, solid-state diffusion bonding, solid-state deformation bonding, etc.

[0034] The second intermediate bonding material 19a can have a base layer 190a, a third surface layer 191a, and a fourth surface layer 192a.

[0035] The base layer 190a may be primarily composed of aluminum (Al). Examples of a configuration primarily composed of Al include a configuration consisting of only Al, a configuration in which an additive metal or the like is added to Al, and various Al alloys. The thickness of the base layer 190a is not limited in any way, and in this embodiment, the base layer 190a may be thicker than the third surface layer 191a and the fourth surface layer 192a. The thickness of the base layer 190a may be, for example, 50 μm or more and 300 μm or less.

[0036] The third surface layer 191a may be located on the z2 side of the base layer 190a in the z direction. The third surface layer 191a may be solid-state bonded to the first switching element 1A. In this embodiment, the third surface layer 191a may be mainly composed of Ag (silver). There are no limitations on the thickness of the third surface layer 191a, and in this embodiment, the third surface layer 191a may be thinner than the base layer 190a. The thickness of the third surface layer 191a may be, for example, not less than 0.1 μm and not more than 15 μm.

[0037] In the present embodiment, the first switching element 1A may further include a fourth bonding layer 151. The fourth bonding layer 151 may be located on the z1 side of the back surface electrode 15 in the z direction. The fourth bonding layer 151 may be solid-state bonded to the third surface layer 191a. In the present embodiment, the fourth bonding layer 151 may contain Ag (silver) as a main component. There are no particular limitations on the thickness of the fourth bonding layer 151, and the thickness may be, for example, 0.01 μm or more and 5 μm or less.

[0038] The metal that is the main component of the third surface layer 191a and the fourth bonding layer 151 is not particularly limited as long as they are configured to be solid-state bonded to each other.

[0039] The boundary between the third surface layer 191 a and the fourth bonding layer 151, which are solid-state bonded to each other, may be unclear compared to the boundary between the base material layer 190 a and the third surface layer 191 a, which is the boundary between dissimilar metals. Generally, the boundary between the third surface layer 191 a and the fourth bonding layer 151 is barely discernible or is only discernible due to the presence of a small gap or the like that occurs during solid-state bonding. These points are similar to those of other solid-state bonded portions in this disclosure.

[0040] The fourth surface layer 192a may be located on the z1 side of the base layer 190a in the z direction. The fourth surface layer 192a may be solid-state bonded to the first conductive portion 2A. In this embodiment, the fourth surface layer 192a may be primarily composed of Ag (silver). There are no limitations on the thickness of the fourth surface layer 192a, and in this embodiment, the fourth surface layer 192a may be thinner than the base layer 190a. The thickness of the fourth surface layer 192a may be, for example, not less than 0.1 μm and not more than 15 μm.

[0041] The third bonding layer 21A of the first conductive portion 2A may be located on the z2 side of the main body layer 20A in the z direction. The third bonding layer 21A may be solid-state bonded to the fourth surface layer 192a. In this embodiment, the third bonding layer 21A may be primarily composed of Ag (silver). The thickness of the third bonding layer 21A is not particularly limited and may be, for example, 0.1 μm or more and 15 μm or less.

[0042] The metal that is the main component of the fourth surface layer 192a and the third bonding layer 21A is not particularly limited as long as they are configured to be solid-state bonded to each other.

[0043] 17, the semiconductor device A1 may have a bonded portion formed by solid-state bonding. This bonded portion may be a structure in which the second switching element 1B and the second conductive portion 2B are bonded via a second intermediate bonding material 19b.

[0044] The second intermediate bonding material 19b can have a base layer 190b, a third surface layer 191b, and a fourth surface layer 192b.

[0045] The base layer 190b may be primarily composed of Cu (copper). There are no limitations on the thickness of the base layer 190b. In this embodiment, the base layer 190b may be thicker than the third surface layer 191b and the fourth surface layer 192b. The thickness of the base layer 190b may be, for example, not less than 50 μm and not more than 300 μm.

[0046] The third surface layer 191b may be located on the z2 side of the base layer 190b in the z direction. The third surface layer 191b is solid-state bonded to the second switching element 1B. In this embodiment, the third surface layer 191b may contain Ag (silver) as a main component. There are no limitations on the thickness of the third surface layer 191b. In this embodiment, the third surface layer 191b may be thinner than the base layer 190b. The thickness of the third surface layer 191b may be, for example, not less than 0.1 μm and not more than 15 μm.

[0047] In the present embodiment, the second switching element 1B may further include a fourth bonding layer 151 similar to that of the first switching element 1A. The fourth bonding layer 151 of the second switching element 1B may be solid-state bonded to the third surface layer 191b.

[0048] The metal that is the main component of the third surface layer 191b and the fourth bonding layer 151 is not particularly limited as long as they are configured to be solid-state bonded to each other.

[0049] The fourth surface layer 192b may be located on the z1 side of the base layer 190b in the z direction. The fourth surface layer 192b is solid-state bonded to the second conductive portion 2B. In this embodiment, the fourth surface layer 192b may contain Ag (silver) as a main component. There are no limitations on the thickness of the fourth surface layer 192b, and in this embodiment, the fourth surface layer 192b is thinner than the base layer 190b. The thickness of the fourth surface layer 192b may be, for example, not less than 0.1 μm and not more than 15 μm.

[0050] The third bonding layer 21B of the second conductive portion 2B may be located on the z2 side of the main body layer 20B in the z direction. The third bonding layer 21B may be solid-state bonded to the fourth surface layer 192b. In this embodiment, the third bonding layer 21B may be primarily composed of Ag (silver). The thickness of the third bonding layer 21B is not particularly limited and may be, for example, 0.1 μm or more and 15 μm or less.

[0051] The metal that is the main component of the fourth surface layer 192b and the third bonding layer 21B is not particularly limited as long as they are configured to be solid-state bonded to each other.

[0052] Support substrate 3: The support substrate 3 supports the support conductor 2. The support substrate 3 may be formed of, for example, a DBC (Direct Bonded Copper) substrate. Alternatively, the support substrate 3 may be formed of, for example, a DBA (Direct Bonded Aluminum) substrate. The support substrate 3 may include an insulating layer 31, a first metal layer 32, and a second metal layer 33.

[0053] The insulating layer 31 may be made of, for example, a ceramic having excellent thermal conductivity. Examples of such ceramic include AlN (aluminum nitride), SiN (silicon nitride), AlO (aluminum oxide), and ZTA (zirconia-reinforced alumina). The insulating layer 31 may be made of an insulating resin instead of ceramic. The insulating layer 31 may have, for example, a rectangular shape in a plan view.

[0054] The first metal layer 32 may be located on the upper surface (surface facing the z2 side) of the insulating layer 31. The first metal layer 32 may be mainly composed of, for example, Cu (copper). The first metal layer 32 may contain Al (aluminum). The first metal layer 32 may include a first portion 32A and a second portion 32B. The first portion 32A and the second portion 32B may be spaced apart in the x direction. The first portion 32A may be located on the x1 side of the second portion 32B. The first portion 32A may be bonded to the first conductive portion 2A and may support the first conductive portion 2A. The second portion 32B may be bonded to the second conductive portion 2B and may support the second conductive portion 2B. The first portion 32A and the second portion 32B may each have a rectangular shape in a planar view, for example.

[0055] The second metal layer 33 may be located on the lower surface (surface facing the z1 side) of the insulating layer 31. The constituent material of the second metal layer 33 may be the same as the constituent material of the first metal layer 32. The lower surface (surface facing the z1 side) of the second metal layer 33 may be exposed from the resin member 8, as shown in FIGS. 10 to 22 . Alternatively, the lower surface of the second metal layer 33 may be covered by the resin member 8. In a configuration in which the lower surface of the second metal layer 33 is exposed from the resin member 8, a heat dissipation member (e.g., a heat sink) (not shown) or the like may be attached to the lower surface. The second metal layer 33 may overlap both the first portion 32A and the second portion 32B in a plan view.

[0056] 15, the semiconductor device A1 may have a bonded portion formed by solid-state bonding. This bonded portion may be a structure in which a first conductive portion 2A and a support substrate 3 are bonded via a first intermediate bonding material 29a.

[0057] The first intermediate bonding material 29a can have a base layer 290a, a first surface layer 291a, and a second surface layer 292a.

[0058] The base layer 290a may be primarily composed of Cu (copper). There are no limitations on the thickness of the base layer 290a. In this embodiment, the base layer 290a may be thicker than the first surface layer 291a and the second surface layer 292a. The thickness of the base layer 290a may be, for example, 50 μm or more and 300 μm or less.

[0059] The first surface layer 291a may be located on the z2 side of the base layer 290a in the z direction. The first surface layer 291a may be solid-state bonded to the first conductive portion 2A. In this embodiment, the first surface layer 291a may be mainly composed of Ag (silver). The thickness of the first surface layer 291a is not limited in any way. In this embodiment, the first surface layer 291a may be thinner than the base layer 290a. The thickness of the first surface layer 291a may be, for example, not less than 0.1 μm and not more than 15 μm.

[0060] The first bonding layer 22A of the first conductive portion 2A may be located on the z1 side of the main body layer 20A in the z direction. The first bonding layer 22A may be solid-state bonded to the first surface layer 291a. In this embodiment, the first bonding layer 22A may be primarily composed of Ag (silver). The thickness of the first bonding layer 22A is not particularly limited and may be, for example, 0.1 μm or more and 15 μm or less.

[0061] The metal that is the main component of the first surface layer 291a and the first bonding layer 22A is not particularly limited as long as they are configured to be solid-state bonded to each other.

[0062] The second surface layer 292a may be located on the z1 side of the base layer 290a in the z direction. The second surface layer 292a may be solid-state bonded to the support substrate 3. In this embodiment, the second surface layer 292a may contain Ag (silver) as a main component. There are no limitations on the thickness of the second surface layer 292a, and in this embodiment, the second surface layer 292a is thinner than the base layer 290a. The thickness of the second surface layer 292a may be, for example, not less than 0.1 μm and not more than 15 μm.

[0063] Support substrate 3 of this embodiment may further include second bonding layer 321A. Second bonding layer 321A may be located on the z2 side of first portion 32A in the z direction. Second bonding layer 321A may be solid-state bonded to second surface layer 292a. In this embodiment, second bonding layer 321A may be primarily composed of Ag (silver). There are no particular limitations on the thickness of second bonding layer 321A and it may be, for example, 0.1 μm or more and 15 μm or less.

[0064] The metal that is the main component of the second surface layer 292a and the second bonding layer 321A is not particularly limited as long as they are configured to be solid-state bonded to each other.

[0065] Either the bonding interface between the first conductive portion 2A and the first intermediate bonding material 29a or the bonding interface between the support substrate 3 and the first intermediate bonding material 29a may include a bonding unique region Pca. The bonding unique region Pca is a region where the bonding state differs from that of the surrounding region. The bonding unique region Pca may be formed by performing a temporary bonding process in the manufacturing method of the semiconductor device A1 described below. One example of a bonding unique region Pca is a configuration where the bonding strength is higher than that of the surrounding region, for example, a configuration where the number of minute voids that can inevitably occur due to solid-state bonding is relatively smaller than that of the surrounding region. For example, when performing SAT (ultrasonic testing), the bonding unique region Pca is recognized as a region where the shading of the image differs from that of the surrounding region.

[0066] The number of junction unique regions Pca is not limited in any way and may be one or more. In the example shown in FIG. 8 , the semiconductor device A1 has two junction unique regions Pca. The two junction unique regions Pca may be located in positions that avoid the multiple first switching elements 1A in a plan view. The two junction unique regions Pca may be located on a diagonal line between the first conductive portion 2A and the first portion 32A. The shape of the junction unique region Pca is not limited in any way and may be any of a variety of shapes, such as a triangle, a rectangle, a polygon, or the like, in addition to the circular shape shown in FIG. 8 .

[0067] In this embodiment, the bonding interface between the first bonding layer 22A of the first conductive part 2A and the first surface layer 291a of the first intermediate bonding material 29a includes the bonding unique region Pca. In this embodiment, the bonding interface between the second bonding layer 321A of the support substrate 3 and the second surface layer 292a of the first intermediate bonding material 29a does not include the bonding unique region Pca. This is determined by the procedure of the manufacturing method of the semiconductor device A1, which will be described later.

[0068] 18, the semiconductor device A1 may have a bonded portion formed by solid-state bonding. This bonded portion may be a structure in which the second conductive portion 2B and the support substrate 3 are bonded via a first intermediate bonding material 29b.

[0069] The first intermediate bonding material 29b can have a base layer 290b, a first surface layer 291b, and a second surface layer 292b.

[0070] The base layer 290b may be primarily composed of Cu (copper). There are no limitations on the thickness of the base layer 290b, and in this embodiment, the base layer 290b may be thicker than the first surface layer 291b and the second surface layer 292b. The thickness of the base layer 290b may be, for example, 50 μm or more and 300 μm or less.

[0071] The first surface layer 291b may be located on the z2 side of the base layer 290b in the z direction. The first surface layer 291b may be solid-state bonded to the second switching element 1B. In this embodiment, the first surface layer 291b may be mainly composed of Ag (silver). There are no limitations on the thickness of the first surface layer 291b. In this embodiment, the first surface layer 291b may be thinner than the base layer 290b. The thickness of the first surface layer 291b may be, for example, not less than 0.1 μm and not more than 15 μm.

[0072] The first bonding layer 22B of the second conductive portion 2B may be located on the z1 side of the main body layer 20B in the z direction. The first bonding layer 22B may be solid-state bonded to the first surface layer 291b. In this embodiment, the first bonding layer 22B may be primarily composed of Ag (silver). The thickness of the first bonding layer 22B is not particularly limited and may be, for example, 0.1 μm or more and 15 μm or less.

[0073] The metal that is the main component of the first surface layer 291b and the first bonding layer 22B is not particularly limited as long as they are configured to be solid-state bonded to each other.

[0074] The second surface layer 292b may be located on the z1 side of the base layer 290b in the z direction. The second surface layer 292b may be solid-state bonded to the support substrate 3. In this embodiment, the second surface layer 292b may be mainly composed of Ag (silver). The thickness of the second surface layer 292b is not limited in any way. In this embodiment, the second surface layer 292b may be thinner than the base layer 290b. The thickness of the second surface layer 292b may be, for example, not less than 0.1 μm and not more than 15 μm.

[0075] The support substrate 3 of this embodiment may further include a second bonding layer 321B. The second bonding layer 321B may be located on the z2 side of the second portion 32B in the z direction. The second bonding layer 321B may be solid-state bonded to the second surface layer 292b. In this embodiment, the second bonding layer 321B may be primarily composed of Ag (silver). The thickness of the second bonding layer 321B is not particularly limited and may be, for example, 0.1 μm or more and 15 μm or less.

[0076] The metal that is the main component of the second surface layer 292b and the second bonding layer 321B is not particularly limited as long as they are configured to be solid-state bonded to each other.

[0077] Either the bonding interface between the second conductive portion 2B and the first intermediate bonding material 29b or the bonding interface between the support substrate 3 and the first intermediate bonding material 29b may include a bonding unique region Pcb. The bonding unique region Pcb may be a region where the bonding state differs from that of the surrounding region. Like the bonding unique region Pca, the bonding unique region Pcb may be formed by performing a temporary bonding process in the manufacturing method of the semiconductor device A1 described below. An example of the bonding unique region Pcb is a configuration where the bonding strength is higher than that of the surrounding region. For example, the bonding unique region Pcb may have relatively fewer microvoids than the surrounding region that can inevitably occur due to solid-state bonding. For example, when performing SAT (ultrasonic testing), the bonding unique region Pcb is recognized as a region where the shading of the image differs from that of the surrounding region.

[0078] The number of junction unique regions Pcb is not limited in any way and may be one or more. In the example shown in FIG. 8 , the semiconductor device A1 has two junction unique regions Pcb. The two junction unique regions Pcb may be located in positions that avoid the multiple second switching elements 1B in plan view. The two junction unique regions Pcb may be located on a diagonal line between the second conductive portion 2B and the second portion 32B. The shape of the junction unique region Pcb is not limited in any way and may be any of a variety of shapes, such as a triangle, a rectangle, a polygon, or the like, in addition to the circular shape shown in FIG. 8 .

[0079] In this embodiment, the bonding interface between the first bonding layer 22B of the second conductive part 2B and the first surface layer 291b of the first intermediate bonding material 29b includes the bond unique region Pcb. In this embodiment, the bonding interface between the second bonding layer 321B of the support substrate 3 and the second surface layer 292b of the first intermediate bonding material 29b does not include the bond unique region Pcb. This is determined by the procedure of the manufacturing method of the semiconductor device A1, which will be described later.

[0080] Multiple power terminals 41-43: The multiple power terminals 41-43 may each be a plate-shaped metal plate. The constituent material of this metal plate may be, for example, primarily Cu. In the examples shown in Figures 1 to 5, 8, and 10, the semiconductor device A1 may include one power terminal 41, two power terminals 42, and two power terminals 43.

[0081] The first power supply voltage can be applied between the power terminal 41 and the two power terminals 42. The power terminal 41 can be, for example, a terminal (P terminal) connected to the positive pole of a DC power supply, and the two power terminals 42 can each be a terminal (N terminal) connected to the negative pole of the DC power supply. Alternatively, the power terminal 41 can be an N terminal and the two power terminals 42 can each be a P terminal. In this case, the wiring inside the package can be appropriately changed to match the change in terminal polarity. The second power supply voltage can be applied to the two power terminals 43. The two power terminals 43 can each be an output terminal capable of outputting a voltage (the second power supply voltage) converted by the switching operations of the multiple first switching elements 1A and the multiple second switching elements 1B. Each of the multiple power terminals 41 to 43 can include a portion covered by the resin member 8 and a portion exposed from the resin member 8.

[0082] The power terminal 41 may be integral with the first conductive portion 2A, as shown in FIGS. 8, 12, and 19. Alternatively, the power terminal 41 may be separated from the first conductive portion 2A and conductively joined to the first conductive portion 2A. As shown in FIG. 8, the power terminal 41 may be located on the x2 side of the multiple semiconductor elements 1 and the first conductive portion 2A (support conductor 2). The insulating layer 31 is electrically connected to the first conductive portion 2A and, via the first conductive portion 2A, to the back electrodes 15 (drain electrodes) of the multiple first switching elements 1A.

[0083] As shown in, for example, FIGS. 8 and 11 , the two power terminals 42 may be spaced apart from the first conductive portion 2A. A second conductive member 72 may be joined to each of the two power terminals 42. As shown in FIG. 8 , the two power terminals 42 may be located on the x2 side of the multiple semiconductor elements 1 and the first conductive portion 2A (support conductor 2). The two power terminals 42 may be electrically connected to the second conductive member 72. The two power terminals 42 may be electrically connected to second main surface electrodes 12 (source electrodes) of the multiple second switching elements 1B via the electrically connected second conductive member 72.

[0084] The power terminal 41 and the two power terminals 42 each protrude from the resin member 8 toward the x2 side. The power terminal 41 and the two power terminals 42 can be spaced apart from each other. The two power terminals 42 can be positioned on opposite sides of the power terminal 41 in the y direction. As can be seen from FIGS. 6, 7, and 9, the power terminal 41 and the two power terminals 42 can overlap each other when viewed in the y direction.

[0085] As shown in FIGS. 8 and 11 , the two power terminals 43 may each be integral with the second conductive portion 2B, for example. Alternatively, the two power terminals 43 may each be separate from the second conductive portion 2B and conductively joined to the second conductive portion 2B. As shown in FIG. 8 , the two power terminals 43 may each be located on the x1 side of the semiconductor elements 1 and the second conductive portion 2B (support conductor 2). Each power terminal 43 may be electrically connected to the first conductive portion 2A and electrically connected to the back electrode 15 (drain) of each second switching element 1B via the electrically connected first conductive portion 2A. The number of power terminals 43 is not limited to two and may be, for example, one or three or more. For example, if there is one power terminal 43, it is preferably connected to the center of the second conductive portion 2B in the y direction.

[0086] Multiple control terminals 44: The multiple control terminals 44 may each be a pin-shaped terminal for controlling the drive of the multiple semiconductor elements 1 (the multiple first switching elements 1A and the multiple second switching elements 1B). The multiple control terminals 44 may each be, for example, a press-fit terminal. The z-direction dimension of each of the multiple control terminals 44 may be, for example, 10 mm to 30 mm (15.8 mm, for example). The z-direction dimension of the control terminal 44 may be the length from the lower end (the end on the z1 side) of a holder 441 (described below) to the upper end (the end on the z2 side) of a metal pin 442 (described below). As shown in FIGS. 1 and 4 , the multiple control terminals 44 may include multiple first control terminals 45 and multiple second control terminals 46. The multiple first control terminals 45 may be used to control the multiple first switching elements 1A. The multiple second control terminals 46 may be used to control the multiple second switching elements 1B.

[0087] Each of the plurality of control terminals 44 (the plurality of first control terminals 45 and the plurality of second control terminals 46 ) may include a holder 441 and a metal pin 442 .

[0088] The holder 441 may be made of a conductive material. As shown in FIGS. 13 and 16 , the holder 441 is bonded to the signal board 5 (the first metal layer 52 described below) via a conductive bonding material 449. The holder 441 may include a cylindrical portion, an upper flange, and a lower flange. The upper flange is connected to an upper end of the cylindrical portion in the z direction (the z2 side), and the lower flange is connected to an end of the cylindrical portion in the z direction (the z1 side). A metal pin 442 may be inserted through at least the upper flange and the cylindrical portion of the holder 441. The holder 441 may be covered with a resin member 8.

[0089] The metal pin 442 may be a rod-shaped member extending in the z direction. The metal pin 442 may be supported by being press-fitted into the holder 441. The metal pin 442 may be electrically connected to the signal substrate 5 (a first metal layer 52 described below) at least via the holder 441. As shown in FIGS. 13 and 16 , when the lower end (the end on the z1 side) of the metal pin 442 is in contact with the conductive bonding material 449 inside the insertion hole of the holder 441, the metal pin 442 may be electrically connected to the signal substrate 5 also via the conductive bonding material 449.

[0090] Multiple first control terminals 45: As shown in FIG. 4, the multiple first control terminals 45 may be positioned at intervals in the y direction. The multiple first control terminals 45 are fixed to the signal board 5 (first signal board 5A). As shown in FIGS. 5 to 7 and 12, the multiple first control terminals 45 may be positioned in the x direction between the multiple first switching elements 1A and the multiple power terminals 41, 42. As shown in FIGS. 1 and 4, the multiple first control terminals 45 may include a first drive terminal 45A and multiple first detection terminals 45B to 45E.

[0091] The first drive terminal 45A may be a terminal (gate terminal) for inputting a drive signal for the plurality of first switching elements 1A. The first drive terminal 45A may be configured to allow input of a first drive signal for driving the plurality of first switching elements 1A (for example, to allow application of a gate voltage).

[0092] The first detection terminal 45B may be a terminal (source sense terminal) for detecting source signals of the multiple first switching elements 1A. The first detection terminal 45B may be configured to output a first detection signal for detecting the conduction state of the multiple first switching elements 1A. For example, the first detection terminal 45B may be configured to detect, as the first detection signal, a voltage (a voltage corresponding to a source current) applied to the second principal surface electrode 12 (source electrode) of the first switching element 1A.

[0093] The first detection terminal 45C and the first detection terminal 45D may be terminals that are each electrically connected to one of the two thermistors 17. The one thermistor 17 may be mounted on a first signal board 5A, which will be described later.

[0094] The first detection terminal 45E may be a terminal (drain sense terminal) for detecting drain signals of the plurality of first switching elements 1A. The first detection terminal 45E may be configured to be able to detect a voltage (a voltage corresponding to a drain current) applied to each back electrode 15 (drain electrode) of the plurality of first switching elements 1A.

[0095] Multiple second control terminals 46: As shown in FIG. 4, the multiple second control terminals 46 may be positioned at intervals in the y direction. The multiple second control terminals 46 may be fixed to the signal board 5 (second signal board 5B). As shown in FIGS. 5 to 7 and 12, the multiple second control terminals 46 may be positioned in the x direction between the multiple second switching elements 1B and the multiple power terminals 43. As shown in FIGS. 1 and 4, the multiple second control terminals 46 may include a second drive terminal 46A and multiple second detection terminals 46B to 46E.

[0096] The second drive terminal 46A can be a terminal (gate terminal) for inputting a drive signal for the plurality of second switching elements 1B. The second drive terminal 46A is configured to be able to input a second drive signal for driving the plurality of second switching elements 1B (for example, it can be configured to be able to apply a gate voltage).

[0097] The second detection terminal 46B may be a terminal (source sense terminal) for detecting source signals of the plurality of second switching elements 1B. The plurality of second detection terminals 46B may be configured to be able to output second detection signals for detecting the conduction states of the plurality of second switching elements 1B. For example, the second detection terminal 46B may be configured to be able to detect, as the second detection signal, a voltage (a voltage corresponding to a source current) applied to the second main surface electrode 12 (source electrode) of the second switching element 1B.

[0098] The second detection terminal 46C and the second detection terminal 46D may be terminals that are electrically connected to the other of the two thermistors 17. The other thermistor 17 may be mounted on a second signal board 5B, which will be described later.

[0099] The second detection terminal 46E can be a terminal (drain sense terminal) for detecting drain signals of the second switching elements 1B. The second detection terminal 46E can detect a voltage (a voltage corresponding to a drain current) applied to each back electrode 15 (drain electrode) of the second switching elements 1B.

[0100] Signal substrate 5: The signal substrate 5 may support a plurality of control terminals 44. The signal substrate 5 may be interposed between the support conductor 2 and each control terminal 44 in the z direction. The thickness of the signal substrate 5 (dimension in the z direction) may be, for example, 0.5 mm or more and 1.0 mm or less. The dimension in the z direction of each control terminal 44 may be 20 times or more and 30 times or less the thickness (dimension in the z direction) of the signal substrate 5. The signal substrate 5 may include a first signal substrate 5A and a second signal substrate 5B.

[0101] 5, 12, and 13, the first signal substrate 5A is located on the first conductive portion 2A and can support a plurality of first control terminals 45. The first signal substrate 5A can be adhered to the first conductive portion 2A via an adhesive layer 6 (first adhesive body 6A) as shown in FIGS.

[0102] 5, 12, and 16, the second signal substrate 5B may be located on the second conductive portion 2B and may support a plurality of second control terminals 46. The second signal substrate 5B may be adhered to the second conductive portion 2B via an adhesive layer 6 (second adhesive body 6B) as shown in FIGS.

[0103] The signal substrates 5 (each of the first signal substrate 5A and the second signal substrate 5B) may be formed of, for example, a DBC substrate. The signal substrate 5 may have an insulating substrate 51, a first metal layer 52, and a second metal layer 53 stacked on top of each other. Unless otherwise specified, the insulating substrate 51, the first metal layer 52, and the second metal layer 53 described below may be common to the first signal substrate 5A and the second signal substrate 5B.

[0104] The insulating substrate 51 may be made of, for example, ceramic. Examples of such ceramics include AlN, SiN, and Al2O3. The insulating substrate 51 may have, for example, a rectangular shape in plan view. As shown in FIGS. 13 and 16, the insulating substrate 51 may have a main surface 51a and a back surface 51b. The main surface 51a and the back surface 51b may be spaced apart in the z direction. The main surface 51a faces the z2 side, and the back surface 51b faces the z1 side. The back surface 51b may face the supporting conductor 2.

[0105] As shown in Figures 13 and 16, the second metal layer 53 may be located above the back surface 51b of the insulating substrate 51. The second metal layer 53 may be adhered to the support conductor 2 via an adhesive layer 6. The second metal layer 53 of the first signal substrate 5A may be adhered to the first conductive portion 2A via a first adhesive 6A described below. The second metal layer 53 of the second signal substrate 5B may be adhered to the second conductive portion 2B via a second adhesive 6B. The second metal layer 53 may be mainly composed of Cu, for example. The second metal layer 53 may be an example of a "metal layer".

[0106] As shown in FIGS. 13 and 16 , the first metal layer 52 may be located above the main surface 51 a of the insulating substrate 51. The plurality of control terminals 44 may be provided upright on the first metal layer 52. The first metal layer 52 of the first signal substrate 5A may have a plurality of first control terminals 45 provided upright. The first metal layer 52 of the second signal substrate 5B may have a plurality of second control terminals 46 provided upright. The first metal layer 52 may be primarily composed of Cu, for example. As shown in FIG. 8 , the first metal layer 52 includes a plurality of wiring layers 521-526. The plurality of wiring layers 521-526 may be spaced apart and insulated from one another.

[0107] 8 , a plurality of wires 73 may be bonded to the wiring layer 521. The wiring layer 521 may be electrically connected to the first principal surface electrodes 11 (gate electrodes) of the respective semiconductor elements 1 via the bonded wires 73. The wiring layer 521 of the first signal substrate 5A may be electrically connected to the first principal surface electrodes 11 of the respective first switching elements 1A via the bonded wires 73. The wiring layer 521 of the second signal substrate 5B may be electrically connected to the first principal surface electrodes 11 of the respective second switching elements 1B via the bonded wires 73.

[0108] As shown in FIG. 8 , a plurality of wires 75 may be bonded to the wiring layer 526. The wiring layer 526 may be electrically connected to the wiring layer 521 via the bonded wires 75. The wiring layer 526 of the first signal substrate 5A may be electrically connected to the first principal surface electrodes 11 (gate electrodes) of the first switching elements 1A via the wires 75, the wiring layer 521 of the first signal substrate 5A, and the wires 73. The wiring layer 526 of the second signal substrate 5B may be electrically connected to the first principal surface electrodes 11 (gate electrodes) of the second switching elements 1B via the wires 75, the wiring layer 521 of the second signal substrate 5B, and the wires 73. The first drive terminal 45A may be bonded to the wiring layer 526 of the first signal substrate 5A. The second drive terminal 46A may be bonded to the wiring layer 526 of the second signal substrate 5B.

[0109] As shown in FIG. 8 , a plurality of wires 74 may be bonded to the wiring layer 522. The wiring layer 522 may be electrically connected to the third principal surface electrode 13 (source sense electrode) of each semiconductor element 1 via each wire 74. The wiring layer 522 of the first signal substrate 5A may be electrically connected to the third principal surface electrode 13 (source sense electrode) of each first switching element 1A via each wire 74. The wiring layer 522 of the second signal substrate 5B may be electrically connected to the third principal surface electrode 13 (source sense electrode) of each second switching element 1B via each wire 74. The first detection terminal 45B may be bonded to the wiring layer 522 of the first signal substrate 5A. The second detection terminal 46B may be bonded to the wiring layer 522 of the second signal substrate 5B.

[0110] As shown in Fig. 8 , the thermistor 17 can be bonded to the wiring layer 523 and the wiring layer 524. As shown in Fig. 8 , the wiring layer 523 of the first signal substrate 5A can be bonded to the first detection terminal 45C. As shown in Fig. 8 , the wiring layer 524 of the first signal substrate 5A can be bonded to the first detection terminal 45D. The wiring layer 523 of the second signal substrate 5B can be bonded to the second detection terminal 46C. The wiring layer 524 of the second signal substrate 5B can be bonded to the second detection terminal 46D.

[0111] Wires 76 may be bonded to the wiring layer 525. The wiring layer 525 may be electrically connected to the support conductor 2 via the bonded wires 76. As shown in FIG. 8 , the wiring layer 525 of the first signal substrate 5A may be electrically connected to the first conductive portion 2A via the wires 76. The wiring layer 525 of the second signal substrate 5B may be electrically connected to the second conductive portion 2B via the wires 76. A first detection terminal 45E may be bonded to the wiring layer 525 of the first signal substrate 5A. A second detection terminal 46E may be bonded to the wiring layer 525 of the second signal substrate 5B.

[0112] The signal board 5 may be a printed circuit board such as a glass epoxy board, instead of a DBC board, on which at least the wiring layers 521 to 526 can be formed.

[0113] Adhesive layer 6: The adhesive layer 6 can bond the signal substrate 5 and the support conductor 2. The adhesive layer 6 can be interposed between the signal substrate 5 and the support conductor 2 in the z direction. The adhesive layer 6 can overlap the signal substrate 5 in a planar view. The thickness (dimension in the z direction) of the adhesive layer 6 can be, for example, 20 μm or more and 200 μm or less (85 μm in one example).

[0114] As shown in FIGS. 12 to 16 , the adhesive layer 6 may include a first adhesive body 6A and a second adhesive body 6B. The first adhesive body 6A may bond the first signal substrate 5A and the first conductive portion 2A together. The first adhesive body 6A may be interposed between the first signal substrate 5A and the first conductive portion 2A and may overlap the first signal substrate 5A in a planar view. The second adhesive body 6B may bond the second signal substrate 5B and the second conductive portion 2B together. The second adhesive body 6B may be interposed between the second signal substrate 5B and the second conductive portion 2B and may overlap the second signal substrate 5B in a planar view.

[0115] 13 and 16, the adhesive layer 6 (each of the first adhesive body 6A and the second adhesive body 6B) may include an insulating layer 61 and a pair of adhesive layers 62, 63. Unless otherwise specified, the insulating layer 61 and the pair of adhesive layers 62, 63 described below may be common to both the first adhesive body 6A and the second adhesive body 6B.

[0116] The insulating layer 61 may be made of a resin material. Considering its heat resistance and insulating properties, polyimide is preferable as the resin material. The insulating layer 61 of the first adhesive body 6A can electrically insulate the first signal substrate 5A from the first conductive portion 2A. The insulating layer 61 of the second adhesive body 6B can electrically insulate the second signal substrate 5B from the second conductive portion 2B. The insulating layer 61 may be, for example, a film. The insulating layer 61 may be a sheet or plate instead of a film. In this disclosure, a sheet may be as soft as a film but thicker. A plate may be harder and less flexible than a film or sheet, and thicker than a sheet. The definitions of film, sheet, and plate are not limited to these and may be modified as appropriate according to conventional classifications. The thickness (z-direction dimension) of the insulating layer 61 may be 0.1% to 1.0% of the z-direction dimension of each control terminal 44. The thickness (dimension in the z direction) of the insulating layer 61 may be 20% or more and 75% or less of the thickness (dimension in the z direction) of the adhesive layer 6. The thickness (dimension in the z direction) of the insulating layer 61 may be, for example, 10 μm or more and 150 μm or less (25 μm in one example).

[0117] 13 and 16, the insulating layer 61 may include a principal surface 61a and a rear surface 61b. The principal surface 61a and the rear surface 61b may be spaced apart in the z direction. The principal surface 61a may face the z2 side (upward in the z direction), and the rear surface 61b may face the z1 side (downward in the z direction).

[0118] The pair of adhesive layers 62, 63 may be positioned above both sides of the insulating layer 61 in the z direction. Each of the pair of adhesive layers 62, 63 may be made of a resin adhesive. The resin adhesive may include, for example, a silicone-based adhesive and an acrylic-based adhesive. The thickness (dimension in the z direction) of each of the pair of adhesive layers 62, 63 may be 10% to 150% of the thickness (dimension in the z direction) of the insulating layer 61. The thickness (dimension in the z direction) of each of the pair of adhesive layers 62, 63 may be, for example, 5 μm to 50 μm (30 μm in one example).

[0119] 13 and 16 , the adhesive layer 62 may be located above the main surface 61 a. The adhesive layer 62 may be interposed between the insulating layer 61 and the signal substrate 5 in the z direction. The adhesive layer 62 of the first adhesive body 6A may be interposed between the insulating layer 61 of the first adhesive body 6A and the first signal substrate 5A in the z direction. The adhesive layer 62 of the second adhesive body 6B may be interposed between the insulating layer 61 of the second adhesive body 6B and the second signal substrate 5B in the z direction.

[0120] 13 and 16 , the adhesive layer 63 may be located above the back surface 61b. The adhesive layer 63 may be interposed between the insulating layer 61 and the supporting conductor 2 in the z direction. The adhesive layer 63 of the first adhesive body 6A may be interposed between the insulating layer 61 of the first adhesive body 6A and the first conductive portion 2A in the z direction. The adhesive layer 63 of the second adhesive body 6B may be interposed between the insulating layer 61 of the second adhesive body 6B and the second conductive portion 2B.

[0121] As can be understood from the above-described configuration, the adhesive layer 6 of the present disclosure can be, for example, a double-sided adhesive tape. In the manufacturing process of the semiconductor device A1, the adhesive layer 6 can be attached to the signal substrate 5 to which a plurality of control terminals 44 are bonded, and then attached to the support conductors 2. Note that the adhesive layer 6 does not have to be a double-sided adhesive tape, and any adhesive that temporarily melts, such as solder, when bonding two components together is acceptable. In other words, the adhesive layer 6 may be any adhesive that can bond two components together without melting.

[0122] First conductive member 71 and second conductive member 72: The first conductive member 71 and the second conductive member 72, together with the support conductor 2, can form a path for a main circuit current switched by the multiple semiconductor elements 1 (the multiple first switching elements 1A and the multiple second switching elements 1B). The first conductive member 71 and the second conductive member 72 can be spaced apart from the main surfaces 201 of the first conductive portion 2A and the second conductive portion 2B on the z2 side and overlap the main surfaces 201 in a plan view. The first conductive member 71 and the second conductive member 72 can each be made of, for example, a metal plate. The metal can be, for example, Cu or a Cu alloy. The first conductive member 71 and the second conductive member 72 can be appropriately bent.

[0123] The first conductive member 71 may electrically connect the plurality of first switching elements 1A and the second conductive portion 2B. As shown in FIGS. 5 and 8 , the first conductive member 71 may be connected to the second main surface electrode 12 (source electrode) of each first switching element 1A and the second conductive portion 2B. As shown in FIGS. 5 and 8 , the first conductive member 71 may electrically connect the second main surface electrode 12 of each first switching element 1A and the second conductive portion 2B. The first conductive member 71 may form a path for a main circuit current switched by the plurality of first switching elements 1A. As shown in FIGS. 5 , 8 , and 12 , the first conductive member 71 may include a main portion 711, a plurality of first connection end portions 712, and a plurality of second connection end portions 713.

[0124] The main portion 711 may be located between the multiple first switching elements 1A and the second conductive portion 2B in the x direction. The main portion 711 may be a strip-shaped portion extending in the y direction. As shown in FIG. 12 , the main portion 711 may be located on the z2 side of the multiple first connection ends 712 and the multiple second connection ends 713. In this embodiment, as shown in FIGS. 5 , 8 , and 12 , the main portion 711 may include multiple openings 711 a. Each of the multiple openings 711 a may be a through hole penetrating the first conductive member 71 (main portion 711) in the z direction. The multiple openings 711 a may be arranged at intervals in the y direction. The multiple openings 711 a do not overlap the second conductive member 72 in a plan view. The plurality of openings 711a can be formed to facilitate the flow of the resin material between the upper side (z2 side) and the lower side (z1 side) near the main portion 711 (first conductive member 71) when injecting the fluid resin material to form the resin member 8. The shape of the main portion 711 is not limited to this configuration, and for example, the openings 711a do not need to be formed.

[0125] The first connection ends 712 and the second connection ends 713 may each be connected to the main portion 711. One of the first connection ends 712 and the second connection ends 713 may face one of the first switching elements 1A. As shown in FIG. 12 , each of the first connection ends 712 is bonded to one of the second principal surface electrodes 12 of the first switching elements 1A via a conductive bonding material 719. Each of the second connection ends 713 is bonded to one of the second conductive portions 2B via a conductive bonding material 719. The conductive bonding material 719 may be, for example, solder, a metal paste material, or a sintered metal. In the examples shown in FIGS. 8 , 12 , 13 , and 21 , each of the first connection ends 712 may include an opening 712 a. The position of each opening 712 a may overlap the center of the corresponding first switching element 1A in a plan view. 12, 13, and 21, each opening 712a may be, for example, a through hole that penetrates each first connection end portion 712 in the z direction. The opening 712a is used, for example, when positioning the first conductive member 71 with respect to the supporting conductor 2.

[0126] In the illustrated example, the multiple first connection ends 712 and the multiple second connection ends 713 are connected to one another by the main portion 711, but instead of this configuration, the main portion 711 may be divided into multiple portions, and the divided portions may connect each of the multiple first connection ends 712 to each of the multiple second connection ends 713. In other words, a configuration may be provided in which one first conducting member 71 is provided for each of the multiple first switching elements 1A.

[0127] As shown in FIG. 5 , the second conductive member 72 may be connected to the second principal surface electrode 12 (source electrode) of each second switching element 1B and the plurality of power terminals 42. The second conductive member 72 may electrically connect the second principal surface electrode 12 of each second switching element 1B to the power terminals 42. The second conductive member 72 may form a path for a main circuit current switched by the plurality of second switching elements 1B. The second conductive member 72 may have a maximum dimension in the x direction of, for example, 25 mm to 40 mm, and a maximum dimension in the y direction of, for example, 30 mm to 45 mm. As shown in FIG. 5 and other figures, the second conductive member 72 may include a pair of a first wiring portion 721, a second wiring portion 722, a third wiring portion 723, and a fourth wiring portion 724.

[0128] One of the pair of first wiring portions 721 may be connected to one of the pair of power terminals 42, and the other of the pair of first wiring portions 721 may be connected to the other of the pair of power terminals 42. As shown in FIG. 5 , each of the pair of first wiring portions 721 may have a strip shape extending in the x direction in a plan view. The pair of first wiring portions 721 may be spaced apart in the y direction and positioned parallel (or approximately parallel). As shown in FIGS. 5 and 11 , each of the pair of first wiring portions 721 may include a first end portion 721 a. Each first end portion 721 a may be an end portion of each first wiring portion 721 on the x2 side. As shown in FIG. 11 , each first end portion 721 a may be positioned closer to the z1 side than other portions of each first wiring portion 721. As shown in FIG. 11 , each first end portion 721 a may be joined to each of the pair of power terminals 42 via a conductive bonding material 729. The conductive bonding material 729 may be, for example, solder, metal paste, or sintered metal. In the example shown in FIG. 5 , each first wiring portion 721 may have one or more depressions. The one or more depressions in each first wiring portion 721 may be, for example, semicircular in plan view. The one or more depressions may overlap the supporting conductor 2 in plan view.

[0129] As shown in FIG. 5 , the second wiring portion 722 may be connected to both of the pair of first wiring portions 721. The second wiring portion 722 is sandwiched between the pair of first wiring portions 721 in the y direction. The second wiring portion 722 may have a strip shape extending in the y direction in a plan view. As shown in FIG. 5 , the second wiring portion 722 may overlap multiple second switching elements 1B. The second wiring portion 722 may be connected to each of the second switching elements 1B. The second wiring portion 722 may have multiple recessed regions 722a. As shown in FIG. 20 , each of the multiple recessed regions 722a extends downward in the z direction (toward the z1 side) further than other portions of the second wiring portion 722. As shown in FIG. 20 , each recessed region 722a of the second wiring portion 722 may be bonded to each of the second main surface electrodes 12 (source electrodes) of the multiple second switching elements 1B via a conductive bonding material 729. 5 and 20, each recessed region 722a may have a slit. The slit may be located at the center of each recessed region 722a in the y direction and extend in the x direction. Each recessed region 722a may include two portions separated in the y direction by the slit. Note that each recessed region 722a does not necessarily have to have a slit.

[0130] As shown in FIG. 5 , the third wiring portion 723 may be connected to both of the pair of first wiring portions 721. The first wiring portion 721 may be sandwiched between the pair of first wiring portions 721 in the y direction. The third wiring portion 723 may be strip-shaped extending in the y direction in a plan view. The third wiring portion 723 may be separated from the second wiring portion 722 in the x direction. The third wiring portion 723 may be arranged parallel (or approximately parallel) to the second wiring portion 722. As shown in FIG. 5 , the third wiring portion 723 may overlap multiple first switching elements 1A in a plan view. The third wiring portion 723 may be located above (on the z2 side of) each first connection end portion 712 of the first conductive member 71 in the z direction. The third wiring portion 723 may overlap the first connection end portion 712 in a plan view.

[0131] As shown in FIG. 5 , each of the multiple fourth wiring portions 724 may be connected to both the second wiring portion 722 and the third wiring portion 723. Each fourth wiring portion 724 may be located between the second wiring portion 722 and the third wiring portion 723 in the x direction. Each fourth wiring portion 724 may have a strip shape extending in the x direction in a plan view. The multiple fourth wiring portions 724 may be spaced apart in the y direction and arranged parallel (or approximately parallel) in a plan view. The multiple fourth wiring portions 724 may be arranged parallel (or approximately parallel) to the pair of first wiring portions 721. One end in the x direction of each of the multiple fourth wiring portions 724 may be connected to a portion of the third wiring portion 723 that overlaps between two first switching elements 1A adjacent in the y direction in a plan view. The other end in the x direction of each of the plurality of fourth wiring portions 724 can be connected to a portion of the second wiring portion 722 that overlaps between two second switching elements 1B adjacent in the y direction in plan view. Each of the plurality of fourth wiring portions 724 can overlap, for example, the first conductive member 71 (main portion 711).

[0132] Multiple Wires 73-76: Each of the multiple wires 73-76 may be, for example, a bonding wire, and may connect two separate portions. The constituent material of each of the wires 73-76 may be, for example, primarily any of Au (gold), Al, and Cu.

[0133] The plurality of wires 73 can be bonded to the wiring layer 521 and the first main surface electrode 11 (gate electrode) of each semiconductor element 1, thereby providing electrical continuity therebetween. As shown in Fig. 8 , the plurality of wires 73 can include wires bonded to the first main surface electrode 11 of each first switching element 1A and the wiring layer 521 of the first signal substrate 5A, and wires bonded to the first main surface electrode 11 of each second switching element 1B and the wiring layer 521 of the second signal substrate 5B.

[0134] The plurality of wires 74 are bonded to the wiring layer 522 and the third principal surface electrode 13 (source sense electrode) of each semiconductor element 1, and can provide electrical continuity therebetween. As shown in Fig. 8 , the plurality of wires 74 can include wires bonded to the third principal surface electrode 13 of each first switching element 1A and the wiring layer 522 of the first signal substrate 5A, and wires bonded to the third principal surface electrode 13 of each second switching element 1B and the wiring layer 522 of the second signal substrate 5B. In a configuration in which each semiconductor element 1 does not have a third principal surface electrode 13, the plurality of wires 74 are bonded to each second principal surface electrode 12 instead of each third principal surface electrode 13.

[0135] The plurality of wires 75 are bonded to the wiring layer 521 and the wiring layer 526 to provide electrical continuity therebetween. As shown in Fig. 8 , the plurality of wires 75 may include wires bonded to the wiring layer 521 and the wiring layer 526 of the first signal substrate 5A and wires bonded to the wiring layer 521 and the wiring layer 526 of the second signal substrate 5B.

[0136] The plurality of wires 76 can be bonded to the wiring layer 525 and the support conductor 2 to provide electrical continuity therebetween. As shown in Fig. 8 , the plurality of wires 76 can include wires bonded to the wiring layer 525 and the first conductive portion 2A of the first signal substrate 5A and wires bonded to the wiring layer 525 and the second conductive portion 2B of the second signal substrate 5B.

[0137] Resin member 8: The resin member 8 may be a sealing material that protects the multiple semiconductor elements 1 (the multiple first switching elements 1A and the multiple second switching elements 1B). The resin member 8 may cover the multiple semiconductor elements 1 (the multiple first switching elements 1A and the multiple second switching elements 1B), the support conductor 2 (the first conductive portion 2A and the second conductive portion 2B), the support substrate 3 (excluding the lower surface of the second metal layer 33), a portion of each of the multiple power terminals 41 to 43, a portion of each of the multiple control terminals 44, the signal substrate 5 (the first signal substrate 5A and the second signal substrate 5B), the adhesive layer 6 (the first adhesive body 6A and the second adhesive body 6B), the first conductive member 71, the second conductive member 72, and the multiple wires 73 to 76. The resin member 8 may be made of, for example, a black epoxy resin. The resin member 8 may be formed, for example, by molding. The resin member 8 may have, for example, an x-direction dimension of approximately 35 mm to 60 mm, a y-direction dimension of approximately 35 mm to 50 mm, and a z-direction dimension of approximately 4 mm to 15 mm. These dimensions may be the size of the largest portion along each direction. The resin member 8 may have a resin main surface 81, a resin back surface 82, and multiple resin side surfaces 831 to 834.

[0138] The resin main surface 81 and the resin back surface 82 may be spaced apart in the z direction, as shown in FIGS. 6 , 7 , 9 , 11 , 12 , and 19 to 22 . The resin main surface 81 may face the z2 side, and the resin back surface 82 may face the z1 side. A configuration may be adopted in which multiple control terminals 44 (multiple first control terminals 45 and multiple second control terminals 46) protrude from the resin main surface 81. As shown in FIG. 10 , the resin back surface 82 may have a frame shape surrounding the lower surface of the second metal layer 33 of the support substrate 3 in a plan view. The lower surface of the second metal layer 33 is exposed from the resin back surface 82 and may be flush with the resin back surface 82, for example. Multiple resin side surfaces 831 to 834 are each connected to both the resin main surface 81 and the resin back surface 82 and are located between them in the z direction. As shown in FIG. 4 and other figures, the resin side surface 831 and the resin side surface 832 may be spaced apart in the x direction. The resin side surface 831 may face the x1 side, and the resin side surface 832 may face the x2 side. Two power terminals 43 may protrude from the resin side surface 831, and multiple power terminals 41, 42 may protrude from the resin side surface 832. As shown in FIG. 4 and other figures, the resin side surface 833 and the resin side surface 834 may be spaced apart in the y direction. The resin side surface 833 may face the y1 side, and the resin side surface 834 may face the y2 side.

[0139] The resin side surface 832 may have a plurality of recesses 832a as shown in FIG. 4 . Each recess 832a may be a portion recessed in the x direction in a plan view. The plurality of recesses 832a may include one located between one of the two power terminals 42 and the power terminal 41 in a plan view, and one located between the other of the two power terminals 42 and the power terminal 41. The plurality of recesses 832a may increase either the creepage distance along the resin side surface 832 between the power terminal 41 and one of the two power terminals 42, or the creepage distance along the resin side surface 832 between the power terminal 41 and the other of the two power terminals 42.

[0140] As shown in FIGS. 11 and 12 , the resin member 8 can have a plurality of first protrusions 851 , a plurality of second protrusions 852 , and a resin void 86 .

[0141] Each of the multiple first protrusions 851 may protrude in the z direction from the resin main surface 81. The multiple first protrusions 851 may be located near four corners of the resin member 8 in a plan view. The tip (the end on the z2 side) of each first protrusion 851 may have a first protrusion end surface 851a. Each of the multiple first protrusions 851 may be parallel (or approximately parallel) to the resin main surface 81. The multiple first protrusion end surfaces 851a may be located on the same plane (x-y plane). Each of the multiple first protrusions 851 may have, for example, a bottomed, hollow truncated cone shape. The multiple first protrusions 851 may be used as spacers when the semiconductor device A1 is mounted on a control circuit board or the like. The control circuit board may be included in a device that uses power generated by the semiconductor device A1. 11 , each of the plurality of first protrusions 851 may have a recess 851b and an inner wall surface 851c that defines the recess 851b. The shape of each of the first protrusions 851 may be columnar, and is preferably cylindrical. It is preferable that the shape of the recess 851b is cylindrical, and that the inner wall surface 851c is a single perfect circle in plan view.

[0142] The semiconductor device A1 may be fixed to the control circuit board or the like by a method such as screwing. In this case, the inner wall surface 851c of the recess 851b of each first protrusion 851 may have a female screw thread. The inner wall surface 851c of the recess 851b of each first protrusion 851 may be configured so that the female screw thread can be formed thereon. The recess 851b of each first protrusion 851 may have an insert nut or the like embedded therein.

[0143] As shown in FIG. 12 and other figures, the multiple second protrusions 852 may protrude in the z direction from the resin main surface 81. The multiple second protrusions 852 may overlap the multiple control terminals 44 in a plan view. The metal pins 442 of the multiple control terminals 44 may protrude from the respective second protrusions 852. Each second protrusion 852 may be frustum-shaped. Each second protrusion 852 may cover the holder 441 and a portion of the metal pin 442 of each control terminal 44.

[0144] 11 , the resin voids 86 can communicate in the z direction from the resin main surface 81 to each main surface 201 of the first conductive portion 2A and the second conductive portion 2B. The resin voids 86 can have a tapered shape, and the cross-sectional area in a plane perpendicular to the z direction can decrease from the resin main surface 81 toward each main surface 201 in the z direction. The resin voids 86 are formed during molding of the resin member 8, and can be portions where the resin member 8 is not formed during molding.

[0145] Resin voids 86 can be formed, for example, when a presser member is present during molding of resin member 8 and prevents fluid resin material from filling the voids. The presser member applies a pressing force to each main surface 201 during molding, and is inserted into the recesses in each first wiring portion 721 of second conductive member 72. This allows the presser member to press support conductor 2 (first conductive portion 2A and second conductive portion 2B) without interfering with second conductive member 72, thereby reducing warping of support substrate 3 to which support conductor 2 is bonded.

[0146] 11 , the semiconductor device A1 includes a resin filling portion 88. The resin filling portion 88 can be filled into the resin void portion 86 so as to fill the resin void portion 86. The resin filling portion 88 can be made of, for example, an epoxy resin like the resin member 8, but may also be made of a resin material different from that of the resin member 8.

[0147] Next, a method for manufacturing the semiconductor device A1 will be described below with reference to FIGS.

[0148] First, the pressing molds M1a and M1b shown in Figures 23 and 24 are prepared. The pressing molds M1a and M1b may have multiple protrusions m1. The protrusions m1 may protrude toward the z1 side in the z direction. In the illustrated example, the pressing molds M1a and M1b may each have two protrusions m1. The two protrusions m1 are located apart from each other on the diagonal lines of the pressing molds M1a and M1b, respectively.

[0149] 24, a first intermediate bonding material 29a is placed on the first conductive portion 2A, and a first intermediate bonding material 29b is placed on the second conductive portion 2B. Then, a pressing die M1a can be placed on the first intermediate bonding material 29a, and a pressing die M1b can be placed on the first intermediate bonding material 29b.

[0150] Next, as shown in FIG. 25 , the first intermediate bonding material 29a is pressed toward the first conductive portion 2A by a pressing die M1a. The first intermediate bonding material 29b is pressed toward the second conductive portion 2B by a pressing die M1b. The pressure at the tip of the protrusion m1 due to these pressings can be the same (or approximately the same) as the pressure applied to the bonding surfaces in the solid-state bonding process described below. The ambient temperature during this pressing can be lower than the ambient temperature during the solid-state bonding process described below, for example, lower than the recrystallization temperature of Ag (silver), the material used in the solid-state bonding. By applying pressure using the pressing die M1a and pressing die M1b, a unique bonding region Pca can be formed as shown in FIG. 26 . In the figure, the portion of the first intermediate bonding material 29a pressed by the protrusion m1 is slightly recessed compared to the surrounding region, but this is just an example. In this embodiment, the unique bonding region Pca can be a region where a bonding similar to solid-state bonding has been achieved. This step may be the temporary bonding step of the present disclosure.

[0151] 23 to 25, for ease of understanding, the case where the temporary bonding of the first conductive portion 2A and the first intermediate bonding material 29a and the temporary bonding of the second conductive portion 2B and the first intermediate bonding material 29b are performed simultaneously is described, but this is not limiting. The temporary bonding may be performed at different times and / or at different locations.

[0152] Next, a joint formwork M2 is prepared as shown in Fig. 27. The joint formwork M2 can have a first recess m21, a second recess m22a, a third recess m22b, a fourth recess m23, a first through hole m24a, and a second through hole m24b.

[0153] The first recess m21 may be a portion recessed from the z2 side to the z1 side in the z direction. The first recess m21 may have a size and shape in a plan view that allows the support substrate 3 to be accommodated therein.

[0154] The second recess m22a is recessed from the bottom of the first recess m21 toward the z2 side in the z direction. The second recess m22a may have a size and shape in a planar view that can accommodate the first conductive portion 2A. The size of the second recess m22a in a planar view is smaller than the size of the support substrate 3 in a planar view. The depth of the second recess m22a in the z direction is smaller than the thickness of the first conductive portion 2A in the z direction. The third recess m22b may be recessed from the bottom of the first recess m21 toward the z2 side in the z direction. The third recess m22b may be aligned with the second recess m22a in the x direction. The third recess m22b may have a size and shape in a planar view that can accommodate the second conductive portion 2B. The size of the third recess m22b in a planar view is smaller than the size of the support substrate 3 in a planar view. The depth of the third recess m22b in the z direction is smaller than the thickness of the second conductive portion 2B in the z direction.

[0155] The fourth recess m23 may be recessed from the z1 side to the z2 side in the z direction. The fourth recess m23 may have a size and shape that overlaps with all of the first switching elements 1A and the second switching elements 1B of the semiconductor device A1 in a plan view.

[0156] The first through hole m24a ​​penetrates in the z direction and can reach the second recess m22a and the fourth recess m23. The first through hole m24a ​​has a size and shape that can accommodate the first switching element 1A. The first through hole m24a ​​is smaller than the first conductive portion 2A. The size of the first through hole m24a ​​in the z direction can be the same as (or approximately the same as) the combined thickness of the first switching element 1A in the z direction and the second intermediate bonding material 19a in the z direction. The number of first through holes m24a ​​can be the same as the number of first switching elements 1A.

[0157] The second through hole m24b penetrates in the z direction and reaches the third recess m22b and the fourth recess m23. The first through hole m24a ​​may have a size and shape capable of accommodating the second switching element 1B. The first through hole m24a ​​is smaller than the second conductive portion 2B. The size of the second through hole m24b in the z direction may be the same as (or approximately the same as) the combined thickness of the second switching element 1B in the z direction and the second intermediate bonding material 19b in the z direction. The number of second through holes m24b may be the same as the number of second switching elements 1B.

[0158] The first conductive portion 2A, to which the first intermediate bonding material 29a has been temporarily bonded, is placed in the second recess m22a. The second conductive portion 2B, to which the first intermediate bonding material 29b has been temporarily bonded, is placed in the third recess m22b. Next, the support substrate 3 is inserted into the first recess m21. As a result, the first portion 32A is placed on the first intermediate bonding material 29a, and the second portion 32B is placed on the first intermediate bonding material 29b.

[0159] Next, the bonding form M2, the first conductive portion 2A, the second conductive portion 2B, the first intermediate bonding material 29a, the first intermediate bonding material 29b, and the support substrate 3 placed on the bonding form M2 are all inverted in the z direction. Then, as shown in FIG. 28 , the second intermediate bonding material 19a and the first switching element 1A are placed in the first through hole m24a. At this time, it is preferable that the second intermediate bonding material 19a is fixed to the first switching element 1A in advance. However, this fixation does not have to be by solid-state bonding. The second intermediate bonding material 19b and the second switching element 1B are placed in the second through hole m24b. At this time, it is preferable that the second intermediate bonding material 19b is fixed to the second switching element 1B in advance. However, this fixation does not have to be by solid-state bonding.

[0160] Next, a pressing die M3 is brought closer in the z direction from the z1 side to the z2 side. Then, as shown in FIG. 29 , the pressing die M3 is pressed against the first switching element 1A, the second switching element 1B, and the bottom of the fourth recess m23 of the joining mold frame M2. At this time, the ambient temperature can be set to a temperature equal to or higher than the recrystallization temperature of Ag (silver), which is the material to be solid-state bonded. This allows the formation of a solid-state bonding interface, as described with reference to FIGS. 14 , 15 , 17 , and 18 . This can be considered as the solid-state bonding process of the present disclosure.

[0161] Thereafter, the signal substrate 5, the plurality of control terminals 44, the wires 73 to 76, the resin member 8, etc. are formed in order, thereby obtaining the semiconductor device A1.

[0162] Next, the operation of the semiconductor device A1 and the method for manufacturing the semiconductor device A1 will be described.

[0163] In this embodiment, as shown in FIG. 15 , the bond interface between the first conductive portion 2A and the first intermediate bonding material 29b may include a bond-specific region Pca. In this embodiment, as shown in FIG. 15 and FIG. 18 , the bond interface between the second conductive portion 2B and 29b may include a bond-specific region Pcb. These bond-specific regions Pca and Pcb may be regions formed by the temporary bonding step shown in FIG. 25 prior to the solid-state bonding step shown in FIG. 29 . Having the bond-specific region Pca and the bond-specific region Pcb reduces misalignment of the first intermediate bonding material 29a and the first intermediate bonding material 29b during the placement step shown in FIGS. 27 and 28 , which is a preparatory step for the solid-state bonding step. This allows the manufacturing method of the semiconductor device A1 of the present disclosure to perform solid-state bonding more appropriately and reliably.

[0164] Depending on the conditions of the temporary joining and solid-state joining, the joining condition of the junction-specific regions Pca and Pcb may be inferior to that of the surrounding regions. Alternatively, the joining condition of the junction-specific regions Pca and Pcb may be good but the joining condition of the regions adjacent to the junction-specific regions Pca and Pcb may be poor. As shown in FIG. 8 , the junction-specific regions Pca and Pcb may be located away from the first switching element 1A and the second switching element 1B in a planar view. This allows the heat dissipation of the first switching element 1A and the second switching element 1B to be appropriately maintained even if at least one of the joining condition of the junction-specific regions Pca and Pcb and the joining condition of the regions adjacent to the junction-specific regions Pca and Pcb is insufficient.

[0165] In the manufacturing method of semiconductor device A1, as shown in Fig. 27, the first conductive portion 2A and the second conductive portion 2B can be positioned by the second recess m22a and the third recess m22b, and the support substrate 3 can be positioned by the first recess m21. In the manufacturing method of semiconductor device A1, as shown in Fig. 28, the first switching element 1A and the semiconductor element 1b can be positioned by the first through hole m24a ​​and the second through hole m24b. Therefore, in the manufacturing method of semiconductor device A1, the position of each element can be more accurately finished in solid-state bonding.

[0166] 30 to 35 show modified examples and other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals. The configurations of the various parts in each modified example and each embodiment can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0167] 30 shows a first modified example of the semiconductor device A1. The semiconductor device A11 of this modified example differs from the semiconductor device A1 in the number of junction unique regions Pca and junction unique regions Pcb.

[0168] This modified example has four junction unique regions Pca and four junction unique regions Pcb. The four junction unique regions Pca can be located near the four corners of the first conductive portion 2A and the first portion 32A. The four junction unique regions Pcb can be located near the four corners of the second conductive portion 2B and the second portion 32B.

[0169] This modification enables the semiconductor device A1 to reduce misalignment between the first intermediate bonding materials 29 a and 29 b. As can be understood from this modification, the number and positions of the bond unique regions Pca and Pcb are not limited in any way.

[0170] 31 and 32 show a semiconductor device A2 according to a second embodiment of the present disclosure. In the semiconductor device A2 of this embodiment, the positions of the junction unique region Pca and the junction unique region Pcb are different from those of the semiconductor device A1.

[0171] As shown in Figure 31, in this embodiment, the bonding interface between the second surface layer 292a of the first intermediate bonding material 29a and the second bonding layer 321A of the first portion 32A includes a bonding unique region Pca, and the bonding interface between the first surface layer 291a of the first intermediate bonding material 29a and the first bonding layer 22A of the first conductive portion 2A does not include the bonding unique region Pca.

[0172] As shown in Figure 32, in this embodiment, the bonding interface between the second surface layer 292b of the first intermediate bonding material 29b and the second bonding layer 321B of the second portion 32B includes a bonding unique region Pcb, and the bonding interface between the first surface layer 291b of the first intermediate bonding material 29a and the first bonding layer 22B of the second conductive portion 2B does not include the bonding unique region Pcb.

[0173] 33 to 35 show an example of a manufacturing method for the semiconductor device A2. In this embodiment, as shown in FIG. 33, a first intermediate bonding material 29a may be placed on the first portion 32A of the support substrate 3, and a first intermediate bonding material 29b may be placed on the second portion 32B. The pressing die M1 may be, for example, a combination of the pressing die M1a and pressing die M1b in the above-described embodiment. The pressing die M1 may be moved from the z2 side to the z1 side in the z direction and placed on the first intermediate bonding material 29a and first intermediate bonding material 29b.

[0174] Then, as shown in Fig. 34 , the first intermediate bonding material 29a and the first intermediate bonding material 29b may be pressed by a pressing die M1. The pressure and atmospheric temperature at this time may be the same as those in the temporary bonding process described with reference to Fig. 25 . By the temporary bonding process shown in Fig. 34 , a bond unique region Pca may be formed at the interface between the first intermediate bonding material 29a and the first portion 32A, and a bond unique region Pcb may be formed at the interface between the first intermediate bonding material 29b and the second portion 32B.

[0175] 35 , the first conductive portion 2A is placed in the second recess m22a of the bonding formwork M2, and the second conductive portion 2B is placed in the third recess m22b. Next, the support substrate 3 to which the first intermediate bonding material 29a and the first intermediate bonding material 29b are temporarily bonded is placed in the first recess m21. As a result, the first intermediate bonding material 29a is placed on the first conductive portion 2A, and the first intermediate bonding material 29b is placed on the second conductive portion 2B.

[0176] Thereafter, solid-state bonding is carried out in the same manner as described with reference to Fig. 29. As a result, the semiconductor device A2 is obtained.

[0177] According to this embodiment, the manufacturing method of the semiconductor device A2 can reduce misalignment of the first intermediate bonding material 29 a and the first intermediate bonding material 29 b. As can be understood from this embodiment, the bond unique region Pca and the bond unique region Pcb may be located on either side of the first intermediate bonding material 29 a and the first intermediate bonding material 29 b. However, when the semiconductor devices A1 and A2 are manufactured using the above-described manufacturing method, the bond unique region Pca and the bond unique region Pcb may be formed on only one side of the first intermediate bonding material 29 a and the first intermediate bonding material 29 b in the z direction.

[0178] The semiconductor and semiconductor device manufacturing method according to the present disclosure are not limited to the above-described embodiments. The specific configuration of the semiconductor and semiconductor device manufacturing method according to the present disclosure can be freely modified in various ways. The present disclosure includes the embodiments described in the following appendices.

[0179] Supplementary Note 1. A semiconductor device comprising: a semiconductor element; a support conductor supporting the semiconductor element; a support substrate supporting the support conductor; and a first intermediate bonding material interposed between the support conductor and the support substrate, wherein the bonding between the support conductor and the first intermediate bonding material and the bonding between the support substrate and the first intermediate bonding material are both solid-state bonding, and either the bonding interface between the support conductor and the first intermediate bonding material or the bonding interface between the support substrate and the first intermediate bonding material includes a bonding-specific region that differs in bonding state from surrounding areas. Supplementary Note 2. The semiconductor device according to Supplementary Note 1, wherein the bonding interface between the support conductor and the first intermediate bonding material includes the bonding-specific region. Supplementary Note 3. The semiconductor device according to Supplementary Note 1, wherein the bonding interface between the support substrate and the first intermediate bonding material includes the bonding-specific region. Supplementary Note 4. The semiconductor device according to any of Supplements 1 to 3, wherein the first intermediate bonding material includes a base layer, a first surface layer interposed between the base layer and the support conductor, and a second surface layer interposed between the base layer and the support substrate. Appendix 5. The semiconductor device according to Appendix 4, wherein the support conductor includes a main body layer and a first bonding layer interposed between the main body layer and the first intermediate bonding material, and the first bonding layer and the first surface layer are solid-state bonded together. Appendix 6. The semiconductor device according to Appendix 5, wherein the first bonding layer and the first surface layer are primarily composed of Ag. Appendix 7. The semiconductor device according to Appendix 5 or 6, wherein the support substrate includes a first metal layer and a second bonding layer interposed between the first metal layer and the first intermediate bonding material, and the second bonding layer and the second surface layer are solid-state bonded together. Appendix 8. The semiconductor device according to Appendix 7, wherein the second bonding layer and the second surface layer are primarily composed of Ag. Appendix 9. The semiconductor device according to any one of Appendixes 5 to 8, wherein the main body layer is primarily composed of Al. Appendix 10. The semiconductor device according to any one of Appendixes 5 to 8, wherein the main body layer is primarily composed of Cu. Appendix 11. The semiconductor device according to claim 7, wherein the first metal layer is primarily composed of Cu. The semiconductor device according to claim 7, wherein the support substrate has an insulating layer to which the first metal layer is bonded, and a second metal layer bonded to the insulating layer on the opposite side from the first metal layer.Appendix 13. The semiconductor device according to Appendix 12, wherein the insulating layer is primarily composed of ceramic. Appendix 14. The semiconductor device according to Appendix 12 or 13, wherein the second metal layer is primarily composed of Cu. Appendix 15. The semiconductor device according to any one of Appendixes 1 to 14, further comprising a second intermediate bonding material interposed between the semiconductor element and the support conductor, wherein the bonding between the semiconductor element and the second intermediate bonding material and the bonding between the support conductor and the second intermediate bonding material are solid-state bonding. Appendix 16. A method for manufacturing a semiconductor device, comprising: a step of temporarily bonding a first intermediate bonding material to one of the support conductor and the support substrate by applying pressure; and a step of applying pressure with the first intermediate bonding material sandwiched between the support conductor and the support substrate, thereby solid-state bonding the first intermediate bonding material to the support conductor and solid-state bonding the first intermediate bonding material to the support substrate. Appendix 17. Attachment 17. The method for manufacturing a semiconductor device according to claim 16, wherein the first intermediate bonding material and the support conductor are temporarily bonded in the temporary bonding step. Attachment 18. The method for manufacturing a semiconductor device according to claim 16, wherein the first intermediate bonding material and the support substrate are temporarily bonded in the temporary bonding step.

[0180] A1, A11, A2: semiconductor device 1: semiconductor element 1A: first switching element 1B: second switching element 1b: semiconductor element 2: supporting conductor 2A: first conductive portion 2B: second conductive portion 3: supporting substrate 5: signal substrate 5A: first signal substrate 5B: second signal substrate 6: adhesive layer 6A: first adhesive body 6B: second adhesive body 8: resin member 10a: element main surface 10b: element back surface 11: first main surface electrode 12: second main surface electrode 13: third main surface electrode 15: back surface electrode 17: thermistor 19a, 19b: second intermediate bonding material 20A, 20B: main body layer 21A, 21B: third bonding layer 22A, 22B: first bonding layer 29a, 29b: first intermediate bonding material 31: insulating layer 32: first metal layer 32A: First portion 32B: Second portion 33: Second metal layer 41, 42, 43: Power terminal 44: Control terminal 45: First control terminal 45A: First drive terminal 45B, 45C, 45D, 45E: First detection terminal 46: Second control terminal 46A: Second drive terminal 46B, 46C, 46D, 46E: Second detection terminal 51: Insulating substrate 51a: Main surface 51b: Back surface 52: First metal layer 53: Second metal layer 61: Insulating layer 61a: Main surface 61b: Back surface 62, 63: Adhesive layers 71: First conductive member 72: Second conductive member 73, 74, 75, 76: Wire 81: Resin main surface 82: Resin back surface 86: Resin void portion 88: Resin filled portion 151: Fourth bonding layer 190a, 190b: Base material layer 191a, 191b: Third surface layer 192a, 192b: Fourth surface layer 201: Main surface 202: Back surface 290a, 290b: Base material layer 291a, 291b: First surface layer 292a, 292b: Second surface layer 321A, 321B: Second bonding layer 441: Holder 442: Metal pin 449: Conductive bonding material 521, 522, 523, 524, 525,526: Wiring layer 711: Main portion 711a: Opening 712: First connection end portion 712a: Opening 713: Second connection end portion 719: Conductive bonding material 721: First wiring portion 721a: First end portion 722: Second wiring portion 722a: Recessed region 723: Third wiring portion 724: Fourth wiring portion 729: Conductive bonding material 831, 832: Resin side surface 832a: Recessed portion 833: Resin side surface 834: Resin side surface 851: First protrusion portion 851a: First protrusion end surface 851b: Recessed portion 851c: Inner wall surface 852: Second protrusion portion M1, M1a, M1b: Pressing mold M2: Joining formwork M3: Pressing mold Pca, Pcb: Joint unique region m1: Protrusion m21: First recess m22a: Second recess m22b: Third recess m23: Fourth recess m24a: First through hole m24b: Second through hole

Claims

1. A semiconductor element; A support conductor for supporting the semiconductor element; A support substrate supporting the support conductor; a first intermediate bonding material interposed between the supporting conductor and the supporting substrate; The bonding between the supporting conductor and the first intermediate bonding material, and the bonding between the supporting substrate and the first intermediate bonding material are both solid-state bonding, A semiconductor device, wherein either the bonding interface between the support conductor and the first intermediate bonding material or the bonding interface between the support substrate and the first intermediate bonding material includes a bonding unique region that has a bonding state different from that of surrounding areas.

2. The semiconductor device according to claim 1 , wherein a bonding interface between the supporting conductor and the first intermediate bonding material includes the bonding unique region.

3. The semiconductor device according to claim 1 , wherein a bonding interface between the support substrate and the first intermediate bonding material includes the bonding unique region.

4. 4. The semiconductor device according to claim 1, wherein the first intermediate bonding material includes a base material layer, a first surface layer interposed between the base material layer and the support conductor, and a second surface layer interposed between the base material layer and the support substrate.

5. The supporting conductor includes a main body layer and a first bonding layer interposed between the main body layer and the first intermediate bonding material, The semiconductor device according to claim 4 , wherein the first bonding layer and the first surface layer are solid-state bonded together.

6. The semiconductor device described in Claim 5, wherein the first bonding layer and the first surface layer are primarily composed of Ag.

7. the supporting substrate includes a first metal layer and a second bonding layer interposed between the first metal layer and the first intermediate bonding material, The semiconductor device according to claim 5 , wherein the second bonding layer and the second surface layer are solid-state bonded together.

8. The semiconductor device described in Claim 7, wherein the second bonding layer and the second surface layer are primarily composed of Ag.

9. The semiconductor device according to claim 5 , wherein the main body layer is mainly composed of Al.

10. The semiconductor device according to claim 5 , wherein the main body layer is mainly composed of Cu.

11. The semiconductor device according to claim 7 , wherein the first metal layer is mainly composed of Cu.

12. 8. The semiconductor device according to claim 7, wherein the support substrate has an insulating layer to which the first metal layer is bonded, and a second metal layer bonded to a side of the insulating layer opposite to the first metal layer.

13. The semiconductor device according to claim 12 , wherein the insulating layer is mainly made of ceramics.

14. The semiconductor device according to claim 12 , wherein the second metal layer is mainly composed of Cu.

15. A second intermediate bonding material is provided between the semiconductor element and the supporting conductor. The semiconductor device according to claim 1 , wherein the semiconductor element and the second intermediate bonding material, and the supporting conductor and the second intermediate bonding material are bonded by solid-state bonding.

16. a step of temporarily bonding a first intermediate bonding material to either the supporting conductor or the supporting substrate by applying pressure; a step of applying pressure to the first intermediate bonding material while it is sandwiched between the supporting conductor and the supporting substrate, thereby solid-state bonding the first intermediate bonding material and the supporting conductor, and solid-state bonding the first intermediate bonding material and the supporting substrate.

17. The method for manufacturing a semiconductor device according to claim 16 , wherein in the temporarily joining step, the first intermediate bonding material and the supporting conductor are temporarily joined.

18. The method for manufacturing a semiconductor device according to claim 16 , wherein in the temporary bonding step, the first intermediate bonding material and the support substrate are temporarily bonded together.