Sic semiconductor device

Abstract

This SiC semiconductor device comprises: a first SiC layer; a second SiC layer stacked on the Sic first SiC layer; a p-type first impurity region formed in the first SiC layer; a p-type second impurity region formed in the second SiC layer; a plurality of n-type first inversion columns formed at intervals in the first SiC layer so as to invert the conductivity type of the first impurity region; and a plurality of n-type second inversion columns formed at intervals in the second SiC layer so as to invert the conductivity type of the second impurity region.

Description

SiC semiconductor device

[0001] This application claims priority to Patent Application No. 2022-212616 filed with the Japan Patent Office on December 28, 2022, the entire contents of which are incorporated herein by reference. The present disclosure relates to a SiC semiconductor device.

[0002] Patent Document 1 (US2015 / 0028351A1) discloses an electronic device having an impurity region introduced into a silicon carbide layer by channeling implantation.

[0003] US Patent Application Publication No. 2015-0028351

[0004] SUMMARY The present disclosure provides a novel SiC semiconductor device.

[0005] The present disclosure provides a SiC semiconductor device including a first SiC layer, a second SiC layer stacked on the first SiC layer, a first p-type impurity region formed in the first SiC layer, a second p-type impurity region formed in the second SiC layer, a plurality of first n-type inversion columns formed at intervals in the first SiC layer to invert the conductivity type of the first impurity region, and a plurality of second n-type inversion columns formed at intervals in the second SiC layer to invert the conductivity type of the second impurity region.

[0006] The present disclosure provides a SiC semiconductor device including a first SiC layer, an n-type second SiC layer stacked on the first SiC layer, a p-type impurity region formed in the first SiC layer, a plurality of n-type first inversion columns formed at intervals in the first SiC layer to invert the conductivity type of the impurity region, and a plurality of p-type second inversion columns formed at intervals in the second SiC layer to invert the conductivity type of the second SiC layer.

[0007] The present disclosure provides a SiC semiconductor device including: a first n-type SiC layer; a second SiC layer stacked on the first SiC layer; a p-type impurity region formed in the second SiC layer; a plurality of first p-type inversion columns formed at intervals in the first SiC layer to invert the conductivity type of the first SiC layer; and a plurality of second n-type inversion columns formed at intervals in the second SiC layer to invert the conductivity type of the impurity region.

[0008] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a plan view showing a SiC semiconductor device according to a first embodiment. FIG. 2A is a cross-sectional view taken along line IIA-IIA in FIG. 1 . FIG. 2B is a cross-sectional view taken along line IIB-IIB in FIG. 1 . FIG. 3A is a plan view showing an example layout of a chip (first layer). FIG. 3B is a plan view showing an example layout of a chip (second layer). FIG. 4 is a perspective view showing an example layout of a chip. FIG. 5 is a cross-sectional perspective view showing a first basic embodiment of an inverted column. FIG. 6A is a graph showing an example concentration gradient of a second impurity region. FIG. 6B is a graph showing an example concentration gradient of a second impurity region. FIG. 6C is a graph showing an example concentration gradient of a second impurity region. FIG. 6D is a graph showing an example concentration gradient of a second impurity region. FIG. 6E is a graph showing an example concentration gradient of a second impurity region. FIG. 7 is a graph showing a comparative example of the concentration gradient of the second impurity region. FIG. 8A is a plan view showing a first layout example of the first basic embodiment. FIG. 8B is a plan view showing a second layout example of the first basic embodiment. FIG. 9 is a cross-sectional perspective view showing a second basic form of an inversion column. FIG. 10A is a plan view showing a first layout example of the second basic form. FIG. 10B is a plan view showing a second layout example of the second basic form. FIG. 11 is a cross-sectional perspective view showing a third basic form of an inversion column. FIG. 12A is a plan view showing a first layout example of the third basic form. FIG. 12B is a plan view showing a second layout example of the third basic form. FIG. 12C is a plan view showing a third layout example of the third basic form. FIG. 13A is a cross-sectional perspective view showing an inversion column according to the first basic form. FIG. 13B is a cross-sectional perspective view showing an inversion column according to the second basic form. FIG. 13C is a cross-sectional perspective view showing an inversion column according to the third basic form. FIG. 13D is a cross-sectional perspective view showing an inversion column according to the fourth basic form. FIG. 13E is a cross-sectional perspective view showing an inversion column according to the fifth basic form. FIG. 13F is a cross-sectional perspective view showing an inversion column according to the sixth basic form. FIG. 14 is a plan view showing a main portion of an active region. Fig. 15 is a cross-sectional perspective view showing a gate structure according to a first embodiment. Fig. 16 is a perspective view showing a configuration of the outer periphery region. Fig. 17A is a cross-sectional view showing a main part of the outer periphery region. Fig. 17B is a cross-sectional view showing a main part of the outer periphery region. Fig. 18 is a cross-sectional perspective view showing a gate structure according to a second embodiment.FIG. 19 is a schematic diagram showing a wafer used in manufacturing a SiC semiconductor device. FIG. 20 is a flowchart showing an example of a method for manufacturing a SiC semiconductor device. FIG. 21A is a cross-sectional perspective view showing an example of a method for manufacturing a SiC semiconductor device. FIG. 21B is a cross-sectional perspective view showing a step subsequent to FIG. 21A. FIG. 21C is a cross-sectional perspective view showing a step subsequent to FIG. 21B. FIG. 21D is a cross-sectional perspective view showing a step subsequent to FIG. 21C. FIG. 21E is a cross-sectional perspective view showing a step subsequent to FIG. 21D. FIG. 21F is a cross-sectional perspective view showing a step subsequent to FIG. 21E. FIG. 21G is a cross-sectional perspective view showing a step subsequent to FIG. 21F. FIG. 21H is a cross-sectional perspective view showing a step subsequent to FIG. 21G. FIG. 21I is a cross-sectional perspective view showing a step subsequent to FIG. 21H. FIG. 21J is a cross-sectional perspective view showing a step subsequent to FIG. 21I. FIG. 22A is a schematic view for explaining a crystal orientation measurement step. FIG. 22B is a schematic view for explaining a crystal orientation measurement step. FIG. 23A is a schematic view for explaining an ion implantation step. 23B is a schematic diagram for explaining an ion implantation step. FIG. 24 is a plan view showing a SiC semiconductor device according to a second embodiment. FIG. 25A is a cross-sectional view taken along line XXVA-XXVA shown in FIG. 24. FIG. 25B is a cross-sectional view taken along line XXVB-XXVB shown in FIG. 24. FIG. 26A is a plan view showing an example layout of a chip (first layer). FIG. 26B is a plan view showing an example layout of a chip (second layer). FIG. 27 is a perspective view showing an example layout of a chip. FIG. 28 is a plan view showing a main part of an active region. FIG. 29 is a cross-sectional perspective view showing a gate structure according to a first embodiment. FIG. 30 is a perspective view showing a configuration of a peripheral region. FIG. 31A is a cross-sectional view showing a main part of the peripheral region. FIG. 31B is a cross-sectional view showing a main part of the peripheral region. FIG. 32 is a cross-sectional perspective view showing a gate structure according to a second embodiment. FIG. 33 is a cross-sectional perspective view showing a gate structure according to a third embodiment. FIG. 34 is a cross-sectional perspective view showing a gate structure according to a fourth embodiment. Fig. 35 is a cross-sectional perspective view showing a gate structure according to a fifth embodiment. Fig. 36 is a plan view showing a SiC semiconductor device according to a third embodiment. Fig. 37A is a cross-sectional view taken along line XXXVIIA-XXXVIIA shown in Fig. 36. Fig. 37B is a cross-sectional view taken along line XXXVIIB-XXXVIIB shown in Fig. 36.FIG. 38A is a plan view showing an example of a chip layout. FIG. 38B is a plan view showing an example of a chip layout. FIG. 39 is a perspective view showing an example of a chip layout. FIG. 40 is a perspective view showing a configuration of an outer periphery region. FIG. 41 is a cross-sectional perspective view showing a diode structure according to a first embodiment. FIG. 42 is a cross-sectional perspective view showing a diode structure according to a second embodiment. FIG. 43 is a cross-sectional perspective view showing a diode structure according to a third embodiment. FIG. 44 is a cross-sectional perspective view showing a diode structure according to a fourth embodiment. FIG. 45 is a cross-sectional perspective view showing a diode structure according to a fifth embodiment. FIG. 46 is a cross-sectional perspective view showing an inversion column according to a first modified example. FIG. 47 is a cross-sectional perspective view showing an inversion column according to a second modified example. FIG. 48 is a cross-sectional perspective view showing an inversion column according to a third modified example. FIG. 49 is a cross-sectional perspective view showing an inversion column according to a fourth modified example.

[0010] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0011] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0012] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0013] FIG. 1 is a plan view showing a SiC semiconductor device 1A according to a first embodiment. FIG. 2A is a cross-sectional view taken along line IIA-IIA in FIG. 1. FIG. 2B is a cross-sectional view taken along line IIB-IIB in FIG. 1. FIG. 3A is a plan view showing an example layout of a chip 2 (first layer 8). FIG. 3B is a plan view showing an example layout of a chip 2 (second layer 9). FIG. 4 is a perspective view showing an example layout of the chip 2. FIG. 5 is a cross-sectional perspective view showing a first basic embodiment of a first inverting column 14 and a second inverting column 16.

[0014] 1 to 5, SiC semiconductor device 1A includes chip 2 including SiC single crystal. Chip 2 may be referred to as a "SiC chip" or a "semiconductor chip." In this embodiment, chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which chip 2 is made of 4H-SiC single crystal, but chip 2 may be made of another polytype.

[0015] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0016] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0017] In the circumferential direction of the chip 2 (clockwise in FIG. 1 ) starting from the first side surface 5A, the second side surface 5B is connected to the first side surface 5A, the third side surface 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0018] In this embodiment, the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal, and the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal. That is, the first side surface 5A and the third side surface 5C are each formed by the m-plane ((1-100) plane) of the SiC single crystal. The second side surface 5B and the fourth side surface 5D are each formed by the a-plane ((11-20) plane) of the SiC single crystal.

[0019] The a-plane is a crystal plane perpendicular to the a-axis direction, and the m-plane is a crystal plane perpendicular to the m-axis direction. Of course, the first direction X may be the m-axis direction of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. The first to fourth side surfaces 5A to 5D may each be a ground surface. The first to fourth side surfaces 5A to 5D may each be a cleavage plane.

[0020] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, an axis extending along the vertical direction Z may be referred to as a "vertical axis." Also, below, the first direction X and the second direction Y may be referred to as a "horizontal direction." The horizontal direction is also a direction extending along the first main surface 3.

[0021] 4, the chip 2 (first main surface 3 and second main surface 4) has an off angle θoff inclined at a predetermined angle in a predetermined off direction Doff with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off direction Doff by the off angle θoff. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off angle θoff.

[0022] The off-direction Doff is preferably the a-axis direction of the SiC single crystal (i.e., the first direction X). The off-angle θoff may be greater than 0° and less than or equal to 10°. The off-angle θoff may have a value belonging to any one of the ranges of greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.

[0023] The off angle θ is preferably 5° or less. The off angle θ is particularly preferably 2° or more and 4.5° or less. The off angle θ is typically set in the range of 4°±0.1°. Of course, this specification does not exclude a configuration in which the off angle θ is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0024] The chip 2 includes an n-type base layer 6 made of SiC single crystal. The base layer 6 may also be referred to as a "base SiC layer," a "base region," or the like. The base layer 6 extends horizontally in a layered manner and forms part of the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the base layer 6 is made of a substrate made of SiC single crystal (i.e., a SiC substrate). The base layer 6 has the off direction Doff and off angle θoff described above.

[0025] The base layer 6 has a base axis channel CHB along the stacking direction. The base axis channel CHB is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the base layer 6, and is surrounded by atomic rows constituting a crystal axis extending in the stacking direction (crystal growth direction).

[0026] In other words, the base axis channel CHB is a region in which a region with sparse atomic rows extends in the stacking direction and in which the atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in a planar view. The base axis channel CHB is preferably a region surrounded by atomic rows along low-index crystal axes among the crystal axes. The low-index crystal axes are crystal axes in which the absolute values ​​of "a1," "a2," "a3," and "c" are all expressed as 2 or less (preferably 1 or less) with respect to the Miller indices (a1, a2, a3, c) (the same applies hereinafter in this specification).

[0027] In this embodiment, the base axis channel CHB is formed by a region surrounded by atomic rows aligned along the c-axis ((0001) axis) of the SiC single crystal. That is, the base axis channel CHB extends along the c-axis and has the off-direction Doff and off-angle θoff described above. In other words, the base axis channel CHB is inclined from the vertical axis toward the off-direction Doff by the off-angle θoff.

[0028] The base layer 6 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration of the base layer 6 may have the following peak value. The base layer 6 preferably has an almost constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the base layer 6 is preferably adjusted with a single pentavalent element. It is particularly preferable that the n-type impurity concentration of the base layer 6 is adjusted with a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the base layer 6 is adjusted with nitrogen.

[0029] The base layer 6 has a base thickness TB. The base thickness TB may be 5 μm or more and 300 μm or less. The base thickness TB may have a value belonging to any one of the following ranges: 5 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or more and 300 μm or less. The base thickness TB is preferably 50 μm or more and 250 μm or less.

[0030] The chip 2 includes a stacked layer 7 stacked on a base layer 6. The stacked layer 7 may be referred to as a "semiconductor layer," a "SiC layer," a "SiC stacked layer," a "semiconductor stacked layer," or the like. The stacked layer 7 has a stacked structure in which multiple (two or more) semiconductor layers made of SiC single crystal are stacked. In this embodiment, the multiple semiconductor layers are provided as layers for forming a superjunction structure SJ. The number of stacked multiple semiconductor layers (superjunction structure SJ) is arbitrary and is adjusted appropriately depending on the electrical characteristics to be achieved. Examples of electrical characteristics include a breakdown voltage and a resistance value.

[0031] The number of stacked semiconductor layers (super junction structure SJ) is typically 2 to 5 (two, three, four, or five). In this embodiment, stacked portion 7 has a two-layer structure including an n-type first layer 8 made of SiC single crystal and an n-type second layer 9 made of SiC single crystal. First layer 8 may be referred to as a "first SiC layer," a "first semiconductor layer," or the like. Second layer 9 may be referred to as a "second SiC layer," a "second semiconductor layer," or the like.

[0032] The first layer 8 is laminated on the base layer 6. The first layer 8 extends horizontally in a layered manner and forms the middle portion of the chip 2 and parts of the first to fourth side surfaces 5A to 5D. The first layer 8 is made of an epitaxial layer (i.e., a SiC epitaxial layer) grown from the base layer 6 as a starting point.

[0033] The first layer 8 has a lower end and an upper end. The lower end of the first layer 8 is the starting point of crystal growth, and the upper end of the first layer 8 is the end point of crystal growth. Because the first layer 8 is grown continuously from the base layer 6, the lower end of the first layer 8 coincides with the upper end of the base layer 6. The boundary between the base layer 6 and the first layer 8 is not necessarily visible and can be indirectly evaluated and / or determined from other configurations or elements. The first layer 8 has an off-direction Doff and an off-angle θoff that are approximately the same as the off-direction Doff and off-angle θoff of the base layer 6.

[0034] The first layer 8 has a first axis channel CH1 along the stacking direction. The first axis channel CH1 is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the first layer 8, and is surrounded by atomic rows along a crystal axis extending in the stacking direction (crystal growth direction).

[0035] In other words, the first axis channel CH1 is a region in which a region in which atomic rows are sparse extends in the stacking direction and in which atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in a plan view. The first axis channel CH1 is preferably a region surrounded by atomic rows along a low-index crystal axis among the crystal axes.

[0036] In this embodiment, the first axis channel CH1 is formed by a region surrounded by atomic rows along the c-axis of the SiC single crystal. That is, the first axis channel CH1 extends along the c-axis and has an off-direction Doff and an off-angle θoff. In other words, the first axis channel CH1 is inclined by the off-angle θoff from the vertical axis toward the off-direction Doff.

[0037] The n-type impurity concentration of the first layer 8 is preferably lower than the n-type impurity concentration of the base layer 6. The first layer 8 has a n-type impurity concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the first layer 8 may have a peak value of the following: The n-type impurity concentration of the first layer 8 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the first layer 8 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0038] In this embodiment, the n-type impurity concentration of the first layer 8 is adjusted by nitrogen. The first layer 8 may have an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the first layer 8 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0039] The first layer 8 preferably contains a pentavalent element other than phosphorus. In this case, the n-type impurity concentration of the first layer 8 is preferably adjusted by at least nitrogen. When the first layer 8 contains two or more pentavalent elements, the first layer 8 preferably contains nitrogen and a pentavalent element other than nitrogen. In this case, the first layer 8 preferably contains either arsenic or antimony, or both, as the pentavalent element other than phosphorus and nitrogen.

[0040] The first layer 8 has a first thickness T1. The first thickness T1 is preferably less than the base thickness TB. The first thickness T1 is preferably 1 μm or greater. The first thickness T1 is preferably 5 μm or less. The first thickness T1 may have a value belonging to any one of the following ranges: 1 μm or greater to 1.5 μm or less, 1.5 μm or greater to 2 μm or less, 2 μm or greater to 2.5 μm or less, 2.5 μm or greater to 3 μm or less, 3 μm or greater to 3.5 μm or less, 3.5 μm or greater to 4 μm or less, 4 μm or greater to 4.5 μm or less, and 4.5 μm or greater to 5 μm or less.

[0041] The second layer 9 is stacked on the first layer 8. The second layer 9 extends horizontally in a layered manner, forming the first main surface 3 and forming parts of the first to fourth side surfaces 5A to 5D. The second layer 9 is made of an epitaxial layer (i.e., a SiC epitaxial layer) crystal-grown starting from the first layer 8.

[0042] The second layer 9 has a lower end and an upper end. The lower end of the second layer 9 is the starting point of crystal growth, and the upper end of the second layer 9 is the end point of crystal growth. Because the second layer 9 is grown continuously from the first layer 8, the lower end of the second layer 9 coincides with the upper end of the first layer 8. The boundary between the first layer 8 and the second layer 9 is not necessarily visible and can be indirectly evaluated and / or determined from other configurations or elements. The second layer 9 has an off-direction Doff and an off-angle θoff that are substantially identical to the off-direction Doff and off-angle θoff of the first layer 8.

[0043] The second layer 9 has a second axis channel CH2 extending along the stacking direction. The second axis channel CH2 is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the second layer 9, and is surrounded by atomic rows along a crystal axis extending in the stacking direction (crystal growth direction).

[0044] In other words, the second axis channel CH2 is a region in which a region in which atomic rows are sparse extends in the stacking direction and in which atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in a plan view. The second axis channel CH2 is preferably a region surrounded by atomic rows along a low-index crystal axis among the crystal axes.

[0045] In this embodiment, the second axis channel CH2 is formed by a region surrounded by atomic rows along the c-axis of the SiC single crystal. That is, the second axis channel CH2 extends along the c-axis and has an off-direction Doff and an off-angle θoff. In other words, the second axis channel CH2 is inclined by the off-angle θoff from the vertical axis toward the off-direction Doff.

[0046] The n-type impurity concentration of the second layer 9 is preferably lower than the n-type impurity concentration of the base layer 6. The second layer 9 has an n-type impurity concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the second layer 9 may have a peak value of the following: The n-type impurity concentration of the second layer 9 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the second layer 9 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0047] The n-type impurity concentration of the second layer 9 is preferably approximately equal to the n-type impurity concentration of the first layer 8. Of course, the n-type impurity concentration of the second layer 9 may be different from the n-type impurity concentration of the first layer 8. In this case, the n-type impurity concentration (peak value) of the second layer 9 may be higher than the n-type impurity concentration (peak value) of the first layer 8, or may be lower than the n-type impurity concentration (peak value) of the first layer 8.

[0048] In this embodiment, the n-type impurity concentration of the second layer 9 is adjusted by nitrogen. The second layer 9 may have an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the second layer 9 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0049] The second layer 9 preferably contains a pentavalent element other than phosphorus. In this case, the n-type impurity concentration of the second layer 9 is preferably adjusted by at least nitrogen. When the second layer 9 contains two or more pentavalent elements, the second layer 9 preferably contains nitrogen and a pentavalent element other than nitrogen. In this case, the second layer 9 preferably contains either arsenic or antimony, or both, as the pentavalent element other than phosphorus and nitrogen.

[0050] The second layer 9 has a second thickness T2. The second thickness T2 is preferably less than the base thickness TB. The second thickness T2 may be approximately equal to the first thickness T1 or may be different from the first thickness T1. The second thickness T2 may be greater than the first thickness T1 or less than the first thickness T1.

[0051] The second thickness T2 is preferably 1 μm or more. The second thickness T2 is preferably 5 μm or less. The second thickness T2 may have a value belonging to any one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0052] The SiC semiconductor device 1A includes an active region 10 set in a chip 2. The active region 10 is set in an inner portion of the chip 2 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 10 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The planar area of ​​the active region 10 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0053] The SiC semiconductor device 1A includes a peripheral region 11 set outside the active region 10 in the chip 2. The peripheral region 11 is provided in a region between the periphery of the chip 2 and the active region 10 in a planar view. The peripheral region 11 extends in a band shape along the active region 10 in a planar view, and is set in a polygonal ring shape (a square ring shape in this embodiment) surrounding the active region 10.

[0054] 5 , SiC semiconductor device 1A includes a p-type first impurity region 12 formed in first layer 8 at least in a portion located in active region 10. In this embodiment, first impurity region 12 is drawn from active region 10 to peripheral region 11. That is, first impurity region 12 is drawn from a portion of first layer 8 located in active region 10 to a portion of first layer 8 located in peripheral region 11.

[0055] Furthermore, first impurity region 12 extends from peripheral region 11 toward first to fourth side surfaces 5A to 5D and is exposed from first to fourth side surfaces 5A to 5D. Of course, first impurity region 12 may be formed in first layer 8 at a distance inward from first to fourth side surfaces 5A to 5D. In this case, the peripheral portion of first impurity region 12 may be located within active region 10 or may be located within peripheral region 11.

[0056] The first impurity region 12 is a region that inverts the conductivity type of the first layer 8 from n-type to p-type. That is, the first impurity region 12 contains a trivalent element in addition to the pentavalent element that constitutes the conductivity type of the first layer 8. The p-type impurity concentration of the first impurity region 12 is higher than the n-type impurity concentration of the first layer 8. The first impurity region 12 has a concentration of 1×10 １５ cm －３ 1x10 or more １８cm －３ The p-type impurity concentration may have the following peak value:

[0057] The p-type impurity concentration of the first impurity region 12 is preferably adjusted by at least one trivalent element. It is particularly preferable that the p-type impurity concentration of the first impurity region 12 is adjusted by a trivalent element that is heavier than carbon. In other words, the first impurity region 12 preferably contains a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the p-type impurity concentration of the first impurity region 12 is adjusted by aluminum.

[0058] The first impurity region 12 is a p-type channeling region that extends along the first axial channel CH1 in the first layer 8 in a cross-sectional view. That is, the first impurity region 12 is an impurity region that is introduced parallel or substantially parallel to a region (first axial channel CH1) that is surrounded by atomic rows along the low-index crystal axis in the first layer 8, and extends at an angle with respect to the first main surface 3.

[0059] Therefore, the first impurity region 12 has an off direction Doff and an off angle θoff that are substantially identical to the off direction Doff and the off angle θoff of the first axial channel CH1. In other words, the first impurity region 12 is inclined from the vertical axis toward the off direction Doff by the off angle θoff.

[0060] The first impurity region 12 has a lower end located on the lower end side of the first layer 8 and an upper end located on the upper end side of the first layer 8. In this embodiment, the lower end of the first impurity region 12 is located in a region on the lower end side of the first layer 8 with respect to the intermediate portion of the thickness range of the first layer 8, and the upper end of the first impurity region 12 is located in a region on the upper end side of the first layer 8 with respect to the intermediate portion of the thickness range of the first layer 8. In other words, the first impurity region 12 is made up of a single impurity region having a thickness (depth) that traverses the intermediate portion of the first layer 8 along the first axial channel CH1.

[0061] The lower end of the first impurity region 12 may be formed at a distance from the lower end of the first layer 8 (i.e., the base layer 6) toward the upper end, and may face the base layer 6 across a part (lower end) of the first layer 8. The lower end of the first impurity region 12 may be substantially coincident with the lower end of the first layer 8 and connected to the base layer 6.

[0062] The distance between the lower end of the first layer 8 and the lower end of the first impurity region 12 may be 0 μm or more and 2 μm or less. The distance between the lower end of the first layer 8 and the lower end of the first impurity region 12 may have a value belonging to any one of the ranges of 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0063] The lower end of the first impurity region 12 may have an extension that crosses the boundary between the base layer 6 and the first layer 8 and is located within the base layer 6. Since the first axis channel CH1 is substantially coincident with the base axis channel CHB, the extension of the first impurity region 12 is formed within the first layer 8 along the base axis channel CHB.

[0064] In this case, the thickness of the extension of the first impurity region 12 may be more than 0 μm and not more than 2 μm, based on the upper end of the base layer 6. The thickness of the extension of the first impurity region 12 may have a value belonging to any one of the ranges of more than 0 μm and not more than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, and 1.5 μm to 2 μm.

[0065] The upper end of the first impurity region 12 may be formed at a distance from the upper end of the first layer 8 (i.e., the second layer 9) toward the lower end, and may face the upper end of the first layer 8 across a part (upper end) of the first layer 8. The upper end of the first impurity region 12 may be substantially coincident with the upper end of the first layer 8 and connected to the second layer 9.

[0066] The distance between the upper end of the first layer 8 and the upper end of the first impurity region 12 may be 0 μm or more and 1 μm or less. The distance between the upper ends of the first layer 8 may have a value belonging to any one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0067] Of course, the first impurity region 12 may be formed in almost the entire region of the first layer 8. In other words, the first impurity region 12 may invert the conductivity type of almost the entire region of the first layer 8 from n-type to p-type. In this case, the first layer 8 may be considered to be a p-type first layer 8.

[0068] The thickness of the first impurity region 12 may be less than the first thickness T1 of the first layer 8. The thickness of the first impurity region 12 may be greater than the first thickness T1. The thickness of the first impurity region 12 may be approximately equal to the first thickness T1. The thickness of the first impurity region 12 may be less than the second thickness T2 of the second layer 9. The thickness of the first impurity region 12 may be greater than the second thickness T2. The thickness of the first impurity region 12 may be approximately equal to the second thickness T2.

[0069] The thickness of the first impurity region 12 is preferably 1 μm or more. The thickness of the first impurity region 12 is preferably 5 μm or less. The thickness of the first impurity region 12 may have a value belonging to any one of the following ranges: 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0070] SiC semiconductor device 1A includes p-type second impurity region 13 formed in second layer 9 at least in a portion located in active region 10. In this embodiment, second impurity region 13 is drawn from active region 10 to peripheral region 11. That is, second impurity region 13 is drawn from a portion of second layer 9 located in active region 10 to a portion of second layer 9 located in peripheral region 11.

[0071] Furthermore, second impurity region 13 extends from peripheral region 11 toward first to fourth side surfaces 5A to 5D and is exposed from first to fourth side surfaces 5A to 5D. Of course, second impurity region 13 may be formed in second layer 9 at a distance inward from first to fourth side surfaces 5A to 5D. In this case, the peripheral portion of second impurity region 13 may be located within active region 10 or may be located within peripheral region 11.

[0072] The second impurity region 13 is a region that inverts the conductivity type of the second layer 9 from n-type to p-type. That is, the second impurity region 13 contains a trivalent element in addition to the pentavalent element that constitutes the conductivity type of the second layer 9. The p-type impurity concentration of the second impurity region 13 is higher than the n-type impurity concentration of the second layer 9. The second impurity region 13 has a concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0073] The p-type impurity concentration (peak value) of the second impurity region 13 may be equal to or greater than the p-type impurity concentration (peak value) of the first impurity region 12. The n-type impurity concentration (peak value) of the second impurity region 13 may be less than the n-type impurity concentration (peak value) of the first impurity region 12. The n-type impurity concentration (peak value) of the second impurity region 13 may be approximately equal to the n-type impurity concentration (peak value) of the first impurity region 12.

[0074] The p-type impurity concentration of the second impurity region 13 is preferably adjusted by at least one trivalent element. It is particularly preferable that the p-type impurity concentration of the second impurity region 13 is adjusted by a trivalent element that is heavier than carbon. In other words, the second impurity region 13 preferably contains a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the p-type impurity concentration of the second impurity region 13 is adjusted by aluminum.

[0075] The second impurity region 13 is a p-type channeling region that extends along the second axial channel CH2 in the second layer 9 in a cross-sectional view. That is, the second impurity region 13 is an impurity region that is introduced parallel or substantially parallel to a region (the second axial channel CH2) that is surrounded by atomic rows along the low-index crystal axis in the second layer 9, and extends at an angle with respect to the first main surface 3.

[0076] Therefore, the second impurity region 13 has an off direction Doff and an off angle θoff that are substantially identical to the off direction Doff and the off angle θoff of the second axial channel CH2. In other words, the second impurity region 13 is inclined by the off angle θoff from the vertical axis toward the off direction Doff.

[0077] The second impurity region 13 has a lower end located on the lower end side of the second layer 9 and an upper end located on the upper end side of the second layer 9. In this embodiment, the lower end of the second impurity region 13 is located in a region closer to the lower end of the second layer 9 than the intermediate portion of the thickness range of the second layer 9, and the upper end of the second impurity region 13 is located in a region closer to the upper end of the second layer 9 than the intermediate portion of the thickness range of the second layer 9. In other words, the second impurity region 13 is made up of a single impurity region having a thickness (depth) that traverses the intermediate portion of the second layer 9 along the second axial channel CH2.

[0078] The lower end of second impurity region 13 preferably has an extension that crosses the boundary between first layer 8 and second layer 9 and is located within first layer 8. In this case, it is particularly preferable that the extension of second impurity region 13 is connected to first impurity region 12 within first layer 8. In other words, second impurity region 13 preferably forms one p-type impurity region together with first impurity region 12. Since second axial channel CH2 approximately coincides with first axial channel CH1, the extension of second impurity region 13 is formed along first axial channel CH1 within first layer 8.

[0079] The thickness of the extension of the second impurity region 13, based on the upper end of the first layer 8, may be more than 0 μm and not more than 2 μm. The thickness of the extension of the second impurity region 13 may have a value belonging to any one of the ranges of more than 0 μm and not more than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, and 1.5 μm to 2 μm.

[0080] Of course, the lower end of second impurity region 13 may be formed at a distance from the lower end of second layer 9 toward the upper end, and may face first layer 8 (first impurity region 12) across a part (lower end) of second layer 9. The lower end of second impurity region 13 may be substantially coincident with the lower end of second layer 9 and connected to first layer 8 or first impurity region 12.

[0081] In this case, the distance between the lower end of the second layer 9 and the lower end of the second impurity region 13 may be 0 μm or more and 2 μm or less. The distance between the lower end of the second layer 9 and the lower end of the second impurity region 13 may have a value belonging to any one of the ranges of 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0082] The upper end of the second impurity region 13 may be formed at a distance from the upper end of the second layer 9 (i.e., the first main surface 3) toward the lower end, and may face the upper end of the second layer 9 across a part (upper end) of the second layer 9. In this case, the space in the second layer 9 between the first main surface 3 and the upper end of the second impurity region 13 may be used as a region for forming a device structure (other impurity regions, etc.). Of course, the upper end of the second impurity region 13 may be exposed from the upper end of the second layer 9 (i.e., the first main surface 3).

[0083] The distance between the upper end of the second layer 9 and the upper end of the second impurity region 13 may be 0 μm or more and 1 μm or less. The distance between the upper end of the second layer 9 and the upper end of the second impurity region 13 may have a value belonging to any one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0084] Of course, the second impurity region 13 may be formed in almost the entire region of the second layer 9. In other words, the second impurity region 13 may invert the conductivity type of almost the entire region of the second layer 9 from n-type to p-type. In this case, the second layer 9 may be considered to be a p-type second layer 9.

[0085] The thickness of the second impurity region 13 may be less than the first thickness T1 of the first layer 8. The thickness of the second impurity region 13 may be greater than the first thickness T1. The thickness of the second impurity region 13 may be approximately equal to the first thickness T1. The thickness of the second impurity region 13 may be less than the second thickness T2 of the second layer 9. The thickness of the second impurity region 13 may be greater than the second thickness T2. The thickness of the second impurity region 13 may be approximately equal to the second thickness T2.

[0086] The thickness of the second impurity region 13 is preferably 1 μm or more. The thickness of the second impurity region 13 is preferably 5 μm or less. The thickness of the second impurity region 13 may have a value belonging to any one of the following ranges: 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0087] The following specifically describes the concentration gradient of the p-type impurity concentration in the first impurity region 12 and the concentration gradient of the p-type impurity concentration in the second impurity region 13. Since the description of the concentration gradient of the first impurity region 12 and the description of the concentration gradient of the second impurity region 13 are almost similar, the following will exemplify the concentration gradient of the second impurity region 13.

[0088] The concentration gradient of the first impurity region 12 can be explained by replacing "first layer 8" with "base layer 6," "second layer 9" with "first layer 8," "second impurity region 13" with "first impurity region 12," and "second axial channel CH2" with "first axial channel CH1" as necessary in the following description. In other words, the relative or absolute positional relationship of the second impurity region 13 with respect to the first layer 8 and the second layer 9 applies mutatis mutandis to the relative or absolute positional relationship of the first impurity region 12 with respect to the base layer 6 and the first layer 8.

[0089] 6A to 6E are graphs showing an example of the concentration gradient of the second impurity region 13 (first impurity region 12). Fig. 7 is a graph showing a comparative example of the concentration gradient of the second impurity region 13 (first impurity region 12). In Fig. 6A to 6E and Fig. 7, the vertical axis represents the p-type impurity concentration of the second impurity region 13, and the horizontal axis represents the depth along the second axial channel CH2, with the upper end (first main surface 3) of the second layer 9 as the reference (zero point).

[0090] 6A to 6E and 7, 1×10 １５ cm －３ A region having the above p-type impurity concentration is defined as the second impurity region 13 and is illustrated as a graph. The values ​​of the impurity concentration, thickness, etc. shown below are examples for explaining the basic configuration of the second impurity region 13 based on the concentration gradient, and are not intended to uniquely limit the configuration of the second impurity region 13. The impurity concentration, thickness, etc. are adjusted to various values ​​depending on the implantation conditions of the trivalent element (dose amount, implantation temperature, implantation energy, etc.), etc.

[0091] 6A to 6E are graphs showing the case where the second impurity region 13 is formed by the channeling implantation method. Each of these graphs shows the concentration gradient of the second impurity region 13 when a predetermined trivalent element (here, aluminum) is introduced into the second layer 9 parallel or nearly parallel to the second axial channel CH2 with an implantation energy of 190 KeV ( FIG. 6A ), 380 KeV ( FIG. 6B ), 650 KeV ( FIG. 6C ), 960 KeV ( FIG. 6D ), or 2000 KeV ( FIG. 6E ). The second thickness T2 of the second layer 9 is about 2.5 μm, and the dose of the trivalent element is 1×10 １３ cm －２ is.

[0092] 7 is a graph showing the case where the second impurity region 13 is formed by random implantation. This graph shows the concentration gradient of the second impurity region 13 when a predetermined trivalent element (here, aluminum) is introduced into the second layer 9 in a random direction with implantation energies of 190 KeV, 380 KeV, 650 KeV, 960 KeV, or 2000 KeV. The random direction is a direction (for example, the vertical direction Z) that is not parallel (or substantially parallel) to the second axial channel CH2. The second thickness T2 of the second layer 9 is about 2.5 μm, and the dose of the trivalent element is 1×10 １３ cm －２ is.

[0093] 6A , second impurity region 13 (190 KeV) has a thickness of 1.5 μm or more and 1.8 μm or less, and has a lower end spaced from the lower end toward the upper end of second layer 9, and an upper end exposed from the upper end (first main surface 3) of second layer 9. The distance between the lower end and the lower end of second layer 9 is 0.1 μm or more and 1 μm or less.

[0094] The p-type impurity concentration of the second impurity region 13 has a concentration gradient that extends from the upper end to the lower end of the second layer 9, and includes a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23. The gradually increasing portion 20 forms the upper end of the second impurity region 13, and is a portion where the p-type impurity concentration gradually increases from the upper end toward the lower end of the second layer 9 to the peak portion 21 at a relatively steep rate of increase.

[0095] The peak portion 21 is a portion having a peak value P (maximum value) of the p-type impurity concentration. The peak portion 21 is also a convex main concentration transition portion including a series of concentration changes (inflection points) where the p-type impurity concentration changes from an increase (increasing trend) to a decrease (decreasing trend). The depth position of the peak portion 21 is 0.1 μm or more and 0.5 μm or less.

[0096] The gradual portion 22 is formed in a region closer to the lower end than the peak portion 21, and is a portion where the impurity concentration gradually decreases at a relatively gradual rate. In other words, the gradual portion 22 is a portion where a constant p-type impurity concentration is maintained within a certain depth range, and forms the main body of the second impurity region 13. The p-type impurity concentration of the gradual portion 22 gradually decreases within a concentration range that is less than the p-type impurity concentration of the peak portion 21.

[0097] The gradual portion 22 is defined as a portion having a concentration decrease rate of 50% or less in a thickness range of at least 0.5 μm. In this example, the gradual portion 22 has a thickness of 0.7 μm or more and 0.8 μm or less, and has a concentration decrease rate of 50% or less in this thickness range. In this example, the p-type impurity concentration of the gradual portion 22 is 4.5×10 １６ cm －３ 9 x 10 or more １６ cm －３ The concentration range is as follows:

[0098] The gradually decreasing portion 23 is a portion that forms the lower end of the second impurity region 13. The gradually decreasing portion 23 has a concentration decrease rate that is greater than that of the gradual portion 22, and is a portion where the p-type impurity concentration gradually decreases from the gradual portion 22 toward the lower end of the second layer 9. The concentration decrease rate per unit thickness of the gradually decreasing portion 23 is greater than the concentration decrease rate per unit thickness of the gradual portion 22. The p-type impurity concentration of the gradually decreasing portion 23 decreases from the gradual portion 22 by 1×10 １５ cm －３ It is gradually decreasing to.

[0099] 6B , second impurity region 13 (380 KeV) has a thickness of 2.2 μm or more and 2.4 μm or less, and has a lower end spaced from the lower end of second layer 9 toward the upper end, and an upper end spaced from the upper end (first main surface 3) of second layer 9 toward the lower end (first layer 8 side). The distance between the lower end of second layer 9 and the lower end of second impurity region 13 is 0.1 μm or more and 0.3 μm or less. The distance between the upper end of second layer 9 and the upper end of second impurity region 13 is 0.01 μm or more and 0.2 μm or less.

[0100] 6A , the p-type impurity concentration of the second impurity region 13 has a concentration gradient that includes a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23 from the upper end to the lower end of the second layer 9. In this example, the gradually increasing portion 20 also increases gradually from the upper end of the second impurity region 13 toward the lower end of the second layer 9 to the peak portion 21 at a relatively steep rate of increase. The depth position of the peak portion 21 is 0.3 μm or more and 0.7 μm or less.

[0101] The gradual portion 22 has a thickness of 0.8 μm or more and 1.1 μm or less, and the concentration reduction rate within this thickness range is 50% or less. In this example, the p-type impurity concentration of the gradual portion 22 is 3.5×10 １６ cm －３ 7 x 10 or more １６ cm －３ The p-type impurity concentration of the gradually decreasing portion 23 is 1×10 １５ cm －３ It is gradually decreasing to.

[0102] 6C , second impurity region 13 (650 KeV) has a thickness of 2.5 μm or more and 2.8 μm or less, and has a lower end located within first layer 8 and an upper end spaced away from the upper end (first main surface 3) of second layer 9 toward the lower end (first layer 8 side). In other words, second impurity region 13 has a thickness equal to or greater than second thickness T2 (=2.5 μm) of second layer 9.

[0103] The lower end of second impurity region 13 has an extension that crosses the boundary between first layer 8 and second layer 9 and extends into first layer 8. The extension has a thickness of 0.4 μm or more and 0.7 μm or less from the upper end of first layer 8. The distance between the upper end of second layer 9 and the upper end of second impurity region 13 is 0.3 μm or more and 0.6 μm or less. The distance between the upper end of second layer 9 and the upper end of second impurity region 13 is 0.1 μm or more and 0.4 μm or less.

[0104] 6A , the p-type impurity concentration of the second impurity region 13 has a concentration gradient from the upper end to the lower end, including a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23. In this example, the gradually increasing portion 20 also increases gradually from the upper end of the second impurity region 13 to the peak portion 21 at a relatively steep rate of increase. The depth position of the peak portion 21 is 0.6 μm or more and 1 μm or less.

[0105] The gradual portion 22 has a thickness of 1 μm or more and 1.3 μm or less, and the concentration reduction rate within this thickness range is 50% or less. In this example, the p-type impurity concentration of the gradual portion 22 is 3×10 １６ cm －３ 6 x 10 or more １６ cm －３The p-type impurity concentration of the gradually decreasing portion 23 is 1×10 １５ cm －３ It is gradually decreasing to.

[0106] 6D , second impurity region 13 (960 KeV) has a thickness of 3.1 μm or more and 3.3 μm or less, and has an upper end spaced from the upper end (first main surface 3) of second layer 9 toward the lower end (first layer 8 side) and a lower end located within first layer 8. In other words, second impurity region 13 has a thickness greater than second thickness T2 (=2.5 μm) of second layer 9.

[0107] The lower end of second impurity region 13 has an extension that crosses the boundary between first layer 8 and second layer 9 and extends into first layer 8. The extension has a thickness of 0.9 μm or more and 1.2 μm or less from the upper end of first layer 8. The distance between the upper end of second layer 9 and the upper end of second impurity region 13 is 0.3 μm or more and 0.6 μm or less.

[0108] 6A , the p-type impurity concentration of the second impurity region 13 has a concentration gradient from the upper end to the lower end, including a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23. In this example, the gradually increasing portion 20 also increases gradually from the upper end of the second impurity region 13 to the peak portion 21 at a relatively steep rate of increase. The depth position of the peak portion 21 is 0.7 μm or more and 1.3 μm or less.

[0109] The gradual portion 22 has a thickness of 1.3 μm or more and 1.7 μm or less, and the concentration reduction rate within this thickness range is 50% or less. In this example, the p-type impurity concentration of the gradual portion 22 is 2.2×10 １６ cm －３ 4.5 x 10 １６ cm －３ The p-type impurity concentration of the gradually decreasing portion 23 is 1×10 １５ cm －３ It is gradually decreasing to.

[0110] 6E , second impurity region 13 (2000 KeV) has a thickness of 3.5 μm or more and 3.8 μm or less, and has an upper end spaced from the upper end (first main surface 3) of second layer 9 toward the lower end (first layer 8 side) and a lower end located within first layer 8. In other words, second impurity region 13 has a thickness greater than second thickness T2 (=2.5 μm) of second layer 9.

[0111] The lower end of second impurity region 13 has an extension that crosses the boundary between first layer 8 and second layer 9 and extends into first layer 8. The extension has a thickness of 1.9 μm or more and 2.2 μm or less from the upper end of first layer 8. The distance between the upper end of second layer 9 and the upper end of second impurity region 13 is 0.7 μm or more and 1 μm or less.

[0112] 6A , the p-type impurity concentration of the second impurity region 13 has a concentration gradient from the upper end to the lower end, including a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23. In this example, the gradually increasing portion 20 also increases gradually from the upper end of the second impurity region 13 to the peak portion 21 at a relatively steep rate of increase. The depth position of the peak portion 21 is 1.3 μm or more and 1.9 μm or less.

[0113] The gradual portion 22 has a thickness of 1.5 μm or more and 1.8 μm or less, and has a concentration decrease rate of 50% or less within this thickness range. In this example, the gradual portion 22 crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8. In other words, the extension of the second impurity region 13 includes a part of the gradual portion 22. In this example, the p-type impurity concentration of the gradual portion 22 is 2×10 １６ cm －３ 4 x 10 or more １６ cm －３ The p-type impurity concentration of the gradually decreasing portion 23 is 1×10 １５ cm －３ It is gradually decreasing to.

[0114] 6A to 6E, the p-type impurity concentration of second impurity region 13 has a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23 at any implantation energy. The thickness (depth) of second impurity region 13 increases with increasing implantation energy. The depth position of the upper end of second impurity region 13 relative to the upper end of second layer 9 also increases with increasing implantation energy.

[0115] The thicknesses of the gradually increasing portion 20, the peak portion 21, the gradual portion 22, and the gradually decreasing portion 23 all increase with increasing implantation energy. On the other hand, the peak value P of the second impurity region 13 decreases with increasing implantation energy. This is because the trivalent element is introduced deeper into the second impurity region 13 as the implantation energy increases, increasing the p-type impurity concentration in the second impurity region 13.

[0116] The gradual portion 22 occupies a thickness range of at least ¼ of the second impurity region 13 (thickness) and is located within the second layer 9. Specifically, the proportion of the gradual portion 22 in the second impurity region 13 is at least ⅓. The proportion of the gradual portion 22 in the second impurity region 13 is typically at most ½ (less than ½). The proportion of the gradual portion 22 in the second impurity region 13 may be at least ½.

[0117] 7, in the case of the random implantation method, the second impurity region 13 had a gradually increasing portion 20, a peak portion 21 (peak value P), and a gradually decreasing portion 23 within a range of 0.5 μm, but did not have a gradual portion 22 having a thickness of 0.5 μm or more. Furthermore, in the case of the random implantation method, the depth position of the peak portion 21 (peak value P) relative to the upper end of the second layer 9 increased with increasing implantation energy, but the thickness of the second impurity region 13 was less than 2 μm at any implantation energy. In other words, the thickness did not vary significantly even when the implantation energy was increased.

[0118] From this, it can be understood that, in the case of the random implantation method, it is difficult to form second impurity region 13 having a relatively large thickness (for example, a thickness of 1 μm or more and 5 μm or less) consisting of a single impurity region in second layer 9 having a relatively large second thickness T2 (for example, a second thickness T2 of 1 μm or more). Unlike Si single crystal, SiC single crystal has physical properties that make it difficult for impurities to diffuse. Therefore, the above problem is generally solved by a multi-epitaxial growth method or a multi-stage random implantation method.

[0119] In the multi-epitaxial growth method, a step of introducing a trivalent element into an epitaxial layer having a relatively small thickness (for example, a thickness of less than 1 μm) by random implantation is repeated multiple times, which increases the number of epitaxial growth steps and random implantation steps, making the manufacturing process more complicated.

[0120] In the multi-stage random implantation method, a process is performed in which a trivalent element is introduced into different depth positions in multiple stages using multiple implantation energies. For example, in the example of FIG. 7, when a 1 μm second layer 9 is formed, the trivalent element is introduced into the second layer 9 using five implantation energies (190 keV, 380 keV, 650 keV, and 960 keV). In this process, the trivalent element can be introduced into the target depth position, but the depth position at which the trivalent element can be introduced is shallow. Therefore, the number of epitaxial growth steps and the number of random implantation steps must be increased, resulting in the same problems as in the multi-epitaxial growth method.

[0121] In contrast, in the case of the channeling implantation method, second impurity region 13 having gentle portion 22 with a thickness of 0.5 μm to 2 μm is formed in second layer 9 having a relatively large thickness (for example, a thickness of 1 μm to 5 μm). Therefore, second impurity region 13 is formed with fewer steps than when the random implantation method is adopted.

[0122] In contrast, the channeling implantation method allows for precise control of the impurity concentration (concentration gradient) and depth position of the trivalent element introduced into the second layer 9. Therefore, the second impurity region 13 having the desired p-type impurity concentration (concentration gradient) can be formed in the second layer 9.

[0123] Of course, this specification does not exclude the technical idea of ​​introducing a plurality of second impurity regions 13 in multiple stages at different depth positions by a channeling implantation method using a plurality of implantation energies to form one second impurity region 13. In this case, each second impurity region 13 is made up of an integrated region of a plurality of impurity regions (second impurity regions 13) respectively formed in the second layer 9 along the second axial channel CH2 so as to cross the intermediate portion of the second layer 9.

[0124] In this case, the p-type impurity concentration (concentration gradient) of each second impurity region 13 is the sum of the p-type impurity concentrations (concentration gradients) of the multiple impurity regions (second impurity regions 13). For example, the p-type impurity concentration of each second impurity region 13 has a concentration gradient (sum of concentration gradients) obtained by superimposing at least two of the five graphs shown in Figures 6A to 6E.

[0125] 6A to 6E, the upper limit of the implantation energy of the channeling implantation method is 2000 KeV, but the second impurity region 13 can also be formed with an implantation energy greater than 2000 KeV. In this case, a relatively thick second impurity region 13 is formed at a position deeper than the concentration gradient shown in FIG.

[0126] However, when an implantation energy greater than 2000 KeV is realized, the amount of trivalent elements passing through the upper end of the second layer 9 increases, and the range of the vacant region on the upper end side (i.e., the distance between the first main surface 3 and the second impurity region 13) expands, making it more difficult to design the second impurity region 13.

[0127] Furthermore, when an implantation energy of more than 2000 KeV is realized, the size of the ion accelerator may reach several tens of meters, which is considered to be unrealistic from the viewpoint of cost-effectiveness (installation space and capital investment). Therefore, when forming a relatively thick second impurity region 13 by channeling implantation, it is preferable to limit the implantation energy to 2000 KeV or less and increase the number of layers in the stacked portion 7.

[0128] 1 to 5 again, the SiC semiconductor device 1A includes a plurality of n-type first inversion columns 14 formed in at least a portion of the first layer 8 located in the active region 10. The first inversion columns 14 may also be referred to as "first inversion regions," etc. The plurality of first inversion columns 14 are formed at intervals in the horizontal direction in the first layer 8, and invert the conductivity type of the first impurity region 12 from p-type to n-type. In other words, the first inversion columns 14 include the pentavalent element of the first layer 8 and the trivalent element of the first impurity region 12.

[0129] The first inverted columns 14 are arranged at intervals in the first arrangement direction Da1 in the first layer 8 and are each formed in a strip shape extending in the first extension direction De1. The first extension direction De1 is a direction that intersects or is perpendicular to the first arrangement direction Da1. In other words, the first inverted columns 14 are formed in a strip shape extending in the first extension direction De1.

[0130] In this embodiment, the first arrangement direction Da1 is the a-axis direction (first direction X), and the first extension direction De1 is the m-axis direction (second direction Y). Of course, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Furthermore, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.

[0131] In this embodiment, the first reversal columns 14 extend from the active region 10 to the peripheral region 11 (see FIG. 3A ). That is, the first reversal columns 14 extend from a portion of the first layer 8 located in the active region 10 to a portion of the first layer 8 located in the peripheral region 11. The first reversal columns 14 are also arranged at intervals in the first array direction Da1 in the peripheral region 11, and are each formed in a strip shape extending in the first extension direction De1.

[0132] Furthermore, the multiple first inversion columns 14 extend from the outer peripheral region 11 toward either or both of the first side surface 5A and the third side surface 5C (both in this embodiment), and each have a portion exposed from either or both of the first side surface 5A and the third side surface 5C (both in this embodiment).

[0133] The first inversion columns 14 are made of n-type channeling regions that extend along the first axial channel CH1 in the first layer 8 in a cross-sectional view. That is, the first inversion columns 14 are made of impurity regions that are introduced parallel or nearly parallel to a region (first axial channel CH1) that is surrounded by atomic rows along the low-index crystal axis in the first layer 8, and extend at an angle with respect to the first main surface 3.

[0134] Therefore, the first reversing columns 14 have an off direction Doff and an off angle θoff that are substantially identical to the off direction Doff and the off angle θoff of the first axis channel CH1. In other words, the first reversing columns 14 are inclined by the off angle θoff from the vertical axis toward the off direction Doff.

[0135] Each of the first inversion columns 14 has a lower end located at the lower end of the first layer 8 and an upper end located at the upper end of the first layer 8. In this configuration, the lower ends of the first inversion columns 14 are located in a region closer to the lower end of the first layer 8 than the middle of the thickness range of the first layer 8, and the upper ends of the first inversion columns 14 are located in a region closer to the upper end of the first layer 8 than the middle of the thickness range of the first layer 8. In other words, the first inversion columns 14 are formed by a single impurity region having a thickness (depth) that traverses the middle of the first layer 8 along the first axial channel CH1.

[0136] The lower ends of the plurality of first inversion columns 14 preferably have extensions that cross the lower ends of the first impurity regions 12. When the lower ends of the first impurity regions 12 are located in the base layer 6, the extensions of the plurality of first inversion columns 14 preferably cross the lower ends of the first impurity regions 12 in the base layer 6 and are connected to the base layer 6.

[0137] When the lower ends of the first impurity regions 12 are located within the first layer 8, the extending portions of the first inversion columns 14 preferably cross the lower ends of the first impurity regions 12 within the first layer 8 and are connected to at least the first layer 8. In this case, the extending portions of the first inversion columns 14 may cross the boundary between the base layer 6 and the first layer 8 and be located in the surface portion of the base layer 6.

[0138] Since the first axial channel CH1 is substantially aligned with the base axial channel CHB, the extending portion of the first inverted column 14 is formed along the base axial channel CHB in the base layer 6. Of course, the extending portions of the multiple first inverted columns 14 may be formed at intervals from the lower end of the first layer 8 toward the upper end of the first layer 8.

[0139] The thickness of the extension of the first inversion column 14 may be greater than 0 μm and less than 2 μm, based on the lower end of the first impurity region 12. The thickness of the extension of the first inversion column 14 may be in any one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, and 1.5 μm to 2 μm.

[0140] The upper end of the first inverted column 14 may be formed at a distance from the upper end of the first layer 8 (i.e., the second layer 9) toward the lower end, and may face the upper end of the first layer 8 across a part (upper end) of the first layer 8. The upper end of the first inverted column 14 may be substantially coincident with the upper end of the first layer 8 and connected to the second layer 9.

[0141] The distance between the upper end of the first layer 8 and the upper end of the first inverted column 14 may be 0 μm or more and 1 μm or less. The distance between the upper end of the first layer 8 and the upper end of the first inverted column 14 may have a value belonging to any one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0142] The first reversing columns 14 are 1×10 １５ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the first inversion column 14 may have the following peak value. The n-type impurity concentration of the first inversion column 14 is preferably adjusted with at least one pentavalent element. For example, the n-type impurity concentration of the first inversion column 14 may be adjusted with at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0143] The first inversion column 14 preferably contains a pentavalent element other than nitrogen and phosphorus. The n-type impurity concentration of the first inversion column 14 is preferably adjusted with at least one of arsenic, antimony, and bismuth. In consideration of availability, the n-type impurity concentration of the first inversion column 14 is preferably adjusted with arsenic or antimony.

[0144] Each of the first inverting columns 14 has a first width W1. The first width W1 is the width of the first inverting columns 14 along the first arrangement direction Da1. The first width W1 is preferably less than the first thickness T1 of the first layer 8. Of course, the first width W1 may be equal to or greater than the first thickness T1. The first width W1 is preferably less than the second thickness T2 of the second layer 9. Of course, the first width W1 may be equal to or greater than the second thickness T2.

[0145] The first width W1 may be 0.1 μm or more and 5 μm or less. The first width W1 may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The first width W1 is preferably 0.5 μm or more and 1.5 μm or less.

[0146] Each of the first inverted columns 14 has a first region thickness TR1 (first region depth). The first region thickness TR1 may be less than the first thickness T1 of the first layer 8. The first region thickness TR1 may be greater than the first thickness T1. The first region thickness TR1 may be approximately equal to the first thickness T1. The first region thickness TR1 may be less than the second thickness T2 of the second layer 9. The first region thickness TR1 may be greater than the second thickness T2. The first region thickness TR1 may be approximately equal to the second thickness T2.

[0147] The first region thickness TR1 is preferably 1 μm or more. The first region thickness TR1 is preferably 5 μm or less. The first region thickness TR1 may have a value belonging to any one of the ranges of 1 μm or more to 1.5 μm or less, 1.5 μm or more to 2 μm or less, 2 μm or more to 2.5 μm or less, 2.5 μm or more to 3 μm or less, 3 μm or more to 3.5 μm or less, 3.5 μm or more to 4 μm or less, 4 μm or more to 4.5 μm or less, and 4.5 μm or more to 5 μm or less.

[0148] Preferably, the first width W1 is less than the first thickness T1 of the first layer 8, and the first region thickness TR1 is greater than the first width W1. That is, the first inverted columns 14 each preferably have a first aspect ratio TR1 / W1 such that they extend in a vertically elongated columnar shape along the first axial channel CH1. The first aspect ratio TR1 / W1 is the ratio of the first region thickness TR1 to the first width W1. In this case, it is particularly preferred that the first region thickness TR1 be greater than the first thickness T1. For example, the first aspect ratio TR1 / W1 may be greater than 1 and not greater than 100.

[0149] The first inverted columns 14 are spaced apart at a first pitch P1 in the first arrangement direction Da1. The first pitch P1 is preferably less than the first thickness T1 of the first layer 8. Of course, the first pitch P1 may be equal to or greater than the first thickness T1. The first pitch P1 is preferably less than the second thickness T2 of the second layer 9. Of course, the first pitch P1 may be equal to or greater than the second thickness T2.

[0150] The first pitch P1 may be 0.1 μm or more and 5 μm or less. The first pitch P1 may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The first pitch P1 is preferably 0.5 μm or more and 1.5 μm or less.

[0151] Although specific illustrations are omitted, the multiple first inversion columns 14 differ from the second impurity regions 13 (first impurity regions 12) in that they are composed of a pentavalent element. However, like the second impurity regions 13 (first impurity regions 12), the multiple first inversion columns 14 have a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23 from the upper end to the lower end (see also FIGS. 6A to 6E ).

[0152] The concentration gradient of the first inversion column 14 can be explained by replacing "second impurity region 13" with "first inversion column 14" and "p-type (trivalent element)" with "n-type (pentavalent element)" in the explanation of the concentration gradient of the second impurity region 13 (first impurity region 12) described above (see also FIGS. 6A to 6E).

[0153] In the case of the first inversion columns 14, a pentavalent element instead of a trivalent element is introduced into the first layer 8. Therefore, even if the same process conditions as those for the first impurity regions 12 are imposed, it should be noted that the concentration profile and thickness (depth) of the first inversion columns 14 are different from those of the first impurity regions 12. Therefore, in order to achieve an appropriate charge balance, it is preferable to set the process conditions for the first impurity regions 12 and the process conditions for the first inversion columns 14 separately.

[0154] The SiC semiconductor device 1A includes a plurality of p-type first non-inversion columns 15 formed in the first layer 8. The first non-inversion columns 15 may also be referred to as "first non-inversion regions," etc. Each of the plurality of first non-inversion columns 15 is formed from a region defined by a plurality of first inversion columns 14 in the first impurity region 12.

[0155] That is, the multiple first non-inversion columns 15 are made of p-type channeling regions extending along the first axial channel CH1 in the first layer 8 in a cross-sectional view, and are defined at intervals in the horizontal direction in the first layer 8. Specifically, the multiple first non-inversion columns 15 are arranged at intervals in the first array direction Da1 in the first layer 8, and are each defined as a strip extending in the first extension direction De1.

[0156] In this embodiment, the first non-inversion columns 15 extend from the active region 10 to the peripheral region 11 (see FIG. 3A ). That is, the first non-inversion columns 15 extend from a portion of the first layer 8 located in the active region 10 to a portion of the first layer 8 located in the peripheral region 11. The first non-inversion columns 15 are also arranged at intervals in the first array direction Da1 in the peripheral region 11, and are each partitioned into strips extending in the first extension direction De1.

[0157] Furthermore, the multiple first non-inverting columns 15 extend from the outer peripheral region 11 toward either or both of the first side surface 5A and the third side surface 5C (both in this embodiment), and each have a portion exposed from either or both of the first side surface 5A and the third side surface 5C (both in this embodiment).

[0158] The first non-inverting columns 15 form first pn junctions having charge balance together with the first inverting columns 14. That is, the first non-inverting columns 15 and the first inverting columns 14 form a first superjunction structure SJ1.

[0159] The charge-balanced state means that, for adjacent first inversion columns 14, the depletion layer extending from one first pn junction and the depletion layer extending from the other first pn junction are connected within the first non-inversion columns 15. In other words, in this configuration, the concentration-adjusted p-type first non-inversion columns 15 (first impurity regions 12) form a charge balance with the concentration-adjusted n-type first inversion columns 14. Furthermore, the description of the first impurity regions 12 also applies to the description of the first non-inversion columns 15 regions.

[0160] The SiC semiconductor device 1A includes a plurality of n-type second inversion columns 16 formed in at least a portion of the second layer 9 located in the active region 10. The second inversion columns 16 may also be referred to as "second inversion regions," etc. The plurality of second inversion columns 16 are formed at intervals in the horizontal direction in the second layer 9, and invert the conductivity type of the second impurity region 13 from p-type to n-type. In other words, the second inversion columns 16 include the pentavalent element of the second layer 9 and the trivalent element of the second impurity region 13.

[0161] In this embodiment, the second inverted columns 16 are formed in the second layer 9 so as to overlap the first inverted columns 14 in the stacking direction. Specifically, the second inverted columns 16 are arranged at intervals in the second layer 9 in a second arrangement direction Da2 different from the first arrangement direction Da1, and are each formed in a strip shape extending in a second extension direction De2 different from the first extension direction De1.

[0162] The second extension direction De2 is a direction that intersects or is perpendicular to the second arrangement direction Da2. That is, the second inversion columns 16 are formed in a stripe shape extending in the second arrangement direction De2. In this embodiment, the second arrangement direction Da2 is the m-axis direction (second direction Y), and the second extension direction De2 is the a-axis direction (first direction X).

[0163] Of course, when the first arrangement direction Da1 is the m-axis direction and the first extension direction De1 is the a-axis direction, the second arrangement direction Da2 may be the a-axis direction and the second extension direction De2 may be the m-axis direction. When the first arrangement direction Da1 is a direction other than the a-axis direction and the m-axis direction and the first extension direction De1 is a direction other than the a-axis direction and the m-axis direction, the second arrangement direction Da2 may be one of the a-axis direction and the m-axis direction, and the second extension direction De2 may be the other of the a-axis direction and the m-axis direction.

[0164] When the first arrangement direction Da1 is a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 is a direction other than the a-axis direction and the m-axis direction, the second arrangement direction Da2 may be a direction other than the a-axis direction and the m-axis direction, and the second extension direction De2 may be a direction other than the a-axis direction and the m-axis direction.

[0165] The second inversion columns 16 intersect with the first inversion columns 14 and the first non-inversion columns 15 in a plan view, so that the second inversion columns 16, together with the first inversion columns 14, form a p-type three-dimensional lattice of inversion columns within the stack 7.

[0166] In this embodiment, the second inversion columns 16 extend from the active region 10 to the peripheral region 11 (see FIG. 3B ). That is, the second inversion columns 16 extend from the portion of the second layer 9 located in the active region 10 to the portion of the second layer 9 located in the peripheral region 11.

[0167] The second reversing columns 16 are also arranged at intervals in the second arrangement direction Da2 in the outer peripheral region 11, and are each formed in a strip shape extending in the second extension direction De2. That is, the second reversing columns 16 intersect with the first reversing columns 14 and the first non-reversing columns 15 in the outer peripheral region 11.

[0168] Furthermore, the multiple second inversion columns 16 extend from the outer peripheral region 11 toward either or both (in this embodiment, both) of the second side surface 5B and the fourth side surface 5D, and each have a portion exposed from either or both (in this embodiment, both) of the second side surface 5B and the fourth side surface 5D.

[0169] The second inversion columns 16 are made of n-type channeling regions that extend along the second axial channel CH2 in the second layer 9 in a cross-sectional view. That is, the second inversion columns 16 are made of impurity regions that are introduced parallel or nearly parallel to a region (the second axial channel CH2) that is surrounded by atomic rows along the low-index crystal axis in the second layer 9, and extend at an angle with respect to the first main surface 3.

[0170] Therefore, the second reversing columns 16 have an off direction Doff and an off angle θoff that are substantially identical to the off direction Doff and the off angle θoff of the second axis channel CH2. In other words, the second reversing columns 16 are inclined by the off angle θoff from the vertical axis toward the off direction Doff.

[0171] The second inversion columns 16 each have a lower end located at the lower end of the second layer 9 and an upper end located at the upper end of the second layer 9. In this configuration, the lower ends of the second inversion columns 16 are located in a region closer to the lower end of the second layer 9 than the middle of the thickness range of the second layer 9, and the upper ends of the second inversion columns 16 are located in a region closer to the upper end of the second layer 9 than the middle of the thickness range of the second layer 9. In other words, the second inversion columns 16 are formed by a single impurity region having a thickness (depth) that traverses the middle of the second layer 9 along the second axial channel CH2.

[0172] The lower ends of the second inversion columns 16 preferably have extensions that cross the lower ends of the second impurity regions 13. When the lower ends of the second impurity regions 13 are located within the first layer 8, the extensions of the second inversion columns 16 preferably cross the lower ends of the second impurity regions 13 within the first layer 8 and are connected to the first layer 8.

[0173] In this case, it is preferable that the extensions of the second inverting columns 16 are connected to the first inverting columns 14 in the first layer 8. In other words, it is preferable that the second inverting columns 16, together with the first inverting columns 14, form a single three-dimensional lattice-like inverting column that extends continuously in the thickness direction. Because the second axial channel CH2 is substantially aligned with the first axial channel CH1, the extensions of the second inverting columns 16 are formed along the first axial channel CH1 in the first layer 8.

[0174] When the lower end of the second impurity region 13 is located within the second layer 9, it is preferable that the extensions of the second inversion columns 16 cross the lower ends of the second impurity region 13 within the second layer 9 and are electrically connected to the first inversion columns 14 via at least the second layer 9.

[0175] In this case, it is preferable that the extending portions of the second inverted columns 16 cross the boundary between the first layer 8 and the second layer 9 and are connected to the first inverted columns 14 within the first layer 8. Of course, the extending portions of the second inverted columns 16 may be formed at intervals from the lower end of the second layer 9 toward the upper end of the second layer 9.

[0176] The thickness of the extension of the second inversion column 16, based on the lower end of the second impurity region 13, may be greater than 0 μm and less than 2 μm. The thickness of the extension of the second inversion column 16 may be in any one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, and 1.5 μm to 2 μm.

[0177] The upper ends of the second inversion columns 16 may be formed at a distance from the upper end of the second layer 9 (i.e., the first main surface 3) toward the lower end, and may face the upper end of the second layer 9 across a part (upper end) of the second layer 9. In this case, the space in the second layer 9 between the first main surface 3 and the upper ends of the second inversion columns 16 may be used as a region for forming a device structure (other impurity regions, etc.). Of course, the upper ends of the second inversion columns 16 may be exposed from the upper end of the second layer 9 (i.e., the first main surface 3).

[0178] The distance between the upper end of the second layer 9 and the upper end of the second inverted column 16 may be 0 μm or more and 1 μm or less. The distance between the upper end of the second layer 9 and the upper end of the second inverted column 16 may have a value belonging to any one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0179] The plurality of second reversing columns 16 are 1×10 １５ cm －３ 1x10 or more １８ cm －３ The peak value of the n-type impurity concentration of the second inversion column 16 may be equal to or greater than the peak value of the n-type impurity concentration of the first inversion column 14. The peak value of the n-type impurity concentration of the second inversion column 16 may be less than the peak value of the n-type impurity concentration of the first inversion column 14. The peak value of the n-type impurity concentration of the second inversion column 16 may be approximately equal to the peak value of the n-type impurity concentration of the first inversion column 14.

[0180] The n-type impurity concentration of the second inversion column 16 is preferably adjusted with at least one pentavalent element. For example, the n-type impurity concentration of the second inversion column 16 may be adjusted with at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0181] The second inversion columns 16 preferably contain a pentavalent element other than nitrogen and phosphorus. The n-type impurity concentration of the second inversion columns 16 is preferably adjusted with at least one of arsenic, antimony, and bismuth. In consideration of availability, the n-type impurity concentration of the second inversion columns 16 is preferably adjusted with arsenic or antimony.

[0182] Each of the second inverting columns 16 has a second width W2. The second width W2 is the width of the second inverting columns 16 along the second arrangement direction Da2. The second width W2 is preferably less than the second thickness T2 of the second layer 9. Of course, the second width W2 may be equal to or greater than the second thickness T2.

[0183] The second width W2 is preferably less than the first thickness T1 of the first layer 8. Of course, the second width W2 may be equal to or greater than the first thickness T1. The second width W2 is preferably approximately equal to the first width W1 of the first reversing column 14. Of course, the second width W2 may be equal to or greater than the first width W1, or may be less than the first width W1.

[0184] The second width W2 may be 0.1 μm or more and 5 μm or less. The second width W2 may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The second width W2 is preferably 0.5 μm or more and 1.5 μm or less.

[0185] Each of the second inverted columns 16 has a second regional thickness TR2 (region depth). The second regional thickness TR2 may be less than the second thickness T2 of the second layer 9. The second regional thickness TR2 may be greater than the second thickness T2. The second regional thickness TR2 may be approximately equal to the second thickness T2.

[0186] The second regional thickness TR2 may be less than the first thickness T1 of the first layer 8. The second regional thickness TR2 may be greater than the first thickness T1. The second regional thickness TR2 may be approximately equal to the first thickness T1. The second regional thickness TR2 may be less than the first regional thickness TR1 of the first inverted column 14. The second regional thickness TR2 may be greater than the first regional thickness TR1. The second regional thickness TR2 may be approximately equal to the first regional thickness TR1.

[0187] The second region thickness TR2 is preferably 1 μm or more. The second region thickness TR2 is preferably 5 μm or less. The second region thickness TR2 may have a value belonging to any one of the ranges of 1 μm or more to 1.5 μm or less, 1.5 μm or more to 2 μm or less, 2 μm or more to 2.5 μm or less, 2.5 μm or more to 3 μm or less, 3 μm or more to 3.5 μm or less, 3.5 μm or more to 4 μm or less, 4 μm or more to 4.5 μm or less, and 4.5 μm or more to 5 μm or less.

[0188] Preferably, the second width W2 is less than the second thickness T2 of the second layer 9, and the second region thickness TR2 is greater than the second width W2. That is, the second inverted columns 16 each preferably have a second aspect ratio TR2 / W2 such that they extend in a vertically elongated columnar shape along the second axial channel CH2. The second aspect ratio TR2 / W2 is the ratio of the second region thickness TR2 to the second width W2. In this case, it is particularly preferred that the second region thickness TR2 be greater than the second thickness T2. For example, the second aspect ratio TR2 / W2 may be greater than 1 and not greater than 100.

[0189] The second inverted columns 16 are spaced apart at a second pitch P2 in the second arrangement direction Da2. The second pitch P2 is preferably less than the second thickness T2 of the second layer 9. Of course, the second pitch P2 may be equal to or greater than the second thickness T2 of the second layer 9. The second pitch P2 is preferably less than the first thickness T1 of the first layer 8. Of course, the second pitch P2 may be equal to or greater than the first thickness T1.

[0190] The second pitch P2 may be approximately equal to the first pitch P1 or may be different from the first pitch P1. The second pitch P2 may be larger than the first pitch P1 or smaller than the first pitch P1.

[0191] The second pitch P2 may be 0.1 μm or more and 5 μm or less. The second pitch P2 may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The second pitch P2 is preferably 0.5 μm or more and 1.5 μm or less.

[0192] Although specific illustrations are omitted, the second inversion columns 16 differ from the second impurity regions 13 (first impurity regions 12) in that they are composed of a pentavalent element. However, like the second impurity regions 13 (first impurity regions 12), the second inversion columns 16 have a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23 from the upper end to the lower end (see also FIGS. 6A to 6E ).

[0193] The concentration gradient of the second inversion column 16 can be explained by replacing the "second impurity region 13" with the "first inversion column 14" and the "p-type (trivalent element)" with the "n-type (pentavalent element)" in the explanation of the concentration gradient of the second impurity region 13 (first impurity region 12) described above.

[0194] In the case of the second inversion columns 16, a pentavalent element is introduced into the second layer 9 instead of a trivalent element, and therefore, even if the same process conditions as those for the second impurity regions 13 are imposed, it should be noted that the concentration profile and thickness (depth) of the second inversion columns 16 are different from those of the second impurity regions 13. Therefore, in order to achieve an appropriate charge balance, it is preferable to set the process conditions for the second impurity regions 13 and the second inversion columns 16 separately.

[0195] The SiC semiconductor device 1A includes a plurality of p-type second non-inversion columns 17 formed in the second layer 9. The second non-inversion columns 17 may also be referred to as "second non-inversion regions," etc. Each of the plurality of second non-inversion columns 17 is formed from a region defined by a plurality of second inversion columns 16 in the second impurity region 13.

[0196] That is, the second non-inversion columns 17 are made of p-type channeling regions extending along the second axial channel CH2 in the second layer 9 in a cross-sectional view, and are defined at intervals in the horizontal direction in the second layer 9. Specifically, the second non-inversion columns 17 are arranged at intervals in the second array direction Da2 in the second layer 9, and are each defined as a strip extending in the second extension direction De2.

[0197] The second non-inverting columns 17 overlap the first non-inverting columns 15 in the stacking direction. Specifically, the second non-inverting columns 17 intersect the first non-inverting columns 14 and the first non-inverting columns 15 in plan view. The second non-inverting columns 17, together with the first non-inverting columns 15, form a p-type three-dimensional lattice of non-inverting columns within the stacking unit 7.

[0198] In this embodiment, the second non-inversion columns 17 extend from the active region 10 to the peripheral region 11 (see FIG. 3B ). That is, the second non-inversion columns 17 extend from a portion of the second layer 9 located in the active region 10 to a portion of the first layer 8 located in the peripheral region 11. The second non-inversion columns 17 are also arranged at intervals in the second array direction Da2 in the peripheral region 11, and are each formed in a strip shape extending in the second extension direction De2.

[0199] Furthermore, the multiple second non-inverted columns 17 extend from the outer peripheral region 11 toward either or both of the second side surface 5B and the fourth side surface 5D (both in this embodiment), and each have a portion exposed from either or both of the second side surface 5B and the fourth side surface 5D (both in this embodiment).

[0200] The second non-inverting columns 17 form second pn junctions having charge balance together with the second inverting columns 16. That is, the second non-inverting columns 17 and the second inverting columns 16 form a second superjunction structure SJ2.

[0201] The charge-balanced state means that, for adjacent second inversion columns 16, the depletion layer extending from one second pn junction and the depletion layer extending from the other second pn junction are connected within the second non-inversion columns 17. In other words, in this configuration, the concentration-adjusted p-type second non-inversion columns 17 (second impurity regions 13) and the concentration-adjusted n-type second inversion columns 16 form a charge balance.

[0202] By connecting the lower ends of the second non-inversion columns 17 (second impurity regions 13) to the first non-inversion columns 15 (first impurity regions 12), the p-type concentration gradient formed at these junctions is alleviated. This improves the accuracy of charge balance. Similarly, by connecting the lower ends of the second inversion columns 16 to the first inversion columns 14, the n-type concentration gradient formed at these junctions is alleviated. This improves the accuracy of charge balance. Furthermore, the description of the second impurity regions 13 also applies to the description of the second non-inversion columns 17.

[0203] In this embodiment, the laminated portion 7 has a two-layer structure. However, a laminated portion 7 having a three-layer or more layer structure may be used. In this case, the odd-numbered (2n+1: n is a natural number greater than or equal to 1) layers have the same configuration as the first layer 8, and the even-numbered (2n+2) layers have the same configuration as the second layer 9.

[0204] Layout examples of the first and second reversing columns 14 and 16 will be described below with reference to FIGS. 5, 8A, and 8B. FIG. 8A is a plan view showing a first layout example of the first and second reversing columns 14 and 16. FIG. 8B is a plan view showing a second layout example of the first and second reversing columns 14 and 16. In FIGS. 8A and 8B, the first reversing columns 14 are indicated by dashed lines, and the second reversing columns 16 are indicated by hatching.

[0205] 5 , 8A, and 8B , the first arrangement direction Da1 of the first inverted columns 14 may be the a-axis direction (first direction X), and the first extension direction De1 of the first inverted columns 14 may be the m-axis direction (second direction Y). In this case, the first extension direction De1 intersects (specifically, is perpendicular to) the off-direction Doff of the first layer 8, and therefore the multiple first inverted columns 14 are inclined by approximately the off angle θoff from the vertical axis toward the off-direction Doff in a cross-sectional view seen from the m-plane ((1-100) plane) of the SiC single crystal. The m-plane of the SiC single crystal is a crystal plane perpendicular to the m-axis direction.

[0206] 5 and 8A , the second inverting columns 16 may be perpendicular to the first inverting columns 14 in a plan view. That is, the second arrangement direction Da2 of the second inverting columns 16 may be the m-axis direction (second direction Y), and the second extension direction De2 of the second inverting columns 16 may be the a-axis direction (first direction X). In this case, the second arrangement direction Da2 coincides with the first extension direction De1 and is perpendicular to the first arrangement direction Da1. Furthermore, the second extension direction De2 coincides with the first arrangement direction Da1 and is perpendicular to the first extension direction De1.

[0207] In this case, since the second extending direction De2 coincides with the off-direction Doff of the second layer 9, the second inverted columns 16 extend substantially in the vertical direction Z in a cross-sectional view taken from the a-plane ((11-20) plane) of the SiC single crystal. The a-plane of the SiC single crystal is a direction perpendicular to the a-axis direction. The second inverted columns 16 are inclined by substantially the off angle θoff from the vertical axis toward the off-direction Doff in a cross-sectional view taken from the m-plane of the SiC single crystal.

[0208] 8B , the second inverted columns 16 may intersect the first inverted columns 14 non-orthogonally in a plan view. That is, the second arrangement direction Da2 of the second inverted columns 16 may be a direction other than the m-axis direction or the a-axis direction, and the second extension direction De2 of the second inverted columns 16 may be a direction other than the m-axis direction or the a-axis direction. In this case, the second arrangement direction Da2 intersects both the first arrangement direction Da1 and the first extension direction De1, and the second extension direction De2 intersects both the first arrangement direction Da1 and the first extension direction De1. Furthermore, the second extension direction De2 intersects the off-direction Doff of the second layer 9.

[0209] The second extension direction De2 may be inclined from the a-axis toward one side (left side of the drawing) or the other side (right side of the drawing) of the m-axis in a plan view. When the a-axis is set as a reference (0°), the second reversal columns 16 have the second extension direction De2 that forms an extension angle θa with the a-axis.

[0210] The absolute value of the extension angle θa may be greater than 0° and less than 90°. The extension angle θa may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° or greater and less than 36°, 36° or greater and less than 54°, 54° or greater and less than 72°, and 72° or greater and less than 90°. The absolute value of the extension angle θa is typically set to a value belonging to any one of the ranges of 30°±5°, 45°±5°, and 60°±5°.

[0211] The first and second reversing columns 14, 16 may have the configurations shown in FIGS. 9, 10A, and 10B. FIG. 9 is a cross-sectional perspective view showing a second basic configuration of the first and second reversing columns 14, 16. FIG. 10A is a plan view showing a first layout example of the first and second reversing columns 14, 16 according to the second basic configuration. FIG. 10B is a plan view showing a second layout example of the first and second reversing columns 14, 16 according to the second basic configuration. In FIGS. 10A and 10B, the first reversing column 14 is indicated by dashed lines, and the second reversing column 16 is indicated by hatching.

[0212] 9 , 10A, and 10B , the first arrangement direction Da1 of the first inverted columns 14 may be the a-axis direction (first direction X), and the first extension direction De1 of the first inverted columns 14 may be the m-axis direction (second direction Y). In this case, the first extension direction De1 coincides with the off-direction Doff of the first layer 8, and therefore the multiple first inverted columns 14 extend substantially in the vertical direction Z in a cross-sectional view seen from the a-plane of the SiC single crystal. The multiple first inverted columns 14 have ends that are inclined by approximately the off angle θoff from the vertical axis toward the off-direction Doff in a cross-sectional view seen from the m-plane of the SiC single crystal.

[0213] 9 and 10A , the second inverting columns 16 may be perpendicular to the first inverting columns 14 in a plan view. That is, the second arrangement direction Da2 of the second inverting columns 16 may be the a-axis direction, and the second extension direction De2 of the second inverting columns 16 may be the m-axis direction. In this case, the second arrangement direction Da2 coincides with the first extension direction De1 and is perpendicular to the first arrangement direction Da1. Furthermore, the second extension direction De2 coincides with the first arrangement direction Da1 and is perpendicular to the first extension direction De1.

[0214] In this case, since the second extending direction De2 intersects (specifically, is perpendicular to) the off direction Doff of the second layer 9, the multiple second inversion columns 16 are inclined by approximately the off angle θoff from the vertical axis toward the off direction Doff in a cross-sectional view seen from the m-plane of the SiC single crystal.

[0215] 10B , the second inverted columns 16 may intersect the first inverted columns 14 non-orthogonally in a plan view. That is, the second arrangement direction Da2 of the second inverted columns 16 may be a direction other than the a-axis direction and the m-axis direction, and the second extension direction De2 of the second inverted columns 16 may be a direction other than the a-axis direction and the m-axis direction. In this case, the second arrangement direction Da2 intersects both the first arrangement direction Da1 and the first extension direction De1, and the second extension direction De2 intersects both the first arrangement direction Da1 and the first extension direction De1. Furthermore, the second extension direction De2 intersects the off-direction Doff of the second layer 9.

[0216] The second extension direction De2 may be inclined from the a-axis toward one side (left side of the drawing) or the other side (right side of the drawing) of the m-axis in a plan view. When the a-axis is set as a reference (0°), the second reversal columns 16 have the second extension direction De2 that forms an extension angle θa with the a-axis.

[0217] The absolute value of the extension angle θa may be greater than 0° and less than 90°. The extension angle θa may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° or greater and less than 36°, 36° or greater and less than 54°, 54° or greater and less than 72°, and 72° or greater and less than 90°. The absolute value of the extension angle θa is typically set to a value belonging to any one of the ranges of 30°±5°, 45°±5°, and 60°±5°.

[0218] The first and second reversing columns 14, 16 may have the configurations shown in FIGS. 11, 12A, 12B, and 12C. FIG. 11 is a cross-sectional perspective view showing a third basic configuration of the first and second reversing columns 14, 16. FIGS. 12A to 12C are plan views showing first to third layout examples of the first and second reversing columns 14, 16 according to the third basic configuration. In FIGS. 12A to 12C, the first reversing column 14 is indicated by a dashed line, and the second reversing column 16 is indicated by hatching.

[0219] 11 and 12A to 12C, the first arrangement direction Da1 of the first inverting columns 14 may be a direction other than the a-axis direction (first direction X) and the m-axis direction (second direction Y), and the first extension direction De1 of the first inverting columns 14 may be a direction other than the a-axis direction and the m-axis direction. In other words, the first inverting columns 14 may intersect both the a-axis direction and the m-axis direction. FIGS. 12A to 12C show an example in which the first inverting columns 14 are inclined toward one side of the m-axis (the left side of the page) with respect to the a-axis.

[0220] In this case, since the first extension direction De1 intersects with the off direction Doff, the multiple first inversion columns 14 are inclined from the vertical axis toward the off direction Doff by approximately the off angle θoff in the cross-sectional view seen from the a-plane of the SiC single crystal and in the cross-sectional view seen from the m-plane of the SiC single crystal.

[0221] The first extension direction De1 forms a first extension angle θ1 with the a-axis when the a-axis is set as a reference (0°). The absolute value of the first extension angle θ1 may be greater than 0° and less than 90°. The first extension angle θ1 may have a value belonging to any one of the following ranges: greater than 0° and less than 18°, 18° or greater but less than 36°, 36° or greater but less than 54°, 54° or greater but less than 72°, and 72° or greater but less than 90°.

[0222] The absolute value of the first extension angle θ1 is typically set to a value belonging to any one of the ranges of 30°±5°, 45°±5°, and 60°±5°. Fig. 12A shows a layout example in which the absolute value of the first extension angle θ1 is approximately 45°, Fig. 12B shows a layout example in which the absolute value of the first extension angle θ1 is approximately 30°, and Fig. 12C shows a layout example in which the absolute value of the first extension angle θ1 is approximately 60°.

[0223] 11 and 12A to 12C, the first arrangement direction Da1 of the second inverting columns 16 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 of the second inverting columns 16 may be a direction other than the a-axis direction and the m-axis direction. In other words, the second inverting columns 16 may intersect both the a-axis direction and the m-axis direction. In this example, the second inverting columns 16 are inclined toward the other side of the m-axis (the right side of the paper) with respect to the a-axis.

[0224] In this case, since the second extension direction De2 intersects with the off direction Doff, the multiple second inversion columns 16 are inclined by approximately the off angle θoff from the vertical axis toward the off direction Doff in the cross-sectional views seen from the a-plane and the m-plane of the SiC single crystal.

[0225] When the a-axis is set as a reference (0°), the second extension direction De2 forms a second extension angle θ2 with the a-axis. When the first extension angle θ1 is defined as a "positive value," the second extension angle θ2 is a "negative value." On the other hand, when the first extension angle θ1 is defined as a "negative value," the second extension angle θ2 is a "positive value."

[0226] The absolute value of the second extension angle θ2 may be greater than 0° and less than 90°. The second extension angle θ2 may have a value that belongs to any one of the ranges of greater than 0° and less than 18°, 18° or more and less than 36°, 36° or more and less than 54°, 54° or more and less than 72°, and 72° or more and less than 90°.

[0227] The absolute value of the second extension angle θ2 is typically set to a value belonging to any one of the ranges of 30°±5°, 45°±5°, and 60°±5°. The absolute value of the second extension angle θ2 is preferably approximately equal to the absolute value of the first extension angle θ1.

[0228] That is, it is preferable that the second inverting columns 16 have a layout that is substantially line-symmetrical with the first inverting columns 14 about the a-axis in a plan view per unit area (i.e., a partial plan view). In other words, it is preferable that the second inverting columns 16 have a layout that is substantially point-symmetrical with the first inverting columns 14 about the vertical axis in a plan view per unit area (i.e., a partial plan view).

[0229] FIG. 12A shows a layout example in which the absolute value of the second extension angle θ2 is approximately 45° (≒θ1), FIG. 12B shows a layout example in which the absolute value of the second extension angle θ2 is approximately 30° (≒θ1), and FIG. 12C shows a layout example in which the absolute value of the second extension angle θ2 is approximately 60° (≒θ1).

[0230] 12A , the second inverted columns 16 extend in a direction intersecting both the a-axis direction and the m-axis direction, and are perpendicular to the first inverted columns 14. The sum of the absolute value of the first extension angle θ1 and the absolute value of the second extension angle θ2 is approximately a right angle (approximately 90°).

[0231] 12B , the second inverted columns 16 extend in a direction intersecting both the a-axis direction and the m-axis direction and non-orthogonally intersect the first inverted columns 14. The sum of the absolute value of the first extension angle θ1 and the absolute value of the second extension angle θ2 is an acute angle (approximately 60°).

[0232] 12C , the second inverted columns 16 extend in a direction intersecting both the a-axis direction and the m-axis direction and intersect non-orthogonally with the first inverted columns 14. The sum of the absolute value of the first extension angle θ1 and the absolute value of the second extension angle θ2 is an obtuse angle (approximately 120°).

[0233] Of course, the absolute value of the second extension angle θ2 may be greater than or less than the absolute value of the first extension angle θ1. That is, the second inverting columns 16 may have a layout that is asymmetrical with the first inverting columns 14 about the a-axis in a plan view per unit area (i.e., a partial plan view). In other words, the second inverting columns 16 may have a layout that is asymmetrical with the first inverting columns 14 about the vertical axis in a plan view per unit area (i.e., a partial plan view).

[0234] 13A to 13F , first to sixth embodiments of the plurality of first reversing columns 14 and the plurality of second reversing columns 16 are shown below. The plurality of first reversing columns 14 and the plurality of second reversing columns 16 according to the first to third basic embodiments may have at least one of the plurality of features shown in the first to sixth embodiments. Furthermore, the plurality of first reversing columns 14 and the plurality of second reversing columns 16 according to the first to third basic embodiments may have a combination of a plurality (two or more) of the features shown in the first to sixth embodiments.

[0235] 13A is a cross-sectional perspective view showing a plurality of first inversion columns 14 and a plurality of second inversion columns 16 according to the first embodiment. Referring to FIG. 13A , the SiC semiconductor device 1A includes, in addition to the plurality of first inversion columns 14 and the plurality of second inversion columns 16, an n-type inversion intermediate column 18 interposed between the first inversion columns 14 and the second inversion columns 16.

[0236] The multiple inverted intermediate columns 18 are formed in the surface layer portion on the upper end side of the first layer 8 so as to be positioned at multiple intersections between at least the multiple first inverted columns 14 and the multiple second inverted columns 16, and overlap the corresponding first inverted columns 14 and second inverted columns 16 in the stacking direction. In this embodiment, the multiple inverted intermediate columns 18 are arranged at intervals in the first arrangement direction Da1 so as to overlap the multiple first inverted columns 14 in a one-to-one correspondence in the stacking direction, and are each formed in a band shape extending in the first extension direction De1.

[0237] In this example, the first arrangement direction Da1 is the a-axis direction (first direction X), and the first extension direction De1 is the m-axis direction (second direction Y). Of course, the arrangement direction and extension direction of the multiple reversing intermediate columns 18 are changed depending on the first arrangement direction Da1 and first extension direction De1 of the multiple first reversing columns 14. Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Furthermore, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.

[0238] The multiple inversion intermediate columns 18, together with the multiple first inversion columns 14, are drawn from the active region 10 to the outer periphery region 11. That is, the multiple inversion intermediate columns 18 are drawn from a portion of the first layer 8 located within the active region 10 to a portion of the first layer 8 located within the outer periphery region 11. The multiple inversion intermediate columns 18 are also arranged at intervals in the first array direction Da1 in the outer periphery region 11, and are each formed in a strip shape extending in the first extension direction De1.

[0239] Furthermore, the multiple inverted intermediate columns 18 extend from the outer peripheral region 11 toward either or both of the first side surface 5A and the third side surface 5C (both in this embodiment), and each have a portion exposed from either or both of the first side surface 5A and the third side surface 5C (both in this embodiment).

[0240] The multiple inverted intermediate columns 18 are formed in the first layer 8 in a region between the upper end of the first layer 8 and the upper end of the first inverted column 14. The multiple inverted intermediate columns 18 are preferably located closer to the upper end of the first layer 8 than the intermediate portion of the thickness range of the first layer 8. The multiple inverted intermediate columns 18 may be exposed from the upper end of the first layer 8, or may be formed at intervals from the upper end to the lower end of the first layer 8. Each inverted intermediate column 18 may be formed in the shape of a horizontally elongated pillar extending horizontally in a cross-sectional view. Of course, each inverted intermediate column 18 may also be formed in the shape of a vertically elongated pillar extending in the vertical direction Z.

[0241] The inversion intermediate columns 18 form charge-balanced intermediate pn junctions together with the first non-inversion columns 15. That is, the inversion intermediate columns 18 form part of the first superjunction structure SJ1 together with the first non-inversion columns 15. The charge-balanced state means that, for adjacent inversion intermediate columns 18, the depletion layer extending from one intermediate pn junction and the depletion layer extending from the other intermediate pn junction are connected within the first non-inversion columns 15.

[0242] Each inversion intermediate column 18 may include a single or multiple n-type region elements that form a peak value (peak portion) of the concentration gradient. When each inversion intermediate column 18 is composed of a single region element, the single region element is formed in the region between the upper end of the first layer 8 and the upper end of the first inversion column 14, and is connected to the upper end of the first inversion column 14.

[0243] When each inverted intermediate column 18 is composed of multiple area elements, the multiple area elements are formed at different depth positions in the area between the upper end of the first layer 8 and the upper end of the first inverted column 14. In this case, the multiple area elements are formed so as to be connected to each other in the stacking direction. Furthermore, at least the lowest area element is connected to the upper end of the first inverted column 14.

[0244] The region element is a random impurity region introduced into a surface portion of the first layer 8 by random implantation into the first layer 8 (see also FIG. 7 ). That is, the region element is not formed in the second layer 9. The region element has a thickness along the first axial channel CH1 that is less than the first region thickness TR1 of the first inversion column 14. The thickness of the region element is also less than the second region thickness TR2 of the second inversion column 16.

[0245] Unlike the first inversion column 14 and the like, the region element does not have a gradual portion 22 having a thickness of 0.5 μm or more, and has a concentration gradient including a gradually increasing portion 20, a peak portion 21, and a gradually decreasing portion 23 within a range of 0.5 μm. When each inversion intermediate column 18 includes multiple region elements, each inversion intermediate column 18 has multiple peak portions 21 (peak value P) in the thickness direction of the first layer 8 according to the number of multiple region elements. The region element has a density of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration may have the following peak value P:

[0246] The n-type impurity concentration of the inversion intermediate column 18 is preferably adjusted by at least one pentavalent element. The pentavalent element of the inversion intermediate column 18 may be the same as or different from the pentavalent element of the first inversion column 14, etc. The pentavalent element of the inversion intermediate column 18 may be at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The pentavalent element of the inversion intermediate column 18 is preferably nitrogen or phosphorus.

[0247] Each of the multiple inverted intermediate columns 18 has an intermediate width WM. The intermediate width WM is the width along the first arrangement direction Da1. The intermediate width WM is preferably less than the first thickness T1 of the first layer 8. Of course, the intermediate width WM may be equal to or greater than the first thickness T1. The intermediate width WM is preferably less than the second thickness T2 of the second layer 9. Of course, the intermediate width WM may be equal to or greater than the second thickness T2.

[0248] The intermediate width WM is preferably approximately equal to the first width W1 of the first reversing column 14. Of course, the intermediate width WM may be equal to or greater than the first width W1, or may be less than the first width W1. The intermediate width WM is preferably 1 μm or greater. The intermediate width WM is preferably 5 μm or less.

[0249] The intermediate width WM may have a value belonging to any one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0250] Each of the multiple inverted intermediate columns 18 has an intermediate thickness TM. The intermediate thickness TM is preferably equal to or greater than the distance between the upper end of the first layer 8 and the upper end of the first inverted column 14. The intermediate thickness TM may be 0.1 μm or more and 2 μm or less. The intermediate thickness TM may have a value belonging to any one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0251] The multiple reversing intermediate columns 18 are spaced apart at an intermediate pitch PM in the first arrangement direction Da1. The intermediate pitch PM is preferably approximately equal to the first pitch P1 of the first reversing columns 14. Of course, the intermediate pitch PM may be equal to or greater than the first pitch P1, or may be less than the first pitch P1. For clarity, FIG. 13A shows the intermediate pitch PM as being greater than the first pitch P1.

[0252] The intermediate pitch PM may be 0.1 μm or more and 5 μm or less. The intermediate pitch PM may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The intermediate pitch PM is preferably 0.5 μm or more and 1.5 μm or less.

[0253] In this configuration, the second inverting column 16 preferably has an extension located within the first layer 8 and is connected to the inverting intermediate column 18 within the first layer 8. In other words, the second inverting column 16 is preferably electrically connected to the first inverting column 14 via the inverting intermediate column 18 within the first layer 8. In this case, the second inverting column 16, together with the first inverting column 14 and the inverting intermediate column 18, forms a single three-dimensional lattice-shaped inverting column that extends continuously in the stacking direction.

[0254] Of course, the extension of the second inverting column 16 may be connected to both the inverting intermediate column 18 and the first inverting column 14 within the first layer 8. In a configuration including the inverting intermediate column 18, the concentration gradient in the region between the first inverting column 14 and the second inverting column 16 is alleviated by the inverting intermediate column 18, improving the accuracy of charge balance.

[0255] In this example, the multiple reversing intermediate columns 18 are arranged in the first arrangement direction Da1 and formed in a strip shape extending in the first extension direction De1. However, the multiple reversing intermediate columns 18 may be arranged in the second arrangement direction Da2 and formed in a strip shape extending in the second extension direction De2. In this case, the multiple second reversing columns 16 may be connected to the multiple reversing intermediate columns 18 in a one-to-one correspondence.

[0256] 13B is a cross-sectional perspective view showing a plurality of first inversion columns 14 and a plurality of second inversion columns 16 according to the second embodiment. Referring to FIG. 13B , the SiC semiconductor device 1A includes, in addition to the plurality of first inversion columns 14 and the plurality of second inversion columns 16, a p-type non-inversion intermediate column 19 interposed between the first non-inversion column 15 and the second non-inversion column 17.

[0257] The non-inverting intermediate columns 19 are formed in the surface layer portion on the upper end side of the first layer 8 so as to be positioned at multiple intersections between at least the multiple first non-inverting columns 15 and the multiple second non-inverting columns 17, and overlap the corresponding first non-inverting columns 15 and second non-inverting columns 17 in the stacking direction. In this embodiment, the non-inverting intermediate columns 19 are arranged at intervals in the first arrangement direction Da1 so as to overlap the multiple first non-inverting columns 15 in a one-to-one correspondence in the stacking direction, and are each formed in a band shape extending in the first extension direction De1.

[0258] In this example, the first arrangement direction Da1 is the a-axis direction (first direction X), and the first extension direction De1 is the m-axis direction (second direction Y). Of course, the arrangement direction and extension direction of the multiple non-reversing intermediate columns 19 are changed depending on the first arrangement direction Da1 and first extension direction De1 of the multiple first non-reversing columns 15. Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Alternatively, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.

[0259] The non-inversion intermediate columns 19, together with the first non-inversion columns 15, are drawn from the active region 10 to the outer circumferential region 11. That is, the non-inversion intermediate columns 19 are drawn from a portion of the first layer 8 located within the active region 10 to a portion of the first layer 8 located within the outer circumferential region 11. The non-inversion intermediate columns 19 are also arranged at intervals in the first array direction Da1 in the outer circumferential region 11, and are each formed in a strip shape extending in the first extension direction De1.

[0260] Furthermore, the multiple non-inverted intermediate columns 19 extend from the outer peripheral region 11 toward either or both of the first side surface 5A and the third side surface 5C (both in this embodiment), and each have a portion exposed from either or both of the first side surface 5A and the third side surface 5C (both in this embodiment).

[0261] The non-inverting intermediate columns 19 are formed in the first layer 8 in a region between the upper end of the first layer 8 and the upper end of the first non-inverting column 15. The non-inverting intermediate columns 19 are preferably located closer to the upper end of the first layer 8 than to the middle of the thickness range of the first layer 8. The non-inverting intermediate columns 19 may be exposed from the upper end of the first layer 8, or may be formed at intervals from the upper end to the lower end of the first layer 8. Each non-inverting intermediate column 19 may be formed in the shape of a horizontally elongated pillar extending horizontally in a cross-sectional view. Of course, each non-inverting intermediate column 19 may also be formed in the shape of a vertically elongated pillar extending in the vertical direction Z.

[0262] The non-inversion intermediate columns 19 form charge-balanced intermediate pn junctions together with the first inversion columns 14. That is, the non-inversion intermediate columns 19 form part of a first superjunction structure SJ1 together with the first inversion columns 14. The charge-balanced state refers to a state in which, for adjacent non-inversion intermediate columns 19, the depletion layer extending from one intermediate pn junction and the depletion layer extending from the other intermediate pn junction are connected within the first inversion columns 14.

[0263] Each non-inverting intermediate column 19 may include a single or multiple p-type region elements that form a peak value (peak portion) of the concentration gradient. When each non-inverting intermediate column 19 is composed of a single region element, the single region element is formed in the region between the upper end of the first layer 8 and the upper end of the first non-inverting column 15 and is connected to the upper end of the first non-inverting column 15.

[0264] When each non-inverted intermediate column 19 is composed of multiple area elements, the multiple area elements are formed at different depth positions in the area between the upper end of the first layer 8 and the upper end of the first non-inverted column 15. In this case, the multiple area elements are formed so as to be connected to each other in the stacking direction. Furthermore, at least the lowest area element is connected to the upper end of the first non-inverted column 15.

[0265] The region elements are formed of random impurity regions introduced into the surface layer of the first layer 8 by random implantation into the first layer 8 (see also FIG. 7 ). That is, the region elements are not formed in the second layer 9. Furthermore, the region elements have a thickness in the direction along the first axial channel CH1 that is less than the first region thickness TR1 of the first non-inverted column 15. Furthermore, the thickness of the region elements is less than the second region thickness TR2 of the second non-inverted column 17.

[0266] Unlike the first non-inverted columns 15 and the like, the region elements do not have gradual portions 22 having a thickness of 0.5 μm or more, and have a concentration gradient including gradually increasing portions 20, peak portions 21, and gradually decreasing portions 23 within a range of 0.5 μm. When each non-inverted intermediate column 19 includes multiple region elements, each non-inverted intermediate column 19 has multiple peak portions 21 (peak values ​​P) in the thickness direction of the first layer 8 according to the number of multiple region elements.

[0267] The area element is 1 x 10 １５ cm －３ 1x10 or more １８ cm －３ The following p-type impurity concentration may be present as a peak value P: The p-type impurity concentration of the non-inverted intermediate column 19 is preferably adjusted with at least one pentavalent element.

[0268] The trivalent element in the non-inverting intermediate column 19 may be the same as the trivalent element in the first non-inverting column 15, etc., or may be a different type from the trivalent element in the first non-inverting column 15, etc. The trivalent element in the non-inverting intermediate column 19 may be at least one of boron, aluminum, gallium, and indium. The multiple non-inverting intermediate columns 19 may have the aforementioned intermediate width W M, intermediate thickness TM, and intermediate pitch P M.

[0269] In such a configuration, the second non-inverting column 17 preferably has an extension located within the first layer 8 and is connected to the non-inverting intermediate column 19 within the first layer 8. That is, the second non-inverting column 17 is preferably electrically connected to the first non-inverting column 15 via the non-inverting intermediate column 19 within the first layer 8. In this case, the second non-inverting column 17, together with the first non-inverting column 15 and the non-inverting intermediate column 19, forms a single three-dimensional lattice-shaped inverting column that extends continuously in the stacking direction.

[0270] Of course, the extension of the second non-inverting column 17 may be connected to both the non-inverting intermediate column 19 and the first non-inverting column 15 in the first layer 8. In a configuration including the non-inverting intermediate column 19, the concentration gradient in the region between the first non-inverting column 15 and the second non-inverting column 17 is alleviated by the non-inverting intermediate column 19, improving the accuracy of charge balance.

[0271] In this example, the non-inverting intermediate columns 19 are arranged in the first arrangement direction Da1 and formed in a strip shape extending in the first extension direction De1. However, the non-inverting intermediate columns 19 may be arranged in the second arrangement direction Da2 and formed in a strip shape extending in the second extension direction De2. In this case, the non-inverting intermediate columns 19 may be connected to the second non-inverting columns 17 in a one-to-one correspondence.

[0272] 13C is a cross-sectional perspective view showing the first inverted columns 14 and the second inverted columns 16 according to the third embodiment. Referring to FIG. 13C , the SiC semiconductor device 1A has the first inverted columns 14 exposed from the upper end of the first layer 8 and the first non-inverted columns 15 exposed from the upper end of the first layer 8.

[0273] The first inversion column 14 may have a concentration gradient in which a part of the gradually increasing portion 20 is exposed from the upper end of the first layer 8. Of course, the first inversion column 14 may have a concentration gradient in which a part of the peak portion 21 is exposed from the upper end of the first layer 8. The first inversion column 14 may have a gradual portion 22 exposed from the upper end of the first layer 8. In this case, the first inversion column 14 has a peak value P at the upper end of the first layer 8 and a concentration gradient that gradually decreases toward the lower end of the first layer 8.

[0274] Similarly, the first non-inverted columns 15 (first impurity regions 12) may have a concentration gradient in which a part of the gradually increasing portion 20 is exposed from the upper end of the first layer 8. Of course, the first non-inverted columns 15 may have a concentration gradient in which a part of the peak portion 21 is exposed from the upper end of the first layer 8. The first non-inverted columns 15 may have a gradual portion 22 exposed from the upper end of the first layer 8. In this case, the first non-inverted columns 15 have a peak value P at the upper end of the first layer 8 and a concentration gradient that gradually decreases toward the lower end of the first layer 8.

[0275] The second inverting column 16 preferably has an extension located within the first layer 8 and is connected to the first inverting column 14 within the first layer 8. In a configuration in which the first inverting column 14 is exposed from the upper end of the first layer 8, the concentration gradient formed in the region between the first inverting column 14 and the second inverting column 16 is alleviated by the exposed portion of the first inverting column 14, improving the accuracy of charge balance.

[0276] The second non-inverting column 17 (second impurity region 13) preferably has an extension located in the first layer 8 and is connected to the first non-inverting column 15 in the first layer 8. In a configuration in which the first non-inverting column 15 is exposed from the upper end of the first layer 8, the concentration gradient formed in the region between the first non-inverting column 15 and the second non-inverting column 17 is alleviated by the exposed portion of the first non-inverting column 15, thereby improving the accuracy of charge balance.

[0277] This structure can be achieved by partially removing the upper end of the first layer 8 after the formation of the first inverted columns 14 (first non-inverted columns 15) until the increased portions 20 of the first inverted columns 14 (first non-inverted columns 15) disappear in part or in whole. For example, the upper end of the first layer 8 may be partially removed by a grinding method. The grinding method may be a mechanical polishing method and / or a chemical mechanical polishing method. In this case, the upper end of the first layer 8 comprises a ground surface, and the first inverted columns 14 are exposed from the ground surface. The second layer 9 is laminated on top of the ground surface of the first layer 8.

[0278] For example, the upper end of the first layer 8 may be partially removed by etching. The etching may be wet etching and / or dry etching. In this case, the upper end of the first layer 8 is an etched surface, and the first inverted columns 14 are exposed from the etched surface. The second layer 9 is laminated on the etched surface of the first layer 8.

[0279] 13D is a cross-sectional perspective view showing the first inverted columns 14 and the second inverted columns 16 according to the fourth embodiment. Referring to Fig. 13D, the SiC semiconductor device 1A has second inverted columns 16 exposed from the upper end (first main surface 3) of the second layer 9 and second non-inverted columns 17 exposed from the upper end (first main surface 3) of the second layer 9.

[0280] The second inversion column 16 may have a concentration gradient in which a part of the gradually increasing portion 20 is exposed from the upper end of the second layer 9. Of course, the second inversion column 16 may have a concentration gradient in which a part of the peak portion 21 is exposed from the upper end of the second layer 9. The second inversion column 16 may have a gradual portion 22 exposed from the upper end of the second layer 9. In this case, the second inversion column 16 has a peak value P at the upper end of the second layer 9 and a concentration gradient that gradually decreases toward the lower end of the second layer 9.

[0281] Similarly, the second non-inverted columns 17 (second impurity regions 13) may have a concentration gradient in which a part of the gradually increasing portion 20 is exposed from the upper end of the second layer 9. Of course, the second non-inverted columns 17 may have a concentration gradient in which a part of the peak portion 21 is exposed from the upper end of the second layer 9. The second non-inverted columns 17 may have a gradual portion 22 exposed from the upper end of the second layer 9. In this case, the second non-inverted columns 17 have a peak value P at the upper end of the second layer 9 and a concentration gradient that gradually decreases toward the lower end of the second layer 9.

[0282] Such a configuration is effective when a device structure is formed using the second layer 9 (first main surface 3) and the electrical characteristics of the device structure are adjusted using the second inverted columns 16 and the second non-inverted columns 17.

[0283] This structure can be achieved by partially removing the upper end of the second layer 9 after the second inverted columns 16 (second non-inverted columns 17) are formed, until the increased portions 20 of the second inverted columns 16 (second non-inverted columns 17) disappear in part or in whole. For example, the upper end of the second layer 9 may be partially removed by a grinding method. The grinding method may be a mechanical polishing method and / or a chemical mechanical polishing method. In this case, the upper end of the second layer 9 is formed as a ground surface, and the second inverted columns 16 are exposed from the ground surface.

[0284] For example, the upper end of the second layer 9 may be partially removed by etching. The etching may be wet etching and / or dry etching. In this case, the upper end of the second layer 9 is an etched surface, and the second inverted columns 16 are exposed from the etched surface.

[0285] 13E is a cross-sectional perspective view showing the first inverting column 14 and the second inverting column 16 according to the fifth embodiment. Referring to Fig. 13E, the stacked portion 7 may have a stacked structure including a buffer layer 26, a second layer 9, and a second layer 9 stacked in this order from the base layer 6 side. The buffer layer 26 may also be referred to as a "buffer SiC layer," a "buffer region," or the like.

[0286] The buffer layer 26 includes SiC single crystal and has n-type conductivity. The buffer layer 26 is stacked on the base layer 6. The buffer layer 26 extends horizontally in a layered manner, forming the middle portion of the chip 2 and part of the first to fourth side surfaces 5A to 5D. The buffer layer 26 is made of an epitaxial layer (i.e., a SiC epitaxial layer) grown from the base layer 6.

[0287] The buffer layer 26 has a lower end and an upper end. The lower end of the buffer layer 26 is the crystal growth starting point, and the upper end of the buffer layer 26 is the crystal growth end point. Because the buffer layer 26 is grown continuously from the base layer 6, the lower end of the buffer layer 26 coincides with the upper end of the base layer 6. The boundary between the base layer 6 and the buffer layer 26 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements. The buffer layer 26 has an off-direction Doff and an off-angle θoff that are approximately the same as the off-direction Doff and the off-angle θoff of the base layer 6.

[0288] The buffer layer 26 has a buffer axis channel CHBu extending along the stacking direction. The buffer axis channel CHBu is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the buffer layer 26, and is surrounded by atomic rows along a crystal axis extending in the stacking direction (crystal growth direction).

[0289] In other words, the buffer axis channel CHBu is a region in which a region in which atomic rows are sparse extends in the stacking direction and in which atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in plan view. The buffer axis channel CHBu is preferably a region surrounded by atomic rows along low-index crystal axes among the crystal axes.

[0290] In this embodiment, the buffer axis channel CHBu is formed by a region surrounded by atomic rows aligned along the c-axis of the SiC single crystal. That is, the buffer axis channel CHBu extends along the c-axis and has an off-direction Doff and an off-angle θoff. In other words, the buffer axis channel CHBu is inclined from the vertical axis toward the off-direction Doff by the off-angle θoff.

[0291] The n-type impurity concentration of the buffer layer 26 is preferably lower than the n-type impurity concentration of the base layer 6. The buffer layer 26 has a dopant concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３The n-type impurity concentration of the buffer layer 26 may have a peak value of the following: The n-type impurity concentration of the buffer layer 26 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the buffer layer 26 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0292] In this embodiment, the n-type impurity concentration of the buffer layer 26 is adjusted by nitrogen. The buffer layer 26 may have an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the buffer layer 26 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The buffer layer 26 preferably contains a pentavalent element other than phosphorus.

[0293] The n-type impurity concentration of the buffer layer 26 is preferably adjusted by at least nitrogen. When the buffer layer 26 contains two or more pentavalent elements, the buffer layer 26 preferably contains nitrogen and a pentavalent element other than nitrogen. In this case, the buffer layer 26 preferably contains either arsenic or antimony, or both, as the pentavalent element other than phosphorus and nitrogen.

[0294] The buffer layer 26 has a buffer thickness TBu. The buffer thickness TBu is preferably less than the base thickness TB. The buffer thickness TBu is preferably 1 μm or more. The buffer thickness TBu is preferably 5 μm or less. The buffer thickness TBu may have a value belonging to any one of the following ranges: 1 μm or more to 1.5 μm or less, 1.5 μm or more to 2 μm or less, 2 μm or more to 2.5 μm or less, 2.5 μm or more to 3 μm or less, 3 μm or more to 3.5 μm or less, 3.5 μm or more to 4 μm or less, 4 μm or more to 4.5 μm or less, and 4.5 μm or more to 5 μm or less.

[0295] In this embodiment, the first layer 8 is stacked on the buffer layer 26, and the second layer 9 is stacked on the first layer 8. The first layer 8 is made of an epitaxial layer (i.e., a SiC epitaxial layer) crystal-grown starting from the buffer layer 26, and has n-type conductivity. Therefore, the first layer 8 has an off-direction Doff and an off-angle θoff that substantially coincide with the off-direction Doff and the off-angle θoff of the buffer layer 26. In addition, the first axis channel CH1 substantially coincides with the buffer axis channel CHBu.

[0296] The first thickness T1 of the first layer 8 is preferably greater than the buffer thickness TBu. Of course, the first thickness T1 may be less than the buffer thickness TBu. Alternatively, the first thickness T1 may be approximately equal to the buffer thickness TBu. The second thickness T2 of the second layer 9 is preferably greater than the buffer thickness TBu. Of course, the second thickness T2 may be less than the buffer thickness TBu. Alternatively, the second thickness T2 may be approximately equal to the buffer thickness TBu.

[0297] The lower end of the first inversion column 14 may be formed at a distance from the lower end toward the upper end of the first layer 8, and may face the buffer layer 26 across a part (lower end) of the first layer 8. In other words, the entire area of ​​the first inversion column 14 (the gradually increasing portion 20, the peak portion 21, the gradual portion 22, and the gradually decreasing portion 23) may be located within the first layer 8.

[0298] The lower end of the first inverted column 14 may have an extension that crosses the boundary between the buffer layer 26 and the first layer 8 and is located within the buffer layer 26. Since the first axial channel CH1 is substantially aligned with the buffer axial channel CHBu, the extension of the first inverted column 14 is formed within the buffer layer 26 along the buffer axial channel CHBu.

[0299] The extending portion of the first inverted column 14 is preferably located on the upper end side of the buffer layer 26 relative to the intermediate portion of the thickness range of the buffer layer 26. The extending portion of the first inverted column 14 includes the gradually tapered portion 23. Of course, the extending portion of the first inverted column 14 may include the gradually tapered portion 23 and part of the gradual portion 22.

[0300] 13F is a cross-sectional perspective view showing the first inverted columns 14 and the second inverted columns 16 according to the sixth embodiment. Referring to Fig. 13F, the stacked portion 7 may include a SiC single-crystalline n-type top layer 30 stacked on the second layer 9. The top layer 30 is formed to separate the first main surface 3 from the plurality of second inverted columns 16 and the plurality of second non-inverted columns 17.

[0301] That is, the top layer 30 also forms at least a part of the region between the first main surface 3 and the upper ends of the plurality of second inverted columns 16. The top layer 30 may also be considered to form the upper end of the second layer 9. In this example, the top layer 30 has n-type conductivity, but the conductivity type of the top layer 30 can be adjusted appropriately depending on the properties of the device structure to be formed on the first main surface 3. Therefore, the conductivity type of the top layer 30 is not necessarily limited to n-type, and may also be p-type.

[0302] The top layer 30 is stacked on the second layer 9. The top layer 30 extends horizontally in a layered manner, forming the first main surface 3 and forming parts of the first to fourth side surfaces 5A to 5D. The top layer 30 is made of an epitaxial layer (i.e., a SiC epitaxial layer) crystal-grown starting from the second layer 9.

[0303] Because the top layer 30 is continuously crystal-grown from the second layer 9, the bottom end of the top layer 30 coincides with the top end of the second layer 9. The boundary between the top layer 30 and the second layer 9 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements. The top layer 30 has an off-direction Doff and an off-angle θoff that are substantially identical to the off-direction Doff and the off-angle θoff of the second layer 9.

[0304] The top layer 30 has a top axis channel CHT along the stacking direction. The top axis channel CHT is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the top layer 30, and is surrounded by atomic rows along a crystal axis extending in the stacking direction (crystal growth direction).

[0305] That is, the top axis channel CHT is a region in which a region in which atomic rows are sparse extends in the stacking direction and in which atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in plan view. The top axis channel CHT is preferably a region surrounded by atomic rows along low-index crystal axes among the crystal axes.

[0306] In this embodiment, the top axis channel CHT is composed of a region surrounded by atomic rows along the c-axis of the SiC single crystal. That is, the top axis channel CHT extends along the c-axis and has an off-direction Doff and an off-angle θoff. In other words, the top axis channel CHT is inclined from the vertical axis toward the off-direction Doff by the off-angle θoff.

[0307] The n-type impurity concentration of the top layer 30 is preferably lower than the n-type impurity concentration of the base layer 6. The top layer 30 has a dopant concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the top layer 30 may have a peak value of the following n-type impurity concentration. The n-type impurity concentration of the top layer 30 may be approximately equal to the n-type impurity concentration of the first layer 8 (second layer 9). The n-type impurity concentration of the top layer 30 may be approximately constant in the thickness direction. Of course, the n-type impurity concentration of the top layer 30 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0308] In this embodiment, the n-type impurity concentration of the top layer 30 is adjusted by nitrogen. The top layer 30 may have an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the top layer 30 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The top layer 30 preferably contains a pentavalent element other than phosphorus.

[0309] The n-type impurity concentration of the top layer 30 is preferably adjusted by at least nitrogen. When the top layer 30 contains two or more pentavalent elements, the top layer 30 preferably contains nitrogen and a pentavalent element other than nitrogen. In this case, the top layer 30 preferably contains either or both of arsenic and antimony as the pentavalent element other than phosphorus and nitrogen.

[0310] The top layer 30 has a top thickness TT. The top thickness TT is preferably less than the base thickness TB. The top thickness TT is preferably less than the first thickness T1 (second thickness T2). Of course, the top thickness TT may be equal to or greater than the first thickness T1 (second thickness T2).

[0311] The top thickness TT may be 0.1 μm or more and 5 μm or less. The top thickness TT may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0312] Below, examples of the device structure formed in the active region 10 are shown. FIG. 14 is a plan view showing a main part of the active region 10. FIG. 15 is a cross-sectional perspective view showing a gate structure 35 according to a first embodiment. FIG. 15 illustrates a configuration to which the first basic embodiment (see FIG. 5) is applied. Of course, a configuration in which one or more of the first to sixth embodiment examples (see FIGS. 13A to 13F) are applied to any one of the first to third basic embodiments may also be applied.

[0313] 14 and 15 , in this embodiment, SiC semiconductor device 1A includes a metal insulator semiconductor (MIS) structure 31 as an example of a device structure formed in active region 10. MIS structure 31 may also be referred to as a “field effect transistor structure.”

[0314] Here, an example is shown in which the MIS structure 31 is formed on the second layer 9 (first main surface 3). When the above-described top layer 30 is formed, the MIS structure 31 is formed on the top layer 30 (first main surface 3). This configuration can be obtained by replacing "second layer 9" with "top layer 30" as necessary in the following description. The following configurations will be described as components of the SiC semiconductor device 1A, but they are also components of the MIS structure 31.

[0315] The SiC semiconductor device 1A includes a plurality of p-type body regions 32 formed in the active region 10. The plurality of body regions 32 are formed in a surface layer portion of the first main surface 3 so as to overlap the plurality of second non-inversion columns 17 in the stacking direction. In this embodiment, the plurality of body regions 32 are arranged at intervals in the second array direction Da2 so as to overlap the plurality of second non-inversion columns 17 in a one-to-one correspondence in the stacking direction, and are each formed in a strip shape extending in the second extension direction De2.

[0316] In this example, the second arrangement direction Da2 is the m-axis direction (second direction Y), and the second extension direction De2 is the a-axis direction (first direction X). Of course, the arrangement direction and extension direction of the body regions 32 are changed depending on the second arrangement direction Da2 and second extension direction De2 of the second non-inverted columns 17 (second inverted columns 16). Therefore, the second arrangement direction Da2 may be the a-axis direction, and the second extension direction De2 may be the m-axis direction. Alternatively, the second arrangement direction Da2 may be a direction other than the a-axis direction and the m-axis direction, and the second extension direction De2 may be a direction other than the a-axis direction and the m-axis direction.

[0317] When the second non-inverted columns 17 are formed at intervals from the first main surface 3, the body regions 32 are respectively formed in regions between the first main surface 3 and the upper ends of the second non-inverted columns 17. The body regions 32 are preferably formed on the first main surface 3 side of the intermediate portion of the thickness range of the second layer 9, and are exposed from the first main surface 3. The body regions 32 are preferably connected to the corresponding second non-inverted columns 17 (upper ends).

[0318] Each of the body regions 32 is formed to be wider than the second non-inversion columns 17 immediately below it, and is formed at intervals from the adjacent second non-inversion columns 17 toward the second non-inversion columns 17 immediately below it. The body regions 32 expose part of the first layer 8 and / or part of the second inversion columns 16 from a region of the first main surface 3 between the adjacent second non-inversion columns 17.

[0319] The body regions 32 are formed of random impurity regions introduced into the surface portion of the second layer 9 by random implantation into the second layer 9 (see also FIG. 7 ). Therefore, the body regions 32 have a thickness along the second axial channel CH2 that is less than the second region thickness TR2 of the second non-inversion column 17. The thickness of the body regions 32 is less than the first region thickness TR1 of the first inversion column 14.

[0320] Unlike the second non-inverted columns 17 and the like, the body regions 32 do not have a gradual portion 22 having a thickness of 0.5 μm or more, but have a concentration gradient including a gradually increasing portion 20, a peak portion 21, and a gradually decreasing portion 23 within a range of 0.5 μm. １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0321] The p-type impurity concentrations of the body regions 32 are preferably adjusted by at least one trivalent element. The trivalent element in the body regions 32 may be the same as or different from the trivalent element in the second non-inversion columns 17, etc. The trivalent element in the body regions 32 may be at least one of boron, aluminum, gallium, and indium.

[0322] The SiC semiconductor device 1A includes one or more n-type source regions 33 formed in the surface layer portions of the plurality of body regions 32 in the active region 10. In this embodiment, a plurality of (two in this embodiment) source regions 33 are formed at intervals in the surface layer portion of each body region 32. The plurality of source regions 33 have an n-type impurity concentration higher than the n-type impurity concentration of the second layer 9 (the plurality of second non-inversion columns 17). The plurality of source regions 33 have an n-type impurity concentration of 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0323] The plurality of source regions 33 may each extend in a strip shape along the extension direction of the corresponding body region 32. Of course, the plurality of source regions 33 may be formed at intervals along the extension direction of the corresponding body region 32. The plurality of source regions 33 are formed at intervals from the bottom of the corresponding body region 32 toward the first main surface 3, and are formed at intervals inward from the periphery of the corresponding body region 32. The plurality of source regions 33, together with the plurality of second inversion columns 16, define a channel (current path) along the first main surface 3 at the periphery of the body region 32.

[0324] The SiC semiconductor device 1A includes one or more p-type contact regions 34 formed in the surface layer portions of the plurality of body regions 32 in the active region 10. The contact regions 34 may also be referred to as "back gate regions." In this embodiment, one contact region 34 is formed in a region between the plurality of adjacent source regions 33 in the surface layer portion of each body region 32.

[0325] The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 32. The p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of second inversion columns 16. The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of second inversion columns 16. １８ cm －３ 1x10 or more ２１ cm －３The p-type impurity concentration may have the following peak value:

[0326] The plurality of contact regions 34 may each extend in a strip shape along the extension direction of the corresponding body region 32. Of course, the plurality of contact regions 34 may also be formed at intervals along the extension direction of the corresponding body region 32. The plurality of contact regions 34 are formed at intervals from the bottom of the corresponding body region 32 toward the first main surface 3, and are formed at intervals inward from the peripheral edge of the corresponding body region 32.

[0327] The SiC semiconductor device 1A includes a plurality of planar electrode type gate structures 35 arranged on the first main surface 3 in the active region 10. The gate structures 35 may also be referred to as "planar gate structures." The plurality of gate structures 35 are arranged at intervals on the first main surface 3 so as to overlap at least one body region 32 (channel) in the stacking direction. A gate potential is applied to the plurality of gate structures 35 as a control potential. The plurality of gate structures 35 control the inversion and non-inversion of the channel (current path) in the body region 32 in response to the gate potential.

[0328] In this embodiment, the gate structures 35 are arranged at intervals in the second arrangement direction Da2 and are each formed in a strip shape extending in the second extension direction De2. In this example, the second arrangement direction Da2 is the m-axis direction (second direction Y), and the second extension direction De2 is the a-axis direction (first direction X).

[0329] Of course, the arrangement direction and extension direction of the multiple gate structures 35 are changed depending on the second arrangement direction Da2 and second extension direction De2 of the multiple second inversion columns 16 (body regions 32). Therefore, the second arrangement direction Da2 may be the a-axis direction, and the second extension direction De2 may be the m-axis direction. Alternatively, the second arrangement direction Da2 may be a direction other than the a-axis direction and the m-axis direction, and the second extension direction De2 may be a direction other than the a-axis direction and the m-axis direction.

[0330] The plurality of gate structures 35 are arranged shifted from the plurality of second non-inversion columns 17 toward the plurality of second inversion columns 16, and overlap the plurality of second inversion columns 16 in a one-to-one correspondence in the stacking direction. In this embodiment, the plurality of gate structures 35 are arranged so as to straddle two adjacent body regions 32, and cover the plurality of source regions 33 located in one and the other body regions 32, respectively.

[0331] Each of the plurality of gate structures 35 has a stacked structure including a gate insulating film 36 disposed on the first main surface 3 and a gate electrode 37 disposed on the gate insulating film 36. The gate insulating film 36 may include a silicon oxide film. The gate electrode 37 may include conductive polysilicon.

[0332] Either or both of the gate insulating film 36 and the gate electrode 37 may be arranged so as to partially overlap the second non-inverting columns 17 in the stacking direction. Of course, either or both of the gate insulating film 36 and the gate electrode 37 may be arranged so as not to partially overlap the second non-inverting columns 17 in the stacking direction.

[0333] The configuration of the outer peripheral region 11 side will be described below. Fig. 16 is a perspective view showing the configuration of the outer peripheral region 11. Fig. 17A is a cross-sectional view in the first direction X showing a main part of the outer peripheral region 11. Fig. 17B is a cross-sectional view in the second direction Y showing a main part of the outer peripheral region 11. In Fig. 16, the multiple first reversing columns 14 and the multiple second reversing columns 16 are omitted from illustration.

[0334] The SiC semiconductor device 1A includes at least one (preferably two to 20) p-type field region 38 formed in the surface layer portion of the first main surface 3 in the peripheral region 11. The number of the multiple field regions 38 is typically four to eight. The multiple field regions 38 are formed in an electrically floating state and relieve the electric field within the chip 2 at the periphery of the first main surface 3. The number, width, depth, p-type impurity concentration, etc. of the field region 38 are arbitrary and can take various values ​​depending on the electric field to be relieved.

[0335] The multiple field regions 38 are formed at intervals in the region between the periphery of the chip 2 and the active region 10. The multiple field regions 38 are formed in strip shapes extending along the active region 10 in a plan view. Each of the multiple field regions 38 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y. In this embodiment, the multiple field regions 38 are formed in an annular shape (specifically, a rectangular annular shape) surrounding the active region 10 in a plan view.

[0336] The plurality of field regions 38 overlap the three-dimensional lattice-shaped inverted columns (three-dimensional lattice-shaped non-inverted columns) in the stacking direction in the outer peripheral region 11. In other words, the plurality of field regions 38 are formed in regions above the plurality of intersections of the plurality of first inverted columns 14 and the plurality of second inverted columns 16.

[0337] The multiple field regions 38 intersect with multiple second inversion columns 16 and multiple second non-inversion columns 17 in the portion extending in the first extension direction De1, and intersect with multiple first inversion columns 14 and multiple first non-inversion columns 15 in the portion extending in the second extension direction De2.

[0338] The plurality of field regions 38 are formed in the second layer 9 at intervals from the lower end of the second layer 9 toward the first main surface 3, and each form a pn junction with the second layer 9. The plurality of field regions 38 preferably have bottoms located on the first main surface 3 side of the intermediate portion of the thickness range of the second layer 9. It is particularly preferable that the bottoms of the plurality of field regions 38 be located on the first main surface 3 side of the intermediate portion of the thickness range of the second inversion column 16.

[0339] The bottoms of the plurality of field regions 38 may be located closer to the lower end of the second inverting column 16 than the depth position of the upper end of the second inverting column 16. In this case, each field region 38 may be connected to either or both of the second inverting column 16 and the second non-inverting column 17 in the portion extending along the second extending direction De2.

[0340] For example, if the distance between the first main surface 3 and the upper end is sufficiently large, the bottom of each field region 38 may be located closer to the first main surface 3 than the depth position of the upper end of the second inverted column 16. Of course, if the top layer 30 is formed, the bottoms of the multiple field regions 38 may be located closer to the first main surface 3 than the depth position of the upper end of the second inverted column 16.

[0341] The field regions 38 may have a thickness approximately equal to that of the body regions 32. In this case, the field regions 38 may be formed simultaneously with the body regions 32. Of course, the field regions 38 may have a thickness greater than that of the body regions 32. Alternatively, the field regions 38 may have a thickness less than that of the body regions 32.

[0342] The field regions 38 are formed of random impurity regions introduced into the surface of the second layer 9 by random implantation (see also FIG. 7 ). Therefore, the field regions 38 have a thickness along the second axial channel CH2 that is less than the second region thickness TR2 of the second inversion column 16. The thickness of the field regions 38 is less than the first region thickness TR1 of the first inversion column 14.

[0343] Unlike the second inversion column 16 and the like, the plurality of field regions 38 do not have a gradual portion 22 having a thickness of 0.5 μm or more, and have a concentration gradient including a gradually increasing portion 20, a peak portion 21, and a gradually decreasing portion 23 within a range of 0.5 μm. １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0344] The p-type impurity concentration of the field region 38 may be approximately equal to the p-type impurity concentration of the body region 32. Of course, the p-type impurity concentrations of the plurality of field regions 38 may be higher than the p-type impurity concentrations of the plurality of body regions 32. Furthermore, the p-type impurity concentrations of the plurality of field regions 38 may be lower than the p-type impurity concentrations of the plurality of body regions 32.

[0345] The p-type impurity concentrations of the plurality of field regions 38 are preferably adjusted by at least one trivalent element. The trivalent element in the field regions 38 may be the same as or different from the trivalent element in the second non-inversion columns 17, etc. The trivalent element in the field regions 38 may be at least one of boron, aluminum, gallium, and indium.

[0346] The field regions 38 preferably have widths different from the width of the second non-inversion columns 17. In other words, the electric field relaxation effect of the field regions 38 is preferably adjusted separately from the second non-inversion columns 17. It is particularly preferable that the width of the field regions 38 be larger than the width of the second non-inversion columns 17. Of course, the width of the field regions 38 may be smaller than the width of the second non-inversion columns 17. Alternatively, the width of the field regions 38 may be approximately equal to the width of the second non-inversion columns 17.

[0347] The field regions 38 are preferably formed at a pitch different from the second pitch P2 of the second reversing columns 16 (the first pitch P1 of the first reversing columns 14). It is particularly preferable that the pitch of the field regions 38 be larger than the second pitch P2 (the first pitch P1). Of course, the pitch of the field regions 38 may be smaller than the second pitch P2 (the first pitch P1). Alternatively, the pitch of the field regions 38 may be approximately equal to the second pitch P2 (the first pitch P1).

[0348] The SiC semiconductor device 1A includes an interlayer insulating film 40 covering the first main surface 3. The interlayer insulating film 40 may also be referred to as an "insulating film," an "interlayer film," an "intermediate insulating film," or the like. In this embodiment, the interlayer insulating film 40 has a stacked structure including a first insulating film 41 and a second insulating film 42. The first insulating film 41 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is particularly preferable that the first insulating film 41 include a silicon oxide film made of an oxide of the chip 2 (second layer 9).

[0349] The first insulating film 41 selectively covers the first main surface 3 in the active region 10 and the peripheral region 11. The first insulating film 41 covers the region outside the gate insulating film 36 in the active region 10 and is connected to the gate insulating film 36. The first insulating film 41 covers a plurality of field regions 38 in the peripheral region 11.

[0350] In this embodiment, the first insulating film 41 is continuous with the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. Of course, the first insulating film 41 may be formed at a distance inward from the periphery of the first main surface 3, so that the second layer 9 is exposed from the periphery of the first main surface 3.

[0351] The second insulating film 42 is stacked on the first insulating film 41. The second insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 40 preferably includes a silicon oxide film. The second insulating film 42 covers the first main surface 3 in the active region 10 and the peripheral region 11, sandwiching the first insulating film 41 therebetween.

[0352] The second insulating film 42 covers the plurality of gate structures 35 in the active region 10. The second insulating film 42 covers the plurality of field regions 38 in the peripheral region 11, sandwiching the first insulating film 41 therebetween. In this embodiment, the second insulating film 42 is continuous with the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. Of course, the second insulating film 42 may be formed at a distance inward from the periphery of the first main surface 3, and may expose the periphery of the first main surface 3 together with the first insulating film 41.

[0353] The SiC semiconductor device 1A includes a plurality of contact openings 43 formed in an interlayer insulating film 40. The plurality of contact openings 43 include a plurality of contact openings 43 (not shown) that expose a plurality of gate structures 35 (gate electrodes 37) and a plurality of contact openings 43 that expose a plurality of source regions 33. The plurality of contact openings 43 for the source regions 33 are formed in regions between adjacent plurality of gate structures 35, and expose a plurality of source regions 33 and a plurality of contact regions 34.

[0354] 1 , SiC semiconductor device 1A includes a gate pad 45 disposed on interlayer insulating film 40. Gate pad 45 is an electrode to which a gate potential is applied from the outside. Gate pad 45 may also be referred to as a "gate pad electrode," a "first pad electrode," or the like. Gate pad 45 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 40 side.

[0355] In this embodiment, the gate pad 45 is disposed on a portion of the interlayer insulating film 40 that covers the active region 10. The gate pad 45 may be disposed at an interval from the outer periphery region 11 toward the active region 10. In this embodiment, the gate pad 45 is disposed on the periphery of the active region 10 in plan view.

[0356] 1 shows an example in which the gate pad 45 is arranged in a region along the center of the first side surface 5A on the periphery of the active region 10. Of course, the gate pad 45 may also be arranged in a region along the center of any of the first to fourth side surfaces 5A to 5D. Of course, the gate pad 45 may also be arranged at any corner of the active region 10 in a plan view. Also, the gate pad 45 may also be arranged in the center of the active region 10 in a plan view. In this embodiment, the gate pad 45 is formed in a quadrangular shape in a plan view.

[0357] The SiC semiconductor device 1A includes at least one gate wiring 46 (multiple in this embodiment) extending from the gate pad 45 onto the interlayer insulating film 40. The gate wiring 46 may also be referred to as a "wiring," "wiring electrode," or the like. The multiple gate wirings 46 may have a layered structure including a Ti-based metal film and an Al-based metal film stacked in this order from the interlayer insulating film 40 side. In this embodiment, the multiple gate wirings 46 include a first gate wiring 46A and a second gate wiring 46B.

[0358] The first gate wiring 46A is drawn out from the gate pad 45 toward the second side surface 5B and extends in a line along the periphery of the active region 10 so as to intersect (specifically, perpendicular to) part (specifically, one end) of the multiple gate structures 35. The first gate wiring 46A penetrates the interlayer insulating film 40 via the multiple contact openings 43 and is electrically connected to one end of the multiple gate structures 35.

[0359] The second gate wiring 46B is drawn out from the gate pad 45 toward the fourth side surface 5D and extends in a line along the periphery of the active region 10 so as to intersect (specifically, perpendicular to) part (specifically, the other end portions) of the multiple gate structures 35. The second gate wiring 46B penetrates the interlayer insulating film 40 via the multiple contact openings 43 and is electrically connected to the other end portions of the multiple gate structures 35.

[0360] The SiC semiconductor device 1A includes a source pad 47 disposed on the interlayer insulating film 40 at a distance from the gate pad 45 and the gate wiring 46. The source pad 47 is an electrode to which a source potential is applied from the outside. The source pad 47 may also be referred to as a "source pad electrode," a "second pad electrode," or the like. The source pad 47 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 40 side.

[0361] The source pad 47 is disposed on a portion of the interlayer insulating film 40 that covers the active region 10. The source pad 47 may be disposed at an interval from the peripheral region 11 toward the active region 10. In this embodiment, the source pad 47 is formed in a polygonal shape having a recess that is recessed along the gate pad 45 in a plan view. Of course, the source pad 47 may also be formed in a quadrangular shape in a plan view.

[0362] The source pad 47 penetrates the interlayer insulating film 40 via the contact openings 43, and is electrically connected to the body regions 32, the source regions 33, and the contact regions 34. That is, the source pad 47 is electrically connected to the second non-inversion columns 17 (second impurity regions 13) via the body regions 32.

[0363] The SiC semiconductor device 1A includes a drain pad 48 covering the second main surface 4. The drain pad 48 is an electrode to which a drain potential is applied from the outside. The drain pad 48 may also be referred to as a "drain pad electrode," a "third pad electrode," or the like. The drain pad 48 forms ohmic contact with the base layer 6 exposed from the second main surface 4. In other words, the drain pad 48 is electrically connected to the first layer 8 (the plurality of first inversion columns 14) and the second layer 9 (the plurality of second inversion columns 16) via the base layer 6.

[0364] The drain pad 48 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The drain pad 48 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0365] The breakdown voltage that can be applied between source pad 47 and drain pad 48 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to any one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0366] When a laminated portion 7 having a two-layer structure is employed, the breakdown voltage is preferably set to a value belonging to any one of the ranges of 500 V to 1000 V, 1000 V to 1500 V, and 1500 V to 2000 V. When a laminated portion 7 having a three-layer structure is employed, the breakdown voltage is preferably set to a value belonging to any one of the ranges of 1000 V to 1500 V, 1500 V to 2000 V, 2000 V to 2500 V, and 2500 V to 3000 V.

[0367] 18 is a cross-sectional perspective view showing a gate structure 35 according to the second embodiment. The gate structures 35 according to the first embodiment extend along the second extension direction De2 of the second inverting columns 16. In contrast, the gate structures 35 according to the second embodiment extend in a direction other than the second extension direction De2 so as to intersect with the second inverting columns 16 and the second non-inverting columns 17.

[0368] In this embodiment, the plurality of body regions 32 extend in a direction other than the second extension direction De2 so as to intersect with the plurality of second inverted columns 16 and the plurality of second non-inverted columns 17. In this embodiment, the plurality of body regions 32 are arranged at intervals in the first arrangement direction Da1 of the first inverted columns 14 and extend in the first extension direction De1 of the first inverted columns 14. In other words, the plurality of body regions 32 are perpendicular to the stacking direction. In this example, the first arrangement direction Da1 is the a-axis direction (first direction X), and the first extension direction De1 is the m-axis direction (second direction Y).

[0369] The body regions 32 may face the first inverted columns 14 in a one-to-one correspondence in the stacking direction. Of course, each body region 32 may face the first inverted columns 14 in the stacking direction. The body regions 32 may face the first non-inverted columns 15 in a one-to-one correspondence in the stacking direction.

[0370] Of course, each body region 32 may face multiple first non-inverted columns 15 in the stacking direction. The multiple body regions 32 may be arranged offset from the multiple first inverted columns 14 in the first arrangement direction Da1 and face either or both of the first inverted columns 14 and the first non-inverted columns 15 in the stacking direction.

[0371] Of course, the arrangement direction and extension direction of the plurality of body regions 32 are changed depending on the first arrangement direction Da1 and first extension direction De1 of the plurality of first inversion columns 14. Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Alternatively, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.

[0372] Of course, the arrangement direction of the body regions 32 may be a direction other than the first arrangement direction Da1 and the second arrangement direction D2. Furthermore, the extension direction of the body regions 32 may be a direction other than the first extension direction De1 and the second extension direction De2. That is, the body regions 32 may intersect both the first inverted columns 14 and the second inverted columns 16 in a plan view. In this case, the arrangement direction of the body regions 32 may be one of the a-axis direction and the m-axis direction, and the extension direction of the body regions 32 may be the other of the a-axis direction and the m-axis direction.

[0373] For example, the angle (absolute value) between the extension direction of the body region 32 and the second extension direction De2 may be greater than 0° and less than 90°. The angle (absolute value) of the body region 32 may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° to 36°, 36° to 54°, 54° to 72°, and 72° to 90°. The angle (absolute value) of the body region 32 may be set to a value belonging to any one of the ranges of 30°±5°, 45°±5°, and 60°±5°.

[0374] The aforementioned multiple source regions 33 and multiple contact regions 34 are formed along the extension direction of the corresponding body regions 32, and face the multiple second inversion columns 16 and the multiple second non-inversion columns 17, respectively, across a portion of the body region 32 corresponding to the stacking direction.

[0375] In this embodiment, the multiple gate structures 35 are arranged at intervals in the first arrangement direction Da1 of the first inversion columns 14 and extend in the first extension direction De1 of the first inversion columns 14. That is, the multiple gate structures 35 are perpendicular to the multiple second inversion columns 16 and the multiple second non-inversion columns 17. In this example, the first arrangement direction Da1 is the a-axis direction (first direction X), and the first extension direction De1 is the m-axis direction (second direction Y).

[0376] The plurality of gate structures 35 may be opposed to the plurality of first inverted columns 14 in a one-to-one correspondence in the stacking direction. Of course, each gate structure 35 may be opposed to the plurality of first inverted columns 14 in the stacking direction. The plurality of gate structures 35 may be opposed to the plurality of first non-inverted columns 15 in a one-to-one correspondence in the stacking direction.

[0377] Of course, each gate structure 35 may be opposed to multiple first non-inverting columns 15 in the stacking direction. The multiple gate structures 35 may be arranged offset from the multiple first inverting columns 14 in the first arrangement direction Da1 and may be opposed to either or both of the first inverting columns 14 and the first non-inverting columns 15 in the stacking direction.

[0378] Of course, the arrangement direction and extension direction of the multiple gate structures 35 are changed depending on the first arrangement direction Da1 and first extension direction De1 of the multiple first inversion columns 14 (body regions 32). Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Alternatively, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.

[0379] Of course, the arrangement direction of the multiple gate structures 35 may be a direction other than the first arrangement direction Da1 and the second arrangement direction D2. Furthermore, the extension direction of the multiple gate structures 35 may be a direction other than the first extension direction De1 and the second extension direction De2. That is, the multiple gate structures 35 may intersect both the multiple first inversion columns 14 and the multiple second inversion columns 16 in a planar view. In this case, the arrangement direction of the multiple gate structures 35 may be one of the a-axis direction and the m-axis direction, and the extension direction of the multiple gate structures 35 may be the other of the a-axis direction and the m-axis direction.

[0380] For example, the angle (absolute value) between the extension direction of the gate structure 35 and the second extension direction De2 may be greater than 0° and less than 90°. The angle (absolute value) of the gate structure 35 may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° to 36°, 36° to 54°, 54° to 72°, and 72° to 90°. The angle (absolute value) of the gate structure 35 may be set to a value belonging to any one of the ranges of 30°±5°, 45°±5°, and 60°±5°.

[0381] In this embodiment, the plurality of gate structures 35 are each disposed across two adjacent body regions 32, and cover the plurality of source regions 33 located in one and the other body regions 32. The plurality of gate structures 35 also face the plurality of second inversion columns 16 and the plurality of second non-inversion columns 17 in the stacking direction, respectively.

[0382] 19 is a schematic diagram showing a wafer 50 used in the manufacture of the SiC semiconductor device 1A. The wafer 50 is a substrate of the base layer 6 and includes a SiC single crystal. The wafer 50 is formed in a flat disk shape. Of course, the wafer 50 may also be formed in a flat rectangular parallelepiped shape. The wafer 50 has a first wafer main surface 51 on one side, a second wafer main surface 52 on the other side, and a wafer side surface 53 connecting the first wafer main surface 51 and the second wafer main surface 52.

[0383] The first wafer main surface 51 corresponds to the upper end of the base layer 6, and the second wafer main surface 52 corresponds to the lower end of the base layer 6. The first wafer main surface 51 and the second wafer main surface 52 are formed by the c-plane of the SiC single crystal. The first wafer main surface 51 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 52 is formed by the carbon surface of the SiC single crystal. The wafer 50 (the first wafer main surface 51 and the second wafer main surface 52) has the off-direction Doff and the off-angle θoff described above.

[0384] The wafer 50 has a mark 54 on the wafer side surface 53 that indicates the crystal orientation of the SiC single crystal. The mark 54 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is linearly cut out in a plan view. The orientation notch is a cutout that is concave (e.g., tapered) toward the center of the first wafer main surface 51 in a plan view.

[0385] The mark 54 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The mark 54 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction. Figure 19 shows an orientation flat extending in the a-axis direction in a plan view.

[0386] For example, a plurality of device regions 55 and a plurality of cutting lines 56 are set on the wafer 50 by alignment marks or the like. Each device region 55 corresponds to a SiC semiconductor device 1A. Each of the plurality of device regions 55 is set to have a quadrangular shape in a plan view.

[0387] In this embodiment, the device regions 55 are set in a matrix along the first direction X and the second direction Y in a plan view. The device regions 55 are set at intervals inward from the periphery of the first wafer main surface 51 in a plan view. The cutting lines 56 are set in a grid pattern extending along the first direction X and the second direction Y to partition the device regions 55.

[0388] Fig. 20 is a flowchart showing an example of a manufacturing method for the SiC semiconductor device 1A. Figs. 21A to 21H are cross-sectional perspective views showing an example of a manufacturing method for the SiC semiconductor device 1A. Figs. 22A to 22B are schematic views for explaining a crystal orientation measurement process. Figs. 23A to 23B are schematic views for explaining an ion implantation process. Figs. 21A to 21H show cross-sectional perspective views of a portion of the active region 10 of one device region 55.

[0389] First, referring to FIG. 21A, the aforementioned wafer 50 preparation step is performed (step S1 in FIG. 20). Next, a determination step is performed as to whether or not an n-type buffer layer 26 (see FIG. 13E) formation step is performed (step S2 in FIG. 20). If a buffer layer 26 is to be formed (step S2 in FIG. 20: YES), the buffer layer 26 is formed starting from the first wafer main surface 51 (wafer 50) by epitaxial growth (step S3 in FIG. 20). If the buffer layer 26 formation step is not performed (step S2 in FIG. 20: NO), this step is omitted.

[0390] Next, referring to FIG. 21B , the step of forming an n-type first layer 8 is performed (step S4 in FIG. 20 ). If the step of forming the buffer layer 26 is omitted, the first layer 8 is formed by epitaxial growth starting from the first wafer main surface 51 (wafer 50). If the buffer layer 26 is formed, the first layer 8 is formed by epitaxial growth starting from the buffer layer 26. In this case, the first layer 8 may be formed by continuous crystal growth from the buffer layer 26 using the step of forming the buffer layer 26 after the step of forming the buffer layer 26.

[0391] Next, a step of measuring the crystal orientation of the first layer 8 is performed (Step S5 in FIG. 20 ). The crystal orientation of the first layer 8 includes a step of measuring the off angle θ of the first layer 8. That is, this step includes a step of measuring the crystal orientation of the first axis channel CH1 of the first layer 8.

[0392] The wafer 50 is cut from an ingot (SiC ingot), which is a crystalline mass, and there is a risk that an error will occur in the off-angle θoff due to a process error. If an error occurs in the off-angle θoff of the wafer 50, a process error will also occur in the off-angle θoff of the first layer 8, which will become an obstacle during the channeling implantation process. Therefore, it is preferable that data (information) on the off-angle θoff be acquired prior to the channeling implantation process, and that the channeling implantation process be performed based on the data (information) on the off-angle θoff.

[0393] 22A , in this step, the crystal orientation of the first layer 8 is measured by an X-ray diffraction method (so-called ω-2θ measurement method) using an X-ray diffraction device 57. The X-ray diffraction device 57 may also be referred to as an "XRD (X-ray Diffraction) device."

[0394] The X-ray diffraction device 57 includes an irradiation unit 58 and a detection unit 59 and performs rocking curve measurement. The irradiation unit 58 irradiates the upper end of the first layer 8 (the first wafer main surface 51 of the wafer 50) with incident X-rays L1 at a predetermined incident angle ω. The incident angle ω is defined as the angle between the incident X-rays L1 and the upper end of the first layer 8 (the first wafer main surface 51 of the wafer 50).

[0395] The detector 59 is disposed at an angular position of a diffraction angle 2θ (θ is the Bragg angle) with respect to the irradiation position of the incident X-rays L1 on the wafer 50, and detects the diffracted X-rays L2. The diffraction angle 2θ is the angle between the incident direction of the incident X-rays L1 and the diffraction direction of the diffracted X-rays L2.

[0396] In the rocking curve measurement method, the incident angle ω is varied within a small angular range while the diffraction angle 2θ is fixed, and a rocking curve representing the intensity of the diffracted X-rays L2 (the intensity profile of the diffracted X-rays L2) is measured. The rocking curve has the intensity of the diffracted X-rays L2 on the vertical axis and the incident angle ω on the horizontal axis. The incident angle ω is determined as the angular position at which the intensity of the diffracted X-rays L2 takes a peak value.

[0397] In this step, the rocking curve measurement method is performed only at one location (for example, the central portion) of the upper end (first wafer main surface 51 of the wafer 50) of the first layer 8. If in-plane variation in the off angle θ is expected, the rocking curve measurement method may be performed at multiple locations (for example, the central portion and peripheral portion) of the upper end (first wafer main surface 51 of the wafer 50) of the first layer 8.

[0398] 22B shows measurement points (five points in this example) at which the rocking curve measurement method was performed on the upper end of the first layer 8. The off angle θoff of the first layer 8 is set to approximately 4° in this example. First to fifth measurement points Po1 to Po5 are shown in FIG.

[0399] The first measurement point Po1 is set in the center of the first layer 8. The second measurement point Po2 is set in the peripheral portion of the first layer 8 at a distance from the first measurement point Po1 on one side in the second direction Y (the opposite side from the mark 54). The third measurement point Po3 is set in the peripheral portion of the first layer 8 at a distance from the first measurement point Po1 on one side in the first direction X (to the right of the mark 54).

[0400] The fourth measurement point Po4 is set on the periphery of the first layer 8 at a distance from the first measurement point Po1 to the other side in the second direction Y (toward the mark 54). The fifth measurement point Po5 is set on the periphery of the first layer 8 at a distance from the first measurement point Po1 to the other side in the first direction X (to the left of the mark 54).

[0401] The measurement results of the incident angle ω, diffraction angle 2θ, and off angle θoff at the first to fifth measurement points Po1 to Po5 are shown in Table 1. The off angle θoff is calculated using the incident angle ω and diffraction angle 2θ by the formula "ω - (2θ × 1 / 2)".

[0402] As shown in Table 1, the average value of the off angle θoff at the first to fifth measurement points Po1 to Po5 was 4.036°, and the standard deviation of these off angles θoff was 0.009° (±0.01°). From this, it can be understood that the in-plane variation of the off angle θoff occurring at the upper end of the first layer 8 (first wafer main surface 51 of the wafer 50) is extremely small, and does not interfere with the channeling implantation process.

[0403] Therefore, it is understood that there is no problem with at least one measurement point on the upper end of the first layer 8 (first wafer main surface 51 of wafer 50). For example, the measurement point may be any one or more (all) of the first to fifth measurement points Po1 to Po5. For example, the measurement point may be only the first measurement point Po1. Reducing the number of measurement points (number of measurements) reduces the number of manufacturing steps (manufacturing costs).

[0404] Of course, the off angle θ may be measured at multiple locations on the upper end of the first layer 8 (first wafer main surface 51 of the wafer 50) and the implantation angle may be set in accordance with the in-plane variation of the off angle θ in the channeling implantation process. In this case, although the number of manufacturing steps (manufacturing costs) increases, the in-plane error of the first inverted columns 14 formed in the first layer 8 is appropriately suppressed.

[0405] The off-angle θ of the first layer 8 is substantially equal to the off-angle θ of the wafer 50 and the off-angle θ of the buffer layer 26. Therefore, the crystal orientation measurement step may be performed on the wafer 50 or the buffer layer 26 prior to the step of forming the first layer 8. However, from the viewpoint of ensuring accuracy, it is preferable that the crystal orientation measurement step be performed on the first layer 8.

[0406] 21C , a step of forming first impurity region 12 is performed (step S6 in FIG. 20 ). The step of forming first impurity region 12 includes a channeling implantation step of a trivalent element (p-type impurity) into first layer 8. In this step, the trivalent element is introduced into the entire first layer 8. First layer 8 (wafer 50) has an off angle θ inclined at a predetermined angle in a predetermined off direction D with respect to first wafer main surface 51. The channeling implantation step is performed based on data (information) of the off angle θ.

[0407] 23A , in the random implantation method, a trivalent element is introduced into the first layer 8 with a predetermined implantation energy in a direction intersecting the first axial channel CH1 (off angle θoff) (see also FIG. 7 ). For example, in the random implantation method, the trivalent element is implanted along the vertical direction Z perpendicular to the upper end (first wafer main surface 51) of the first layer 8.

[0408] In the random implantation method, the trivalent element is introduced along the direction in which the atomic rows are relatively dense in a plan view, and therefore the trivalent element collides with the atomic rows at a relatively shallow depth position. Therefore, the atomic rows hinder the introduction of the trivalent element into a relatively deep depth position in the first layer 8. As a result, the first inverted columns 14 without the slow portions 22 are formed (see also FIG. 7 ).

[0409] 23B , in the channeling implantation method, the implantation angle of the trivalent element with respect to the first layer 8 is controlled, and the trivalent element is introduced into the first layer 8 along the first axial channel CH1 (in this embodiment, the c-axis of the SiC single crystal) with a predetermined implantation energy (see also FIGS. 6A to 6E ). In this case, either or both of the implantation angle of the trivalent element with respect to the first layer 8 and the tilt angle of the first layer 8 with respect to the implantation angle of the trivalent element are adjusted.

[0410] For example, the wafer 50 may be supported horizontally, and the trivalent element may be introduced into the first layer 8 along the first axial channel CH1. Of course, the wafer 50 may be supported in a state inclined by the off angle θoff with respect to the horizontal, and the trivalent element may be introduced into the first layer 8 along the first axial channel CH1. By selecting any combination of the implantation energy of the trivalent element and the implantation temperature of the trivalent element (temperature of the wafer 50), a plurality of first inversion columns 14 having a predetermined thickness are formed at predetermined depth positions (see also FIGS. 6A to 6E ).

[0411] The implantation energy of the trivalent element may be 100 KeV to 2000 KeV, or may have a value belonging to any one of the ranges of 100 KeV to 250 KeV, 250 KeV to 500 KeV, 500 KeV to 750 KeV, 750 KeV to 1000 KeV, 1000 KeV to 1250 KeV, 1250 KeV to 1500 KeV, 1500 KeV to 1750 KeV, and 1750 KeV to 2000 KeV.

[0412] The implantation temperature of the trivalent element may be adjusted in the range of 0° C. to 1500° C. The implantation temperature may have a value belonging to any one of the ranges of 0° C. to 25° C., 25° C. to 50° C., 50° C. to 100° C., 100° C. to 250° C., 250° C. to 500° C., 500° C. to 750° C., 750° C. to 1000° C., 1000° C. to 1250° C., and 1250° C. to 1500° C.

[0413] The implantation angle of the trivalent element is preferably set within a range of ±2° with respect to the axis along the first axial channel CH1 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°). The implantation angle of the trivalent element is particularly preferably set within a range of ±1° with respect to the axis along the first axial channel CH1 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°).

[0414] In the case of the channeling implantation method, the trivalent element is introduced along the first axial channel CH1 in which the atomic rows are relatively sparse in a plan view. The trivalent element travels through the first axial channel CH1 while repeatedly undergoing small-angle scattering due to the channeling effect, and reaches a relatively deep position in the first layer 8. In other words, in the case of the channeling implantation method, the probability of the trivalent element colliding with the atomic rows of the SiC single crystal is reduced.

[0415] In this case, it is preferable that a trivalent element that is heavier than carbon is introduced into the first layer 8. That is, it is preferable that the trivalent element is a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the trivalent element is aluminum.

[0416] After the step of implanting the trivalent element, an annealing method may be performed to electrically activate the trivalent element and simultaneously repair lattice defects and the like that have occurred in the first layer 8. The annealing temperature for the first layer 8 may be 500° C. or higher and 2000° C. or lower.

[0417] Next, referring to FIG. 21D , a step of forming a first mask 60 having a predetermined pattern is performed (step S7 in FIG. 20 ). The first mask 60 is preferably an organic mask (resist mask). The first mask 60 is disposed on the upper end of the first layer 8 and has a plurality of first openings 61 that expose areas in the first layer 8 where the plurality of first inverted columns 14 are to be formed.

[0418] Specifically, the multiple first openings 61 are formed at intervals in the first arrangement direction Da1 over the entire surface of the upper end of the first layer 8, and are each partitioned into stripes extending in the first extension direction De1. That is, the multiple first openings 61 cross the multiple device regions 55 and the multiple lines to cut 56 in the first extension direction De1, exposing the multiple device regions 55 and the multiple lines to cut 56 in stripes. The multiple first openings 61 expose both a portion of the upper end of each device region 55 that is located within the active region 10 and a portion that is located within the peripheral region 11.

[0419] 21E , a step of forming a plurality of first inversion columns 14 is performed (Step S8 in FIG. 20 ). The step of forming the plurality of first inversion columns 14 includes a channeling implantation step of a pentavalent element (n-type impurity) into the first layer 8. The channeling implantation step is performed based on the data (information) of the off angle θoff described above.

[0420] In the channeling implantation method, the implantation angle of the pentavalent element with respect to the first layer 8 is controlled, and the pentavalent element is introduced into the first layer 8 along a first axial channel CH1 (in this embodiment, the c-axis of the SiC single crystal) with a predetermined implantation energy (see also FIGS. 6A to 6E ). In this case, either or both of the implantation angle of the pentavalent element with respect to the first layer 8 and the tilt angle of the first layer 8 with respect to the implantation angle of the pentavalent element are adjusted.

[0421] For example, the wafer 50 may be supported horizontally, and the pentavalent element may be introduced into the first layer 8 along the first axial channel CH1. Of course, the wafer 50 may be supported in a state inclined by the off angle θoff with respect to the horizontal, and the pentavalent element may be introduced into the first layer 8 along the first axial channel CH1. By selecting any combination of the implantation energy of the pentavalent element and the implantation temperature of the pentavalent element, a plurality of first inversion columns 14 having a predetermined thickness are formed at predetermined depth positions (see also FIGS. 6A to 6E ).

[0422] The implantation energy of the pentavalent element may be 100 KeV to 2000 KeV, or may have a value belonging to any one of the ranges of 100 KeV to 250 KeV, 250 KeV to 500 KeV, 500 KeV to 750 KeV, 750 KeV to 1000 KeV, 1000 KeV to 1250 KeV, 1250 KeV to 1500 KeV, 1500 KeV to 1750 KeV, and 1750 KeV to 2000 KeV.

[0423] The implantation energy for the first inversion column 14 may be approximately equal to or different from the implantation energy for the first impurity region 12. The implantation energy for the first inversion column 14 may be equal to or greater than the implantation energy for the first impurity region 12. Alternatively, the implantation energy for the first inversion column 14 may be less than the implantation energy for the first impurity region 12.

[0424] The implantation temperature of the pentavalent element may be adjusted in the range of 0° C. to 1500° C. The implantation temperature may have a value belonging to any one of the ranges of 0° C. to 25° C., 25° C. to 50° C., 50° C. to 100° C., 100° C. to 250° C., 250° C. to 500° C., 500° C. to 750° C., 750° C. to 1000° C., 1000° C. to 1250° C., and 1250° C. to 1500° C.

[0425] The implantation temperature for the first inversion columns 14 may be approximately equal to or different from the implantation temperature for the first impurity region 12. The implantation temperature for the first inversion columns 14 may be equal to or higher than the implantation temperature for the first impurity region 12. Alternatively, the implantation temperature for the first inversion columns 14 may be lower than the implantation temperature for the first impurity region 12.

[0426] The implantation angle of the pentavalent element is preferably set within a range of ±2° with respect to the axis along the first axial channel CH1 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°). The implantation angle of the pentavalent element is particularly preferably set within a range of ±1° with respect to the axis along the first axial channel CH1 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°).

[0427] In the case of channeling implantation, the pentavalent element is introduced along the first axial channel CH1, in which the atomic rows are relatively sparse in plan view. The pentavalent element travels through the first axial channel CH1 while repeatedly undergoing small-angle scattering due to the channeling effect, and reaches a relatively deep position in the first layer 8. In other words, in the case of channeling implantation, the probability of the pentavalent element colliding with the atomic rows of the SiC single crystal is reduced. The pentavalent element is preferably arsenic or antimony.

[0428] The first extension direction De1 may be the a-axis direction or the m-axis direction. The first extension direction De1 may be a direction other than the a-axis direction or the m-axis direction. When the first extension direction De1 coincides with the m-axis direction (see also FIG. 8A ), the pentavalent element is introduced into the first layer 8 through the multiple first openings 61 at an angle approximately equal to the off angle θoff with respect to the upper end of the first layer 8 in a cross-sectional view along the first arrangement direction Da1.

[0429] When the first extension direction De1 coincides with the a-axis direction (off direction Doff) (see also FIG. 10A , etc.), the pentavalent element is introduced into the first layer 8 through the multiple first openings 61 substantially perpendicular to the upper end of the first layer 8 in a cross-sectional view along the first arrangement direction Da1. This prevents the multiple first reversal columns 14 from being formed in an inclined position in the first layer 8. Furthermore, the wall surfaces of the multiple first openings 61 are prevented from acting as a shield against the incident path of the pentavalent element.

[0430] When the first extension direction De1 is a direction other than the a-axis direction and the m-axis direction (see also Figures 12A to 12C, etc.), there is no need to strictly control the alignment misalignment of the multiple first inversion columns 14 with respect to the crystal orientation of the SiC single crystal.

[0431] After the step of implanting the pentavalent element, an annealing method may be performed to electrically activate the pentavalent element and simultaneously repair lattice defects and the like that have occurred in the first layer 8. The annealing temperature for the first layer 8 may be 500° C. or higher and 2000° C. or lower. This results in the formation of a plurality of first inversion columns 14 and a plurality of first non-inversion columns 15, as well as the formation of the first superjunction structure SJ1.

[0432] The first inverted columns 14 and the first non-inverted columns 15 are arranged at intervals in the first arrangement direction Da1 across the entire first layer 8, and are each formed to extend in a strip shape in the first extension direction De1. That is, the first inverted columns 14 and the first non-inverted columns 15 are formed in a stripe shape so as to cross the device regions 55 and the cutting lines 56 in the first extension direction De1. After the step of forming the first inverted columns 14, the first mask 60 is removed.

[0433] The annealing method for the plurality of first inversion columns 14 may also serve as the annealing method for the first impurity regions 12. In this case, the annealing method for the first impurity regions 12 before the step of forming the first inversion columns 14 may be omitted.

[0434] Next, a determination step is performed as to whether or not a thickness adjustment step of the first layer 8 is to be performed (step S9 in FIG. 20). If the thickness of the first layer 8 is to be adjusted (step S9 in FIG. 20: YES), the first layer 8 is thinned from the upper end side (step S10 in FIG. 20).

[0435] The thickness adjusting step (thinning step) may include a step of partially removing an upper end portion of the first layer 8 by a grinding method. The grinding method may be a mechanical polishing method and / or a chemical mechanical polishing method. The thickness adjusting step may include a step of partially removing an upper end portion of the first layer 8 by an etching method. The etching method may be a wet etching method and / or a dry etching method.

[0436] The thickness adjustment step may include a step of exposing the first inverted columns 14 and the first non-inverted columns 15 from the upper end of the first layer 8 (see also FIG. 13C ). That is, the thickness adjustment step may include a step of removing part or all of the gradually increasing portions 20 of the first inverted columns 14 (first non-inverted columns 15). If the thickness adjustment step is not performed (step S9 in FIG. 20 : NO), this step is omitted.

[0437] Next, a determination step is performed to determine whether or not one or both of a step of forming a plurality of inverted intermediate columns 18 (see FIG. 13A ) and a step of forming a plurality of non-inverted intermediate columns 19 (see FIG. 13B ) are to be performed (step S11 in FIG. 20 ). If a plurality of inverted intermediate columns 18 are to be formed (step S11 in FIG. 20 : YES), the plurality of inverted intermediate columns 18 are formed on the surface portion of the first layer 8 (step S12 in FIG. 20 ).

[0438] The process of forming the plurality of inverted intermediate columns 18 includes placing a mask (not shown) having a predetermined pattern on the top end of the first layer 8. The mask (not shown) is preferably an organic mask (resist mask). The mask (not shown) has a plurality of openings that respectively expose regions of the first layer 8 where the plurality of first inverted columns 14 are formed.

[0439] Specifically, the multiple openings are formed at intervals in the first arrangement direction Da1 over the entire surface of the upper end of the first layer 8, and are each partitioned into stripes extending in the first extension direction De1. That is, the multiple openings cross the multiple device regions 55 and the multiple lines to cut 56 in the first extension direction De1, exposing the multiple device regions 55 and the multiple lines to cut 56 in stripes. The multiple openings expose both a portion of the upper end of each device region 55 that is located within the active region 10 and a portion that is located within the outer periphery region 11.

[0440] The process of forming the multiple inverted intermediate columns 18 includes a step of introducing a pentavalent element into the first layer 8 at a predetermined implantation energy in a direction intersecting the first axial channel CH1 (off angle θoff) by a random implantation method through a mask (not shown) (see also FIG. 7 ). The pentavalent element may be introduced into the first layer 8 once or multiple times. When the pentavalent element is introduced multiple times, the pentavalent element may be introduced in multiple stages at different depth positions in the first layer 8 at multiple implantation energies.

[0441] The multiple inverted intermediate columns 18 are arranged at intervals in the first arrangement direction Da1 across the entire area of ​​the first layer 8, and are each formed so as to extend in a strip shape in the first extension direction De1. That is, the multiple inverted intermediate columns 18 are formed in a stripe shape so as to cross the multiple device regions 55 and the multiple cutting lines 56 in the first extension direction De1. After the process of forming the multiple inverted intermediate columns 18, the mask (not shown) is removed.

[0442] If the thickness adjustment process for the first layer 8 is not performed, the process for forming the plurality of inverted intermediate columns 18 may be performed consecutively from the process for forming the plurality of first inverted columns 14. In this case, the plurality of inverted intermediate columns 18 may be formed using the first mask 60.

[0443] On the other hand, if multiple non-inverted intermediate columns 19 are to be formed (step S11 in FIG. 20 : YES), multiple non-inverted intermediate columns 19 are formed in the surface layer portion of the first layer 8 (step S12 in FIG. 20 ). The process of forming the multiple non-inverted intermediate columns 19 includes a step of placing a mask (not shown) having a predetermined pattern on the upper end of the first layer 8. The mask (not shown) is preferably an organic mask (resist mask). The mask (not shown) has multiple openings that respectively expose regions of the first layer 8 where the multiple first non-inverted columns 15 are formed.

[0444] Specifically, the multiple openings are formed at intervals in the first arrangement direction Da1 over the entire surface of the upper end of the first layer 8, and are each partitioned into stripes extending in the first extension direction De1. That is, the multiple openings cross the multiple device regions 55 and the multiple lines to cut 56 in the first extension direction De1, exposing the multiple device regions 55 and the multiple lines to cut 56 in stripes. The multiple openings expose both a portion of the upper end of each device region 55 that is located within the active region 10 and a portion that is located within the outer periphery region 11.

[0445] The process of forming the plurality of non-inverted intermediate columns 19 includes a step of introducing a trivalent element into the first layer 8 at a predetermined implantation energy in a direction intersecting the first axial channel CH1 (off angle θoff) by a random implantation method through a mask (not shown) (see also FIG. 7 ). The trivalent element may be introduced into the first layer 8 once or multiple times. When the trivalent element is introduced multiple times, the trivalent element may be introduced in multiple stages at different depth positions in the first layer 8 at multiple implantation energies.

[0446] The non-inverted intermediate columns 19 are arranged at intervals in the first arrangement direction Da1 across the entire first layer 8, and are each formed to extend in a strip shape in the first extension direction De1. That is, the non-inverted intermediate columns 19 are formed in a stripe shape so as to cross the device regions 55 and the cutting lines 56 in the first extension direction De1. After the process of forming the non-inverted intermediate columns 19, the mask (not shown) is removed.

[0447] Next, referring to Fig. 21F, a step of forming second layer 9 is performed (step S13 in Fig. 20). Second layer 9 is formed starting from first layer 8 by epitaxial growth. Thereafter, a step of measuring the crystal orientation (off-angle θoff) of second layer 9 may be performed by a method similar to step S4 in Fig. 20 (also see Figs. 22A and 22B).

[0448] 21G, a step of forming second impurity region 13 is performed (step S14 in FIG. 20). The step of forming second impurity region 13 includes a channeling implantation step of a trivalent element (p-type impurity) into second layer 9. In this step, the trivalent element is introduced into the entire region of second layer 9. The channeling implantation step is performed based on the data (information) of the off angle θoff described above.

[0449] In the channeling implantation method, the implantation angle of the trivalent element with respect to the second layer 9 is controlled, and the trivalent element is introduced into the second layer 9 along the second axial channel CH2 (in this embodiment, the c-axis of the SiC single crystal) with a predetermined implantation energy (see also FIGS. 6A to 6E ). In this case, either or both of the implantation angle of the trivalent element with respect to the second layer 9 and the tilt angle of the second layer 9 with respect to the implantation angle of the trivalent element are adjusted.

[0450] For example, the wafer 50 may be supported horizontally, and the trivalent element may be introduced into the second layer 9 along the second axial channel CH2. Of course, the wafer 50 may be supported in a state inclined by the off angle θoff with respect to the horizontal, and the trivalent element may be introduced into the second layer 9 along the second axial channel CH2. By selecting any combination of the implantation energy of the trivalent element and the implantation temperature of the trivalent element, a plurality of first inversion columns 14 having a predetermined thickness are formed at predetermined depth positions (see also FIGS. 6A to 6E ).

[0451] The implantation energy of the trivalent element may be 100 KeV to 2000 KeV, or may have a value belonging to any one of the ranges of 100 KeV to 250 KeV, 250 KeV to 500 KeV, 500 KeV to 750 KeV, 750 KeV to 1000 KeV, 1000 KeV to 1250 KeV, 1250 KeV to 1500 KeV, 1500 KeV to 1750 KeV, and 1750 KeV to 2000 KeV.

[0452] The implantation energy for the second impurity region 13 may be approximately equal to the implantation energy for the first impurity region 12, or may be different from the implantation energy for the first impurity region 12. The implantation energy for the second impurity region 13 may be equal to or greater than the implantation energy for the first impurity region 12. Alternatively, the implantation energy for the second impurity region 13 may be less than the implantation energy for the first impurity region 12.

[0453] The implantation temperature of the trivalent element may be adjusted in the range of 0° C. to 1500° C. The implantation temperature may have a value belonging to any one of the ranges of 0° C. to 25° C., 25° C. to 50° C., 50° C. to 100° C., 100° C. to 250° C., 250° C. to 500° C., 500° C. to 750° C., 750° C. to 1000° C., 1000° C. to 1250° C., and 1250° C. to 1500° C.

[0454] The implantation temperature for the second impurity region 13 may be approximately equal to the implantation temperature for the first impurity region 12, or may be different from the implantation temperature for the first impurity region 12. The implantation temperature for the second impurity region 13 may be equal to or higher than the implantation temperature for the first impurity region 12. Alternatively, the implantation temperature for the second impurity region 13 may be lower than the implantation temperature for the first impurity region 12.

[0455] The implantation angle of the trivalent element is preferably set within a range of ±2° with respect to the axis along the second axial channel CH2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°). The implantation angle of the trivalent element is particularly preferably set within a range of ±1° with respect to the axis along the second axial channel CH2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°).

[0456] In the case of the channeling implantation method, the trivalent element is introduced along the second axial channel CH2 in which the atomic rows are relatively sparse in a plan view. The trivalent element travels through the second axial channel CH2 while repeatedly undergoing small-angle scattering due to the channeling effect, and reaches a relatively deep position in the second layer 9. In other words, in the case of the channeling implantation method, the probability of the trivalent element colliding with the atomic rows of the SiC single crystal is reduced.

[0457] In this case, it is preferable that a trivalent element that is heavier than carbon is introduced into the second layer 9. That is, it is preferable that the trivalent element is a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the trivalent element is aluminum.

[0458] After the step of implanting the trivalent element, an annealing method may be performed to electrically activate the trivalent element and simultaneously repair lattice defects and the like that have occurred in the second layer 9. The annealing temperature for the second layer 9 may be 500° C. or higher and 2000° C. or lower. The annealing method for the second impurity region 13 may also serve as the annealing method for the first impurity region 12 and the annealing method for the first inversion column 14 described above. In this case, the annealing method for the first impurity region 12 and the annealing method for the first inversion column 14 before the step of forming the second impurity region 13 may be omitted.

[0459] Next, referring to FIG. 21H , a step of forming a second mask 62 having a predetermined pattern is performed (step S15 in FIG. 20 ). The second mask 62 is preferably an organic mask (resist mask). The second mask 62 is disposed on the upper end of the second layer 9 and has a plurality of second openings 63 that expose areas in the second layer 9 where a plurality of second inverted columns 16 are to be formed.

[0460] Specifically, the second openings 63 are formed at intervals in a second arrangement direction Da2 different from the first arrangement direction Da1 over the entire surface of the upper end of the second layer 9, and are each partitioned into strips extending in a second extension direction De2 different from the first extension direction De1. That is, the second openings 63 cross the device regions 55 and the lines to cut 56 in the second extension direction De2, exposing the device regions 55 and the lines to cut 56 in a stripe pattern. The second openings 63 expose both a portion of the upper end of each device region 55 that is located within the active region 10 and a portion that is located within the peripheral region 11.

[0461] 21I, a step of forming a plurality of second inversion columns 16 is performed (step S16 in FIG. 20). The step of forming the plurality of second inversion columns 16 includes a channeling implantation step of a pentavalent element (n-type impurity) into the second layer 9. The channeling implantation step is performed based on the data (information) of the off angle θoff described above.

[0462] In the channeling implantation method, the implantation angle of the pentavalent element with respect to the second layer 9 is controlled, and the pentavalent element is introduced into the second layer 9 along the second axial channel CH2 (in this embodiment, the c-axis of the SiC single crystal) with a predetermined implantation energy (see also FIGS. 6A to 6E ). In this case, either or both of the implantation angle of the pentavalent element with respect to the second layer 9 and the tilt angle of the second layer 9 with respect to the implantation angle of the pentavalent element are adjusted.

[0463] For example, the wafer 50 may be supported horizontally, and the pentavalent element may be introduced into the second layer 9 along the second axial channel CH2. Of course, the wafer 50 may be supported in a state inclined by the off angle θoff with respect to the horizontal, and the pentavalent element may be introduced into the second layer 9 along the second axial channel CH2. By selecting any combination of the implantation energy of the pentavalent element and the implantation temperature of the pentavalent element, a plurality of second inversion columns 16 having a predetermined thickness are formed at predetermined depth positions (see also FIGS. 6A to 6E ).

[0464] The implantation energy of the pentavalent element may be 100 KeV to 2000 KeV, or may have a value belonging to any one of the ranges of 100 KeV to 250 KeV, 250 KeV to 500 KeV, 500 KeV to 750 KeV, 750 KeV to 1000 KeV, 1000 KeV to 1250 KeV, 1250 KeV to 1500 KeV, 1500 KeV to 1750 KeV, and 1750 KeV to 2000 KeV.

[0465] The implant energy of the second inverting column 16 may be approximately equal to or different from the implant energy of the first inverting column 14. The implant energy of the second inverting column 16 may be equal to or greater than the implant energy of the first inverting column 14. Alternatively, the implant energy of the second inverting column 16 may be less than the implant energy of the first inverting column 14.

[0466] The implantation energy for the second inversion columns 16 may be approximately equal to or different from the implantation energy for the second impurity region 13. The implantation energy for the second inversion columns 16 may be equal to or greater than the implantation energy for the second impurity region 13. Alternatively, the implantation energy for the second inversion columns 16 may be less than the implantation energy for the second impurity region 13.

[0467] The implantation temperature of the pentavalent element may be adjusted in the range of 0° C. to 1500° C. The implantation temperature may have a value belonging to any one of the ranges of 0° C. to 25° C., 25° C. to 50° C., 50° C. to 100° C., 100° C. to 250° C., 250° C. to 500° C., 500° C. to 750° C., 750° C. to 1000° C., 1000° C. to 1250° C., and 1250° C. to 1500° C.

[0468] The injection temperature of the second inverting column 16 may be approximately equal to or different from the injection temperature of the first inverting column 14. The injection temperature of the second inverting column 16 may be equal to or higher than the injection temperature of the first inverting column 14. Alternatively, the injection temperature of the second inverting column 16 may be lower than the injection temperature of the first inverting column 14.

[0469] The implantation temperature for the second inversion columns 16 may be approximately equal to or different from the implantation temperature for the second impurity region 13. The implantation temperature for the second inversion columns 16 may be equal to or higher than the implantation temperature for the second impurity region 13. Alternatively, the implantation temperature for the second inversion columns 16 may be lower than the implantation temperature for the second impurity region 13.

[0470] The implantation angle of the pentavalent element is preferably set within a range of ±2° with respect to the axis along the second axial channel CH2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°). It is particularly preferable that the implantation angle of the pentavalent element be set within a range of ±1° with respect to the axis along the second axial channel CH2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°).

[0471] In the case of channeling implantation, the pentavalent element is introduced along the second axial channel CH2, in which the atomic rows are relatively sparse in plan view. The pentavalent element travels through the second axial channel CH2 while repeatedly undergoing small-angle scattering due to the channeling effect, and reaches a relatively deep position in the second layer 9. In other words, in the case of channeling implantation, the probability of the pentavalent element colliding with the atomic rows of the SiC single crystal is reduced. The pentavalent element is preferably arsenic or antimony.

[0472] The second extension direction De2 may be the a-axis direction or the m-axis direction. The second extension direction De2 may be a direction other than the a-axis direction or the m-axis direction. When the second extension direction De2 coincides with the a-axis direction (off direction Doff) (see also FIG. 8A ), the pentavalent element is introduced into the second layer 9 through the second openings 63 approximately perpendicular to the upper end of the second layer 9 in a cross-sectional view along the second arrangement direction Da2. This prevents the second reversal columns 16 from being formed in an inclined position in the second layer 9. Furthermore, the wall surfaces of the second openings 63 are prevented from blocking the incident path of the pentavalent element.

[0473] When the second extension direction De2 coincides with the m-axis direction (see also Figure 10A, etc.), the pentavalent element is introduced into the second layer 9 through multiple second openings 63 at an angle of approximately the off angle θoff relative to the upper end of the second layer 9 in a cross-sectional view along the second arrangement direction Da2.

[0474] When the second extension direction De2 is a direction other than the a-axis direction and the m-axis direction (see also Figures 12A to 12C, etc.), there is no need to strictly control the alignment misalignment of the multiple second inversion columns 16 with respect to the crystal orientation of the SiC single crystal.

[0475] When the first extension direction De1 of the first inverted columns 14 is a direction other than the a-axis direction and the m-axis direction, it is preferable that the second extension direction De2 is also a direction other than the a-axis direction and the m-axis direction. In this case, the first inverted columns 14 have a first extension angle θ1 inclined toward one side of the m-axis with respect to the a-axis, and the second inverted columns 16 have a second extension angle θ2 inclined toward the other side of the m-axis with respect to the a-axis.

[0476] The absolute value of the second extension angle θ2 may be different from the absolute value of the first extension angle θ1. However, in this case, the condition of the relative implantation angle of the pentavalent element in the process of forming the second inverted columns 16 is different from the condition of the relative implantation angle of the pentavalent element in the process of forming the first inverted columns 14. Therefore, the shielding area of ​​the plurality of second openings 63 with respect to the incident path of the pentavalent element is different from the shielding area of ​​the plurality of first openings 61 with respect to the incident path of the pentavalent element.

[0477] That is, the process error of the second reversing columns 16 caused by the shadowing of the second openings 63 is different from the process error of the first reversing columns 14 caused by the shadowing of the first openings 61. Therefore, it is preferable that the absolute value of the second extension angle θ2 is approximately equal to the absolute value of the first extension angle θ1. In this case, the process error of the second reversing columns 16 is approximately equal to the process error of the first reversing columns 14. Therefore, the accuracy of charge balance is improved.

[0478] For example, the first extension angle θ1 may be +45°±5° and the second extension angle θ2 may be −45°±5° (see FIG. 12A). For example, the first extension angle θ1 may be +30°±5° and the second extension angle θ2 may be −30°±5° (see FIG. 12B). For example, the first extension angle θ1 may be +60°±5° and the second extension angle θ2 may be −60°±5° (see FIG. 12C).

[0479] After the step of implanting the pentavalent element, an annealing method may be performed to electrically activate the pentavalent element and simultaneously repair lattice defects and the like that have occurred in the second layer 9. The annealing temperature for the second layer 9 may be 500° C. or higher and 2000° C. or lower. This results in the formation of a plurality of second inversion columns 16 and a plurality of second non-inversion columns 17, as well as the formation of a second superjunction structure SJ2.

[0480] The second inverted columns 16 and the second non-inverted columns 17 are arranged at intervals in the second arrangement direction Da2 across the entire second layer 9, and are each formed to extend in a strip shape in the second extension direction De2. That is, the second inverted columns 16 and the second non-inverted columns 17 are formed in a stripe shape so as to cross the device regions 55 and the lines to cut 56 in the second extension direction De2.

[0481] The annealing method for the plurality of second inversion columns 16 may also serve as the annealing method for the first impurity regions 12, the annealing method for the first inversion columns 14, and the annealing method for the second impurity regions 13. In this case, the annealing method for the first impurity regions 12, the annealing method for the first inversion columns 14, and the annealing method for the second impurity regions 13 before the step of forming the second impurity regions 13 may be omitted.

[0482] Next, a determination step is performed as to whether or not a thickness adjustment step of the second layer 9 is to be performed (step S17 in FIG. 20). If the thickness of the second layer 9 is to be adjusted (step S17 in FIG. 20: YES), the second layer 9 is thinned from the upper end side (step S18 in FIG. 20).

[0483] The thickness adjustment step (thinning step) may include a step of partially removing an upper end portion of the second layer 9 by a grinding method. The grinding method may be a mechanical polishing method and / or a chemical mechanical polishing method. The thinning step of the second layer 9 may include a step of partially removing an upper end portion of the second layer 9 by an etching method. The etching method may be a wet etching method and / or a dry etching method.

[0484] The thickness adjusting step may include a step of exposing the second inverted columns 16 and the second non-inverted columns 17 from the upper end of the second layer 9 (see also FIG. 13D ). That is, the thickness adjusting step may include a step of removing part or all of the second gradually increasing portions 20B of the second inverted columns 16. If the thickness adjusting step is not performed (step S17 in FIG. 20 : NO), this step is omitted.

[0485] Next, a determination step is performed as to whether or not a further superjunction structure SJ is to be formed on the second layer 9 (step S19 in FIG. 20 ). For example, if a third superjunction structure is to be formed (step S19: YES in FIG. 20 ), a third layer similar to the first layer 8 is formed on the second layer 9 through steps similar to steps S13 to S16 in FIG. 20 , and a third impurity region and a third inversion column similar to the first impurity region 12 and the first inversion column 14 are formed in the third layer (step S20 in FIG. 20 ).

[0486] Of course, prior to the step of forming the further superjunction structure SJ, a plurality of inverted intermediate columns 18 and a plurality of non-inverted intermediate columns 19 may be formed in the surface layer portion of the second layer 9 through a step similar to step S11 in Fig. 20. If the step of forming the further superjunction structure SJ is not performed (step S19 in Fig. 20: NO), this step is omitted.

[0487] Next, a determination step is performed as to whether or not a step of forming the top layer 30 (see also FIG. 13F) is to be performed (step S21 in FIG. 20). If the step of forming the top layer 30 is to be performed (step S21 in FIG. 20: YES), the top layer 30 is formed starting from the second layer 9 by epitaxial growth (step S22 in FIG. 20). If the step of forming the top layer 30 is not to be performed (step S21 in FIG. 20: NO), this step is omitted.

[0488] Thereafter, the MIS structure 31, a plurality of field regions 38, the interlayer insulating film 40, the gate pad 45, the gate wiring 46, the source pad 47, the drain pad 48, etc. are formed (step S23 in FIG. 20 ). Then, the wafer 50 is cut along a plurality of cutting lines 56. Through the steps including those described above, a plurality of SiC semiconductor devices 1A are manufactured from one wafer 50.

[0489] The various determination steps described above (steps S2, S9, S11, S17, S19, and S21 in FIG. 20 ) may be determined in advance in the step of preparing wafer 50 (step S1 in FIG. 20 ). In other words, SiC semiconductor device 1A may be manufactured along a predetermined manufacturing line.

[0490] Fig. 24 is a plan view showing a SiC semiconductor device 1B according to a second embodiment. Fig. 25A is a cross-sectional view taken along line XXVA-XXVA shown in Fig. 24. Fig. 25B is a cross-sectional view taken along line XXVB-XXVB shown in Fig. 24. Fig. 26A is a plan view showing an example layout of chip 2 (first layer 8). Fig. 26B is a plan view showing an example layout of chip 2 (second layer 9). Fig. 27 is a perspective view showing an example layout of chip 2.

[0491] 24 to 27, SiC semiconductor device 1B includes chip 2, base layer 6, stacked portion 7 (first layer 8 and second layer 9), active region 10 and peripheral region 11, similar to SiC semiconductor device 1A.

[0492] In this embodiment, the SiC semiconductor device 1B includes an active surface 71, an outer surface 72, and first to fourth connecting surfaces 73A to 73D formed on the first main surface 3. The active surface 71, the outer surface 72, and the first to fourth connecting surfaces 73A to 73D define an active plateau 74 on the first main surface 3.

[0493] The active surface 71 may be referred to as a “first surface portion,” the outer peripheral surface 72 may be referred to as a “second surface portion,” the first to fourth connecting surfaces 73A to 73D may be referred to as “connecting surface portions,” and the active plateau 74 may be referred to as a “mesa portion.” The active surface 71, the outer peripheral surface 72, and the first to fourth connecting surfaces 73A to 73D (i.e., the active plateau 74) may be considered to be components of the chip 2 (first main surface 3).

[0494] The active surface 71 is formed in the active region 10. That is, the active surface 71 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 71 has a flat surface extending in the first direction X and the second direction Y. In this embodiment, the active surface 71 is formed by the c-plane (Si-plane). In this embodiment, the active surface 71 is formed in a quadrilateral shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0495] The outer peripheral surface 72 is formed in the outer peripheral region 11. In other words, the outer peripheral surface 72 is formed outside the active surface 71. The outer peripheral surface 72 is recessed in the thickness direction of the chip 2 (toward the second main surface 4) with respect to the active surface 71. Specifically, in this embodiment, the outer peripheral surface 72 is recessed to a depth less than the thickness of the second layer 9 so as to expose the second layer 9. The outer peripheral surface 72 extends in a band shape along the active surface 71 in a plan view, and is formed in a ring shape (specifically, a square ring) surrounding the active surface 71.

[0496] The outer peripheral surface 72 has a flat surface extending in the first direction X and the second direction Y, and is formed substantially parallel to the active surface 71. In this embodiment, the outer peripheral surface 72 is formed by the c-plane (Si-plane). The outer peripheral surface 72 is continuous with the first to fourth side surfaces 5A to 5D. The outer peripheral surface 72 has a circumferential depth DO.

[0497] The peripheral depth DO may be 0.1 μm or more and 2 μm or less. The peripheral depth DO may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less. The peripheral depth DO is preferably 0.1 μm or more and 1.5 μm or less.

[0498] The first to fourth connection surfaces 73A to 73D extend in the vertical direction Z and connect the active surface 71 and the outer peripheral surface 72. The first connection surface 73A is located on the first side surface 5A side, the second connection surface 73B is located on the second side surface 5B side, the third connection surface 73C is located on the third side surface 5C side, and the fourth connection surface 73D is located on the fourth side surface 5D side. The first connection surface 73A and the third connection surface 73C extend in the first direction X and face the second direction Y. The second connection surface 73B and the fourth connection surface 73D extend in the second direction Y and face the first direction X.

[0499] The first to fourth connection surfaces 73A to 73D may extend substantially perpendicularly between the active surface 71 and the outer peripheral surface 72 so as to define a quadrangular pillar-shaped active plateau 74. The first to fourth connection surfaces 73A to 73D may be inclined obliquely downward from the active surface 71 toward the outer peripheral surface 72 so as to define a quadrangular pyramid-shaped active plateau 74. In this manner, the active plateau 74 is defined in a protruding shape on the second layer 9 on the first main surface 3. The active plateau 74 is formed only on the second layer 9, and not on the first layer 8.

[0500] The SiC semiconductor device 1B includes a plurality of p-type first inversion columns 14, a plurality of first non-inversion columns 15, a plurality of second inversion columns 16, and a plurality of second non-inversion columns 17 formed in the stack portion 7 in the active region 10. The plurality of first inversion columns 14 and the plurality of second inversion columns 16 may have at least one of the features shown in the first to third basic forms.

[0501] The first reversing columns 14 and the second reversing columns 16 may have at least one of the features described in the first to sixth embodiments. The first reversing columns 14 and the second reversing columns 16 may have a combination of two or more of the features described in the first to sixth embodiments.

[0502] In this embodiment, the first inverted columns 14 are each formed in a region surrounded in plan view by at least the periphery (first to fourth connection surfaces 73A to 73D) of the active surface 71. In this embodiment, the first inverted columns 14 are drawn out from the active region 10 to the outer peripheral region 11 across the region directly below the first to fourth connection surfaces 73A to 73D (see FIG. 26A).

[0503] That is, the multiple first inversion columns 14 extend from a portion of the first layer 8 facing the active surface 71 to a portion of the first layer 8 facing the outer peripheral surface 72. The multiple first inversion columns 14 are also arranged at intervals in the first arrangement direction Da1 in the outer peripheral region 11, and are each formed in a strip shape extending in the first extension direction De1. The multiple first inversion columns 14 are formed at intervals from the outer peripheral surface 72 to the lower end side of the first layer 8 in the outer peripheral region 11, and face the outer peripheral surface 72 with the second layer 9 between them.

[0504] Furthermore, the multiple first inversion columns 14 extend from the outer peripheral region 11 toward either or both of the first side surface 5A and the third side surface 5C (both in this embodiment), and each have a portion exposed from either or both of the first side surface 5A and the third side surface 5C (both in this embodiment).

[0505] In this embodiment, the first non-inverted columns 15 are each formed in a region surrounded in plan view by at least the periphery (first to fourth connection surfaces 73A to 73D) of the active surface 71. In this embodiment, the first non-inverted columns 15 are drawn out from the active region 10 to the outer peripheral region 11 across the region directly below the first to fourth connection surfaces 73A to 73D (see FIG. 26A ).

[0506] That is, the multiple first non-inverted columns 15 extend from a portion of the first layer 8 facing the active surface 71 to a portion of the first layer 8 facing the outer peripheral surface 72. The multiple first non-inverted columns 15 are also arranged at intervals in the first arrangement direction Da1 in the outer peripheral region 11, and are each formed in a strip shape extending in the first extension direction De1. The multiple first non-inverted columns 15 are formed at intervals from the outer peripheral surface 72 to the lower end side of the first layer 8 in the outer peripheral region 11, and face the outer peripheral surface 72 with the second layer 9 interposed therebetween.

[0507] Furthermore, the multiple first non-inverting columns 15 extend from the outer peripheral region 11 toward either or both of the first side surface 5A and the third side surface 5C (both in this embodiment), and each have a portion exposed from either or both of the first side surface 5A and the third side surface 5C (both in this embodiment).

[0508] In this embodiment, the second inverted columns 16 are each formed in a region surrounded in plan view by at least the periphery (first to fourth connection surfaces 73A to 73D) of the active surface 71. In this embodiment, the second inverted columns 16 extend from a portion of the second layer 9 located in the active region 10 to a portion of the second layer 9 located in the outer peripheral region 11.

[0509] The portions of the second reversing columns 16 located in the outer circumferential region 11 may have a thickness less than that of the first reversing columns 14. Of course, the portions of the second reversing columns 16 located in the outer circumferential region 11 may have a thickness equal to or greater than that of the first reversing columns 14.

[0510] In the active region 10, the lower ends of the second inversion columns 16 are located in a region closer to the lower end of the second layer 9 than the depth position of the outer circumferential surface 72 in the thickness direction of the second layer 9. In addition, in the active region 10, the upper ends of the second inversion columns 16 are located in a region closer to the active surface 71 than the outer circumferential surface 72 in the thickness direction of the second layer 9.

[0511] Therefore, the second reversing columns 16 are exposed from at least one of the first to fourth connecting surfaces 73A to 73D that is perpendicular to the second extending direction De2. In this embodiment, the second reversing columns 16 are exposed from both the second connecting surface 73B and the fourth connecting surface 73D.

[0512] Of course, when the first connection surface 73A is formed along the second extension direction De2 from the middle of the second reversing column 16, the second reversing column 16 may be exposed from the entire first connection surface 73A. Also, when the third connection surface 73C is formed along the second extension direction De2 from the middle of the second reversing column 16, the second reversing column 16 may be exposed from the entire third connection surface 73C.

[0513] Furthermore, when the second extension direction De2 is perpendicular to the first connection surface 73A and the third connection surface 73C, the second reversing columns 16 may be exposed from either or both of the first connection surface 73A and the third connection surface 73C. In these cases, the second reversing columns 16 may be exposed from the entire area of ​​either or both of the second connection surface 73B and the fourth connection surface 73D.

[0514] The second reversing columns 16 are also arranged at intervals in the second arrangement direction Da2 in the outer peripheral region 11, and are each formed in a strip shape extending in the second extension direction De2. The second reversing columns 16 are exposed from the outer peripheral surface 72 in the outer peripheral region 11.

[0515] Furthermore, the multiple second inversion columns 16 extend from the outer peripheral region 11 toward either or both (in this embodiment, both) of the second side surface 5B and the fourth side surface 5D, and each have a portion exposed from either or both (in this embodiment, both) of the second side surface 5B and the fourth side surface 5D.

[0516] In this embodiment, the second non-inversion columns 17 are each formed in a region surrounded in plan view by at least the periphery (first to fourth connection surfaces 73A to 73D) of the active surface 71. In this embodiment, the second non-inversion columns 17 are extended from a portion of the second layer 9 located in the active region 10 to a portion of the second layer 9 located in the outer peripheral region 11.

[0517] The portions of the second non-inverting columns 17 located in the outer circumferential region 11 may have a thickness less than that of the first inverting columns 14. Of course, the portions of the second non-inverting columns 17 located in the outer circumferential region 11 may have a thickness equal to or greater than that of the first inverting columns 14.

[0518] In the active region 10, the lower ends of the second non-inversion columns 17 are located in a region closer to the lower end of the second layer 9 than the depth position of the outer circumferential surface 72 in the thickness direction of the second layer 9. In addition, in the active region 10, the upper ends of the second non-inversion columns 17 are located in a region closer to the active surface 71 than the outer circumferential surface 72 in the thickness direction of the second layer 9.

[0519] Therefore, the second non-inverting columns 17 are exposed from at least one of the first to fourth connection surfaces 73A to 73D that is perpendicular to the second extending direction De2. In this embodiment, the second non-inverting columns 17 are exposed from both the second connection surface 73B and the fourth connection surface 73D.

[0520] Of course, when the first connection surface 73A is formed along the second extension direction De2 from the middle of the second non-inverting column 17, the second non-inverting column 17 may be exposed from the entire first connection surface 73A. Furthermore, when the third connection surface 73C is formed along the second extension direction De2 from the middle of the second non-inverting column 17, the second non-inverting column 17 may be exposed from the entire third connection surface 73C.

[0521] Furthermore, when the second extension direction De2 is perpendicular to the first connection surface 73A and the third connection surface 73C, the second non-inverting columns 17 may be exposed from either or both of the first connection surface 73A and the third connection surface 73C. In these cases, the second non-inverting columns 17 may be exposed from the entire area of ​​either or both of the second connection surface 73B and the fourth connection surface 73D.

[0522] The second non-inverting columns 17 are also arranged at intervals in the second arrangement direction Da2 in the outer peripheral region 11, and are each formed in a strip shape extending in the second extension direction De2. The second non-inverting columns 17 are exposed from the outer peripheral surface 72 in the outer peripheral region 11.

[0523] Furthermore, the multiple second non-inverted columns 17 extend from the outer peripheral region 11 toward either or both of the second side surface 5B and the fourth side surface 5D (both in this embodiment), and each have a portion exposed from either or both of the second side surface 5B and the fourth side surface 5D (both in this embodiment).

[0524] Fig. 28 is a plan view showing a main part of active region 10. Fig. 29 is a cross-sectional perspective view showing gate structure 35 according to the first embodiment. With reference to Figs. 28 and 29, SiC semiconductor device 1B includes MIS structure 31 formed in active region 10. The following configurations will be described as components of SiC semiconductor device 1B, but are also components of MIS structure 31.

[0525] The SiC semiconductor device 1B includes a p-type body region 32 formed in a surface layer portion of the first main surface 3 (active surface 71). In this embodiment, the body region 32 is formed in a layer shape extending along the active surface 71. The body region 32 may be formed over the entire active surface 71 and exposed from the first to fourth connection surfaces 73A to 73D.

[0526] The body region 32 is formed at an interval from the lower end of the second layer 9 toward the active surface 71, and overlaps with the second inverted columns 16 and the second non-inverted columns 17 in the stacking direction. The body region 32 is preferably formed at an interval from the depth position of the outer peripheral surface 72 toward the active surface 71, and is exposed from the first main surface 3.

[0527] When the second non-inverted columns 17 are formed at intervals from the first main surface 3, the body region 32 is formed in a region between the active surface 71 and the upper ends of the second non-inverted columns 17. The body region 32 is preferably connected to the second non-inverted columns 17 (upper ends).

[0528] The body region 32 is formed of a random impurity region introduced into the surface portion of the second layer 9 by random implantation into the second layer 9 (see also FIG. 7 ). Therefore, the body region 32 has a thickness along the second axial channel CH2 that is less than the second region thickness TR2 of the second inversion column 16. The thickness of the body region 32 is less than the first region thickness TR1 of the first inversion column 14.

[0529] Unlike the second non-inverted column 17, the body region 32 does not have a gradual portion 22 having a thickness of 0.5 μm or more, but has a concentration gradient including a gradually increasing portion 20, a peak portion 21, and a gradually decreasing portion 23 within a range of 0.5 μm. １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0530] The p-type impurity concentration of the body region 32 is preferably adjusted by at least one trivalent element. The trivalent element of the body region 32 may be the same as or different from the trivalent element of the second non-inversion columns 17, etc. The trivalent element of the body region 32 may be at least one of boron, aluminum, gallium, and indium. Of course, the body region 32 may be formed by utilizing a part of the p-type top layer 30.

[0531] The SiC semiconductor device 1B includes a plurality of trench electrode-type gate structures 35 formed on the first main surface 3 (active surface 71) in the active region 10. The gate structures 35 may also be referred to as "trench gate structures." A gate potential is applied to the plurality of gate structures 35 as a control potential. The plurality of gate structures 35 control inversion and non-inversion of a channel (current path) in the body region 32 in response to the gate potential.

[0532] The multiple gate structures 35 are arranged at intervals inward from the periphery (first to fourth connection surfaces 73A to 73D) of the active surface 71 in the active region 10. In this embodiment, the multiple gate structures 35 are arranged at intervals in the second array direction Da2 and are each formed in a strip shape extending in the second extension direction De2. That is, in this embodiment, the multiple gate structures 35 are arranged in stripes extending along the multiple second inversion columns 16.

[0533] In this example, the second arrangement direction Da2 is the m-axis direction (second direction Y), and the second extension direction De2 is the a-axis direction (first direction X). Of course, the arrangement direction and extension direction of the multiple gate structures 35 are changed depending on the second arrangement direction Da2 and second extension direction De2 of the multiple second inversion columns 16. Therefore, the second arrangement direction Da2 may be the a-axis direction, and the second extension direction De2 may be the m-axis direction. Alternatively, the second arrangement direction Da2 may be a direction other than the a-axis direction and the m-axis direction, and the second extension direction De2 may be a direction other than the a-axis direction and the m-axis direction.

[0534] In this embodiment, the plurality of gate structures 35 are arranged offset from the plurality of second non-inverting columns 17 toward the plurality of second inverting columns 16. Specifically, the plurality of gate structures 35 penetrate the body region 32 at intervals from the plurality of second non-inverting columns 17 and are arranged in a one-to-one correspondence within the plurality of second inverting columns 16. In other words, the plurality of gate structures 35 are arranged alternately with the plurality of second non-inverting columns 17 along the second array direction Da2 and face the plurality of second non-inverting columns 17 in the horizontal direction.

[0535] The plurality of gate structures 35 are formed at intervals from the lower ends of the plurality of second inverted columns 16 toward the active surface 71, and face the plurality of first inverted columns 14 and the plurality of second non-inverted columns 17 across portions of the plurality of second inverted columns 16. The plurality of gate structures 35 are preferably formed at intervals from the middle of the thickness range of the plurality of second inverted columns 16 toward the active surface 71. Of course, the plurality of gate structures 35 may also be formed at a depth position that crosses the middle of the thickness range of the plurality of second inverted columns 16.

[0536] Each gate structure 35 has a trench width WT in the arrangement direction and a trench depth DT in the vertical direction Z. The trench width WT is less than the second pitch P2 (first pitch P1). The trench depth DT is less than the second thickness T2 of the second layer 9. It is preferable that the trench depth DT is approximately equal to the aforementioned peripheral depth DO. Of course, the trench depth DT may be greater than or less than the peripheral depth DO.

[0537] The trench width WT may be 0.1 μm or more and 5 μm or less. The trench width WT may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0538] The trench depth DT may be 0.1 μm or more and 5 μm or less. The trench depth DT may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less. The trench depth DT is preferably 0.1 μm or more and 1.5 μm or less.

[0539] Each gate structure 35 includes a trench 75, an insulating film 76, and a buried electrode 77. The trench 75 is formed in the active surface 71 and defines the wall surface of the gate structure 35. The insulating film 76 covers the wall surface of the trench 75. The insulating film 76 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0540] In this embodiment, the insulating film 76 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 76 includes a silicon oxide film made of an oxide of the chip 2. The buried electrode 77 is buried in the trench 75 with the insulating film 76 therebetween and faces the channel with the insulating film 76 therebetween. The buried electrode 77 may include p-type or n-type conductive polysilicon.

[0541] The SiC semiconductor device 1B includes a plurality of source regions 33 formed on both sides of a plurality of gate structures 35 in a surface layer portion of the first main surface 3 (active surface 71). The plurality of source regions 33 are formed in a surface layer portion of the body region 32. The plurality of source regions 33 have a higher n-type impurity concentration (peak value) than the second layer 9 (second inversion columns 16). The plurality of source regions 33 have a concentration of n-type impurities (peak value) of 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0542] The source regions 33 extend in a strip shape along the corresponding gate structures 35 in a plan view. The source regions 33 are formed at intervals from the bottom of the body region 32 toward the active surface 71, and face the second inversion columns 16 across a part of the body region 32 in the stacking direction. The source regions 33, together with the second inversion columns 16 located directly below them, define channels (current paths) that extend along the wall surfaces of the corresponding gate structures 35.

[0543] The plurality of source regions 33 may face the second non-inversion column 17 across a part of the body region 32 in the stacking direction. Of course, the plurality of source regions 33 may be formed at intervals from the second non-inversion column 17 to the second inversion column 16 side (gate structure 35 side) so as not to face the second non-inversion column 17 in the stacking direction.

[0544] The SiC semiconductor device 1A includes a plurality of contact regions 34 formed in regions between a plurality of gate structures 35 in a surface layer portion of the first main surface 3 (active surface 71). The plurality of contact regions 34 are formed in a surface layer portion of the body region 32.

[0545] The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 32. The p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of second non-inversion columns 17. The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of second non-inversion columns 17. １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0546] The contact regions 34 are interposed in regions between the adjacent source regions 33 and extend in strip shapes along the gate structures 35. The contact regions 34 are formed at intervals from the bottom of the body region 32 toward the active surface 71, and face the second non-inversion columns 17 with a part of the body region 32 sandwiched therebetween in the stacking direction.

[0547] The plurality of contact regions 34 may face the second inverted column 16 across a part of the body region 32 in the stacking direction. Of course, the plurality of contact regions 34 may be formed at intervals from the second inverted column 16 toward the second non-inverted column 17 so as not to face the second inverted column 16 in the stacking direction.

[0548] The configuration of the outer peripheral region 11 side will be described below. Fig. 30 is a perspective view showing the configuration of the outer peripheral region 11. Fig. 31A is a cross-sectional view in the first direction X showing a main part of the outer peripheral region 11. Fig. 31B is a cross-sectional view in the second direction Y showing a main part of the outer peripheral region 11. In Fig. 30, the multiple first reversing columns 14 and the multiple second reversing columns 16 are omitted from illustration.

[0549] The SiC semiconductor device 1B includes a p-type well region 78 formed in a surface layer portion of the outer peripheral surface 72. The well region 78 is formed at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the outer peripheral surface 72 toward the active surface 71 in a plan view, and extends in a band shape along the active surface 71. In this embodiment, the well region 78 is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 71 in a plan view. The well region 78 is drawn out from the surface layer portion of the outer peripheral surface 72 toward the first to fourth connecting surfaces 73A to 73D, and extends along the surface layer portions of the first to fourth connecting surfaces 73A to 73D.

[0550] The well region 78 is electrically connected to the body region 32 in the surface layer portion of the active surface 71, and is electrically connected to the second non-inverted columns 17 at the first to fourth connection surfaces 73A to 73D. The well region 78 is formed at an interval from the lower end of the second layer 9 toward the outer circumferential surface 72, and faces the first layer 8 with a part of the second layer 9 interposed therebetween.

[0551] The bottom of the well region 78 is located closer to the lower end of the second layer 9 than the bottom wall of the gate structure 35. The bottom of the well region 78 is preferably located closer to the outer circumferential surface 72 than the lower ends of the second non-inverted columns 17. It is particularly preferable that the bottom of the well region 78 is located closer to the outer circumferential surface 72 than the intermediate portions of the thickness ranges of the second non-inverted columns 17.

[0552] The well region 78 is formed of a random impurity region introduced into the surface portion of the second layer 9 by random implantation into the second layer 9 (see also FIG. 7 ). Therefore, the well region 78 has a thickness along the second axial channel CH2 that is less than the second region thickness TR2 of the second inversion column 16. The thickness of the well region 78 is less than the first region thickness TR1 of the first inversion column 14.

[0553] Unlike the second non-inverted column 17, the well region 78 does not have a gradual portion 22 having a thickness of 0.5 μm or more, and has a concentration gradient including a gradually increasing portion 20, a peak portion 21, and a gradually decreasing portion 23 within a range of 0.5 μm. １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0554] The well region 78 has a p-type impurity concentration lower than the p-type impurity concentration of the contact region 34. The p-type impurity concentration of the well region 78 is higher than the p-type impurity concentration of the body region 32. Of course, the p-type impurity concentration of the well region 78 may be lower than that of the body region 32. The well region 78 forms a pn junction with the second layer 9.

[0555] The p-type impurity concentration of the well region 78 is preferably adjusted by at least one trivalent element. The trivalent element of the well region 78 may be the same as the trivalent element of the second non-inversion columns 17, etc., or may be a different element from the trivalent element of the second non-inversion columns 17, etc. The trivalent element of the well region 78 may be at least one of boron, aluminum, gallium, and indium.

[0556] SiC semiconductor device 1B includes at least one (preferably two or more and 20 or less) p-type field region 38 formed in the surface layer portion of outer peripheral surface 72 in outer peripheral region 11. The multiple field regions 38 are formed in the surface layer portion of outer peripheral surface 72 in the same manner as in SiC semiconductor device 1A.

[0557] In this embodiment, the field regions 38 are arranged at intervals from the periphery of the active surface 71 (first to fourth connection surfaces 73A to 73D) and the periphery of the chip 2 (first to fourth side surfaces 5A to 5D). Specifically, the field regions 38 are arranged at intervals from the well region 78 toward the periphery of the outer circumferential surface 72. The field regions 38 extend in a band shape along the active surface 71 in a plan view, and are formed in a ring shape (specifically, a rectangular ring) surrounding the active surface 71.

[0558] In this embodiment, the plurality of field regions 38 overlap the three-dimensional lattice-shaped inverted columns (three-dimensional lattice-shaped non-inverted columns) in the stacking direction on the outer peripheral surface 72. In other words, the plurality of field regions 38 are formed in regions above the plurality of intersections of the plurality of first inverted columns 14 and the plurality of second inverted columns 16.

[0559] The multiple field regions 38 intersect with multiple second inversion columns 16 and multiple second non-inversion columns 17 in the portion extending in the first extension direction De1 when viewed in a plane, and intersect with multiple first inversion columns 14 and multiple first non-inversion columns 15 in the portion extending in the second extension direction De2.

[0560] Each field region 38 is connected to a plurality of second inverting columns 16 and a plurality of second non-inverting columns 17 in the portion extending in the first extension direction De1. Each field region 38 may be connected to either or both of the second inverting columns 16 and the second non-inverting columns 17 in the portion extending along the second extension direction De2.

[0561] The plurality of field regions 38 are formed at intervals from the bottom of the second layer 9 toward the outer circumferential surface 72, and face the first layer 8 across a portion of the second layer 9. The plurality of field regions 38 are located closer to the lower end of the second layer 9 than the bottom of the gate structure 35. The bottoms of the plurality of field regions 38 are preferably located closer to the outer circumferential surface 72 than the middle of the thickness range of the second inversion column 16.

[0562] The SiC semiconductor device 1B includes the aforementioned interlayer insulating film 40 that covers the first main surface 3. The interlayer insulating film 40 has a layered structure including a first insulating film 41 and a second insulating film 42. In this embodiment, the first insulating film 41 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connecting surfaces 73A to 73D. The first insulating film 41 is connected to an insulating film 76 on the active surface 71, exposing the buried electrode 77.

[0563] The first insulating film 41 covers the well region 78 and the plurality of field regions 38 on the outer peripheral surface 72. In this embodiment, the first insulating film 41 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the first insulating film 41 may be formed at an interval inward from the periphery of the outer peripheral surface 72, with the second layer 9 exposed from the periphery of the outer peripheral surface 72. The first insulating film 41 covers the well region 78 on the first to fourth connection surfaces 73A to 73D.

[0564] In this embodiment, the second insulating film 42 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connecting surfaces 73A to 73D, sandwiching the first insulating film 41 therebetween. The second insulating film 42 covers the plurality of gate structures 35 in the active region 10. The second insulating film 42 covers the plurality of field regions 38 and well regions 78 in the outer peripheral region 11, sandwiching the first insulating film 41 therebetween. In this embodiment, the second insulating film 42 is continuous with the periphery of the first main surface 3 (the first to fourth side surfaces 5A to 5D). Of course, the second insulating film 42 may be formed spaced inward from the periphery of the outer peripheral surface 72, exposing the periphery of the first main surface 3 together with the first insulating film 41.

[0565] The SiC semiconductor device 1A includes a plurality of contact openings 43 formed in the interlayer insulating film 40. The plurality of contact openings 43 include a plurality of contact openings 43 (not shown) that expose a plurality of gate structures 35 (buried electrodes 77) and a plurality of contact openings 43 that expose a plurality of source regions 33. The plurality of contact openings 43 for the source regions 33 are formed in regions between adjacent plurality of gate structures 35, and expose a plurality of source regions 33 and a plurality of contact regions 34.

[0566] The SiC semiconductor device 1B includes a sidewall structure 79 disposed in the interlayer insulating film 40 so as to cover at least one of the first to fourth connection surfaces 73A to 73D. The sidewall structure 79 is disposed on the first insulating film 41 and is covered by the second insulating film 42. The sidewall structure 79 reduces a step formed between the active surface 71 and the outer peripheral surface 72.

[0567] The sidewall structure 79 is formed in a strip shape extending along at least one of the first to fourth connecting surfaces 73A to 73D. In this embodiment, the sidewall structure 79 is formed in a ring shape (specifically, a rectangular ring shape) extending along the first to fourth connecting surfaces 73A to 73D so as to surround the active surface 71 in a plan view.

[0568] The sidewall structure 79 may have a portion extending in a film-like manner along the outer peripheral surface 72 and a portion extending in a film-like manner along the first to fourth connection surfaces 73A to 73D. In this embodiment, the sidewall structure 79 is formed at an interval from the innermost field region 38 toward the active surface 71, and faces the plurality of second inversion columns 16 and the well region 78 in the horizontal direction and the stacking direction, with the first insulating film 41 sandwiched therebetween. The sidewall structure 79 may face the body region 32, with the first insulating film 41 sandwiched therebetween.

[0569] Similar to the SiC semiconductor device 1A, the SiC semiconductor device 1B includes a gate pad 45, a plurality of gate wirings 46, a source pad 47, and a drain pad 48. The drain pad 48 is formed in the same form as in the first embodiment.

[0570] In this embodiment, the gate pad 45 is disposed on the active surface 71 at a distance from the outer peripheral surface 72 in a plan view. The gate pad 45 is disposed in a region close to the center of one side of the active surface 71 (the second connection surface 73B in this embodiment) in a plan view. Of course, the gate pad 45 may also be disposed in a corner of the active surface 71 or in the center of the active surface 71 in a plan view.

[0571] In this embodiment, the plurality of gate wirings 46 are arranged on the active surface 71 at intervals from the outer peripheral surface 72 in a plan view. The plurality of gate wirings 46 include a first gate wiring 46A and a second gate wiring 46B.

[0572] The first gate wiring 46A is drawn out from the gate pad 45 toward the second connection surface 73B and extends in a line along the periphery of the active surface 71 so as to intersect (specifically, orthogonal to) some (specifically, one end) of the multiple gate structures 35. The first gate wiring 46A penetrates the interlayer insulating film 40 via the multiple contact openings 43 and is electrically connected to one end of the multiple gate structures 35 (buried electrodes 77).

[0573] The second gate wiring 46B is drawn out from the gate pad 45 toward the fourth connection surface 73D and extends in a line along the periphery of the active surface 71 so as to intersect (specifically, orthogonal to) some (specifically, the other ends) of the multiple gate structures 35. The second gate wiring 46B penetrates the interlayer insulating film 40 via the multiple contact openings 43 and is electrically connected to the other ends of the multiple gate structures 35 (buried electrodes 77).

[0574] In this embodiment, the source pad 47 is disposed on the active surface 71 at a distance from the outer peripheral surface 72 in a plan view. The source pad 47 penetrates the interlayer insulating film 40 via a plurality of contact openings 43 and is electrically connected to the body region 32, the plurality of source regions 33, and the plurality of contact regions 34. In other words, the source pad 47 is electrically connected to the plurality of first non-inverting columns 15 and the plurality of second non-inverting columns 17 via the body region 32.

[0575] 32 is a cross-sectional perspective view showing a gate structure 35 according to the second embodiment. The plurality of gate structures 35 according to the first embodiment described above were arranged shifted from the plurality of second non-inverting columns 17 toward the plurality of second inverting columns 16. In contrast, referring to FIG. 32, the plurality of gate structures 35 according to the second embodiment are arranged so as to overlap the plurality of second non-inverting columns 17 in the stacking direction. The plurality of gate structures 35 overlap the plurality of second non-inverting columns 17 in a one-to-one correspondence in the stacking direction.

[0576] Each of the plurality of gate structures 35 has a bottom wall connected to a corresponding second non-inverting column 17. Specifically, each of the plurality of gate structures 35 is formed wider than the corresponding second non-inverting column 17, and has a bottom wall connected to the corresponding second non-inverting column 17 and a side wall connected to the corresponding second inverting column 16.

[0577] That is, the buried electrodes 77 face the corresponding second non-inversion columns 17 across the insulating film 76 in the stacking direction, and face the corresponding second inversion columns 16 across the insulating film 76 in the horizontal direction. The aforementioned multiple source regions 33 and multiple contact regions 34 face the corresponding second inversion columns 16 across a part of the body region 32 in the stacking direction.

[0578] 33 is a cross-sectional perspective view showing a gate structure 35 according to the third embodiment. The gate structures 35 according to the third embodiment each have a layout that does not require consideration of misalignment with the second inverting columns 16 and the second non-inverting columns 17.

[0579] 33 , the plurality of gate structures 35 extend in a direction other than the second extension direction De2 so as to intersect with the plurality of second inversion columns 16 and the plurality of second non-inversion columns 17. In this embodiment, the plurality of gate structures 35 are arranged at intervals in the first arrangement direction Da1 of the first inversion columns 14 and extend in the first extension direction De1 of the first inversion columns 14. In this example, the first arrangement direction Da1 is the a-axis direction (first direction X), and the first extension direction De1 is the m-axis direction (second direction Y).

[0580] The plurality of gate structures 35 may be opposed to the plurality of first inverted columns 14 in a one-to-one correspondence in the stacking direction. Of course, each gate structure 35 may be opposed to the plurality of first inverted columns 14 in the stacking direction. The plurality of gate structures 35 may be opposed to the plurality of first non-inverted columns 15 in a one-to-one correspondence in the stacking direction.

[0581] Of course, each gate structure 35 may be opposed to multiple first non-inverting columns 15 in the stacking direction. The multiple gate structures 35 may be arranged offset from the multiple first inverting columns 14 in the first arrangement direction Da1 and may be opposed to either or both of the first inverting columns 14 and the first non-inverting columns 15 in the stacking direction.

[0582] Of course, the arrangement direction and extension direction of the multiple gate structures 35 are changed depending on the first arrangement direction Da1 and first extension direction De1 of the multiple first inversion columns 14. Therefore, the first arrangement direction Da1 may be the m-axis direction and the first extension direction De1 may be the a-axis direction. Also, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.

[0583] Of course, the arrangement direction of the multiple gate structures 35 may be a direction other than the first arrangement direction Da1 and the second arrangement direction D2. Furthermore, the extension direction of the multiple gate structures 35 may be a direction other than the first extension direction De1 and the second extension direction De2. In other words, the multiple gate structures 35 may intersect both the multiple first inversion columns 14 and the multiple second inversion columns 16 in a plan view.

[0584] For example, the angle (absolute value) between the extension direction of the gate structure 35 and the second extension direction De2 may be greater than 0° and less than 90°. The angle (absolute value) of the gate structure 35 may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° to 36°, 36° to 54°, 54° to 72°, and 72° to 90°. The angle (absolute value) of the gate structure 35 may be set to a value belonging to any one of the ranges of 30°±5°, 45°±5°, and 60°±5°.

[0585] In this embodiment, the buried electrode 77 faces the second inversion columns 16 and the second non-inversion columns 17 across the insulating film 76 in the stacking direction and the horizontal direction. In this embodiment, the source regions 33 and contact regions 34 face the second inversion columns 16 and the second non-inversion columns 17 across a part of the body region 32 in the stacking direction.

[0586] Fig. 34 is a cross-sectional perspective view showing a gate structure 35 according to the fourth embodiment. Referring to Fig. 34, the plurality of gate structures 35 according to the fourth embodiment each have a configuration that contributes to narrowing the pitch. The plurality of gate structures 35 according to the fourth embodiment are particularly effective in realizing narrower p...

Claims

1. a first SiC layer; a second SiC layer stacked on the first SiC layer; a p-type first impurity region formed in the first SiC layer; a p-type second impurity region formed in the second SiC layer; a plurality of n-type first inversion columns formed at intervals in the first SiC layer to invert the conductivity type of the first impurity region; a plurality of n-type second inversion columns formed at intervals in the second SiC layer to invert the conductivity type of the second impurity region.

2. the conductivity type of the first SiC layer is n-type; the conductivity type of the second SiC layer is n-type; the first impurity region inverts the conductivity type of the first SiC layer; 2. The SiC semiconductor device according to claim 1, wherein said second impurity region inverts the conductivity type of said second SiC layer.

3. 2. The SiC semiconductor device according to claim 1, wherein the plurality of second inversion columns cross a boundary between the first SiC layer and the second SiC layer and are connected to the plurality of first inversion columns within the first SiC layer.

4. each of the first inverted columns comprises a single region across a middle portion of the first SiC layer; The SiC semiconductor device of claim 1 , wherein each of the second inversion columns comprises a single region that crosses a middle portion of the second SiC layer.

5. the first SiC layer has a first axial channel in a stacking direction; the second SiC layer has a second axial channel in a stacking direction; a plurality of the first inversion columns extending along the first axial channel; The SiC semiconductor device of claim 1 , wherein the second inverted columns extend along the second axial channel.

6. The first reversal columns extend in a strip shape in a first extension direction in a plan view, 6. The SiC semiconductor device according to claim 1, wherein the second inverted columns extend in a band shape in a second extension direction other than the first extension direction in a plan view and intersect with the first inverted columns.

7. The plurality of first reversal columns extend in a band shape in one direction in a plan view, 6. The SiC semiconductor device according to claim 1, wherein the plurality of second inversion columns extend in a band shape in the one direction in a plan view.

8. a first SiC layer; an n-type second SiC layer stacked on the first SiC layer; a p-type impurity region formed in the first SiC layer; a plurality of n-type first inversion columns formed at intervals in the first SiC layer to invert the conductivity type of the impurity region; a plurality of second p-type inversion columns formed at intervals in the second SiC layer to invert the conductivity type of the second SiC layer.

9. The conductivity type of the first SiC layer is n-type.

9. The SiC semiconductor device according to claim 8, wherein the impurity region inverts the conductivity type of the first SiC layer.

10. The impurity region further includes a plurality of p-type non-inversion columns, each of which is formed in a region partitioned by the plurality of first inversion columns, 9. The SiC semiconductor device according to claim 8, wherein the second inversion columns cross a boundary between the first SiC layer and the second SiC layer and are connected to the non-inversion columns within the first SiC layer.

11. each of the first inverted columns comprises a single region across a middle portion of the first SiC layer; The SiC semiconductor device of claim 8 , wherein each of the second inversion columns comprises a single region that crosses a middle portion of the second SiC layer.

12. the first SiC layer has a first axial channel in a stacking direction; the second SiC layer has a second axial channel in a stacking direction; a plurality of the first inversion columns extending along the first axial channel; The SiC semiconductor device of claim 8 , wherein the second inverted columns extend along the second axial channel.

13. The first reversal columns each extend in a strip shape in a first extension direction in a plan view, 13. The SiC semiconductor device according to claim 8, wherein the second inversion columns each extend in a band shape in a second extension direction other than the first extension direction in a plan view and intersect with the first inversion columns.

14. The first reversing columns each extend in a strip shape in one direction in a plan view, 13. The SiC semiconductor device according to claim 8, wherein the second inversion columns each extend in a strip shape in the one direction in plan view.

15. an n-type first SiC layer; a second SiC layer stacked on the first SiC layer; a p-type impurity region formed in the second SiC layer; a plurality of p-type first inversion columns formed at intervals in the first SiC layer to invert the conductivity type of the first SiC layer; a plurality of n-type second inversion columns formed at intervals in the second SiC layer to invert the conductivity type of the impurity region.

16. the conductivity type of the second SiC layer is n-type; 16. The SiC semiconductor device according to claim 15, wherein the impurity region inverts the conductivity type of the second SiC layer.

17. a plurality of n-type non-inversion columns each formed in an area defined by the plurality of first inversion columns in the first SiC layer; 16. The SiC semiconductor device of claim 15, wherein the second inversion columns cross a boundary between the first SiC layer and the second SiC layer and are connected to the non-inversion columns within the first SiC layer.

18. each of the first inverted columns comprises a single region across a middle portion of the first SiC layer; The SiC semiconductor device of claim 15 , wherein each of the second inversion columns comprises a single region across a middle portion of the second SiC layer.

19. The first reversal columns each extend in a strip shape in a first extension direction in a plan view, The SiC semiconductor device according to any one of claims 15 to 18, wherein the second inverted columns each extend in a band shape in a second extension direction other than the first extension direction in a planar view and intersect with the first inverted columns.

20. The first reversing columns each extend in a strip shape in one direction in a plan view, The SiC semiconductor device according to any one of claims 15 to 18, wherein the plurality of second inversion columns each extend in a band shape in the one direction in a plan view.