SiC SEMICONDUCTOR DEVICE

Abstract

This SiC semiconductor device comprises: a SiC layer including a main surface and having an axial channel in the lamination direction; a p-type impurity region formed in the SiC layer; a trench formed shallower than the impurity region in the main surface and defining a lower region including a portion of the impurity region between the trench and the bottom of the SiC layer; and an n-type inversion column that is formed in the lower region so as to extend along the axial channel and that inverts the conductivity type of the impurity region.

Description

SiC semiconductor device

[0001] This application claims priority to Japanese Patent Application No. 2022-212617 filed with the Japan Patent Office on December 28, 2022, the entire contents of which are incorporated herein by reference. The present disclosure relates to a SiC semiconductor device.

[0002] Patent Document 1 (US2015 / 0028351A1) discloses an electronic device having an impurity region introduced into a silicon carbide layer by channeling implantation.

[0003] US Patent Application Publication No. 2015 / 0028351

[0004] SUMMARY The present disclosure provides a novel SiC semiconductor device.

[0005] The present disclosure provides a SiC semiconductor device including: a SiC layer including a main surface and having an axial channel in a stacking direction; a p-type impurity region formed in the SiC layer; a trench formed in the main surface shallower than the impurity region and defining a lower region including a part of the impurity region between the trench and a bottom of the SiC layer; and an n-type inversion column formed in the lower region so as to extend along the axial channel and inverting the conductivity type of the impurity region.

[0006] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0007] FIG. 1 is a plan view showing a SiC semiconductor device according to a specific embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example of a chip layout. FIG. 4 is a perspective view showing an example of a chip layout. FIG. 5 is a plan view showing an active region and a trench structure according to a first embodiment. FIG. 6 is a cross-sectional perspective view showing an active region and a trench structure according to the first embodiment. FIG. 7 is an enlarged cross-sectional view showing the trench structure according to the first embodiment. FIG. 8 is a graph showing an example of a p-type concentration gradient in an impurity region. FIG. 9 is a graph showing a comparative example of a p-type concentration gradient in an impurity region. FIG. 10 is a graph showing an example of an n-type concentration gradient in a column region. FIG. 11 is a perspective view showing a configuration of a peripheral region. FIG. 12 is a cross-sectional view showing a main portion of the peripheral region. FIG. 13 is a cross-sectional view showing a main portion of the peripheral region. FIG. 14 is a schematic view showing a wafer used in manufacturing a SiC semiconductor device. FIG. 15 is a flowchart showing an example of a method for manufacturing a SiC semiconductor device. FIG. 16A is a cross-sectional perspective view showing an example of a method for manufacturing a SiC semiconductor device. FIG. 16B is a cross-sectional perspective view showing a step subsequent to FIG. 16A. FIG. 16C is a cross-sectional perspective view showing a step subsequent to FIG. 16B. FIG. 16D is a cross-sectional perspective view showing a step subsequent to FIG. 16C. FIG. 16E is a cross-sectional perspective view showing a step subsequent to FIG. 16D. FIG. 16F is a cross-sectional perspective view showing a step subsequent to FIG. 16E. FIG. 16G is a cross-sectional perspective view showing a step subsequent to FIG. 16F. FIG. 16H is a cross-sectional perspective view showing a step subsequent to FIG. 16G. FIG. 16I is a cross-sectional perspective view showing a step subsequent to FIG. 16H. FIG. 16J is a cross-sectional perspective view showing a step subsequent to FIG. 16I. FIG. 16K is a cross-sectional perspective view showing a step subsequent to FIG. 16J. FIG. 16L is a cross-sectional perspective view showing a step subsequent to FIG. 16K. FIG. 16M is a cross-sectional perspective view showing a step subsequent to FIG. 16L. FIG. 16N is a cross-sectional perspective view showing a step subsequent to FIG. 16M. FIG. 16O is a cross-sectional perspective view showing a step subsequent to FIG. 16N. Fig. 17A is a schematic diagram for explaining a crystal orientation measurement step. Fig. 17B is a schematic diagram for explaining a crystal orientation measurement step. Fig. 18A is a schematic diagram for explaining an ion implantation step. Fig. 18B is a schematic diagram for explaining an ion implantation step. Fig. 19 is a cross-sectional perspective view showing a trench structure according to a second embodiment.Fig. 20 is a sectional perspective view showing a trench structure according to a third embodiment. Fig. 21 is a sectional perspective view showing a trench structure according to a fourth embodiment. Fig. 22 is a sectional perspective view showing a SiC semiconductor device according to a first modified example. Fig. 23 is a sectional perspective view showing a SiC semiconductor device according to a second modified example. Fig. 24 is a sectional perspective view showing a SiC semiconductor device according to a third modified example.

[0008] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0009] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0010] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0011] FIG. 1 is a plan view showing a SiC semiconductor device 1 according to a specific embodiment. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1. FIG. 3 is a plan view showing an example layout of a chip 2. FIG. 4 is a perspective view showing an example layout of a chip 2. FIG. 5 is a plan view showing a trench structure 25 according to the first embodiment together with an active region 8. FIG. 6 is a cross-sectional perspective view showing the trench structure 25 according to the first embodiment together with the active region 8. FIG. 7 is an enlarged cross-sectional view showing the trench structure 25 according to the first embodiment.

[0012] 1 to 7 , SiC semiconductor device 1 includes chip 2 including SiC single crystal. Chip 2 may be referred to as a "SiC chip" or a "semiconductor chip." In this embodiment, chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which chip 2 is made of 4H-SiC single crystal, but chip 2 may be made of another polytype.

[0013] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0014] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0015] In the circumferential direction of the chip 2 (counterclockwise in FIG. 1 ) starting from the first side surface 5A, the second side surface 5B is connected to the first side surface 5A, the third side surface 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0016] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0017] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, an axis extending along the vertical direction Z may be referred to as a "vertical axis." Also, below, the first direction X and the second direction Y may be referred to as a "horizontal direction." The horizontal direction is also a direction extending along the first main surface 3.

[0018] 4, the chip 2 (first main surface 3 and second main surface 4) has an off angle θo inclined at a predetermined angle in a predetermined off direction Do with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off direction Do by the off angle θo. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off angle θo.

[0019] The off-direction Do is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle θo may be greater than 0° and less than or equal to 10°. The off-angle θo may have a value belonging to any one of the ranges of greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.

[0020] The off angle θo is preferably 5° or less. The off angle θo is particularly preferably 2° or more and 4.5° or less. The off angle θo is typically set in the range of 4°±0.1°. Of course, this specification does not exclude a configuration in which the off angle θo is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0021] The chip 2 includes an n-type base layer 6 made of SiC single crystal. The base layer 6 may also be referred to as a "base SiC layer," a "base region," or the like. The base layer 6 extends horizontally in a layered manner and forms part of the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the base layer 6 is made of a substrate made of SiC single crystal (i.e., a SiC substrate). The base layer 6 has the off direction Do and off angle θo described above.

[0022] The base layer 6 has a first axis channel C1 along the stacking direction. The first axis channel C1 is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the base layer 6, and is surrounded by atomic rows constituting a crystal axis extending in the stacking direction (crystal growth direction).

[0023] In other words, the first axis channel C1 is a region in which a region with sparse atomic rows extends in the stacking direction and in which the atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in a planar view. The first axis channel C1 is preferably a region surrounded by atomic rows along low-index crystal axes among the crystal axes. The low-index crystal axes are crystal axes in which the absolute values ​​of "a1," "a2," "a3," and "c" are all expressed as 2 or less (preferably 1 or less) with respect to the Miller indices (a1, a2, a3, c) (the same applies hereinafter in this specification).

[0024] In this embodiment, the first axis channel C1 is formed by a region surrounded by atomic rows aligned along the c-axis ((0001) axis) of the SiC single crystal. That is, the first axis channel C1 extends along the c-axis and has the off-direction Do and off-angle θo described above. In other words, the first axis channel C1 is inclined by the off-angle θo from the vertical axis toward the off-direction Do.

[0025] The base layer 6 is 1×10 １８ cm－３ 1x10 or more ２１ cm －３ The n-type impurity concentration of the base layer 6 may have the following peak value. The base layer 6 preferably has an almost constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the base layer 6 is preferably adjusted with a single pentavalent element. It is particularly preferable that the n-type impurity concentration of the base layer 6 is adjusted with a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the base layer 6 is adjusted with nitrogen.

[0026] The base layer 6 has a first thickness T1. The first thickness T1 may be 5 μm or more and 300 μm or less. The first thickness T1 may have a value belonging to any one of the following ranges: 5 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or more, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or more and 300 μm or less. The first thickness T1 is preferably 50 μm or more and 250 μm or less.

[0027] The chip 2 includes a semiconductor layer 7 made of single crystal SiC stacked on a base layer 6. The semiconductor layer 7 may also be referred to as a "SiC layer," a "semiconductor region," or the like. The semiconductor layer 7 extends horizontally in a layered manner and forms part of the first main surface 3 and the first to fourth side surfaces 5A to 5D. The semiconductor layer 7 is made of an epitaxial layer (i.e., a SiC epitaxial layer) grown from the base layer 6.

[0028] The semiconductor layer 7 has a lower end and an upper end. The lower end of the semiconductor layer 7 is the starting point of crystal growth, and the upper end of the semiconductor layer 7 is the ending point of crystal growth. The lower end of the semiconductor layer 7 is also the bottom of the semiconductor layer 7. Since the semiconductor layer 7 is grown continuously from the base layer 6, the lower end of the semiconductor layer 7 coincides with the upper end of the base layer 6.

[0029] The boundary between the base layer 6 and the semiconductor layer 7 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements. The semiconductor layer 7 has an off-direction Do and an off-angle θo that are approximately identical to the off-direction Do and the off-angle θo of the base layer 6.

[0030] The semiconductor layer 7 has a second axis channel C2 extending along the stacking direction. The second axis channel C2 is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the semiconductor layer 7, and is surrounded by atomic rows extending along a crystal axis in the stacking direction (crystal growth direction).

[0031] In other words, the second axis channel C2 is a region in which a region in which atomic rows are sparse extends in the stacking direction and in which atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in a plan view. The second axis channel C2 is preferably a region surrounded by atomic rows along a low-index crystal axis among the crystal axes.

[0032] In this embodiment, the second axis channel C2 is formed by a region surrounded by atomic rows along the c-axis of the SiC single crystal. That is, the second axis channel C2 extends along the c-axis and has an off-direction Do and an off-angle θo. In other words, the second axis channel C2 is inclined from the vertical axis toward the off-direction Do by the off-angle θo. Furthermore, the second axis channel C2 substantially coincides with the first axis channel C1.

[0033] The n-type impurity concentration of the semiconductor layer 7 is preferably lower than the n-type impurity concentration of the base layer 6. The semiconductor layer 7 has a dopant concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the semiconductor layer 7 may have a peak value of the following: The n-type impurity concentration of the semiconductor layer 7 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the semiconductor layer 7 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0034] In this embodiment, the n-type impurity concentration of the semiconductor layer 7 is adjusted by nitrogen. The semiconductor layer 7 may have an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the semiconductor layer 7 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. It is preferable that the semiconductor layer 7 contains a pentavalent element other than phosphorus.

[0035] The n-type impurity concentration of the semiconductor layer 7 is preferably adjusted by at least nitrogen. When the semiconductor layer 7 contains two or more pentavalent elements, the semiconductor layer 7 preferably contains nitrogen and a pentavalent element other than nitrogen. In this case, the semiconductor layer 7 preferably contains either or both of arsenic and antimony as the pentavalent element other than phosphorus and nitrogen.

[0036] The semiconductor layer 7 has a second thickness T2 that is less than the first thickness T1. The second thickness T2 may be 1 μm or more and 10 μm or less. The second thickness T2 may have a value that belongs to any one of the following ranges: 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The second thickness T2 is preferably 2 μm or more and 8 μm or less.

[0037] The SiC semiconductor device 1 includes an active region 8 set in the chip 2. The active region 8 is set in an inner portion of the chip 2 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 8 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The planar area of ​​the active region 8 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0038] The SiC semiconductor device 1 includes a peripheral region 9 set outside the active region 8 in the chip 2. The peripheral region 9 is provided in a region between the periphery of the chip 2 and the active region 8 in a plan view. The peripheral region 9 extends in a band shape along the active region 8 in a plan view and is set in a polygonal ring shape (a square ring in this embodiment) surrounding the active region 8.

[0039] The SiC semiconductor device 1 includes an active surface 10, an outer surface 11, and first to fourth connecting surfaces 12A to 12D formed on a first main surface 3. The active surface 10, the outer surface 11, and the first to fourth connecting surfaces 12A to 12D define an active plateau 13 on the first main surface 3.

[0040] The active surface 10 may be referred to as the “first surface portion,” the outer peripheral surface 11 may be referred to as the “second surface portion,” the first to fourth connecting surfaces 12A to 12D may be referred to as “connecting surface portions,” and the active plateau 13 may be referred to as the “mesa portion.” The active surface 10, the outer peripheral surface 11, and the first to fourth connecting surfaces 12A to 12D (i.e., the active plateaus 13) may be considered to be components of the chip 2 (first main surface 3).

[0041] The active surface 10 is formed in the active region 8. That is, the active surface 10 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 10 has a flat surface extending in the first direction X and the second direction Y. In this embodiment, the active surface 10 is formed by the c-plane (Si-plane). In this embodiment, the active surface 10 is formed in a quadrilateral shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0042] The outer peripheral surface 11 is formed in the outer peripheral region 9. In other words, the outer peripheral surface 11 is formed outside the active surface 10. The outer peripheral surface 11 is recessed in the thickness direction of the chip 2 (toward the second main surface 4) with respect to the active surface 10. Specifically, in this embodiment, the outer peripheral surface 11 is recessed to a depth less than the thickness of the semiconductor layer 7 so as to expose the semiconductor layer 7. In other words, the outer peripheral surface 11 faces the base layer 6 with a part of the semiconductor layer 7 sandwiched therebetween, exposing the semiconductor layer 7.

[0043] The outer peripheral surface 11 extends in a band shape along the active surface 10 in a plan view and is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 10. The outer peripheral surface 11 has a flat surface extending in the first direction X and the second direction Y and is formed substantially parallel to the active surface 10. In this embodiment, the outer peripheral surface 11 is formed by a c-plane (Si-plane). The outer peripheral surface 11 is continuous with the first to fourth side surfaces 5A to 5D.

[0044] The outer peripheral surface 11 has a circumferential depth DO. The circumferential depth DO may be 0.1 μm or more and 2 μm or less. The circumferential depth DO may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less. The circumferential depth DO is preferably 0.1 μm or more and 1.5 μm or less.

[0045] The first to fourth connection surfaces 12A to 12D extend in the vertical direction Z and connect the active surface 10 and the outer peripheral surface 11. The first connection surface 12A is located on the first side surface 5A side, the second connection surface 12B is located on the second side surface 5B side, the third connection surface 12C is located on the third side surface 5C side, and the fourth connection surface 12D is located on the fourth side surface 5D side. The first connection surface 12A and the third connection surface 12C extend in the first direction X and face the second direction Y. The second connection surface 12B and the fourth connection surface 12D extend in the second direction Y and face the first direction X.

[0046] The first to fourth connection surfaces 12A to 12D may extend substantially perpendicularly between the active surface 10 and the outer peripheral surface 11 so as to define the square-prism-shaped active plateaus 13. The first to fourth connection surfaces 12A to 12D may be inclined obliquely downward from the active surface 10 toward the outer peripheral surface 11 so as to define the square-pyramid-shaped active plateaus 13. In this manner, the active plateaus 13 are defined in a protruding shape on the semiconductor layer 7 at the first main surface 3. The active plateaus 13 are formed only on the semiconductor layer 7, and not on the base layer 6.

[0047] 6 and 7 , SiC semiconductor device 1 includes p-type impurity region 15 formed in semiconductor layer 7 at least in a portion located in active region 8. Impurity region 15 has an n-type impurity concentration higher than the n-type impurity concentration of semiconductor layer 7, and inverts the conductivity type of semiconductor layer 7 from n-type to p-type.

[0048] That is, the impurity region 15 contains a trivalent element in addition to the pentavalent element that constitutes the conductivity type of the semiconductor layer 7. The impurity region 15 contains a 1×10 １５ cm －３ 1x10 or more １８ cm－３ The p-type impurity concentration of the impurity region 15 may have the following peak value: The p-type impurity concentration of the impurity region 15 is preferably adjusted by at least one kind of trivalent element.

[0049] It is particularly preferable that the p-type impurity concentration of impurity region 15 is adjusted by a trivalent element that is heavier than carbon. That is, impurity region 15 preferably contains a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the p-type impurity concentration of impurity region 15 is adjusted by aluminum.

[0050] In this embodiment, the impurity region 15 is formed in the semiconductor layer 7 at a distance inward from the periphery of the active region 8, and has a peripheral portion located within the active region 8. Of course, the impurity region 15 may be extended from the active region 8 to the peripheral region 9. In this case, the impurity region 15 may be extended from the portion of the semiconductor layer 7 located in the active region 8 to the portion of the semiconductor layer 7 located in the peripheral region 9.

[0051] Impurity region 15 may extend from outer periphery region 9 toward first to fourth side surfaces 5A to 5D and may be exposed from first to fourth side surfaces 5A to 5D. Of course, impurity region 15 may be formed in semiconductor layer 7 at a distance inward from first to fourth side surfaces 5A to 5D. In this case, the periphery of impurity region 15 may be located within outer periphery region 9.

[0052] The impurity region 15 has an upper end located on the upper end side of the semiconductor layer 7 and a lower end located on the lower end side of the semiconductor layer 7. In this embodiment, the upper end of the impurity region 15 is located in a region closer to the upper end of the semiconductor layer 7 than the intermediate part of the thickness range of the semiconductor layer 7, and the lower end of the impurity region 15 is located in a region closer to the lower end of the semiconductor layer 7 than the intermediate part of the thickness range of the semiconductor layer 7.

[0053] Although not specifically shown in the drawings, the upper end of impurity region 15 may be exposed from first main surface 3. Of course, the upper end of impurity region 15 may be formed at a distance from the upper end of semiconductor layer 7 (i.e., semiconductor layer 7) toward the lower end, and may face first main surface 3 with a part (upper end) of semiconductor layer 7 in between. Such a structure is identified by analyzing the p-type impurity concentration (concentration gradient) of impurity region 15.

[0054] The distance between the first main surface 3 and the upper end of the impurity region 15 may be 0 μm or more and 1 μm or less. The distance between the first main surface 3 and the upper end of the impurity region 15 may have a value belonging to any one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0055] The lower end of impurity region 15 is formed at a distance from the lower end of semiconductor layer 7 (i.e., base layer 6) toward the upper end, and faces base layer 6 across a part (lower end) of semiconductor layer 7. The distance between the lower end of semiconductor layer 7 and the lower end of impurity region 15 may be more than 0 μm and not more than 5 μm. The distance between the lower end of semiconductor layer 7 and the lower end of impurity region 15 may have a value belonging to any one of the ranges of more than 0 μm and not more than 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, and 4 μm to 5 μm.

[0056] The impurity region 15 has a thickness less than the second thickness T2 of the semiconductor layer 7. The thickness of the impurity region 15 may be 1 μm or more and less than 10 μm. The thickness of the impurity region 15 may be a value belonging to any one of the following ranges: 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and less than 10 μm. The thickness of the impurity region 15 is preferably 2 μm or more and 8 μm or less. Of course, the lower end of the impurity region 15 may cross the boundary between the base layer 6 and the semiconductor layer 7 and be located within the base layer 6.

[0057] The impurity region 15 is a p-type channeling region that extends along the second axis channel C2 in the semiconductor layer 7 in a cross-sectional view. That is, the impurity region 15 is an impurity region that is introduced parallel or substantially parallel to a region (the second axis channel C2) that is surrounded by atomic rows along the low-index crystal axis in the semiconductor layer 7, and extends at an angle with respect to the first main surface 3.

[0058] Therefore, the impurity region 15 has an off-direction Do and an off-angle θo that are substantially identical to the off-direction Do and the off-angle θo of the second axis channel C2. In other words, the impurity region 15 is tilted from the vertical axis toward the off-direction Do by the off-angle θo. The impurity region 15 is made of a single impurity region having a thickness (depth) that crosses the middle portion of the semiconductor layer 7 along the second axis channel C2.

[0059] The n-type concentration gradient of the impurity region 15 will be specifically described below. Fig. 8 is a graph (simulation) showing an example of the p-type concentration gradient of the impurity region 15. Fig. 9 is a graph (simulation) showing a comparative example of the p-type concentration gradient of the impurity region 15. In Figs. 8 and 9, the vertical axis represents the p-type impurity concentration of the impurity region 15, and the horizontal axis represents the depth along the second axial channel C2 with the first main surface 3 as the reference (zero point).

[0060] In Figures 8 and 9, 1 x 10 １５ cm －３ A region having the above p-type impurity concentration is defined as an impurity region 15 and is illustrated as a graph. The values ​​of the impurity concentration, thickness, etc. shown below are examples for explaining the basic configuration of the impurity region 15 based on the concentration gradient, and are not intended to uniquely limit the configuration of the impurity region 15. The impurity concentration, thickness, etc. are adjusted to various values ​​depending on the implantation conditions of the trivalent element (dose amount, implantation temperature, implantation energy, etc.).

[0061] 8 is a graph showing the concentration gradient of the impurity region 15 formed by the channeling implantation method when a predetermined trivalent element (here, aluminum) is introduced into the semiconductor layer 7 parallel or nearly parallel to the second axial channel C2 with an implantation energy of 500 KeV or more and 800 KeV or less.

[0062] The dose of the trivalent element is 1×10 １３ cm －２ The thickness of the semiconductor layer 7 is about 5 μm. In Fig. 8, the concentration gradient when the impurity region 15 is formed with an implantation energy of 1500 KeV or more and 2500 KeV or less is shown by a broken line.

[0063] 9 is a graph showing the case where impurity region 15 is formed by random implantation, which shows the concentration gradient of impurity region 15 when a predetermined trivalent element (here, aluminum) is introduced into semiconductor layer 7 in random directions with an implantation energy of 500 KeV or more and 800 KeV or less.

[0064] The random direction is a direction (for example, the vertical direction Z) that is not parallel (or substantially parallel) to the second axial channel C2. The dose of the trivalent element is 1×10 １３ cm －２ The thickness of the semiconductor layer 7 is about 5 μm. In Fig. 9, the concentration gradient when the impurity region 15 is formed with an implantation energy of 1500 KeV or more and 2500 KeV or less is shown by a broken line.

[0065] 8, impurity region 15 has a thickness of 2.5 μm or more and 2.8 μm or less, and has an upper end spaced from first main surface 3 toward the lower end of semiconductor layer 7, and a lower end spaced from the lower end of semiconductor layer 7 toward the upper end. Impurity region 15 has a concentration gradient that gradually decreases from the upper end side toward the lower end side.

[0066] Specifically, the p-type impurity concentration of impurity region 15 has a concentration gradient from the upper end side to the lower end side, including a first gradually increasing portion 16, a first peak portion 17, a first gradual portion 18, and a first gradually decreasing portion 19. First gradually increasing portion 16 is a portion that forms the upper end of impurity region 15, and the p-type impurity concentration gradually increases from the upper end side to first peak portion 17 at a relatively steep rate of increase from the upper end side to the lower end side.

[0067] The first peak portion 17 is a portion having a first peak value P1 (maximum value) of the p-type impurity concentration. The first peak portion 17 is also a main convex concentration transition portion including a series of concentration changes (inflection points) where the p-type impurity concentration changes from an increase (increasing trend) to a decrease (decreasing trend).

[0068] The first gradual portion 18 is formed in a region closer to the lower end than the first peak portion 17, and is a portion where the impurity concentration gradually decreases at a relatively gradual rate. In other words, the first gradual portion 18 is a portion where a constant p-type impurity concentration is maintained within a certain depth range, and forms the main body of the impurity region 15. The p-type impurity concentration of the first gradual portion 18 gradually decreases within a concentration range that is less than the p-type impurity concentration of the first peak portion 17.

[0069] The first gradual portion 18 is defined as a portion having a density decrease rate of 50% or less in a thickness range of at least 0.5 μm. In the example of FIG. 8 , the first gradual portion 18 has a thickness of 1 μm or more and 1.3 μm or less, and has a density decrease rate of 50% or less in the thickness range.

[0070] The first gradual portion 18 occupies a thickness range of at least ¼ of the impurity region 15. Specifically, the proportion of the first gradual portion 18 in the impurity region 15 is at least ⅓. The proportion of the first gradual portion 18 in the impurity region 15 is typically at most ½ (less than ½). Of course, the proportion of the first gradual portion 18 in the impurity region 15 may be at least ½.

[0071] The first gradually tapering portion 19 is a portion that forms the lower end of the impurity region 15. The first gradually tapering portion 19 has a concentration decrease rate that is greater than the concentration decrease rate in the first gradual portion 18, and is a portion where the p-type impurity concentration gradually decreases from the first gradual portion 18 toward the lower end. The concentration decrease rate per unit thickness of the first gradually tapering portion 19 is greater than the concentration decrease rate per unit thickness of the first gradual portion 18.

[0072] In the case of channeling implantation, the thickness (depth) of the impurity region 15 increases with increasing implantation energy. The depth position of the upper end of the impurity region 15 relative to the first main surface 3 increases with increasing implantation energy. The thicknesses of the first gradually increasing portion 16, the first peak portion 17, the first gradual portion 18, and the first gradually decreasing portion 19 increase with increasing implantation energy. On the other hand, the first peak value P1 of the impurity region 15 decreases with increasing implantation energy. This is because the trivalent element is introduced into deeper regions with increasing implantation energy, increasing the p-type impurity concentration in these deep regions.

[0073] Conversely, the depth position of the upper end of impurity region 15 relative to first main surface 3 decreases as the implantation energy decreases. The thicknesses of first gradually increasing portion 16, first peak portion 17, first gradual portion 18, and first gradually decreasing portion 19 also decrease as the implantation energy decreases. Meanwhile, first peak value P1 of impurity region 15 increases as the implantation energy decreases. This is because trivalent elements are captured in shallower regions as the implantation energy decreases.

[0074] 9 , in the case of the random implantation method, impurity region 15 has first gradually increasing portion 16, first peak portion 17 (first peak value P1), and first gradually decreasing portion 19 within a range of 0.5 μm, but does not have first gradual portion 18 having a thickness of 0.5 μm or more. Furthermore, in the case of the random implantation method, the depth position of first peak portion 17 (first peak value P1) relative to first main surface 3 increased with increasing implantation energy, but the thickness of impurity region 15 was less than 2 μm. In other words, the thickness did not vary significantly even when the implantation energy was increased.

[0075] From this, it can be understood that, since SiC single crystal has physical properties that make it difficult for impurities to diffuse, in the case of the random injection method, it is difficult to form impurity region 15 consisting of a single region and having a relatively large thickness (for example, a thickness of 1 μm or more and 5 μm or less) in semiconductor layer 7 having a relatively large second thickness T2 (for example, 1 μm or more).

[0076] 6 and 7 , SiC semiconductor device 1 includes p-type body region 20 formed in a surface layer portion of first main surface 3 (active surface 10). In this embodiment, body region 20 is formed in a layer shape extending along active surface 10. Body region 20 may be formed over the entire area of ​​active surface 10 and exposed from first to fourth connection surfaces 12A to 12D. Body region 20 is formed at an interval from the lower end of semiconductor layer 7 toward active surface 10.

[0077] Preferably, body region 20 is formed at a distance from the depth position of outer peripheral surface 11 toward active surface 10, and is exposed from active surface 10. When impurity region 15 is formed at a distance from first main surface 3, body region 20 is formed in a region between first main surface 3 and impurity region 15, and is connected to impurity region 15. When impurity region 15 is exposed from first main surface 3, body region 20 is formed in a surface portion of impurity region 15, and is connected to impurity region 15.

[0078] The body region 20 is made of a random region introduced into the surface layer of the semiconductor layer 7 by random implantation into the semiconductor layer 7. Therefore, unlike the impurity region 15, the body region 20 does not have a gentle region such as the first gentle region 18. The body region 20 has a thickness less than the thickness of the impurity region 15 in the direction along the second axial channel C2.

[0079] The body region 20 is 1×10 １５ cm －３ 1x10 or more １８ cm －３The p-type impurity concentration of the body region 20 may have the following peak value: The p-type impurity concentration of the body region 20 is preferably adjusted by at least one trivalent element. The trivalent element of the body region 20 may be at least one of boron, aluminum, gallium, and indium.

[0080] The body region 20 does not necessarily have to be formed. For example, if a part (surface layer) of the impurity region 15 can function as part of the body region 20, the part (surface layer) of the impurity region 15 may be formed as the body region 20, and the body region 20 may be omitted. In other words, the surface layer portion of the impurity region 15 may also serve as the body region 20, and the body region 20 may be formed using the surface layer portion of the impurity region 15. Such a configuration is applicable both to the case where the impurity region 15 is formed at an interval from the first main surface 3 toward the lower end of the semiconductor layer 7, and to the case where the impurity region 15 is exposed from the first main surface 3.

[0081] The SiC semiconductor device 1 includes a plurality of trench electrode-type trench structures 25 formed in the first main surface 3 (active surface 10) in the active region 8. The trench structures 25 may also be referred to as "gate structures," "trench gate structures," or the like. A gate potential serving as a control potential is applied to the plurality of trench structures 25. In response to the gate potential, the plurality of trench structures 25 control inversion and non-inversion of a channel Ch (see FIG. 7 ) serving as a current path in the body region 20.

[0082] The plurality of trench structures 25 are arranged at intervals inward from the periphery (first to fourth connection surfaces 12A to 12D) of the active surface 10 in the active region 8. In this embodiment, the plurality of trench structures 25 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y.

[0083] That is, the trench structures 25 are arranged at intervals in the m-axis direction and extend in the a-axis direction. In this embodiment, the trench structures 25 are arranged in stripes extending in the a-axis direction (second direction Y). The extension direction of the trench structures 25 coincides with the off-direction Do of the semiconductor layer 7.

[0084] The plurality of trench structures 25 are formed at intervals from the lower end (base layer 6) of the semiconductor layer 7 toward the first main surface 3 (active surface 10), and face the base layer 6 across a part of the semiconductor layer 7. The plurality of trench structures 25 define a lower region 7 a in a region between the lower end (base layer 6) of the semiconductor layer 7 and the bottom walls of the plurality of trench structures 25.

[0085] In this embodiment, the plurality of trench structures 25 are formed at intervals from the bottom of the impurity region 15 toward the first main surface 3 (active surface 10), and face a portion (lower end) of the semiconductor layer 7 across a portion (lower end) of the impurity region 15. In other words, the plurality of trench structures 25 are formed shallower than the impurity region 15, and define a lower region 7a that includes a portion (lower end) of the impurity region 15. In this embodiment, the lower region 7a includes a portion (lower end) of the semiconductor layer 7 and a portion (lower end) of the impurity region 15.

[0086] The plurality of trench structures 25 are preferably formed at intervals from the middle of the thickness range of the impurity region 15 toward the active surface 10. Of course, the plurality of trench structures 25 may also be formed at a depth position that crosses the middle of the thickness range of the impurity region 15.

[0087] Each trench structure 25 has a trench width WT in the arrangement direction and a trench depth DT in the vertical direction Z. The trench width WT is preferably less than the second thickness T2 of the semiconductor layer 7. The trench width WT is preferably less than the thickness of the impurity region 15. The trench width WT may be 0.1 μm or more and 5 μm or less.

[0088] The trench width WT may have a value belonging to any one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0089] The trench depth DT is preferably less than the second thickness T2 of the semiconductor layer 7. The trench depth DT is preferably less than the thickness of the impurity region 15. It is particularly preferable that the trench depth DT is approximately equal to the aforementioned peripheral depth DO. Of course, the trench depth DT may be equal to or greater than the peripheral depth DO, or may be less than the peripheral depth DO.

[0090] The trench depth DT is preferably greater than the trench width WT. That is, the trench structures 25 preferably each have an aspect ratio DT / WT such that they extend in a vertically elongated columnar shape. The aspect ratio DT / WT is the ratio of the trench width WT to the trench depth DT. The trench depth DT may be 0.1 μm or more and 5 μm or less.

[0091] The trench depth DT may have a value belonging to any one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, and 4 μm to 5 μm. The trench depth DT is preferably 0.1 μm to 1.5 μm.

[0092] The plurality of trench structures 25 are arranged at intervals of a trench pitch PT in the first direction X. The trench pitch PT is preferably less than the second thickness T2 of the semiconductor layer 7. The trench pitch PT is preferably less than the thickness of the impurity region 15. The trench pitch PT is preferably less than the trench depth DT. The trench pitch PT may be 0.1 μm or more and 5 μm or less.

[0093] The trench pitch PT may have a value belonging to any one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The trench pitch PT is preferably 0.5 μm to 1.5 μm.

[0094] Each trench structure 25 includes a trench 26, an insulating film 27, and a buried electrode 28. The trench 26 is formed in the active surface 10 and defines the wall surfaces (sidewalls and bottom wall) of the trench structure 25. The bottom wall of the trench 26 preferably has a portion that extends flat.

[0095] It is particularly preferable that the flat portion of the bottom wall extends substantially parallel to the first main surface 3. In other words, it is preferable that the bottom wall of the trench 26 has an off angle θo inclined at a predetermined angle in a predetermined off direction Do with respect to the c-plane. In other words, it is preferable that the bottom wall of the trench 26 has a flat portion extending in the off direction Do. Of course, the bottom wall may be curved in an arc shape toward the lower end side of the semiconductor layer 7.

[0096] The insulating film 27 covers the wall surface of the trench 26. The insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 27 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 27 include a silicon oxide film made of an oxide of the chip 2.

[0097] The buried electrode 28 is buried in the trench 26 and faces the channel Ch across the insulating film 27. In this embodiment, the buried electrode 28 faces the impurity region 15 and the body region 20 across the insulating film 27. The buried electrode 28 may include p-type or n-type conductive polysilicon.

[0098] The SiC semiconductor device 1 includes a plurality of n-type inversion columns 30 formed at intervals in the horizontal direction in the semiconductor layer 7. The inversion columns 30 may also be referred to as "first column regions," "inversion column regions," "drift regions," "inversion drift regions," etc. The inversion columns 30 have a higher n-type impurity concentration than the p-type impurity concentration of the impurity regions 15, and invert the conductivity type of the impurity regions 15 from p-type to n-type.

[0099] That is, the inversion column 30 contains a pentavalent element in addition to the trivalent element that constitutes the conductivity type of the impurity region 15. The inversion column 30 has a concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the inversion column 30 may have the following peak value: The n-type impurity concentration of the inversion column 30 is preferably adjusted with at least one pentavalent element. For example, the n-type impurity concentration of the inversion column 30 may be adjusted with at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0100] The inversion column 30 preferably contains a pentavalent element other than nitrogen and phosphorus. The n-type impurity concentration of the inversion column 30 is preferably adjusted with at least one of arsenic, antimony, and bismuth. In view of availability, the n-type impurity concentration of the inversion column 30 is preferably adjusted with arsenic or antimony.

[0101] The multiple inversion columns 30 are formed in the lower region 7a of the semiconductor layer 7. That is, the multiple inversion columns 30 are formed in the thickness range between the lower end of the semiconductor layer 7 and the bottom walls of the multiple trench structures 25. Specifically, the multiple inversion columns 30 are arranged at intervals in the first direction X in the lower region 7a, and are each formed in a strip shape extending in the second direction Y.

[0102] That is, the inversion columns 30 are arranged at intervals in the m-axis direction and extend in the a-axis direction of the SiC single crystal. The inversion columns 30 are also formed in stripes extending in the a-axis direction (second direction Y), and the extending direction of the inversion columns 30 coincides with the off-direction Do of the semiconductor layer 7.

[0103] The multiple inversion columns 30 overlap the multiple trench structures 25 in the stacking direction. Specifically, the multiple inversion columns 30 overlap the multiple trench structures 25 in a one-to-one correspondence in the stacking direction. The multiple inversion columns 30 are formed in the active region 8 at intervals inward from the periphery of the active surface 10 (first to fourth connection surfaces 12A to 12D).

[0104] In the second direction Y, both ends of the multiple inversion columns 30 may be located on the inner side of the active region 8 relative to both ends of the multiple trench structures 25. In the second direction Y, both ends of the multiple inversion columns 30 may be located on the peripheral side of the active region 8 relative to both ends of the multiple trench structures 25.

[0105] When the periphery of the impurity region 15 is located within the active region 8, both ends of the multiple inversion columns 30 may be located on the inner side of the active region 8 relative to the periphery (both ends) of the impurity region 15. Of course, both ends of the multiple inversion columns 30 may be located on the periphery side of the active region 8 relative to the periphery (both ends) of the impurity region 15.

[0106] The multiple inversion columns 30 have upper ends located on the bottom wall side of the trench structure 25 and lower ends located on the lower end side of the semiconductor layer 7. In this configuration, the upper ends of the multiple inversion columns 30 are located in a region on the bottom wall side of the trench structure 25 relative to the intermediate part of the thickness range of the lower region 7a, and the lower ends of the multiple inversion columns 30 are located in a region on the lower end side of the semiconductor layer 7 relative to the intermediate part of the thickness range of the lower region 7a.

[0107] The upper ends of the multiple inversion columns 30 are formed at intervals toward the lower end of the semiconductor layer 7 relative to the depth position of the outer circumferential surface 11. The upper ends of the multiple inversion columns 30 are formed at intervals toward the lower end of the semiconductor layer 7 from the bottom walls of the multiple trench structures 25, and face the multiple trench structures 25 with part of the impurity region 15 in between. In other words, the upper ends of the multiple inversion columns 30 are electrically connected to the relatively high-concentration impurity region 15. Of course, the upper ends of the multiple inversion columns 30 may also be connected to the bottom walls of the multiple trench structures 25.

[0108] The intermediate distance between the bottom walls of the trench structures 25 and the upper ends of the inversion columns 30 may be 0 μm to 1 μm, and may have a value in any one of the ranges of 0 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, and 0.75 μm to 1 μm.

[0109] The lower ends of the multiple inversion columns 30 extend across the bottoms of the impurity regions 15 to the lower portion of the semiconductor layer 7. That is, the multiple inversion columns 30 include a portion located in the region between the bottoms of the impurity regions 15 and the bottom walls of the multiple trench structures 25, and a portion located in the region between the lower end of the semiconductor layer 7 and the bottom of the impurity regions 15. The lower ends of the multiple inversion columns 30 are electrically connected to the lower portion of the semiconductor layer 7. That is, the multiple inversion columns 30 are electrically connected to the base layer 6 via part of the semiconductor layer 7.

[0110] The cross-sectional area of ​​the portions of the inversion columns 30 located in the impurity region 15 is preferably larger than the cross-sectional area of ​​the portions of the inversion columns 30 located in the semiconductor layer 7. Of course, the cross-sectional area of ​​the portions of the inversion columns 30 located in the impurity region 15 may be smaller than the cross-sectional area of ​​the portions of the inversion columns 30 located in the semiconductor layer 7.

[0111] In this embodiment, the lower ends of the multiple inversion columns 30 are spaced apart from the lower end of the semiconductor layer 7 toward the bottom of the impurity region 15, and face the base layer 6 across a portion of the semiconductor layer 7. Of course, the lower ends of the multiple inversion columns 30 may cross the boundary between the semiconductor layer 7 and the base layer 6 and be located within the base layer 6. When the lower end of the impurity region 15 is located within the base layer 6, the lower ends of the multiple inversion columns 30 may cross the bottom of the impurity region 15 within the base layer 6.

[0112] The bottom distance between the bottom end of the semiconductor layer 7 and the bottom ends of the plurality of inversion columns 30 may be 0 μm or more and 2 μm or less. The bottom distance may have a value belonging to any one of the ranges of 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0113] The inversion columns 30 are formed by channeling regions extending along the second axis channel C2 in a cross-sectional view. That is, the inversion columns 30 are impurity regions introduced parallel or nearly parallel to a region (second axis channel C2) surrounded by atomic rows along the low-index crystal axis in the semiconductor layer 7, and extend at an angle with respect to the first main surface 3.

[0114] Therefore, the multiple reversing columns 30 have an off direction Do and an off angle θo that are approximately the same as the off direction Do and the off angle θo of the second axis channel C2. In other words, the multiple reversing columns 30 are inclined by the off angle θo from the vertical axis toward the off direction Do. The multiple reversing columns 30 are formed by a single region having a thickness (depth) that crosses the middle portion of the lower region 7 a along the second axis channel C2.

[0115] The multiple inversion columns 30 each have a column width WC in the arrangement direction. The column width WC may be approximately equal to the trench width WT. The column width WC may be greater than the trench width WT. The column width WC may be less than the trench width WT. The column width WC may be less than the trench depth DT. The column width WC may be greater than the trench depth DT. The column width WC is preferably less than the second thickness T2 of the semiconductor layer 7. The column width WC is preferably less than the thickness of the impurity region 15.

[0116] The column width WC may be 0.1 μm or more and 5 μm or less. The column width WC may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0117] Each of the multiple inversion columns 30 has a column thickness TC (region depth). The column thickness TC is preferably less than the second thickness T2 of the semiconductor layer 7. The column thickness TC is preferably less than the thickness of the impurity region 15. It is particularly preferable that the column thickness TC be equal to or greater than the trench depth DT. It is preferable that the column thickness TC be greater than the trench width WT. It is particularly preferable that the column thickness TC be greater than the trench depth DT. Of course, the column thickness TC may be less than the trench depth DT.

[0118] The column thickness TC may be greater than or equal to 1 and less than or equal to 5 times the trench depth DT. The ratio TC / DT of the column thickness TC to the trench depth DT may have a value belonging to any one of the ranges of 1 to 1.5, 1.5 to 2, 2 to 2.5, 2.5 to 3, 3 to 3.5, 3.5 to 4, 4 to 4.5, and 4.5 to 5.

[0119] The column thickness TC is preferably greater than the column width WC. That is, each of the inverted columns 30 preferably has an aspect ratio TC / WC such that the inverted columns 30 extend in a vertically elongated columnar shape along the second axial channel C2. The aspect ratio TC / WC is the ratio of the column thickness TC to the column width WC. The column thickness TC is preferably 1 μm or more and 5 μm or less.

[0120] The column thickness TC may have a value belonging to any one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0121] The multiple inverted columns 30 are formed at intervals of a column pitch PC in the arrangement direction. The column pitch PC may be approximately equal to the trench pitch PT, or may be larger than the trench pitch PT, or may be smaller than the trench pitch PT.

[0122] The column pitch PC is preferably less than the column thickness TC. The column pitch PC is preferably less than the trench depth DT. The column pitch PC is preferably less than the second thickness T2 of the semiconductor layer 7. The column pitch PC is preferably less than the thickness of the impurity region 15. The column pitch PC may be 0.1 μm or more and 5 μm or less.

[0123] The column pitch PC may have a value belonging to any one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The column pitch PC is preferably 0.5 μm to 1.5 μm.

[0124] The n-type impurity concentration gradient of the inversion column 30 will be specifically described below. Fig. 10 is a graph showing an example of the n-type impurity concentration gradient of the inversion column 30. In Fig. 10, the vertical axis represents the n-type impurity concentration of the inversion column 30, and the horizontal axis represents the depth along the second axial channel C2, with the bottom wall of the trench structure 25 as the reference (zero point).

[0125] In FIG. 10, 1×10 １５ cm －３A region having the above n-type impurity concentration is defined as an inversion column 30 and is shown as a graph. The values ​​of the impurity concentration, thickness, etc. shown below are examples for explaining the basic configuration of the inversion column 30 based on the concentration gradient, and are not intended to uniquely limit the configuration of the inversion column 30. The impurity concentration, thickness, etc. are adjusted to various values ​​depending on the implantation conditions of the pentavalent element (dose amount, implantation temperature, implantation energy, etc.).

[0126] 10 is a graph showing the concentration gradient of the inversion columns 30 formed by channeling implantation, when a predetermined pentavalent element (arsenic in this example) is introduced into the lower region 7a parallel or nearly parallel to the second axial channel C2 with an implantation energy of 500 KeV or more and 800 KeV or less.

[0127] The dose of the pentavalent element is 1×10 １３ cm －２ The trench depth DT is about 1 μm, and the thickness of the lower region 7 a is about 4 μm. In FIG. 10 , the concentration gradient when the inversion columns 30 are formed with an implantation energy of 1500 KeV or more and 2500 KeV or less is shown by a broken line.

[0128] 10 , inversion column 30 has a thickness of 2.1 μm or more and 2.4 μm or less, and has an upper end spaced from the bottom wall of trench structure 25 toward the bottom of impurity region 15, and a lower end spaced from the bottom of impurity region 15 toward the bottom wall of trench structure 25. Inversion column 30 has a concentration gradient that gradually decreases from the upper end toward the lower end.

[0129] Specifically, the n-type impurity concentration of the inversion column 30 has a concentration gradient from the upper end side to the lower end side, including a second gradually increasing portion 31, a second peak portion 32, a second gradual portion 33, and a second gradually decreasing portion 34. The second gradually increasing portion 31 is a portion that forms the upper end of the inversion column 30, and the n-type impurity concentration gradually increases from the upper end side to the lower end side at a relatively steep rate of increase up to the second peak portion 32. In this embodiment, the second gradually increasing portion 31 is located within the impurity region 15 and is electrically connected to the impurity region 15.

[0130] The second peak portion 32 is a portion having a second peak value P2 (maximum value) of the n-type impurity concentration. The second peak portion 32 is also a convex main concentration transition portion including a series of concentration changes (inflection points) where the n-type impurity concentration changes from an increase (increasing trend) to a decrease (decreasing trend). The second peak portion 32 is electrically connected to the impurity region 15. In this embodiment, the second peak value P2 is located closer to the bottom of the impurity region 15 than the first peak value P1 of the impurity region 15.

[0131] The second gradual decrease portion 33 is formed in a region closer to the lower end than the second peak portion 32, and is a portion where the impurity concentration gradually decreases at a relatively gradual rate. In other words, the second gradual decrease portion 33 is a portion where a constant n-type impurity concentration is maintained within a certain depth range, and forms the main body of the inversion column 30. The n-type impurity concentration of the second gradual decrease portion 33 gradually decreases within a concentration range that is less than the n-type impurity concentration of the second peak portion 32.

[0132] The second gradual portion 33 is defined by a portion having a concentration decrease rate of 50% or less in a thickness range of at least 0.5 μm. In the example of FIG. 10 , the second gradual portion 33 has a thickness of 0.8 μm or more and 1.1 μm or less, and has a concentration decrease rate of 50% or less in this thickness range. The second gradual portion 33 is located within the impurity region 15 and electrically connected to the impurity region 15. The second gradual portion 33 may have a portion located in a thickness range between the lower end of the semiconductor layer 7 and the bottom of the impurity region 15, and may be electrically connected to the semiconductor layer 7.

[0133] The second gradual section 33 occupies a thickness range of at least one-quarter of the inverting column 30. Specifically, the proportion of the second gradual section 33 in the inverting column 30 is at least one-third. The proportion of the second gradual section 33 in the inverting column 30 is typically at most one-half (less than one-half). Of course, the proportion of the second gradual section 33 in the inverting column 30 may be at least one-half.

[0134] The second gradually tapering portion 34 forms the lower end of the inversion column 30. The second gradually tapering portion 34 has a concentration decrease rate greater than that of the second gradual portion 33, and is a portion where the n-type impurity concentration gradually decreases from the second gradual portion 33 toward the lower end. The concentration decrease rate per unit thickness of the second gradually tapering portion 34 is greater than that of the second gradual portion 33. The second gradually tapering portion 34 is located in a thickness range between the lower end of the semiconductor layer 7 and the lower end of the impurity region 15, and is electrically connected to the semiconductor layer 7.

[0135] In the case of channeling implantation, the thickness (depth) of the inversion columns 30 increases with increasing implantation energy. The depth position of the upper end of the inversion columns 30 relative to the bottom wall of the trench structure 25 increases with increasing implantation energy. The thicknesses of the second gradually increasing portion 31, the second peak portion 32, the second gradually decreasing portion 33, and the second gradually decreasing portion 34 increase with increasing implantation energy. On the other hand, the second peak value P2 of the inversion columns 30 decreases with increasing implantation energy. This is because the pentavalent element is introduced deeper into the inversion columns 30 as the implantation energy increases, increasing the n-type impurity concentration in the deeper regions.

[0136] Conversely, the depth position of the upper end of the inversion column 30 relative to the bottom wall of the trench structure 25 decreases as the implantation energy decreases. The thicknesses of the second gradually increasing portion 31, the second peak portion 32, the second gradually decreasing portion 33, and the second gradually decreasing portion 34 also decrease as the implantation energy decreases. Meanwhile, the second peak value P2 of the inversion column 30 increases as the implantation energy decreases. This is because the introduction of the pentavalent element is inhibited in shallower regions as the implantation energy decreases.

[0137] In the case of the inversion columns 30, a pentavalent element is introduced into the semiconductor layer 7 instead of a trivalent element, so it should be noted that even if the same process conditions as those for the impurity regions 15 are imposed, the concentration profile and thickness (depth) of the inversion columns 30 are different from those of the impurity regions 15. Therefore, in order to achieve an appropriate charge balance, it is preferable to set the process conditions for the inversion columns 30 and the process conditions for the impurity regions 15 separately.

[0138] The SiC semiconductor device 1 includes a plurality of p-type non-inversion columns 35 formed in the semiconductor layer 7. The non-inversion columns 35 may also be referred to as "second column regions," "non-inversion column regions," etc. Each of the plurality of non-inversion columns 35 is formed from a region of the impurity region 15 that is partitioned by a plurality of inversion columns 30.

[0139] That is, each of the non-inversion columns 35 is composed of a p-type channeling region extending along the second axial channel C2. The non-inversion columns 35 are arranged at intervals in the first direction X (m-axis direction) in the semiconductor layer 7 (lower region 7 a) and are each partitioned into strips extending in the second direction Y (a-axis direction). The non-inversion columns 35 overlap regions between the trench structures 25 in the stacking direction.

[0140] The non-inversion columns 35 form charge-balanced pn junctions together with the inversion columns 30. The charge-balanced state means that, for adjacent non-inversion columns 35, the depletion layer extending from one pn junction and the depletion layer extending from the other pn junction are connected within the inversion columns 30.

[0141] In this configuration, a plurality of p-type non-inversion columns 35, the concentration of which is adjusted by a trivalent element (impurity regions 15), form a charge balance with a plurality of n-type inversion columns 30, the concentration of which is adjusted by a pentavalent element. The plurality of non-inversion columns 35 form a superjunction structure with the plurality of inversion columns 30 in the lower region 7 a.

[0142] The SiC semiconductor device 1 includes a plurality of n-type intermediate regions 36 formed in the semiconductor layer 7 in regions directly below the plurality of trench structures 25. In this embodiment, one intermediate region 36 is interposed in the region between the bottom wall of one trench structure 25 and the upper end of one inversion column 30. The plurality of intermediate regions 36 are arranged at intervals in the first direction X (m-axis direction) in the lower region 7a, and are each formed in a strip shape extending in the second direction Y (a-axis direction).

[0143] With respect to one and the other trench structures 25, the intermediate region 36 on one side located directly below one trench structure 25 is formed at a distance in the arrangement direction (first direction X) of the multiple trench structures 25 from the intermediate region 36 on the other side located directly below the other trench structure 25. The multiple intermediate regions 36 on one side face the multiple intermediate regions 36 on the other side in the arrangement direction (first direction X), with part of the impurity region 15 sandwiched therebetween.

[0144] Each intermediate region 36 is connected to the bottom wall of the trench structure 25 and the upper end of the inverted column 30. Each intermediate region 36 further has portions that extend from the region directly below the trench structure 25 to both sides of the trench structure 25 and along the sidewalls of the trench structure 25.

[0145] Each intermediate region 36 is formed at a distance from the bottom of the body region 20 toward the bottom wall of the trench structure 25, and faces the body region 20 across a part of the impurity region 15. Of course, each intermediate region 36 may be connected to the bottom of the body region 20. Alternatively, each intermediate region 36 may be formed narrower than the bottom wall of the trench structure 25, and may be formed only along the bottom wall of the trench structure 25.

[0146] In the second direction Y, both ends of each intermediate region 36 may be located on the inner side of the active region 8 relative to both ends of the corresponding trench structure 25. In the second direction Y, both ends of the multiple inversion columns 30 may be located on the peripheral side of the active region 8 relative to both ends of the multiple trench structures 25.

[0147] The intermediate regions 36 form charge-balanced intermediate pn junctions together with the non-inversion columns 35. That is, the intermediate regions 36 form part of a superjunction structure together with the non-inversion columns 35. The charge-balanced state means that, for adjacent intermediate regions 36, the depletion layer extending from one intermediate pn junction and the depletion layer extending from the other intermediate pn junction are connected within the non-inversion columns 35.

[0148] The intermediate regions 36 are random regions introduced into the surface portions of the non-inverted columns 35 by random implantation into the semiconductor layer 7. That is, the intermediate regions 36 have a thickness along the second axial channel C2 that is less than the thickness of the inverted columns 30. The intermediate regions 36 do not have second relaxed portions 33 having a thickness of 0.5 μm or more in either direction along the second axial channel C2.

[0149] The plurality of intermediate regions 36 are 1×10 １５ cm －３ 1x10 or more １８ cm －３ The plurality of intermediate regions 36 may have the following n-type impurity concentrations (peak values) as peak values. The plurality of intermediate regions 36 may have n-type impurity concentrations (peak values) higher than the n-type impurity concentrations (peak values) of the plurality of inversion columns 30. Of course, the n-type impurity concentrations (peak values) of the plurality of intermediate regions 36 may be lower than the n-type impurity concentrations (peak values) of the plurality of inversion columns 30.

[0150] The n-type impurity concentration of the intermediate region 36 is preferably adjusted with at least one pentavalent element. For example, the n-type impurity concentration of the intermediate region 36 may be adjusted with at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The intermediate region 36 preferably contains at least phosphorus.

[0151] The SiC semiconductor device 1 includes a plurality of source regions 37 formed on both sides of the plurality of trench structures 25 in a surface layer portion of the first main surface 3 (active surface 10). The plurality of source regions 37 are formed in a surface layer portion of the body region 20. The plurality of source regions 37 have a higher n-type impurity concentration (peak value) than that of the semiconductor layer 7.

[0152] The n-type impurity concentration (peak value) of the plurality of source regions 37 is preferably higher than the n-type impurity concentration (peak value) of the inversion column 30. It is particularly preferable that the n-type impurity concentration (peak value) of the plurality of source regions 37 is higher than the n-type impurity concentration (peak value) of the intermediate region 36. The plurality of source regions 37 has a peak impurity concentration of 1×10 １８ cm －３ 1x10 or more ２１ cm－３ The n-type impurity concentration may have the following peak value:

[0153] The multiple source regions 37 extend in a strip shape in the extension direction of the corresponding trench structures 25 in a plan view. The multiple source regions 37 are formed at intervals from the bottom of the body region 20 toward the active surface 10. The multiple source regions 37, together with the intermediate region 36 located directly below, define a channel Ch as a current path extending along the wall surface of the corresponding trench structure 25. In this configuration, the multiple source regions 37 face a part of the impurity region 15 in the stacking direction, sandwiching a part of the body region 20 therebetween. Therefore, the channel Ch is formed in a part of the impurity region 15 and a part of the body region 20.

[0154] The SiC semiconductor device 1 includes a plurality of contact regions 38 formed in regions between the plurality of trench structures 25 in a surface layer portion of the first main surface 3 (active surface 10). The plurality of contact regions 38 are formed in a surface layer portion of the body region 20.

[0155] The plurality of contact regions 38 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the impurity region 15. The p-type impurity concentration (peak value) of the plurality of contact regions 38 is higher than the p-type impurity concentration (peak value) of the body region 20. The plurality of contact regions 38 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the body region 20. １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0156] The contact regions 38 are interposed between adjacent source regions 37 and extend in strip shapes in the extension direction of the trench structures 25. The contact regions 38 are formed at intervals from the bottom of the body region 20 toward the active surface 10 in the stacking direction, and face the non-inversion column 35 directly below, sandwiching a part of the body region 20 therebetween.

[0157] The configuration of the outer peripheral region 9 will be described below. Fig. 11 is a perspective view showing the configuration of the outer peripheral region 9. Fig. 12 is a cross-sectional view showing a main part of the outer peripheral region 9. Fig. 13 is a cross-sectional view showing a main part of the outer peripheral region 9.

[0158] The SiC semiconductor device 1 includes a p-type well region 39 formed in a surface layer portion of the outer peripheral surface 11. The well region 39 is formed at an interval from the periphery of the outer peripheral surface 11 (first to fourth side surfaces 5A to 5D) toward the active surface 10 in a plan view, and extends in a band shape along the active surface 10. In this embodiment, the well region 39 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 10 in a plan view.

[0159] The well region 39 is drawn out from the surface layer portion of the outer peripheral surface 11 toward the first to fourth connection surfaces 12A to 12D and extends along the surface layer portions of the first to fourth connection surfaces 12A to 12D. The well region 39 is electrically connected to the body region 20 in the surface layer portion of the active surface 10.

[0160] The well region 39 is formed at a distance from the lower end of the semiconductor layer 7 toward the outer peripheral surface 11, and faces the base layer 6 across a part of the semiconductor layer 7. Specifically, the well region 39 is formed at a distance from the bottom of the impurity region 15 toward the outer peripheral surface 11, and is located closer to the bottom of the impurity region 15 than the bottom wall of the trench structure 25. The well region 39 forms a pn junction with the semiconductor layer 7 (impurity region 15).

[0161] The well region 39 is made of a random region introduced into the surface layer of the semiconductor layer 7 by random implantation into the semiconductor layer 7. The well region 39 has a thickness in the direction along the second axial channel C2 that is less than the thickness of the impurity region 15. The thickness of the well region 39 is also less than the thickness of the inversion column 30.

[0162] Unlike the inverted column 30, the well region 39 does not have a slack portion having a thickness of 0.5 μm or more. １５ cm －３ 1x10 or more １８ cm －３The well region 39 may have a p-type impurity concentration below the peak value. The well region 39 has a p-type impurity concentration lower than the p-type impurity concentration of the contact region 38. The p-type impurity concentration of the well region 39 may be higher than the p-type impurity concentration of the body region 20. Of course, the p-type impurity concentration of the well region 39 may be lower than that of the body region 20.

[0163] The p-type impurity concentration of well region 39 is preferably adjusted by at least one trivalent element. The trivalent element of well region 39 may be the same as or different from the trivalent element of impurity region 15. The trivalent element of well region 39 may be at least one of boron, aluminum, gallium, and indium.

[0164] The SiC semiconductor device 1 includes at least one (preferably two to 20) p-type field region 40 formed in the surface layer of the outer peripheral surface 11 (first main surface 3) in the outer peripheral region 9. The number of the multiple field regions 40 is typically four to eight. The multiple field regions 40 are formed in an electrically floating state and relieve the electric field within the chip 2 at the periphery of the first main surface 3. The number, width, depth, p-type impurity concentration, etc. of the field region 40 are arbitrary and can take various values ​​depending on the electric field to be relieved.

[0165] In this embodiment, the field regions 40 are arranged at intervals from the periphery (first to fourth connection surfaces 12A to 12D) of the active surface 10 and the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. Specifically, the field regions 40 are arranged at intervals from the well region 39 toward the periphery of the outer circumferential surface 11.

[0166] The field regions 40 are formed in strip shapes extending along the active region 8 in plan view. Each of the field regions 40 has a strip-like portion extending in the first direction X and a strip-like portion extending in the second direction Y. In this embodiment, the field regions 40 are formed in an annular shape (specifically, a rectangular annular shape) surrounding the active region 8 (i.e., the inversion columns 30) in plan view.

[0167] The plurality of field regions 40 are formed in the semiconductor layer 7 at intervals from the lower end of the semiconductor layer 7 toward the outer circumferential surface 11, and form pn junctions with the semiconductor layer 7. The plurality of field regions 40 preferably have bottoms located closer to the outer circumferential surface 11 than the intermediate portion of the thickness range of the semiconductor layer 7.

[0168] In this embodiment, the field regions 40 are formed at intervals from the inversion columns 30 toward the periphery of the chip 2, and do not face the inversion columns 30 in the stacking direction. The field regions 40 are located closer to the bottom of the semiconductor layer 7 (impurity regions 15) than the bottom wall of the trench structure 25.

[0169] The bottoms of the field regions 40 may be located closer to the bottom of the semiconductor layer 7 than the depth positions of the upper ends of the inversion columns 30. Of course, the bottoms of the field regions 40 may be located closer to the outer circumferential surface 11 than the depth positions of the upper ends of the inversion columns 30.

[0170] The field regions 40 are random regions introduced into the surface layer of the semiconductor layer 7 by random implantation into the semiconductor layer 7. The field regions 40 have a thickness in the direction along the second axial channel C2 that is less than the thickness of the impurity region 15. The thickness of the field regions 40 is also less than the thickness of the inversion column 30.

[0171] Unlike the inversion columns 30 and the like, the field regions 40 do not have any slack portions having a thickness of 0.5 μm or more. １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration of the field region 40 may be lower than the p-type impurity concentration of the contact region 38 .

[0172] The p-type impurity concentration of the field region 40 may be approximately equal to the p-type impurity concentration of the body region 20. The p-type impurity concentrations of the plurality of field regions 40 may be higher than the p-type impurity concentration of the body region 20. The p-type impurity concentrations of the plurality of field regions 40 may be lower than the p-type impurity concentration of the body region 20.

[0173] The p-type impurity concentrations of the plurality of field regions 40 are preferably adjusted by at least one trivalent element. The trivalent element in the field region 40 may be the same as or different from the trivalent element in the impurity region 15. The trivalent element in the field region 40 may be at least one of boron, aluminum, gallium, and indium.

[0174] The field regions 40 preferably have a width different from the column width WC of the inversion columns 30. In other words, the electric field relaxation effect of the field regions 40 is preferably adjusted separately from the inversion columns 30. It is particularly preferable that the width of the field regions 40 be greater than the column width WC. Of course, the width of the field regions 40 may be smaller than the column width WC. Alternatively, the width of the inversion columns 30 may be approximately equal to the column width WC.

[0175] The plurality of field regions 40 are preferably formed at a pitch different from the column pitch PC of the inverted columns 30. It is particularly preferable that the pitch of the plurality of field regions 40 be larger than the column pitch PC. The pitch of the plurality of field regions 40 may be smaller than the column pitch PC. The pitch of the plurality of field regions 40 may also be approximately equal to the column pitch PC.

[0176] The SiC semiconductor device 1 includes an interlayer insulating film 41 covering the first main surface 3. The interlayer insulating film 41 may also be referred to as an "insulating film," an "interlayer film," an "intermediate insulating film," or the like. In this embodiment, the interlayer insulating film 41 has a stacked structure including a first insulating film 42 and a second insulating film 43. The first insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is particularly preferable that the first insulating film 42 include a silicon oxide film made of an oxide of the chip 2 (semiconductor layer 7).

[0177] The first insulating film 42 selectively covers the first main surface 3 in the active region 8 and the peripheral region 9. Specifically, the first insulating film 42 selectively covers the active surface 10, the peripheral surface 11, and the first to fourth connecting surfaces 12A to 12D. The first insulating film 42 is connected to the insulating film 27 on the active surface 10, exposing the buried electrode 28.

[0178] The first insulating film 42 covers the well region 39 and the multiple field regions 40 on the outer peripheral surface 11. In this embodiment, the first insulating film 42 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the first insulating film 42 may be formed at an interval inward from the periphery of the outer peripheral surface 11, exposing the semiconductor layer 7 from the periphery of the outer peripheral surface 11. The first insulating film 42 covers the body region 20 and the well region 39 on the first to fourth connecting surfaces 12A to 12D.

[0179] The second insulating film 43 is stacked on the first insulating film 42. The second insulating film 43 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 41 preferably includes a silicon oxide film. The second insulating film 43 covers the first main surface 3 in the active region 8 and the peripheral region 9, sandwiching the first insulating film 42 therebetween. Specifically, the second insulating film 43 selectively covers the active surface 10, the peripheral surface 11, and the first to fourth connecting surfaces 12A to 12D, sandwiching the first insulating film 42 therebetween.

[0180] The second insulating film 43 covers the multiple trench structures 25 (buried electrodes 28) in the active region 8. The second insulating film 43 covers the well region 39 and the multiple field regions 40 on the periphery of the outer periphery region 9, sandwiching the first insulating film 42 therebetween. In this embodiment, the second insulating film 43 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the second insulating film 43 may be formed at a distance inward from the periphery of the outer periphery surface 11, and may expose the periphery of the first main surface 3 together with the first insulating film 42.

[0181] The SiC semiconductor device 1 includes a plurality of contact openings 44 formed in an interlayer insulating film 41. The plurality of contact openings 44 include a plurality of contact openings 44 (not shown) that expose the plurality of trench structures 25 (buried electrodes 28) and a plurality of contact openings 44 that expose the plurality of source regions 37. The plurality of contact openings 44 for the source regions 37 are formed in regions between the plurality of adjacent trench structures 25, and expose the plurality of source regions 37 and the plurality of contact regions 38.

[0182] The SiC semiconductor device 1 includes a sidewall structure 45 disposed in the interlayer insulating film 41 so as to cover at least one of the first to fourth connecting surfaces 12A to 12D. The sidewall structure 45 is disposed on the first insulating film 42 and is covered by the second insulating film 43. The sidewall structure 45 reduces a step formed between the active surface 10 and the outer peripheral surface 11.

[0183] The sidewall structure 45 is formed in a strip shape extending along at least one of the first to fourth connecting surfaces 12A to 12D. In this embodiment, the sidewall structure 45 is formed in a ring shape (specifically, a rectangular ring shape) extending along the first to fourth connecting surfaces 12A to 12D so as to surround the active surface 10 in a plan view.

[0184] The sidewall structure 45 may have a portion extending in a film-like manner along the outer peripheral surface 11 and a portion extending in a film-like manner along the first to fourth connecting surfaces 12A to 12D. In this embodiment, the sidewall structure 45 is formed at a distance from the innermost field region 40 toward the active surface 10, and faces the well region 39 in the horizontal direction and the stacking direction, with the first insulating film 42 sandwiched therebetween. The sidewall structure 45 may face the body region 20, with the first insulating film 42 sandwiched therebetween.

[0185] 1 , SiC semiconductor device 1 includes gate pad 50 disposed on interlayer insulating film 41. Gate pad 50 is an electrode to which a gate potential is applied from the outside. Gate pad 50 may also be referred to as a "gate pad electrode," a "first pad electrode," or the like. Gate pad 50 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 41 side.

[0186] In this embodiment, the gate pad 50 is disposed on a portion of the interlayer insulating film 41 that covers the active region 8. Specifically, the gate pad 50 is disposed on the active surface 10 at a distance from the outer peripheral surface 11 in a plan view. The gate pad 50 is disposed in a region close to the center of one side of the active surface 10 (the second connection surface 12B in this embodiment) in a plan view.

[0187] Of course, the gate pad 50 may be disposed in a region along any of the central portions of the first to fourth connection surfaces 12A to 12D. Of course, the gate pad 50 may be disposed at any corner of the active surface 10 in a plan view. The gate pad 50 may also be disposed at the central portion of the active surface 10 in a plan view. In this embodiment, the gate pad 50 is formed in a quadrangular shape in a plan view.

[0188] The SiC semiconductor device 1 includes at least one gate wiring 51 (a plurality of gate wirings in this embodiment) extending from the gate pad 50 onto the interlayer insulating film 41. The gate wiring 51 may also be referred to as a "wiring" or "wiring electrode." In this embodiment, the plurality of gate wirings 51 are arranged on the active surface 10 at intervals from the outer peripheral surface 11 in a plan view.

[0189] The plurality of gate wirings 51 may have a laminated structure including a Ti-based metal film and an Al-based metal film laminated in this order from the side of the interlayer insulating film 41. In this embodiment, the plurality of gate wirings 51 include a first gate wiring 51A and a second gate wiring 51B.

[0190] The first gate wiring 51A is drawn out from the gate pad 50 toward the first connection surface 12A, and extends in a line along the periphery of the active surface 10 so as to intersect (specifically, perpendicular to) part of (specifically, one end portion) of the multiple trench structures 25. The first gate wiring 51A penetrates the interlayer insulating film 41 via the multiple contact openings 44, and is electrically connected to one end portion of the multiple trench structures 25.

[0191] The second gate wiring 51B is drawn out from the gate pad 50 toward the third connection surface 12C and extends in a line along the periphery of the active surface 10 so as to intersect (specifically, perpendicular to) part of (specifically, the other end portions) of the multiple trench structures 25. The second gate wiring 51B penetrates the interlayer insulating film 41 via the multiple contact openings 44 and is electrically connected to the other end portions of the multiple trench structures 25.

[0192] The SiC semiconductor device 1 includes a source pad 52 disposed on the interlayer insulating film 41 at a distance from the gate pad 50 and the gate wiring 51. The source pad 52 is an electrode to which a source potential is applied from the outside. The source pad 52 may also be referred to as a "source pad electrode," a "second pad electrode," or the like. The source pad 52 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 41 side.

[0193] In this embodiment, the source pad 52 is disposed on the active surface 10 at a distance from the outer peripheral surface 11 in a plan view. In this embodiment, the source pad 52 is formed in a polygonal shape having a recess that is recessed along the gate pad 50 in a plan view. Of course, the source pad 52 may also be formed in a quadrangular shape in a plan view.

[0194] The source pad 52 penetrates the interlayer insulating film 41 via the contact openings 44, and is electrically connected to the body region 20, the source regions 37, and the contact regions 38. That is, the source pad 52 is electrically connected to the non-inversion columns 35 (impurity regions 15) via the body region 20.

[0195] The SiC semiconductor device 1 includes a drain pad 53 covering the second main surface 4. The drain pad 53 is an electrode to which a drain potential is applied from the outside. The drain pad 53 may also be referred to as a "drain pad electrode," a "third pad electrode," or the like. The drain pad 53 forms an ohmic contact with the base layer 6 exposed from the second main surface 4.

[0196] That is, the drain pad 53 is electrically connected to the multiple inversion columns 30 (intermediate region 36) via the base layer 6. The drain pad 53 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The drain pad 53 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0197] The breakdown voltage that can be applied between source pad 52 and drain pad 53 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to any one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0198] 14 is a schematic diagram showing a wafer 60 used in the manufacture of the SiC semiconductor device 1. The wafer 60 is a substrate of the base layer 6 and includes a SiC single crystal. The wafer 60 is formed in a flat disk shape. Of course, the wafer 60 may also be formed in a flat rectangular parallelepiped shape. The wafer 60 has a first wafer main surface 61 on one side, a second wafer main surface 62 on the other side, and a wafer side surface 63 connecting the first wafer main surface 61 and the second wafer main surface 62.

[0199] The first wafer main surface 61 corresponds to the upper end of the base layer 6, and the second wafer main surface 62 corresponds to the lower end of the base layer 6. The first wafer main surface 61 and the second wafer main surface 62 are formed by the c-plane of the SiC single crystal. The first wafer main surface 61 is formed by the silicon face of the SiC single crystal, and the second wafer main surface 62 is formed by the carbon face of the SiC single crystal. The wafer 60 (the first wafer main surface 61 and the second wafer main surface 62) has the off-direction Do and the off-angle θo described above.

[0200] The wafer 60 has a mark 64 on the wafer side surface 63 that indicates the crystal orientation of the SiC single crystal. The mark 64 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is linearly cut out in a plan view. The orientation notch is a cutout that is concave (e.g., tapered) toward the center of the first wafer main surface 61 in a plan view.

[0201] The mark 64 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The mark 64 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction. Figure 14 shows an orientation flat extending in the m-axis direction (first direction X) in a plan view.

[0202] For example, a plurality of device regions 65 and a plurality of cutting lines 66 are set on the wafer 60 by alignment marks or the like. Each device region 65 corresponds to a SiC semiconductor device 1. Each of the plurality of device regions 65 is set to have a quadrangular shape in a plan view.

[0203] In this embodiment, the multiple device regions 65 are set in a matrix along the first direction X and the second direction Y in a plan view. The multiple device regions 65 are set at intervals inward from the periphery of the first wafer main surface 61 in a plan view. The multiple cutting lines 66 are set in a grid pattern extending along the first direction X and the second direction Y to partition the multiple device regions 65.

[0204] Fig. 15 is a flowchart showing an example of a method for manufacturing the SiC semiconductor device 1. Figs. 16A to 16O are cross-sectional perspective views showing an example of a method for manufacturing the SiC semiconductor device 1. Figs. 17A to 17B are schematic views for explaining a crystal orientation measurement process. Figs. 18A to 18B are schematic views for explaining an ion implantation process. Figs. 16A to 16O show cross-sectional perspective views of a portion of the active region 8 of one device region 65.

[0205] First, referring to Fig. 16A, the aforementioned wafer 60 preparation step is performed (step S1 in Fig. 15). Next, referring to Fig. 16B, the semiconductor layer 7 formation step is performed (step S2 in Fig. 15). The semiconductor layer 7 is formed by epitaxial growth starting from the first wafer main surface 61 (wafer 60).

[0206] Next, a step of measuring the crystal orientation of the semiconductor layer 7 is performed (step S3 in FIG. 15). The crystal orientation of the semiconductor layer 7 includes a step of measuring the off angle θo of the semiconductor layer 7. That is, this step includes a step of measuring the crystal orientation of the second axial channel C2 of the semiconductor layer 7.

[0207] The wafer 60 is cut from an ingot (SiC ingot), which is a crystalline mass, and there is a risk that an error will occur in the off-angle θo due to a process error. If an error occurs in the off-angle θo of the wafer 60, a process error will also occur in the off-angle θo of the semiconductor layer 7, which will become an obstacle during the channeling implantation process. Therefore, it is preferable that data (information) on the off-angle θo is obtained prior to the channeling implantation process, and the channeling implantation process be performed based on the data (information) on the off-angle θo.

[0208] 17A , in this step, the crystal orientation of the semiconductor layer 7 is measured by an X-ray diffraction method (so-called ω-2θ measurement method) using an X-ray diffraction device 67. The X-ray diffraction device 67 may also be referred to as an "XRD (X-ray Diffraction) device."

[0209] The X-ray diffraction apparatus 67 includes an irradiation unit 68 and a detection unit 69 and performs rocking curve measurement. The irradiation unit 68 irradiates the upper end of the semiconductor layer 7 (first wafer main surface 61 of the wafer 60) with incident X-rays L1 at a predetermined incident angle ω. The incident angle ω is defined as the angle between the incident X-rays L1 and the upper end of the semiconductor layer 7 (first wafer main surface 61 of the wafer 60).

[0210] The detector 69 is disposed at an angular position of a diffraction angle 2θ (θ is the Bragg angle) with respect to the irradiation position of the incident X-rays L1 on the wafer 60, and detects the diffracted X-rays L2. The diffraction angle 2θ is the angle between the incident direction of the incident X-rays L1 and the diffraction direction of the diffracted X-rays L2.

[0211] In the rocking curve measurement method, the incident angle ω is varied within a small angular range while the diffraction angle 2θ is fixed, and a rocking curve representing the intensity of the diffracted X-rays L2 (the intensity profile of the diffracted X-rays L2) is measured. The rocking curve has the intensity of the diffracted X-rays L2 on the vertical axis and the incident angle ω on the horizontal axis. The incident angle ω is determined as the angular position at which the intensity of the diffracted X-rays L2 takes a peak value.

[0212] In this step, the rocking curve measurement method is performed on only one location (for example, the central portion) of the upper end (first wafer main surface 61 of the wafer 60) of the semiconductor layer 7. If in-plane variation in the off angle θo is expected, the rocking curve measurement method may be performed on multiple locations (for example, the central portion and peripheral portion) of the upper end (first wafer main surface 61 of the wafer 60) of the semiconductor layer 7.

[0213] 17B shows measurement points when rocking curve measurement is performed on multiple points (five points in this example) on the upper end of the semiconductor layer 7. The off angle θo of the semiconductor layer 7 is set to approximately 4° in this example. First to fifth measurement points Po1 to Po5 are shown in FIG.

[0214] The first measurement point Po1 is set in the center of the semiconductor layer 7. The second measurement point Po2 is set in the peripheral portion of the semiconductor layer 7 at a distance from the first measurement point Po1 on one side in the second direction Y (the opposite side from the mark 64). The third measurement point Po3 is set in the peripheral portion of the semiconductor layer 7 at a distance from the first measurement point Po1 on one side in the first direction X (to the right of the mark 64).

[0215] The fourth measurement point Po4 is set on the periphery of the semiconductor layer 7 at a distance from the first measurement point Po1 on the other side in the second direction Y (toward the mark 64). The fifth measurement point Po5 is set on the periphery of the semiconductor layer 7 at a distance from the first measurement point Po1 on the other side in the first direction X (to the left of the mark 64).

[0216] The measurement results of the incident angle ω, diffraction angle 2θ, and off-angle θo at the first to fifth measurement points Po1 to Po5 are shown in Table 1. The off-angle θo can be calculated using the incident angle ω and diffraction angle 2θ by the formula "ω - (2θ × 1 / 2)".

[0217] As shown in Table 1, the average value of the off angle θo at the first to fifth measurement points Po1 to Po5 was 4.036°, and the standard deviation of these off angles θo was 0.009° (±0.01°). From this, it can be understood that the in-plane variation of the off angle θo occurring at the upper end of the semiconductor layer 7 (first wafer main surface 61 of wafer 60) is extremely small and does not interfere with the channeling implantation process.

[0218] Therefore, it is understood that there is no problem with measuring at least one location on the upper end (first wafer main surface 61) of the semiconductor layer 7. For example, the measurement location may be any one or more (all) of the first to fifth measurement points Po1 to Po5. For example, the measurement location may be only the first measurement point Po1. Reducing the number of measurement locations (number of measurements) reduces the number of manufacturing steps (manufacturing costs).

[0219] Of course, the off angle θo may be measured at multiple locations on the upper end (first wafer main surface 61) of the semiconductor layer 7, and an implantation angle may be set in the channeling implantation step according to the in-plane variation of the off angle θo. In this case, although the number of manufacturing steps (manufacturing costs) increases, the in-plane error of the impurity regions 15 and the multiple inversion columns 30 formed in the semiconductor layer 7 is appropriately suppressed.

[0220] The off-angle θo of the semiconductor layer 7 is substantially the same as the off-angle θo of the wafer 60. Therefore, the crystal orientation measurement step may be performed on the wafer 60 prior to the step of forming the semiconductor layer 7. However, from the viewpoint of ensuring accuracy, it is preferable that the crystal orientation measurement step be performed on the semiconductor layer 7.

[0221] 16C , the step of forming impurity region 15 is performed (Step S4 in FIG. 15 ). The step of forming impurity region 15 includes a channeling injection step of a trivalent element (p-type impurity) into semiconductor layer 7. In this step, the trivalent element is introduced into the entire semiconductor layer 7 via a mask (not shown) having a predetermined layout.

[0222] A mask (not shown) is placed on the upper end of the semiconductor layer 7, exposing a region in the active region where the impurity region 15 is to be formed and covering the remaining region. Of course, if the trivalent element is introduced into the entire semiconductor layer 7, the mask (not shown) may be omitted. The semiconductor layer 7 (wafer 60) has an off angle θo inclined at a predetermined angle in a predetermined off direction Do with respect to the first wafer main surface 61. The channeling implantation step is performed based on data (information) of the off angle θo.

[0223] 18A , in the random implantation method, a trivalent element is introduced into the semiconductor layer 7 with a predetermined implantation energy in a direction intersecting the second axial channel C2 (off angle θo) (see also FIG. 9 ). For example, in the random implantation method, the trivalent element is implanted along a vertical direction Z perpendicular to the upper end (first wafer main surface 61) of the semiconductor layer 7.

[0224] In the case of the random implantation, the trivalent element is introduced along a direction in which atomic rows are relatively dense in a plan view, and therefore the trivalent element collides with the atomic rows at a relatively shallow depth position. Therefore, the atomic rows hinder the introduction of the trivalent element into a relatively deep depth position of the semiconductor layer 7. As a result, the impurity region 15 without the first relaxed portion 18 is formed.

[0225] 18B , in the channeling implantation method, the implantation angle of the trivalent element with respect to the semiconductor layer 7 is controlled, and the trivalent element is introduced into the semiconductor layer 7 along the second axial channel C2 (in this embodiment, the c-axis of the SiC single crystal) with a predetermined implantation energy (see also FIG. 8 ). In this case, either or both of the implantation angle of the trivalent element with respect to the semiconductor layer 7 and the tilt angle of the semiconductor layer 7 with respect to the implantation angle of the trivalent element are adjusted.

[0226] For example, the wafer 60 may be supported horizontally, and the trivalent element may be introduced along the second axial channel C2 into the semiconductor layer 7. Of course, the wafer 60 may be supported in a state tilted by an off angle θo from the horizontal, and the trivalent element may be introduced along the second axial channel C2 into the semiconductor layer 7. By selecting any combination of the implantation energy of the trivalent element and the implantation temperature of the trivalent element (the temperature of the wafer 60), the impurity region 15 having a predetermined thickness is formed at a predetermined depth.

[0227] The implantation energy of the trivalent element may be 100 KeV to 2000 KeV, or may have a value belonging to any one of the ranges of 100 KeV to 250 KeV, 250 KeV to 500 KeV, 500 KeV to 750 KeV, 750 KeV to 1000 KeV, 1000 KeV to 1250 KeV, 1250 KeV to 1500 KeV, 1500 KeV to 1750 KeV, and 1750 KeV to 2000 KeV.

[0228] The implantation temperature of the trivalent element may be adjusted in the range of 0° C. to 1500° C. The implantation temperature may have a value belonging to any one of the ranges of 0° C. to 25° C., 25° C. to 50° C., 50° C. to 100° C., 100° C. to 250° C., 250° C. to 500° C., 500° C. to 750° C., 750° C. to 1000° C., 1000° C. to 1250° C., and 1250° C. to 1500° C.

[0229] The implantation angle of the trivalent element is preferably set within a range of ±2° with respect to the axis along the second axial channel C2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°). The implantation angle of the trivalent element is particularly preferably set within a range of ±1° with respect to the axis along the second axial channel C2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°).

[0230] In the case of the channeling implantation method, the trivalent element is introduced along the second axial channel C2 in which the atomic rows are relatively sparse in a plan view. The trivalent element travels through the second axial channel C2 while repeatedly undergoing small-angle scattering due to the channeling effect, and reaches a relatively deep position in the semiconductor layer 7. In other words, in the case of the channeling implantation method, the probability of the trivalent element colliding with the atomic rows of the SiC single crystal is reduced.

[0231] In this case, it is preferable that a trivalent element that is heavier than carbon is introduced into the semiconductor layer 7. That is, it is preferable that the trivalent element is a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the trivalent element is aluminum.

[0232] After the step of implanting the trivalent element, an annealing method may be performed to electrically activate the trivalent element and simultaneously repair lattice defects and the like that have occurred in the semiconductor layer 7. The annealing temperature for the semiconductor layer 7 may be 500° C. or higher and 2000° C. or lower.

[0233] 16D , the body region 20 is formed (step S5 in FIG. 15 ). The body region 20 formation process includes a random implantation process of a trivalent element (p-type impurity) into the surface portion of the semiconductor layer 7. In this process, the trivalent element is introduced into the entire semiconductor layer 7. For example, in the random implantation method, the trivalent element is implanted along the vertical direction Z perpendicular to the upper end (first wafer main surface 61) of the semiconductor layer 7. As a result, the body region 20 is formed throughout the entire surface portion of the semiconductor layer 7.

[0234] 16E, a step of forming a plurality of source regions 37 is performed (step S6 in FIG. 15). The plurality of source regions 37 are formed by introducing a pentavalent element into the surface layer portion of the semiconductor layer 7 by a random implantation method using a mask (not shown) having a predetermined layout.

[0235] Furthermore, a step of forming a plurality of contact regions 38 is performed (step S7 in FIG. 15 ). The plurality of contact regions 38 are formed by introducing a trivalent element into the surface layer portion of the semiconductor layer 7 by random implantation through a mask (not shown) having a predetermined layout. The step of forming the contact regions 38 may be performed prior to the step of forming the source region 37.

[0236] 16F, a step of forming a first mask 71 having a predetermined pattern is performed (step S8 in FIG. 15). The first mask 71 is preferably an inorganic mask (hard mask). The first mask 71 is disposed on the upper end of the semiconductor layer 7 and has a plurality of first openings 71a that expose regions where the plurality of trenches 26 are to be formed.

[0237] The multiple first openings 71a are formed at intervals in the first direction X and are each partitioned into bands extending in the second direction Y. That is, the multiple first openings 71a have an extension direction that extends along the off direction Do in a plan view. The first mask 71 also has first openings 71a (not shown) that expose the region where the outer peripheral surface 11 is to be formed. The first openings 71a for the outer peripheral surface 11 are formed in a grid pattern along the multiple lines 66 to cut.

[0238] Next, a step of forming a plurality of trenches 26 is performed (step S9 in FIG. 15 ). In the step of forming the trenches 26, unnecessary portions of the semiconductor layer 7 are removed by etching using a first mask 71. The etching may be either or both of wet etching and dry etching.

[0239] The etching method is preferably RIE (Reactive Ion Etching), which forms a plurality of trenches 26 at the upper end of the semiconductor layer 7. Also, the active surface 10, the outer peripheral surface 11, and the first to fourth connection surfaces 12A to 12D are formed at the upper end of the semiconductor layer 7. After the step of forming the plurality of trenches 26, the first mask 71 is removed.

[0240] Next, referring to FIG. 16G , a step of forming a second mask 72 having a predetermined pattern is performed (step S10 in FIG. 15 ). The second mask 72 is preferably an organic mask (resist mask). The second mask 72 is disposed on the upper end of the semiconductor layer 7 and has a plurality of second openings 72 a that expose the plurality of trenches 26 in a one-to-one correspondence. The second openings 72 a are formed at intervals in the first direction X and are each partitioned into strips extending in the second direction Y. In other words, the second openings 72 a have an extension direction that extends along the off-direction Do in a plan view.

[0241] Next, a step of forming a plurality of inversion columns 30 is performed (step S11 in FIG. 15 ). The step of forming the plurality of inversion columns 30 includes a channeling implantation step of a pentavalent element (n-type impurity) into the semiconductor layer 7. The pentavalent element is introduced into the lower region 7 a of the semiconductor layer 7 through the plurality of second openings 72 a of the second mask 72 and the bottom walls of the plurality of trenches 26. The channeling implantation step is performed based on the data (information) of the off-angle θo described above.

[0242] In the channeling implantation method, the implantation angle of the pentavalent element with respect to the semiconductor layer 7 is controlled, and the pentavalent element is introduced into the semiconductor layer 7 with a predetermined implantation energy along the second axial channel C2 (in this embodiment, the c-axis of the SiC single crystal). In this case, either or both of the implantation angle of the pentavalent element with respect to the semiconductor layer 7 and the tilt angle of the semiconductor layer 7 with respect to the implantation angle of the pentavalent element are adjusted.

[0243] For example, the wafer 60 may be supported horizontally, and the pentavalent element may be introduced along the second axial channel C2 into the semiconductor layer 7. Of course, the wafer 60 may be supported in a state inclined by an off angle θo from the horizontal, and the pentavalent element may be introduced along the second axial channel C2 into the semiconductor layer 7. By selecting any combination of the implantation energy and the implantation temperature of the pentavalent element, a plurality of inversion columns 30 having a predetermined thickness are formed at a predetermined depth.

[0244] The implantation energy of the pentavalent element may be 100 KeV to 2000 KeV, or may have a value belonging to any one of the ranges of 100 KeV to 250 KeV, 250 KeV to 500 KeV, 500 KeV to 750 KeV, 750 KeV to 1000 KeV, 1000 KeV to 1250 KeV, 1250 KeV to 1500 KeV, 1500 KeV to 1750 KeV, and 1750 KeV to 2000 KeV.

[0245] The implantation energy for the inversion columns 30 may be approximately equal to or different from the implantation energy for the impurity regions 15. The implantation energy for the inversion columns 30 may be equal to or greater than the implantation energy for the impurity regions 15. The implantation energy for the inversion columns 30 may be less than the implantation energy for the impurity regions 15.

[0246] The implantation temperature of the pentavalent element may be adjusted in the range of 0° C. to 1500° C. The implantation temperature may have a value belonging to any one of the ranges of 0° C. to 25° C., 25° C. to 50° C., 50° C. to 100° C., 100° C. to 250° C., 250° C. to 500° C., 500° C. to 750° C., 750° C. to 1000° C., 1000° C. to 1250° C., and 1250° C. to 1500° C.

[0247] The implantation temperature for the inversion column 30 may be approximately equal to or different from the implantation temperature for the impurity region 15. The implantation temperature for the inversion column 30 may be equal to or higher than the implantation temperature for the impurity region 15. The implantation temperature for the inversion column 30 may be lower than the implantation temperature for the impurity region 15.

[0248] The implantation angle of the pentavalent element is preferably set within a range of ±2° with respect to the axis along the second axial channel C2 (the c-axis of the SiC single crystal in this embodiment) as the reference (0°). The implantation angle of the pentavalent element is particularly preferably set within a range of ±1° with respect to the axis along the second axial channel C2 (the c-axis of the SiC single crystal in this embodiment) as the reference (0°).

[0249] In the case of channeling implantation, the pentavalent element is introduced along the second axial channel C2, in which the atomic rows are relatively sparse in plan view. The pentavalent element travels through the second axial channel C2 while repeatedly undergoing small-angle scattering due to the channeling effect, and reaches a relatively deep position in the semiconductor layer 7. In other words, in the case of channeling implantation, the probability of the pentavalent element colliding with the atomic rows of the SiC single crystal is reduced. The pentavalent element is preferably arsenic or antimony.

[0250] The second openings 72 a have an extension direction that extends along the off-direction Do, and the implantation angle of the pentavalent element is inclined with respect to the off-direction Do. Therefore, the pentavalent element is introduced into the semiconductor layer 7 through the second openings 72 a substantially perpendicular to the bottom wall of the trench 26 in a cross-sectional view orthogonal to the extension direction.

[0251] This prevents the formation of the multiple inversion columns 30 in an inclined position in the semiconductor layer 7. Furthermore, the wall surfaces of the multiple second openings 72a are prevented from blocking the incident path of the pentavalent element. This prevents process errors of the multiple inversion columns 30 caused by shadowing of the wall surfaces of the multiple second openings 72a. Therefore, the accuracy of charge balance is improved.

[0252] After the step of implanting the pentavalent element, an annealing method may be performed to electrically activate the pentavalent element and simultaneously repair lattice defects and the like that have occurred in the semiconductor layer 7. The annealing temperature for the semiconductor layer 7 may be 500° C. or higher and 2000° C. or lower. This results in the formation of a plurality of inversion columns 30 and a plurality of non-inversion columns 35, and also the formation of a superjunction structure.

[0253] The annealing method for the inversion columns 30 may also serve as the annealing method for the impurity regions 15. In this case, the annealing method for the impurity regions 15 before the step of forming the inversion columns 30 may be omitted. Referring to Figure 16H, after the step of forming the plurality of inversion columns 30, the second mask 72 is removed.

[0254] Next, referring to FIG. 16I, a step of forming a third mask 73 having a predetermined pattern is performed (step S12 in FIG. 15). The third mask 73 is preferably an organic mask (resist mask). The third mask 73 is disposed on the upper end of the semiconductor layer 7 and has a plurality of third openings 73a that selectively expose the plurality of trenches 26. The plurality of third openings 73a are spaced apart in the first direction X and the second direction Y, and each exposes a portion of the plurality of trenches 26.

[0255] Next, a step of forming a plurality of intermediate regions 36 is performed (step S13 in FIG. 15 ). The step of forming the plurality of intermediate regions 36 includes a step of introducing a pentavalent element into the semiconductor layer 7 at a predetermined implantation energy in a direction intersecting the second axial channel C2 (off angle θo) by a random implantation method via a third mask 73. The pentavalent element is introduced into the semiconductor layer 7 (impurity regions 15) from the plurality of third openings 73 a through the wall surfaces (side walls and bottom walls) of the plurality of trenches 26. The pentavalent element may be introduced into the semiconductor layer 7 once or multiple times.

[0256] When the pentavalent element is introduced multiple times, the pentavalent element may be introduced in multiple stages at different depth positions in the semiconductor layer 7 using multiple implantation energies. The pentavalent element may be introduced into the semiconductor layer 7 (impurity regions 15) through the wall surfaces (side walls and bottom walls) of the multiple trenches 26 by oblique ion implantation. Referring to FIG. 16J , after the step of forming the multiple intermediate regions 36, the third mask 73 is removed.

[0257] Although not specifically shown in the drawings, a step of forming well region 39 is performed prior to or after the step of forming intermediate region 36. Well region 39 is formed by introducing a trivalent element into semiconductor layer 7 by random implantation using a mask (not shown) that selectively exposes outer circumferential surface 11 and first to fourth connecting surfaces 12A to 12D.

[0258] Although not specifically shown in the drawings, a step of forming a plurality of field regions 40 is carried out prior to or after the step of forming intermediate region 36. The plurality of field regions 40 are formed by introducing a trivalent element into the surface portion of semiconductor layer 7 by random implantation using a mask (not shown) that selectively exposes outer circumferential surface 11.

[0259] Next, referring to FIG. 16K , the step of forming the insulating film 27 is performed (step S14 in FIG. 15 ). The step of forming the insulating film 27 also serves as the step of forming the first insulating film 42. The insulating film 27 may be formed by either or both of a CVD (Chemical Vapor Deposition) method and an oxidation treatment method. The insulating film 27 and the first insulating film 42 are typically formed by a thermal oxidation treatment method. The insulating film 27 is formed in a film shape on the wall surfaces of the plurality of trenches 26, and the first insulating film 42 is formed in a film shape in a region of the upper end of the semiconductor layer 7 outside the plurality of trenches 26.

[0260] Next, referring to FIG. 16L, a step of forming a buried electrode 28 is performed (step S15 in FIG. 15). This step includes a step of forming a base electrode film 74 on the insulating film 27. In this embodiment, the base electrode film 74 includes conductive polysilicon. The base electrode film 74 backfills the plurality of trenches 26 and covers the upper end of the semiconductor layer 7. The base electrode film 74 may be formed by a CVD method.

[0261] 16M, unnecessary portions of the buried electrode 28 are removed by etching until the insulating film 27 is exposed. The etching method may be either a wet etching method or a dry etching method, or both. As a result, the buried electrodes 28 are buried in the trenches 26, respectively, and a plurality of trench structures 25 are formed.

[0262] 16N, a step of forming interlayer insulating film 41 (second insulating film 43) is performed (step S16 in FIG. 15). Interlayer insulating film 41 may be formed by a CVD method. A plurality of contact openings 44 having a predetermined layout are formed in interlayer insulating film 41 by an etching method using a mask (not shown) having a predetermined layout.

[0263] 16O, a step of forming gate pad 50, gate wiring 51, and source pad 52 is performed (step S17 in FIG. 15). Gate pad 50, gate wiring 51, and source pad 52 are formed by depositing a metal film on interlayer insulating film 41 by sputtering, and then shaping the metal film into a predetermined layout by etching using a mask (not shown) having a predetermined layout.

[0264] Next, a step of forming drain pad 53 is performed (step S18 in FIG. 15 ). Drain pad 53 is formed by depositing a metal film on second wafer main surface 62 by sputtering. Thereafter, wafer 60 is cut along a plurality of cutting lines 66 (step S19 in FIG. 15 ). Through the steps including those described above, a plurality of SiC semiconductor devices 1 are manufactured from one wafer 60.

[0265] Other embodiments of the trench structure 25 are shown below. Fig. 19 is a cross-sectional perspective view showing the trench structure 25 according to a second embodiment. Referring to Fig. 19, the plurality of trench structures 25 according to the second embodiment each have a configuration that contributes to narrowing the pitch. The plurality of trench structures 25 according to the second embodiment are particularly effective in realizing a narrow pitch between the plurality of inversion columns 30.

[0266] Each of the multiple trench structures 25 includes a trench 26, an insulating film 27, a buried electrode 28, and a buried insulator 80. The trench 26 has the same configuration as in the first embodiment. In this configuration, the insulating film 27 is formed at a distance from the first main surface 3 (active surface 10) toward the bottom wall of the trench 26, exposing a surface portion of the first main surface 3 (active surface 10) at the opening end of the trench 26. The upper end of the insulating film 27 is preferably located closer to the first main surface 3 than the intermediate portion of the depth range of the trench 26.

[0267] In this embodiment, the buried electrode 28 is buried in the trench 26 at a distance from the first main surface 3 (active surface 10) toward the bottom wall of the trench 26, and defines an open recess that is recessed toward the bottom wall of the trench 26 at the open end of the trench 26. The buried electrode 28 exposes a surface portion of the first main surface 3 (active surface 10) and an upper end of the insulating film 27 at the open end of the trench 26. The upper end of the buried electrode 28 is preferably located on the first main surface 3 side relative to the intermediate depth range of the trench 26.

[0268] The buried insulator 80 is buried in the trench 26 (open recess) so as to expose the first main surface 3 (active surface 10), and covers the insulating film 27 and the buried electrode 28 within the trench 26. The buried insulator 80 is buried in the trench 26 at a distance from the first main surface 3 (active surface 10) toward the buried electrode 28, and exposes a surface portion of the first main surface 3 (active surface 10) at the open end of the trench 26.

[0269] The upper end of the buried insulator 80 is preferably located closer to the first main surface 3 than the intermediate depth of the trench 26. The buried insulator 80 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The buried insulator 80 preferably includes a silicon oxide film.

[0270] In this embodiment, the aforementioned plurality of source regions 37 are respectively formed in regions between the plurality of adjacent trench structures 25 in the surface layer portion of the first main surface 3 (active surface 10). The plurality of source regions 37 are arranged at intervals along the plurality of trench structures 25 so as to be connected to the plurality of trench structures 25 located on both sides.

[0271] Specifically, the plurality of source regions 37 arranged along one sidewall of the trench structure 25 face in one-to-one correspondence with the plurality of source regions 37 arranged along the other sidewall of the trench structure 25. In other words, the plurality of source regions 37 are arranged in a matrix in plan view.

[0272] Of course, the plurality of source regions 37 on one side may face the regions between the plurality of source regions 37 on the other side in a one-to-one correspondence. That is, the plurality of source regions 37 may be arranged in a staggered pattern in a plan view. The plurality of source regions 37 have portions exposed from the sidewall of the trench 26 at the opening end of the trench 26, and face the buried electrode 28 and the buried insulator 80 with the insulating film 27 interposed therebetween.

[0273] In this embodiment, the aforementioned plurality of contact regions 38 are formed in regions between adjacent trench structures 25 in the surface layer portion of the first main surface 3 (active surface 10). The plurality of contact regions 38 are arranged at intervals along the plurality of trench structures 25 so as to be connected to the plurality of trench structures 25 located on both sides.

[0274] Specifically, the contact regions 38 are arranged alternately with the source regions 37 along the trench structures 25. More specifically, the contact regions 38 arranged along one sidewall of the trench structure 25 face, in a one-to-one correspondence, the contact regions 38 arranged along the other sidewall of the trench structure 25. The contact regions 38 are also arranged in a matrix in plan view.

[0275] Of course, the multiple contact regions 38 on one side may face the regions between the multiple source regions 37 on the other side (i.e., the multiple source regions 37) in a one-to-one correspondence. That is, the multiple contact regions 38 may be arranged in a staggered pattern in a plan view. The multiple contact regions 38 have portions exposed from the sidewall of the trench 26 at the opening end of the trench 26, and face the buried electrode 28 and the buried insulator 80 with the insulating film 27 interposed therebetween.

[0276] Although not specifically shown in the drawings, the interlayer insulating film 41 has a layered structure including a first insulating film 42 and a second insulating film 43. As in the first embodiment, the first insulating film 42 selectively covers the active surface 10, the outer peripheral surface 11, and the first to fourth connecting surfaces 12A to 12D.

[0277] In this embodiment, the first insulating film 42 covers the peripheral edge of the active surface 10 and exposes the plurality of trench structures 25 collectively in the inner portion of the active surface 10. Specifically, the first insulating film 42 is connected to the insulating film 27 at both ends of the plurality of trench structures 25, exposing the buried electrodes 28. The first insulating film 42 also covers the outer peripheral surface 11 and the first to fourth connecting surfaces 12A to 12D in the same manner as in the first embodiment.

[0278] As in the first embodiment, the second insulating film 43 selectively covers the active surface 10, the outer peripheral surface 11, and the first to fourth connecting surfaces 12A to 12D, sandwiching the first insulating film 42. In this embodiment, the second insulating film 43 covers the peripheral portion of the active surface 10 and exposes the plurality of trench structures 25 collectively in the inner portion of the active surface 10. Specifically, the second insulating film 43 extends from above the first main surface 3 (active surface 10) into the trenches 26 at both ends of the plurality of trench structures 25 and is connected to the buried insulator 80 in the trenches 26.

[0279] In this form, the interlayer insulating film 41 includes a plurality of contact openings 44 (not shown) that expose both ends (buried electrodes 28) of the plurality of trench structures 25, and a single contact opening 44 that collectively exposes the inner portions (buried insulators 80) of the plurality of trench structures 25, the plurality of source regions 37, and the plurality of contact regions 38.

[0280] The gate pad 50, the gate wirings 51, and the drain pad 53 have the same configurations as those in the first embodiment. The source pad 52 extends from above the interlayer insulating film 41 into the single contact opening 44, and collectively covers the inner portions (buried insulator 80) of the trench structures 25, the source regions 37, and the contact regions 38 within the single contact opening 44.

[0281] The source pad 52 is electrically insulated from the plurality of trench structures 25 (buried electrodes 28) by the buried insulator 80, and is electrically connected to the plurality of source regions 37 and the plurality of contact regions 38 on the first main surface 3 (active surface 10). In this embodiment, the source pad 52 is also electrically connected to exposed portions of the plurality of intermediate regions 36 on the first main surface 3.

[0282] The source pad 52 has a buried portion buried in the trench 26. The buried portion of the source pad 52 faces the buried electrode 28 within the trench 26 with the buried insulator 80 sandwiched therebetween, and is electrically connected to the plurality of source regions 37 and the plurality of contact regions 38 at the open end of the trench 26.

[0283] Fig. 20 is a cross-sectional perspective view showing a trench structure 25 according to the third embodiment. Referring to Fig. 20, the plurality of trench structures 25 according to the third embodiment each have a configuration obtained by modifying the plurality of trench structures 25 according to the second embodiment.

[0284] Each of the plurality of trench structures 25 includes a trench 26, an insulating film 27, a buried electrode 28, and a buried insulator 80. The trench 26 has the same configuration as in the first embodiment. In this configuration, the insulating film 27 includes an upper insulating film 81 and a lower insulating film 82.

[0285] The upper insulating film 81 is formed as the insulating film 27 for controlling the channel Ch, and covers the wall surface of the trench 26 on the opening side relative to the bottom of the body region 20. The upper insulating film 81 has a portion that crosses the bottom of the body region 20 and covers the impurity region 15 (non-inversion column 35). In this case, the coverage area of ​​the upper insulating film 81 with respect to the body region 20 is preferably larger than the coverage area of ​​the upper insulating film 81 with respect to the impurity region 15 (non-inversion column 35).

[0286] The upper insulating film 81 may include a silicon oxide film. The upper insulating film 81 preferably includes a silicon oxide film made of an oxide of the chip 2. The upper insulating film 81 may have a thickness of 1 nm or more and 100 nm or less. The thickness of the upper insulating film 81 may have a value belonging to any one of the ranges of 1 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0287] The lower insulating film 82 covers the wall surface of the trench 26 on the bottom wall side relative to the bottom of the body region 20. The lower insulating film 82 covers the impurity region 15 (non-inversion column 35). The coverage area of ​​the lower insulating film 82 relative to the impurity region 15 (non-inversion column 35) is larger than the coverage area of ​​the body region 20 by the upper insulating film 81.

[0288] The lower insulating film 82 may include a silicon oxide film. The lower insulating film 82 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method. The lower insulating film 82 has a thickness greater than that of the upper insulating film 81. The thickness of the lower insulating film 82 is preferably 10 to 50 times the thickness of the upper insulating film 81.

[0289] The lower insulating film 82 may have a thickness of 100 nm to 500 nm. The thickness of the lower insulating film 82 may have a value belonging to any one of the ranges of 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, and 450 nm to 500 nm.

[0290] In this embodiment, the buried electrode 28 has a multi-electrode structure (double electrode structure) including an upper electrode 83, a lower electrode 84, and an intermediate insulating film 85. The upper electrode 83 is buried on the opening side of the trench 26 with an insulating film 27 interposed therebetween. Specifically, the upper electrode 83 is buried on the opening side of the trench 26 with an upper insulating film 81 interposed therebetween, and faces the body region 20 with the upper insulating film 81 interposed therebetween.

[0291] The area of ​​the upper electrode 83 facing the body region 20 is larger than the area of ​​the upper electrode 83 facing the impurity region 15 (non-inversion column 35). In this embodiment, the upper electrode 83 is embedded in the trench 26 at a distance from the first main surface 3 (active surface 10) toward the bottom wall of the trench 26, and defines an open recess that is recessed toward the bottom wall of the trench 26 at the opening end of the trench 26. The upper electrode 83 exposes a surface portion of the first main surface 3 (active surface 10) and an upper end of the upper insulating film 81 at the opening end of the trench 26.

[0292] A gate potential as a control potential is applied to the upper electrode 83. In response to the gate potential, the upper electrode 83 controls the inversion and non-inversion of a channel Ch (current path) in the body region 20. The upper electrode 83 may include p-type or n-type conductive polysilicon.

[0293] The lower electrode 84 is embedded in the bottom wall side of the trench 26 with the insulating film 27 interposed therebetween. Specifically, the lower electrode 84 is embedded in the bottom wall side of the trench 26 with the lower insulating film 82 interposed therebetween, and faces the impurity region 15 (non-inversion column 35) with the lower insulating film 82 interposed therebetween. In other words, the lower electrode 84 is embedded in the bottom wall side of the trench 26 with respect to the bottom of the body region 20. Although not specifically shown in the drawings, the lower electrode 84 is drawn out to the opening side of the trench 26 in part of the trench 26 (both ends in this embodiment).

[0294] The area of ​​the lower electrode 84 facing the impurity region 15 (non-inversion column 35) is larger than the area of ​​the upper electrode 83 facing the body region 20. The lower electrode 84 extends in a wall shape along the depth direction of the trench 26. The lower electrode 84 has an upper end that protrudes from the lower insulating film 82 toward the upper electrode 83 and is engaged with the lower end of the upper electrode 83. The upper end of the lower electrode 84 faces the upper insulating film 81 (body region 20) across the lower end of the upper electrode 83 in the horizontal direction.

[0295] A gate potential or a source potential may be applied to the lower electrode 84. When a gate potential is applied to the lower electrode 84, the lower electrode 84 has the same potential as the upper electrode 83. Therefore, the voltage drop between the upper electrode 83 and the lower electrode 84 is suppressed. This suppresses electric field concentration in the trench structure 25.

[0296] On the other hand, when a source potential is applied to the lower electrode 84, the lower electrode 84 can function as a field electrode. Therefore, the parasitic capacitance between the lower electrode 84 (field electrode) and the impurity region 15 (non-inverted column 35) is reduced. This suppresses a decrease in switching speed due to the parasitic capacitance. The lower electrode 84 may include p-type or n-type conductive polysilicon.

[0297] The intermediate insulating film 85 is interposed between the upper electrode 83 and the lower electrode 84, and electrically insulates the upper electrode 83 and the lower electrode 84 within the trench 26. The intermediate insulating film 85 is continuous with the upper insulating film 81 and the lower insulating film 82. The intermediate insulating film 85 has a thickness smaller than that of the lower insulating film 82. The thickness of the intermediate insulating film 85 is preferably greater than that of the upper insulating film 81. The intermediate insulating film 85 may include a silicon oxide film. The intermediate insulating film 85 preferably includes a silicon oxide film made of an oxide of the lower electrode 84.

[0298] The buried insulator 80 is buried in the trench 26 (open recess) so as to expose the first main surface 3 (active surface 10), and covers the upper insulating film 81 and the upper electrode 83 within the recess. The buried insulator 80 is buried in the trench 26 at a distance from the first main surface 3 (active surface 10) toward the upper electrode 83, and exposes a surface portion of the first main surface 3 (active surface 10) at the open end of the trench 26.

[0299] The inversion columns 30 and the intermediate regions 36 are formed in the same manner as in the previous embodiment. In this embodiment, each intermediate region 36 faces the lower electrode 84 across the lower insulating film 82 at the portion along the bottom wall of the trench 26, and faces the lower electrode 84 across the lower insulating film 82 at the portion along the sidewall of the trench 26.

[0300] The portion of each intermediate region 36 along the sidewall of the trench 26 is formed at an interval from the bottom of the body region 20 toward the bottom wall of the trench structure 25, and faces the body region 20 across a part of the impurity region 15. Of course, each intermediate region 36 may be connected to the body region 20. In this case, each intermediate region 36 may face the upper electrode 83 with the upper insulating film 81 interposed therebetween.

[0301] In this embodiment, the plurality of source regions 37 have portions exposed from the sidewall of the trench 26 at the opening end of the trench 26, and face the upper electrode 83 and the buried insulator 80 across the upper insulating film 81. In this embodiment, the plurality of contact regions 38 have portions exposed from the sidewall of the trench 26 at the opening end of the trench 26, and face the upper electrode 83 and the buried insulator 80 across the upper insulating film 81.

[0302] In this embodiment, the aforementioned plurality of gate wirings 51 penetrate the interlayer insulating film 41 via the plurality of contact openings 44 and are electrically connected to the plurality of upper electrodes 83. When a gate potential is applied to the lower electrode 84, the plurality of gate wirings 51 penetrate the interlayer insulating film 41 via the plurality of contact openings 44 and are electrically connected to the plurality of upper electrodes 83 and the plurality of lower electrodes 84.

[0303] When a source potential is applied to the lower electrode 84, the source pad 52 is electrically connected to the plurality of lower electrodes 84. In this case, the SiC semiconductor device 1 may include a source wiring extending from the source pad 52 onto the interlayer insulating film 41. In this case, the source wiring is formed in a line shape extending along the periphery of the active surface 10 so as to intersect (specifically, orthogonally intersect) with a portion (one end or both ends) of the plurality of trench structures 25 in a region outside the plurality of gate wirings 51. The source wiring penetrates the interlayer insulating film 41 via the plurality of contact openings 44 and is electrically connected to the plurality of lower electrodes 84.

[0304] 21 is a cross-sectional perspective view showing a trench structure 25 according to a fourth embodiment. The plurality of trench structures 25 according to the first embodiment are arranged at intervals in the first direction X (m-axis direction) and each formed in a strip shape extending in the second direction Y (a-axis direction). However, the plurality of trench structures 25 may each be formed in a strip shape extending in the first direction X (m-axis direction) and arranged at intervals in the second direction Y (a-axis direction).

[0305] The multiple inversion columns 30 are each formed in a strip shape extending in the first direction X (m-axis direction) according to the layout of the multiple trench structures 25, and are arranged at intervals in the second direction Y (a-axis direction). In this case, the extension direction of the multiple inversion columns 30 intersects (specifically, is perpendicular to) the off-direction Do of the SiC single crystal, and therefore the multiple inversion columns 30 are inclined by approximately the off-angle θo from the vertical axis toward the off-direction Do in a cross-sectional view seen from the m-plane of the SiC single crystal. Therefore, in consideration of the accuracy of charge balance, it is preferable that the multiple inversion columns 30 extend in the off-direction Do.

[0306] Of course, the arrangement direction of the multiple trench structures 25 may be a direction other than the a-axis direction and the m-axis direction, and the extension direction of the multiple trench structures 25 may be a direction other than the a-axis direction and the m-axis direction. In other words, the multiple trench structures 25 may extend in a direction intersecting both the a-axis direction and the m-axis direction. In this case, the arrangement direction of the multiple inversion columns 30 is a direction other than the a-axis direction and the m-axis direction, and the extension direction of the multiple inversion columns 30 is a direction other than the a-axis direction and the m-axis direction. In other words, the multiple inversion columns 30 extend in a direction intersecting both the a-axis direction and the m-axis direction.

[0307] Modified examples of the SiC semiconductor device 1 will be described below. The configurations of the modified examples are applicable to the first to fourth embodiments described above. Fig. 22 is a cross-sectional perspective view showing the SiC semiconductor device 1 according to the first modified example. In the above embodiments, the impurity region 15 is formed at an interval from the lower end of the semiconductor layer 7 toward the first main surface 3.

[0308] In contrast, the impurity region 15 according to the first modification has a bottom located within the base layer 6 across the boundary between the base layer 6 and the semiconductor layer 7. The bottom of the impurity region 15 is located in the surface layer of the base layer 6. Since the second axial channel C2 substantially coincides with the first axial channel C1, the bottom of the impurity region 15 is formed within the base layer 6 along the first axial channel C1.

[0309] On the other hand, the inversion column 30 described above crosses the bottom of the impurity region 15 in the base layer 6 and has a lower end electrically connected to the base layer 6. The lower end of the inversion column 30 is located in the surface layer of the base layer 6. Since the second axial channel C2 substantially coincides with the first axial channel C1, the lower end of the inversion column 30 is formed along the first axial channel C1 in the base layer 6.

[0310] 23 is a cross-sectional perspective view showing a SiC semiconductor device 1 according to a second modification. In the above-described embodiment, impurity region 15 is formed in semiconductor layer 7. In contrast, in SiC semiconductor device 1 according to the second modification, a p-type semiconductor layer 7 (a p-type epitaxial layer) is formed, and p-type impurity region 15 is omitted. P-type semiconductor layer 7 is distinguished from impurity region 15 in that it does not have first gradually increasing portion 16, first peak portion 17, first gradual portion 18, or first gradual decreasing portion 19.

[0311] The p-type impurity concentration of the semiconductor layer 7 is preferably lower than the n-type impurity concentration of the base layer 6. The semiconductor layer 7 has a p-type impurity concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration of the semiconductor layer 7 may have the following peak value: The p-type impurity concentration of the semiconductor layer 7 may be substantially constant in the thickness direction. Of course, the p-type impurity concentration of the semiconductor layer 7 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0312] The p-type impurity concentration of the semiconductor layer 7 may be adjusted by at least one trivalent element. The trivalent element of the semiconductor layer 7 may be at least one of boron, aluminum, gallium, and indium. The trivalent element of the semiconductor layer 7 is typically boron or aluminum.

[0313] The above-described body region 20 does not necessarily have to be formed. For example, if a part (surface layer) of the semiconductor layer 7 can function as part of the body region 20, the part (surface layer) of the semiconductor layer 7 may be formed as the body region 20, and the body region 20 may be omitted. In other words, the surface layer portion of the semiconductor layer 7 may also serve as the body region 20, and the body region 20 may be formed by utilizing the surface layer portion of the semiconductor layer 7.

[0314] The plurality of inversion columns 30 (intermediate region 36) are formed in the lower region 7a so as to invert the conductivity type of the p-type semiconductor layer 7, and define a plurality of non-inversion columns 35, each made of a part of the p-type semiconductor layer 7. The conductivity type of the well region 39 is changed from p-type to n-type. Also, the conductivity type of the field region 40 is changed from p-type to n-type.

[0315] Of course, even when the p-type semiconductor layer 7 is formed, a configuration including the p-type impurity region 15 may be adopted. In this case, the p-type impurity concentration of the p-type semiconductor layer 7 is corrected (adjusted) by the p-type impurity region 15.

[0316] 24 is a cross-sectional perspective view showing a SiC semiconductor device 1 according to a third modification. The SiC semiconductor device 1 according to the third modification further includes an n-type buffer layer 86 made of single crystal SiC stacked on the base layer 6. The buffer layer 86 is also a component of the chip 2. The buffer layer 86 may also be referred to as a "buffer SiC layer," a "buffer region," or the like.

[0317] The buffer layer 86 extends horizontally in a layered manner and forms a central portion and parts of the first to fourth side surfaces 5A to 5D of the chip 2. The buffer layer 86 is made of an epitaxial layer (i.e., a SiC epitaxial layer) grown from the base layer 6 as a starting point.

[0318] The buffer layer 86 has a lower end and an upper end. The lower end of the buffer layer 86 is the crystal growth starting point, and the upper end of the buffer layer 86 is the crystal growth end point. Because the buffer layer 86 is grown continuously from the base layer 6, the lower end of the buffer layer 86 coincides with the upper end of the base layer 6. The boundary between the base layer 6 and the buffer layer 86 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements. The buffer layer 86 has an off-direction Do and an off-angle θo that are approximately the same as the off-direction Do and the off-angle θo of the base layer 6.

[0319] The buffer layer 86 has a third axis channel C3 along the stacking direction. The third axis channel C3 is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the buffer layer 86, and is surrounded by atomic rows along a crystal axis extending in the stacking direction (crystal growth direction).

[0320] In other words, the third axis channel C3 is a region in which a region in which atomic rows are sparse extends in the stacking direction and in which atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in a plan view. The third axis channel C3 is preferably a region surrounded by atomic rows along a low-index crystal axis among the crystal axes.

[0321] In this embodiment, the third axis channel C3 is formed by a region surrounded by atomic rows along the c-axis of the SiC single crystal. That is, the third axis channel C3 extends along the c-axis and has an off-direction Do and an off-angle θo. In other words, the third axis channel C3 is inclined by the off-angle θo from the vertical axis toward the off-direction Do.

[0322] The n-type impurity concentration of the buffer layer 86 is preferably lower than the n-type impurity concentration of the base layer 6. The buffer layer 86 has a dopant concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３The n-type impurity concentration of the buffer layer 86 may have the following peak value: The n-type impurity concentration of the buffer layer 86 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the buffer layer 86 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0323] The buffer layer 86 has an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the buffer layer 86 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The buffer layer 86 preferably contains a pentavalent element other than phosphorus.

[0324] The n-type impurity concentration of the buffer layer 86 is preferably adjusted by at least nitrogen. When the buffer layer 86 contains two or more pentavalent elements, the buffer layer 86 preferably contains nitrogen and a pentavalent element other than nitrogen. In this case, the buffer layer 86 preferably contains either arsenic or antimony, or both, as the pentavalent element other than phosphorus and nitrogen.

[0325] The buffer layer 86 has a third thickness T3. The third thickness T3 is preferably less than the first thickness T1 of the base layer 6. The third thickness T3 is preferably 1 μm or greater. The third thickness T3 is preferably 5 μm or less. The third thickness T3 may have a value belonging to any one of the following ranges: 1 μm or greater to 1.5 μm or less, 1.5 μm or greater to 2 μm or less, 2 μm or greater to 2.5 μm or less, 2.5 μm or greater to 3 μm or less, 3 μm or greater to 3.5 μm or less, 3.5 μm or greater to 4 μm or less, 4 μm or greater to 4.5 μm or less, and 4.5 μm or greater to 5 μm or less.

[0326] The semiconductor layer 7 is stacked on the buffer layer 86. The semiconductor layer 7 is made of an epitaxial layer (i.e., a SiC epitaxial layer) crystal-grown starting from the buffer layer 86. Therefore, the semiconductor layer 7 has an off-direction Do and an off-angle θo that are approximately identical to the off-direction Do and the off-angle θo of the buffer layer 86. In addition, the second axis channel C2 approximately coincides with the third axis channel C3.

[0327] The second thickness T2 of the semiconductor layer 7 is preferably greater than the third thickness T3. Of course, the second thickness T2 may be less than the third thickness T3. Alternatively, the second thickness T2 may be approximately equal to the third thickness T3.

[0328] The impurity region 15 may have a bottom located in the semiconductor layer 7, and the inversion column 30 may have a lower end located in the base layer 6, the semiconductor layer 7, or the buffer layer 86. Of course, the impurity region 15 may have a bottom located in the buffer layer 86, and the inversion column 30 may have a lower end located in the base layer 6 or the buffer layer 86.

[0329] The above-described embodiment can be implemented in other embodiments. For example, the above-described embodiment employs the base layer 6, the semiconductor layer 7, and the buffer layer 86, each of which includes a SiC single crystal. However, at least one or all of the base layer 6, the semiconductor layer 7, and the buffer layer 86 may include a single crystal of a wide bandgap semiconductor other than a SiC single crystal.

[0330] Wide bandgap semiconductors are semiconductors that have a bandgap larger than that of silicon. Wide bandgap semiconductor single crystals include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga ２ O ３ The base layer 6, the semiconductor layer 7, and the buffer layer 86 may be made of the same type of single crystal, or may be made of different types of single crystal.

[0331] The channeling implantation process (the process of implanting impurities into regions with sparse atomic rows) described above can also be applied to single crystals that have a cubic crystal structure. Therefore, the single crystal of the wide bandgap semiconductor may be a cubic or hexagonal crystal structure. When a cubic single crystal structure is used for at least one or all of the base layer 6, the semiconductor layer 7, and the buffer layer 86, the axial channels are formed by regions surrounded by atomic rows aligned along low-index crystal axes of the cubic crystal structure.

[0332] A low-index crystal axis related to a cubic crystal is a crystal axis in which the absolute values ​​of "h," "k," and "l" in the Miller indices (h, k, l) are all equal to or less than 2 (preferably equal to or less than 1). Of course, at least one or all of the base layer 6, the semiconductor layer 7, and the buffer layer 86 may contain single crystal silicon.

[0333] In the above-described embodiment, an n-type base layer 6 is shown. However, a p-type base layer 6 may be employed. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, in the above description, the "source" of the MISFET structure is replaced with the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced with the "collector" of the IGBT structure. The p-type base layer 6 may be a p-type region containing a trivalent element introduced into the surface layer of the second main surface 4 of the chip 2 by ion implantation.

[0334] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the above-mentioned embodiments. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," etc., as necessary.

[0335] [A1] A semiconductor device (1) including: a semiconductor layer (7) including a main surface (3) and having an axial channel (C2) in a stacking direction (Z); a p-type impurity region (15) formed in the semiconductor layer (7); a trench (26) formed in the main surface (3) shallower than the impurity region (15) and defining a lower region (7a) including a part of the impurity region (15) between the trench (26) and a bottom of the semiconductor layer (7); and an n-type inversion column (30) formed in the lower region (7a) so as to extend along the axial channel (C2) and inverting the conductivity type of the impurity region (15).

[0336] [A2] The semiconductor device (1) according to A1, wherein the inverted column (30) traverses the middle part of the thickness range of the lower region (7a) along the axial channel (C2).

[0337] [A3] A semiconductor device (1) according to A1 or A2, wherein the inversion column (30) has a thickness (TC) in the thickness direction of the semiconductor layer (7) that is greater than the depth (DT) of the trench (26).

[0338] [A4] The semiconductor device (1) according to any one of A1 to A3, wherein the inversion column (30) is made up of a single region.

[0339] [A5] The semiconductor device (1) described in any one of A1 to A4, wherein the inversion column (30) has an upper end on the trench (26) side and a lower end on the bottom side of the semiconductor layer (7), and has a concentration gradient that gradually decreases from the upper end to the lower end.

[0340] [A6] The semiconductor device (1) described in A5, wherein the concentration gradient includes a peak value (P2) on the upper end side and a gradual portion (33) in which the impurity concentration gradually decreases at a gradual rate of decrease in the region on the lower end side of the peak value (P2).

[0341] [A7] The semiconductor device (1) according to A6, wherein the slow portion (33) occupies a thickness range of at least 1 / 4 of the inverted column (30).

[0342] [A8] A semiconductor device (1) according to any one of A1 to A7, wherein the trench (26) extends in a band shape in a planar view, and the inversion column (30) extends in a band shape along the trench (26) in a planar view.

[0343] [A9] The semiconductor device (1) according to A8, wherein the trench (26) extends in the a-axis direction of the semiconductor layer (7) in a plan view.

[0344] [A10] The semiconductor device (1) according to any one of A1 to A9, wherein the semiconductor layer (7) has an off angle (θo) inclined toward an off direction (Do) with respect to a vertical axis (Z), and the axial channel (C2) has the off angle (θo) inclined toward the off direction (Do) with respect to the vertical axis (Z).

[0345] [A11] The semiconductor device (1) according to A10, wherein the off direction (Do) is the a-axis direction of the semiconductor layer (7).

[0346] [A12] The semiconductor device (1) according to A10 or A11, wherein the off angle (θo) is 10° or less.

[0347] [A13] The semiconductor device (1) according to any one of A1 to A12, wherein the semiconductor layer (7) is n-type and the impurity region (15) inverts the conductivity type of the semiconductor layer (7).

[0348] [A14] A semiconductor device (1) according to any one of A1 to A13, wherein the impurity region (15) crosses the middle part of the thickness range of the semiconductor layer (7) along the axial channel (C2).

[0349] [A15] The semiconductor device (1) according to any one of A1 to A14, wherein the inversion column (30) crosses the bottom of the impurity region (15).

[0350] [A16] A semiconductor device (1) according to any one of A1 to A15, wherein the impurity region (15) is formed at an interval from the bottom of the semiconductor layer (7) toward the main surface (3), and the inversion column (30) is electrically connected to a lower layer of the semiconductor layer (7).

[0351] [A17] A semiconductor device (1) according to any one of A1 to A16, wherein the inversion column (30) is formed at a distance from the bottom wall of the trench (26) to the bottom side of the semiconductor layer (7).

[0352] [A18] The semiconductor device (1) according to A17, further comprising an n-type intermediate region (36) formed in the semiconductor layer (7) in a region between the bottom wall of the trench (26) and the inversion column (30).

[0353] [A19] The semiconductor device (1) according to A18, further comprising an n-type source region (37) formed on the side of the trench (26) at a distance from the intermediate region (36) toward the main surface (3) in a surface layer portion of the main surface (3), and defining a channel (Ch) as a current path leading to the inversion column (30) between the intermediate region (36) and the n-type source region (37).

[0354] [A20] The semiconductor device (1) according to A19, wherein the source region (37) has an n-type impurity concentration higher than the n-type impurity concentration of the inversion column (30).

[0355] [A21] The semiconductor device (1) according to any one of A1 to A20, wherein the semiconductor layer (7) is a SiC layer (7) containing a SiC single crystal.

[0356] Although specific embodiments have been described in detail above, these are merely examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification or the order of the embodiment examples.

[0357] REFERENCE SIGNS LIST 1 SiC semiconductor device 3 First main surface 7 Semiconductor layer 7a Lower region 15 Impurity region 26 Trench 30 Inversion column 33 Second gentle region 36 Intermediate region 37 Source region C2 Second axial channel Ch Channel (current path) DT Trench depth P2 Second peak value TC Column thickness Do Off direction θo Off angle Z Vertical direction

Claims

1. a SiC layer including a main surface and having an axial channel in a stacking direction; a p-type impurity region formed in the SiC layer; a trench formed in the main surface shallower than the impurity region, the trench defining a lower region including a part of the impurity region between the trench and a bottom of the SiC layer; an n-type inversion column formed in the lower region so as to extend along the axial channel and invert the conductivity type of the impurity region.

2. The SiC semiconductor device of claim 1 , wherein the inverted column traverses a middle portion of the thickness range of the lower region along the axial channel.

3. The SiC semiconductor device according to claim 1 , wherein the inversion column has a thickness in a thickness direction of the SiC layer that is greater than a depth of the trench.

4. The SiC semiconductor device according to claim 1 , wherein the inversion column is formed of a single region.

5. 2. The SiC semiconductor device according to claim 1, wherein the inversion column has an upper end on the trench side and a lower end on the bottom side of the SiC layer, and has a concentration gradient that gradually decreases from the upper end to the lower end.

6. 6. The SiC semiconductor device according to claim 5, wherein the concentration gradient includes a peak value on the upper end side and a gradual portion in which the impurity concentration gradually decreases at a gradual decrease rate in a region on the lower end side of the peak value.

7. The SiC semiconductor device according to claim 6 , wherein the loose portion occupies a thickness range of at least one-fourth of the inverted column.

8. The trench extends in a strip shape in a plan view, The SiC semiconductor device according to claim 1 , wherein the inversion column extends in a band shape along the trench in a plan view.

9. The SiC semiconductor device according to claim 8 , wherein the trench extends in the a-axis direction of the SiC single crystal in a plan view.

10. the SiC layer has an off angle inclined toward an off direction with respect to a vertical axis, The SiC semiconductor device according to claim 1 , wherein the axial channel has the off angle inclined toward the off direction with respect to the vertical axis.

11. The SiC semiconductor device according to claim 10 , wherein the off-direction is the a-axis direction of the SiC single crystal.

12. The SiC semiconductor device according to claim 10 , wherein the off angle is 10° or less.

13. the SiC layer is n-type; 2. The SiC semiconductor device according to claim 1, wherein said impurity region inverts the conductivity type of said SiC layer.

14. The SiC semiconductor device according to claim 1 , wherein the impurity region traverses a middle portion of a thickness range of the SiC layer along the axial channel.

15. The SiC semiconductor device according to claim 1 , wherein the inversion column crosses the bottom of the impurity region.

16. the impurity region is formed at an interval from the bottom of the SiC layer toward the main surface, The SiC semiconductor device according to claim 1 , wherein the inversion column is electrically connected to a lower portion of the SiC layer.

17. 17. The SiC semiconductor device according to claim 1, wherein the inversion column is formed at a distance from the bottom wall of the trench toward the bottom of the SiC layer.

18. 18. The SiC semiconductor device of claim 17, further comprising an n-type intermediate region formed in the SiC layer in a region between the bottom wall of the trench and the inversion column.

19. 19. The SiC semiconductor device according to claim 18, further comprising an n-type source region formed laterally of the trench at a distance from the intermediate region toward the main surface in a surface layer portion of the main surface, the n-type source region defining a channel as a current path leading to the inversion column between the intermediate region and the n-type source region.

20. 20. The SiC semiconductor device of claim 19, wherein the source region has an n-type impurity concentration higher than an n-type impurity concentration of the inversion column.