SiC SEMICONDUCTOR DEVICE

Abstract

This SiC semiconductor device comprises: a first SiC layer of a first conductivity type having a first axial channel along a stacking direction; a second SiC layer of the first conductivity type having a second axial channel along the stacking direction and stacked on the first SiC layer; a first region of a second conductivity type extending along the first axial channel in the first SiC layer in a cross-sectional view and extending in a first extending direction in a plan view; and a second region of the second conductivity type extending along the second axial channel in the second SiC layer in the cross-sectional view and extending in a second extending direction intersecting the first extending direction so as to intersect the first region in the plan view.

Description

SiC semiconductor device

[0001] This application claims priority to Patent Application No. 2022-212609 filed with the Japan Patent Office on December 28, 2022, the entire disclosure of which is incorporated herein by reference. The present disclosure relates to a SiC semiconductor device.

[0002] Patent Document 1 (US2015 / 0028351A1) discloses an electronic device having an impurity region introduced into a silicon carbide layer by channeling implantation.

[0003] US Patent Application Publication No. 2015 / 0028351

[0004] SUMMARY The present disclosure provides a novel SiC semiconductor device.

[0005] The present disclosure provides a SiC semiconductor device including: a first SiC layer of a first conductivity type having a first axial channel along a stacking direction; a second SiC layer of a first conductivity type having a second axial channel along the stacking direction and stacked on the first SiC layer; a first region of a second conductivity type extending along the first axial channel in the first SiC layer in a cross-sectional view and extending in a first extension direction in a planar view; and a second region of a second conductivity type extending along the second axial channel in the second SiC layer in a cross-sectional view and extending in a second extension direction intersecting the first extension direction so as to intersect with the first region in a planar view.

[0006] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0007] FIG. 1 is a plan view showing a SiC semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example layout of a chip. FIG. 4 is a perspective view showing an example layout of a chip. FIG. 5 is a cross-sectional perspective view showing a first basic embodiment of a column region. FIG. 6A is a plan view showing a first layout example of the first basic embodiment. FIG. 6B is a plan view showing a second layout example of the first basic embodiment. FIG. 7 is a cross-sectional perspective view showing a second basic embodiment of a column region. FIG. 8A is a plan view showing a first layout example of the second basic embodiment. FIG. 8B is a plan view showing a second layout example of the second basic embodiment. FIG. 9 is a cross-sectional perspective view showing a third basic embodiment of a column region. FIG. 10A is a plan view showing a first layout example of the third basic embodiment. FIG. 10B is a plan view showing a second layout example of the third basic embodiment. FIG. 10C is a plan view showing a third layout example of the third basic embodiment. FIG. 11A is a graph showing an example of a concentration gradient in a second region (first region). FIG. 11B is a graph showing an example of a concentration gradient in the second region (first region). FIG. 11C is a graph showing an example of a concentration gradient in the second region (first region). FIG. 11D is a graph showing an example of a concentration gradient in the second region (first region). FIG. 11E is a graph showing an example of a concentration gradient in the second region (first region). FIG. 12 is a graph showing a comparative example of a concentration gradient in the second region (first region). FIG. 13 is a cross-sectional perspective view showing a column region according to the first embodiment. FIG. 14 is a graph showing an example of a concentration gradient in the column region shown in FIG. 13. FIG. 15 is a cross-sectional perspective view showing a column region according to the second embodiment. FIG. 16 is a graph showing an example of a concentration gradient in the column region shown in FIG. 15. FIG. 17 is a cross-sectional perspective view showing a column region according to the third embodiment. FIG. 18 is a graph showing an example of a concentration gradient in the column region shown in FIG. 17. FIG. 19 is a cross-sectional perspective view showing a column region according to the fourth embodiment. FIG. 20 is a graph showing an example of a concentration gradient in the column region shown in FIG. 19. Fig. 21 is a cross-sectional perspective view showing a column region according to a fifth embodiment. Fig. 22 is a graph showing an example of a concentration gradient in the column region shown in Fig. 21. Fig. 23 is a cross-sectional perspective view showing a column region according to a sixth embodiment. Fig. 24 is a graph showing an example of a concentration gradient in the column region shown in Fig. 23.25 is a cross-sectional perspective view showing a column region according to the seventh embodiment. FIG. 26 is a graph showing an example of a concentration gradient in the column region shown in FIG. 25. FIG. 27 is a cross-sectional perspective view showing a column region according to the eighth embodiment. FIG. 28 is a graph showing an example of a concentration gradient in the column region shown in FIG. 27. FIG. 29 is a cross-sectional perspective view showing a column region according to the ninth embodiment. FIG. 30 is a cross-sectional perspective view showing a column region according to the tenth embodiment. FIG. 31 is a cross-sectional perspective view showing a column region according to the eleventh embodiment. FIG. 32 is a cross-sectional perspective view showing a column region according to the twelfth embodiment. FIG. 33 is a plan view showing a main part of an active region. FIG. 34 is a cross-sectional perspective view showing a gate structure according to the first embodiment. FIG. 35 is a cross-sectional view showing a main part of a peripheral region. FIG. 36 is a cross-sectional perspective view showing a gate structure according to the second embodiment. FIG. 37 is a schematic view showing a wafer used in manufacturing a SiC semiconductor device. FIG. 38 is a flowchart showing an example of a method for manufacturing a SiC semiconductor device. FIG. 39A is a cross-sectional perspective view showing an example of a method for manufacturing a SiC semiconductor device. 39B is a cross-sectional perspective view showing a step subsequent to FIG. 39A . FIG. 39C is a cross-sectional perspective view showing a step subsequent to FIG. 39B . FIG. 39D is a cross-sectional perspective view showing a step subsequent to FIG. 39C . FIG. 39E is a cross-sectional perspective view showing a step subsequent to FIG. 39D . FIG. 39F is a cross-sectional perspective view showing a step subsequent to FIG. 39E . FIG. 39G is a cross-sectional perspective view showing a step subsequent to FIG. 39F . FIG. 39H is a cross-sectional perspective view showing a step subsequent to FIG. 39G . FIG. 40A is a schematic view for explaining a crystal orientation measurement step. FIG. 40B is a schematic view for explaining a crystal orientation measurement step. FIG. 41A is a schematic view for explaining an ion implantation step. FIG. 41B is a schematic view for explaining an ion implantation step. FIG. 42 is a plan view showing a SiC semiconductor device according to the second embodiment. FIG. 43 is a cross-sectional view taken along line XLIII-XLIII shown in FIG. 42 . FIG. 44 is a plan view showing an example of a chip layout. FIG. 45 is a perspective view showing an example of a chip layout. Fig. 46 is a plan view showing a main part of an active region. Fig. 47 is a cross-sectional perspective view showing a gate structure according to a first embodiment. Fig. 48 is a cross-sectional perspective view showing a main part of a peripheral region. Fig. 49 is a cross-sectional perspective view showing a gate structure according to a second embodiment.FIG. 50 is a sectional perspective view showing a gate structure according to a third embodiment. FIG. 51 is a sectional perspective view showing a gate structure according to a fourth embodiment. FIG. 52 is a sectional perspective view showing a gate structure according to a fifth embodiment. FIG. 53 is a plan view showing a SiC semiconductor device according to the third embodiment. FIG. 54 is a sectional view taken along line LIV-LIV shown in FIG. 53. FIG. 55 is a plan view showing an example of a chip layout. FIG. 56 is a perspective view showing an example of a chip layout. FIG. 57 is a sectional perspective view showing a diode structure according to a first embodiment. FIG. 58 is a sectional perspective view showing a diode structure according to a second embodiment. FIG. 59 is a sectional perspective view showing a diode structure according to a third embodiment. FIG. 60 is a sectional perspective view showing a diode structure according to a fourth embodiment. FIG. 61 is a sectional perspective view showing a diode structure according to a fifth embodiment.

[0008] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0009] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0010] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0011] Fig. 1 is a plan view showing a SiC semiconductor device 1A according to a first embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a chip 2. Fig. 4 is a perspective view showing an example layout of a chip 2. Fig. 5 is a cross-sectional perspective view showing a main part of a chip 2 together with a first basic form of a column region 12.

[0012] 1 to 5, SiC semiconductor device 1A includes chip 2 including SiC single crystal. Chip 2 may be referred to as a "SiC chip" or a "semiconductor chip." In this embodiment, chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which chip 2 is made of 4H-SiC single crystal, but chip 2 may be made of another polytype.

[0013] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0014] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0015] In the circumferential direction of the chip 2 (counterclockwise in FIG. 1 ) starting from the first side surface 5A, the second side surface 5B is connected to the first side surface 5A, the third side surface 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0016] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0017] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, an axis extending along the vertical direction Z may be referred to as a "vertical axis." Also, below, the first direction X and the second direction Y may be referred to as a "horizontal direction." The horizontal direction is also a direction extending along the first main surface 3.

[0018] 5, the chip 2 (first main surface 3 and second main surface 4) has an off angle θoff inclined at a predetermined angle in a predetermined off direction Doff with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off direction Doff by the off angle θoff. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off angle θoff.

[0019] The off-direction Doff is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle θoff may be greater than 0° and less than or equal to 10°. The off-angle θoff may have a value belonging to any one of the ranges of greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.

[0020] The off angle θ is preferably 5° or less. The off angle θ is particularly preferably 2° or more and 4.5° or less. The off angle θ is typically set in the range of 4°±0.1°. Of course, this specification does not exclude a configuration in which the off angle θ is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0021] The chip 2 includes an n-type base layer 6 made of SiC single crystal. The base layer 6 may also be referred to as a "base SiC layer," a "base region," or the like. The base layer 6 extends horizontally in a layered manner and forms part of the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the base layer 6 is made of a substrate made of SiC single crystal (i.e., a SiC substrate). The base layer 6 has the off direction Doff and off angle θoff described above.

[0022] The base layer 6 has a base axis channel CHB along the stacking direction. The base axis channel CHB is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the base layer 6, and is surrounded by atomic rows constituting a crystal axis extending in the stacking direction (crystal growth direction).

[0023] In other words, the base axis channel CHB is a region in which a region with sparse atomic rows extends in the stacking direction and in which the atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in a planar view. The base axis channel CHB is preferably a region surrounded by atomic rows along low-index crystal axes among the crystal axes. The low-index crystal axes are crystal axes in which the absolute values ​​of "a1," "a2," "a3," and "c" are all expressed as 2 or less (preferably 1 or less) with respect to the Miller indices (a1, a2, a3, c) (the same applies hereinafter in this specification).

[0024] In this embodiment, the base axis channel CHB is formed by a region surrounded by atomic rows aligned along the c-axis ((0001) axis) of the SiC single crystal. That is, the base axis channel CHB extends along the c-axis and has the off-direction Doff and off-angle θoff described above. In other words, the base axis channel CHB is inclined from the vertical axis toward the off-direction Doff by the off-angle θoff.

[0025] The base layer 6 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration of the base layer 6 may have the following peak value. The base layer 6 preferably has an almost constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the base layer 6 is preferably adjusted with a single pentavalent element. It is particularly preferable that the n-type impurity concentration of the base layer 6 is adjusted with a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the base layer 6 is adjusted with nitrogen.

[0026] The base layer 6 has a base thickness TB. The base thickness TB may be 5 μm or more and 300 μm or less. The base thickness TB may have a value belonging to any one of the following ranges: 5 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or more and 300 μm or less. The base thickness TB is preferably 50 μm or more and 250 μm or less.

[0027] The chip 2 includes a stacked layer 7 stacked on a base layer 6. The stacked layer 7 may be referred to as a "semiconductor layer," a "SiC layer," a "SiC stacked layer," a "semiconductor stacked layer," or the like. The stacked layer 7 has a stacked structure in which multiple (two or more) semiconductor layers made of SiC single crystal are stacked. In this embodiment, the multiple semiconductor layers are provided as layers for forming a superjunction structure SJ. The number of stacked multiple semiconductor layers (superjunction structure SJ) is arbitrary and is adjusted appropriately depending on the electrical characteristics to be achieved. Examples of electrical characteristics include a breakdown voltage and a resistance value.

[0028] The number of stacked semiconductor layers (super junction structure SJ) is typically 2 to 5 (two, three, four, or five). In this embodiment, stacked portion 7 has a two-layer structure including an n-type first layer 8 made of SiC single crystal and an n-type second layer 9 made of SiC single crystal. First layer 8 may be referred to as a "first SiC layer," a "first semiconductor layer," or the like. Second layer 9 may be referred to as a "second SiC layer," a "second semiconductor layer," or the like.

[0029] The first layer 8 is laminated on the base layer 6. The first layer 8 extends horizontally in a layered manner and forms the middle portion of the chip 2 and parts of the first to fourth side surfaces 5A to 5D. The first layer 8 is made of an epitaxial layer (i.e., a SiC epitaxial layer) grown from the base layer 6 as a starting point.

[0030] The first layer 8 has a lower end and an upper end. The lower end of the first layer 8 is the starting point of crystal growth, and the upper end of the first layer 8 is the end point of crystal growth. Because the first layer 8 is grown continuously from the base layer 6, the lower end of the first layer 8 coincides with the upper end of the base layer 6. The boundary between the base layer 6 and the first layer 8 is not necessarily visible and can be indirectly evaluated and / or determined from other configurations or elements. The first layer 8 has an off-direction Doff and an off-angle θoff that are approximately the same as the off-direction Doff and off-angle θoff of the base layer 6.

[0031] The first layer 8 has a first axis channel CH1 along the stacking direction. The first axis channel CH1 is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the first layer 8, and is surrounded by atomic rows along a crystal axis extending in the stacking direction (crystal growth direction).

[0032] In other words, the first axis channel CH1 is a region in which a region in which atomic rows are sparse extends in the stacking direction and in which atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in a plan view. The first axis channel CH1 is preferably a region surrounded by atomic rows along a low-index crystal axis among the crystal axes.

[0033] In this embodiment, the first axis channel CH1 is formed by a region surrounded by atomic rows along the c-axis of the SiC single crystal. That is, the first axis channel CH1 extends along the c-axis and has an off-direction Doff and an off-angle θoff. In other words, the first axis channel CH1 is inclined by the off-angle θoff from the vertical axis toward the off-direction Doff.

[0034] The n-type impurity concentration of the first layer 8 is preferably lower than the n-type impurity concentration of the base layer 6. The first layer 8 has a n-type impurity concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the first layer 8 may have a peak value of the following: The n-type impurity concentration of the first layer 8 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the first layer 8 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0035] The first layer 8 has an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the first layer 8 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The first layer 8 preferably contains a pentavalent element other than phosphorus.

[0036] The n-type impurity concentration of the first layer 8 is preferably adjusted by at least nitrogen. When the first layer 8 contains two or more pentavalent elements, the first layer 8 preferably contains nitrogen and a pentavalent element other than nitrogen. In this case, the first layer 8 preferably contains either arsenic or antimony, or both, as the pentavalent element other than phosphorus and nitrogen.

[0037] The first layer 8 has a first thickness T1. The first thickness T1 is preferably less than the base thickness TB. The first thickness T1 is preferably 1 μm or greater. The first thickness T1 is preferably 5 μm or less. The first thickness T1 may have a value belonging to any one of the following ranges: 1 μm or greater to 1.5 μm or less, 1.5 μm or greater to 2 μm or less, 2 μm or greater to 2.5 μm or less, 2.5 μm or greater to 3 μm or less, 3 μm or greater to 3.5 μm or less, 3.5 μm or greater to 4 μm or less, 4 μm or greater to 4.5 μm or less, and 4.5 μm or greater to 5 μm or less.

[0038] The second layer 9 is stacked on the first layer 8. The second layer 9 extends horizontally in a layered manner, forming the first main surface 3 and forming parts of the first to fourth side surfaces 5A to 5D. The second layer 9 is made of an epitaxial layer (i.e., a SiC epitaxial layer) crystal-grown starting from the first layer 8.

[0039] The second layer 9 has a lower end and an upper end. The lower end of the second layer 9 is the starting point of crystal growth, and the upper end of the second layer 9 is the end point of crystal growth. Because the second layer 9 is grown continuously from the first layer 8, the lower end of the second layer 9 coincides with the upper end of the first layer 8. The boundary between the first layer 8 and the second layer 9 is not necessarily visible and can be indirectly evaluated and / or determined from other configurations or elements. The second layer 9 has an off-direction Doff and an off-angle θoff that are substantially identical to the off-direction Doff and off-angle θoff of the first layer 8.

[0040] The second layer 9 has a second axis channel CH2 extending along the stacking direction. The second axis channel CH2 is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the second layer 9, and is surrounded by atomic rows along a crystal axis extending in the stacking direction (crystal growth direction).

[0041] In other words, the second axis channel CH2 is a region in which a region in which atomic rows are sparse extends in the stacking direction and in which atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in a plan view. The second axis channel CH2 is preferably a region surrounded by atomic rows along a low-index crystal axis among the crystal axes.

[0042] In this embodiment, the second axis channel CH2 is formed by a region surrounded by atomic rows along the c-axis of the SiC single crystal. That is, the second axis channel CH2 extends along the c-axis and has an off-direction Doff and an off-angle θoff. In other words, the second axis channel CH2 is inclined by the off-angle θoff from the vertical axis toward the off-direction Doff.

[0043] The n-type impurity concentration of the second layer 9 is preferably lower than the n-type impurity concentration of the base layer 6. The second layer 9 has an n-type impurity concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the second layer 9 may have a peak value of the following: The n-type impurity concentration of the second layer 9 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the second layer 9 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0044] The n-type impurity concentration of the second layer 9 is preferably approximately equal to the n-type impurity concentration of the first layer 8. Of course, the n-type impurity concentration of the second layer 9 may be different from the n-type impurity concentration of the first layer 8. In this case, the n-type impurity concentration (peak value) of the second layer 9 may be higher than the n-type impurity concentration (peak value) of the first layer 8, or may be lower than the n-type impurity concentration (peak value) of the first layer 8.

[0045] The second layer 9 has an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the second layer 9 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The second layer 9 preferably contains a pentavalent element other than phosphorus.

[0046] The n-type impurity concentration of second layer 9 is preferably adjusted by at least nitrogen. When second layer 9 contains two or more pentavalent elements, second layer 9 preferably contains nitrogen and a pentavalent element other than nitrogen. In this case, second layer 9 preferably contains either arsenic or antimony, or both, as the pentavalent element other than phosphorus and nitrogen.

[0047] The second layer 9 has a second thickness T2. The second thickness T2 is preferably less than the base thickness TB. The second thickness T2 may be approximately equal to the first thickness T1 or may be different from the first thickness T1. The second thickness T2 may be greater than the first thickness T1 or less than the first thickness T1.

[0048] The second thickness T2 is preferably 1 μm or more. The second thickness T2 is preferably 5 μm or less. The second thickness T2 may have a value belonging to any one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0049] The SiC semiconductor device 1A includes an active region 10 set in a chip 2. The active region 10 is set in an inner portion of the chip 2 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 10 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The planar area of ​​the active region 10 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0050] The SiC semiconductor device 1A includes a peripheral region 11 set outside the active region 10 in the chip 2. The peripheral region 11 is provided in a region between the periphery of the chip 2 and the active region 10 in a planar view. The peripheral region 11 extends in a band shape along the active region 10 in a planar view, and is set in a polygonal ring shape (a square ring shape in this embodiment) surrounding the active region 10.

[0051] The SiC semiconductor device 1A includes a p-type column region 12 formed in the stacked portion 7 in the active region 10. The column region 12 may also be referred to as a "column layer," a "pillar layer (region)," a "p-type layer (region)," a "p-type zone," or the like. The column region 12 is formed in a three-dimensional lattice shape within the stacked portion 7, and defines an n-type drift region 13 having a three-dimensional lattice shape and made up of a part of the stacked portion 7.

[0052] The column region 12 is formed in at least one of the semiconductor layers constituting the multilayer portion 7, and forms a superjunction structure SJ together with the drift region 13 within the multilayer portion 7. In this embodiment, the column region 12 has a multilayer structure including a plurality of p-type first regions 14 and a plurality of p-type second regions 15.

[0053] The first regions 14 are formed at intervals in the horizontal direction within the first layer 8, and define a plurality of n-type first drift regions 16, each made up of a part of the first layer 8. The first regions 14, together with the first drift regions 16, form a plurality of first pn junctions having charge balance.

[0054] That is, the multiple first regions 14 constitute a first superjunction structure SJ1 together with the multiple first drift regions 16. The charge-balanced state means that, for multiple adjacent first regions 14, the depletion layer extending from one first pn junction and the depletion layer extending from the other first pn junction are connected within the multiple first drift regions 16.

[0055] The first regions 14 are arranged at intervals in the first array direction Da1 in the first layer 8 and are each formed in a strip shape extending in the first extension direction De1. The first extension direction De1 is a direction that intersects or is perpendicular to the first array direction Da1. In other words, the first regions 14 are formed in a stripe shape extending in the first extension direction De1, and the first drift regions 16 are formed in a stripe shape extending in the first extension direction De1.

[0056] The multiple first regions 14 are formed of channeling regions (first channeling regions) extending along the first axial channel CH1 in the first layer 8 in a cross-sectional view. That is, the first regions 14 are impurity regions introduced parallel or nearly parallel to a region (first axial channel CH1) surrounded by atomic rows along the low-index crystal axis in the first layer 8, and extend at an angle with respect to the first main surface 3.

[0057] Therefore, the first regions 14 have an off direction Doff and an off angle θoff that are substantially identical to the off direction Doff and the off angle θoff of the first axis channel CH1. In other words, the first regions 14 are inclined from the vertical axis toward the off direction Doff by the off angle θoff.

[0058] Each of the multiple first regions 14 has a first lower end 14a at the lower end of the first layer 8 and a first upper end 14b at the upper end of the first layer 8. The first lower end 14a is located in a region on the lower end side of the first layer 8 relative to the intermediate portion of the thickness range of the first layer 8, and the first upper end 14b is located in a region on the upper end side of the first layer 8 relative to the intermediate portion of the thickness range of the first layer 8. In other words, each of the multiple first regions 14 is made up of a single impurity region having a thickness (depth) that traverses the intermediate portion of the first layer 8 along the first axial channel CH1.

[0059] The first lower end 14a may be formed at a distance from the lower end of the first layer 8 toward the upper end, and may face the base layer 6 across a part (lower end) of the first layer 8. The first lower end 14a may be substantially coincident with the lower end of the first layer 8 and connected to the base layer 6.

[0060] The distance between the lower end of the first layer 8 and the first lower end 14a may be 0 μm or more and 2 μm or less. The distance between the lower end of the first layer 8 and the first lower end 14a may have a value belonging to any one of the ranges of 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0061] The first lower end 14a may have an extension that crosses the boundary between the base layer 6 and the first layer 8 and is located within the base layer 6. In this case, the thickness of the extension of the first lower end 14a, measured from the upper end of the base layer 6, may be greater than 0 μm and less than 2 μm. The thickness of the extension of the first lower end 14a may have a value that belongs to any one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm or more to 1 μm or less, 1 μm or more to 1.5 μm or less, and 1.5 μm or more to 2 μm or less.

[0062] The first upper end 14b may be formed at a distance from the upper end of the first layer 8 (i.e., the second layer 9) toward the lower end, and may face the upper end of the first layer 8 across a part (upper end) of the first layer 8. The first upper end 14b may be substantially coincident with the upper end of the first layer 8 and connected to the second layer 9.

[0063] The distance between the upper end of the first layer 8 and the first upper end 14b may be 0 μm or more and 1 μm or less. The distance between the upper end of the first layer 8 and the first upper end 14b may have a value belonging to any one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0064] The plurality of first regions 14 are 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration of the first region 14 may have the following peak value. The p-type impurity concentration of the first region 14 is preferably adjusted by at least one trivalent element. It is particularly preferable that the p-type impurity concentration of the first region 14 is adjusted by a trivalent element that is heavier than carbon. In other words, the first region 14 preferably contains a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the p-type impurity concentration of the first region 14 is adjusted by aluminum.

[0065] Each of the multiple first regions 14 has a first width W1. The first width W1 is the width of the first regions 14 along the first arrangement direction Da1. The first width W1 is preferably less than the first thickness T1 of the first layer 8. Of course, the first width W1 may be equal to or greater than the first thickness T1. The first width W1 is preferably less than the second thickness T2 of the second layer 9. Of course, the first width W1 may be equal to or greater than the second thickness T2.

[0066] The first width W1 may be 0.1 μm or more and 5 μm or less. The first width W1 may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The first width W1 is preferably 0.5 μm or more and 1.5 μm or less.

[0067] The plurality of first regions 14 each have a first region thickness TR1 (first region depth). The first region thickness TR1 may be less than the first thickness T1 of the first layer 8. The first region thickness TR1 may be greater than the first thickness T1. The first region thickness TR1 may be approximately equal to the first thickness T1. The first region thickness TR1 may be less than the second thickness T2 of the second layer 9. The first region thickness TR1 may be greater than the second thickness T2. The first region thickness TR1 may be approximately equal to the second thickness T2.

[0068] The first region thickness TR1 is preferably 1 μm or more. The first region thickness TR1 is preferably 5 μm or less. The first region thickness TR1 may have a value belonging to any one of the ranges of 1 μm or more to 1.5 μm or less, 1.5 μm or more to 2 μm or less, 2 μm or more to 2.5 μm or less, 2.5 μm or more to 3 μm or less, 3 μm or more to 3.5 μm or less, 3.5 μm or more to 4 μm or less, 4 μm or more to 4.5 μm or less, and 4.5 μm or more to 5 μm or less.

[0069] Preferably, the first width W1 is less than the first thickness T1 of the first layer 8, and the first region thickness TR1 is greater than the first width W1. That is, the first regions 14 each preferably have a first aspect ratio TR1 / W1 such that they extend in a vertically elongated columnar shape along the first axial channel CH1. The first aspect ratio TR1 / W1 is the ratio of the first region thickness TR1 to the first width W1. In this case, it is particularly preferred that the first region thickness TR1 be greater than the first thickness T1. For example, the first aspect ratio TR1 / W1 may be greater than 1 and not greater than 100.

[0070] The first regions 14 are formed at intervals of a first pitch P1 in the first arrangement direction Da1. The first pitch P1 is preferably less than the first thickness T1 of the first layer 8. Of course, the first pitch P1 may be equal to or greater than the first thickness T1. The first pitch P1 is preferably less than the second thickness T2 of the second layer 9. Of course, the first pitch P1 may be equal to or greater than the second thickness T2.

[0071] The first pitch P1 may be 0.1 μm or more and 5 μm or less. The first pitch P1 may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The first pitch P1 is preferably 0.5 μm or more and 1.5 μm or less.

[0072] The second regions 15 are formed at intervals in the horizontal direction within the second layer 9, and define a plurality of n-type second drift regions 17, each made of a part of the second layer 9. The second regions 15, together with the second drift regions 17, form a plurality of second pn junctions having charge balance.

[0073] That is, the second regions 15 and the second layer 9 form a second superjunction structure SJ2. The charge balance state means that, for the plurality of second regions 15 adjacent to each other, the depletion layer extending from one second pn junction and the depletion layer extending from the other second pn junction are connected within the plurality of second drift regions 17.

[0074] The second regions 15 are formed in the second layer 9 so as to overlap the first regions 14 in the stacking direction. Specifically, the second regions 15 are arranged at intervals in the second layer 9 in a second arrangement direction Da2 different from the first arrangement direction Da1, and are each formed in a strip shape extending in the second extension direction De2 different from the first extension direction De1.

[0075] The second array direction Da2 is a direction intersecting the first array direction Da1, and the second extension direction De2 is a direction intersecting the first extension direction De1. The second extension direction De2 is a direction intersecting or perpendicular to the second array direction Da2. That is, the multiple second regions 15 are formed in stripes extending in the second extension direction De2, and the multiple second drift regions 17 are formed in stripes extending in the second extension direction De2.

[0076] The second regions 15 intersect with the first regions 14 in a plan view. That is, the second drift regions 17 are connected to the first drift regions 16 in a lattice pattern at the boundary between the first layer 8 and the second layer 9, and together with the first drift regions 16 form one three-dimensional lattice-shaped drift region 13. The second drift regions 17, together with the first drift regions 16, form a three-dimensional lattice-shaped current path.

[0077] The second regions 15 are formed of channeling regions (second channeling regions) extending along the second axial channel CH2 in the second layer 9 in a cross-sectional view. That is, the second regions 15 are impurity regions introduced parallel or nearly parallel to a region (second axial channel CH2) surrounded by atomic rows along the low-index crystal axis in the second layer 9, and extend at an angle with respect to the first main surface 3.

[0078] Therefore, the second regions 15 have an off direction Doff and an off angle θoff that are substantially identical to the off direction Doff and the off angle θoff of the second axis channel CH2. In other words, the second regions 15 are inclined from the vertical axis toward the off direction Doff by the off angle θoff.

[0079] Each of the second regions 15 has a second lower end 15a at the lower end of the second layer 9 and a second upper end 15b at the upper end of the second layer 9. The second lower end 15a is located in a region closer to the lower end of the second layer 9 than the intermediate portion of the thickness range of the second layer 9, and the second upper end 15b is located in a region closer to the upper end of the second layer 9 than the intermediate portion of the thickness range of the second layer 9. In other words, each of the second regions 15 is formed of a single impurity region having a thickness (depth) that traverses the intermediate portion of the second layer 9 along the second axial channel CH2.

[0080] The second lower end 15a may be formed at a distance from the lower end of the second layer 9 toward the upper end, and may face the first layer 8 (the plurality of first regions 14) across a part (lower end) of the second layer 9. The second lower end 15a may be substantially coincident with the lower end of the second layer 9 and connected to the first layer 8.

[0081] The distance between the lower end of the second layer 9 and the second lower end 15a may be 0 μm or more and 2 μm or less. The distance between the lower end of the second layer 9 and the second lower end 15a may have a value belonging to any one of the ranges of 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0082] Second lower end 15a may have an extension that crosses the boundary between first layer 8 and second layer 9 and is located within first layer 8. In this case, the thickness of the extension of second lower end 15a, measured from the upper end of first layer 8, may be greater than 0 μm and less than 2 μm. The thickness of the extension of second lower end 15a may have a value that belongs to any one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm or more to 1 μm or less, 1 μm or more to 1.5 μm or less, and 1.5 μm or more to 2 μm or less.

[0083] The second upper end 15b may be formed at a distance from the upper end of the second layer 9 (i.e., the first main surface 3) toward the lower end, and may face the upper end of the second layer 9 across a part (upper end) of the second layer 9. In this case, the space between the first main surface 3 and the second upper end 15b of the second layer 9 may be used as a region for forming a device structure (other impurity regions, etc.). Of course, the second upper end 15b may be exposed from the upper end of the second layer 9 (i.e., the first main surface 3).

[0084] The distance between the upper end of the second layer 9 and the second upper end 15b may be 0 μm or more and 1 μm or less. The distance between the upper end of the second layer 9 and the second upper end 15b may have a value belonging to any one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0085] The plurality of second regions 15 are 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration (peak value) of the second region 15 may be equal to or greater than the p-type impurity concentration (peak value) of the first region 14. The p-type impurity concentration (peak value) of the second region 15 may be less than the p-type impurity concentration (peak value) of the first region 14. The p-type impurity concentration (peak value) of the second region 15 may be approximately equal to the p-type impurity concentration (peak value) of the first region 14.

[0086] The p-type impurity concentration of the second region 15 is preferably adjusted by at least one trivalent element. It is particularly preferable that the p-type impurity concentration of the second region 15 is adjusted by a trivalent element that is heavier than carbon. In other words, the second region 15 preferably contains a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the p-type impurity concentration of the second region 15 is adjusted by aluminum.

[0087] Each of the second regions 15 has a second width W2. The second width W2 is the width of the second regions 15 along the second arrangement direction Da2. The second width W2 is preferably less than the second thickness T2 of the second layer 9. Of course, the second width W2 may be equal to or greater than the second thickness T2.

[0088] The second width W2 is preferably less than the first thickness T1 of the first layer 8. Of course, the second width W2 may be equal to or greater than the first thickness T1. The second width W2 is preferably approximately equal to the first width W1 of the first region 14. Of course, the second width W2 may be equal to or greater than the first width W1, or may be less than the first width W1.

[0089] The second width W2 may be 0.1 μm or more and 5 μm or less. The second width W2 may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The second width W2 is preferably 0.5 μm or more and 1.5 μm or less.

[0090] Each of the second regions 15 has a second region thickness TR2 (region depth). The second region thickness TR2 may be less than the second thickness T2 of the second layer 9. The second region thickness TR2 may be greater than the second thickness T2. The second region thickness TR2 may be approximately equal to the second thickness T2.

[0091] The second regional thickness TR2 may be less than the first thickness T1 of the first layer 8. The second regional thickness TR2 may be greater than the first thickness T1. The second regional thickness TR2 may be approximately equal to the first thickness T1. The second regional thickness TR2 may be less than the first regional thickness TR1 of the first region 14. The second regional thickness TR2 may be greater than the first regional thickness TR1. The second regional thickness TR2 may be approximately equal to the first regional thickness TR1.

[0092] The second region thickness TR2 is preferably 1 μm or more. The second region thickness TR2 is preferably 5 μm or less. The second region thickness TR2 may have a value belonging to any one of the ranges of 1 μm or more to 1.5 μm or less, 1.5 μm or more to 2 μm or less, 2 μm or more to 2.5 μm or less, 2.5 μm or more to 3 μm or less, 3 μm or more to 3.5 μm or less, 3.5 μm or more to 4 μm or less, 4 μm or more to 4.5 μm or less, and 4.5 μm or more to 5 μm or less.

[0093] Preferably, the second width W2 is less than the second thickness T2 of the second layer 9, and the second region thickness TR2 is greater than the second width W2. That is, the second regions 15 each preferably have a second aspect ratio TR2 / W2 such that they extend in a vertically elongated columnar shape along the second axial channel CH2. The second aspect ratio TR2 / W2 is the ratio of the second region thickness TR2 to the second width W2. In this case, it is particularly preferred that the second region thickness TR2 be greater than the second thickness T2. For example, the second aspect ratio TR2 / W2 may be greater than 1 and not greater than 100.

[0094] The second regions 15 are formed at intervals of a second pitch P2 in the second arrangement direction Da2. The second pitch P2 is preferably less than the second thickness T2 of the second layer 9. Of course, the second pitch P2 may be equal to or greater than the second thickness T2 of the second layer 9. The second pitch P2 is preferably less than the first thickness T1 of the first layer 8. Of course, the second pitch P2 may be equal to or greater than the first thickness T1.

[0095] The second pitch P2 may be approximately equal to the first pitch P1 or may be different from the first pitch P1. The second pitch P2 may be larger than the first pitch P1 or smaller than the first pitch P1.

[0096] The second pitch P2 may be 0.1 μm or more and 5 μm or less. The second pitch P2 may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The second pitch P2 is preferably 0.5 μm or more and 1.5 μm or less.

[0097] In this embodiment, a superjunction structure SJ having a two-layer structure is shown. However, a superjunction structure SJ having a stacked structure of three or more layers may also be adopted. That is, a stacked portion 7 having a stacked structure of three or more layers may be formed, and a column region 12 having a stacked structure of three or more layers may be formed.

[0098] In this case, the third and subsequent semiconductor layers in the stacked portion 7 are formed to have the same configuration as the second layer 9. On the other hand, in the column region 12, the regions formed in the odd-numbered (2n+1: n is a natural number greater than or equal to 1) semiconductor layers are formed to have the same configuration as the first region 14, and the regions formed in the even-numbered (2n+2) semiconductor layers are formed to have the same configuration as the second region 15. The (n+2)th layer region of the column region 12 is formed in the (n+2)th layer semiconductor layer in the same relationship as the (n+1)th layer region to the nth layer region.

[0099] Layout examples of the first region 14 and the second region 15 will be described below with reference to FIGS. 5, 6A, and 6B. FIG. 6A is a plan view showing a first layout example of the column region 12 according to the first basic form. FIG. 6B is a plan view showing a second layout example of the column region 12 according to the first basic form. In FIGS. 6A and 6B, the first region 14 is indicated by dashed lines, and the second region 15 is indicated by hatching.

[0100] 5, 6A, and 6B, the first arrangement direction Da1 of the first regions 14 may be the a-axis direction (second direction Y), and the first extension direction De1 of the first regions 14 may be the m-axis direction (first direction X). In this case, the first extension direction De1 intersects (specifically, is perpendicular to) the off-direction Doff of the first layer 8, and therefore the multiple first regions 14 are inclined by approximately the off angle θoff from the vertical axis toward the off-direction Doff in a cross-sectional view taken from the m-plane ((1-100) plane) of the SiC single crystal. The m-plane of the SiC single crystal is a crystal plane perpendicular to the m-axis direction.

[0101] 5 and 6A , the second regions 15 may be orthogonal to the first regions 14 in a plan view. That is, the second arrangement direction Da2 of the second regions 15 may be the m-axis direction (first direction X), and the second extension direction De2 of the second regions 15 may be the a-axis direction (second direction Y). In this case, the second arrangement direction Da2 coincides with the first extension direction De1 and is orthogonal to the first arrangement direction Da1. Furthermore, the second extension direction De2 coincides with the first arrangement direction Da1 and is orthogonal to the first extension direction De1.

[0102] In this case, since the second extending direction De2 coincides with the off-direction Doff of the second layer 9, the second regions 15 extend substantially in the vertical direction Z in a cross-sectional view taken from the a-plane ((11-20) plane) of the SiC single crystal. The a-plane of the SiC single crystal is a direction perpendicular to the a-axis direction. The second regions 15 are inclined by substantially the off angle θoff from the vertical axis toward the off-direction Doff in a cross-sectional view taken from the m-plane of the SiC single crystal.

[0103] 6B , the second regions 15 may intersect the first regions 14 non-orthogonally in a planar view. That is, the second arrangement direction Da2 of the second regions 15 may be a direction other than the m-axis direction and the a-axis direction, and the second extension direction De2 of the second regions 15 may be a direction other than the m-axis direction and the a-axis direction. In this case, the second arrangement direction Da2 intersects both the first arrangement direction Da1 and the first extension direction De1, and the second extension direction De2 intersects both the first arrangement direction Da1 and the first extension direction De1. Furthermore, the second extension direction De2 intersects the off-direction Doff of the second layer 9.

[0104] The second extension direction De2 may be inclined from the a-axis toward one side (left side of the paper) or the other side (right side of the paper) of the m-axis in a plan view. When the a-axis is taken as a reference (0°), the second regions 15 have the second extension direction De2 that forms an extension angle θa with the a-axis.

[0105] The absolute value of the extension angle θa may be greater than 0° and less than 90°. The extension angle θa may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° or greater and less than 36°, 36° or greater and less than 54°, 54° or greater and less than 72°, and 72° or greater and less than 90°. The absolute value of the extension angle θa is typically set to a value belonging to any one of the ranges of 30°±5°, 45°±5°, and 60°±5°.

[0106] The column region 12 may have the configurations shown in Figures 7, 8A, and 8B. Figure 7 is a cross-sectional perspective view showing a second basic configuration of the column region 12. Figures 8A and 8B are plan views showing first and second layout examples of the column region 12 according to the second basic configuration. In Figures 8A and 8B, the first region 14 is indicated by a dashed line, and the second region 15 is indicated by hatching.

[0107] 7 , 8A, and 8B , the first arrangement direction Da1 of the first regions 14 may be the m-axis direction (first direction X), and the first extension direction De1 of the first regions 14 may be the a-axis direction (second direction Y). In this case, the first extension direction De1 coincides with the off-direction Doff of the first layer 8, and therefore the multiple first regions 14 extend substantially in the vertical direction Z in a cross-sectional view seen from the a-plane of the SiC single crystal. The multiple first regions 14 are inclined by substantially the off angle θoff from the vertical axis toward the off-direction Doff in a cross-sectional view seen from the m-plane of the SiC single crystal.

[0108] 7 and 8A , the second regions 15 may be orthogonal to the first regions 14 in a plan view. That is, the second arrangement direction Da2 of the second regions 15 may be the a-axis direction (second direction Y), and the second extension direction De2 of the second regions 15 may be the m-axis direction (first direction X). In this case, the second arrangement direction Da2 coincides with the first extension direction De1 and is orthogonal to the first arrangement direction Da1. Furthermore, the second extension direction De2 coincides with the first arrangement direction Da1 and is orthogonal to the first extension direction De1.

[0109] In this case, since the second extension direction De2 intersects (specifically, is perpendicular to) the off-direction Doff of the second layer 9, the multiple second regions 15 are inclined by approximately the off-angle θoff from the vertical axis toward the off-direction Doff in a cross-sectional view seen from the m-plane of the SiC single crystal.

[0110] 8B , the second regions 15 may intersect the first regions 14 non-orthogonally in a planar view. That is, the second arrangement direction Da2 of the second regions 15 may be a direction other than the a-axis direction and the m-axis direction, and the second extension direction De2 of the second regions 15 may be a direction other than the a-axis direction and the m-axis direction. In this case, the second arrangement direction Da2 intersects both the first arrangement direction Da1 and the first extension direction De1, and the second extension direction De2 intersects both the first arrangement direction Da1 and the first extension direction De1. Furthermore, the second extension direction De2 intersects the off-direction Doff of the second layer 9.

[0111] The second extension direction De2 may be inclined from the a-axis toward one side (left side of the paper) or the other side (right side of the paper) of the m-axis in a plan view. When the a-axis is taken as a reference (0°), the second regions 15 have the second extension direction De2 that forms an extension angle θa with the a-axis.

[0112] The absolute value of the extension angle θa may be greater than 0° and less than 90°. The extension angle θa may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° or greater and less than 36°, 36° or greater and less than 54°, 54° or greater and less than 72°, and 72° or greater and less than 90°. The absolute value of the extension angle θa is typically set to a value belonging to any one of the ranges of 30°±5°, 45°±5°, and 60°±5°.

[0113] The column region 12 may have the configurations shown in FIGS. 9, 10A, 10B, and 10C. FIG. 9 is a cross-sectional perspective view showing a third basic configuration of the column region 12. FIGS. 10A, 10B, and 10C are plan views showing first, second, and third layout examples of the column region 12 according to the third basic configuration. In FIGS. 10A to 10C, the first region 14 is indicated by a dashed line, and the second region 15 is indicated by hatching.

[0114] 9 and 10A to 10C, the first arrangement direction Da1 of the first regions 14 may be a direction other than the a-axis direction (second direction Y) and the m-axis direction (first direction X), and the first extension direction De1 of the first regions 14 may be a direction other than the a-axis direction and the m-axis direction. In other words, the multiple first regions 14 may intersect both the a-axis direction and the m-axis direction. 10A to 10C show an example in which the first regions 14 are tilted toward one side of the m-axis (the left side of the paper) with respect to the a-axis.

[0115] In this case, since the first extension direction De1 intersects with the off direction Doff, the multiple first regions 14 are inclined from the vertical axis toward the off direction Doff by approximately the off angle θoff in a cross-sectional view seen from the a-plane of the SiC single crystal and in a cross-sectional view seen from the m-plane of the SiC single crystal.

[0116] The first extension direction De1 forms a first extension angle θ1 with the a-axis when the a-axis is set as a reference (0°). The absolute value of the first extension angle θ1 may be greater than 0° and less than 90°. The first extension angle θ1 may have a value belonging to any one of the following ranges: greater than 0° and less than 18°, 18° or greater but less than 36°, 36° or greater but less than 54°, 54° or greater but less than 72°, and 72° or greater but less than 90°.

[0117] The absolute value of the first extension angle θ1 is typically set to a value belonging to any one of the ranges of 30°±5°, 45°±5°, and 60°±5°. Fig. 10A shows a layout example in which the absolute value of the first extension angle θ1 is approximately 45°, Fig. 10B shows a layout example in which the absolute value of the first extension angle θ1 is approximately 30°, and Fig. 10C shows a layout example in which the absolute value of the first extension angle θ1 is approximately 60°.

[0118] 9 and 10A to 10C, the first arrangement direction Da1 of the second regions 15 may be a direction other than the a-axis direction (second direction Y) and the m-axis direction (first direction X), and the first extension direction De1 of the second regions 15 may be a direction other than the a-axis direction and the m-axis direction. In other words, the second regions 15 may intersect with both the a-axis direction and the m-axis direction. In this example, the second regions 15 are inclined toward the other side of the m-axis (the right side of the paper) with respect to the a-axis.

[0119] In this case, since the second extension direction De2 intersects with the off direction Doff, the multiple second regions 15 are inclined from the vertical axis toward the off direction Doff by approximately the off angle θoff in a cross-sectional view from the a-plane and a cross-sectional view from the m-plane of the SiC single crystal.

[0120] When the a-axis is set as a reference (0°), the second extension direction De2 forms a second extension angle θ2 with the a-axis. When the first extension angle θ1 is defined as a "positive value," the second extension angle θ2 is a "negative value." On the other hand, when the first extension angle θ1 is defined as a "negative value," the second extension angle θ2 is a "positive value."

[0121] The absolute value of the second extension angle θ2 may be greater than 0° and less than 90°. The second extension angle θ2 may have a value that belongs to any one of the ranges of greater than 0° and less than 18°, 18° or more and less than 36°, 36° or more and less than 54°, 54° or more and less than 72°, and 72° or more and less than 90°.

[0122] The absolute value of the second extension angle θ2 is typically set to a value belonging to any one of the ranges of 30°±5°, 45°±5°, and 60°±5°. The absolute value of the second extension angle θ2 is preferably approximately equal to the absolute value of the first extension angle θ1. In other words, the second regions 15 preferably have a layout that is approximately line-symmetric with the first regions 14 about the a-axis in a plan view per unit area (i.e., a partial plan view). In other words, the second regions 15 preferably have a layout that is approximately point-symmetric with the first regions 14 about the vertical axis in a plan view per unit area (i.e., a partial plan view).

[0123] FIG. 10A shows a layout example in which the absolute value of the second extension angle θ2 is approximately 45° (≒θ1), FIG. 10B shows a layout example in which the absolute value of the second extension angle θ2 is approximately 30° (≒θ1), and FIG. 10C shows a layout example in which the absolute value of the second extension angle θ2 is approximately 60° (≒θ1).

[0124] 10A , the second regions 15 extend in a direction intersecting both the a-axis direction and the m-axis direction, and are perpendicular to the first regions 14. The sum of the absolute value of the first extension angle θ1 and the absolute value of the second extension angle θ2 is approximately a right angle (approximately 90°).

[0125] 10B , the second regions 15 extend in a direction intersecting both the a-axis direction and the m-axis direction and intersect non-orthogonally with the first regions 14. The sum of the absolute value of the first extension angle θ1 and the absolute value of the second extension angle θ2 is an acute angle (approximately 60°). In the layout example of FIG. 10C , the second regions 15 extend in a direction intersecting both the a-axis direction and the m-axis direction and intersect non-orthogonally with the first regions 14. The sum of the absolute value of the first extension angle θ1 and the absolute value of the second extension angle θ2 is an obtuse angle (approximately 120°).

[0126] Of course, the absolute value of the second extension angle θ2 may be greater than or less than the absolute value of the first extension angle θ1. That is, the second regions 15 may have a layout that is asymmetrical with the first regions 14 about the a-axis in a plan view per unit area (i.e., a partial plan view). In other words, the second regions 15 may have a layout that is asymmetrical with the first regions 14 about the vertical axis in a plan view per unit area (i.e., a partial plan view).

[0127] The following specifically describes the concentration gradient of the p-type impurity concentration in the first region 14 and the concentration gradient of the p-type impurity concentration in the second region 15. Since the concentration gradient of the first region 14 and the concentration gradient of the second region 15 are almost the same, the concentration gradient of the second region 15 will be exemplified below.

[0128] The concentration gradient of the first region 14 can be explained by replacing "the first layer 8" with "the base layer 6," "the second layer 9" with "the first layer 8," "the second region 15 (the second lower end 15a and the second upper end 15b)" with "the first region 14 (the first lower end 14a and the first upper end 14b)," and "the second axial channel CH2" with "the first axial channel CH1" as necessary in the following description. In other words, the relative or absolute positional relationship of the second region 15 with respect to the first layer 8 and the second layer 9 applies mutatis mutandis to the relative or absolute positional relationship of the first region 14 with respect to the base layer 6 and the first layer 8.

[0129] 11A to 11E are graphs showing an example of the concentration gradient in the second region 15 (first region 14). Fig. 12 is a graph showing a comparative example of the concentration gradient in the second region 15 (first region 14). In Figs. 11 and 12, the vertical axis represents the p-type impurity concentration in the second region 15, and the horizontal axis represents the depth along the second axial channel CH2, with the upper end (first main surface 3) of the second layer 9 as the reference (zero point).

[0130] 11A to 11E and 12, 1×10 １５ cm －３A region having the above p-type impurity concentration is defined as second region 15 and is illustrated as a graph. The values ​​of impurity concentration, thickness, etc. shown below are examples for explaining the basic configuration of second region 15 based on the concentration gradient, and are not intended to uniquely limit the configuration of second region 15. The impurity concentration, thickness, etc. are adjusted to various values ​​depending on the implantation conditions of the trivalent element (dose amount, implantation temperature, implantation energy, etc.).

[0131] 11A to 11E are graphs showing the case where second region 15 is formed by channeling implantation. Each of FIGS. 11A to 11E shows the concentration gradient of second region 15 when a predetermined trivalent element (here, aluminum) is introduced into second layer 9 parallel or nearly parallel to second axial channel CH2 with implantation energies of 190 KeV (FIG. 11A), 380 KeV (FIG. 11B), 650 KeV (FIG. 11C), 960 KeV (FIG. 11D), or 2000 KeV (FIG. 11E). Second thickness T2 of second layer 9 is about 3 μm, and the dose of the trivalent element is 1×10 １３ cm －２ is.

[0132] On the other hand, Fig. 12 is a graph showing the case where the second region 15 is formed by the random implantation method. Fig. 12 shows the concentration gradient of the second region 15 when a predetermined trivalent element (here, aluminum) is introduced into the second layer 9 in a random direction by implantation energies of 190 KeV, 380 KeV, 650 KeV, 960 KeV, or 2000 KeV. The random direction is a direction (for example, the vertical direction Z) that is not parallel (or substantially parallel) to the second axial channel CH2. The second thickness T2 of the second layer 9 is about 3 µm, and the dose of the trivalent element is 1 × 10 １３ cm －２ is.

[0133] 11A , second region 15 (190 KeV) has a second region thickness TR2 of 1.5 μm or more and 1.8 μm or less, and has second lower end 15a spaced from the lower end toward the upper end of second layer 9, and second upper end 15b exposed from the upper end (first main surface 3) of second layer 9. The distance between the lower end of second layer 9 and second lower end 15a is 1.2 μm or more and 1.5 μm or less.

[0134] The p-type impurity concentration of second region 15 has a concentration gradient that extends from the upper end to the lower end of second layer 9, and includes a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23. Gradually increasing portion 20 forms second upper end 15b of second region 15, and is a portion where the p-type impurity concentration gradually increases from second upper end 15b toward the lower end of second layer 9 to peak portion 21 at a relatively steep rate of increase.

[0135] The peak portion 21 is a portion having a peak value P (maximum value) of the p-type impurity concentration. The peak portion 21 is also a convex main concentration transition portion including a series of concentration changes (inflection points) where the p-type impurity concentration changes from an increase (increasing trend) to a decrease (decreasing trend). The depth position of the peak portion 21 is 0.1 μm or more and 0.5 μm or less.

[0136] The gradual portion 22 is formed in a region closer to the second lower end 15a than the peak portion 21, and is a portion where the impurity concentration gradually decreases at a relatively gradual rate. In other words, the gradual portion 22 is a portion where a constant p-type impurity concentration is maintained within a certain depth range, and forms the main body of the second region 15. The p-type impurity concentration of the gradual portion 22 gradually decreases within a concentration range that is less than the p-type impurity concentration of the peak portion 21.

[0137] The gradual portion 22 is defined as a portion having a concentration decrease rate of 50% or less in a thickness range of at least 0.5 μm. In this example, the gradual portion 22 has a thickness of 0.7 μm or more and 0.8 μm or less, and has a concentration decrease rate of 50% or less in this thickness range. In this example, the p-type impurity concentration of the gradual portion 22 is 4.5×10 １６ cm －３ 9 x 10 or more １６ cm －３ The concentration range is as follows:

[0138] The gradually decreasing portion 23 is a portion that forms the second lower end 15a of the second region 15. The gradually decreasing portion 23 has a concentration decrease rate that is greater than that of the gradual portion 22, and is a portion where the p-type impurity concentration gradually decreases from the gradual portion 22 toward the lower end of the second layer 9. The concentration decrease rate per unit thickness of the gradually decreasing portion 23 is greater than the concentration decrease rate per unit thickness of the gradual portion 22. The p-type impurity concentration of the gradually decreasing portion 23 decreases from the gradual portion 22 by 1×10 １５cm －３ It is gradually decreasing to.

[0139] 11B , second region 15 (380 KeV) has a second region thickness TR2 of 2.2 μm or more and 2.4 μm or less, and has a second lower end 15a spaced from the lower end of second layer 9 toward the upper end, and a second upper end 15b spaced from the upper end (first main surface 3) of second layer 9 toward the lower end (first layer 8 side). The distance between the lower end of second layer 9 and second lower end 15a is 0.5 μm or more and 0.8 μm or less. The distance between the upper end of second layer 9 and second upper end 15b of second region 15 is 0.01 μm or more and 0.2 μm or less.

[0140] 11A , the p-type impurity concentration of second region 15 has a concentration gradient that includes a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23 from the upper end to the lower end of second layer 9. In this example, gradually increasing portion 20 also increases gradually from second upper end 15b toward the lower end of second layer 9 to peak portion 21 at a relatively steep rate of increase. The depth position of peak portion 21 is 0.3 μm or more and 0.7 μm or less.

[0141] The gradual portion 22 has a thickness of 0.8 μm or more and 1.1 μm or less, and the concentration reduction rate within this thickness range is 50% or less. In this example, the p-type impurity concentration of the gradual portion 22 is 3.5×10 １６ cm －３ 7 x 10 or more １６ cm －３ The p-type impurity concentration of the gradually decreasing portion 23 is 1×10 １５ cm －３ It is gradually decreasing to.

[0142] 11C , second region 15 (650 KeV) has a second region thickness TR2 of 2.5 μm or more and 2.8 μm or less, and has a second lower end 15a spaced from the lower end of second layer 9 toward the upper end, and a second upper end 15b spaced from the upper end (first main surface 3) of second layer 9 toward the lower end (first layer 8 side). The distance between the lower end of second layer 9 and second lower end 15a is 0.01 μm or more and 0.1 μm or less. The distance between the upper end of second layer 9 and second upper end 15b of second region 15 is 0.1 μm or more and 0.4 μm or less.

[0143] 11A , the p-type impurity concentration of second region 15 has a concentration gradient from second upper end 15b to second lower end 15a, including a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23. In this example, gradually increasing portion 20 also increases gradually from second upper end 15b of second region 15 to peak portion 21 at a relatively steep rate of increase. The depth position of peak portion 21 is 0.6 μm or more and 1 μm or less.

[0144] The gradual portion 22 has a thickness of 1 μm or more and 1.3 μm or less, and the concentration reduction rate within this thickness range is 50% or less. In this example, the p-type impurity concentration of the gradual portion 22 is 3×10 １６ cm －３ 6 x 10 or more １６ cm －３ The p-type impurity concentration of the gradually decreasing portion 23 is 1×10 １５ cm －３ It is gradually decreasing to.

[0145] 11D , second region 15 (960 KeV) has a second region thickness TR2 of 3.1 μm or more and 3.3 μm or less, and has a second upper end 15b spaced from the upper end (first main surface 3) of second layer 9 toward the lower end (first layer 8 side) and a second lower end 15a located within first layer 8. In other words, second region 15 has a second region thickness TR2 that is larger than the second thickness T2 (=3 μm) of second layer 9.

[0146] Second lower end 15a has an extension that crosses the boundary between first layer 8 and second layer 9 and extends into first layer 8. The extension of second lower end 15a has a thickness of 0.4 μm or more and 0.7 μm or less from the upper end of first layer 8. The distance between the upper end of second layer 9 and second upper end 15b of second region 15 is 0.3 μm or more and 0.6 μm or less.

[0147] 11A , the p-type impurity concentration of second region 15 has a concentration gradient from second upper end 15b to second lower end 15a, including a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23. In this example, gradually increasing portion 20 also increases gradually from second upper end 15b of second region 15 to peak portion 21 at a relatively steep rate of increase. The depth position of peak portion 21 is 0.7 μm or more and 1.3 μm or less.

[0148] The gradual portion 22 has a thickness of 1.3 μm or more and 1.7 μm or less, and the concentration reduction rate within this thickness range is 50% or less. In this example, the p-type impurity concentration of the gradual portion 22 is 2.2×10 １６ cm －３ 4.5 x 10 １６ cm －３ The p-type impurity concentration of the gradually decreasing portion 23 is 1×10 １５ cm －３ It is gradually decreasing to.

[0149] 11E , second region 15 (2000 KeV) has a second region thickness TR2 of 3.5 μm or more and 3.8 μm or less, and has a second upper end 15b spaced from the upper end (first main surface 3) of second layer 9 toward the lower end (first layer 8 side) and a second lower end 15a located within first layer 8. In other words, second region 15 has a second region thickness TR2 that is larger than second thickness T2 (=3 μm) of second layer 9.

[0150] Second lower end 15a has an extension that crosses the boundary between first layer 8 and second layer 9 and extends into first layer 8. The extension of second lower end 15a has a thickness of 1.4 μm or more and 1.8 μm or less from the upper end of first layer 8. The distance between the upper end of second layer 9 and second upper end 15b of second region 15 is 0.7 μm or more and 1 μm or less.

[0151] 11A , the p-type impurity concentration of second region 15 has a concentration gradient from second upper end 15b to second lower end 15a, including a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23. In this example, gradually increasing portion 20 also increases gradually from second upper end 15b of second region 15 to peak portion 21 at a relatively steep rate of increase. The depth position of peak portion 21 is 1.3 μm or more and 1.9 μm or less.

[0152] The gradual portion 22 has a thickness of 1.5 μm or more and 1.8 μm or less, and has a concentration decrease rate of 50% or less within this thickness range. In this example, the gradual portion 22 crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8. In other words, the extension of the second region 15 includes a part of the gradual portion 22. In this example, the p-type impurity concentration of the gradual portion 22 is 2×10 １６ cm －３ 4 x 10 or more １６ cm －３ The p-type impurity concentration of the gradually decreasing portion 23 is 1×10 １５ cm －３ It is gradually decreasing to.

[0153] 11A to 11E, the p-type impurity concentration of second region 15 has a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23 at any implantation energy. Furthermore, second region thickness TR2 (depth) of second region 15 increases with increasing implantation energy. Furthermore, the depth position of second upper end 15b of second region 15 relative to the upper end of second layer 9 increases with increasing implantation energy.

[0154] The thicknesses of the gradually increasing portion 20, the peak portion 21, the gradual portion 22, and the gradually decreasing portion 23 all increase with increasing implantation energy. On the other hand, the peak value P of the second region 15 decreases with increasing implantation energy. This is because the trivalent element is introduced deeper into the region as the implantation energy increases, increasing the p-type impurity concentration in the deep region.

[0155] The gradual portion 22 occupies a thickness range of at least ¼ of the second region 15 (second region thickness TR2) and is located within the second layer 9. Specifically, the proportion of the gradual portion 22 in the second region 15 is at least ⅓. The proportion of the gradual portion 22 in the second region 15 is typically at most ½ (less than ½). The proportion of the gradual portion 22 in the second region 15 may be at least ½.

[0156] 12 , in the case of the random implantation method, second region 15 had a gradually increasing portion 20, a peak portion 21 (peak value P), and a gradually decreasing portion 23 within a range of 0.5 μm, but did not have a gradual portion 22 having a thickness of 0.5 μm or more. Furthermore, in the case of the random implantation method, the depth position of peak portion 21 (peak value P) relative to the upper end of second layer 9 increased with increasing implantation energy, but second region thickness TR2 of second region 15 was less than 2 μm at any implantation energy. In other words, even when the implantation energy was increased, second region thickness TR2 did not fluctuate significantly.

[0157] From this, it can be understood that in the case of the random implantation method, it is difficult to improve the accuracy of the charge balance by using second region 15 consisting of a single impurity region for second layer 9 having a relatively large second thickness T2 (for example, second thickness T2 of 1 μm or more). Unlike Si single crystal, SiC single crystal has physical properties that make it difficult for impurities to diffuse. Therefore, the above problem is generally solved by using a multi-epitaxial growth method or a multi-stage random implantation method.

[0158] In the multi-epitaxial growth method, a step of introducing a trivalent element into an epitaxial layer having a relatively small thickness (for example, a thickness of less than 1 μm) by random implantation is repeated multiple times, which increases the number of epitaxial growth steps and random implantation steps, making the manufacturing process more complicated.

[0159] In the multi-stage random implantation method, a process is performed in which a trivalent element is introduced into different depth positions in multiple stages using multiple implantation energies. For example, in the example of FIG. 12, when a 1 μm second layer 9 is formed, the trivalent element is introduced into the second layer 9 using five implantation energies (190 keV, 380 keV, 650 keV, and 960 keV). In this process, the trivalent element can be introduced into the target depth position, but the depth position at which the trivalent element can be introduced is shallow. Therefore, the number of epitaxial growth steps and the number of random implantation steps must be increased, resulting in the same problems as in the multi-epitaxial growth method.

[0160] In contrast, in the case of channeling implantation, second region 15 having gentle portion 22 with a thickness of 0.5 μm to 2 μm is formed in second layer 9 having a relatively large thickness (for example, a thickness of 1 μm to 5 μm). Therefore, second region 15 having charge balance is formed with fewer steps than the steps required when random implantation is employed.

[0161] Of course, this specification does not exclude the technical idea of ​​introducing multiple second regions 15 in multiple stages at different depth positions by a channeling implantation method using multiple implantation energies to form one second region 15. In this case, each second region 15 is made up of an integrated region of multiple impurity regions (second regions 15) formed in the second layer 9 along the second axial channel CH2 so as to cross the middle portion of the second layer 9.

[0162] In this case, the p-type impurity concentration (concentration gradient) of each second region 15 is the sum of the p-type impurity concentrations (concentration gradients) of the multiple impurity regions (second regions 15). For example, the p-type impurity concentration of each second region 15 has a concentration gradient (sum of concentration gradients) obtained by superimposing at least two of the five graphs shown in Figures 11A to 11E.

[0163] 11A to 11E, the upper limit of the implantation energy of the channeling implantation method is 2000 KeV, but the second region 15 can also be formed by implantation energy greater than 2000 KeV. In this case, a relatively thick second region 15 is formed at a position deeper than the concentration gradient shown in FIG.

[0164] However, when an implantation energy greater than 2000 KeV is realized, the amount of trivalent elements passing through the upper end of the second layer 9 increases, and the range of the free space on the upper end side (i.e., the distance between the first main surface 3 and the second region 15) expands, which increases the difficulty of designing the column region 12. Furthermore, when an implantation energy greater than 2000 KeV is realized, the size of the ion accelerator may reach several tens of meters, which is considered to be unrealistic from the standpoint of cost-effectiveness (installation location and capital investment).

[0165] Therefore, when forming a relatively thick column region 12 by channeling implantation, it is preferable to limit the implantation energy to 2000 KeV or less and increase the number of layers in the stacked portion 7 (the number of layers in the superjunction structure SJ).

[0166] 13 to 33, first to twelfth embodiment examples of the column region 12 are shown below. The column region 12 according to the first to third basic embodiments may have at least one of the plurality of features shown in the first to twelfth embodiment examples. The column region 12 according to the first to third basic embodiments may have a feature that combines a plurality (two or more) of the features shown in the first to twelfth embodiment examples.

[0167] Hereinafter, the "gradual increase portion 20," "peak portion 21 (peak value P)," "slow portion 22," and "gradual decrease portion 23" of the first region 14 will be referred to as the "first gradual increase portion 20A," "first peak portion 21A (first peak value PA)," "first gradual decrease portion 22A," and "first gradual decrease portion 23A." Also, below, the "gradual increase portion 20," "peak portion 21 (peak value P)," "slow portion 22," and "gradual decrease portion 23" of the second region 15 will be referred to as the "second gradual increase portion 20B," "second peak portion 21B (second peak value PB)," "second gradual decrease portion 22B," and "second gradual decrease portion 23B."

[0168] Fig. 13 is a cross-sectional perspective view showing the column region 12 according to the first embodiment, and Fig. 14 is a graph showing an example of the concentration gradient of the column region 12 shown in Fig. 13 .

[0169] 13 and 14 , first region 14 has a first region thickness TR1 that is less than first thickness T1 of first layer 8, and is formed in first layer 8 at a distance from both the lower end and the upper end of first layer 8. Specifically, first lower end 14a of first region 14 is formed at a distance from the lower end (base layer 6) of first layer 8 toward the upper end, and faces base layer 6 with a part (lower end) of first layer 8 in between.

[0170] On the other hand, the first upper end 14b of the first region 14 is formed at a distance from the upper end (second layer 9) of the first layer 8 toward the lower end, and faces the second layer 9 across a part (upper end) of the first layer 8. The first gradually increasing portion 20A, the first peak portion 21A, the first gradual portion 22A, and the first gradually decreasing portion 23A of the first region 14 are located within the first layer 8.

[0171] 14 shows an example in which the first layer 8 has a first thickness T1 of 3 μm and the first region 14 is formed in the first layer 8 by implantation energy of 650 KeV. Of course, the first region 14 may be formed by implantation energy of 650 KeV or less.

[0172] The second region 15 has a second region thickness TR2 that is less than the second thickness T2 of the second layer 9, and is formed within the second layer 9 at a distance from both the lower end and the upper end of the second layer 9. Specifically, the second lower end 15a of the second region 15 is formed at a distance from the lower end (first layer 8) of the second layer 9 toward the upper end, and faces the first layer 8 with a part (lower end) of the second layer 9 in between.

[0173] On the other hand, second upper end 15b of second region 15 is formed at a distance from the upper end (first principal surface 3) of second layer 9 toward the lower end, and faces first principal surface 3 across a part (upper end) of second layer 9. Second gradually increasing portion 20B, second peak portion 21B, second gradual portion 22B, and second gradually decreasing portion 23B of second region 15 are located within second layer 9.

[0174] 14 shows an example in which the second layer 9 has a second thickness T2 of 3 μm and the second region 15 is formed in the second layer 9 by implantation energy of 650 KeV. Of course, the second region 15 may be formed by implantation energy of 650 KeV or less. Furthermore, the implantation energy for the second region 15 may be different from the implantation energy for the first region 14.

[0175] That is, the second region thickness TR2 of the second region 15 may be different from the first region thickness TR1 of the first region 14. The second region thickness TR2 may be less than the first region thickness TR1 or may be greater than the first region thickness TR1.

[0176] Fig. 15 is a cross-sectional perspective view showing the column region 12 according to the second embodiment. Fig. 16 is a graph showing an example of the concentration gradient of the column region 12 shown in Fig. 15. With reference to Figs. 15 and 16, the column region 12 according to the second embodiment has a modified form of the second region 15 according to the first embodiment. The form of the first region 14 according to the second embodiment is similar to that of the first region 14 according to the first embodiment.

[0177] The second region 15 is formed in the second layer 9 at a distance from the upper end to the lower end of the second layer 9, and has a portion that crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8. In other words, the second lower end 15a of the second region 15 has an extending portion that crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8.

[0178] Because the second axial channel CH2 is substantially aligned with the first axial channel CH1, the extension of the second lower end 15a is formed along the first axial channel CH1 in the first layer 8. The extension of the second lower end 15a is preferably positioned closer to the upper end of the first layer 8 than the intermediate portion of the thickness range of the first layer 8. The extension of the second lower end 15a is connected to the first region 14 (first upper end 14b) in the first layer 8.

[0179] In this configuration, a part (extension) of the second region 15 is provided in the space between the upper end of the first layer 8 and the first upper end 14 b of the first region 14, and the first region 14 and the second region 15 form one column region 12 that extends continuously in a three-dimensional lattice pattern. This improves the accuracy of charge balance.

[0180] In this example, the second region 15 has a second region thickness TR2 that is greater than the second thickness T2 of the second layer 9. The second region thickness TR2 is also greater than the first thickness T1 of the first layer 8. The second region thickness TR2 is also greater than the first region thickness TR1 of the first region 14. Of course, the second region thickness TR2 may be less than the second thickness T2. The second region thickness TR2 may also be less than the first region thickness TR1. The second region thickness TR2 may also be less than the first region thickness TR1.

[0181] The second gradually increasing portion 20B, the second peak portion 21B, the second gradual portion 22B, and the second gradually decreasing portion 23B of the second region 15 are located in the second layer 9. At least a portion of the second gradually decreasing portion 23B is located in the first layer 8. That is, the extension of the second lower end portion 15a includes the second gradually decreasing portion 23B. Of course, a portion of the second gradual decreasing portion 22B may be located in the first layer 8 (see FIG. 11E ). That is, the extension of the second lower end portion 15a may include a portion of the second gradual decreasing portion 22B and the second gradual decreasing portion 23B.

[0182] 16 shows an example in which the second layer 9 has a first thickness T1 of 3 μm, and the second region 15 is formed in the second layer 9 by implantation energy of 960 KeV. Of course, the second region 15 may be formed by implantation energy of 960 KeV or more. For example, the second thickness T2 may be greater than 3 μm and less than or equal to 5 μm. In this case, the second region 15 connected to the first region 14 is formed in the first layer 8 by implantation energy of 960 KeV or more (see also FIGS. 11F to 11E).

[0183] Fig. 17 is a cross-sectional perspective view showing the column region 12 according to the third embodiment. Fig. 18 is a graph showing an example of the concentration gradient of the column region 12 shown in Fig. 17. With reference to Figs. 17 and 18, the column region 12 according to the third embodiment has a modified form of the second region 15 according to the second embodiment. The first region 14 according to the third embodiment has a form similar to that of the first region 14 according to the first embodiment.

[0184] The second region 15 according to the second embodiment is formed in the second layer 9 having a second thickness T2 that is approximately equal to the first thickness T1 of the first layer 8. In contrast, the second region 15 according to the third embodiment is formed in the second layer 9 having a second thickness T2 that is less than the first thickness T1 of the first layer 8. In this example, the second region 15 has a second region thickness TR2 that is greater than the second thickness T2 of the second layer 9.

[0185] 17 shows an example in which the second layer 9 has a second thickness T2 of less than 3 μm (here, 2 μm), and the second region 15 is formed in the second layer 9 by implantation energy of 650 KeV. Of course, the second region 15 may also be formed by implantation energy of 650 KeV or less.

[0186] For example, the second thickness T2 may be equal to or greater than 1 μm and equal to or less than 2 μm. In this case, the second region 15 connected to the first region 14 is formed in the first layer 8 by implantation energy of 190 KeV or more (see also FIGS. 11A to 11E). For example, the second thickness T2 may be equal to or greater than 2 μm and less than 3 μm. In this case, the second region 15 connected to the first region 14 is formed in the first layer 8 by implantation energy of 380 KeV or more (see also FIGS. 11B to 11E).

[0187] In this configuration, the concentration gradient formed at the connection between the first region 14 and the second region 15 is alleviated, improving the accuracy of charge balance. Furthermore, since the second layer 9 has a relatively small second thickness T2, the second region 15 connected to the first region 14 can be formed with a relatively small implantation energy. Therefore, manufacturing costs are reduced.

[0188] For example, a relatively small second thickness T2 may allow the first region thickness TR1 (implantation energy) of the first region 14 and the second region thickness TR2 (implantation energy) of the second region 15 to be set to the same value, while forming the second region 15 in the first layer 8, which is connected to the first region 14. This facilitates process control of the manufacturing process. In these cases, the second thickness T2 of the second layer 9 may be set to be less than the first thickness T1 of the first layer 8, and the second region 15 may be formed having a second region thickness TR2 greater than the second thickness T2.

[0189] Fig. 19 is a cross-sectional perspective view showing the column region 12 according to the fourth embodiment. Fig. 20 is a graph showing an example of the concentration gradient of the column region 12 shown in Fig. 19. With reference to Figs. 19 and 20, the column region 12 according to the fourth embodiment has a configuration obtained by modifying the first region 14 according to the second embodiment. The second region 15 according to the fourth embodiment has a configuration similar to that of the second region 15 according to the second embodiment. Of course, the second region 15 according to the fourth embodiment may have a configuration similar to that of the second region 15 according to the third embodiment.

[0190] The first region 14 is formed in the first layer 8 at a distance from the upper end to the lower end of the first layer 8, and has a portion that crosses the boundary between the base layer 6 and the first layer 8 and is located within the base layer 6. In other words, the first lower end 14a of the first region 14 has an extending portion that crosses the boundary between the base layer 6 and the first layer 8 and is located within the base layer 6.

[0191] Since the first axial channel CH1 substantially coincides with the base axial channel CHB, the extension of the first lower end 14a is formed along the base axial channel CHB within the base layer 6. The extension of the first lower end 14a is preferably located on the upper end side of the base layer 6 relative to the intermediate portion of the thickness range of the base layer 6. The extension of the first lower end 14a is connected to the base layer 6 within the base layer 6.

[0192] In this example, the first region 14 has a first region thickness TR1 that is greater than the first thickness T1 of the first layer 8. The first region thickness TR1 is also greater than the second thickness T2 of the second layer 9. The first region thickness TR1 is also greater than the second region thickness TR2 of the second region 15. Of course, the first region thickness TR1 may be less than the first thickness T1. The first region thickness TR1 may be less than the second thickness T2. The first region thickness TR1 may be less than the second region thickness TR2.

[0193] The first gradually increasing portion 20A, the first peak portion 21A, the first gradual portion 22A, and the first gradually decreasing portion 23A of the first region 14 are located in the first layer 8. At least a portion of the first gradually decreasing portion 23A is located in the base layer 6. That is, the extension of the first lower end portion 14a includes the first gradually decreasing portion 23A. Of course, a portion of the first gradual decreasing portion 22A may be located in the base layer 6 (see FIG. 11E ). That is, the extension of the first lower end portion 14a may include a portion of the first gradual decreasing portion 22A and the first gradual decreasing portion 23A.

[0194] 20 shows an example in which the first layer 8 has a first thickness T1 of 3 μm, and the first region 14 is formed in the first layer 8 by implantation energy of 960 KeV. Of course, the first region 14 may also be formed by implantation energy of 960 KeV or higher. For example, the first thickness T1 may be greater than 3 μm and less than or equal to 5 μm. In this case, the first region 14 is formed partially within the base layer 6 by implantation energy of 960 KeV or higher (see also FIGS. 11F to 11E).

[0195] Fig. 21 is a cross-sectional perspective view showing the column region 12 according to the fifth embodiment. Fig. 22 is a graph showing an example of the concentration gradient of the column region 12 shown in Fig. 21. With reference to Figs. 21 and 22, the column region 12 according to the fifth embodiment has a configuration obtained by modifying the first region 14 according to the fourth embodiment. The second region 15 according to the fifth embodiment has a configuration similar to that of the second region 15 according to the second embodiment. Of course, the second region 15 according to the fifth embodiment may also have a configuration similar to that of the second region 15 according to the third embodiment.

[0196] In the fourth embodiment, the first layer 8 has a first thickness T1 of 3 μm, and the first region 14 is formed in the first layer 8 by implantation energy of 960 KeV or greater. In contrast, in the fifth embodiment, the first layer 8 has a first thickness T1 of less than 3 μm, and the first region 14 is formed in the first layer 8 by implantation energy of 650 KeV or greater. The first region 14 has a first region thickness TR1 that is greater than the first thickness T1 in this example. The first thickness T1 is less than the second thickness T2 of the second layer 9 in this example.

[0197] For example, first thickness T1 may be 1 μm or more and 2 μm or less. In this case, first region 14 located partially within base layer 6 is formed by implantation energy of 190 KeV or more (see also FIGS. 11A to 11E). For example, first thickness T1 may be 2 μm or more and less than 3 μm. In this case, first region 14 located partially within base layer 6 is formed by implantation energy of 380 KeV or more (see also FIGS. 11B to 11E).

[0198] Fig. 23 is a cross-sectional perspective view showing the column region 12 according to the sixth embodiment. Fig. 24 is a graph showing an example of the concentration gradient of the column region 12 shown in Fig. 23. Referring to Figs. 23 and 24, the column region 12 includes a first region 14 and a second region 15, as well as a p-type intermediate region 25 interposed between the first region 14 and the second region 15.

[0199] The first region 14 may have a form similar to any one of the forms of the first region 14 according to the first to fifth embodiments. In this example, the first region 14 has a form similar to the form of the first region 14 according to the fourth embodiment. The second region 15 may have a form similar to any one of the forms of the second region 15 according to the first to fifth embodiments. In this example, the second region 15 has a form similar to the form of the second region 15 according to the fourth embodiment (second embodiment).

[0200] The plurality of intermediate regions 25 are formed in the surface layer portion on the upper end side of the first layer 8 so as to be positioned at least at a plurality of intersections between the plurality of first regions 14 and the plurality of second regions 15, and overlap the corresponding first regions 14 and second regions 15 in the stacking direction. In this embodiment, the plurality of intermediate regions 25 are arranged at intervals in the first arrangement direction Da1 so as to overlap the plurality of first regions 14 in a one-to-one correspondence in the stacking direction, and are each formed in a strip shape extending in the first extension direction De1.

[0201] In this example, the first arrangement direction Da1 is the a-axis direction (second direction Y), and the first extension direction De1 is the m-axis direction (first direction X). Of course, the arrangement direction and extension direction of the multiple intermediate regions 25 are changed depending on the first arrangement direction Da1 and first extension direction De1 of the multiple first regions 14. Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Alternatively, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.

[0202] The multiple intermediate regions 25 are formed in the first layer 8 in a region between the upper end of the first layer 8 and the first upper end 14b of the first region 14. The multiple intermediate regions 25 are preferably located closer to the upper end of the first layer 8 than the middle portion of the thickness range of the first layer 8. The multiple intermediate regions 25 may be exposed from the upper end of the first layer 8, or may be formed at intervals from the upper end to the lower end of the first layer 8. Each intermediate region 25 may be formed in the shape of a horizontally elongated column extending horizontally in a cross-sectional view. Of course, each intermediate region 25 may also be formed in the shape of a vertically elongated column extending in the vertical direction Z.

[0203] The multiple intermediate regions 25 form multiple intermediate pn junctions having charge balance together with the first layer 8. That is, the multiple intermediate regions 25 constitute a part of the first superjunction structure SJ1 together with the multiple first drift regions 16. The state of having charge balance means that, with respect to the multiple intermediate regions 25 adjacent to each other, the depletion layer extending from one intermediate pn junction and the depletion layer extending from the other intermediate pn junction are connected within the multiple first drift regions 16.

[0204] 24 , each intermediate region 25 may include a single region element 25 a or multiple region elements 25 a. An example in which each intermediate region 25 includes multiple (two) region elements 25 a is shown in FIG. 24 . When each intermediate region 25 is configured with a single region element 25 a, the single region element 25 a is formed in the region between the upper end of the first layer 8 and the first upper end 14 b of the first region 14, and is connected to the first upper end 14 b of the first region 14.

[0205] When each intermediate region 25 is composed of multiple region elements 25a, the multiple region elements 25a are formed at different depth positions in the region between the upper end of the first layer 8 and the first upper end 14b of the first region 14. In this case, the multiple region elements 25a are formed so as to be connected to each other in the stacking direction. Furthermore, at least the lowest region element 25a is connected to the first upper end 14b of the first region 14.

[0206] The region element 25a is a random impurity region introduced into a surface portion of the first layer 8 by random implantation into the first layer 8 (see also FIG. 12 ). That is, the region element 25a is not formed in the second layer 9. Furthermore, the region element 25a has a thickness in the direction along the first axial channel CH1 that is less than the first region thickness TR1 of the first region 14. Furthermore, the thickness of the region element 25a is less than the second region thickness TR2 of the second region 15.

[0207] Unlike the first region 14 and the like, the region element 25a does not have a gradual portion 22 having a thickness of 0.5 μm or more, and has a concentration gradient including a gradually increasing portion 20, a peak portion 21, and a gradually decreasing portion 23 within a range of 0.5 μm. When each intermediate region 25 includes multiple region elements 25a, each intermediate region 25 has multiple peak portions 21 (peak values ​​P) in the thickness direction of the first layer 8 according to the number of the multiple region elements 25a.

[0208] The area element 25a is 1×10 １５ cm －３ 1x10 or more １８ cm －３ In FIG. 24, the peak value P of the p-type impurity concentration of the region element 25a is 1×10１６ cm －３ 1x10 or more １７ cm －３ An example is shown below.

[0209] The p-type impurity concentration of intermediate region 25 is preferably adjusted by at least one trivalent element. The trivalent element of intermediate region 25 may be the same as or different from the trivalent element of first region 14, etc. The trivalent element of intermediate region 25 may be at least one of boron, aluminum, gallium, and indium.

[0210] Each of the multiple intermediate regions 25 has a middle width WM. The middle width WM is the width along the first arrangement direction Da1. The middle width WM is preferably less than the first thickness T1 of the first layer 8. Of course, the middle width WM may be equal to or greater than the first thickness T1. The middle width WM is preferably less than the second thickness T2 of the second layer 9. Of course, the middle width WM may be equal to or greater than the second thickness T2.

[0211] The intermediate width WM is preferably approximately equal to the first width W1 of the first region 14. Of course, the intermediate width WM may be equal to or greater than the first width W1, or may be less than the first width W1. The intermediate width WM is preferably 1 μm or greater. The intermediate width WM is preferably 5 μm or less.

[0212] The intermediate width WM may have a value belonging to any one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0213] Each of the intermediate regions 25 has an intermediate thickness TM. The intermediate thickness TM is preferably equal to or greater than the distance between the upper end of the first layer 8 and the first upper end 14b of the first region 14. The intermediate thickness TM may be 0.1 μm or greater and 2 μm or less. The intermediate thickness TM may have a value belonging to any one of the ranges of 0.1 μm or greater and 0.5 μm or less, 0.5 μm or greater and 1 μm or less, 1 μm or greater and 1.5 μm or less, and 1.5 μm or greater and 2 μm or less.

[0214] The intermediate regions 25 are formed at an intermediate pitch PM in the first arrangement direction Da1. The intermediate pitch PM is preferably approximately equal to the first pitch P1 of the first regions 14. Of course, the intermediate pitch PM may be equal to or greater than the first pitch P1, or may be less than the first pitch P1. For clarity, FIG. 23 shows an intermediate pitch PM that is greater than the first pitch P1.

[0215] The intermediate pitch PM may be 0.1 μm or more and 5 μm or less. The intermediate pitch PM may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The intermediate pitch PM is preferably 0.5 μm or more and 1.5 μm or less.

[0216] In such a configuration, second region 15 preferably has an extension located within first layer 8 and is connected to intermediate region 25 within first layer 8. That is, second region 15 preferably is electrically connected to first region 14 via intermediate region 25 within first layer 8. In this case, second region 15, together with first region 14 and intermediate region 25, forms one drift region 13 that extends continuously in the stacking direction.

[0217] Of course, the extension of the second region 15 may be connected to both the intermediate region 25 and the first region 14 within the first layer 8. In a configuration having the intermediate region 25, the concentration gradient in the region between the first region 14 and the second region 15 is alleviated by the intermediate region 25, improving the accuracy of charge balance.

[0218] Fig. 25 is a cross-sectional perspective view showing the column region 12 according to the seventh embodiment. Fig. 26 is a graph showing an example of the concentration gradient of the column region 12 shown in Fig. 25. With reference to Figs. 25 and 26, the column region 12 according to the seventh embodiment has a configuration obtained by modifying the first region 14 according to the first to sixth embodiments. The second region 15 according to the seventh embodiment may have a configuration similar to any one of the configurations of the second region 15 according to the first to sixth embodiments.

[0219] In this example, the first region 14 is exposed from the upper end of the first layer 8. The first region 14 does not have part or all of the first gradually increasing portion 20A. Figure 26 shows an example in which the first region 14 does not have all of the first gradually increasing portion 20A and the first peak portion 21A. That is, in this example, the first upper end portion 14b includes the first gradual portion 22A exposed from the upper end of the first layer 8.

[0220] The first region 14 has a first peak value PA at the upper end of the first layer 8, and has a concentration gradient that gradually decreases toward the lower end of the first layer 8. Of course, the first upper end 14b may include a part of the first gradually increasing portion 20A or a part of the first peak portion 21A, and a part of the first gradually increasing portion 20A or a part of the first peak portion 21A may be exposed from the upper end of the first layer 8.

[0221] In this configuration, second region 15 preferably has an extension located within first layer 8 and is connected to first region 14 within first layer 8. In a configuration in which first region 14 is exposed from the upper end of first layer 8, the concentration gradient formed in the region between first region 14 and second region 15 is alleviated by the exposed portion of first region 14, improving the accuracy of charge balance.

[0222] This structure can be achieved by partially removing the upper end of the first layer 8 after forming the first region 14 until part or all of the first gradually increasing portion 20A of the first region 14 disappears. For example, the upper end of the first layer 8 may be partially removed by a grinding method. The grinding method may be a mechanical polishing method and / or a chemical mechanical polishing method. In this case, the upper end of the first layer 8 is a ground surface, and the first region 14 is exposed from the ground surface. The second layer 9 is laminated on top of the ground surface of the first layer 8.

[0223] For example, the upper end of the first layer 8 may be partially removed by etching. The etching may be wet etching and / or dry etching. In this case, the upper end of the first layer 8 is an etched surface, and the first region 14 is exposed from the etched surface. The second layer 9 is laminated on the etched surface of the first layer 8.

[0224] Fig. 27 is a cross-sectional perspective view showing the column region 12 according to the eighth embodiment. Fig. 28 is a graph showing an example of the concentration gradient of the column region 12 shown in Fig. 27. With reference to Figs. 27 and 28, the column region 12 according to the eighth embodiment has a configuration obtained by modifying the second region 15 according to the first to seventh embodiments. The first region 14 according to the eighth embodiment may have a configuration similar to any one of the configurations of the first region 14 according to the first to seventh embodiments. Figs. 27 and 28 show the first region 14 according to the seventh embodiment.

[0225] In this example, the second region 15 is exposed from the upper end (first main surface 3) of the second layer 9. The second region 15 does not have part or all of the second gradually increasing portion 20B. Figure 28 shows an example in which the second region 15 does not have all of the second gradually increasing portion 20B and the second peak portion 21B. That is, in this example, the second upper end 15b includes the second gradual portion 22B exposed from the upper end of the second layer 9.

[0226] The second region 15 has a second peak value PB at the upper end of the second layer 9, and has a concentration gradient that gradually decreases toward the lower end of the second layer 9. Of course, the second upper end 15b may include a part of the second gradually increasing portion 20B or a part of the second peak portion 21B, and a part of the second gradually increasing portion 20B or a part of the second peak portion 21B may be exposed from the upper end of the second layer 9.

[0227] The configuration in which the second region 15 is exposed from the upper end of the second layer 9 is effective when a device structure is formed using the second layer 9 (first main surface 3) and the electrical characteristics of the device structure are adjusted using the second region 15.

[0228] This structure can be obtained by partially removing the upper end of the second layer 9 after the second region 15 is formed, until part or all of the second gradually increasing portion 20B of the second region 15 disappears. For example, the upper end (first main surface 3) of the second layer 9 may be partially removed by a grinding method. The grinding method may be a mechanical polishing method and / or a chemical mechanical polishing method. In this case, the upper end of the second layer 9 is a ground surface, and the second region 15 is exposed from the ground surface.

[0229] For example, the upper end (first main surface 3) of the second layer 9 may be partially removed by etching. The etching may be wet etching and / or dry etching. In this case, the upper end of the second layer 9 is an etched surface, and the second region 15 is exposed from the etched surface.

[0230] Fig. 29 is a cross-sectional perspective view showing the column region 12 according to the ninth embodiment. Fig. 30 is a cross-sectional perspective view showing the column region 12 according to the tenth embodiment. With reference to Figs. 29 and 30 , the stacked portion 7 may have a stacked structure including a buffer layer 26, a first layer 8, and a second layer 9 stacked in this order from the base layer 6 side. The buffer layer 26 may be referred to as a "buffer SiC layer," a "buffer region," or the like.

[0231] The buffer layer 26 includes SiC single crystal and has n-type conductivity. The buffer layer 26 is stacked on the base layer 6. The buffer layer 26 extends horizontally in a layered manner, forming the middle portion of the chip 2 and part of the first to fourth side surfaces 5A to 5D. The buffer layer 26 is made of an epitaxial layer (i.e., a SiC epitaxial layer) grown from the base layer 6.

[0232] The buffer layer 26 has a lower end and an upper end. The lower end of the buffer layer 26 is the crystal growth starting point, and the upper end of the buffer layer 26 is the crystal growth end point. Because the buffer layer 26 is grown continuously from the base layer 6, the lower end of the buffer layer 26 coincides with the upper end of the base layer 6. The boundary between the base layer 6 and the buffer layer 26 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements. The buffer layer 26 has an off-direction Doff and an off-angle θoff that are approximately the same as the off-direction Doff and the off-angle θoff of the base layer 6.

[0233] The buffer layer 26 has a buffer axis channel CHBu extending along the stacking direction. The buffer axis channel CHBu is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the buffer layer 26, and is surrounded by atomic rows along a crystal axis extending in the stacking direction (crystal growth direction).

[0234] In other words, the buffer axis channel CHBu is a region in which a region in which atomic rows are sparse extends in the stacking direction and in which atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in plan view. The buffer axis channel CHBu is preferably a region surrounded by atomic rows along low-index crystal axes among the crystal axes.

[0235] In this embodiment, the buffer axis channel CHBu is formed by a region surrounded by atomic rows aligned along the c-axis of the SiC single crystal. That is, the buffer axis channel CHBu extends along the c-axis and has an off-direction Doff and an off-angle θoff. In other words, the buffer axis channel CHBu is inclined from the vertical axis toward the off-direction Doff by the off-angle θoff.

[0236] The n-type impurity concentration of the buffer layer 26 is preferably lower than the n-type impurity concentration of the base layer 6. The buffer layer 26 has a dopant concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the buffer layer 26 may have a peak value of the following: The n-type impurity concentration of the buffer layer 26 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the buffer layer 26 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0237] The buffer layer 26 has an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the buffer layer 26 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The buffer layer 26 preferably contains a pentavalent element other than phosphorus.

[0238] The n-type impurity concentration of the buffer layer 26 is preferably adjusted by at least nitrogen. When the buffer layer 26 contains two or more pentavalent elements, the buffer layer 26 preferably contains nitrogen and a pentavalent element other than nitrogen. In this case, the buffer layer 26 preferably contains either arsenic or antimony, or both, as the pentavalent element other than phosphorus and nitrogen.

[0239] The buffer layer 26 has a buffer thickness TBu. The buffer thickness TBu is preferably less than the base thickness TB. The buffer thickness TBu is preferably 1 μm or more. The buffer thickness TBu is preferably 5 μm or less. The buffer thickness TBu may have a value belonging to any one of the following ranges: 1 μm or more to 1.5 μm or less, 1.5 μm or more to 2 μm or less, 2 μm or more to 2.5 μm or less, 2.5 μm or more to 3 μm or less, 3 μm or more to 3.5 μm or less, 3.5 μm or more to 4 μm or less, 4 μm or more to 4.5 μm or less, and 4.5 μm or more to 5 μm or less.

[0240] In this embodiment, the first layer 8 is stacked on the buffer layer 26, and the second layer 9 is stacked on the first layer 8. The first layer 8 is made of an epitaxial layer (i.e., a SiC epitaxial layer) crystal-grown starting from the buffer layer 26, and has n-type conductivity. Therefore, the first layer 8 has an off-direction Doff and an off-angle θoff that substantially coincide with the off-direction Doff and the off-angle θoff of the buffer layer 26. In addition, the first axis channel CH1 substantially coincides with the buffer axis channel CHBu.

[0241] The first thickness T1 of the first layer 8 is preferably greater than the buffer thickness TBu. Of course, the first thickness T1 may be less than the buffer thickness TBu. Alternatively, the first thickness T1 may be approximately equal to the buffer thickness TBu. The second thickness T2 of the second layer 9 is preferably greater than the buffer thickness TBu. Of course, the second thickness T2 may be less than the buffer thickness TBu. Alternatively, the second thickness T2 may be approximately equal to the buffer thickness TBu.

[0242] The first region 14 has a shape similar to any one of the shapes of the first region 14 according to the first to eighth embodiments, and is formed in the first layer 8. The second region 15 has a shape similar to any one of the shapes of the first region 14 according to the first to eighth embodiments, and is formed in the second layer 9.

[0243] 29 , first lower end 14a of first region 14 may be formed at a distance from the lower end toward the upper end of first layer 8, and may face buffer layer 26 across a part (lower end) of first layer 8. In other words, the entire area of ​​first region 14 (first gradually increasing portion 20A, first peak portion 21A, first gradual portion 22A, and first gradually decreasing portion 23A) may be located within first layer 8. Of course, first lower end 14a may be substantially coincident with the lower end of first layer 8 and connected to buffer layer 26.

[0244] 30 , the first lower end 14 a may have an extension that crosses the boundary between the buffer layer 26 and the first layer 8 and is located within the buffer layer 26. Since the first axis channel CH1 is substantially aligned with the buffer axis channel CHBu, the extension of the first lower end 14 a is formed within the buffer layer 26 along the buffer axis channel CHBu.

[0245] The extension of the first lower end 14a is preferably located closer to the upper end of the buffer layer 26 than the intermediate portion of the thickness range of the buffer layer 26. The extension of the first lower end 14a includes the first gradually tapering portion 23A. Of course, the extension of the first lower end 14a may include the first gradually tapering portion 23A and a part of the first gradual portion 22A.

[0246] Fig. 31 is a cross-sectional perspective view showing a column region 12 according to an eleventh embodiment. In the above-described embodiment, it has been explained that a superjunction structure SJ having a stacked structure of three or more layers can be adopted. Fig. 31 shows, as an example, a stacked portion 7 having a three-layer structure and a column region 12 having a three-layer structure.

[0247] Specifically, the stacked portion 7 includes an n-type third layer 27 made of single-crystal SiC stacked on the second layer 9. The third layer 27 may also be referred to as a "third SiC layer," a "third semiconductor layer," or the like. In this example, the second layer 9 forms the middle portion of the chip 2 and forms part of the first to fourth side surfaces 5A to 5D. The third layer 27 extends horizontally in a layered manner, forms the first main surface 3, and forms part of the first to fourth side surfaces 5A to 5D. The third layer 27 is made of an epitaxial layer (i.e., a SiC epitaxial layer) grown from the second layer 9.

[0248] The third layer 27 has a lower end and an upper end. The lower end of the third layer 27 is the crystal growth starting point, and the upper end of the third layer 27 is the crystal growth end point. Because the third layer 27 is grown continuously from the second layer 9, the lower end of the third layer 27 coincides with the upper end of the second layer 9. The boundary between the second layer 9 and the third layer 27 is not necessarily visible and can be indirectly evaluated and / or determined from other configurations or elements. The third layer 27 has an off-direction Doff and an off-angle θoff that are substantially identical to the off-direction Doff and off-angle θoff of the second layer 9.

[0249] The third layer 27 has a third axis channel CH3 extending along the stacking direction. The third axis channel CH3 is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the third layer 27, and is surrounded by atomic rows along a crystal axis extending in the stacking direction (crystal growth direction).

[0250] In other words, the third axis channel CH3 is a region in which a region in which atomic rows are sparse extends in the stacking direction and in which atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in plan view. The third axis channel CH3 is preferably a region surrounded by atomic rows along a low-index crystal axis among the crystal axes.

[0251] In this embodiment, the third axis channel CH3 is formed by a region surrounded by atomic rows along the c-axis of the SiC single crystal. That is, the third axis channel CH3 extends along the c-axis and has an off-direction Doff and an off-angle θoff. In other words, the third axis channel CH3 is inclined by the off-angle θoff from the vertical axis toward the off-direction Doff.

[0252] The n-type impurity concentration of the third layer 27 is preferably lower than the n-type impurity concentration of the base layer 6. The third layer 27 has an n-type impurity concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the third layer 27 may have a peak value of the following: The n-type impurity concentration of the third layer 27 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the third layer 27 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0253] The third layer 27 has an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the third layer 27 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The third layer 27 preferably contains a pentavalent element other than phosphorus.

[0254] The n-type impurity concentration of the third layer 27 is preferably adjusted by at least nitrogen. When the third layer 27 contains two or more pentavalent elements, the third layer 27 preferably contains nitrogen and a pentavalent element other than nitrogen. In this case, the third layer 27 preferably contains either arsenic or antimony, or both, as the pentavalent element other than phosphorus and nitrogen.

[0255] The third layer 27 has a third thickness T3. The third thickness T3 is preferably less than the base thickness TB. The third thickness T3 may be approximately equal to the second thickness T2, greater than or equal to the second thickness T2, or less than the second thickness T2. The third thickness T3 may be approximately equal to the first thickness T1, greater than or equal to the first thickness T1, or less than the first thickness T1.

[0256] The third thickness T3 is preferably 1 μm or more. The third thickness T3 is preferably 5 μm or less. The third thickness T3 may have a value belonging to any one of the ranges of 1 μm or more to 1.5 μm or less, 1.5 μm or more to 2 μm or less, 2 μm or more to 2.5 μm or less, 2.5 μm or more to 3 μm or less, 3 μm or more to 3.5 μm or less, 3.5 μm or more to 4 μm or less, 4 μm or more to 4.5 μm or less, and 4.5 μm or more to 5 μm or less.

[0257] The column region 12 includes third regions 28 formed in the third layer 27. The third regions 28 are formed at intervals in the horizontal direction in the third layer 27, and define a plurality of n-type third drift regions 29, each made of a part of the third layer 27. The third regions 28, together with the third drift regions 29, form a plurality of third pn junctions having charge balance.

[0258] That is, the plurality of third regions 28 constitute a third super junction structure SJ3 together with the third layer 27. The state of charge balance means a state in which, with respect to the plurality of adjacent third regions 28, a depletion layer extending from one third pn junction and a depletion layer extending from the other third pn junction are connected within the plurality of third drift regions 29.

[0259] The multiple third regions 28 are formed in the third layer 27 so as to overlap the multiple second regions 15 in the stacking direction. Specifically, the multiple third regions 28 are arranged at intervals in the third layer 27 in a third array direction Da3 different from the second array direction Da2, and are each formed in a strip shape extending in a third extension direction De3 different from the second extension direction De2. In other words, the multiple third regions 28 are formed in a stripe shape extending in the third extension direction De3, and the multiple third drift regions 29 are formed in a stripe shape extending in the third extension direction De3.

[0260] The multiple third regions 28 intersect with the multiple second regions 15 in a plan view. Therefore, the multiple third drift regions 29 are connected to the multiple second drift regions 17 at the boundary between the second layer 9 and the third layer 27, and together with the multiple first drift regions 16 and the multiple second drift regions 17, form one three-dimensional lattice-shaped drift region 13. The multiple third drift regions 29, together with the multiple first drift regions 16 and the multiple second drift regions 17, form a three-dimensional lattice-shaped current path extending in the stacking direction.

[0261] The third arrangement direction Da3 may coincide with the first arrangement direction Da1. Furthermore, the third extension direction De3 may coincide with the first extension direction De1. That is, the third regions 28 may extend in the same direction as the first regions 14 in a plan view. In this case, the third regions 28 may face the first regions 14 in a one-to-one correspondence in the stacking direction.

[0262] Of course, the multiple third regions 28 may be arranged offset from the multiple first regions 14 in the first array direction Da1 and may face either one or both of the first regions 14 and the first drift region 16 in the stacking direction. Of course, the third array direction Da3 may be different from the first array direction Da1. Furthermore, the third extension direction De3 may be different from the first extension direction De1. In other words, the multiple third regions 28 may intersect (for example, perpendicular to) the multiple first regions 14 in a planar view.

[0263] The multiple third regions 28 are formed of channeling regions (third channeling regions) extending along the third axis channel CH3 in the third layer 27 in a cross-sectional view. That is, the third regions 28 are impurity regions introduced parallel or substantially parallel to a region (third axis channel CH3) surrounded by atomic rows along the low-index crystal axis in the third layer 27, and extend at an angle with respect to the first main surface 3.

[0264] Each of the plurality of third regions 28 has a third lower end 28a on the lower end side of the third layer 27 and a third upper end 28b on the upper end side of the third layer 27. The third lower end 28a is located in a region on the lower end side of the third layer 27 with respect to the intermediate portion of the thickness range of the third layer 27, and the third upper end 28b is located in a region on the upper end side of the third layer 27 with respect to the intermediate portion of the thickness range of the third layer 27. In other words, each of the plurality of third regions 28 is formed of a single impurity region having a thickness (depth) that traverses the intermediate portion of the third layer 27 along the third axial channel CH3.

[0265] The third lower end 28a may be formed at a distance from the lower end of the third layer 27 toward the upper end, and may face the second layer 9 across a part (lower end) of the third layer 27. The third lower end 28a may be substantially coincident with the lower end of the third layer 27 and connected to the second layer 9.

[0266] The distance between the lower end of the third layer 27 and the third lower end 28a may be 0 μm or more and 2 μm or less. The distance between the lower end of the third layer 27 and the third lower end 28a may have a value belonging to any one of the ranges of 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0267] The third lower end 28a may have an extension that crosses the boundary between the second layer 9 and the third layer 27 and is located within the second layer 9. In this case, the thickness of the extension of the third lower end 28a, measured from the upper end of the second layer 9, may be greater than 0 μm and less than 2 μm. The thickness of the extension of the third lower end 28a may have a value that belongs to any one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm or more to 1 μm or less, 1 μm or more to 1.5 μm or less, and 1.5 μm or more to 2 μm or less.

[0268] The third upper end 28b may be formed at a distance from the upper end of the third layer 27 (i.e., the first main surface 3) toward the lower end, and may face the upper end of the third layer 27 across a part (upper end) of the third layer 27. The third upper end 28b may be exposed from the upper end of the third layer 27 (i.e., the first main surface 3).

[0269] The distance between the upper end of the third layer 27 and the third upper end 28b may be 0 μm or more and 1 μm or less. The distance between the upper end of the third layer 27 and the third upper end 28b may have a value belonging to any one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0270] The plurality of third regions 28 are 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration (peak value) of the third region 28 may be equal to or greater than the p-type impurity concentration (peak value) of the first region 14. The p-type impurity concentration (peak value) of the third region 28 may be less than the p-type impurity concentration (peak value) of the first region 14. It is preferable that the p-type impurity concentration (peak value) of the third region 28 is approximately equal to the p-type impurity concentration (peak value) of the first region 14.

[0271] The p-type impurity concentration of third region 28 is preferably adjusted with at least one trivalent element. It is particularly preferable that the p-type impurity concentration of third region 28 be adjusted with a trivalent element that is heavier than carbon. In other words, third region 28 preferably contains a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the p-type impurity concentration of third region 28 is adjusted with aluminum.

[0272] Each of the multiple third regions 28 has a third width W3. The third width W3 is the width along the third arrangement direction Da3. The third width W3 is preferably less than the third thickness T3 of the third layer 27. Of course, the third width W3 may be equal to or greater than the third thickness T3. The third width W3 is preferably less than the first thickness T1 of the first layer 8. Of course, the third width W3 may be equal to or greater than the first thickness T1. The third width W3 is preferably less than the second thickness T2 of the second layer 9. Of course, the third width W3 may be equal to or greater than the second thickness T2.

[0273] The third width W3 may be equal to or greater than the first width W1 of the first region 14, or may be less than the first width W1. The third width W3 is preferably approximately equal to the first width W1. The third width W3 may be equal to or greater than the second width W2 of the second region 15, or may be less than the second width W2. The third width W3 is preferably approximately equal to the second width W2.

[0274] The third width W3 may be 0.1 μm or more and 5 μm or less. The third width W3 may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The third width W3 is preferably 0.5 μm or more and 1.5 μm or less.

[0275] The plurality of third regions 28 each have a third region thickness TR3. The third region thickness TR3 may be less than the third thickness T3 of the third layer 27. The third region thickness TR3 may be greater than the third thickness T3. The third region thickness TR3 may be approximately equal to the third thickness T3.

[0276] The third regional thickness TR3 may be less than the first thickness T1 of the first layer 8. The third regional thickness TR3 may be greater than the first thickness T1. The third regional thickness TR3 may be approximately equal to the first thickness T1. The third regional thickness TR3 may be less than the second thickness T2 of the second layer 9. The third regional thickness TR3 may be greater than the second thickness T2. The third regional thickness TR3 may be approximately equal to the second thickness T2.

[0277] The third region thickness TR3 is preferably 1 μm or more. The third region thickness TR3 is preferably 5 μm or less. The third region thickness TR3 may have a value belonging to any one of the following ranges: 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0278] Preferably, the third width W3 is less than the third thickness T3 of the third layer 27, and the third region thickness TR3 is greater than the third width W3. That is, the plurality of third regions 28 preferably each have a third aspect ratio TR3 / W3 such that they extend in a vertically elongated columnar shape along the third axial channel CH3. The third aspect ratio TR3 / W3 is the ratio of the third region thickness TR3 to the third width W3. In this case, it is particularly preferred that the third region thickness TR3 be greater than the third thickness T3. For example, the third aspect ratio TR3 / W3 may be greater than 1 and not greater than 100.

[0279] The multiple third regions 28 are formed at intervals of a third pitch P3 in the third arrangement direction Da3. The third pitch P3 is preferably less than the third thickness T3 of the third layer 27. Of course, the third pitch P3 may be equal to or greater than the third thickness T3. The third pitch P3 is preferably less than the first thickness T1 of the first layer 8. Also, the third pitch P3 is preferably less than the second thickness T2 of the second layer 9. Of course, the third pitch P3 may be equal to or greater than the first thickness T1. Also, the third pitch P3 may be equal to or greater than the second thickness T2.

[0280] The third pitch P3 may be approximately equal to the first pitch P1 or may be different from the first pitch P1. The third pitch P3 may be larger than the first pitch P1 or may be smaller than the first pitch P1. The third pitch P3 may be approximately equal to the second pitch P2 or may be different from the second pitch P2. The third pitch P3 may be larger than the second pitch P2 or may be smaller than the second pitch P2.

[0281] The third pitch P3 may be 0.1 μm or more and 5 μm or less. The third pitch P3 may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The third pitch P3 is preferably 0.5 μm or more and 1.5 μm or less.

[0282] 11A to 11E are applied to the description of the concentration gradient of the third region 28. Furthermore, the configurations of the first region 14 (first layer 8) and the second region 15 (second layer 9) shown in the first to twelfth embodiments are applied to the configuration of the third region 28 (third layer 27).

[0283] 32 is a cross-sectional perspective view showing the column region 12 according to the twelfth embodiment. Referring to FIG. 32 , the stacked portion 7 in this example includes an n-type SiC single-crystalline top layer 30 stacked on the second layer 9. The top layer 30 is formed to separate the first main surface 3 from the column region 12. In other words, the top layer 30 also forms at least a part of the region between the first main surface 3 and the second upper ends 15 b of the plurality of second regions 15. The top layer 30 may also be considered to be a portion forming the upper ends of the second layer 9.

[0284] In this example, the top layer 30 has n-type conductivity, but the conductivity type of the top layer 30 can be adjusted appropriately depending on the properties of the device structure to be formed on the first main surface 3. Therefore, the conductivity type of the top layer 30 is not necessarily limited to n-type, and may be p-type.

[0285] The top layer 30 is stacked on the second layer 9. The top layer 30 extends horizontally in a layered manner, forming the first main surface 3 and forming parts of the first to fourth side surfaces 5A to 5D. The top layer 30 is made of an epitaxial layer (i.e., a SiC epitaxial layer) crystal-grown starting from the second layer 9.

[0286] Because the top layer 30 is continuously crystal-grown from the second layer 9, the bottom end of the top layer 30 coincides with the top end of the second layer 9. The boundary between the top layer 30 and the second layer 9 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements. The top layer 30 has an off-direction Doff and an off-angle θoff that are substantially identical to the off-direction Doff and the off-angle θoff of the second layer 9.

[0287] The top layer 30 has a top axis channel CHT along the stacking direction. The top axis channel CHT is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the top layer 30, and is surrounded by atomic rows along a crystal axis extending in the stacking direction (crystal growth direction).

[0288] That is, the top axis channel CHT is a region in which a region in which atomic rows are sparse extends in the stacking direction and in which atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in plan view. The top axis channel CHT is preferably a region surrounded by atomic rows along low-index crystal axes among the crystal axes.

[0289] In this embodiment, the top axis channel CHT is composed of a region surrounded by atomic rows along the c-axis of the SiC single crystal. That is, the top axis channel CHT extends along the c-axis and has an off-direction Doff and an off-angle θoff. In other words, the top axis channel CHT is inclined from the vertical axis toward the off-direction Doff by the off-angle θoff.

[0290] The n-type impurity concentration of the top layer 30 is preferably lower than the n-type impurity concentration of the base layer 6. The top layer 30 has a dopant concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the top layer 30 may have a peak value of the following n-type impurity concentration. The n-type impurity concentration of the top layer 30 may be approximately equal to the n-type impurity concentration of the first layer 8 (second layer 9). The n-type impurity concentration of the top layer 30 may be approximately constant in the thickness direction. Of course, the n-type impurity concentration of the top layer 30 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0291] The top layer 30 has an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the top layer 30 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The top layer 30 preferably contains a pentavalent element other than phosphorus.

[0292] The n-type impurity concentration of the top layer 30 is preferably adjusted by at least nitrogen. When the top layer 30 contains two or more pentavalent elements, the top layer 30 preferably contains nitrogen and a pentavalent element other than nitrogen. In this case, the top layer 30 preferably contains either or both of arsenic and antimony as the pentavalent element other than phosphorus and nitrogen.

[0293] The top layer 30 has a top thickness TT. The top thickness TT is preferably less than the base thickness TB. The top thickness TT is preferably less than the first thickness T1 (second thickness T2). Of course, the top thickness TT may be equal to or greater than the first thickness T1 (second thickness T2).

[0294] The top thickness TT may be 0.1 μm or more and 5 μm or less. The top thickness TT may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0295] Below, examples of the device structure formed in the active region 10 are shown. FIG. 33 is a plan view showing a main part of the active region 10. FIG. 34 is a cross-sectional perspective view showing a gate structure 35 according to the first embodiment. FIG. 34 illustrates a configuration in which the column region 12 according to the second embodiment is applied to the column region 12 according to the first basic embodiment. Of course, FIG. 34 may also apply a configuration in which one or more of the column regions 12 according to the first to twelfth embodiment are applied to one of the column regions 12 according to the first to third basic embodiments.

[0296] 33 and 34 , in this embodiment, SiC semiconductor device 1A includes a metal insulator semiconductor (MIS) structure 31 as an example of a device structure formed in active region 10. MIS structure 31 may also be referred to as a “field effect transistor structure.”

[0297] Here, an example is shown in which the MIS structure 31 is formed on the second layer 9 (first main surface 3). When the above-described top layer 30 is formed, the MIS structure 31 is formed on the top layer 30 (first main surface 3). This configuration can be obtained by replacing "second layer 9" with "top layer 30" as necessary in the following description. The following configurations will be described as components of the SiC semiconductor device 1A, but they are also components of the MIS structure 31.

[0298] The SiC semiconductor device 1A includes a plurality of p-type body regions 32 formed in the active region 10. The plurality of body regions 32 are formed in a surface layer portion of the first main surface 3 so as to overlap the plurality of second regions 15 in the stacking direction. In this embodiment, the plurality of body regions 32 are arranged at intervals in the second array direction Da2 so as to overlap the plurality of second regions 15 in a one-to-one correspondence in the stacking direction, and are each formed in a strip shape extending in the second extension direction De2.

[0299] In this example, the second arrangement direction Da2 is the m-axis direction (first direction X), and the second extension direction De2 is the a-axis direction (second direction Y). Of course, the arrangement direction and extension direction of the multiple body regions 32 are changed depending on the second arrangement direction Da2 and second extension direction De2 of the multiple second regions 15. Therefore, the second arrangement direction Da2 may be the a-axis direction, and the second extension direction De2 may be the m-axis direction. Alternatively, the second arrangement direction Da2 may be a direction other than the a-axis direction and the m-axis direction, and the second extension direction De2 may be a direction other than the a-axis direction and the m-axis direction.

[0300] When the second regions 15 are formed at intervals from the first main surface 3, the body regions 32 are each formed in a region between the first main surface 3 and the second upper ends 15b of the second regions 15. The body regions 32 are preferably formed on the first main surface 3 side of the intermediate portion of the thickness range of the second layer 9 and are exposed from the first main surface 3. The body regions 32 are preferably connected to the corresponding second regions 15 (second upper ends 15b).

[0301] The plurality of body regions 32 are each formed to be wider than the second region 15 directly below them, and are formed at intervals from the adjacent plurality of second regions 15 toward the second region 15 directly below them. The plurality of body regions 32 expose a part of the second drift region 17 from a region of the first main surface 3 between the adjacent plurality of second regions 15.

[0302] The body regions 32 are formed of random impurity regions introduced into a surface portion of the second layer 9 by random implantation into the second layer 9 (see also FIG. 12 ). Therefore, the body regions 32 have a thickness along the second axial channel CH2 that is less than the second region thickness TR2 of the second region 15. The thickness of the body regions 32 is less than the first region thickness TR1 of the first region 14.

[0303] Unlike the second region 15 and the like, the body regions 32 do not have a gradual portion 22 having a thickness of 0.5 μm or more, but have a concentration gradient including a gradually increasing portion 20, a peak portion 21, and a gradually decreasing portion 23 within a range of 0.5 μm. １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0304] The p-type impurity concentrations of the body regions 32 are preferably adjusted by at least one trivalent element. The trivalent element in the body regions 32 may be the same as or different from the trivalent element in the second regions 15, etc. The trivalent element in the body regions 32 may be at least one of boron, aluminum, gallium, and indium.

[0305] The SiC semiconductor device 1A includes one or more n-type source regions 33 formed in the surface layer portions of the plurality of body regions 32 in the active region 10. In this embodiment, a plurality of (two in this embodiment) source regions 33 are formed at intervals in the surface layer portion of each body region 32. The plurality of source regions 33 have an n-type impurity concentration higher than the n-type impurity concentration of the second layer 9 (the plurality of second drift regions 17). The plurality of source regions 33 have an n-type impurity concentration of 1×10 １８cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0306] The multiple source regions 33 may each extend in a strip shape along the extension direction of the corresponding body region 32. Of course, the multiple source regions 33 may be formed at intervals along the extension direction of the corresponding body region 32. The multiple source regions 33 are formed at intervals from the bottom of the corresponding body region 32 toward the first main surface 3, and are formed at intervals inward from the periphery of the corresponding body region 32. The multiple source regions 33, together with the multiple second drift regions 17, define a channel (current path) along the first main surface 3 at the periphery of the body region 32.

[0307] The SiC semiconductor device 1A includes one or more p-type contact regions 34 formed in the surface layer portions of the plurality of body regions 32 in the active region 10. The contact regions 34 may also be referred to as "back gate regions." In this embodiment, one contact region 34 is formed in a region between the plurality of adjacent source regions 33 in the surface layer portion of each body region 32.

[0308] The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 32. The p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of second regions 15. The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of second regions 15. １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0309] The plurality of contact regions 34 may each extend in a strip shape along the extension direction of the corresponding body region 32. Of course, the plurality of contact regions 34 may also be formed at intervals along the extension direction of the corresponding body region 32. The plurality of contact regions 34 are formed at intervals from the bottom of the corresponding body region 32 toward the first main surface 3, and are formed at intervals inward from the peripheral edge of the corresponding body region 32.

[0310] The SiC semiconductor device 1A includes a plurality of planar electrode type gate structures 35 arranged on the first main surface 3 in the active region 10. The gate structures 35 may also be referred to as "planar gate structures." The plurality of gate structures 35 are arranged at intervals on the first main surface 3 so as to overlap at least one body region 32 (channel) in the stacking direction. A gate potential is applied to the plurality of gate structures 35 as a control potential. The plurality of gate structures 35 control the inversion and non-inversion of the channel (current path) in the body region 32 in response to the gate potential.

[0311] In this embodiment, the gate structures 35 are arranged at intervals in the second arrangement direction Da2 and are each formed in a strip shape extending in the second extension direction De2. In this example, the second arrangement direction Da2 is the m-axis direction (first direction X), and the second extension direction De2 is the a-axis direction (second direction Y).

[0312] Of course, the arrangement direction and extension direction of the multiple gate structures 35 are changed depending on the second arrangement direction Da2 and second extension direction De2 of the multiple second regions 15 (body regions 32). Therefore, the second arrangement direction Da2 may be the a-axis direction, and the second extension direction De2 may be the m-axis direction. Alternatively, the second arrangement direction Da2 may be a direction other than the a-axis direction and the m-axis direction, and the second extension direction De2 may be a direction other than the a-axis direction and the m-axis direction.

[0313] The plurality of gate structures 35 are arranged shifted from the plurality of second regions 15 toward the plurality of second drift regions 17, and overlap the plurality of second drift regions 17 in a one-to-one correspondence in the stacking direction. In this embodiment, the plurality of gate structures 35 are arranged so as to straddle two adjacent body regions 32, and cover the plurality of source regions 33 located in one and the other body regions 32, respectively.

[0314] Each of the plurality of gate structures 35 has a stacked structure including a gate insulating film 36 disposed on the first main surface 3 and a gate electrode 37 disposed on the gate insulating film 36. The gate insulating film 36 may include a silicon oxide film. The gate electrode 37 may include conductive polysilicon.

[0315] Either or both of the gate insulating film 36 and the gate electrode 37 may be arranged so as to partially overlap the second region 15 in the stacking direction. Of course, either or both of the gate insulating film 36 and the gate electrode 37 may be arranged so as not to partially overlap the second region 15 in the stacking direction.

[0316] The configuration on the side of peripheral region 11 will be described below. Fig. 35 is a cross-sectional view showing a main portion of peripheral region 11. SiC semiconductor device 1A includes at least one (preferably two to 20) p-type field region 38 formed in a surface layer portion of first main surface 3 in peripheral region 11.

[0317] The number of field regions 38 is typically 4 to 8. The field regions 38 are formed in an electrically floating state and relieve the electric field within chip 2 at the periphery of first main surface 3. The number, width, depth, p-type impurity concentration, etc. of field regions 38 are arbitrary and can take various values ​​depending on the electric field to be relieved.

[0318] The multiple field regions 38 are formed at intervals in the region between the periphery of the chip 2 and the active region 10. The multiple field regions 38 are formed in strip shapes extending along the active region 10 in a plan view. Each of the multiple field regions 38 has a portion extending in strip shape in the first direction X and a portion extending in strip shape in the second direction Y. In this embodiment, the multiple field regions 38 are formed in an annular shape (specifically, a rectangular annular shape) surrounding the active region 10 (i.e., the column region 12) in a plan view.

[0319] The plurality of field regions 38 are formed in the second layer 9 at intervals from the lower end of the second layer 9 toward the first main surface 3, and each form a pn junction with the second layer 9. It is preferable that the plurality of field regions 38 have bottoms located on the first main surface 3 side of the intermediate portion of the thickness range of the second layer 9. In this embodiment, the plurality of field regions 38 are formed at intervals from the column regions 12 toward the periphery of the chip 2. Therefore, the plurality of field regions 38 do not face the column regions 12 in the stacking direction.

[0320] The bottoms of the plurality of field regions 38 may be located closer to the first main surface 3 than the depth position of the second upper end 15b of the second region 15. Of course, the bottoms of the plurality of field regions 38 may be located closer to the second lower end 15a of the second region 15 than the depth position of the second upper end 15b of the second region 15. In this case, it is preferable that the bottoms of the plurality of field regions 38 be located closer to the first main surface 3 than the intermediate portion of the thickness range of the second region 15.

[0321] The field regions 38 may have a thickness approximately equal to that of the body regions 32. In this case, the field regions 38 may be formed simultaneously with the body regions 32. Of course, the field regions 38 may have a thickness greater than that of the body regions 32. Alternatively, the field regions 38 may have a thickness less than that of the body regions 32.

[0322] The field regions 38 are formed of random impurity regions introduced into the surface portion of the second layer 9 by random implantation into the second layer 9 (see also FIG. 12 ). Therefore, the field regions 38 have a thickness along the second axial channel CH2 that is less than the second region thickness TR2 of the second region 15. The thickness of the field regions 38 is less than the first region thickness TR1 of the first region 14.

[0323] Unlike the second region 15 and the like, the plurality of field regions 38 do not have a gradual portion 22 having a thickness of 0.5 μm or more, and have a concentration gradient including a gradually increasing portion 20, a peak portion 21, and a gradually decreasing portion 23 within a range of 0.5 μm. １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0324] The p-type impurity concentration of the field region 38 may be approximately equal to the p-type impurity concentration of the body region 32. Of course, the p-type impurity concentrations of the plurality of field regions 38 may be higher than the p-type impurity concentrations of the plurality of body regions 32. Furthermore, the p-type impurity concentrations of the plurality of field regions 38 may be lower than the p-type impurity concentrations of the plurality of body regions 32.

[0325] The p-type impurity concentrations of the plurality of field regions 38 are preferably adjusted by at least one trivalent element. The trivalent element in the field region 38 may be the same as or different from the trivalent element in the second region 15, etc. The trivalent element in the field region 38 may be at least one of boron, aluminum, gallium, and indium.

[0326] The plurality of field regions 38 preferably have a width different from the second width W2 of the second region 15 (the first width W1 of the first region 14). In other words, the electric field relaxation effect of the plurality of field regions 38 is preferably adjusted separately from the column region 12.

[0327] It is particularly preferable that the width of the plurality of field regions 38 be greater than the second width W2 (first width W1) of the second region 15. Of course, the width of the plurality of field regions 38 may be smaller than the second width W2 (first width W1). Furthermore, the width of the column region 12 may be approximately equal to the second width W2 (first width W1).

[0328] The field regions 38 are preferably formed at a pitch different from the second pitch P2 of the second regions 15 (the first pitch P1 of the first regions 14). It is particularly preferable that the pitch of the field regions 38 be larger than the second pitch P2 (the first pitch P1). Of course, the pitch of the field regions 38 may be smaller than the second pitch P2 (the first pitch P1). Alternatively, the pitch of the field regions 38 may be approximately equal to the second pitch P2 (the first pitch P1).

[0329] The SiC semiconductor device 1A includes an interlayer insulating film 40 covering the first main surface 3. The interlayer insulating film 40 may also be referred to as an "insulating film," an "interlayer film," an "intermediate insulating film," or the like. In this embodiment, the interlayer insulating film 40 has a stacked structure including a first insulating film 41 and a second insulating film 42. The first insulating film 41 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is particularly preferable that the first insulating film 41 include a silicon oxide film made of an oxide of the chip 2 (second layer 9).

[0330] The first insulating film 41 selectively covers the first main surface 3 in the active region 10 and the peripheral region 11. The first insulating film 41 covers the region outside the gate insulating film 36 in the active region 10 and is connected to the gate insulating film 36. The first insulating film 41 covers a plurality of field regions 38 in the peripheral region 11. In this embodiment, the first insulating film 41 is continuous with the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D). Of course, the first insulating film 41 may be formed at a distance inward from the periphery of the first main surface 3, with the second layer 9 exposed from the periphery of the first main surface 3.

[0331] The second insulating film 42 is stacked on the first insulating film 41. The second insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 40 preferably includes a silicon oxide film. The second insulating film 42 covers the first main surface 3 in the active region 10 and the peripheral region 11, sandwiching the first insulating film 41 therebetween.

[0332] The second insulating film 42 covers the plurality of gate structures 35 in the active region 10. The second insulating film 42 covers the plurality of field regions 38 in the peripheral region 11, sandwiching the first insulating film 41 therebetween. In this embodiment, the second insulating film 42 is continuous with the periphery of the first main surface 3. Of course, the second insulating film 42 may be formed at a distance inward from the periphery of the first main surface 3, and may expose the periphery of the first main surface 3 together with the first insulating film 41.

[0333] The SiC semiconductor device 1A includes a plurality of contact openings 43 formed in an interlayer insulating film 40. The plurality of contact openings 43 include a plurality of contact openings 43 (not shown) that expose a plurality of gate structures 35 (gate electrodes 37) and a plurality of contact openings 43 that expose a plurality of source regions 33. The plurality of contact openings 43 for the source regions 33 are formed in regions between adjacent plurality of gate structures 35, and expose a plurality of source regions 33 and a plurality of contact regions 34.

[0334] 1 , SiC semiconductor device 1A includes a gate pad 45 disposed on interlayer insulating film 40. Gate pad 45 is an electrode to which a gate potential is applied from the outside. Gate pad 45 may also be referred to as a "gate pad electrode," a "first pad electrode," or the like. Gate pad 45 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 40 side.

[0335] In this embodiment, the gate pad 45 is disposed on a portion of the interlayer insulating film 40 that covers the active region 10. The gate pad 45 may be disposed at an interval from the outer periphery region 11 toward the active region 10. In this embodiment, the gate pad 45 is disposed on the periphery of the active region 10 in plan view.

[0336] 1 shows an example in which the gate pad 45 is arranged in a region along the center of the second side surface 5B on the periphery of the active region 10. Of course, the gate pad 45 may also be arranged in a region along the center of any of the first to fourth side surfaces 5A to 5D. Of course, the gate pad 45 may also be arranged at any corner of the active region 10 in a plan view. Also, the gate pad 45 may be arranged in the center of the active region 10 in a plan view. In this embodiment, the gate pad 45 is formed in a quadrangular shape in a plan view.

[0337] The SiC semiconductor device 1A includes at least one gate wiring 46 (multiple in this embodiment) extending from the gate pad 45 onto the interlayer insulating film 40. The gate wiring 46 may also be referred to as a "wiring," "wiring electrode," or the like. The multiple gate wirings 46 may have a layered structure including a Ti-based metal film and an Al-based metal film stacked in this order from the interlayer insulating film 40 side. In this embodiment, the multiple gate wirings 46 include a first gate wiring 46A and a second gate wiring 46B.

[0338] The first gate wiring 46A is drawn out from the gate pad 45 toward the first side surface 5A and extends in a line along the periphery of the active region 10 so as to intersect (specifically, perpendicular to) part (specifically, one end) of the multiple gate structures 35. The first gate wiring 46A penetrates the interlayer insulating film 40 via the multiple contact openings 43 and is electrically connected to one end of the multiple gate structures 35.

[0339] The second gate wiring 46B is drawn out from the gate pad 45 toward the third side surface 5C and extends in a line along the periphery of the active region 10 so as to intersect (specifically, perpendicular to) part (specifically, the other end portions) of the multiple gate structures 35. The second gate wiring 46B penetrates the interlayer insulating film 40 via the multiple contact openings 43 and is electrically connected to the other end portions of the multiple gate structures 35.

[0340] The SiC semiconductor device 1A includes a source pad 47 disposed on the interlayer insulating film 40 at a distance from the gate pad 45 and the gate wiring 46. The source pad 47 is an electrode to which a source potential is applied from the outside. The source pad 47 may also be referred to as a "source pad electrode," a "second pad electrode," or the like. The source pad 47 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 40 side.

[0341] The source pad 47 is disposed on a portion of the interlayer insulating film 40 that covers the active region 10. The source pad 47 may be disposed at an interval from the peripheral region 11 toward the active region 10. In this embodiment, the source pad 47 is formed in a polygonal shape having a recess that is recessed along the gate pad 45 in a plan view. Of course, the source pad 47 may also be formed in a quadrangular shape in a plan view.

[0342] The source pad 47 penetrates the interlayer insulating film 40 via the contact openings 43, and is electrically connected to the body regions 32, the source regions 33, and the contact regions 34. In other words, the source pad 47 is electrically connected to the column region 12 via the body regions 32.

[0343] The SiC semiconductor device 1A includes a drain pad 48 covering the second main surface 4. The drain pad 48 is an electrode to which a drain potential is applied from the outside. The drain pad 48 may also be referred to as a "drain pad electrode," a "third pad electrode," or the like. The drain pad 48 forms ohmic contact with the base layer 6 exposed from the second main surface 4. In other words, the drain pad 48 is electrically connected to the first layer 8 (the plurality of first drift regions 16) and the second layer 9 (the plurality of second drift regions 17) via the base layer 6.

[0344] The drain pad 48 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The drain pad 48 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0345] The breakdown voltage that can be applied between source pad 47 and drain pad 48 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to any one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0346] When a laminated portion 7 having a two-layer structure is employed, the breakdown voltage is preferably set to a value belonging to any one of the ranges of 500 V to 1000 V, 1000 V to 1500 V, and 1500 V to 2000 V. When a laminated portion 7 having a three-layer structure is employed, the breakdown voltage is preferably set to a value belonging to any one of the ranges of 1000 V to 1500 V, 1500 V to 2000 V, 2000 V to 2500 V, and 2500 V to 3000 V.

[0347] 36 is a cross-sectional perspective view showing a gate structure 35 according to the second embodiment. The gate structures 35 according to the first embodiment extend along the second extension direction De2 of the second regions 15. In contrast, the gate structures 35 according to the second embodiment extend in a direction other than the second extension direction De2 so as to intersect with the second regions 15.

[0348] In this embodiment, the plurality of body regions 32 described above extend in a direction other than the second extension direction De2 so as to intersect with the plurality of second regions 15 in the stacking direction. In this embodiment, the plurality of body regions 32 are arranged at intervals in the first arrangement direction Da1 of the first regions 14 and extend in the first extension direction De1 of the first regions 14. In other words, the plurality of body regions 32 are perpendicular to the plurality of second regions 15. In this example, the first arrangement direction Da1 is the a-axis direction (second direction Y), and the first extension direction De1 is the m-axis direction (first direction X).

[0349] The body regions 32 may face the first regions 14 in a one-to-one correspondence in the stacking direction. Of course, each body region 32 may face the first regions 14 in the stacking direction. The body regions 32 may face the first drift regions 16 in a one-to-one correspondence in the stacking direction.

[0350] Of course, each body region 32 may face multiple first drift regions 16 in the stacking direction. The multiple body regions 32 may be arranged shifted from the multiple first regions 14 in the first array direction Da1 and face either one or both of the first regions 14 and the first drift regions 16 in the stacking direction.

[0351] Of course, the arrangement direction and extension direction of the plurality of body regions 32 are changed depending on the first arrangement direction Da1 and first extension direction De1 of the plurality of first regions 14. Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Alternatively, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.

[0352] Of course, the arrangement direction of the body regions 32 may be a direction other than the first arrangement direction Da1 and the second arrangement direction D2. Furthermore, the extension direction of the body regions 32 may be a direction other than the first extension direction De1 and the second extension direction De2. That is, the body regions 32 may intersect with both the first regions 14 and the second regions 15 in a plan view. In this case, the arrangement direction of the body regions 32 may be one of the a-axis direction and the m-axis direction, and the extension direction of the body regions 32 may be the other of the a-axis direction and the m-axis direction.

[0353] For example, the angle (absolute value) between the extension direction of the body region 32 and the second extension direction De2 may be greater than 0° and less than 90°. The angle (absolute value) of the body region 32 may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° to 36°, 36° to 54°, 54° to 72°, and 72° to 90°. The angle (absolute value) of the body region 32 may be set to a value belonging to any one of the ranges of 30°±5°, 45°±5°, and 60°±5°.

[0354] The aforementioned multiple source regions 33 and multiple contact regions 34 are formed along the extension direction of the corresponding body regions 32, and face the multiple second regions 15 and the multiple second drift regions 17, respectively, across a portion of the body region 32 corresponding to the stacking direction.

[0355] In this embodiment, the multiple gate structures 35 are arranged at intervals in the first arrangement direction Da1 of the first region 14 and extend in the first extension direction De1 of the first region 14. That is, the multiple gate structures 35 are perpendicular to the multiple second regions 15. In this example, the first arrangement direction Da1 is the a-axis direction (second direction Y), and the first extension direction De1 is the m-axis direction (first direction X).

[0356] The plurality of gate structures 35 may face the plurality of first regions 14 in a one-to-one correspondence in the stacking direction. Of course, each gate structure 35 may face the plurality of first regions 14 in the stacking direction. The plurality of gate structures 35 may face the plurality of first drift regions 16 in a one-to-one correspondence in the stacking direction.

[0357] Of course, each gate structure 35 may face multiple first drift regions 16 in the stacking direction. The multiple gate structures 35 may be arranged shifted from the multiple first regions 14 in the first array direction Da1 and face either one or both of the first regions 14 and the first drift regions 16 in the stacking direction.

[0358] Of course, the arrangement direction and extension direction of the multiple gate structures 35 are changed depending on the first arrangement direction Da1 and first extension direction De1 of the multiple first regions 14 (body regions 32). Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Alternatively, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.

[0359] Of course, the arrangement direction of the multiple gate structures 35 may be a direction other than the first arrangement direction Da1 and the second arrangement direction D2. Furthermore, the extension direction of the multiple gate structures 35 may be a direction other than the first extension direction De1 and the second extension direction De2. That is, the multiple gate structures 35 may intersect both the multiple first regions 14 and the multiple second regions 15 in a planar view. In this case, a configuration in which the arrangement direction of the multiple gate structures 35 is one of the a-axis direction and the m-axis direction and the extension direction of the multiple gate structures 35 is the other of the a-axis direction and the m-axis direction is not prevented.

[0360] For example, the angle (absolute value) between the extension direction of the gate structure 35 and the second extension direction De2 may be greater than 0° and less than 90°. The angle (absolute value) of the gate structure 35 may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° to 36°, 36° to 54°, 54° to 72°, and 72° to 90°. The angle (absolute value) of the gate structure 35 may be set to a value belonging to any one of the ranges of 30°±5°, 45°±5°, and 60°±5°.

[0361] In this embodiment, the plurality of gate structures 35 are each arranged to straddle two adjacent body regions 32, and cover the plurality of source regions 33 located in one and the other body regions 32. The plurality of gate structures 35 also face the plurality of second regions 15 (second regions 15) and the plurality of second drift regions 17 in the stacking direction, respectively.

[0362] 37 is a schematic diagram showing a wafer 50 used in the manufacture of the SiC semiconductor device 1A. The wafer 50 is a substrate of the base layer 6 and includes a SiC single crystal. The wafer 50 is formed in a flat disk shape. Of course, the wafer 50 may also be formed in a flat rectangular parallelepiped shape. The wafer 50 has a first wafer main surface 51 on one side, a second wafer main surface 52 on the other side, and a wafer side surface 53 connecting the first wafer main surface 51 and the second wafer main surface 52.

[0363] The first wafer main surface 51 corresponds to the upper end of the base layer 6, and the second wafer main surface 52 corresponds to the lower end of the base layer 6. The first wafer main surface 51 and the second wafer main surface 52 are formed by the c-plane of the SiC single crystal. The first wafer main surface 51 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 52 is formed by the carbon surface of the SiC single crystal. The wafer 50 (the first wafer main surface 51 and the second wafer main surface 52) has the off-direction Doff and the off-angle θoff described above.

[0364] The wafer 50 has a mark 54 on the wafer side surface 53 that indicates the crystal orientation of the SiC single crystal. The mark 54 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is linearly cut out in a plan view. The orientation notch is a cutout that is concave (e.g., tapered) toward the center of the first wafer main surface 51 in a plan view.

[0365] The mark 54 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The mark 54 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction. Figure 37 shows an orientation flat extending in the m-axis direction in a plan view.

[0366] For example, a plurality of device regions 55 and a plurality of cutting lines 56 are set on the wafer 50 by alignment marks or the like. Each device region 55 corresponds to a SiC semiconductor device 1A. Each of the plurality of device regions 55 is set to have a quadrangular shape in a plan view.

[0367] In this embodiment, the device regions 55 are set in a matrix along the first direction X and the second direction Y in a plan view. The device regions 55 are set at intervals inward from the periphery of the first wafer main surface 51 in a plan view. The cutting lines 56 are set in a grid pattern extending along the first direction X and the second direction Y to partition the device regions 55.

[0368] Fig. 38 is a flowchart showing an example of a manufacturing method for the SiC semiconductor device 1A. Figs. 39A to 39H are cross-sectional perspective views showing an example of a manufacturing method for the SiC semiconductor device 1A. Figs. 40A to 40B are schematic views for explaining a crystal orientation measurement process. Figs. 41A to 41B are schematic views for explaining an ion implantation process. Figs. 39A to 39H show cross-sectional perspective views of a portion of the active region 10 of one device region 55.

[0369] First, referring to FIG. 39A, the aforementioned wafer 50 preparation step is performed (step S1 in FIG. 38). Next, a determination step is performed as to whether or not an n-type buffer layer 26 (see FIGS. 29 and 30) formation step is performed (step S2 in FIG. 38). If a buffer layer 26 is to be formed (step S2 in FIG. 38: YES), the buffer layer 26 is formed by epitaxial growth starting from the first wafer main surface 51 (wafer 50) (step S3 in FIG. 38). If the buffer layer 26 formation step is not performed (step S2 in FIG. 38: NO), this step is omitted.

[0370] 39B , the step of forming an n-type first layer 8 is performed (step S4 in FIG. 38 ). If the step of forming the buffer layer 26 is omitted, the first layer 8 is formed by epitaxial growth starting from the first wafer main surface 51 (wafer 50). If the buffer layer 26 is formed, the first layer 8 is formed by epitaxial growth starting from the buffer layer 26. In this case, the first layer 8 may be formed by continuous crystal growth from the buffer layer 26 using the step of forming the buffer layer 26 after the step of forming the buffer layer 26.

[0371] Next, a step of measuring the crystal orientation of the first layer 8 is performed (Step S5 in FIG. 38 ). The crystal orientation of the first layer 8 includes a step of measuring the off angle θ of the first layer 8. That is, this step includes a step of measuring the crystal orientation of the first axis channel CH1 of the first layer 8.

[0372] The wafer 50 is cut from an ingot (SiC ingot), which is a crystalline mass, and there is a risk that an error will occur in the off-angle θoff due to a process error. If an error occurs in the off-angle θoff of the wafer 50, a process error will also occur in the off-angle θoff of the first layer 8, which will become an obstacle during the channeling implantation process. Therefore, it is preferable that data (information) on the off-angle θoff be acquired prior to the channeling implantation process, and that the channeling implantation process be performed based on the data (information) on the off-angle θoff.

[0373] 40A , in this step, the crystal orientation of the first layer 8 is measured by an X-ray diffraction method (so-called ω-2θ measurement method) using an X-ray diffraction device 57. The X-ray diffraction device 57 may also be referred to as an "XRD (X-ray Diffraction) device."

[0374] The X-ray diffraction device 57 includes an irradiation unit 58 and a detection unit 59 and performs rocking curve measurement. The irradiation unit 58 irradiates the upper end of the first layer 8 (the first wafer main surface 51 of the wafer 50) with incident X-rays L1 at a predetermined incident angle ω. The incident angle ω is defined as the angle between the incident X-rays L1 and the upper end of the first layer 8 (the first wafer main surface 51 of the wafer 50).

[0375] The detector 59 is disposed at an angular position of a diffraction angle 2θ (θ is the Bragg angle) with respect to the irradiation position of the incident X-rays L1 on the wafer 50, and detects the diffracted X-rays L2. The diffraction angle 2θ is the angle between the incident direction of the incident X-rays L1 and the diffraction direction of the diffracted X-rays L2.

[0376] In the rocking curve measurement method, the incident angle ω is varied within a small angular range while the diffraction angle 2θ is fixed, and a rocking curve representing the intensity of the diffracted X-rays L2 (the intensity profile of the diffracted X-rays L2) is measured. The rocking curve has the intensity of the diffracted X-rays L2 on the vertical axis and the incident angle ω on the horizontal axis. The incident angle ω is determined as the angular position at which the intensity of the diffracted X-rays L2 takes a peak value.

[0377] In this step, the rocking curve measurement method is performed only at one location (for example, the central portion) of the upper end (first wafer main surface 51 of the wafer 50) of the first layer 8. If in-plane variation in the off angle θ is expected, the rocking curve measurement method may be performed at multiple locations (for example, the central portion and peripheral portion) of the upper end (first wafer main surface 51 of the wafer 50) of the first layer 8.

[0378] 40B shows measurement points obtained by performing rocking curve measurement on multiple locations (five locations in this example) on the upper end of the first layer 8. The off angle θoff of the first layer 8 is set to approximately 4° in this example. First to fifth measurement points Po1 to Po5 are shown in FIG.

[0379] The first measurement point Po1 is set in the center of the first layer 8. The second measurement point Po2 is set in the peripheral portion of the first layer 8 at a distance from the first measurement point Po1 on one side in the second direction Y (the opposite side from the mark 54). The third measurement point Po3 is set in the peripheral portion of the first layer 8 at a distance from the first measurement point Po1 on one side in the first direction X (to the right of the mark 54).

[0380] The fourth measurement point Po4 is set on the periphery of the first layer 8 at a distance from the first measurement point Po1 to the other side in the second direction Y (toward the mark 54). The fifth measurement point Po5 is set on the periphery of the first layer 8 at a distance from the first measurement point Po1 to the other side in the first direction X (to the left of the mark 54).

[0381] The measurement results of the incident angle ω, diffraction angle 2θ, and off angle θoff at the first to fifth measurement points Po1 to Po5 are shown in Table 1. The off angle θoff is calculated using the incident angle ω and diffraction angle 2θ by the formula "ω - (2θ × 1 / 2)".

[0382] As shown in Table 1, the average value of the off angle θoff at the first to fifth measurement points Po1 to Po5 was 4.036°, and the standard deviation of these off angles θoff was 0.009° (±0.01°). From this, it can be understood that the in-plane variation of the off angle θoff occurring at the upper end of the first layer 8 (first wafer main surface 51 of the wafer 50) is extremely small, and does not interfere with the channeling implantation process.

[0383] Therefore, it is understood that there is no problem with at least one measurement point on the upper end of the first layer 8 (first wafer main surface 51 of wafer 50). For example, the measurement point may be any one or more (all) of the first to fifth measurement points Po1 to Po5. For example, the measurement point may be only the first measurement point Po1. Reducing the number of measurement points (number of measurements) reduces the number of manufacturing steps (manufacturing costs).

[0384] Of course, the off angle θ may be measured at multiple locations on the upper end of the first layer 8 (first wafer main surface 51 of the wafer 50) and the implantation angle may be set in accordance with the in-plane variation of the off angle θ in the channeling implantation process. In this case, although the number of manufacturing steps (manufacturing costs) increases, the in-plane error of the first region 14 formed in the first layer 8 is appropriately suppressed.

[0385] The off-angle θ of the first layer 8 is substantially equal to the off-angle θ of the wafer 50 and the off-angle θ of the buffer layer 26. Therefore, the crystal orientation measurement step may be performed on the wafer 50 or the buffer layer 26 prior to the step of forming the first layer 8. However, from the viewpoint of ensuring accuracy, it is preferable that the crystal orientation measurement step be performed on the first layer 8.

[0386] 39C , a step of forming a first mask 60 having a predetermined pattern is performed (step S6 in FIG. 38 ). The first mask 60 is preferably an organic mask (resist mask). The first mask 60 is disposed on the upper end of the first layer 8 and has a plurality of first openings 61 that expose regions of the first layer 8 where the plurality of first regions 14 are to be formed. The plurality of first openings 61 are formed at intervals in the first arrangement direction Da1 and are each partitioned into strips extending in the first extension direction De1.

[0387] 39D , a step of forming a plurality of first regions 14 is performed (step S7 in FIG. 38 ). The step of forming the plurality of first regions 14 includes a channeling implantation step of a trivalent element (p-type impurity) into the first layer 8. The first layer 8 (wafer 50) has an off angle θ inclined at a predetermined angle in a predetermined off direction D with respect to the first wafer main surface 51. The channeling implantation step is performed based on data (information) of the off angle θ.

[0388] 41A , in the random implantation method, a trivalent element is introduced into the first layer 8 with a predetermined implantation energy in a direction intersecting the first axial channel CH1 (off angle θoff) (see also FIG. 12 ). For example, in the random implantation method, the trivalent element is implanted along the vertical direction Z perpendicular to the upper end (first wafer main surface 51) of the first layer 8.

[0389] In the case of random implantation, the trivalent element is introduced along a direction in which atomic rows are relatively dense in a plan view, and therefore the trivalent element collides with the atomic rows at a relatively shallow depth. Therefore, the atomic rows hinder the introduction of the trivalent element into a relatively deep depth of the first layer 8. As a result, the first region 14 without the slow portion 22 is formed (see also FIG. 12 ).

[0390] 41B , in the channeling implantation method, the implantation angle of the trivalent element with respect to the first layer 8 is controlled, and the trivalent element is introduced into the first layer 8 along the first axial channel CH1 (in this embodiment, the c-axis of the SiC single crystal) with a predetermined implantation energy (see also FIGS. 11A to 11E ). In this case, either or both of the implantation angle of the trivalent element with respect to the first layer 8 and the tilt angle of the first layer 8 with respect to the implantation angle of the trivalent element are adjusted.

[0391] For example, the wafer 50 may be supported horizontally, and the trivalent element may be introduced into the first layer 8 along the first axial channel CH1. Of course, the wafer 50 may be supported in a state tilted by the off angle θoff from the horizontal, and the trivalent element may be introduced into the first layer 8 along the first axial channel CH1. By selecting any combination of the implantation energy of the trivalent element and the implantation temperature of the trivalent element (temperature of the wafer 50), a plurality of first regions 14 having a predetermined thickness are formed at predetermined depth positions (see also FIGS. 11A to 11E ).

[0392] The implantation energy of the trivalent element may be 100 KeV to 2000 KeV, or may have a value belonging to any one of the ranges of 100 KeV to 250 KeV, 250 KeV to 500 KeV, 500 KeV to 750 KeV, 750 KeV to 1000 KeV, 1000 KeV to 1250 KeV, 1250 KeV to 1500 KeV, 1500 KeV to 1750 KeV, and 1750 KeV to 2000 KeV.

[0393] The implantation temperature of the trivalent element may be adjusted in the range of 0° C. to 1500° C. The implantation temperature may have a value belonging to any one of the ranges of 0° C. to 25° C., 25° C. to 50° C., 50° C. to 100° C., 100° C. to 250° C., 250° C. to 500° C., 500° C. to 750° C., 750° C. to 1000° C., 1000° C. to 1250° C., and 1250° C. to 1500° C.

[0394] The implantation angle of the trivalent element is preferably set within a range of ±2° with respect to the axis along the first axial channel CH1 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°). The implantation angle of the trivalent element is particularly preferably set within a range of ±1° with respect to the axis along the first axial channel CH1 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°).

[0395] In the case of the channeling implantation method, the trivalent element is introduced along the first axial channel CH1 in which the atomic rows are relatively sparse in a plan view. The trivalent element travels through the first axial channel CH1 while repeatedly undergoing small-angle scattering due to the channeling effect, and reaches a relatively deep position in the first layer 8. In other words, in the case of the channeling implantation method, the probability of the trivalent element colliding with the atomic rows of the SiC single crystal is reduced.

[0396] In this case, it is preferable that a trivalent element that is heavier than carbon is introduced into the first layer 8. That is, it is preferable that the trivalent element is a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the trivalent element is aluminum.

[0397] The first extension direction De1 may be the a-axis direction or the m-axis direction. The first extension direction De1 may be a direction other than the a-axis direction or the m-axis direction. When the first extension direction De1 coincides with the m-axis direction (see also FIG. 6A ), the trivalent element is introduced into the first layer 8 through the multiple first openings 61 at an angle approximately equal to the off angle θoff with respect to the upper end of the first layer 8 in a cross-sectional view along the first arrangement direction Da1.

[0398] When the first extension direction De1 coincides with the a-axis direction (off direction Doff) (see also FIG. 8A , etc.), the trivalent element is introduced into the first layer 8 through the multiple first openings 61 substantially perpendicular to the upper end of the first layer 8 in a cross-sectional view along the first arrangement direction Da1. This prevents the multiple first regions 14 from being formed in the first layer 8 at an angle. Furthermore, the wall surfaces of the multiple first openings 61 are prevented from acting as a shield against the incident path of the trivalent element.

[0399] When the first extension direction De1 is a direction other than the a-axis direction and the m-axis direction (see also Figures 10A to 10C, etc.), there is no need to strictly control the alignment misalignment of the multiple first regions 14 with respect to the crystal orientation of the SiC single crystal.

[0400] After the step of implanting the trivalent element, an annealing method may be used to electrically activate the trivalent element and simultaneously repair lattice defects and the like that have occurred in the first layer 8. The annealing temperature for the first layer 8 may be 500° C. or higher and 2000° C. or lower. This results in the formation of the plurality of first regions 14 and the first superjunction structure SJ1 at the same time. After the step of forming the plurality of first regions 14, the first mask 60 is removed.

[0401] Next, a determination step is performed as to whether or not a thickness adjustment step of the first layer 8 is to be performed (step S8 in FIG. 38). If the thickness of the first layer 8 is to be adjusted (step S8 in FIG. 38: YES), the first layer 8 is thinned from the upper end side (step S9 in FIG. 38).

[0402] The thickness adjusting step (thinning step) may include a step of partially removing an upper end portion of the first layer 8 by a grinding method. The grinding method may be a mechanical polishing method and / or a chemical mechanical polishing method. The thickness adjusting step may include a step of partially removing an upper end portion of the first layer 8 by an etching method. The etching method may be a wet etching method and / or a dry etching method.

[0403] The thickness adjusting step may include a step of exposing the plurality of first regions 14 from the upper end of the first layer 8 (see also FIGS. 25 to 28, etc.). That is, the thickness adjusting step may include a step of removing part or all of the first gradually increasing portions 20A of the plurality of first regions 14. If the thickness adjusting step is not performed (step S8 in FIG. 38: NO), this step is omitted.

[0404] Next, a determination step is performed as to whether a step of forming a plurality of intermediate regions 25 (see also FIGS. 23 and 24 ) is to be performed (step S10 in FIG. 38 ). If a plurality of intermediate regions 25 are to be formed (step S10 in FIG. 38 : YES), the plurality of intermediate regions 25 are formed in the surface layer portion of the first layer 8 (step S11 in FIG. 38 ).

[0405] The step of forming the plurality of intermediate regions 25 includes a step of placing a mask (not shown) having a predetermined pattern on the upper end of the first layer 8. The mask (not shown) is preferably an organic mask (resist mask). The mask (not shown) has a plurality of openings that expose the regions of the first layer 8 where the plurality of first regions 14 are formed. The plurality of openings are formed at intervals in the first direction X and are each partitioned into strips extending in the second direction Y.

[0406] The step of forming the plurality of intermediate regions 25 includes a step of doping the trivalent element into the first layer 8 by random implantation through a mask (not shown) in a direction intersecting the first axial channel CH1 (off angle θ) with a predetermined implantation energy (see also FIG. 12 ). The trivalent element may be doped into the first layer 8 once or multiple times.

[0407] When the trivalent element is introduced multiple times, the trivalent element may be introduced in multiple stages at different depths of the first layer 8 using multiple implantation energies. After the process of forming the multiple intermediate regions 25, the mask (not shown) is removed. If the aforementioned process of adjusting the thickness of the first layer 8 is not performed, the process of forming the multiple intermediate regions 25 may be performed consecutively from the process of forming the multiple first regions 14. In this case, the multiple intermediate regions 25 may be formed using the aforementioned first mask 60.

[0408] 39E, a step of forming second layer 9 is performed (step S12 in FIG. 38). Second layer 9 is formed by epitaxial growth starting from first layer 8. Thereafter, a step of measuring the crystal orientation (off-angle θoff) of second layer 9 may be performed by a method similar to step S4 in FIG. 38 (also see FIGS. 40A and 40B).

[0409] Next, referring to FIG. 39F , a step of forming a second mask 62 having a predetermined pattern is performed (step S13 in FIG. 38 ). The second mask 62 is preferably an organic mask (resist mask). The second mask 62 is disposed on the upper end of the first layer 8 and has a plurality of second openings 63 that expose regions of the first layer 8 in which the plurality of second regions 15 are to be formed. The second openings 63 are formed at intervals in a second arrangement direction Da2 that is different from the first arrangement direction Da1, and are each partitioned into strips extending in a second extension direction De2 that is different from the first extension direction De1.

[0410] 39G , a step of forming a plurality of second regions 15 is performed (step S14 in FIG. 38 ). The step of forming a plurality of second regions 15 includes a channeling implantation step of a trivalent element (p-type impurity) into second layer 9. The channeling implantation step is performed based on the data (information) of the off angle θoff described above.

[0411] In the channeling implantation method, the implantation angle of the trivalent element with respect to the second layer 9 is controlled, and the trivalent element is introduced into the second layer 9 along the second axial channel CH2 (in this embodiment, the c-axis of the SiC single crystal) with a predetermined implantation energy (see also FIGS. 11A to 11E). In this case, either or both of the implantation angle of the trivalent element with respect to the second layer 9 and the tilt angle of the second layer 9 with respect to the implantation angle of the trivalent element are adjusted.

[0412] For example, the wafer 50 may be supported horizontally, and the trivalent element may be introduced into the second layer 9 along the second axial channel CH2. Of course, the wafer 50 may be supported in a state inclined by the off angle θoff with respect to the horizontal, and the trivalent element may be introduced into the second layer 9 along the second axial channel CH2. By selecting any combination of the implantation energy of the trivalent element and the implantation temperature of the trivalent element, a plurality of second regions 15 having a predetermined thickness are formed at predetermined depth positions (see also FIGS. 11A to 11E ).

[0413] The implantation energy of the trivalent element may be 100 KeV to 2000 KeV, or may have a value belonging to any one of the ranges of 100 KeV to 250 KeV, 250 KeV to 500 KeV, 500 KeV to 750 KeV, 750 KeV to 1000 KeV, 1000 KeV to 1250 KeV, 1250 KeV to 1500 KeV, 1500 KeV to 1750 KeV, and 1750 KeV to 2000 KeV.

[0414] The implantation energy for the second region 15 may be approximately equal to or different from the implantation energy for the first region 14. The implantation energy for the second region 15 may be equal to or greater than the implantation energy for the first region 14. Alternatively, the implantation energy for the second region 15 may be less than the implantation energy for the first region 14.

[0415] The implantation temperature of the trivalent element may be adjusted in the range of 0° C. to 1500° C. The implantation temperature may have a value belonging to any one of the ranges of 0° C. to 25° C., 25° C. to 50° C., 50° C. to 100° C., 100° C. to 250° C., 250° C. to 500° C., 500° C. to 750° C., 750° C. to 1000° C., 1000° C. to 1250° C., and 1250° C. to 1500° C.

[0416] The implantation temperature for the second region 15 may be approximately equal to or different from the implantation temperature for the first region 14. The implantation temperature for the second region 15 may be equal to or higher than the implantation temperature for the first region 14. Alternatively, the implantation temperature for the second region 15 may be lower than the implantation temperature for the first region 14.

[0417] The implantation angle of the trivalent element is preferably set within a range of ±2° with respect to the axis along the second axial channel CH2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°). The implantation angle of the trivalent element is particularly preferably set within a range of ±1° with respect to the axis along the second axial channel CH2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°).

[0418] In the case of the channeling implantation method, the trivalent element is introduced along the second axial channel CH2 in which the atomic rows are relatively sparse in a plan view. The trivalent element travels through the second axial channel CH2 while repeatedly undergoing small-angle scattering due to the channeling effect, and reaches a relatively deep position in the second layer 9. In other words, in the case of the channeling implantation method, the probability of the trivalent element colliding with the atomic rows of the SiC single crystal is reduced.

[0419] In this case, it is preferable that a trivalent element that is heavier than carbon is introduced into the second layer 9. That is, it is preferable that the trivalent element is a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the trivalent element is aluminum.

[0420] The second extension direction De2 may be the a-axis direction or the m-axis direction. The second extension direction De2 may be a direction other than the a-axis direction or the m-axis direction. When the second extension direction De2 coincides with the a-axis direction (off direction Doff) (see also FIG. 6A ), the trivalent element is introduced into the second layer 9 through the second openings 63 approximately perpendicular to the upper end of the second layer 9 in a cross-sectional view along the second arrangement direction Da2. This prevents the second regions 15 from being formed in an inclined position in the second layer 9. Furthermore, the wall surfaces of the second openings 63 are prevented from blocking the incident path of the trivalent element.

[0421] When the second extension direction De2 coincides with the m-axis direction (see also Figure 8A, etc.), the trivalent element is introduced into the second layer 9 through multiple second openings 63 at an angle of approximately the off angle θoff relative to the upper end of the second layer 9 in a cross-sectional view along the second arrangement direction Da2.

[0422] When the second extension direction De2 is a direction other than the a-axis direction and the m-axis direction (see also Figures 10A to 10C, etc.), there is no need to strictly control the alignment misalignment of the multiple second regions 15 with respect to the crystal orientation of the SiC single crystal.

[0423] When the first extension direction De1 of the first regions 14 is a direction other than the a-axis direction and the m-axis direction, it is preferable that the second extension direction De2 is also a direction other than the a-axis direction and the m-axis direction. In this case, the first regions 14 have a first extension angle θ1 inclined toward one side of the m-axis with respect to the a-axis, and the second regions 15 have a second extension angle θ2 inclined toward the other side of the m-axis with respect to the a-axis.

[0424] The absolute value of the second extension angle θ2 may be different from the absolute value of the first extension angle θ1. In this case, however, the condition of the relative implantation angle of the trivalent element in the step of forming the second region 15 is different from the condition of the relative implantation angle of the trivalent element in the step of forming the first region 14. Therefore, the shielding area of ​​the plurality of second openings 63 with respect to the incident path of the trivalent element is different from the shielding area of ​​the plurality of first openings 61 with respect to the incident path of the trivalent element.

[0425] That is, the process error of the second regions 15 caused by the shadowing of the second openings 63 is different from the process error of the first regions 14 caused by the shadowing of the first openings 61. Therefore, it is preferable that the absolute value of the second extension angle θ2 is approximately equal to the absolute value of the first extension angle θ1. In this case, the process error of the second regions 15 is approximately equal to the process error of the first regions 14. Therefore, the accuracy of charge balance is improved.

[0426] For example, the first extension angle θ1 may be +45°±5° and the second extension angle θ2 may be −45°±5° (see FIG. 10A). For example, the first extension angle θ1 may be +30°±5° and the second extension angle θ2 may be −30°±5° (see FIG. 10B). For example, the first extension angle θ1 may be +60°±5° and the second extension angle θ2 may be −60°±5° (see FIG. 10C).

[0427] After the step of implanting the trivalent element, an annealing method may be performed to electrically activate the trivalent element and simultaneously repair lattice defects and the like that have occurred in the second layer 9. The annealing temperature for the second layer 9 may be 500°C or higher and 2000°C or lower. As a result, the second superjunction structure SJ2 is formed simultaneously with the formation of the plurality of second regions 15. The annealing method for the plurality of second regions 15 may also serve as the annealing method for the plurality of first regions 14 described above. In this case, the annealing method for the plurality of first regions 14 before the step of forming the second regions 15 may be omitted.

[0428] Next, a determination step is performed as to whether or not a thickness adjustment step of the second layer 9 is to be performed (step S15 in FIG. 38). If the thickness of the second layer 9 is to be adjusted (step S15 in FIG. 38: YES), the second layer 9 is thinned from the upper end side (step S16 in FIG. 38).

[0429] The thickness adjustment step (thinning step) may include a step of partially removing an upper end portion of the second layer 9 by a grinding method. The grinding method may be a mechanical polishing method and / or a chemical mechanical polishing method. The thinning step of the second layer 9 may include a step of partially removing an upper end portion of the second layer 9 by an etching method. The etching method may be a wet etching method and / or a dry etching method.

[0430] The thickness adjusting step may include a step of exposing the plurality of second regions 15 from the upper end of the second layer 9 (see also FIGS. 25 to 28, etc.). That is, the thickness adjusting step may include a step of removing part or all of the second gradually increasing portions 20B of the plurality of second regions 15. If the thickness adjusting step is not performed (step S15 in FIG. 38: NO), this step is omitted.

[0431] Next, a determination step is performed as to whether or not a further superjunction structure SJ is to be formed on the second layer 9 (step S17 in FIG. 38 ). For example, if a third superjunction structure SJ3 (see also FIG. 31 ) is to be formed (step S17 in FIG. 38 : YES), a third layer 27 is formed on the second layer 9 through steps similar to steps S12 to S14 in FIG. 38 , and a plurality of third regions 28 are formed in the third layer 27 (step S18 in FIG. 38 ).

[0432] Of course, prior to the step of forming the further superjunction structure SJ, a plurality of intermediate regions 25 may be formed in the surface layer portion of the second layer 9 through a step similar to step S11 in Fig. 38 (see also Figs. 23 and 24). If the step of forming the further superjunction structure SJ is not performed (step S17 in Fig. 38: NO), this step is omitted.

[0433] Next, a determination step is performed as to whether or not a step of forming the top layer 30 (see also FIG. 32 ) is to be performed (step S19 in FIG. 38 ). If the step of forming the top layer 30 is to be performed (step S19 in FIG. 38 : YES), the top layer 30 is formed starting from the second layer 9 by epitaxial growth (step S20 in FIG. 38 ). If the step of forming the top layer 30 is not to be performed (step S19 in FIG. 38 : NO), this step is omitted.

[0434] Thereafter, the MIS structure 31, a plurality of field regions 38, the interlayer insulating film 40, the gate pad 45, the gate wiring 46, the source pad 47, the drain pad 48, etc. are formed (step S21 in FIG. 38 ). Then, the wafer 50 is cut along a plurality of cutting lines 56. In this way, a plurality of SiC semiconductor devices 1A are manufactured from one wafer 50.

[0435] The various determination steps described above (steps S2, S8, S10, S15, S17, and S19 in FIG. 38 ) may be determined in advance in the step of preparing wafer 50 (step S1 in FIG. 38 ). In other words, SiC semiconductor device 1A may be manufactured along a predetermined manufacturing line.

[0436] Fig. 42 is a plan view showing a SiC semiconductor device 1B according to a second embodiment. Fig. 43 is a cross-sectional view taken along line XLIII-XLIII shown in Fig. 42. Fig. 44 is a plan view showing an example layout of chip 2. Fig. 45 is a perspective view showing an example layout of chip 2.

[0437] 42 to 45, SiC semiconductor device 1B includes chip 2, base layer 6, stacked portion 7 (first layer 8 and second layer 9), active region 10 and peripheral region 11, similar to SiC semiconductor device 1A.

[0438] In this embodiment, the SiC semiconductor device 1B includes an active surface 71, an outer surface 72, and first to fourth connecting surfaces 73A to 73D formed on the first main surface 3. The active surface 71, the outer surface 72, and the first to fourth connecting surfaces 73A to 73D define an active plateau 74 on the first main surface 3.

[0439] The active surface 71 may be referred to as a “first surface portion,” the outer peripheral surface 72 may be referred to as a “second surface portion,” the first to fourth connecting surfaces 73A to 73D may be referred to as “connecting surface portions,” and the active plateau 74 may be referred to as a “mesa portion.” The active surface 71, the outer peripheral surface 72, and the first to fourth connecting surfaces 73A to 73D (i.e., the active plateau 74) may be considered to be components of the chip 2 (first main surface 3).

[0440] The active surface 71 is formed in the active region 10. That is, the active surface 71 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 71 has a flat surface extending in the first direction X and the second direction Y. In this embodiment, the active surface 71 is formed by the c-plane (Si-plane). In this embodiment, the active surface 71 is formed in a quadrilateral shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0441] The outer peripheral surface 72 is formed in the outer peripheral region 11. In other words, the outer peripheral surface 72 is formed outside the active surface 71. The outer peripheral surface 72 is recessed in the thickness direction of the chip 2 (toward the second main surface 4) with respect to the active surface 71. Specifically, in this embodiment, the outer peripheral surface 72 is recessed to a depth less than the thickness of the second layer 9 so as to expose the second layer 9. The outer peripheral surface 72 extends in a band shape along the active surface 71 in a plan view, and is formed in a ring shape (specifically, a square ring) surrounding the active surface 71.

[0442] The outer peripheral surface 72 has a flat surface extending in the first direction X and the second direction Y, and is formed substantially parallel to the active surface 71. In this embodiment, the outer peripheral surface 72 is formed by the c-plane (Si-plane). The outer peripheral surface 72 is continuous with the first to fourth side surfaces 5A to 5D. The outer peripheral surface 72 has a circumferential depth DO.

[0443] The peripheral depth DO may be 0.1 μm or more and 2 μm or less. The peripheral depth DO may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less. The peripheral depth DO is preferably 0.1 μm or more and 1.5 μm or less.

[0444] The first to fourth connection surfaces 73A to 73D extend in the vertical direction Z and connect the active surface 71 and the outer peripheral surface 72. The first connection surface 73A is located on the first side surface 5A side, the second connection surface 73B is located on the second side surface 5B side, the third connection surface 73C is located on the third side surface 5C side, and the fourth connection surface 73D is located on the fourth side surface 5D side. The first connection surface 73A and the third connection surface 73C extend in the first direction X and face the second direction Y. The second connection surface 73B and the fourth connection surface 73D extend in the second direction Y and face the first direction X.

[0445] The first to fourth connection surfaces 73A to 73D may extend substantially perpendicularly between the active surface 71 and the outer peripheral surface 72 so as to define a quadrangular pillar-shaped active plateau 74. The first to fourth connection surfaces 73A to 73D may be inclined obliquely downward from the active surface 71 toward the outer peripheral surface 72 so as to define a quadrangular pyramid-shaped active plateau 74. In this manner, the active plateau 74 is defined in a protruding shape on the second layer 9 on the first main surface 3. The active plateau 74 is formed only on the second layer 9, and not on the first layer 8.

[0446] The SiC semiconductor device 1B includes a p-type column region 12 formed in the stack portion 7 in the active region 10. The column region 12 is formed in the same layout as that of the SiC semiconductor device 1A. That is, the multiple first regions 14 are formed in the first layer 8 in the same layout as the multiple first regions 14 in the SiC semiconductor device 1A, and define multiple first drift regions 16. The multiple second regions 15 are formed in the second layer 9 in the same layout as the multiple second regions 15 in the SiC semiconductor device 1A, and define multiple second drift regions 17.

[0447] The column region 12 may have at least one of the features shown in the first to twelfth embodiments. The column region 12 may also have a feature that is a combination of a plurality (two or more) of the features shown in the first to twelfth embodiments.

[0448] In this embodiment, the multiple first regions 14 are each formed within an area surrounded by the periphery of the active surface 71 (the first to fourth connecting surfaces 73A to 73D) in a plan view. The multiple first regions 14 may be formed at intervals inward from the periphery of the active surface 71 in a plan view. Of course, the multiple first regions 14 may also be exposed from the first to fourth connecting surfaces 73A to 73D. It is preferable that the first upper ends 14b of the multiple first regions 14 are formed at intervals toward the lower end of the first layer 8 relative to the depth position of the outer circumferential surface 72.

[0449] In this embodiment, the second regions 15 are each formed within an area surrounded by the periphery of the active surface 71 (the first to fourth connecting surfaces 73A to 73D) in a plan view. The second regions 15 may be formed at intervals inward from the periphery of the active surface 71 in a plan view. Of course, the second regions 15 may be exposed from the first to fourth connecting surfaces 73A to 73D.

[0450] The second lower ends 15 a of the second regions 15 are preferably located in a region closer to the lower end of the second layer 9 than the depth position of the outer peripheral surface 72 in the thickness direction of the second layer 9. The second upper ends 15 b of the second regions 15 are preferably located in a region closer to the active surface 71 than the outer peripheral surface 72 in the thickness direction of the second layer 9.

[0451] Fig. 46 is a plan view showing a main part of active region 10. Fig. 47 is a cross-sectional perspective view showing gate structure 35 according to the first embodiment. With reference to Figs. 46 and 47, SiC semiconductor device 1B includes MIS structure 31 formed in active region 10. The following configurations will be described as components of SiC semiconductor device 1B, but are also components of MIS structure 31.

[0452] The SiC semiconductor device 1B includes a p-type body region 32 formed in a surface layer portion of the first main surface 3 (active surface 71). In this embodiment, the body region 32 is formed in a layer shape extending along the active surface 71. The body region 32 may be formed over the entire active surface 71 and exposed from the first to fourth connection surfaces 73A to 73D.

[0453] The body region 32 is formed at a distance from the lower end of the second layer 9 toward the active surface 71, and overlaps the column region 12 (the plurality of second regions 15) in the stacking direction. The body region 32 is preferably formed at a distance from the depth position of the outer circumferential surface 72 toward the active surface 71, and is exposed from the first main surface 3. When the plurality of second regions 15 are formed at a distance from the first main surface 3, the body region 32 is formed in a region between the active surface 71 and the second upper ends 15b of the plurality of second regions 15. The body region 32 is preferably connected to the plurality of second regions 15 (the second upper ends 15b).

[0454] The body region 32 is made of a random impurity region introduced into a surface portion of the second layer 9 by random implantation into the second layer 9 (see also FIG. 12 ). Therefore, the body region 32 has a thickness along the second axial channel CH2 that is less than the second region thickness TR2 of the second region 15. The thickness of the body region 32 is less than the first region thickness TR1 of the first region 14.

[0455] Unlike the second region 15 and the like, the body region 32 does not have a gradual portion 22 having a thickness of 0.5 μm or more, but has a concentration gradient including a gradually increasing portion 20, a peak portion 21, and a gradually decreasing portion 23 within a range of 0.5 μm. １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0456] The p-type impurity concentration of the body region 32 is preferably adjusted by at least one trivalent element. The trivalent element of the body region 32 may be the same as or different from the trivalent element of the second region 15, etc. The trivalent element of the body region 32 may be at least one of boron, aluminum, gallium, and indium. Of course, the body region 32 may be formed by utilizing a part of the p-type top layer 30.

[0457] The SiC semiconductor device 1B includes a plurality of trench electrode-type gate structures 35 formed on the first main surface 3 (active surface 71) in the active region 10. The gate structures 35 may also be referred to as "trench gate structures." A gate potential is applied to the plurality of gate structures 35 as a control potential. The plurality of gate structures 35 control inversion and non-inversion of a channel (current path) in the body region 32 in response to the gate potential.

[0458] The multiple gate structures 35 are arranged inwardly from the periphery (first to fourth connection surfaces 73A to 73D) of the active surface 71 in the active region 10 at intervals. In this embodiment, the multiple gate structures 35 are arranged at intervals in the second array direction Da2 and are each formed in a strip shape extending in the second extension direction De2. That is, in this embodiment, the multiple gate structures 35 are arranged in stripes extending along the multiple second regions 15 and intersect with the multiple first regions 14 and the multiple first drift regions 16 in the stacking direction.

[0459] In this example, the second arrangement direction Da2 is the m-axis direction (first direction X), and the second extension direction De2 is the a-axis direction (second direction Y). Of course, the arrangement direction and extension direction of the multiple gate structures 35 are changed depending on the second arrangement direction Da2 and second extension direction De2 of the multiple second regions 15. Therefore, the second arrangement direction Da2 may be the a-axis direction, and the second extension direction De2 may be the m-axis direction. Alternatively, the second arrangement direction Da2 may be a direction other than the a-axis direction and the m-axis direction, and the second extension direction De2 may be a direction other than the a-axis direction and the m-axis direction.

[0460] In this embodiment, the multiple gate structures 35 are arranged shifted toward the multiple second drift regions 17 from the multiple second regions 15. Specifically, the multiple gate structures 35 penetrate the body region 32 at intervals from the multiple second regions 15, and are arranged in a one-to-one correspondence within the multiple second drift regions 17. In other words, the multiple gate structures 35 are arranged alternately with the multiple second regions 15 along the second array direction Da2, and face the multiple second regions 15 in the horizontal direction.

[0461] The multiple gate structures 35 are formed at intervals from the lower ends of the multiple second drift regions 17 toward the active surface 71, and face the multiple first regions 14 and the multiple first drift regions 16 across parts of the multiple second drift regions 17. The multiple gate structures 35 are preferably formed at intervals from intermediate portions of the thickness ranges of the multiple second regions 15 toward the active surface 71. Of course, the multiple gate structures 35 may also be formed at depth positions that cross the intermediate portions of the thickness ranges of the multiple second regions 15.

[0462] Each gate structure 35 has a trench width WT in the arrangement direction (first direction X in this embodiment) and a trench depth DT in the vertical direction Z. The trench width WT is less than the second pitch P2 (first pitch P1). The trench depth DT is less than the second thickness T2 of the second layer 9. It is preferable that the trench depth DT is approximately equal to the aforementioned periphery depth DO. Of course, the trench depth DT may be greater than or less than the periphery depth DO.

[0463] The trench width WT may be 0.1 μm or more and 5 μm or less. The trench width WT may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0464] The trench depth DT may be 0.1 μm or more and 5 μm or less. The trench depth DT may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less. The trench depth DT is preferably 0.1 μm or more and 1.5 μm or less.

[0465] Each gate structure 35 includes a trench 75, an insulating film 76, and a buried electrode 77. The trench 75 is formed in the active surface 71 and defines the wall surface of the gate structure 35. The insulating film 76 covers the wall surface of the trench 75. The insulating film 76 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0466] In this embodiment, the insulating film 76 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 76 includes a silicon oxide film made of an oxide of the chip 2. The buried electrode 77 is buried in the trench 75 with the insulating film 76 therebetween and faces the channel with the insulating film 76 therebetween. The buried electrode 77 may include p-type or n-type conductive polysilicon.

[0467] The SiC semiconductor device 1B includes a plurality of source regions 33 formed on both sides of a plurality of gate structures 35 in a surface layer portion of the first main surface 3 (active surface 71). The plurality of source regions 33 are formed in a surface layer portion of the body region 32. The plurality of source regions 33 have a higher n-type impurity concentration (peak value) than the second layer 9 (second drift region 17). The plurality of source regions 33 have a concentration of n-type impurities (peak value) of 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0468] The plurality of source regions 33 extend in a strip shape along the corresponding gate structures 35 in a plan view. The plurality of source regions 33 are formed at intervals from the bottom of the body region 32 toward the active surface 71, and face the second drift region 17 across a part of the body region 32 in the stacking direction. The plurality of source regions 33, together with the plurality of second drift regions 17 located directly below, define channels (current paths) that extend along the wall surfaces of the corresponding gate structures 35.

[0469] The plurality of source regions 33 may face the second region 15 across a part of the body region 32 in the stacking direction. Of course, the plurality of source regions 33 may be formed at intervals from the second region 15 toward the second drift region 17 (the gate structure 35 side) so as not to face the second region 15 in the stacking direction.

[0470] The SiC semiconductor device 1A includes a plurality of contact regions 34 formed in regions between a plurality of gate structures 35 in a surface layer portion of the first main surface 3 (active surface 71). The plurality of contact regions 34 are formed in a surface layer portion of the body region 32.

[0471] The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 32. The p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of second regions 15. The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of second regions 15. １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0472] The plurality of contact regions 34 are interposed in regions between the plurality of adjacent source regions 33 and extend in strip shapes along the plurality of gate structures 35. The plurality of contact regions 34 are formed at intervals from the bottom of the body region 32 toward the active surface 71, and face the plurality of second regions 15 with a part of the body region 32 sandwiched therebetween in the stacking direction.

[0473] The plurality of contact regions 34 may face the second drift region 17 across a part of the body region 32 in the stacking direction. Of course, the plurality of contact regions 34 may be formed at intervals from the second drift region 17 toward the second region 15 so as not to face the second drift region 17 in the stacking direction.

[0474] The configuration on the side of outer periphery region 11 will be described below. Fig. 48 is a cross-sectional view showing a main portion of outer periphery region 11. Referring to Fig. 48, SiC semiconductor device 1B includes p-type well region 78 formed in a surface layer portion of outer periphery surface 72. Well region 78 is formed at an interval from the periphery of outer periphery surface 72 (first to fourth side surfaces 5A to 5D) toward active surface 71 in a plan view, and extends in a band shape along active surface 71.

[0475] In this embodiment, the well region 78 is formed in a ring shape (specifically, a rectangular ring shape) surrounding the active surface 71 in a plan view. The well region 78 is drawn out from the surface portion of the outer circumferential surface 72 toward the first to fourth connection surfaces 73A to 73D, and extends along the surface portions of the first to fourth connection surfaces 73A to 73D. The well region 78 is electrically connected to the body region 32 in the surface portion of the active surface 71. The well region 78 is formed at a distance from the lower end of the second layer 9 toward the outer circumferential surface 72, and faces the first layer 8 with a portion of the second layer 9 sandwiched therebetween.

[0476] The bottom of the well region 78 is located closer to the lower end of the second layer 9 than the bottom wall of the gate structure 35. The bottom of the well region 78 is preferably located closer to the outer circumferential surface 72 than the second lower ends 15a of the second regions 15. It is particularly preferable that the bottom of the well region 78 is located closer to the outer circumferential surface 72 than the thickness range intermediate portions of the second regions 15.

[0477] The well region 78 is made of a random impurity region introduced into the surface layer of the second layer 9 by random implantation into the second layer 9 (see also FIG. 12 ). Therefore, the well region 78 has a thickness along the second axial channel CH2 that is less than the second region thickness TR2 of the second region 15. The thickness of the well region 78 is less than the first region thickness TR1 of the first region 14.

[0478] Unlike the second region 15 and the like, the well region 78 does not have a gradual portion 22 having a thickness of 0.5 μm or more, and has a concentration gradient including a gradually increasing portion 20, a peak portion 21, and a gradually decreasing portion 23 within a range of 0.5 μm. １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0479] The well region 78 has a p-type impurity concentration lower than the p-type impurity concentration of the contact region 34. The p-type impurity concentration of the well region 78 is higher than the p-type impurity concentration of the body region 32. Of course, the p-type impurity concentration of the well region 78 may be lower than that of the body region 32. The well region 78 forms a pn junction with the second layer 9.

[0480] The p-type impurity concentration of well region 78 is preferably adjusted by at least one trivalent element. The trivalent element of well region 78 may be the same as the trivalent element of second region 15, etc., or may be a different species from the trivalent element of second region 15, etc. The trivalent element of well region 78 may be at least one of boron, aluminum, gallium, and indium.

[0481] SiC semiconductor device 1B includes at least one (preferably two or more and 20 or less) p-type field region 38 formed in the surface layer portion of outer peripheral surface 72 in outer peripheral region 11. The multiple field regions 38 are formed in the surface layer portion of outer peripheral surface 72 in the same manner as in SiC semiconductor device 1A.

[0482] In this embodiment, the field regions 38 are arranged at intervals from the periphery (first to fourth connection surfaces 73A to 73D) of the active surface 71 and the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. Specifically, the field regions 38 are arranged at intervals from the well region 78 toward the periphery of the outer circumferential surface 72.

[0483] The field regions 38 extend in a strip shape along the active surface 71 in a plan view and are formed in a ring shape (specifically, a square ring shape) surrounding the active surface 71. The field regions 38 are formed at intervals from the bottom of the second layer 9 toward the outer peripheral surface 72, and face the first layer 8 with part of the second layer 9 in between. The field regions 38 are located closer to the lower end of the second layer 9 than the bottom of the gate structure 35.

[0484] The SiC semiconductor device 1B includes the aforementioned interlayer insulating film 40 that covers the first main surface 3. The interlayer insulating film 40 has a layered structure including a first insulating film 41 and a second insulating film 42. In this embodiment, the first insulating film 41 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connecting surfaces 73A to 73D. The first insulating film 41 is connected to an insulating film 76 on the active surface 71, exposing the buried electrode 77.

[0485] The first insulating film 41 covers the well region 78 and the plurality of field regions 38 on the outer peripheral surface 72. In this embodiment, the first insulating film 41 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the first insulating film 41 may be formed at an interval inward from the periphery of the outer peripheral surface 72, with the second layer 9 exposed from the periphery of the outer peripheral surface 72. The first insulating film 41 covers the well region 78 on the first to fourth connection surfaces 73A to 73D.

[0486] In this embodiment, the second insulating film 42 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connection surfaces 73A to 73D, sandwiching the first insulating film 41 therebetween. The second insulating film 42 covers the plurality of gate structures 35 in the active region 10. The second insulating film 42 covers the plurality of field regions 38 and well regions 78 in the outer peripheral region 11, sandwiching the first insulating film 41 therebetween. In this embodiment, the second insulating film 42 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the second insulating film 42 may be formed spaced inward from the periphery of the outer peripheral surface 72, so that the second layer 9, together with the first insulating film 41, is exposed from the periphery of the outer peripheral surface 72.

[0487] The SiC semiconductor device 1A includes a plurality of contact openings 43 formed in the interlayer insulating film 40. The plurality of contact openings 43 include a plurality of contact openings 43 (not shown) that expose a plurality of gate structures 35 (buried electrodes 77) and a plurality of contact openings 43 that expose a plurality of source regions 33. The plurality of contact openings 43 for the source regions 33 are formed in regions between adjacent plurality of gate structures 35, and expose a plurality of source regions 33 and a plurality of contact regions 34.

[0488] The SiC semiconductor device 1B includes a sidewall structure 79 disposed in the interlayer insulating film 40 so as to cover at least one of the first to fourth connection surfaces 73A to 73D. The sidewall structure 79 is disposed on the first insulating film 41 and is covered by the second insulating film 42. The sidewall structure 79 reduces a step formed between the active surface 71 and the outer peripheral surface 72.

[0489] The sidewall structure 79 is formed in a strip shape extending along at least one of the first to fourth connecting surfaces 73A to 73D. In this embodiment, the sidewall structure 79 is formed in a ring shape (specifically, a rectangular ring shape) extending along the first to fourth connecting surfaces 73A to 73D so as to surround the active surface 71 in a plan view.

[0490] The sidewall structure 79 may have a portion extending in a film-like manner along the outer peripheral surface 72 and a portion extending in a film-like manner along the first to fourth connecting surfaces 73A to 73D. In this embodiment, the sidewall structure 79 is formed at a distance from the innermost field region 38 toward the active surface 71, and faces the well region 78 in the horizontal direction and the stacking direction, with the first insulating film 41 sandwiched therebetween. The sidewall structure 79 may face the body region 32, with the first insulating film 41 sandwiched therebetween.

[0491] Similar to the SiC semiconductor device 1A, the SiC semiconductor device 1B includes a gate pad 45, a plurality of gate wirings 46, a source pad 47, and a drain pad 48. The drain pad 48 is formed in the same form as in the first embodiment.

[0492] In this embodiment, the gate pad 45 is disposed on the active surface 71 at a distance from the outer peripheral surface 72 in a plan view. The gate pad 45 is disposed in a region close to the center of one side of the active surface 71 (the second connection surface 73B in this embodiment) in a plan view. Of course, the gate pad 45 may also be disposed in a corner of the active surface 71 or in the center of the active surface 71 in a plan view.

[0493] In this embodiment, the plurality of gate wirings 46 are arranged on the active surface 71 at intervals from the outer peripheral surface 72 in a plan view. The plurality of gate wirings 46 include a first gate wiring 46A and a second gate wiring 46B.

[0494] The first gate wiring 46A is drawn out from the gate pad 45 toward the first connection surface 73A, and extends in a line along the periphery of the active surface 71 so as to intersect (specifically, orthogonal to) some (specifically, one end) of the multiple gate structures 35. The first gate wiring 46A penetrates the interlayer insulating film 40 via the multiple contact openings 43, and is electrically connected to one end of the multiple gate structures 35 (buried electrodes 77).

[0495] The second gate wiring 46B is drawn out from the gate pad 45 toward the third connection surface 73C and extends in a line along the periphery of the active surface 71 so as to intersect (specifically, orthogonal to) some (specifically, the other ends) of the multiple gate structures 35. The second gate wiring 46B penetrates the interlayer insulating film 40 via the multiple contact openings 43 and is electrically connected to the other ends of the multiple gate structures 35 (buried electrodes 77).

[0496] In this embodiment, the source pad 47 is disposed on the active surface 71 at a distance from the outer peripheral surface 72 in a plan view. The source pad 47 penetrates the interlayer insulating film 40 via a plurality of contact openings 43 and is electrically connected to the body region 32, the plurality of source regions 33, and the plurality of contact regions 34. In other words, the source pad 47 is electrically connected to the column region 12 via the body region 32.

[0497] 49 is a cross-sectional perspective view showing a gate structure 35 according to the second embodiment. The plurality of gate structures 35 according to the first embodiment described above were arranged shifted from the column region 12 (the plurality of second regions 15) toward the plurality of second drift regions 17. In contrast, referring to FIG. 49, the plurality of gate structures 35 according to the second embodiment are arranged so as to overlap the plurality of second regions 15 in the stacking direction. The plurality of gate structures 35 overlap the plurality of second regions 15 in a one-to-one correspondence in the stacking direction.

[0498] The plurality of gate structures 35 each have a bottom wall connected to a corresponding second region 15. Specifically, the plurality of gate structures 35 are formed wider than the corresponding second region 15, and each have a bottom wall connected to the corresponding second region 15 and a side wall connected to the corresponding second drift region 17.

[0499] That is, the buried electrodes 77 face the corresponding second regions 15 across the insulating film 76 in the stacking direction, and face the corresponding second drift regions 17 across the insulating film 76 in the horizontal direction. The aforementioned multiple source regions 33 and multiple contact regions 34 face the corresponding second drift regions 17 across a part of the body region 32 in the stacking direction.

[0500] 50 is a cross-sectional perspective view showing a gate structure 35 according to the third embodiment. The plurality of gate structures 35 according to the third embodiment each have a layout that does not require consideration of misalignment with the plurality of second regions 15.

[0501] 50 , the plurality of gate structures 35 extend in a direction other than the second extension direction De2 so as to intersect with the plurality of second regions 15. In this embodiment, the plurality of gate structures 35 are arranged at intervals in the first arrangement direction Da1 of the first regions 14, and extend in the first extension direction De1 of the first regions 14. In this example, the first arrangement direction Da1 is the a-axis direction (second direction Y), and the first extension direction De1 is the m-axis direction (first direction X).

[0502] The plurality of gate structures 35 may face the plurality of first regions 14 in a one-to-one correspondence in the stacking direction. Of course, each gate structure 35 may face the plurality of first regions 14 in the stacking direction. The plurality of gate structures 35 may face the plurality of first drift regions 16 in a one-to-one correspondence in the stacking direction.

[0503] Of course, each gate structure 35 may face multiple first drift regions 16 in the stacking direction. The multiple gate structures 35 may be arranged shifted from the multiple first regions 14 in the first array direction Da1 and face either one or both of the first regions 14 and the first drift regions 16 in the stacking direction.

[0504] Of course, the arrangement direction and extension direction of the multiple gate structures 35 are changed depending on the first arrangement direction Da1 and first extension direction De1 of the multiple first regions 14. Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Alternatively, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.

[0505] Of course, the arrangement direction of the plurality of gate structures 35 may be a direction other than the first arrangement direction Da1 and the second arrangement direction D2. Furthermore, the extension direction of the plurality of gate structures 35 may be a direction other than the first extension direction De1 and the second extension direction De2. In other words, the plurality of gate structures 35 may intersect both the plurality of first regions 14 and the plurality of second regions 15 in a plan view.

[0506] For example, the angle (absolute value) between the extension direction of the gate structure 35 and the second extension direction De2 may be greater than 0° and less than 90°. The angle (absolute value) of the gate structure 35 may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° to 36°, 36° to 54°, 54° to 72°, and 72° to 90°. The angle (absolute value) of the gate structure 35 may be set to a value belonging to any one of the ranges of 30°±5°, 45°±5°, and 60°±5°.

[0507] In this embodiment, the buried electrode 77 faces the second regions 15 and the second drift regions 17 with the insulating film 76 sandwiched between them in the stacking direction and the horizontal direction. In this embodiment, the source regions 33 and the contact regions 34 face the second regions 15 and the second drift regions 17 with part of the body region 32 sandwiched between them in the stacking direction.

[0508] Fig. 51 is a cross-sectional perspective view showing a gate structure 35 according to the fourth embodiment. Referring to Fig. 51, the plurality of gate structures 35 according to the fourth embodiment each have a configuration that contributes to narrowing the pitch. The plurality of gate structures 35 according to the fourth embodiment are particularly effective in realizing narrower pitches in the column regions 12 (plurality of second regions 15). Fig. 51 shows an example in which the gate structure 35 according to the first embodiment described above is replaced with the gate structure 35 according to the fourth embodiment, but the configuration of the gate structure 35 according to the fourth embodiment is also applicable to the configurations of the gate structures 35 according to the second and third embodiments.

[0509] Each of the multiple gate structures 35 includes a trench 75, an insulating film 76, a buried electrode 77, and a buried insulator 80. The trench 75 has the same configuration as in the first embodiment. In this configuration, the insulating film 76 is formed at a distance from the first main surface 3 (active surface 71) toward the bottom wall of the trench 75, exposing a surface portion of the first main surface 3 (active surface 71) at the opening end of the trench 75. The upper end of the insulating film 76 is preferably located closer to the first main surface 3 than the intermediate depth of the trench 75.

[0510] In this embodiment, the buried electrode 77 is buried in the trench 75 at a distance from the first main surface 3 (active surface 71) toward the bottom wall of the trench 75, and defines an open recess that is recessed toward the bottom wall of the trench 75 at the open end of the trench 75. The buried electrode 77 exposes a surface portion of the first main surface 3 (active surface 71) and an upper end of the insulating film 76 at the open end of the trench 75. The upper end of the buried electrode 77 is preferably located on the first main surface 3 side relative to the intermediate depth range of the trench 75.

[0511] The buried insulator 80 is buried in the trench 75 (open recess) so as to expose the first main surface 3 (active surface 71), and covers the insulating film 76 and the buried electrode 77 within the trench 75. The buried insulator 80 is buried in the trench 75 at a distance from the first main surface 3 (active surface 71) toward the buried electrode 77, and exposes a surface portion of the first main surface 3 (active surface 71) at the open end of the trench 75.

[0512] The upper end of the buried insulator 80 is preferably located closer to the first main surface 3 than the intermediate depth of the trench 75. The buried insulator 80 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The buried insulator 80 preferably includes a silicon oxide film.

[0513] In this embodiment, the aforementioned plurality of source regions 33 are respectively formed in regions between the plurality of adjacent gate structures 35 in the surface layer portion of the first main surface 3 (active surface 71). The plurality of source regions 33 are arranged at intervals along the plurality of gate structures 35 so as to be connected to the plurality of gate structures 35 located on both sides thereof.

[0514] Specifically, the plurality of source regions 33 arranged along one sidewall of the gate structure 35 face in one-to-one correspondence with the plurality of source regions 33 arranged along the other sidewall of the gate structure 35. In other words, the plurality of source regions 33 are arranged in a matrix in plan view.

[0515] Of course, the plurality of source regions 33 on one side may face the regions between the plurality of source regions 33 on the other side in a one-to-one correspondence. That is, the plurality of source regions 33 may be arranged in a staggered pattern in a plan view. The plurality of source regions 33 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the buried electrode 77 and the buried insulator 80 with the insulating film 76 interposed therebetween.

[0516] In this embodiment, the aforementioned plurality of contact regions 34 are formed in regions between adjacent gate structures 35 in the surface layer portion of the first main surface 3 (active surface 71). The plurality of contact regions 34 are arranged at intervals along the plurality of gate structures 35 so as to be connected to the plurality of gate structures 35 located on both sides.

[0517] Specifically, the plurality of contact regions 34 are arranged alternately with the plurality of source regions 33 along the plurality of gate structures 35. More specifically, the plurality of contact regions 34 arranged along one sidewall of the gate structure 35 face in one-to-one correspondence with the plurality of contact regions 34 arranged along the other sidewall of the gate structure 35. Furthermore, the plurality of source regions 33 are arranged in a matrix in plan view.

[0518] Of course, the multiple contact regions 34 on one side may face the regions between the multiple source regions 33 on the other side (i.e., the multiple source regions 33) in a one-to-one correspondence. That is, the multiple contact regions 34 may be arranged in a staggered pattern in a plan view. The multiple contact regions 34 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the buried electrode 77 and the buried insulator 80 with the insulating film 76 sandwiched therebetween.

[0519] Although specific illustration is omitted, the interlayer insulating film 40 has a laminated structure including a first insulating film 41 and a second insulating film 42. As in the first embodiment, the first insulating film 41 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connecting surfaces 73A to 73D.

[0520] In this embodiment, the first insulating film 41 covers the peripheral edge of the active surface 71 and exposes the plurality of gate structures 35 collectively in the inner portion of the active surface 71. Specifically, the first insulating film 41 is connected to the insulating film 76 at both ends of the plurality of gate structures 35, exposing the buried electrodes 77. The first insulating film 41 also covers the outer peripheral surface 72 and the first to fourth connecting surfaces 73A to 73D in the same manner as in the first embodiment.

[0521] As in the first embodiment, the second insulating film 42 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connecting surfaces 73A to 73D, sandwiching the first insulating film 41. In this embodiment, the second insulating film 42 covers the peripheral portion of the active surface 71 and exposes the plurality of gate structures 35 collectively in the inner portion of the active surface 71. Specifically, the second insulating film 42 extends from above the first main surface 3 (active surface 71) into the trench 75 at both ends of the plurality of gate structures 35 and is connected to the buried insulator 80 within the trench 75.

[0522] In this form, the interlayer insulating film 40 includes a plurality of contact openings 43 (not shown) that expose both ends (buried electrodes 77) of the plurality of gate structures 35, and a single contact opening 43 that collectively exposes the inner portions (buried insulator 80) of the plurality of gate structures 35, the plurality of source regions 33, and the plurality of contact regions 34.

[0523] The gate pad 45, the gate wirings 46, and the drain pad 48 have the same configurations as those in the first embodiment. The source pad 47 extends from above the interlayer insulating film 40 into the single contact opening 43, and collectively covers the inner portions (buried insulator 80) of the gate structures 35, the source regions 33, and the contact regions 34 within the single contact opening 43.

[0524] The source pad 47 is electrically insulated from the plurality of gate structures 35 (buried electrodes 77) by the buried insulator 80, and is electrically connected to the plurality of source regions 33 and the plurality of contact regions 34 on the first main surface 3 (active surface 71). The source pad 47 has a buried portion buried in the trench 75. The buried portion of the source pad 47 faces the buried electrode 77 within the trench 75 with the buried insulator 80 sandwiched therebetween, and is electrically connected to the plurality of source regions 33 and the plurality of contact regions 34 at the open end of the trench 75.

[0525] 52 is a cross-sectional perspective view showing a gate structure 35 according to the fifth embodiment. Referring to Fig. 52, the plurality of gate structures 35 according to the fifth embodiment each have a configuration obtained by modifying the plurality of gate structures 35 according to the fourth embodiment. The configuration of the gate structure 35 according to the fifth embodiment is also applicable to the configurations of the gate structures 35 according to the first to third embodiments.

[0526] Each of the gate structures 35 includes a trench 75, an insulating film 76, a buried electrode 77, and a buried insulator 80. The trench 75 has the same configuration as in the first embodiment. In this configuration, the insulating film 76 includes an upper insulating film 81 and a lower insulating film 82.

[0527] The upper insulating film 81 is formed as an insulating film for channel control, and covers the wall surface of the opening side of the trench 75 relative to the bottom of the body region 32. The upper insulating film 81 has a portion that covers the second drift region 17 across the boundary between the second drift region 17 and the body region 32. In this case, the coverage area of ​​the upper insulating film 81 with respect to the body region 32 is preferably larger than the coverage area of ​​the upper insulating film 81 with respect to the second drift region 17.

[0528] The upper insulating film 81 may include a silicon oxide film. The upper insulating film 81 preferably includes a silicon oxide film made of an oxide of the chip 2. The upper insulating film 81 may have a thickness of 1 nm or more and 100 nm or less. The thickness of the upper insulating film 81 may have a value belonging to any one of the ranges of 1 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0529] The lower insulating film 82 covers the wall surface of the trench 75 on the bottom wall side of the bottom of the body region 32. The lower insulating film 82 covers the second drift region 17. The coverage area of ​​the second drift region 17 with the lower insulating film 82 is larger than the coverage area of ​​the body region 32 with the upper insulating film 81.

[0530] The lower insulating film 82 may include a silicon oxide film. The lower insulating film 82 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method. The lower insulating film 82 has a thickness greater than that of the upper insulating film 81. The thickness of the lower insulating film 82 is preferably 10 to 50 times the thickness of the upper insulating film 81.

[0531] The lower insulating film 82 may have a thickness of 100 nm to 500 nm. The thickness of the lower insulating film 82 may have a value belonging to any one of the ranges of 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, and 450 nm to 500 nm.

[0532] In this embodiment, the buried electrode 77 has a multi-electrode structure (double electrode structure) including an upper electrode 83, a lower electrode 84, and an intermediate insulating film 85. The upper electrode 83 is buried in the opening side of the trench 75 with an insulating film 76 sandwiched therebetween. Specifically, the upper electrode 83 is buried in the opening side of the trench 75 with an upper insulating film 81 sandwiched therebetween, and faces the body region 32 with the upper insulating film 81 sandwiched therebetween.

[0533] The area of ​​the upper electrode 83 facing the body region 32 is larger than the area of ​​the upper electrode 83 facing the second drift region 17. In this embodiment, the upper electrode 83 is embedded in the trench 75 at a distance from the first main surface 3 (active surface 71) toward the bottom wall of the trench 75, and defines an open recess that is recessed toward the bottom wall of the trench 75 at the opening end of the trench 75. The upper electrode 83 exposes a surface portion of the first main surface 3 (active surface 71) and an upper end of the upper insulating film 81 at the opening end of the trench 75.

[0534] A gate potential as a control potential is applied to the upper electrode 83. In response to the gate potential, the upper electrode 83 controls the inversion and non-inversion of a channel (current path) in the body region 32. The upper electrode 83 may include p-type or n-type conductive polysilicon.

[0535] The lower electrode 84 is embedded in the bottom wall side of the trench 75 with the insulating film 76 interposed therebetween. Specifically, the lower electrode 84 is embedded in the bottom wall side of the trench 75 with the lower insulating film 82 interposed therebetween, and faces the second drift region 17 with the lower insulating film 82 interposed therebetween. In other words, the lower electrode 84 is embedded in the bottom wall side of the trench 75 with respect to the bottom of the body region 32. Although not specifically shown in the drawings, the lower electrode 84 is extended to the opening side of the trench 75 in part of the trench 75 (both ends in this embodiment).

[0536] The area of ​​the lower electrode 84 facing the second drift region 17 is larger than the area of ​​the upper electrode 83 facing the body region 32. The lower electrode 84 extends in a wall shape along the depth direction of the trench 75. The lower electrode 84 has an upper end that protrudes from the lower insulating film 82 toward the upper electrode 83 and is engaged with the lower end of the upper electrode 83. The upper end of the lower electrode 84 faces the upper insulating film 81 (body region 32) across the lower end of the upper electrode 83 in the horizontal direction.

[0537] A gate potential or a source potential may be applied to the lower electrode 84. When a gate potential is applied to the lower electrode 84, the lower electrode 84 has the same potential as the upper electrode 83. Therefore, the voltage drop between the upper electrode 83 and the lower electrode 84 is suppressed. This suppresses electric field concentration on the gate structure 35.

[0538] On the other hand, when a source potential is applied to the lower electrode 84, the lower electrode 84 can function as a field electrode. Therefore, the parasitic capacitance between the lower electrode 84 (field electrode) and the second layer 9 (drift region 13) is reduced. This suppresses a decrease in switching speed due to the parasitic capacitance. The lower electrode 84 may include p-type or n-type conductive polysilicon.

[0539] The intermediate insulating film 85 is interposed between the upper electrode 83 and the lower electrode 84, and electrically insulates the upper electrode 83 and the lower electrode 84 within the trench 75. The intermediate insulating film 85 is continuous with the upper insulating film 81 and the lower insulating film 82. The intermediate insulating film 85 has a thickness smaller than that of the lower insulating film 82. The thickness of the intermediate insulating film 85 is preferably greater than that of the upper insulating film 81. The intermediate insulating film 85 may include a silicon oxide film. The intermediate insulating film 85 preferably includes a silicon oxide film made of an oxide of the lower electrode 84.

[0540] The buried insulator 80 is buried in the trench 75 (open recess) so as to expose the first main surface 3 (active surface 71), and covers the upper insulating film 81 and the upper electrode 83 within the recess. The buried insulator 80 is buried in the trench 75 at a distance from the first main surface 3 (active surface 71) toward the upper electrode 83, and exposes a surface portion of the first main surface 3 (active surface 71) at the open end of the trench 75.

[0541] In this embodiment, the plurality of source regions 33 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the upper electrode 83 and the buried insulator 80 with the upper insulating film 81 interposed therebetween. In this embodiment, the plurality of contact regions 34 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the upper electrode 83 and the buried insulator 80 with the upper insulating film 81 interposed therebetween.

[0542] The plurality of field regions 38, the interlayer insulating film 40, the gate pad 45, the plurality of gate wirings 46, the source pad 47, and the drain pad 48 have the same configurations as those in the second embodiment. In this configuration, the plurality of gate wirings 46 penetrate the interlayer insulating film 40 via the plurality of contact openings 43 and are electrically connected to the plurality of upper electrodes 83. When a gate potential is applied to the lower electrode 84, the plurality of gate wirings 46 penetrate the interlayer insulating film 40 via the plurality of contact openings 43 and are electrically connected to the plurality of upper electrodes 83 and the plurality of lower electrodes 84.

[0543] When a source potential is applied to the lower electrode 84, the source pad 47 is electrically connected to the plurality of lower electrodes 84. In this case, the SiC semiconductor device 1B may include a source wiring extending from the source pad 47 onto the interlayer insulating film 40. In this case, the source wiring is formed in a line shape extending along the periphery of the active surface 71 so as to intersect (specifically, orthogonally intersect) with a portion (one end or both ends) of the plurality of gate structures 35 in a region outside the plurality of gate wirings 46. The source wiring penetrates the interlayer insulating film 40 via the plurality of contact openings 43 and is electrically connected to the plurality of lower electrodes 84.

[0544] Fig. 53 is a plan view showing a SiC semiconductor device 1C according to a third embodiment. Fig. 54 is a cross-sectional view taken along line LIV-LIV shown in Fig. 53. Fig. 55 is a plan view showing an example layout of chip 2. Fig. 56 is a perspective view showing an example layout of chip 2.

[0545] 53 to 56 , the SiC semiconductor device 1C includes, similarly to the SiC semiconductor device 1A, a chip 2, a base layer 6, a stacked portion 7 (a first layer 8 and a second layer 9), an active region 10, a peripheral region 11, a column region 12, and a plurality of field regions 38. The column region 12 may have at least one of the plurality of features shown in the first to twelfth embodiments described above. The column region 12 may also have a feature that combines a plurality (two or more) of the features shown in the first to twelfth embodiments described above.

[0546] The SiC semiconductor device 1C includes an interlayer insulating film 90 that selectively covers the first main surface 3. The interlayer insulating film 90 may have a single layer structure or a multilayer structure including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the interlayer insulating film 90 has a single layer structure including a silicon oxide film.

[0547] The interlayer insulating film 90 covers the multiple field regions 38 in the peripheral region 11. In this embodiment, the interlayer insulating film 90 is continuous with the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. Of course, the interlayer insulating film 90 may be formed at a distance inward from the periphery of the first main surface 3, with the second layer 9 exposed from the periphery of the first main surface 3.

[0548] The interlayer insulating film 90 has a contact opening 91 that exposes the active region 10. In this form, the contact opening 91 has an opening wall surface positioned above the innermost field region 38, exposing the entire active region 10 and the inner edge of the innermost field region 38.

[0549] The SiC semiconductor device 1C includes a first pad electrode 92 covering the first main surface 3 in the active region 10. The first pad electrode 92 is formed as an anode pad. The first pad electrode 92 is arranged inward from the periphery of the chip 2 with a space therebetween. The first pad electrode 92 is formed in a polygonal shape (a quadrangular shape in this embodiment) that follows the periphery of the chip 2 in a plan view.

[0550] The first pad electrode 92 extends from above the interlayer insulating film 90 into the contact opening 91 and is electrically connected to the first main surface 3 and the innermost field region 38 within the contact opening 91. The first pad electrode 92 forms a Schottky junction with the first main surface 3 (second layer 9). As a result, an SBD structure 93 (Schottky Barrier Diode structure) serving as a diode structure (device structure) is formed in the active region 10.

[0551] The SiC semiconductor device 1C includes a second pad electrode 94 covering the second main surface 4. The second pad electrode 94 is formed as a cathode pad. The second pad electrode 94 forms ohmic contact with the base layer 6 exposed from the second main surface 4. In other words, the second pad electrode 94 is electrically connected to the first layer 8 (the plurality of first drift regions 16) and the second layer 9 (the plurality of second drift regions 17) via the base layer 6.

[0552] The second pad electrode 94 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The second pad electrode 94 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0553] The breakdown voltage that can be applied between the first pad electrode 92 and the second pad electrode 94 (between the first main surface 3 and the second main surface 4) may be 500 V to 3000 V or less. The breakdown voltage may have a value that belongs to any one of the following ranges: 500 V to 1000 V or less, 1000 V to 1500 V, 1500 V to 2000 V, 2000 V to 2500 V, and 2500 V to 3000 V.

[0554] When a laminated portion 7 having a two-layer structure is employed, the breakdown voltage is preferably set to a value belonging to any one of the ranges of 500 V to 1000 V, 1000 V to 1500 V, and 1500 V to 2000 V. When a laminated portion 7 having a three-layer structure is employed, the breakdown voltage is preferably set to a value belonging to any one of the ranges of 1000 V to 1500 V, 1500 V to 2000 V, 2000 V to 2500 V, and 2500 V to 3000 V.

[0555] 57 to 61 , first to fifth embodiments of the SBD structure 93 will be described. Fig. 57 is a cross-sectional perspective view showing the SBD structure 93 according to the first embodiment. Referring to Fig. 57 , when the second upper ends 15b of the plurality of second regions 15 are formed at intervals from the first main surface 3 toward the lower end of the second layer 9 (see also Figs. 18 to 25 , for example), the first pad electrode 92 forms a Schottky junction with a portion of the second layer 9 that is interposed between the first main surface 3 and the second upper ends 15b.

[0556] 58 is a cross-sectional perspective view showing an SBD structure 93 according to the second embodiment. Referring to Fig. 58, when the second regions 15 and the second drift regions 17 are exposed from the first main surface 3 (see also Fig. 27, for example), the first pad electrode 92 is mechanically and electrically connected to the second regions 15 and the second drift regions 17 at the first main surface 3. In this case, the first pad electrode 92 forms a JBS structure (Junction Barrier Controlled Schottky structure) with the second regions 15 and forms a Schottky junction with the second drift regions 17.

[0557] 59 is a cross-sectional perspective view showing an SBD structure 93 according to the third embodiment. Referring to Fig. 59, when the stacked layer 7 includes the top layer 30 (see also Fig. 32 etc.), the first pad electrode 92 forms a Schottky junction with the top layer 30 (first main surface 3). Of course, when the top layer 30 is not formed and a sufficient space is formed in the second layer 9 between the first main surface 3 and the column region 12, the top layer 30 may be omitted.

[0558] 60 is a cross-sectional perspective view showing an SBD structure 93 according to the fourth embodiment. Referring to Fig. 60, when the stacked portion 7 includes the top layer 30 (see also Fig. 32 etc.), the SiC semiconductor device 1C may include a plurality of p-type surface layer regions 95 (impurity regions) formed in the surface layer portion of the first main surface 3 in the top layer 30 of the active region 10.

[0559] In this embodiment, the surface layer regions 95 are arranged at intervals in the second arrangement direction Da2 and are each formed in a strip shape extending in the second extension direction De2. That is, in this embodiment, the surface layer regions 95 are arranged in stripes extending along the second extension direction De2 of the second regions 15.

[0560] In this example, the second arrangement direction Da2 is the m-axis direction, and the second extension direction De2 is the a-axis direction. Of course, the arrangement direction and extension direction of the multiple surface layer regions 95 are changed depending on the second arrangement direction Da2 and second extension direction De2 of the multiple second regions 15. Therefore, the second arrangement direction Da2 may be the a-axis direction, and the second extension direction De2 may be the m-axis direction. Alternatively, the second arrangement direction Da2 may be a direction other than the a-axis direction and the m-axis direction, and the second extension direction De2 may be a direction other than the a-axis direction and the m-axis direction.

[0561] It is preferable that the plurality of surface layer regions 95 each have a width different from the width of the plurality of first regions 14, and are arranged at a pitch different from the pitch of the plurality of first regions 14. The width of the surface layer region 95 may be less than the width of the plurality of first regions 14, and the pitch of the surface layer regions 95 may be less than the pitch of the plurality of first regions 14. The width of the surface layer region 95 may be less than the width of the plurality of first regions 14, and the pitch of the surface layer regions 95 may be greater than the pitch of the plurality of first regions 14.

[0562] The width of the surface region 95 may be greater than the width of the plurality of first regions 14, and the pitch of the surface region 95 may be less than the pitch of the plurality of first regions 14. The width of the surface region 95 may be greater than the width of the plurality of first regions 14, and the pitch of the surface region 95 may be greater than the pitch of the plurality of first regions 14. Of course, the width of the plurality of surface regions 95 may be approximately equal to the width of the plurality of first regions 14. Furthermore, the pitch of the plurality of surface regions 95 may be approximately equal to the pitch of the plurality of first regions 14.

[0563] It is preferable that the plurality of surface layer regions 95 each have a width different from the width of the plurality of second regions 15, and are arranged at a pitch different from the pitch of the plurality of second regions 15. The width of the surface layer region 95 may be less than the width of the plurality of second regions 15, and the pitch of the surface layer regions 95 may be less than the pitch of the plurality of second regions 15. The width of the surface layer region 95 may be less than the width of the plurality of second regions 15, and the pitch of the surface layer regions 95 may be greater than the pitch of the plurality of second regions 15.

[0564] The width of the surface region 95 may be greater than the width of the plurality of second regions 15, and the pitch of the surface region 95 may be less than the pitch of the plurality of second regions 15. The width of the surface region 95 may be greater than the width of the plurality of second regions 15, and the pitch of the surface region 95 may be greater than the pitch of the plurality of second regions 15. Of course, the width of the plurality of surface regions 95 may be approximately equal to the width of the plurality of second regions 15. Furthermore, the pitch of the plurality of surface regions 95 may be approximately equal to the pitch of the plurality of second regions 15.

[0565] The plurality of surface layer regions 95 are formed at intervals from the plurality of second regions 15 toward the first main surface 3. The plurality of surface layer regions 95 are preferably formed at intervals from the lower end (second layer 9) of the top layer 30 toward the first main surface 3, and face the plurality of second layers 9 with at least a portion of the top layer 30 interposed therebetween. The plurality of surface layer regions 95 may face either one or both of the second regions 15 and the second drift region 17 in the stacking direction.

[0566] The surface regions 95 are made of random impurity regions introduced into the surface portion of the second layer 9 by random implantation into the second layer 9 (see also FIG. 12 ). Therefore, the surface regions 95 have a thickness in the direction along the top axis channel CHT that is less than the second region thickness TR2 of the second region 15. The thickness of the surface regions 95 is less than the first region thickness TR1 of the first region 14.

[0567] Unlike the second region 15 and the like, the surface region 95 does not have a gradual portion 22 having a thickness of 0.5 μm or more, and has a concentration gradient including a gradually increasing portion 20, a peak portion 21, and a gradually decreasing portion 23 within a range of 0.5 μm. １５ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0568] The p-type impurity concentrations of the plurality of surface regions 95 are preferably adjusted by at least one trivalent element. The trivalent element in the surface region 95 may be the same as or different from the trivalent element in the second region 15, etc. The trivalent element in the surface region 95 may be at least one of boron, aluminum, gallium, and indium.

[0569] The first pad electrode 92 is mechanically and electrically connected to the top layer 30 on the first main surface 3. In this case, the first pad electrode 92 forms a JBS structure with the plurality of surface layer regions 95 on the first main surface 3, and forms a Schottky junction with a region between the plurality of surface layer regions 95 on the first main surface 3. That is, in the SBD structure 93 according to the fourth embodiment, the layout restrictions and electrical characteristic restrictions of the JBS structure resulting from the layout of the superjunction structure SJ (second superjunction structure SJ2) are alleviated.

[0570] In this example, a plurality of surface layer regions 95 are formed in the top layer 30. However, if a sufficient space is formed between the first main surface 3 and the column region 12 in the second layer 9 when the top layer 30 is not formed, the top layer 30 may be omitted.

[0571] 61 is a cross-sectional perspective view showing an SBD structure 93 according to the fifth embodiment. The SBD structure 93 according to the fifth embodiment has a layout that is a modification of the layout of the surface layer regions 95 according to the fourth embodiment. Specifically, the surface layer regions 95 are arranged in stripes in the active region 10, extending in a direction intersecting the second extension direction De2 of the second regions 15.

[0572] In this embodiment, the multiple surface layer regions 95 are arranged at intervals in the first arrangement direction Da1 of the first regions 14 and extend in the first extension direction De1 of the first regions 14. In this example, the first arrangement direction Da1 is the m-axis direction, and the first extension direction De1 is the a-axis direction. Of course, the arrangement direction and extension direction of the multiple surface layer regions 95 are changed depending on the first arrangement direction Da1 and first extension direction De1 of the multiple first regions 14. Therefore, the first arrangement direction Da1 may be the a-axis direction, and the first extension direction De1 may be the m-axis direction. Alternatively, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.

[0573] Of course, the arrangement direction of the surface layer regions 95 may be a direction other than the first arrangement direction Da1 and the second arrangement direction D2. Furthermore, the extension direction of the surface layer regions 95 may be a direction other than the first extension direction De1 and the second extension direction De2. In other words, the surface layer regions 95 may intersect both the first regions 14 and the second regions 15 in a plan view.

[0574] For example, the angle (absolute value) between the extension direction of the surface region 95 and the second extension direction De2 may be greater than 0° and less than 90°. The angle (absolute value) of the surface region 95 may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° to 36°, 36° to 54°, 54° to 72°, and 72° to 90°. The angle (absolute value) of the surface region 95 may be set to a value belonging to any one of the ranges of 30°±5°, 45°±5°, and 60°±5°.

[0575] The above-described embodiments can be implemented in other embodiments. For example, in each of the above-described embodiments, the base layer 6, the first layer 8, the second layer 9, the buffer layer 26, and the top layer 30 each contain a SiC single crystal. However, at least one or all of the base layer 6, the first layer 8, the second layer 9, the buffer layer 26, and the top layer 30 may contain a single crystal of a wide bandgap semiconductor other than a SiC single crystal.

[0576] Wide bandgap semiconductors are semiconductors that have a bandgap larger than that of silicon. Wide bandgap semiconductor single crystals include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga ２ O ３ The base layer 6, the first layer 8, the second layer 9, the buffer layer 26, and the top layer 30 may be made of the same type of single crystal, or may be made of different types of single crystal.

[0577] The channeling implantation process (the process of implanting impurities into regions with sparse atomic rows) can also be applied to single crystals that have a cubic crystal structure. Therefore, the single crystal of the wide bandgap semiconductor may be a cubic or hexagonal crystal structure. When a cubic single crystal structure is used for at least one or all of the base layer 6, the first layer 8, the second layer 9, the buffer layer 26, and the top layer 30, these axial channels are formed by regions surrounded by atomic rows aligned along low-index crystal axes of the cubic crystal structure.

[0578] A low-index crystal axis related to a cubic crystal is a crystal axis in which the absolute values ​​of "h," "k," and "l" in the Miller indices (h, k, l) are all equal to or less than 2 (preferably equal to or less than 1). Of course, at least one or all of the base layer 6, first layer 8, second layer 9, buffer layer 26, and top layer 30 may contain single crystal silicon.

[0579] In the above-described embodiments, examples have been shown in which the MIS structure 31 and the SBD structure 93 are individually formed on different chips 2. However, the MIS structure 31 and the SBD structure 93 may be formed on one chip 2. In this case, the SBD structure 93 may be electrically interposed between the source pad 47 (anode pad) and the drain pad 48 (cathode pad) as a freewheeling diode for the MIS structure 31.

[0580] In the above-described embodiments, an n-type base layer 6 has been described. However, a p-type base layer 6 may also be employed. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, in the above description, the "source" of the MISFET structure is replaced with the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced with the "collector" of the IGBT structure. The p-type base layer 6 may be a p-type region containing a trivalent element introduced into the surface layer of the second main surface 4 of the chip 2 by ion implantation.

[0581] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in each of the above-mentioned embodiments, but are not intended to limit the scope of each clause to the above-mentioned embodiments. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0582] [A1] A semiconductor device (1A, 1B, 1C) including: a first layer (8) of a first conductivity type (n-type) including a semiconductor single crystal and having a first axial channel (CH1) along a stacking direction; a second layer (9) of a first conductivity type (n-type) including a semiconductor single crystal and having a second axial channel (CH2) along the stacking direction and stacked on the first layer (8); a first region (14) of a second conductivity type (p-type) extending along the first axial channel (CH1) in the first layer (8) in a cross-sectional view and extending in a first extension direction (De1) in a planar view; and a second region (15) of a second conductivity type (p-type) extending along the second axial channel (CH2) in the second layer (9) in a cross-sectional view and extending in a second extension direction (De2) that intersects the first extension direction (De1) so as to intersect the first region (14) in a planar view.

[0583] [A2] The semiconductor device (1A, 1B, 1C) according to A1, wherein the first extending direction (De1) is the m-axis direction or the a-axis direction of crystal orientations.

[0584] [A3] The semiconductor device (1A, 1B, 1C) according to A2, wherein the second extension direction (De2) is perpendicular to the first extension direction (De1).

[0585] [A4] The semiconductor device (1A, 1B, 1C) according to A2, wherein the second extension direction (De2) is not orthogonal to the first extension direction (De1).

[0586] [A5] The semiconductor device (1A, 1B, 1C) according to A1, wherein the first extension direction (De1) is a direction other than the m-axis direction and the a-axis direction among the crystal orientations.

[0587] [A6] The semiconductor device (1A, 1B, 1C) according to A5, wherein the second extension direction (De2) is perpendicular to the first extension direction (De1).

[0588] [A7] The semiconductor device (1A, 1B, 1C) according to A5, wherein the second extension direction (De2) is not orthogonal to the first extension direction (De1).

[0589] [A8] A semiconductor device (1A, 1B, 1C) according to any one of A1 to A7, wherein the second extension direction (De2) is a direction other than the m-axis direction and the a-axis direction among the crystal orientations.

[0590] [A9] A semiconductor device (1A, 1B, 1C) according to any one of A1 to A8, wherein the second region (15) has an extension that crosses the boundary between the first layer (...

Claims

1. a first SiC layer of a first conductivity type having a first axial channel along a stacking direction; a second SiC layer of the first conductivity type having a second axial channel along the stacking direction and stacked on the first SiC layer; a first region of a second conductivity type extending along the first axial channel in the first SiC layer in a cross-sectional view and extending in a first extension direction in a plan view; a second region of a second conductivity type extending in a second extension direction that intersects with the first extension direction so as to intersect with the first region in a plan view, the second region extending in the second SiC layer along the second axial channel in a cross-sectional view.

2. The SiC semiconductor device according to claim 1 , wherein the first extending direction is an m-axis direction or an a-axis direction of crystal orientations of SiC.

3. The SiC semiconductor device according to claim 2 , wherein the second extending direction is perpendicular to the first extending direction.

4. The SiC semiconductor device according to claim 2 , wherein the second extending direction is not perpendicular to the first extending direction.

5. The SiC semiconductor device according to claim 1 , wherein the first extending direction is a direction other than the m-axis direction and the a-axis direction among the crystal orientations of SiC.

6. The SiC semiconductor device according to claim 5 , wherein the second extending direction is perpendicular to the first extending direction.

7. The SiC semiconductor device according to claim 5 , wherein the second extending direction is not perpendicular to the first extending direction.

8. The SiC semiconductor device according to claim 1 , wherein the second extending direction is a direction other than the m-axis direction and the a-axis direction among the crystal orientations of SiC.

9. 9. The SiC semiconductor device according to claim 1, wherein the second region has an extension that crosses a boundary between the first SiC layer and the second SiC layer and is located within the first SiC layer.

10. The SiC semiconductor device according to claim 9 , wherein the extension of the second region is connected to the first region within the first SiC layer.

11. The SiC semiconductor device according to claim 9 , wherein the first region is formed at an interval from an upper end to a lower end of the first SiC layer.

12. 9. The SiC semiconductor device according to claim 1, further comprising an intermediate region of a second conductivity type interposed in a region between the first region and the second region.

13. The SiC semiconductor device according to claim 12 , wherein the intermediate region is formed in the first SiC layer in a region between the first region and the second region.

14. the first region comprises a single impurity region that traverses a middle portion of the first SiC layer along the first axial channel; 9. The SiC semiconductor device according to claim 1, wherein the second region is composed of a single impurity region that crosses an intermediate portion of the second SiC layer along the second axial channel.

15. The SiC semiconductor device according to any one of claims 1 to 8, wherein the first region has a first lower end portion on the lower end side of the first SiC layer and a first upper end portion on the upper end side of the first SiC layer, and has a first concentration gradient that gradually decreases from the first upper end portion toward the first lower end portion.

16. 16. The SiC semiconductor device according to claim 15, wherein the first concentration gradient includes a first peak value on the first upper end side, and a first gradual portion in which the impurity concentration gradually decreases at a gradual rate of decrease in a region on the first lower end side of the first peak value.

17. The SiC semiconductor device according to claim 16 , wherein the first relaxed portion occupies a thickness range of at least one-fourth of the first region.

18. The SiC semiconductor device according to any one of claims 1 to 8, wherein the second region has a second lower end portion on the lower end side of the second SiC layer and a second upper end portion on the upper end side of the second SiC layer, and has a second concentration gradient that gradually decreases from the second upper end portion toward the second lower end portion.

19. 19. The SiC semiconductor device according to claim 18, wherein the second concentration gradient includes a second peak value on the second upper end side, and a second gradual portion in which the impurity concentration gradually decreases at a gradual rate of decrease in a region on the second lower end side of the second peak value.

20. The SiC semiconductor device according to claim 19 , wherein the second relaxed portion occupies a thickness range of at least one-fourth of the second region.