Transformer chip

Abstract

This transformer chip comprises: an insulating layer that has a top surface and a bottom surface facing opposite sides from one another in the thickness direction; a first coil that is disposed closer to the top surface within the insulating layer; a second coil that is disposed closer to the bottom surface within the insulating layer and opposite the first coil; and a first pad that is formed on the top surface and is electrically connected to the first coil. The first pad comprises a first extending section that, viewed from the thickness direction, is positioned in an inner region surrounded by the first coil and extends beyond a position 5 µm inward of the inner edge of the first coil toward the first coil.

Description

Transformer Chip

[0001] The present disclosure relates to a transformer chip.

[0002] An insulated gate driver is known as a gate driver that applies a gate voltage to the gate of a switching element such as a transistor. For example, Patent Document 1 describes an electronic component including a transformer chip having a primary coil and a secondary coil.

[0003] JP 2018-78169 A

[0004] Incidentally, in the above-mentioned transformer chip, there are cases where an improvement in the dielectric strength is required.

[0005] A transformer chip according to one aspect of the present disclosure includes an insulating layer having an upper surface and a lower surface facing opposite each other in the thickness direction, a first coil arranged within the insulating layer near the upper surface, a second coil arranged within the insulating layer near the lower surface and facing the first coil, and a first pad formed on the upper surface and electrically connected to the first coil, wherein the first pad is arranged in an inner region surrounded by the first coil when viewed from the thickness direction and includes a first extension portion extending toward the first coil beyond a position 5 μm inward from the inner circumferential end of the first coil.

[0006] According to the transformer chip of one aspect of the present disclosure, it is possible to improve the dielectric strength voltage.

[0007] FIG. 1 is a circuit diagram schematically illustrating the configuration of a signal transmission device according to one embodiment. FIG. 2 is a plan view schematically illustrating the configuration of the signal transmission device of FIG. 1. FIG. 3 is a cross-sectional view schematically illustrating the configuration of the signal transmission device of FIG. 2. FIG. 4 is a schematic perspective view illustrating a transformer chip of the signal transmission device of FIG. 3. FIG. 5 is a schematic plan view of the transformer chip of FIG. 4. FIG. 6 is a schematic plan view of a second coil of the transformer chip of FIG. 4. FIG. 7 is a schematic plan view of a first coil of the transformer chip of FIG. 4. FIG. 8 is a cross-sectional view taken along line 8-8 of FIG. 5. FIG. 9 is a cross-sectional view taken along line 9-9 of FIG. 5. FIG. 10 is a partially enlarged plan view of the first coil of FIG. 6. FIG. 11 is a cross-sectional view taken along line 11-11 of FIG. 10. FIG. 12 is a schematic cross-sectional view illustrating a simulation result of the electric field strength in the transformer chip of FIG. 4. FIG. 13 is a schematic cross-sectional view illustrating a simulation result of the electric field strength in a transformer chip of a comparative example. FIG. 14 is a schematic plan view of a transformer chip of a modified example. FIG. 15 is a partially enlarged plan view of FIG. 14. FIG. 16 is a partial schematic plan view showing a transformer chip of a modified example. FIG. 17 is a schematic cross-sectional view showing a transformer chip of a modified example. FIG. 18 is a schematic cross-sectional view showing a transformer chip of a modified example. FIG. 19 is a schematic cross-sectional view showing a transformer chip of a modified example. FIG. 20 is a partial schematic plan view showing a transformer chip of a modified example. FIG. 21 is a partial schematic cross-sectional view showing the transformer chip of FIG. 20. FIG. 22 is a partial schematic plan view showing a transformer chip of a modified example. FIG. 23 is a partial schematic cross-sectional view showing the transformer chip of FIG. 22. FIG. 24 is a schematic plan view showing a transformer chip of a modified example. FIG. 25 is a schematic plan view showing a transformer chip of a modified example. FIG. 26 is a schematic plan view showing a transformer chip of a modified example. FIG. 27 is a circuit diagram schematically showing the configuration of a signal transmission device of a modified example. FIG. 28 is a plan view schematically showing the configuration of the signal transmission device of FIG. 27.

[0008] Hereinafter, several embodiments of the signal transmission device and transformer chip of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure. Terms such as "first," "second," and "third" in the present disclosure are used merely to distinguish between objects and do not rank them.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] The phrase "at least one" as used herein means "one or more" of the desired options. As an example, the phrase "at least one" as used herein means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used herein means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0011] (One embodiment) (General configuration of signal transmission device) A general configuration of a signal transmission device 10 according to one embodiment will be described with reference to Figs. 1 to 3 .

[0012] Fig. 1 schematically shows the circuit configuration of a signal transmission device 10 according to one embodiment. Fig. 2 schematically shows an example of the internal configuration (planar structure) of the signal transmission device 10. Fig. 3 schematically shows an example of a portion of the internal configuration (cross-sectional structure) of the signal transmission device 10. Note that hatched lines are omitted in Fig. 3 for convenience.

[0013] As shown in Fig. 1, the signal transmission device 10 is applied to an inverter device 500, for example. The inverter device 500 includes a control circuit (ECU: Electronic Control Unit) 503, the signal transmission device 10, and switching elements 501 and 502. The signal transmission device 10 is used as a gate driver that drives the switching element 501 via the control circuit 503. Fig. 1 shows the signal transmission device 10 that drives the switching element 501.

[0014] The switching element 501 is, for example, a high-side switching element connected to a drive power supply, and the switching element 502 is a low-side switching element. Examples of the switching elements 501 and 502 include transistors such as SiMOSFETs (Si Metal-Oxide-Semiconductor Field-Effect Transistors), SiCMOSFETs, and IGBTs (Insulated Gate Bipolar Transistors).

[0015] The signal transmission device 10 applies a drive voltage signal to the control terminal of the switching element 501. In the following description, as an example, a case will be described in which SiC MOSFETs are used as the switching elements 501 and 502. The signal transmission device 10 is provided for each of the switching elements 501 and 502, and drives the switching elements 501 and 502 individually.

[0016] The signal transmission device 10 includes a low-voltage circuit 20 to which a first voltage V1 is applied, a high-voltage circuit 30 to which a second voltage V2 higher than the first voltage V1 is applied, and a transformer 40 provided between the low-voltage circuit 20 and the high-voltage circuit 30. That is, the low-voltage circuit 20 and the high-voltage circuit 30 are connected via the transformer 40. The first voltage V1 and the second voltage V2 are DC voltages.

[0017] The signal transmission device 10 of this embodiment is configured so that, based on a control signal from the control circuit 503, a signal is transmitted from the low-voltage circuit 20 to the high-voltage circuit 30 via the transformer 40, and a drive voltage signal is output from the high-voltage circuit 30.

[0018] The signal transmitted from the low-voltage circuit 20 to the high-voltage circuit 30, i.e., the signal output from the low-voltage circuit 20, is, for example, a signal for driving the switching element 501, and examples thereof include a set signal (SET) and a reset signal (RESET). The set signal is a signal that transmits the rising edge of a control signal from the control circuit 503, and the reset signal is a signal that transmits the falling edge of a control signal from the control circuit 503. The set signal and the reset signal can also be said to be signals for generating a drive voltage signal for the switching element 501. For this reason, the set signal and the reset signal correspond to the "first signal."

[0019] More specifically, the low-voltage circuit 20 is configured to operate when a first voltage V1 is applied. The low-voltage circuit 20 is electrically connected to the control circuit 503 and generates a set signal and a reset signal based on a control signal input from the control circuit 503. For example, the low-voltage circuit 20 generates a set signal in response to a rising edge of the control signal, and generates a reset signal in response to a falling edge of the control signal. The low-voltage circuit 20 then transmits the generated set signal and reset signal to the high-voltage circuit 30.

[0020] The high-voltage circuit 30 is configured to operate when a second voltage V2 is applied to it. The high-voltage circuit 30 is electrically connected to the gate of the switching element 501. The high-voltage circuit 30 generates a drive voltage signal for driving the switching element 501 based on the set signal and reset signal received from the low-voltage circuit 20, and applies the drive voltage signal to the gate of the switching element 501. In other words, the high-voltage circuit 30 can also be said to generate a drive voltage signal to be applied to the gate of the switching element 501 based on the first signal output from the low-voltage circuit 20. More specifically, the high-voltage circuit 30 generates a drive voltage signal that turns on the switching element 501 based on the set signal, and applies the drive voltage signal to the gate of the switching element 501. On the other hand, the high-voltage circuit 30 generates a drive voltage signal that turns off the switching element 501 based on the reset signal, and applies the drive voltage signal to the gate of the switching element 501. In this way, the on / off of the switching element 501 is controlled by the signal transmission device 10.

[0021] The high-voltage circuit 30 includes, for example, an RS flip-flop circuit to which a set signal and a reset signal are input, and a driver unit that generates a drive voltage signal based on the output signal of the RS flip-flop circuit. However, the specific circuit configuration of the high-voltage circuit 30 can be changed as desired.

[0022] In the signal transmission device 10 of this embodiment, the low-voltage circuit 20 and the high-voltage circuit 30 are insulated from each other by the transformer 40. More specifically, the transformer 40 restricts the transmission of DC voltage between the low-voltage circuit 20 and the high-voltage circuit 30, while allowing the transmission of various signals such as a set signal and a reset signal.

[0023] In other words, the state in which the low-voltage circuit 20 and the high-voltage circuit 30 are insulated means that the transmission of DC voltage is blocked between the low-voltage circuit 20 and the high-voltage circuit 30, while the transmission of signals between the low-voltage circuit 20 and the high-voltage circuit 30 is permitted.

[0024] The withstand voltage of the signal transmission device 10 is, for example, 2500 Vrms or more and 7500 Vrms or less. The withstand voltage of the signal transmission device 10 of this embodiment is approximately 5000 Vrms. However, the specific value of the withstand voltage of the signal transmission device 10 is not limited to this and can be any value.

[0025] In this embodiment, the ground GND1 of the low-voltage circuit 20 and the ground GND2 of the high-voltage circuit 30 are provided independently. Hereinafter, the potential of the ground GND1 of the low-voltage circuit 20 will be referred to as a first reference potential, and the potential of the ground GND2 of the high-voltage circuit 30 will be referred to as a second reference potential. In this case, the first voltage V1 is a voltage derived from the first reference potential, and the second voltage V2 is a voltage derived from the second reference potential. The first voltage V1 is, for example, 4.5 V or more and 5.5 V or less, and the second voltage V2 is, for example, 9 V or more and 24 V or less.

[0026] (Transformer) The transformer 40 will be described in detail below. The signal transmission device 10 of this embodiment includes two transformers 40 corresponding to the two signals transmitted from the low-voltage circuit 20 to the high-voltage circuit 30. For convenience, one of the two transformers 40 will be referred to as transformer 40A, and the other of the two transformers 40 will be referred to as transformer 40B. In one example, the transformer 40A is used to transmit a set signal. The transformer 40B is used to transmit a reset signal. In one example, the set signal and the reset signal may be set signals and reset signals in a receiving circuit included in the high-voltage circuit 30.

[0027] The signal transmission device 10 includes a low-voltage signal line 21A that connects the low-voltage circuit 20 and the transformer 40A, and a low-voltage signal line 21B that connects the low-voltage circuit 20 and the transformer 40B. Therefore, the low-voltage signal line 21A transmits a set signal from the low-voltage circuit 20 to the transformer 40A. The low-voltage signal line 21B transmits a reset signal from the low-voltage circuit 20 to the transformer 40B.

[0028] The signal transmission device 10 includes a high-voltage signal line 31A that connects the transformer 40A and the high-voltage circuit 30, and a high-voltage signal line 31B that connects the transformer 40B and the high-voltage circuit 30. Therefore, the high-voltage signal line 31A transmits a set signal from the transformer 40A to the high-voltage circuit 30. The high-voltage signal line 31B transmits a reset signal from the transformer 40B to the high-voltage circuit 30.

[0029] The transformer 40A transmits a set signal from the low-voltage circuit 20 to the high-voltage circuit 30, while electrically insulating the low-voltage circuit 20 from the high-voltage circuit 30. The transformer 40B transmits a reset signal from the low-voltage circuit 20 to the high-voltage circuit 30, while electrically insulating the low-voltage circuit 20 from the high-voltage circuit 30.

[0030] The transformers 40A and 40B each have a first coil 41 and a second coil 42. The first coil 41 and the second coil 42 are electrically insulated from each other and configured to be magnetically coupled to each other.

[0031] The second coil 42 of the transformer 40A is connected to the low-voltage circuit 20 by the low-voltage signal line 21A and is also connected to the ground GND1 of the low-voltage circuit 20. That is, a first end of the second coil 42 of the transformer 40A is electrically connected to the low-voltage circuit 20, and a second end of the second coil 42 of the transformer 40A is electrically connected to the ground GND1 of the low-voltage circuit 20. The second coil 42 of the transformer 40B is connected to the low-voltage circuit 20 by the low-voltage signal line 21B and is also connected to the ground GND1 of the low-voltage circuit 20. That is, a first end of the second coil 42 of the transformer 40B is electrically connected to the low-voltage circuit 20, and a second end of the second coil 42 of the transformer 40B is electrically connected to the ground GND1 of the low-voltage circuit 20. Therefore, the potential of the second ends of the second coils 42 of the transformers 40A and 40B is the first reference potential. The first reference potential is, for example, 0 V.

[0032] The first coil 41 of the transformer 40A is connected to the high-voltage circuit 30 by a high-voltage signal line 31A and is also connected to ground GND2 of the high-voltage circuit 30. That is, a first end of the first coil 41 of the transformer 40A is electrically connected to the high-voltage circuit 30, and a second end of the first coil 41 of the transformer 40A is electrically connected to ground GND2 of the high-voltage circuit 30. The first coil 41 of the transformer 40B is connected to the high-voltage circuit 30 by a high-voltage signal line 31B and is also connected to ground GND2 of the high-voltage circuit 30. That is, a first end of the first coil 41 of the transformer 40B is electrically connected to the high-voltage circuit 30, and a second end of the first coil 41 of the transformer 40B is electrically connected to ground GND2 of the high-voltage circuit 30. Therefore, the potential of the second ends of the first coils 41 of the transformers 40A and 40B is the second reference potential. Ground GND2 of the high-voltage circuit 30 is connected to the source of the switching element 501. Therefore, the second reference potential fluctuates as the inverter device 500 is driven, and may become, for example, 600 V or higher.

[0033] FIG. 2 shows an example of a plan view illustrating the internal configuration of the signal transmission device 10. FIG. 3 shows an example of a cross-sectional view illustrating the internal configuration of the signal transmission device 10. Note that, because FIG. 1 shows a simplified circuit configuration of the signal transmission device 10, the number of external terminals of the signal transmission device 10 in FIG. 2 is greater than the number of external terminals of the signal transmission device 10 in FIG. 1. Here, the number of external terminals of the signal transmission device 10 refers to the number of external electrodes that can connect the signal transmission device 10 to external electronic components of the signal transmission device 10, such as the control circuit 503 and the switching element 501 (see FIG. 1). Furthermore, the number of signal lines (the number of wires W1 to W4, described below) that transmit signals from the low-voltage circuit 20 to the high-voltage circuit 30 in the signal transmission device 10 in FIG. 2 is greater than the number of signal lines in the signal transmission device 10 in FIG. 1.

[0034] 2, the signal transmission device 10 is a semiconductor device in which multiple semiconductor chips are packaged together, and is mounted on a circuit board provided in, for example, an inverter device 500. Note that the switching elements 501 and 502 are mounted on a mounting board separate from the circuit board. A cooler is attached to this mounting board.

[0035] The signal transmission device 10 is packaged in a small outline (SO) format, which is a small outline package (SOP) in this embodiment. The low-voltage circuit chip 60, the high-voltage circuit chip 70, and the transformer chip 80 of the signal transmission device 10 are, for example, semiconductor chips. The low-voltage circuit chip 60 is mounted on a low-voltage lead frame 100. The high-voltage circuit chip 70 is mounted on a high-voltage lead frame 110. A molded resin 120 encapsulates portions of the lead frames 100 and 110 and the chips 60, 70, and 80. In this embodiment, the transformer chip 80 and the molded resin 120 correspond to an "insulation module" that insulates the low-voltage circuit 20 from the high-voltage circuit 30. In FIG. 2, the molded resin 120 is indicated by a two-dot chain line for the purpose of illustrating the internal structure of the signal transmission device 10. The package format of the signal transmission device 10 can be arbitrarily changed.

[0036] The molded resin 120 is made of an electrically insulating material. This resin is, for example, a resin containing black epoxy resin. The molded resin 120 is formed in the shape of a rectangular plate with its thickness direction in the z direction. The molded resin 120 has four resin side surfaces 121 to 124. More specifically, the molded resin 120 has resin side surfaces 121 and 122 as both end surfaces in the x direction and resin side surfaces 123 and 124 as both end surfaces in the y direction. The x direction and the y direction are directions orthogonal to the z direction. The x direction and the y direction are orthogonal to each other. The x direction corresponds to the "first direction." The y direction corresponds to the "second direction." In the following description, a planar view means a view from the z direction.

[0037] The low-voltage lead frame 100 and the high-voltage lead frame 110 are each a conductor, and in this embodiment are made of a material containing Cu (copper), Fe (iron), etc. Each lead frame 100, 110 is provided across the inside and outside of the mold resin 120.

[0038] The low-voltage lead frame 100 has a low-voltage die pad 101 disposed within a molded resin 120, and a plurality of low-voltage leads 102 disposed across the inside and outside of the molded resin 120. Each low-voltage lead 102 constitutes an external terminal that electrically connects to an external electronic device such as a control circuit 503 (see FIG. 1 ).

[0039] In this embodiment, both the low-voltage circuit chip 60 and the transformer chip 80 are mounted on the low-voltage die pad 101. In a plan view, the low-voltage die pad 101 is arranged so that its center in the y direction is closer to the resin side surface 123 than the center in the y direction of the molded resin 120. In this embodiment, the low-voltage die pad 101 is not exposed from the molded resin 120. In a plan view, the low-voltage die pad 101 has a rectangular shape with its long side in the x direction and its short side in the y direction.

[0040] The plurality of low-voltage leads 102 are arranged spaced apart from one another in the x direction. Of the plurality of low-voltage leads 102, the low-voltage leads 102 arranged at both ends in the x direction are each integrated with the low-voltage die pad 101. A portion of each low-voltage lead 102 protrudes outward from the resin side surface 123 of the molded resin 120.

[0041] The high-voltage lead frame 110 has a high-voltage die pad 111 disposed within a molded resin 120, and a plurality of high-voltage leads 112 disposed across the inside and outside of the molded resin 120. Each high-voltage lead 112 constitutes an external terminal that electrically connects to an external electronic device, such as the gate of a switching element 501 (see FIG. 1 ).

[0042] The high-voltage die pad 111 has a high-voltage circuit chip 70 mounted thereon. In plan view, the high-voltage die pad 111 is disposed closer to the resin side surface 124 in the y direction than the low-voltage die pad 101. In this embodiment, the high-voltage die pad 111 is not exposed from the molded resin 120. In plan view, the high-voltage die pad 111 has a rectangular shape with its long side oriented in the x direction and its short side oriented in the y direction.

[0043] The low-voltage die pad 101 and the high-voltage die pad 111 are arranged at a distance from each other in the y direction. Therefore, the y direction can also be said to be the arrangement direction of the two die pads 101, 101. The dimensions of the low-voltage die pad 101 and the high-voltage die pad 111 in the y direction are set depending on the size and number of semiconductor chips to be mounted. In this embodiment, the low-voltage circuit chip 60 and the transformer chip 80 are mounted on the low-voltage die pad 101, and the high-voltage circuit chip 70 is mounted on the high-voltage die pad 111. Therefore, the dimension of the low-voltage die pad 101 in the y direction is larger than the dimension of the high-voltage die pad 111 in the y direction.

[0044] The plurality of high-voltage leads 112 are arranged spaced apart from each other in the x direction. Of the plurality of high-voltage leads 112, a pair of high-voltage leads 112 are integrated with the high-voltage die pad 111. A portion of each high-voltage lead 112 protrudes outward from the resin side surface 124 of the molded resin 120.

[0045] In this embodiment, the number of high-voltage leads 112 is the same as the number of low-voltage leads 102. As can be seen from Fig. 2, the plurality of low-voltage leads 102 and the plurality of high-voltage leads 112 are arranged in a direction (x direction) perpendicular to the arrangement direction (y direction) of the low-voltage die pads 101 and the high-voltage die pads 111. Note that the number of high-voltage leads 112 and the number of low-voltage leads 102 can each be changed as desired.

[0046] In this embodiment, the low-voltage die pad 101 is supported by a pair of low-voltage leads 102 that are integrated with the low-voltage die pad 101. The high-voltage die pad 111 is supported by a pair of high-voltage leads 112 that are integrated with the high-voltage die pad 111. Therefore, each die pad 101, 101 does not have a suspension lead that is exposed from the resin side surfaces 121, 122. This allows for a large insulation distance between the low-voltage lead frame 100 and the high-voltage lead frame 110.

[0047] The low-voltage circuit chip 60, the high-voltage circuit chip 70, and the transformer chip 80 are arranged spaced apart from one another in the y direction. The low-voltage circuit chip 60, the transformer chip 80, and the high-voltage circuit chip 70 are arranged in this order in the y direction from the low-voltage lead 102 to the high-voltage lead 112.

[0048] The low-voltage circuit chip 60 includes the low-voltage circuit 20 shown in FIG. 1. In plan view, the low-voltage circuit chip 60 has a rectangular shape with short and long sides. In plan view, the low-voltage circuit chip 60 is mounted on the low-voltage die pad 101 with the long sides aligned in the x direction and the short sides aligned in the y direction. As shown in FIG. 3, the low-voltage circuit chip 60 has a chip main surface 60s and a chip back surface 60r that face opposite each other in the z direction. The chip back surface 60r of the low-voltage circuit chip 60 is bonded to the low-voltage die pad 101 by a conductive bonding material SD. The conductive bonding material SD may be solder, Ag (silver) paste, or the like.

[0049] A plurality of first electrode pads 61, a plurality of second electrode pads 62, and a plurality of third electrode pads 63 are formed on a chip main surface 60s of the low-voltage circuit chip 60. Each of the electrode pads 61 to 63 is electrically connected to the low-voltage circuit 20.

[0050] The multiple first electrode pads 61 are arranged on the chip main surface 60s closer to the low-voltage lead 102 than the center of the chip main surface 60s in the y direction. The multiple first electrode pads 61 are arranged in the x direction. The multiple second electrode pads 62 are arranged at the end of the chip main surface 60s in the y direction that is closer to the transformer chip 80. The multiple second electrode pads 62 are arranged in the x direction. The multiple third electrode pads 63 are arranged at both ends of the chip main surface 60s in the x direction.

[0051] The high-voltage circuit chip 70 includes the high-voltage circuit 30 shown in FIG. 1. In plan view, the high-voltage circuit chip 70 has a rectangular shape with short and long sides. In plan view, the high-voltage circuit chip 70 is mounted on the high-voltage die pad 111 with the long sides aligned along the x direction and the short sides aligned along the y direction. As shown in FIG. 3, the high-voltage circuit chip 70 has a chip main surface 70s and a chip back surface 70r that face opposite each other in the z direction. The chip back surface 70r of the high-voltage circuit chip 70 is bonded to the high-voltage die pad 111 by a conductive bonding material SD.

[0052] A plurality of first electrode pads 71, a plurality of second electrode pads 72, and a plurality of third electrode pads 73 are formed on a chip main surface 70s of the high-voltage circuit chip 70. Each of the electrode pads 71 ​​to 73 is electrically connected to the high-voltage circuit 30.

[0053] The multiple first electrode pads 71 ​​are arranged at the end closest to the transformer chip 80 of both end portions in the y direction of the chip main surface 70s. The multiple first electrode pads 71 ​​are arranged in the x direction. The multiple second electrode pads 72 are arranged at the end farther from the transformer chip 80 of both end portions in the y direction of the chip main surface 70s. In other words, the multiple second electrode pads 72 are arranged at the end closer to the high-voltage lead 112 of both end portions in the y direction of the chip main surface 70s. The multiple second electrode pads 72 are arranged in the x direction. The multiple third electrode pads 73 are arranged at both end portions in the x direction of the chip main surface 70s.

[0054] The transformer chip 80 includes the transformer 40 (40A, 40B) shown in Figure 1. The shape of the transformer chip 80 in plan view is a rectangle having short and long sides. In this embodiment, the transformer chip 80 is mounted on the low-voltage die pad 101 so that the long sides are aligned in the x direction and the short sides are aligned in the y direction in plan view.

[0055] The transformer chip 80 is disposed adjacent to the low-voltage circuit chip 60 in the y direction. The transformer chip 80 is disposed closer to the high-voltage circuit chip 70 than the low-voltage circuit chip 60. In other words, the transformer chip 80 is disposed between the low-voltage circuit chip 60 and the high-voltage circuit chip 70 in the y direction.

[0056] 3, the transformer chip 80 has a chip main surface 80s and a chip back surface 80r that face opposite to each other in the z direction. The chip back surface 80r of the transformer chip 80 is bonded to the low-voltage die pad 101 by a conductive bonding material SD.

[0057] 2, a plurality of first electrode pads 81 and a plurality of second electrode pads 82 are formed on the chip main surface 80s of the transformer chip 80. The plurality of second electrode pads 82 are arranged, for example, at one of both ends in the y direction of the chip main surface 80s that is closer to the low-voltage circuit chip 60. The plurality of second electrode pads 82 are arranged in the x direction. The plurality of first electrode pads 81 are arranged, for example, near the center in the y direction of the chip main surface 80s. The plurality of first electrode pads 81 are arranged in the x direction.

[0058] 2, in order to set the dielectric strength voltage of the signal transmission device 10 to a preset dielectric strength voltage, it is necessary to separate the low-voltage die pad 101 and the high-voltage die pad 111, which are closest to each other on the lead frames 100 and 110. Therefore, in a plan view, the distance between the high-voltage circuit chip 70 and the transformer chip 80 is greater than the distance between the low-voltage circuit chip 60 and the transformer chip 80.

[0059] A plurality of wires W1 to W4 are connected to each of the low-voltage circuit chip 60, the transformer chip 80, and the high-voltage circuit chip 70. Each of the wires W1 to W4 is a bonding wire formed by a wire bonding device, and is made of a conductor containing, for example, Au (gold), Al (aluminum), Cu, or the like.

[0060] The low-voltage circuit chip 60 is electrically connected to the low-voltage lead frame 100 by wires W1. More specifically, the low-voltage circuit chip 60's first electrode pads 61 and third electrode pads 63 are connected to the low-voltage leads 102 by wires W1. The low-voltage circuit chip 60's third electrode pads 63 are connected to a pair of the low-voltage leads 102 that are integrated with the low-voltage die pad 101 by wires W1. This electrically connects the low-voltage circuit 20 to the low-voltage leads 102 (the external electrodes of the signal transmission device 10 that are electrically connected to the control circuit 503). In this embodiment, the pair of low-voltage leads 102 that are integrated with the low-voltage die pad 101 form ground terminals, and the low-voltage circuit 20 and the low-voltage die pad 101 are electrically connected by wires W1. As a result, the low-voltage die pad 101 has the same potential as the ground GND1 of the low-voltage circuit 20.

[0061] The high-voltage circuit chip 70 and the multiple high-voltage leads 112 of the high-voltage lead frame 110 are each electrically connected by a wire W4. More specifically, the multiple second electrode pads 72 and multiple third electrode pads 73 of the high-voltage circuit chip 70 are connected to the high-voltage leads 112 by the wire W4. This electrically connects the high-voltage circuit 30 and the multiple high-voltage leads 112 (external electrodes of the signal transmission device 10 that are electrically connected to the switching elements 501, etc.). In this embodiment, a pair of high-voltage leads 112 integrated with the high-voltage die pad 111 constitute ground terminals, and the high-voltage circuit 30 and the high-voltage die pad 111 are electrically connected by the wire W4. As a result, the high-voltage die pad 111 has the same potential as the ground GND2 of the high-voltage circuit 30.

[0062] The transformer chip 80 is connected to the low-voltage circuit chip 60 by wires W2. The transformer chip 80 is also connected to the high-voltage circuit chip 70 by wires W3. More specifically, the second electrode pads 82 of the transformer chip 80 are connected to the second electrode pads 62 of the low-voltage circuit chip 60 by wires W2. The first electrode pads 81 of the transformer chip 80 are connected to the first electrode pads 71 ​​of the high-voltage circuit chip 70 by wires W3.

[0063] The second coils 42 of the transformers 40A and 40B (see FIG. 1) are both electrically connected to the ground GND1 of the low-voltage circuit 20 via the wire W2, the low-voltage circuit chip 60, etc. The first coils 41 of the transformers 40A and 40B (see FIG. 1) are both electrically connected to the ground GND2 of the high-voltage circuit 30 via the wire W3, the high-voltage circuit chip 70, etc.

[0064] 4 to 11, an example of the configuration of the transformer chip 80 will be described. In the following description, the direction from the chip back surface 80r toward the chip main surface 80s of the transformer chip 80 shown in FIGS. 8 and 9 will be referred to as "upward," and the direction from the chip main surface 80s toward the chip back surface 80r will be referred to as "downward."

[0065] Fig. 4 is a perspective view showing the appearance of the transformer chip 80. Fig. 5 is a plan view of the transformer chip 80. For ease of explanation, in Fig. 5, the passivation film 160 is indicated by a two-dot chain line, and the transformers 40A and 40B and the floating dummy wiring 150 described later are indicated by dashed lines.

[0066] Fig. 6 is a cross-sectional view of the transformer chip 80 taken along the xy plane at the z-direction position of the second coil 42, showing the connection relationship of the second coil 42. Fig. 7 is a cross-sectional view of the transformer chip 80 taken along the xy plane at the z-direction position of the first coil 41, showing the connection relationship of the first coil 41. For convenience, hatching is omitted in Figs. 6 and 7.

[0067] Figure 8 is a cross-sectional view of the transformer chip 80 taken along line 8-8 in Figure 5, showing the cross-sectional structures of the first coil 41, floating dummy wiring 150, and first pad 81A. Figure 9 is a cross-sectional view of the transformer chip 80 taken along line 9-9 in Figure 5, showing the cross-sectional structures of the outer dummy wiring 44, floating dummy wiring 150, second pad 81C, and fourth pad 82C. For convenience, hatching has been omitted for some components in Figures 8 and 9.

[0068] Fig. 10 is a schematic plan view enlarging a portion of the transformer chip 80, showing the first pad 81A, the second pad 81C, the first coil 41, and the floating dummy wiring 150. Fig. 11 is a cross-sectional view of the transformer chip 80 taken along line 11-11 in Fig. 10, showing the cross-sectional structures of the first coil 41, the first pad 81A, and the second pad 81C.

[0069] As shown in Figure 5, the transformer chip 80 of this embodiment includes two pairs of transformers 40A, 40B. More specifically, the transformer chip 80 is a semiconductor chip that integrates the two pairs of transformers 40A, 40B into a single chip. In other words, the transformer chip 80 is provided separately from the low-voltage circuit chip 60 and the high-voltage circuit chip 70 (both of which are shown in Figure 2).

[0070] The transformers 40A and 40B are disposed near the center of the chip main surface 80s in the y direction in a plan view. In one example, the first electrode pads 81 and the transformers 40A and 40B are disposed in positions where they do not overlap each other in a plan view. Each of the electrode pads 81 and 82 is electrically connected to the transformers 40A and 40B.

[0071] The first electrode pads 81 include a first pad 81A arranged in the inner region 41A of the transformers 40A and 40B and a second pad 81C arranged outside the transformers 40A and 40B. The first pad 81A is electrically connected to each of the transformers 40A and 40B. In one example, the second pad 81C is arranged between the transformers 40A and 40B. The second pad 81C is electrically connected to the transformers 40A and 40B. It can be said that the second pad 81C is provided as a common pad for the two transformers 40A and 40B.

[0072] In a plan view, the first pad 81A has a shape in which the length in the y direction, which is orthogonal to the x direction, is greater than the length in the x direction in which the first electrode pads 81 are arranged. In one example, the shape of the first pad 81A is an ellipse that is long in the y direction. In a plan view, the second pad 81C has a shape in which the length in the y direction, which is orthogonal to the x direction, is greater than the length in the x direction in which the first electrode pads 81 are arranged. In one example, the shape of the second pad 81C is a rectangle that is long in the y direction.

[0073] In a plan view, the second electrode pads 82 are arranged at positions aligned with the two transformers 40A and the two transformers 40B in the x direction, and between the transformers 40A and 40B in the x direction. The second electrode pads 82 are arranged closer to the chip side surface 802 in the y direction than the transformers 40A and 40B. In other words, the second electrode pads 82 are arranged between the transformers 40A and 40B and the chip side surface 802 in the y direction. In other words, the second electrode pads 82 are arranged closer to the low-voltage lead 102 (see FIG. 2 ) than the transformers 40A and 40B in a plan view.

[0074] In a plan view, the second electrode pads 82 have a shape that is elongated in the x direction in which the second electrode pads 82 are arranged. In one example, the shape of the second electrode pads 82 is a rectangle that is elongated in the x direction. The second electrode pads 82 include a third pad 82A corresponding to the first pad 81A of the first electrode pad 81 and a fourth pad 82C corresponding to the second pad 81C of the first electrode pad 81. In the transformer chip 80 of this embodiment, the third pad 82A is electrically connected to each of the transformers 40A and 40B. The fourth pad 82C is electrically connected to the transformer 40A and the transformer 40B. It can be said that the fourth pad 82C is provided as a pad common to the two transformers 40A and 40B.

[0075] The third pad 82A is disposed at a position overlapping the transformers 40A and 40B when viewed from the y direction. The fourth pad 82C is disposed at a position overlapping the portion between the transformers 40A and 40B in the x direction when viewed from the y direction. Therefore, the multiple second electrode pads 82 (82A, 82C) are aligned with each other in the y direction and spaced apart from each other in the x direction.

[0076] Each pair of transformers 40A, 40B has the same configuration. Furthermore, the transformer 40B has the same configuration as the transformer 40A. Therefore, the detailed structure of the transformer 40A will be described, and a description of the transformer 40B will be omitted.

[0077] As shown in FIG. 5 , the transformer chip 80 has four chip side surfaces 801, 802, 803, and 804 that are perpendicular to both the chip main surface 80s and the chip back surface 80r. The chip side surfaces 801 to 804 are provided between the chip main surface 80s and the chip back surface 80r in the z direction. The chip side surfaces 801 and 802 form both end surfaces of the transformer chip 80 in the y direction, and the chip side surfaces 803 and 804 form both end surfaces of the transformer chip 80 in the x direction. In a plan view, the chip side surfaces 801 and 802 form the long sides of the transformer chip 80, and the chip side surfaces 803 and 804 form the short sides of the transformer chip 80. In this embodiment, the chip side surface 801 is closer to the high-voltage circuit chip 70 (see FIG. 2 ) than the chip side surface 802, and the chip side surface 802 is closer to the low-voltage circuit chip 60 (see FIG. 2 ) than the chip side surface 801.

[0078] 5, 8, and 9, the transformer chip 80 has a substrate 83 and an insulating layer 84 formed on the substrate 83. The substrate 83 is made of, for example, a semiconductor substrate. In this embodiment, the substrate 83 is made of a material containing Si (silicon). Examples of Si substrates used for the substrate 83 include a semiconductor substrate made of a single-crystal intrinsic semiconductor material, a p-type semiconductor substrate containing acceptor-type impurities, and an n-type semiconductor substrate containing donor-type impurities.

[0079] The substrate 83 may be a semiconductor substrate made of a wide bandgap semiconductor or a compound semiconductor. Alternatively, the substrate 83 may be an insulating substrate made of a material containing glass, instead of a semiconductor substrate. The wide bandgap semiconductor is a semiconductor substrate having a bandgap of 2.0 eV or more. Examples of wide bandgap semiconductors include SiC (silicon carbide), GaN (gallium nitride), and Ga ２ O ３ The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN, and GaAs (gallium arsenide).

[0080] The substrate 83 has a substrate main surface 83s and a substrate back surface 83r that face opposite to each other in the z direction. The substrate back surface 83r forms the chip back surface 80r of the transformer chip 80.

[0081] 8 and 9 , the insulating layer 84 of this embodiment has a plurality of insulating films 85 stacked in the z direction from the substrate main surface 83s of the substrate 83. In other words, the z direction can also be said to be the thickness direction of the insulating layer 84. The z direction can also be said to be the stacking direction of the insulating films 85. The insulating layer 84 is formed on the substrate main surface 83s of the substrate 83. The insulating layer 84 includes an upper surface 84s and a lower surface 84r facing the opposite side to the upper surface 84s.

[0082] The insulating film 85 has a first insulating film 85A and a second insulating film 85B formed on the first insulating film 85A. The first insulating film 85A is a thin film, and is, for example, an etching stopper layer. The first insulating film 85A is made of a material containing SiN (silicon nitride), SiC, SiCN (nitrogen-doped silicon carbide), or the like. In this embodiment, the first insulating film 85A is made of a material containing SiN. The second insulating film 85B is, for example, an interlayer insulating film. The second insulating film 85B is made of SiO ２ The second insulating film 85B is formed of a material containing silicon oxide (SiO 2 ). The thickness of the second insulating film 85B is thicker than the thickness of the first insulating film 85A. The thickness of the first insulating film 85A may be 100 nm or more and less than 1000 nm. The thickness of the second insulating film 85B may be 1000 nm or more and 3000 nm or less. In this embodiment, the thickness of the first insulating film 85A is, for example, about 300 nm, and the thickness of the second insulating film 85B is, for example, about 2000 nm.

[0083] Both the bottom insulating film 85L in contact with the substrate main surface 83s of the substrate 83 and the top insulating film 85U are composed of the second insulating film 85B. In one example, the thicknesses of both the bottom insulating film 85L and the top insulating film 85U are thinner than the other insulating films 85. The thicknesses of both the bottom insulating film 85L and the top insulating film 85U are equal to or greater than the thickness of the first insulating film 85A and equal to or less than the thickness of the second insulating film 85B.

[0084] The thicknesses of both the bottom insulating film 85L and the top insulating film 85U can be changed as desired. For example, the thicknesses of both the bottom insulating film 85L and the top insulating film 85U may be thicker than the thickness of the second insulating film 85B, or may be equal to or greater than the thickness of the insulating film 85 formed by the first insulating film 85A and the second insulating film 85B.

[0085] (Second Coil) As shown in FIG. 6 , the second coil 42 of the transformers 40A, 40B is formed by second coil wiring 46. The second coil wiring 46 has an elliptical spiral shape in a plan view. The second coil 42 is formed from a material including one or more appropriately selected from the group consisting of titanium (Ti), titanium nitride (TiN), gold (Au), silver (Ag), copper (Cu), aluminum (Al), and tungsten (W). An inner end wiring 57 is disposed inside the second coil wiring 46, and an outer end wiring 58 is disposed outside the second coil wiring 46. One end of the second coil wiring 46 is electrically connected to the inner end wiring 57, and the other end of the second coil wiring 46 is electrically connected to the outer end wiring 58.

[0086] The inner end wiring 57 and the outer end wiring 58 are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. The outer end wiring 58 is configured as a common end wiring for the second coils 42 of the transformers 40A and 40B. Note that an outer end wiring may be provided for each of the second coils 42 of the transformers 40A and 40B.

[0087] 6 and 8, the inner end wiring 57 is connected to the third pad 82A by a connection wiring 131A. The connection wiring 131A is made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0088] As shown in FIG. 8 , the connection wiring 131A includes a first wiring portion 132A extending in the z-direction so as to penetrate the multiple insulating films 85, and a second wiring portion 133A extending in the y-direction. The first wiring portion 132A is positioned so as to overlap the third pad 82A in a plan view and is connected to the third pad 82A. The first wiring portion 132A penetrates from the insulating film 85 below the top insulating film 85U to the insulating film 85 two layers above the bottom insulating film 85L. The first wiring portion 132A includes a flat wiring portion and multiple vias. The wiring portions are provided at the same positions as the insulating films 851 and 852 where the coils 41 and 42 are provided. Vias are provided between the two wiring portions in the z-direction, between the upper wiring portion and the third pad 82A, and between the lower wiring portion and the second wiring portion 133A.

[0089] The second wiring portion 133A is located closer to the substrate 83 than the first wiring portion 132A. The second wiring portion 133A is located closer to the substrate 83 than the second coil 42. In this embodiment, the second wiring portion 133A is located in an insulating film 85 one layer above the lowest insulating film 85L among the multiple insulating films 85. Of both ends of the second wiring portion 133A in the x direction, a first end closer to the chip side surface 802 of the transformer chip 80 is located at a position overlapping the first wiring portion 132A in a planar view. The second wiring portion 133A is connected to the first wiring portion 132A. A second end of the second wiring portion 133A opposite the first end is located at a position overlapping the second coil 42 of the transformer 40A in a planar view. More specifically, the second end is located at a position overlapping the inner end wiring 57 to which the second coil 42 of the transformer 40A is connected in a planar view. The second wiring portion 133A has a plurality of vias 134A that connect the second wiring portion 133A and the inner end wiring 57.

[0090] 6 and 9, the outer end wiring 58 is electrically connected to the fourth pad 82C by a connection wiring 131C. The connection wiring 131C is made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0091] 9, the connection wiring 131C has a first wiring portion 132C extending in the z direction so as to penetrate the multiple insulating films 85, and a second wiring portion 133C extending in the y direction. The first wiring portion 132C has a configuration similar to that of the first wiring portion 132A of the connection wiring 131A.

[0092] The first wiring portion 132C is disposed at a position overlapping the fourth pad 82C in a plan view and is connected to the fourth pad 82C. The first wiring portion 132C penetrates from the insulating film 85 below the uppermost insulating film 85U to the insulating film 85 two layers above the lowermost insulating film 85L among the multiple insulating films 85. The first wiring portion 132C has a flat wiring portion and multiple vias. The wiring portions are provided at the same positions as the insulating films 851 and 852 where the coils 41 and 42 are provided. Vias are provided between the two wiring portions in the z direction, between the upper wiring portion and the third pad 82A, and between the lower wiring portion and the second wiring portion 133C.

[0093] The second wiring portion 133C is located closer to the substrate 83 than the first wiring portion 132C. The second wiring portion 133C is located closer to the substrate 83 than the second coil 42. In this embodiment, the second wiring portion 133C is located in an insulating film 85 one layer above the lowest insulating film 85L among the multiple insulating films 85. Of both ends of the second wiring portion 133C in the x direction, a first end closer to the chip side surface 802 of the transformer chip 80 is located in a position overlapping the first wiring portion 132C in a plan view. The second wiring portion 133C is connected to the first wiring portion 132C. The second end of the second wiring portion 133C, opposite the first end, is located in a position not overlapping the second coil 42 of the transformer 40A in a plan view. More specifically, the second end is located in a position overlapping the outer end wiring 58 to which the second coil 42 of the transformer 40A is connected in a plan view. The second wiring portion 133C has a plurality of vias 134C that connect the second wiring portion 133C and the outer end wiring 58. The second wiring portion 133C of the connection wiring 131C is electrically connected to the substrate 83 by vias 136 that penetrate the insulating film 85L of the lowest layer. Note that the vias 136 may be omitted.

[0094] (First Coil) As shown in FIG. 7 , the first coil 41 of the transformers 40A, 40B includes a first coil wiring 43. The first coil wiring 43 has an elliptical spiral shape in a plan view. The first coil 41 is made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. A first pad 81A is disposed in an inner region 41A of the first coil wiring 43. A second pad 81C is disposed outside the first coil wiring 43. One end of the first coil wiring 43 is electrically connected to the first pad 81A, and the other end of the first coil wiring 43 is electrically connected to the second pad 81C.

[0095] The first electrode pads 81 (first pad 81A and second pad 81C) are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. The second pad 81C is configured as a pad common to the first coils 41 of the transformers 40A and 40B. Note that a configuration in which the second pad 81C is provided for each of the first coils 41 of the transformers 40A and 40B may also be adopted.

[0096] In this embodiment, the first coil wiring 43 is formed in the same winding direction as the second coil wiring 46 shown in Fig. 6 in a plan view. The number of turns of the first coil wiring 43 is the same as the number of turns of the second coil wiring 46.

[0097] 8, the second coil 42 and the first coil 41 of the transformer 40A (40B) are arranged opposite each other in the z direction via an insulating film 85. In this embodiment, the second coil 42 and the first coil 41 are arranged opposite each other in the z direction via a plurality of insulating films 85.

[0098] The second coil 42 is configured as a conductive layer embedded in one insulating film 85. More specifically, the insulating film 851 in which the second coil 42 is embedded has a coil groove (second coil groove) 141 that penetrates both the first insulating film 85A and the second insulating film 85B in the z direction. The conductive layer that constitutes the second coil 42 is embedded in the coil groove 141 of the insulating film 851. The insulating film 851 in which the second coil 42 is embedded is covered by the insulating film 85 that is adjacent to the insulating film 851 in the z direction. As a result, it can be said that the second coil 42 is embedded in the insulating film 85.

[0099] The first coil 41 is configured as a conductive layer embedded in one insulating film 85. More specifically, the insulating film 852 in which the first coil 41 is embedded has a coil groove (first coil groove) 142 that penetrates both the first insulating film 85A and the second insulating film 85B in the z-direction. The conductive layer that constitutes the first coil 41 is embedded in the coil groove 142 of the insulating film 852. The insulating film 852 in which the first coil 41 is embedded is covered by the insulating film 85 that is adjacent to the insulating film 852 in the z-direction. As a result, it can be said that the first coil 41 is embedded in the insulating film 85.

[0100] In the z direction, the first coil 41 is located farther from the substrate 83 than the second coil 42. In other words, the first coil 41 can be said to be located higher than the second coil 42. Furthermore, the second coil 42 can be said to be disposed closer to the substrate 83 than the first coil 41. In this embodiment, the distance between the second coil 42 and the first coil 41 in the z direction is greater than the distance between the second coil 42 and the substrate main surface 83s of the substrate 83.

[0101] 8, the first pad 81A includes a base wiring 51A and a pad wiring 52A electrically connected to the base wiring 51A. The base wiring 51A is disposed at the same position as the first coil wiring 43 in the z direction. That is, the base wiring 51A is formed in the insulating film 852 in which the first coil 41 is embedded. The base wiring 51A is formed in a through-hole that penetrates the insulating film 852 in the z direction. The pad wiring 52A is formed on the uppermost insulating film 85U. The pad wiring 52A is electrically connected to the base wiring 51A by a via 54A that penetrates the insulating film 85U.

[0102] As shown in FIG. 9 , the second pad 81C includes a base wiring 51C and a pad wiring 52C electrically connected to the base wiring 51C. The base wiring 51C is located at the same position in the z-direction as the first coil wiring 43 (see FIG. 8 ). That is, the base wiring 51C is formed in the insulating film 852 in which the first coil 41 and the base wiring 51A of the first pad 81A shown in FIG. 8 are embedded. The base wiring 51C is formed in a through-hole that penetrates the insulating film 852 in the z-direction. The pad wiring 52C is formed on the uppermost insulating film 85U. The pad wiring 52C is electrically connected to the base wiring 51C by a via 54C that penetrates the insulating film 85U.

[0103] 8, the third pad 82A includes a base wiring 91A and a pad wiring 92A electrically connected to the base wiring 91A. The base wiring 91A is disposed in the same position in the z-direction as the first coil wiring 43 and the base wiring 51A of the first pad 81A. That is, the base wiring 91A is formed in the insulating film 852 in which the first coil 41 is embedded. The base wiring 91A is formed in a through-hole that penetrates the insulating film 852 in the z-direction. The pad wiring 92A is formed on the uppermost insulating film 85U. The pad wiring 92A is electrically connected to the base wiring 91A by a via 94A that penetrates the insulating film 85U.

[0104] As shown in FIG. 9 , the fourth pad 82C includes a base wiring 91C and a pad wiring 92C electrically connected to the base wiring 91C. The base wiring 91C is disposed in the same position in the z direction as the first coil wiring 43 (see FIG. 8 ). That is, the base wiring 91C is formed in the insulating film 852 in which the first coil 41 shown in FIG. 8 is embedded. The base wiring 91C is formed in a through-hole that penetrates the insulating film 852 in the z direction. The pad wiring 92C is formed on the uppermost insulating film 85U. The pad wiring 92C is electrically connected to the base wiring 91C by a via 94C that penetrates the insulating film 85U.

[0105] 5 and 7 , the first coil 41 of this embodiment includes outer dummy wiring 44. The outer dummy wiring 44 is a wiring pattern formed so that no current flows through the first coil wiring 43 of the first coil 41. In this embodiment, the outer dummy wiring 44 includes first dummy wiring 44A, second dummy wiring 44B, and third dummy wiring 44C. The first dummy wiring 44A and the second dummy wiring 44B are formed from a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0106] In plan view, the first dummy wiring 44A is provided in a region where the second pad 81C is arranged, between the first coil wiring 43 of the transformer 40A and the first coil wiring 43 of the transformer 40B in the x direction. The third dummy wiring 44C is provided in a region where the second pad 81C is not arranged, between the first coil wiring 43 of the transformer 40A and the first coil wiring 43 of the transformer 40B in the x direction.

[0107] The first dummy wiring 44A and the third dummy wiring 44C are formed in a pattern different from that of the first coil wiring 43. The first dummy wiring 44A and the third dummy wiring 44C are composed of a plurality of wirings. The wiring width and wiring spacing of the first dummy wiring 44A and the third dummy wiring 44C, which are composed of a plurality of wirings, are, in one example, equal to the wiring width and wiring spacing of the first coil wiring 43. In other words, the density (wiring density) of the first dummy wiring 44A and the third dummy wiring 44C is equal to the density (wiring density) of the first coil wiring 43. Note that the densities of the first dummy wiring 44A and the third dummy wiring 44C may be different from the density of the first coil wiring 43. Furthermore, the density of the first dummy wiring 44A and the densities of the third dummy wiring 44C may be different from each other.

[0108] 7, the first dummy wiring 44A and the third dummy wiring 44C have, for example, first slits 44D formed along the y direction. The first slits 44D form the first dummy wiring 44A in an open ring shape. The first slits 44D suppress the formation of a current loop in the first dummy wiring 44A.

[0109] The first dummy wiring 44A and the third dummy wiring 44C are electrically connected to the second pad 81C of the first electrode pad 81. In one example, the first dummy wiring 44A includes a first connection portion 44E electrically connected to the second pad 81C. The position of the first connection portion 44E is arbitrary. Note that the first dummy wiring 44A only needs to be electrically connected to one of the second pads 81C. In this manner, the first dummy wiring 44A has the same potential as the first coil 41. Therefore, as the second reference potential of the first coil 41 changes, the voltage of the first dummy wiring 44A may sometimes become higher than that of the second coil 42, similar to the first coil 41.

[0110] 8 , although not shown, the first dummy wiring 44A is disposed in a position aligned with the first coil 41 in the z direction. In other words, the first dummy wiring 44A is disposed in a position farther from the substrate 83 than the second coil 42. In other words, it can be said that the floating dummy wiring 150 is provided around the coil of one of the transformers 40A and 40B that is closer to the chip main surface 80s of the transformer chip 80.

[0111] By making the first dummy wiring 44A have the same voltage as the first coil 41, it is possible to suppress a voltage drop between the first coil 41 and the first dummy wiring 44A. Therefore, it is possible to suppress electric field concentration on the first coil 41.

[0112] 7, the second dummy wiring 44B is formed to surround the first coil 41, the first dummy wiring 44A, and the third dummy wiring 44C in a plan view. The second dummy wiring 44B is electrically connected to the first dummy wiring 44A. That is, the second dummy wiring 44B is electrically connected to the first coil 41. In one example, the second dummy wiring 44B includes a second connection portion 44F electrically connected to the first dummy wiring 44A. The position of the second connection portion 44F is arbitrary.

[0113] The second dummy wiring 44B is composed of a plurality of wires surrounding the first coil 41 and the first dummy wiring 44A. The wire width and wire spacing of the second dummy wiring 44B composed of a plurality of wires are, for example, equal to the wire width and wire spacing of the first coil wiring 43 of the first coil 41. In other words, the density (wire density) of the second dummy wiring 44B is equal to the density (wire density) of the first coil wiring 43. Note that the density of the second dummy wiring 44B may be different from the density of the first coil wiring 43.

[0114] In one example, the second dummy wiring 44B has a second slit 44G formed along the y direction. The second slit 44G causes the second dummy wiring 44B to be formed in an open ring shape. The second slit 44G suppresses the formation of a current loop in the second dummy wiring 44B.

[0115] 8, the second dummy wiring 44B is arranged in a position aligned with the first coil 41 in the z direction. Although not shown, the second dummy wiring 44B is also arranged in a position aligned with the first coil 41 in the z direction. In other words, the second dummy wiring 44B is arranged in a position farther from the substrate 83 than the second coil 42. The second dummy wiring 44B suppresses electric field concentration around the first coil 41.

[0116] 7 , in the transformer chip 80 of this embodiment, the floating dummy wiring 150 includes a first dummy pattern 151 and a second dummy pattern 152. The first dummy pattern 151 is formed of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. The floating dummy wiring 150 includes a second dummy pattern 152. The second dummy pattern 152 is formed of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0117] 7 , the first dummy pattern 151 is formed to surround the second dummy wiring 44B in a plan view. The first dummy pattern 151 is electrically independent from the first coil 41. In other words, the first dummy pattern 151 is not electrically connected to the first coil 41.

[0118] The first dummy pattern 151 is composed of a plurality of wires. In one example, each of the plurality of wires is formed in a closed loop. In one example, the wire width of the first dummy pattern 151 composed of a plurality of wires is equal to the wire width of the first coil wire 43 of the first coil 41. In one example, the wire spacing of the first dummy pattern 151 is greater than the wire spacing of the first coil wire 43 of the first coil 41. In other words, the density (wiring density) of the first dummy pattern 151 is lower than the density (wiring density) of the first coil wire 43. Note that the density of the first dummy pattern 151 may be equal to the density of the first coil wire 43.

[0119] As shown in Figure 8, the first dummy pattern 151 is arranged in a position aligned with the first coil 41 in the z direction. Also, although not shown, the first dummy pattern 151 is arranged in a position aligned with the first coil 41 in the z direction. In other words, the first dummy pattern 151 is arranged in a position farther from the substrate 83 than the second coil 42. As shown in Figures 8 and 9, the outer dummy wirings 44 (44A, 44B) and the floating dummy wiring 150 (first dummy pattern 151) are arranged in positions aligned with each other in the z direction. The first dummy pattern 151 suppresses an increase in the electric field strength around the first coil 41.

[0120] 7 , the second dummy pattern 152 is disposed between the first coil 41 and the second electrode pad 82 in a plan view. The second dummy pattern 152 extends along the x direction. The second dummy pattern 152 is formed along the plurality of second electrode pads 82 in a plan view. The second dummy pattern 152 may include a plurality of wirings. The second dummy pattern 152 is electrically independent from the first coil 41. In other words, the second dummy pattern 152 is not electrically connected to the first coil 41. The second dummy pattern 152 separates the plurality of second electrode pads 82 from the first coil 41.

[0121] As shown in Figures 8 and 9, the transformer chip 80 includes a passivation film 160. The passivation film 160 is formed on the upper surface 84s of the insulating layer 84. The passivation film 160 is a film that protects the insulating layer 84. The passivation film 160 is a surface protection film for the transformer chip 80. The passivation film 160 is formed from a material containing, for example, silicon oxide or silicon nitride. Examples of materials containing silicon nitride include SiN and SiCN. The passivation film 160 forms the chip main surface 80s of the transformer chip 80.

[0122] The second electrode pad 82 and the first electrode pad 81 are covered with a passivation film 160. The passivation film 160 has openings that expose portions of the second electrode pad 82 and the first electrode pad 81. As a result, the second electrode pad 82 has an exposed surface for connecting the wire W2. The first electrode pad 81 has an exposed surface for connecting the wire W3.

[0123] The transformer chip 80 includes a resin layer 170 formed on a passivation film 160. The resin layer 170 is formed of a material containing, for example, polyimide (PI). The resin layer 170 is separated into an inner resin layer and an outer resin layer by a separation groove 173. As shown in FIG. 4 , the separation groove 173 is formed to surround the transformers 40A and 40B in a plan view. The resin layer 170 includes a first resin opening 174 exposing the second electrode pad 82 and a second resin opening 175 exposing the first electrode pad 81.

[0124] 7, 10, and 11, the first pad 81A is disposed in an inner region 41A surrounded by the first coil 41 in a plan view. The inner region 41A has an elliptical spiral shape, which is the shape of the first coil 41.

[0125] As shown in FIGS. 7 , 8 , 10 , and 11 , in a plan view, the pad wiring 52A of the first pad 81A has a first extension portion 53A extending toward the first coil 41. It can be said that the first pad 81A has the first extension portion 53A. The first extension portion 53A extends toward the first coil 41 from a position 5 μm inward from the inner circumferential end 41AA of the first coil 41. In this embodiment, the first coil 41 is formed by the first coil wiring 43. The inner circumferential end 41AA of the first coil 41 is the inner circumferential end of the first coil wiring 43. The distance L1 between the tip 53AA of the first extension portion 53A and the inner circumferential end 41AA of the first coil 41 is preferably 5 μm or less. The first extension portion 53A is formed in an annular shape. It is preferable that the distance L1 from the tip 53AA of the first extending portion 53A to the inner circumferential end 41AA be 5 μm or less over the entire circumference of the first extending portion 53A.

[0126] 7, 9, and 10, pad wiring 52C of second pad 81C is disposed outside first coil 41 and adjacent to first pad 81A. Second pad 81C is disposed in outer region 41B surrounded by first coil wiring 43 of first coil 41 of transformers 40A and 40B and outer dummy wiring 44. In one example, outer region 41B has a rectangular shape that is long in the y direction, which is orthogonal to the x direction in plan view, relative to the x direction in which first coils 41 are adjacent to each other.

[0127] As shown in Figures 9, 10, and 11, in a plan view, the pad wiring 52C of the second pad 81C has a second extension portion 53C extending toward the first coil 41. It can be said that the second pad 81C has the second extension portion 53C. The second extension portion 53C extends toward the first coil wiring 43 and the outer dummy wiring 44 from a position 5 μm away from the wiring portions of the first coil wiring 43 and the outer dummy wiring 44 that define the outer region 41B. In one example, the second extension portion 53C extends toward both the first coil wiring 43 and the outer dummy wiring 44. It is preferable that the distance L2 from the tip 53CA of the second extension portion 53C to the ends of the first coil wiring 43 and the outer dummy wiring 44 be 5 μm or less. The second extension portion 53C is formed in a ring shape. The distance L2 from the tip 53CA of the second extending portion 53C to the first coil wiring 43 and the outer dummy wiring 44 is preferably 5 μm or less over the entire circumference of the second extending portion 53C. Note that the distance between the second extending portion 53C and at least one of the first coil wiring 43 and the outer dummy wiring 44 and the second extending portion 53C does not have to be 5 μm or less in some parts in the circumferential direction of the second extending portion 53C.

[0128] (Operation) Next, the operation of the transformer chip 80 of this embodiment will be described. FIG. 12 shows the results of a simulation of the electric field distribution and electric field strength near the first coil 41 (first coil wiring 43) and the first pad 81A in the transformer chip 80 of this embodiment. FIG. 13 shows the results of a simulation of the electric field distribution and electric field strength near the first coil 41X (first coil wiring 43) and the first pad 81A in the transformer chip 80X of the comparative example. In FIGS. 12 and 13, the shade of the dots indicates the strength of the electric field strength. Higher electric field strength is indicated by darker dots. Also, in FIGS. 12 and 13, the two-dot chain lines indicate equipotential lines (electric field distribution).

[0129] As shown in FIG. 13 , in the transformer chip 80X of the comparative example, the distance L1X between the end of the first pad 81A and the inner peripheral end 41AA of the first coil 41X is greater than the distance L1 in the transformer chip 80 of this embodiment. The distance L1X in the comparative example is, for example, 20 μm. In this transformer chip 80X of the comparative example, the equipotential lines extend from between the first coil 41X and the first pad 81A around to the upper side of the first coil 41X. Therefore, it can be seen that electric field concentration occurs at the inner peripheral end of the first coil 41X. This electric field concentration reduces the dielectric strength of the transformer chip 80X.

[0130] As shown in FIG. 12 , in the transformer chip 80 of this embodiment, the first pad 81A is disposed in an inner region 41A surrounded by the first coil 41 (first coil wiring 43) in a plan view. The first pad 81A has a first extension portion 53A extending toward the first coil 41 from a position 5 μm inward from the inner circumferential end 41AA of the first coil 41. It can be seen that this first extension portion 53A prevents equipotential lines from wrapping around the upper side of the first coil 41. This reduces electric field concentration at the inner circumferential end 41AA of the first coil 41. In other words, the first extension portion 53A of the first pad 81A suppresses electric field concentration at the inner circumferential end 41AA of the first coil 41. This improves the dielectric strength of the transformer chip 80.

[0131] In the transformer chip 80 of this embodiment, the second pad 81C is disposed in the outer region 41B surrounded by the first coil 41 (first coil wiring 43) and the outer dummy wiring 44 in a plan view. The second pad 81C has a second extension portion 53C extending toward the first coil 41. The second extension portion 53C extends toward the first coil wiring 43 and the outer dummy wiring 44 from a position 5 μm away from the wiring portions of the first coil wiring 43 and the outer dummy wiring 44 that define the outer region 41B. Therefore, similar to the first pad 81A, the second extension portion 53C of the second pad 81C can prevent equipotential lines from wrapping around to the upper side of the first coil 41. This can alleviate electric field concentration at the outer peripheral edge of the first coil 41 that defines the outer region 41B. This improves the dielectric strength of the transformer chip 80.

[0132] The first pad 81A has a first extension portion 53A that extends toward the first coil 41 beyond a position 5 μm inward from the inner circumferential end 41AA of the first coil 41. It can be seen that this first extension portion 53A prevents equipotential lines from wrapping around to the upper side of the first coil 41. This reduces electric field concentration at the inner circumferential end 41AA of the first coil 41. In other words, the first extension portion 53A of the first pad 81A suppresses electric field concentration at the inner circumferential end 41AA of the first coil 41. This improves the dielectric strength of the transformer chip 80.

[0133] 5, 7, and 8, the first coil 41 of the transformer chip 80 includes outer dummy wiring 44 that surrounds the first coil wiring 43. Although not shown, the equipotential lines in the transformers 40A and 40B bypass the outer dummy wiring 44 that surrounds the first coil wiring 43. Therefore, electric field concentration at the outer peripheral edge of the first coil wiring 43 is alleviated.

[0134] Furthermore, the first coil 41 of the transformer chip 80 includes floating dummy wiring 150 (first dummy pattern 151) surrounding the outer dummy wiring 44. Although not shown, the equipotential lines in the transformers 40A and 40B bypass the floating dummy wiring 150 surrounding the outer dummy wiring 44. Therefore, electric field concentration at the outer peripheral edge of the outer dummy wiring 44, i.e., the outer peripheral edge of the first coil 41, is alleviated.

[0135] (Effects) As described above, one embodiment provides the following effects. (1) In the transformer chip 80 of this embodiment, the first pad 81A is disposed in the inner region 41A surrounded by the first coil 41 (first coil wiring 43) in a plan view. The first pad 81A has a first extension portion 53A that extends toward the first coil 41 beyond a position 5 μm inward from the inner circumferential end 41AA of the first coil 41. It can be seen that this first extension portion 53A prevents equipotential lines from wrapping around to the upper side of the first coil 41. This reduces electric field concentration at the inner circumferential end 41AA of the first coil 41. In other words, the first extension portion 53A of the first pad 81A suppresses electric field concentration at the inner circumferential end 41AA of the first coil 41. This improves the dielectric strength of the transformer chip 80.

[0136] (2) In a plan view, the second pad 81C is disposed in the outer region 41B surrounded by the first coil 41 (first coil wiring 43) and the outer dummy wiring 44. The second pad 81C has a second extension portion 53C extending toward the first coil 41. The second extension portion 53C extends toward the first coil wiring 43 and the outer dummy wiring 44 from a position 5 μm away from the wiring portions of the first coil wiring 43 and the outer dummy wiring 44 that define the outer region 41B. Therefore, similar to the first pad 81A, the second extension portion 53C of the second pad 81C can prevent equipotential lines from wrapping around to the upper side of the first coil 41. This can alleviate electric field concentration at the outer peripheral edge of the first coil 41. This improves the dielectric strength of the transformer chip 80.

[0137] (3) The first coil 41 of the transformer chip 80 includes outer dummy wiring 44 that surrounds the first coil wiring 43. The equipotential lines in the transformers 40A and 40B bypass the outer dummy wiring 44 that surrounds the first coil wiring 43. This reduces electric field concentration at the outer circumferential edge of the first coil wiring 43. This allows the dielectric strength of the transformer chip 80 to be improved.

[0138] (4) The first coil 41 of the transformer chip 80 includes floating dummy wiring 150 (first dummy pattern 151) surrounding the outer dummy wiring 44. The equipotential lines in the transformers 40A and 40B bypass the floating dummy wiring 150 surrounding the outer dummy wiring 44. This reduces electric field concentration at the outer circumferential edge of the outer dummy wiring 44, i.e., the outer circumferential edge of the first coil 41. This improves the dielectric strength of the transformer chip 80.

[0139] (5) In the transformer chip 80, multiple transformers 40A, 40B are arranged in a row along the x direction. The arrangement direction of these transformers 40A, 40B corresponds to the longitudinal direction of the transformer chip 80 in a plan view. The first coil 41 and the second coil 42 of each transformer 40A, 40B are formed in an oval shape elongated in the y direction, in which the first electrode pads 81 and the second electrode pads 82 are aligned, in a plan view. In the transformer chip 80 of this embodiment, the y direction corresponds to the width direction (short direction) of the transformer chip 80. Therefore, the longitudinal length of the transformer chip 80 can be shortened compared to a transformer chip 80 including the same number of transformers 40A, 40B, for example, in which the transformers 40A, 40B are arranged in an oval shape elongated in the longitudinal direction. This prevents the longitudinal length of the transformer chip 80 from increasing when the number of transformers 40 is increased.

[0140] (Modifications) The above embodiment can be modified, for example, as follows. The above embodiment and each of the following modifications can be combined with each other as long as no technical contradiction occurs. In the following modifications, parts that are common to the above embodiment will be assigned the same reference numerals as in the above embodiment, and their description will be omitted.

[0141] 14 and 15, the pad wiring 52A of the first pad 81A may be formed so as to cover a portion of the first coil wiring 43. In one example, the shape of the pad wiring 52A of the first pad 81A may be a rectangle whose length in the y direction is longer than its length in the x direction. Also, as shown in FIG. 16, the pad wiring 52A of the first pad 81A may be a polygonal shape (an octagonal shape in FIG. 16). Also, the first pad 81A may be formed so as to cover the entire inner region 41A.

[0142] Similarly, the pad wiring 52C of the second pad 81C may be formed so as to cover a portion of the first coil wiring 43. Furthermore, the pad wiring 52C of the second pad 81C may be formed so as to cover a portion of the outer dummy wiring 44. Furthermore, the pad wiring 52C of the second pad 81C may be formed so as to cover both a portion of the first coil wiring 43 and a portion of the outer dummy wiring 44, that is, so as to cover the entire outer region 41B. The shape of the pad wiring 52C of the second pad 81C may be any shape, such as an oval shape or a polygonal shape (octagonal shape), similar to the first pad 81A.

[0143] The sizes of the first pad 81A (pad wiring 52A) and the second pad 81C (pad wiring 52C) in a plan view may be changed as appropriate. For example, as shown in Figures 14 and 15, the size of the second pad 81C is smaller than the size of the first pad 81A in a plan view. The size of the second pad 81C may be equal to or larger than the size of the first pad 81A.

[0144] The configuration of the first pad 81A may be changed as appropriate. In the transformer chip 80 shown in Fig. 17, the first pad 81A includes a base wiring 51A and a cap wiring 55A that contacts an upper surface 51As of the base wiring 51A. The base wiring 51A is disposed at the same position in the z direction as the first coil wiring 43 of the first coil 41.

[0145] The cap wiring 55A is formed on the upper surface of the insulating film 85U. The insulating film 85U has an opening 85U1 that exposes a portion of the upper surface 51As of the base wiring 51A. The cap wiring 55A is electrically connected to the base wiring 51A by contacting the upper surface 51As of the base wiring 51A within the opening 85U1 of the insulating film 85U. The cap wiring 55A is made of a material containing one or more appropriately selected from Cu, Al, Ni (nickel), Pd (palladium), and W.

[0146] The cap wiring 55A protrudes beyond the base wiring 51A. The cap wiring 55A includes a first extension portion 56A that extends toward the first coil 41. In the transformer chip 80 configured in this manner, the first extension portion 56A of the cap wiring 55A can mitigate electric field concentration at the inner circumferential end 41AA of the first coil 41. This can improve the dielectric strength of the transformer chip 80.

[0147] 17, the transformer chip 80 shown in Fig. 18 has a first pad 81A that includes a base wiring 51A and a cap wiring 55A. In this transformer chip 80, the base wiring 51A protrudes beyond the cap wiring 55A. The base wiring 51A includes a first extension portion 57A that extends toward the first coil 41. In the transformer chip 80 configured in this manner, the first extension portion 57A of the base wiring 51A can alleviate electric field concentration at the inner circumferential end 41AA of the first coil 41. This can improve the dielectric strength of the transformer chip 80.

[0148] 17, the transformer chip 80 shown in Fig. 19 has a first pad 81A that includes a base wiring 51A and a cap wiring 55A. In this transformer chip 80, both the base wiring 51A and the cap wiring 55A extend toward the first coil 41. That is, in this transformer chip 80, both the base wiring 51A and the cap wiring 55A include the first extension portions 53A and 57A. This allows the dielectric strength of the transformer chip 80 to be improved.

[0149] In the transformer chip 80 shown in FIGS. 17, 18, and 19, the third pad 82A can include a base wiring 51C and a cap wiring in contact with the upper surface of the base wiring 51C, similar to the first pad 81A.

[0150] 17 to 19, the first pad 81A has been described, but the second pad 81C shown in Fig. 9 can also have the same configuration as the first pad 81A. Also, while the third pad 82A has been described in Fig. 17 to 19, the fourth pad 82C shown in Fig. 9 can also have the same configuration.

[0151] The transformer chip 80 shown in Figures 20 and 21 includes inner dummy wiring 45 arranged in the inner region 41A of the first coil 41. The inner dummy wiring 45 includes a plurality of wirings extending along the inside of the first coil wiring 43. The inner dummy wiring 45 is electrically connected to the first coil wiring 43. The first coil wiring 43 includes a connection portion 43A electrically connected to the first pad 81A. The inner dummy wiring 45 is electrically connected to the first coil wiring 43 by this connection portion 43A. The inner dummy wiring 45 has a slit 45B and is formed in an open ring shape.

[0152] In this transformer chip 80, the first coil 41 can be said to include the inner dummy wiring 45. The inner end of the first coil 41 is the inner end 45AA of the inner dummy wiring 45. The pad wiring 52A of the first pad 81A has a first extension portion 53A extending toward the inner dummy wiring 45. The distance L3 between the tip 53AA of the first extension portion 53A and the inner end 45AA of the inner dummy wiring 45 is 5 μm or less. Similar to the transformer chip 80 of the above embodiment, the transformer chip 80 of this modified example can reduce electric field concentration at the inner end 41AA of the first coil 41, thereby improving the dielectric strength of the transformer chip 80. In this transformer chip 80, the pad wiring 52A of the first pad 81A may be formed to cover part or all of the inner dummy wiring 45 in a plan view.

[0153] 22 and 23, the transformer chip 80 has a first coil wiring 43 of a first coil 41 arranged in place of the inner dummy wiring 45 of the transformer chip 80 shown in FIGS. 20 and 21. That is, the first coil wiring 43 of the first coil 41 is wound toward the base wiring 51A of the first pad 81A, resulting in a larger number of turns of the first coil wiring 43. The second coil wiring 46 of the second coil 42 is wound toward the inner end wiring 57, similar to the first coil wiring 43. In this transformer chip 80, the number of turns of the first coil wiring 43 and the second coil wiring 46 are the same. However, the number of turns of the first coil wiring 43 and the second coil wiring 46 may be different.

[0154] The pad wiring 52A of the first pad 81A has a first extension portion 53A extending toward the first coil wiring 43. The distance L4 between the tip 53AA of the first extension portion 53A and the inner peripheral end 41AA of the first coil wiring 43 is 5 μm or less. The transformer chip 80 configured in this manner, like the transformer chip 80 of the above embodiment, can alleviate electric field concentration at the inner peripheral end 41AA of the first coil 41, thereby improving the dielectric strength of the transformer chip 80.

[0155] The number of transformers included in the transformer chip can be changed as appropriate. The transformer chip 80 shown in FIG. 24 includes four pairs of transformers 40A, 40B. In this way, in a transformer chip 80 including many transformers 40A, 40B, it is possible to suppress an increase in the length in the longitudinal direction (x direction). In other words, it is possible to increase the number of transformers included in the transformer chip 80 while suppressing an increase in the length in the longitudinal direction (x direction) of the transformer chip 80. Furthermore, in this transformer chip 80, it is possible to improve the dielectric strength voltage.

[0156] The transformer chip 80 shown in FIG. 25 includes a pair of transformers 40A and 40B. This transformer chip 80 can have an improved dielectric strength. The transformer chip 80 shown in FIG. 26 includes one transformer 40. In this transformer chip 80, the second pad 81C is disposed in an outer region 41B surrounded by the first coil wiring 43 of the first coil 41 and the first dummy wiring 44A and second dummy wiring 44B of the outer dummy wiring 44. This transformer chip 80 can have an improved dielectric strength, similar to the transformer chip 80 of the above embodiment.

[0157] The configuration of the signal transmission device can be changed as needed. A configuration may be adopted in which a plurality of transformers are connected in series between the low-voltage circuit 20 and the high-voltage circuit 30 to transmit signals.

[0158] 27 shows an example of a signal transmission device 10. This signal transmission device 10 includes two transformers 40, 240 between a low-voltage circuit 20 and a high-voltage circuit 30. In one example, the signal transmission device 10 includes two transformers 40A, 240A that transmit a set signal and two transformers 40B, 240B that transmit a reset signal.

[0159] The transformers 40A and 40B include a first coil 41 and a second coil 42. The transformers 240A and 240B include a first coil 241 and a second coil 242. The second coils 42 of the transformers 40A and 40B are electrically connected to the low-voltage circuit 20. The first coils 41 of the transformers 40A and 40B are electrically connected to the first coils 241 of the transformers 240A and 240B. The second coils 242 of the transformers 240A and 240B are electrically connected to the high-voltage circuit 30.

[0160] Figure 28 shows an example of a plan view illustrating the internal configuration of the signal transmission device 10 of Figure 27. The signal transmission device 10 includes a low-voltage circuit chip 60, a high-voltage circuit chip 70, a first transformer chip 80, and a second transformer chip 280. The low-voltage circuit chip 60, the high-voltage circuit chip 70, the first transformer chip 80, and the second transformer chip 280 are arranged spaced apart from each other in the y direction. These chips 60, 70, 80, and 280 are arranged in the arrangement direction of the low-voltage die pad 101 and the high-voltage die pad 111.

[0161] 28 , the low-voltage circuit chip 60, the first transformer chip 80, the second transformer chip 280, and the high-voltage circuit chip 70 are arranged in this order from the low-voltage lead 102 toward the high-voltage lead 112. In other words, the first transformer chip 80 and the second transformer chip 280 are arranged between the low-voltage circuit chip 60 and the high-voltage circuit chip 70 in a plan view.

[0162] Both the low-voltage circuit chip 60 and the first transformer chip 80 are mounted on a low-voltage die pad 101 of a low-voltage lead frame 100. The high-voltage circuit chip 70 and the second transformer chip 280 are mounted on a high-voltage die pad 111 of a high-voltage lead frame 110. The second electrode pads 82 of the first transformer chip 80 and the second transformer chip 280 are electrically connected to the high-voltage circuit chip 70 by wires W3. The first electrode pads 81 of the second transformer chip 280 are electrically connected to the first electrode pads 81 of the first transformer chip 80 by wires W5.

[0163] Both the first transformer chip 80 and the second transformer chip 280 have the same configuration as the transformer chip 80 of the above embodiment. Therefore, the dielectric strength is improved in both the first transformer chip 80 and the second transformer chip 280. The signal transmission device 10 has a dielectric strength corresponding to the dielectric strength of each of the first transformer chip 80 and the second transformer chip 280 connected in series.

[0164] The term "on" as used in this disclosure includes both the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0165] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (for example, the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the x-direction may be the vertical direction, or the y-direction may be the vertical direction.

[0166] (Supplementary Notes) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the Supplementary Notes are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples to aid understanding, and the components described in each Supplementary Note should not be limited to the components indicated by the reference symbols.

[0167] (Supplementary Note 1) A transformer chip comprising: an insulating layer (84) including an upper surface and a lower surface facing opposite each other in a thickness direction; a first coil (41) arranged in the insulating layer (84) near the upper surface; a second coil (42) arranged in the insulating layer (84) near the lower surface and facing the first coil (41); and a first pad (81A) formed on the upper surface and electrically connected to the first coil (41), wherein the first pad (81A) is arranged in an inner region (41A) surrounded by the first coil (41) when viewed from the thickness direction, and includes a first extension portion (53A) extending toward the first coil (41) beyond a position 5 μm inward from an inner peripheral end of the first coil (41).

[0168] (Supplementary Note 2) The transformer chip according to Supplementary Note 1, wherein the first extension portion (53A) is formed in an annular shape, and the distance from the tip to the inner peripheral end of the first extension portion (53A) is 5 μm or less over the entire circumference.

[0169] (Supplementary Note 3) The transformer chip according to Supplementary Note 1 or Supplementary Note 2, wherein the first pad (81A) covers the entire inner region (41A).

[0170] (Supplementary Note 4) The transformer chip described in any one of Supplementary Note 1 to Supplementary Note 3, wherein the first coil (41) includes a spiral coil wiring through which a current flows, and the inner peripheral end of the first coil (41) is the inner peripheral end of the coil wiring.

[0171] (Supplementary Note 5) The transformer chip described in any one of Supplementary Note 1 to Supplementary Note 3, wherein the first coil (41) includes a spiral coil wiring (43) through which a current flows, and an inner dummy wiring (45) that is provided inside the coil wiring and is configured so that the current does not flow, and the inner end of the first coil (41) is the inner end of the inner dummy wiring (45).

[0172] (Supplementary Note 6) The transformer chip according to Supplementary Note 5, wherein the inner dummy wiring (45) is formed in an open ring shape having a slit (45B).

[0173] (Supplementary Note 7) The transformer chip according to Supplementary Note 5 or Supplementary Note 6, wherein the density of the inner dummy wiring (45) is equal to the density of the coil wiring.

[0174] (Appendix 8) A transformer chip described in any one of Appendices 4 to 7, comprising a second pad (81C) provided separately from the first pad (81A) and electrically connected to the first coil (41), the second pad (81C) being arranged outside the first coil (41) and next to the first pad (81A), and including a second extension portion (53C) extending toward the first coil (41) beyond a position 5 μm away from the outer peripheral end of the first coil (41) when viewed in the thickness direction.

[0175] (Appendix 9) The transformer chip described in Appendix 8, wherein the first coil (41) is provided with an outer dummy wiring (44) that is arranged outside the coil wiring when viewed from the thickness direction and is configured so that the current does not flow, the second pad (81C) is arranged within an outer region (41B) surrounded by the coil wiring and the outer dummy wiring (44), and the second extension portion (53C) extends toward both the coil wiring and the outer dummy wiring (44) from a position more than 5 μm away from the wiring portions of the coil wiring and the outer dummy wiring (44) that define the outer region (41B).

[0176] (Appendix 10) The transformer chip described in Appendix 9, wherein the second extension portion (53C) is formed in a ring shape, and the distance from the tip of the second extension portion (53C) to the ends of the coil wiring and the outer dummy wiring (44) is 5 μm or less around the entire circumference.

[0177] (Supplementary Note 11) The transformer chip according to Supplementary Note 9 or Supplementary Note 10, wherein the second pad (81C) covers the entire outer region (41B).

[0178] (Appendix 12) A transformer chip described in any one of Appendices 8 to 11, wherein, when viewed from the thickness direction, the second pad (81C) is arranged in a line in a first direction relative to the first pad (81A), and the second pad (81C) has a rectangular shape that is long in a second direction perpendicular to the first direction when viewed from the thickness direction.

[0179] (Appendix 13) The transformer chip described in Appendix 12, wherein the inner region (41A) has an elliptical shape that is long in the second direction, and the first pad (81A) has an elliptical shape that is long in the second direction corresponding to the inner region (41A).

[0180] (Appendix 14) The transformer chip described in Appendix 12, wherein the inner region (41A) has an elliptical shape that is long in the second direction, and the first pad (81A) has a rectangular shape that is long in the second direction corresponding to the inner region (41A).

[0181] (Appendix 15) A transformer chip described in any one of Appendixes 1 to 14, wherein the first pad (81A) has a base wiring (51A) arranged at the same position as the first coil (41) in the thickness direction, and a cap wiring (55A) in contact with the upper surface of the base wiring, and the cap wiring protrudes beyond the base wiring and includes the first extension portion (53A).

[0182] (Appendix 16) A transformer chip described in any one of Appendices 1 to 14, wherein the first pad (81A) has a base wiring (51A) arranged at the same position as the first coil (41) in the thickness direction, and a cap wiring (55A) contacting the upper surface of the base wiring, wherein the base wiring protrudes beyond the cap wiring and the base wiring includes the first extension portion (53A).

[0183] (Appendix 17) A transformer chip described in any one of Appendices 1 to 14, wherein the first pad (81A) has a base wiring (51A) arranged at the same position as the first coil (41) in the thickness direction, and a cap wiring (55A) contacting the upper surface of the base wiring, and the cap wiring and the base wiring form the first extension portion (53A).

[0184] (Supplementary Note 18) The transformer chip according to any one of Supplementary Note 1 to Supplementary Note 17, wherein the second coil (42) is formed in a spiral shape overlapping the first coil (41) in the thickness direction.

[0185] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0186] 10 Signal transmission device 20 Low-voltage circuit 21A, 21B Low-voltage signal line 30 High-voltage circuit 31A, 31B High-voltage signal line 40, 40A, 40B Transformer 41 Coil (first coil) 41A Inner region 41AA Inner peripheral end 41B Outer region 42 Coil (second coil) 43 First coil wiring 43A Connection portion 44 Outer dummy wiring 44A First dummy wiring 44B Second dummy wiring 44C Third dummy wiring 44D First slit 44E First connection portion 44F Second connection portion 44G Second slit 45 Inner dummy wiring 45AA Inner end portion 46 Second coil wiring 51A Base wiring 51As Upper surface 51C Base wiring 51Cs Upper surface 52A, 52C Pad wiring 53A First extending portion 53AA Tip 53C Second extending portion 53CA Tip 54A, 54C Via 55A, 55C Cap wiring 57A First extending portion 57 Inner end wiring 58 Outer end wiring 60 Low-voltage circuit chip 60r Chip back surface 60s Chip main surface 61 First electrode pad 62 Second electrode pad 63 Third electrode pad 70 High-voltage circuit chip 70r Chip back surface 70s Chip main surface 71 First electrode pad 72 Second electrode pad 73 Third electrode pad 80 Transformer chip (first transformer chip) 801 to 804 Chip side surface 80r Chip back surface 80s Chip main surface 81 First electrode pad 81A First pad 81C Second pad 82 Second electrode pad 82A Third pad 82C Fourth pad 83 Substrate 83r Back surface of substrate 83s Main surface of substrate 84 Insulating layer 84r Lower surface 84s Upper surface 85, 851, 852 Insulating film 85A First insulating film 85B Second insulating film 85L, 85U Insulating film 85U1 Opening 91A, 91C Base wiring 92A, 92C Pad wiring 94A, 94C Via 100 Low-voltage lead frame 101 Die pad 101 Low-voltage die pad 102 Low-voltage lead 110 High-voltage lead frame 111 High-voltage die pad 112 High-voltage lead 120 Molding resin 121 to 124 Resin side surface 131A,131C Connection wiring 132A, 132C First wiring portion 133A, 133C Second wiring portion 134A, 134C Via 136 Via 141, 142 Coil groove 150 Floating dummy wiring 151 First dummy pattern 152 Second dummy pattern 160 Passivation film 170 Resin layer 173 Separation groove 174 First resin opening 175 Second resin opening 240A, 240B Transformer 241 First coil 242 Second coil 280 Second transformer chip 500 Inverter device 501, 502 Switching element 503 Control circuit GND1, GND2 Ground L1 to L4 Distance SD Conductive bonding material V1 First voltage V2 Second voltage W1 to W4 Wire,

Claims

1. an insulating layer including an upper surface and a lower surface facing opposite to each other in a thickness direction; a first coil disposed in the insulating layer near the upper surface; a second coil disposed in the insulating layer near the lower surface and facing the first coil; a first pad formed on the top surface and electrically connected to the first coil; Including, The first pad is disposed in an inner region surrounded by the first coil when viewed from the thickness direction, and includes a first extension portion that extends toward the first coil beyond a position 5 μm away from an inner circumferential end of the first coil. Transformer chip.

2. The first extension portion is formed in an annular shape, and the distance from the tip to the inner circumferential end of the first extension portion is 5 μm or less over the entire circumference. The transformer chip according to claim 1 .

3. The first pad covers the entire inner region. The transformer chip according to claim 1 or 2.

4. The first coil is It includes a spiral coil wiring through which a current flows, The inner peripheral end of the first coil is the inner peripheral end of the coil wiring. The transformer chip according to claim 1 or 2.

5. The first coil is A spiral coil wiring through which current flows, an inner dummy wiring provided inside the coil wiring and configured so that the current does not flow; Including, The inner peripheral end of the first coil is the inner peripheral end of the inner dummy wiring. The transformer chip according to claim 1 or 2.

6. the inner dummy wiring is formed in an open ring shape having a slit, The transformer chip according to claim 5 .

7. the density of the inner dummy wiring is equal to the density of the coil wiring; The transformer chip according to claim 5 .

8. a second pad provided separately from the first pad and electrically connected to the first coil; The second pad is disposed outside the first coil and adjacent to the first pad, and includes a second extension portion that extends toward the first coil beyond a position 5 μm away from an outer peripheral end of the first coil when viewed in the thickness direction. The transformer chip according to claim 4 .

9. the first coil includes outer dummy wiring that is arranged outside the coil wiring when viewed from the thickness direction and is configured so that the current does not flow; the second pad is disposed in an outer region surrounded by the coil wiring and the outer dummy wiring, the second extension portion extends from a position 5 μm or more away from wiring portions of the coil wiring and the outer dummy wiring that define the outer region toward both the coil wiring and the outer dummy wiring; The transformer chip according to claim 8.

10. the second extension portion is formed in a ring shape, and the distance from a tip of the second extension portion to an end of the coil wiring and the outer dummy wiring is 5 μm or less over the entire circumference; The transformer chip according to claim 9.

11. The second pad covers the entire outer region. The transformer chip according to claim 9.

12. When viewed from the thickness direction, the second pad is arranged next to the first pad in the first direction, The second pad has a rectangular shape that is long in a second direction perpendicular to the first direction when viewed from the thickness direction. The transformer chip according to claim 8.

13. the inner region has an elliptical shape that is long in the second direction, and the first pad has an elliptical shape that is long in the second direction corresponding to the inner region. The transformer chip according to claim 12.

14. the inner region has an elliptical shape that is long in the second direction, and the first pad has a rectangular shape that is long in the second direction corresponding to the inner region. The transformer chip according to claim 12.

15. The first pad is a base wiring provided at the same position as the first coil in the thickness direction; a cap wiring in contact with an upper surface of the base wiring; It has the cap wiring protrudes beyond the base wiring, and the cap wiring includes the first extension portion; The transformer chip according to claim 1 .

16. The first pad is a base wiring provided at the same position as the first coil in the thickness direction; a cap wiring in contact with an upper surface of the base wiring; It has the base wiring protrudes beyond the cap wiring, and the base wiring includes the first extension portion; The transformer chip according to claim 1 .

17. The first pad is a base wiring provided at the same position as the first coil in the thickness direction; a cap wiring in contact with an upper surface of the base wiring; It has the cap wiring and the base wiring constitute the first extending portion; The transformer chip according to claim 1 .

18. The second coil is formed in a spiral shape overlapping the first coil in the thickness direction. The transformer chip according to claim 1 .