Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor which has an improved bonding force between an internal electrode and a conductive component of an external electrode, and which is capable of suppressing ESR to a low level.　A multilayer ceramic capacitor according to the present invention is provided with: a multilayer body which comprises a plurality of stacked dielectric layers, and which has a first main surface and a second main surface opposite to each other in a height direction that is the stacking direction of the dielectric layers, a first side surface and a second side surface opposite to each other in a width direction that is perpendicular to the height direction, a first end surface and a second end surface opposite to each other in a length direction that is perpendicular to the height direction and the width direction, first internal electrode layers that are stacked alternately with the plurality of dielectric layers and are exposed in the first end surface, and second internal electrode layers that are stacked alternately with the plurality of dielectric layers and are exposed in the second end surface; a first external electrode which is provided on the first end surface; and a second external electrode which is provided on the second end surface. Each of the first end surface and the second end surface is curved from the first main surface to the second main surface, and the radius of curvature of each of the first end surface and the second end surface is 5 / 2 or less of the thickness in the height direction of the multilayer body in a central part thereof in the length direction.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] In recent years, as electronic devices incorporating multilayer ceramic capacitors become smaller, the dimensions of electronic components have also become smaller.

[0003] Furthermore, when a device equipped with a multilayer ceramic capacitor, such as a smartphone, is dropped from a certain height, the external electrodes of the multilayer ceramic capacitor can peel off from the multilayer chip due to the bending transmitted from the substrate.

[0004] Therefore, Patent Document 1 and the like disclose a technique in which a glass component layer is provided between the laminated chip and the external electrode to increase the bonding strength between the laminated chip and the external electrode.

[0005] Japanese Patent Application Laid-Open No. 2018-182107

[0006] However, when a glass component layer is provided between the laminated chip and the external electrodes as in Patent Document 1, the internal electrodes are covered with the glass component, which may increase the ESR.

[0007] SUMMARY OF THE INVENTION Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor that can improve the adhesive strength between the conductive components of the external electrodes and the internal electrodes and can keep the ESR low.

[0008] a first end face and a second end face that face each other in a longitudinal direction that is perpendicular to the width direction; first internal electrode layers that are alternately stacked with the dielectric layers and exposed at the first end face; and second internal electrode layers that are alternately stacked with the dielectric layers and exposed at the second end face; and a first external electrode provided on the first end face and a second external electrode provided on the second end face, wherein each of the first end face and the second end face is curved from the first main face to the second main face, and the radius of curvature of each of the first end face and the second end face is 5 / 2 or less of the thickness of the laminate in a height direction at a central portion in the longitudinal direction of the laminate.

[0009] According to the present invention, by curving the end faces, etc. of the dielectric layers, the exposed area of ​​the internal electrodes at the end faces, etc. is increased, thereby improving the adhesive strength between the conductive components of the external electrodes and the internal electrodes and reducing the ESR, thereby providing a multilayer ceramic capacitor with high moisture resistance and reliability.

[0010] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0011] 1 is an external perspective view showing a multilayer ceramic capacitor as an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. 2 is a front view showing a multilayer ceramic capacitor as an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. 3 is a left side view showing a multilayer ceramic capacitor as an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. 5 is a cross-sectional view taken along line V-V in FIG. 1. 6 is a cross-sectional schematic view illustrating a structure around an end face of a laminate of a multilayer ceramic capacitor as an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. 7 is an external perspective view showing a multilayer ceramic capacitor as an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7. 9 is a cross-sectional view taken along line IX-IX in FIG. 7. 10 is a cross-sectional view taken along line X-X in FIG. 7. 11 is an exploded perspective view of the laminate shown in FIG. 12. 12 is a cross-sectional schematic view taken along line XIIa-XIIa in FIG. 13, illustrating a structure of a multilayer ceramic capacitor as an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. 11 is a cross-sectional view taken along line XIIb-XIIb in FIG. 11 , illustrating the structure of a multilayer ceramic capacitor that is an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. 12 is a cross-sectional view taken along line XIIIc-XIIIc in FIG. 11 , illustrating the structure of a multilayer ceramic capacitor that is an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. 13 is a cross-sectional view taken along line XIId-XIId in FIG. 11 , illustrating the structure of a multilayer ceramic capacitor that is an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. 14 is a cross-sectional view taken along line XIII-XIII in FIG. 11 , illustrating the structure of a multilayer ceramic capacitor that is an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. 15 is a cross-sectional view showing a modification of the laminate shown in FIG. 7 .(a) is a cross-sectional view schematically illustrating the structure of external electrodes of a multilayer ceramic capacitor that is an example of a multilayer ceramic capacitor according to a modified example of a second embodiment of the present invention, and (b) is a cross-sectional view schematically illustrating the structure of external electrodes different from that of the multilayer ceramic capacitor of (a). (a) is a cross-sectional view schematically illustrating the structure of external electrodes of a multilayer ceramic capacitor that is an example of a multilayer ceramic capacitor according to another modified example of the second embodiment of the present invention, and (b) is a cross-sectional view schematically illustrating the structure of external electrodes different from that of the multilayer ceramic capacitor of (a). (a) is a cross-sectional view schematically illustrating the structure of external electrodes of a multilayer ceramic capacitor that is an example of a multilayer ceramic capacitor according to another modified example of the second embodiment of the present invention, and (b) is a cross-sectional view schematically illustrating the structure of external electrodes different from that of the multilayer ceramic capacitor of (a).

[0012] A. First Embodiment 1. Multilayer Ceramic Capacitor A multilayer ceramic capacitor 10 will be described as an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 1 is an external perspective view showing a multilayer ceramic capacitor as an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 2 is a front view showing a multilayer ceramic capacitor as an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 3 is a top view showing a multilayer ceramic capacitor as an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 4 is a left side view showing a multilayer ceramic capacitor as an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1. FIG. 6 is a cross-sectional schematic view illustrating the structure around an end face of a laminate of a multilayer ceramic capacitor as an example of a multilayer ceramic capacitor according to the first embodiment of the present invention.

[0013] The multilayer ceramic capacitor 10 has a laminate 12 and external electrodes 24. The configuration of each will be described below in the order of the laminate 12 and the external electrodes 24.

[0014] (Laminate) The laminate 12 includes a plurality of stacked dielectric layers 14 and a plurality of internal electrode layers 16. The laminate 12 further includes a first main surface 12a and a second main surface 12b that face in a height direction x, which is the stacking direction of the plurality of dielectric layers 14, a first side surface 12c and a second side surface 12d that face in a width direction y that is perpendicular to the height direction x, and a first end surface 12e and a second end surface 12f that face in a length direction z that is perpendicular to the height direction x and the width direction y. Note that a corner refers to a portion where three adjacent surfaces of the laminate 12 intersect, and a ridge refers to a portion where two adjacent surfaces of the laminate 12 intersect. Furthermore, unevenness or the like may be formed on some or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0015] As shown in Figures 4 and 5, the laminate 12 has, in the height direction x connecting the first main surface 12a and the second main surface 12b, an effective layer portion 15a in which a plurality of internal electrode layers 16 face each other, a first outer layer portion 15b1 formed from a plurality of dielectric layers 14 located between the first main surface 12a and the internal electrode layer 16 located closest to the first main surface 12a, and a second outer layer portion 15b2 formed from a plurality of dielectric layers 14 located between the second main surface 12b and the internal electrode layer 16 located closest to the second main surface 12b.

[0016] The first outer layer portion 15b1 is located on the first main surface 12a side of the laminate 12, and is an assembly of a plurality of dielectric layers 14 located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a.

[0017] The second outer layer portion 15b2 is located on the second main surface 12b side of the laminate 12, and is an assembly of a plurality of dielectric layers 14 located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b.

[0018] The area sandwiched between the first outer layer portion 15b1 and the second outer layer portion 15b2 is the effective layer portion 15a.

[0019] The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 10 to 2000, including the first outer layer portion 15b1 and the second outer layer portion 15b2. The thickness of the dielectric layers 14 is preferably 10 μm or less.

[0020] The dielectric layer 14 may be formed from, for example, a dielectric material. Examples of the dielectric material include dielectric ceramics composed mainly of BaTiO3, CaTiO3, SrTiO3, CaZnO3, etc. Sub-components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may also be added to these main components.

[0021] The dielectric layer 14 may have a plurality of crystal grains containing a perovskite-type compound having a basic structure of BaTiO3.

[0022] The thinner the dielectric layer 14, the greater the capacitance of the capacitor, so the crystal grain size is preferably 1 μm or less. The size of the crystal grains is appropriately designed depending on the thickness of the dielectric layer 14.

[0023] In particular, the thickness of the first outer layer portion 15b1 is preferably 1 μm or more and 15 μm or less, and the thickness of the second outer layer portion 15b2 is preferably 1 μm or more and 15 μm or less.

[0024] The thickness of the first outer layer portion 15b1 is defined by measuring the distance between the first main surface 12a and either the first internal electrode layer 16a or the second internal electrode layer 16b of the internal electrode layer 16 closest to the first main surface 12a.

[0025] The thickness of the second outer layer portion 15b2 is defined by measuring the distance between the second main surface 12b and either the first internal electrode layer 16a or the second internal electrode layer 16b of the internal electrode layer 16 closest to the second main surface 12b.

[0026] The dimensions of the laminate 12 in the height direction x, width direction y, and length direction z are not particularly limited.

[0027] The first end face 12e of the laminate 12 is preferably curved from the first main surface 12a to the second main surface 12b. The second end face 12f of the laminate 12 is preferably curved from the first main surface 12a to the second main surface 12b. This increases the exposed area of ​​the internal electrode layers 16 on the first end face 12e and the second end face 12f, thereby increasing the adhesive strength between the conductive components of the external electrodes 24 and the laminate 12. Furthermore, because the exposed area of ​​the conductive components of the external electrodes 24 is increased, an increase in ESR is suppressed.

[0028] The radius of curvature of the curved first end face 12e is preferably 5 / 2 or less of the thickness dimension in the height direction x of the laminate 12 at the center in the length direction z of the laminate 12.

[0029] The radius of curvature of the curved second end face 12f is preferably 5 / 2 or less of the thickness dimension in the height direction x of the laminate 12 at the center in the length direction z of the laminate 12.

[0030] If the radius of curvature is 5 / 2 or more, the exposed area of ​​the internal electrode layers 16 decreases, which reduces the bonding area between the conductive components in the external electrodes 24 and the internal electrode layers 16, thereby reducing the bonding strength between the external electrodes 24 and the laminate 12. In addition, it becomes difficult to sufficiently reduce the ESR.

[0031] The curvature radii of the first end face 12e and the second end face 12f of the laminate 12 can be measured by the following method.

[0032] First, the cross section of the multilayer ceramic capacitor 10 is exposed. Specifically, polishing is performed until the cross section reaches a position of ½ W of the multilayer ceramic capacitor 10 so as to be approximately parallel to the first side surface 12c or the second side surface 12d. Next, for example, a microscope (VHX-5000: manufactured by Keyence Corporation) is used at a magnification of 1500 times to measure the dimension of the polished cross section of the laminate 12 in the height direction x connecting the first main surface 12a and the second main surface 12b.

[0033] 6 , on the first end face 12 e side, the position O is defined as a position O where the dimension in the longitudinal direction of the first end face 12 e is maximum. The positions are then defined as a position P1 where a perpendicular line V1 (a straight line along the height direction x) passing through an end 18 b1 of a second opposing electrode portion 18 b of a second internal electrode layer 16 b that is not exposed on the first end face 12 e side among the plurality of electrode layers of the internal electrode layer 16 intersects with the surface on the first main surface 12 a side of the laminate 12, and a position P2 where the perpendicular line V1 intersects with the surface on the second main surface 12 b side of the laminate 12.

[0034] Then, the distance D between position P1 and position O is measured along the longitudinal direction z, and position Q1 is defined as the intersection point between a perpendicular line V2 passing through a position shifted from position P1 by a distance d, which is 5% of the distance D, toward the first end face 12e and the surface on the first main surface 12a side of the laminate 12, and position Q2 is defined as the intersection point between a perpendicular line V2 passing through a position shifted from position P2 by a distance d toward the first end face 12e and the surface on the second main surface 12b side of the laminate 12.

[0035] The radius of curvature of the contour portion R of the cross section that starts at each of positions Q1 and Q2 and passes through position O is measured, and this is taken as the radius of curvature of the first end face 12e.

[0036] Although not shown in the drawings, on the second end face 12 f side, this is defined as a position O' where the dimension in the longitudinal direction z of the second end face 12 f is maximum. Then, a position P1' where a perpendicular line passing through an end of the first opposing electrode portion 18 a of the first internal electrode layer 16 a that is not exposed on the second end face 12 f side among the multiple electrode layers of the internal electrode layer 16 intersects with the surface on the first main surface 12 a side of the laminate 12, and a position P2' where the perpendicular line intersects with the surface on the second main surface 12 b side of the laminate 12 are measured.

[0037] Position Q1' is defined as the intersection point between a perpendicular line passing through a position shifted by a distance d', which is 5% of the distance D between position P1' and position O', along the width direction y toward the second end face 12f and the surface on the first main surface 12a side of the laminate 12, and position Q2' is defined as the intersection point between a perpendicular line passing through a position shifted by a distance d' from position P2' toward the second end face 12f and the surface on the second main surface 12b side of the laminate 12.

[0038] The radius of curvature of the contour portion R' of the cross section passing through the position O' is measured from each of the extreme positions Q1' and Q2' as starting points, and this is taken as the radius of curvature of the second end face 12f.

[0039] In addition, for multiple second internal electrode layers 16b, if the positions of the ends of the second opposing electrode portions 18b are not aligned along the longitudinal direction z, positions P1 and P2 are measured based on the position of the end 18b1 of the second internal electrode layer 16b that is closest to the first end face 12e, as indicated by the symbol, and positions Q1 and Q2, which are the starting points for measuring the radius of curvature, are defined.

[0040] The thickness of the laminate 12 in the height direction x is preferably 60 μm or less. When the thickness is 60 μm or less, the above-described effects of the present invention can be obtained.

[0041] Furthermore, the first side surface 12c is preferably curved from the first main surface 12a to the second main surface 12b, and the second side surface 12d is preferably curved from the first main surface 12a to the second main surface 12b, which helps prevent chipping of the laminate 12.

[0042] (Internal Electrode Layers) As shown in Figures 4 and 5, the internal electrode layers 16 include first internal electrode layers 16a and second internal electrode layers 16b. The first internal electrode layers 16a and the second internal electrode layers 16b are alternately stacked with the dielectric layers 14 interposed therebetween.

[0043] The first internal electrode layer 16a is disposed on the surface of the dielectric layer 14. The first internal electrode layer 16a has a first opposing electrode portion 18a that faces the second internal electrode layer 16b, and a first lead electrode portion 20a that is located on one end side of the first internal electrode layer 16a and extends from the first opposing electrode portion 18a to the first end face 12e of the laminate 12. An end of the first lead electrode portion 20a is led out to and exposed at the first end face 12e.

[0044] The shape of the first opposing electrode portion 18a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first opposing electrode portion 18a may be tapered in plan view, with a slope increasing in either direction.

[0045] The shape of the first lead electrode portion 20a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first lead electrode portion 20a may be tapered in plan view, with a slope increasing in either direction.

[0046] The width of the first opposing electrode portion 18a of the first internal electrode layer 16a and the width of the first extraction electrode portion 20a of the first internal electrode layer 16a may be formed to be the same width, or one of them may be formed to be narrower in width.

[0047] The second internal electrode layer 16b is arranged on a surface of a dielectric layer 14 different from the dielectric layer 14 on which the first internal electrode layer 16a is arranged. The second internal electrode layer 16b has a second opposing electrode portion 18b facing the first internal electrode layer 16a, and a second extraction electrode portion 20b located on one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 18b to a second end face 12f of the laminate 12. The second extraction electrode portion 20b has an end portion extended to and exposed at the second end face 12f.

[0048] The shape of the second opposing electrode portion 18b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second opposing electrode portion 18b may be tapered in plan view, with a slope increasing in either direction.

[0049] The shape of the second extraction electrode portion 20b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second extraction electrode portion 20b may be tapered in plan view, with a slope increasing in either direction.

[0050] The width of the second opposing electrode portion 18b of the second internal electrode layer 16b and the width of the second extraction electrode portion 20b of the second internal electrode layer 16b may be formed to be the same width, or one of them may be formed to be narrower in width.

[0051] The first lead electrode portion 20 a of the first internal electrode layer 16 a may be curved toward the center of the first end face 12 e of the laminate 12 .

[0052] The second extraction electrode portion 20 b of the second internal electrode layer 16 b may be curved toward the center of the second end face 12 f of the laminate 12 .

[0053] Of the first extraction electrode portions 20a of the first internal electrode layer 16a extracted to the first end face 12e, the distance between the one located closest to the first main surface 12a and the one located closest to the second main surface 12b may be shorter than the distance between the first opposing electrode portions 18a of the first internal electrode layer 16a located closest to the first main surface 12a and the one located closest to the second main surface 12b.

[0054] Of the second extraction electrode portions 20b of the second internal electrode layer 16b extracted to the second end face 12f, the distance between the one located closest to the first main surface 12a and the one located closest to the second main surface 12b may be shorter than the distance between the second opposing electrode portions 18b of the second internal electrode layer 16b located closest to the first main surface 12a and the one located closest to the second main surface 12b.

[0055] Furthermore, as shown in FIG. 4, the laminate 12 includes ends (hereinafter referred to as "L gaps") 22b of the laminate 12 formed between the end of the first internal electrode layer 16a opposite the first extraction electrode portion 20a and the second end face 12f, and between the end of the second internal electrode layer 16b opposite the second extraction electrode portion 20b and the first end face 12e.

[0056] As shown in FIG. 5 , the laminate 12 includes side portions (hereinafter referred to as “W gaps”) 22 a of the laminate 12 formed between one end of the first opposing electrode portion 18 a and the second opposing electrode portion 18 b in the width direction y and the first side surface 12 c, and between the other end of the first opposing electrode portion 18 a and the second opposing electrode portion 18 b in the width direction y and the second side surface 12 d.

[0057] A step layer may be disposed in the L gap 22b.

[0058] The first internal electrode layer 16a or the second internal electrode layer 16b may be arranged so as to cover a portion of the step layer, or the step layer may be arranged so as to cover a portion of the first internal electrode layer 16a or the second internal electrode layer 16b.

[0059] The step layer preferably has a thickness similar to that of the dielectric layer 14 .

[0060] The step layer preferably has the same composition as the dielectric layer 14, but is not limited to this.

[0061] A first dummy electrode layer and a second dummy electrode layer may be disposed in the L gap 22b.

[0062] The first dummy electrode layer and the second dummy electrode layer may be disposed on the first outer layer portion 15b1 and the second outer layer portion 15b2, respectively. In this case, they are preferably disposed on portions corresponding to positions obtained by translating the L gap 22b in the height direction x.

[0063] The first dummy electrode layer preferably has a thickness equal to the sum of the thicknesses of the first internal electrode layers 16 a. In other words, the first dummy electrode layer preferably has a thickness equal to the thickness of the first internal electrode layer 16 a multiplied by the number of first internal electrode layers 16 a.

[0064] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of an appropriate conductive material, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy. In this embodiment, the first opposing electrode portion 18a of the first internal electrode layer 16a and the second opposing electrode portion 18b of the second internal electrode layer 16b face each other via the dielectric layer 14, thereby forming capacitance and exhibiting capacitor characteristics.

[0065] In order to increase the capacitance of the capacitor, it is necessary to increase the area of ​​each of the first internal electrode layers 16 a and the second internal electrode layers 16 b of the internal electrode layers 16, and therefore it is preferable that the LW surface coverage of each of the first internal electrode layers 16 a and the second internal electrode layers 16 b is 90% or more. The LW surface coverage is defined as the ratio of the area inside the edge of the first internal electrode layer 16 a or the second internal electrode layer 16 b when viewed from the LW surface (the plane formed by the length direction z and the width direction y) of the laminate 12 minus the area of ​​the gap.

[0066] The higher the LW surface coverage, the higher the capacitance of the capacitor. However, even if the coverage is low, the dielectric layers 14 are bonded together via gaps, so the bonding strength between the layers is high and delamination is less likely to occur.

[0067] It is preferable that each of the first internal electrode layer 16a and the second internal electrode layer 16b has a uniform thickness, but the thickness of the edge portion in the width direction y may be greater than the thickness of the central portion in the width direction y.

[0068] The thickness of the first internal electrode layer 16a and the second internal electrode layer 16b is preferably, for example, about 0.2 μm or more and 2.0 μm or less.

[0069] The total number of the first internal electrode layers 16a and the second internal electrode layers 16b is preferably 10 or more and 2000 or less.

[0070] (External Electrodes) As shown in FIGS. 1 to 4, external electrodes 24 are disposed on the first end face 12e side and the second end face 12f side of the laminate 12.

[0071] The external electrode 24 includes a base electrode layer 26 and a plating layer 28 formed to cover the base electrode layer 26 .

[0072] The external electrode 24 includes a first external electrode 24a and a second external electrode 24b.

[0073] The first external electrode 24a is disposed only on the surface of the first end face 12e of the laminate 12, a portion of the first main surface 12a, and a portion of the second main surface 12b. In this case, the first external electrode 24a is electrically connected to the first extraction electrode portion 20a of the first internal electrode layer 16a. The first external electrode 24a is not disposed on a portion of the first side surface 12c or a portion of the second side surface 12d, but may extend around to some extent.

[0074] The second external electrode 24b is disposed only on the surface of the second end face 12f of the laminate 12, a portion of the first main surface 12a, and a portion of the second main surface 12b. In this case, the second external electrode 24b is electrically connected to the second extraction electrode portion 20b of the second internal electrode layer 16b. The second external electrode 24b is not disposed on a portion of the first side surface 12c and a portion of the second side surface 12d, but may extend around to some extent.

[0075] The thickness of the first external electrode 24a and the second external electrode 24b is preferably, for example, about 1 μm or more and 30.0 μm or less.

[0076] (Underlying Electrode Layer) The underlying electrode layer 26 includes a first underlying electrode layer 26a and a second underlying electrode layer 26b.

[0077] The first base electrode layer 26a is formed to cover the first end face 12e of the laminate 12, as well as a portion of the first main surface 12a on the first end face 12e side of the laminate 12 and a portion of the second main surface 12b on the first end face 12e side of the laminate 12.

[0078] The second base electrode layer 26b is formed to cover the second end face 12f of the laminate 12, as well as a portion of the first main surface 12a on the second end face 12f side of the laminate 12, and a portion of the second main surface 12b on the second end face 12f side of the laminate 12.

[0079] The base electrode layer 26 formed of a thin film layer includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0080] (In the case of baking layer) The baking layer contains a glass component and a metal component. The glass component of the baking layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baking layer contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baking layer is formed by applying a conductive paste containing a glass component and a metal component to the laminate 12 and baking it.

[0081] The baked layer may be formed by simultaneously firing a laminated chip having an internal electrode layer 16 and a dielectric layer 14 with a conductive paste applied to the laminated chip, or may be formed by firing a laminated chip having an internal electrode layer 16 and a dielectric layer 14 to obtain a laminate and then baking a conductive paste onto the laminate.

[0082] In addition, when a laminated chip having an internal electrode layer 16 and a dielectric layer 14 and a conductive paste applied to the laminated chip are fired simultaneously, it is preferable to form the firing layer by firing a layer to which a dielectric material has been added instead of a glass component.

[0083] The baking layer may be a multi-layer.

[0084] In the case of a baked layer, the thickness of the first base electrode layer 26a located on the first end face 12e at the center in the height direction x is preferably, for example, 0.1 μm to 200 μm, and the thickness of the second base electrode layer 26b located on the second end face 12f at the center in the height direction x is preferably, for example, 0.1 μm to 200 μm.

[0085] Furthermore, when the first base electrode layer 26a as a baked layer is provided on the first main surface 12a and the second main surface 12b, it is preferable that the thickness of the first base electrode layer 26a located on the first main surface 12a and the second main surface 12b at the center in the height direction x is, for example, not less than 0.1 μm and not more than 200 μm.

[0086] When the second base electrode layer 26b as a baked layer is provided on the first main surface 12a and the second main surface 12b, it is preferable that the thickness of the second base electrode layer 26b located on the first main surface 12a and the second main surface 12b at the center in the height direction x is, for example, not less than 0.1 μm and not more than 200 μm.

[0087] (In the case of a conductive resin layer) The base electrode layer 26 as a conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even if the multilayer ceramic capacitor is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the multilayer ceramic capacitor.

[0088] The metal contained in the conductive resin layer can be Ag, Cu, Ni, or an alloy thereof. Alternatively, a metal powder whose surface is coated with Ag can be used. When a metal powder whose surface is coated with Ag is used, it is preferable to use Cu or Ni as the metal powder. Alternatively, Cu that has been subjected to an oxidation prevention treatment can be used.

[0089] The reason for using Ag conductive metal powder as the metal contained in the conductive resin layer is that Ag has the lowest resistivity of all metals, making it suitable as an electrode material, and because Ag is a noble metal, it does not oxidize and has high resistance.The reason for using Ag-coated metal is that it makes it possible to use a cheaper base metal while maintaining the above-mentioned properties of Ag.

[0090] The metal contained in the conductive resin layer is preferably contained in an amount of 35 vol % or more and 75 vol % or less with respect to the volume of the entire conductive resin.

[0091] The average particle size of the metal contained in the conductive resin layer is not particularly limited, and the average particle size of the conductive filler may be, for example, about 0.3 μm or more and 10 μm or less.

[0092] The metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, when the conductive fillers come into contact with each other, a conductive path is formed inside the conductive resin layer.

[0093] The metal contained in the conductive resin layer is not particularly limited, but spherical or flat metal powders can be used, and it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0094] The resin for the conductive resin layer may be any of various known thermosetting resins, such as epoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins, as it has excellent heat resistance, moisture resistance, adhesion, etc.

[0095] The resin contained in the conductive resin layer is preferably contained in an amount of 25 vol % or more and 65 vol % or less with respect to the volume of the entire conductive resin.

[0096] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, and imidazole-based compounds can be used as the curing agent for the epoxy resin.

[0097] The base electrode layer 26 as a conductive resin layer may be a multi-layered layer.

[0098] The conductive resin layer may be disposed on the baked layer so as to cover the baked layer, or may be disposed directly on the laminate.

[0099] In the case of a conductive resin layer, the thickness of the first base electrode layer 26a located on the first end face 12e at the center in the height direction x is preferably, for example, about 10 μm to 200 μm, and the thickness of the second base electrode layer 26b located on the second end face 12f at the center in the height direction x is preferably, for example, about 10 μm to 200 μm.

[0100] Furthermore, when the first base electrode layer 26a as a conductive resin layer is provided on the first main surface 12a and the second main surface 12b, it is preferable that the thickness of the first base electrode layer 26a located on the first main surface 12a and the second main surface 12b at the center in the height direction x is, for example, 5 μm or more and 50 μm or less.

[0101] When the second base electrode layer 26b as a conductive resin layer is provided on the first main surface 12a and the second main surface 12b, it is preferable that the thickness of the second base electrode layer 26b located on the first main surface 12a and the second main surface 12b at the center in the height direction x is, for example, 5 μm or more and 50 μm or less.

[0102] (In the case of a thin film layer) The base electrode layer 26 as a thin film layer is preferably formed by a thin film formation method such as a sputtering method or a vapor deposition method. The thin film layer is preferably a layer of 1 μm or less in thickness in which metal particles are deposited.

[0103] (Plating Layer) The plating layer 28 includes a first plating layer 28a and a second plating layer 28b.

[0104] The first plating layer 28a is disposed so as to cover the first base electrode layer 26a.

[0105] The second plating layer 28b is disposed so as to cover the second base electrode layer 26b.

[0106] The plating layer 28 is formed of multiple layers.

[0107] The plating layer 28 preferably contains at least one selected from, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0108] The plating layer 28 may be formed of multiple layers. In the present embodiment, the plating layer 28 has a two-layer structure of Ni plating and Sn plating, and includes a lower plating layer 30 which is a Ni plating layer that covers the base electrode layer 26, and an upper plating layer 32 which is a Sn plating layer that is disposed so as to cover the lower plating layer 30.

[0109] The lower plating layer 30 includes a first lower plating layer 30a and a second lower plating layer 30b.

[0110] The first lower-layer plating layer 30a is disposed so as to cover the surface of the first base electrode layer 26a. Specifically, the first lower-layer plating layer 30a is disposed on the first end face 12e of the surface of the first base electrode layer 26a, and is provided so as to extend to the first main surface 12a and the second main surface 12b of the surface of the first base electrode layer 26a.

[0111] The second lower-layer plating layer 30b is disposed so as to cover the surface of the second base electrode layer 26b. Specifically, the second lower-layer plating layer 30b is disposed on the first end face 12e of the surface of the second base electrode layer 26b, and is provided so as to extend to the first main surface 12a and the second main surface 12b of the surface of the second base electrode layer 26b.

[0112] The upper plating layer 32 has a first upper plating layer 32a and a second upper plating layer 32b.

[0113] The first upper plating layer 32a is disposed so as to cover the first lower plating layer 30a. Specifically, the first upper plating layer 32a is disposed on the first end face 12e of the surface of the first lower plating layer 30a, and is provided so as to extend to the first main surface 12a and the second main surface 12b of the surface of the first lower plating layer 30a.

[0114] The second upper plating layer 32b is disposed so as to cover the second lower plating layer 30b. Specifically, the second upper plating layer 32b is disposed on the second end face 12f of the surface of the second lower plating layer 30b, and is provided so as to extend to the first and second main surfaces 12a and 12b of the surface of the second lower plating layer 30b.

[0115] When the plating layer 28 has a three-layer structure, it is preferable that Sn plating, Ni plating, and Sn plating are laminated in this order.

[0116] The thickness of each plating layer is preferably 1 μm or more and 15 μm or less.

[0117] (In the case of direct plating layer) The plating layer may be a direct plating layer formed directly on the surface of the laminate 12. That is, the multilayer ceramic capacitor 10 may have a structure including a direct plating layer electrically connected to the first internal electrode layer 16a or the second internal electrode layer 16b. In such a case, the direct plating layer may be formed after a catalyst is disposed on the surface of the laminate 12 as a pretreatment.

[0118] The direct plating layer preferably contains, for example, at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, Zn, or the like, or an alloy containing such a metal.

[0119] For example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, it is preferable that the direct plating layer be formed using Cu, which has good bonding properties with Ni.

[0120] The thickness of each direct plating layer is preferably 1 μm or more and 15 μm or less.

[0121] It is preferable that the plating layers do not contain glass, and the metal content per unit volume of the plating layers is preferably 99% by volume or more.

[0122] The dimension in the length direction z of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 24a, and the second external electrode 24b is defined as dimension L, the dimension in the height direction x of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 24a, and the second external electrode 24b is defined as dimension T, and the dimension in the width direction y of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 24a, and the second external electrode 24b is defined as dimension W.

[0123] The dimensions of the multilayer ceramic capacitor 10 are preferably such that the L dimension in the length direction z is 0.2 mm to 6.5 mm, the T dimension in the height direction x is 0.03 mm to 6.5 mm, and the W dimension in the width direction y is 0.1 mm to 5.5 mm. Furthermore, the ESL can be reduced by reversing the L dimension and the W dimension to shorten the current path.

[0124] 1, each of the first end face 12e and the second end face 12f of the laminate 12 is curved from the first main surface 12a to the second main surface 12b, with the radius of curvature being 5 / 2 or less of the thickness dimension in the height direction x of the laminate 12 at the center in the length direction z of the laminate 12. This increases the exposed area of ​​the internal electrode layers 16 on the first end face 12e and the second end face 12f, thereby increasing the adhesive strength between the conductive components of the external electrodes 24 and the laminate 12. Furthermore, because the exposed area of ​​the conductive components of the external electrodes 24 is increased, the ESR can be kept low.

[0125] Furthermore, in the multilayer ceramic capacitor 10 shown in FIG. 1, if each of the first side surface 12c and the second side surface 12d of the laminate 12 is curved from the first main surface 12a to the second main surface 12b, chipping and cracking of the laminate 12 can be prevented.

[0126] 2. Method for Manufacturing the Multilayer Ceramic Capacitor A method for manufacturing the multilayer ceramic capacitor, which is an example of the multilayer ceramic capacitor according to the first embodiment, will now be described.

[0127] First, a dielectric sheet and a conductive paste for the internal electrodes are prepared. The dielectric sheet and the conductive paste for the internal electrode layers contain a binder (e.g., a known organic binder) and a solvent (e.g., a known organic binder).

[0128] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, screen printing or gravure printing, to form an internal electrode pattern. Specifically, a conductive paste layer is formed by applying a paste made of a conductive material to the dielectric sheet by a method such as the printing method described above. The conductive paste is, for example, a paste made of a metal powder to which an organic binder and an organic solvent have been added. Regarding the dielectric sheets, outer layer dielectric sheets on which no internal electrode patterns are printed are also produced.

[0129] A laminated sheet is produced using the dielectric sheets on which these internal electrode patterns are formed. That is, a predetermined number of dielectric sheets for outer layers on which no internal electrode pattern is formed are laminated, and dielectric sheets on which internal electrode patterns corresponding to the first internal electrode layer 16a and dielectric sheets on which internal electrode patterns corresponding to the second internal electrode layer 16b are formed are alternately laminated thereon, and a predetermined number of dielectric sheets for outer layers on which no internal electrode pattern is formed are further laminated thereon to produce a laminated sheet.

[0130] Furthermore, the laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0131] Next, the laminated block is cut to a predetermined size to cut out laminated chips.

[0132] Next, a laminated chip having a desired shape is formed by barrel polishing. Specifically, the diameter of the barrel polishing media is preferably in the range of 0.2 mm to 0.7 mm, the amount of media is preferably in the range of 200 cc to 700 cc, and the media is rotated not only in one direction but also in multiple directions. In this way, barrel polishing is performed until the entire end face of the laminated chip is rounded as desired.

[0133] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the materials of the dielectric layers and internal electrode layers, but is preferably 900° C. or higher and 1400° C. or lower.

[0134] Subsequently, a base electrode layer 26 is formed on the first end face 12e and the second end face 12f of the laminate 12, as well as on a portion of the first principal surface 12a and a portion of the second principal surface 12b.

[0135] (When the base electrode layer is a baked layer) A conductive paste that will become the base electrode layer is applied to the first end face 12e and the second end face 12f of the laminate 12, as well as a portion of the first main surface 12a and a portion of the second main surface 12b of the laminate 12, to form the first base electrode layer 26a and the second base electrode layer 26b of the base electrode layer 26.

[0136] The baking layer is formed by applying a conductive paste containing a glass component and a metal by, for example, dipping, followed by baking. The baking temperature is preferably 700° C. or higher and 900° C. or lower. When the laminated chip having the internal electrode layer 16 and the dielectric layer 14 and the conductive paste applied to the laminated chip are simultaneously baked, the baking layer is preferably formed by baking a material to which a dielectric material is added instead of the glass component.

[0137] If necessary, the surface of the baked layer may be plated.

[0138] (When the base electrode layer is a conductive resin layer) When the base electrode layer is formed of a conductive resin layer, the method is as follows: The conductive resin layer may be formed on the surface of the baked layer, or the conductive resin layer may be formed alone directly on the laminate without forming a baked layer.

[0139] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baking layer or the laminate, and then performing a heat treatment at a temperature of 250°C to 550°C to thermally cure the resin and form the conductive resin layer. The heat treatment is preferably performed in an N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable to keep the oxygen concentration below 100 ppm.

[0140] (When the base electrode layer is a thin film layer) When the base electrode layer is formed as a thin film layer, a thin film formation method such as a sputtering method or a vapor deposition method is used. The base electrode layer 26 formed as a thin film layer is a layer of 1 μm or less in thickness in which metal particles are deposited.

[0141] (Direct Plating Layer) A plating layer may be provided directly on the exposed portions of the internal electrode layers 16 of the laminate 12. In this case, the following method is used.

[0142] The first end face 12e and the second end face 12f of the laminate 12 of the laminate, as well as a portion of the first main surface 12a and a portion of the second main surface 12b, are plated to form a plating film directly on the exposed portions of the internal electrode layers 16. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating requires pretreatment using a catalyst or the like to improve the plating deposition rate, which has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferred. Barrel plating is preferably used as the plating method. If necessary, an upper-layer plated electrode may be formed on the surface of the lower-layer plated electrode in the same manner.

[0143] Thereafter, a plating layer 28 is formed on the surface of the base electrode layer 26. In this embodiment, a lower plating layer 30, which is a Ni plating layer, and an upper plating layer 32, which is a Sn plating layer disposed so as to cover the lower plating layer 30, are formed on the base electrode layer 26 as a baked layer. The Ni plating layer and the Sn plating layer are formed in this order by, for example, barrel plating.

[0144] In this manner, the multilayer ceramic capacitor 10 shown in FIG. 1 can be manufactured.

[0145] According to the method for manufacturing a multilayer ceramic capacitor according to the present embodiment described above, it is possible to manufacture a high-quality multilayer ceramic capacitor according to the present invention that has high humidity resistance and can improve the adhesive strength between the conductive components of the external electrodes and the internal electrodes and can keep the ESR low.

[0146] B. Second Embodiment 1. Multilayer Ceramic Capacitor Next, a multilayer ceramic capacitor according to a second embodiment of the present invention will be described. FIG. 7 is an external perspective view showing a multilayer ceramic capacitor as an example of the multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 7. FIG. 10 is a cross-sectional view taken along line X-X in FIG. 7. FIG. 11 is an exploded perspective view of the laminate shown in FIG. 7. FIG. 12a is a cross-sectional schematic view taken along line XIIa-XIIa in FIG. 10, and is a cross-sectional schematic view for explaining the structure of a multilayer ceramic capacitor as an example of the multilayer ceramic capacitor according to the second embodiment of the present invention.

[0147] Fig. 12b is a cross-sectional view taken along line XIIb-XIIb in Fig. 10, illustrating the structure of a multilayer ceramic capacitor that is an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. Fig. 12c is a cross-sectional view taken along line XIIc-XIIc in Fig. 10, illustrating the structure of a multilayer ceramic capacitor that is an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. Fig. 12d is a cross-sectional view taken along line XIId-XIId in Fig. 10, illustrating the structure of an external electrode of a multilayer ceramic capacitor that is an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. Fig. 13 is a cross-sectional view taken along line XIII-XIII in Fig. 10, illustrating the structure of a multilayer ceramic capacitor that is an example of a multilayer ceramic capacitor according to the second embodiment of the present invention.

[0148] The multilayer ceramic capacitor 510 includes a laminate 512 and external electrodes 524 and 525 .

[0149] (Laminate) The laminate 512 includes a plurality of dielectric layers 514 and a plurality of internal electrode layers 516. The laminate 512 has a first main surface 512a and a second main surface 512b that face each other in a height direction x, a first side surface 512c and a second side surface 512d that face each other in a width direction y that is perpendicular to the height direction x, and a third side surface 512e and a fourth side surface 512f that face each other in a length direction z that is perpendicular to the height direction x and the width direction y. The first main surface 512a and the second main surface 512b extend along the width direction y and the length direction z, respectively. The first side surface 512c and the second side surface 512d extend along the height direction x and the width direction z, respectively. The third side surface 512e and the fourth side surface 512f extend along the height direction x and the width direction y, respectively. Therefore, the height direction x is the direction connecting the first main surface 512a and the second main surface 512b, the width direction y is the direction connecting the first side surface 512c and the second side surface 512d, and the length direction z is the direction connecting the third side surface 512e and the fourth side surface 512f.

[0150] The laminate 512 has a rectangular parallelepiped shape. Here, a corner is a portion where three faces of the laminate 512 intersect, and a ridge is a portion where two faces of the laminate 512 intersect.

[0151] As shown in Figures 8 and 9, the laminate 512 has, in the height direction x connecting the first main surface 512a and the second main surface 512b, an effective layer portion 515a in which multiple internal electrode layers 516 face each other, a first outer layer portion 515b1 formed from multiple dielectric layers 514 located between the internal electrode layer 516 located closest to the first main surface 512a and the first main surface 512a, and a second outer layer portion 515b2 formed from multiple dielectric layers 514 located between the internal electrode layer 516 located closest to the second main surface 512b and the second main surface 512b.

[0152] The first outer layer portion 515b1 is located on the first main surface 512a side of the laminate 512, and is an assembly of multiple dielectric layers 514 located between the first main surface 512a and the internal electrode layer 516 closest to the first main surface 512a.

[0153] The second outer layer portion 515b2 is located on the second main surface 512b side of the laminate 512, and is an assembly of multiple dielectric layers 514 located between the second main surface 512b and the internal electrode layer 516 closest to the second main surface 512b.

[0154] The region sandwiched between the first outer layer portion 515b1 and the second outer layer portion 515b2 is the effective layer portion 515a. The region sandwiched between the first outer layer portion 515b1 and the second outer layer portion 515b2 is the effective layer portion 515a. The number of dielectric layers 514 to be stacked is not particularly limited, but is preferably 50 or less, including the first outer layer portion 515b1 and the second outer layer portion 515b2. The thickness of the dielectric layer 514 is preferably 0.2 μm or more and 10.0 μm or less.

[0155] The region sandwiched between the first outer layer portion 515b1 and the second outer layer portion 515b2 is the effective layer portion 515a, that is, the effective layer portion 515a is the region where the internal electrode layers 516 are stacked.

[0156] The dielectric layer 514 can be formed of, for example, a dielectric material. Examples of the dielectric material include dielectric ceramics whose main components are BaTiO3, CaTiO3, SrTiO3, and CaZnO3. Alternatively, these main components may be supplemented with a minor component, such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound, in a smaller amount than the main component.

[0157] Furthermore, the dielectric layer 514 may have a plurality of crystal grains containing a perovskite compound having a basic structure of BaTiO. Since the thinner the dielectric layer 514, the greater the capacitance as a capacitor, it is preferable that the crystal grain size be 1 μm or less.

[0158] The dielectric layer 514 for the effective layer portion 515a is made of dielectric ceramic particles having a perovskite structure, the main component of which is a perovskite compound containing, for example, Ba and Ti.

[0159] Furthermore, at least one of Si, Mg, Ba, and Mn may be added as an additive to these main components, which exists between ceramic particles.

[0160] The dielectric layers 514 for the first outer layer portion 515b1 and the second outer layer portion 515b2 are formed from the same dielectric ceramic material as the dielectric layer 514 for the effective layer portion 515a. Note that the dielectric layers 514 for the first outer layer portion 515b1 and the second outer layer portion 515b2 may be formed from a material different from that of the dielectric layer 514 for the effective layer portion 515a.

[0161] Furthermore, when the dielectric layers 514 for the first outer layer portion 515b1 and the second outer layer portion 515b2 each have a multi-layer structure, it is preferable that the segregated portions of Si in the other dielectric layers 514 are larger than the segregated portions of Si in the dielectric layer 514 located closest to the first internal electrode layer 16a and the second internal electrode layer 16b. This can improve the flexural strength of the multilayer ceramic capacitor from the height direction x side.

[0162] Each of the dielectric layers 514 for the first outer layer portion 515b1 and the second outer layer portion 515b2 may be a multi-layer structure or a single layer structure.

[0163] Each of the first side surface 512c, the second side surface 512d, the third side surface 512e, and the fourth side surface 512f is curved from the first main surface 512a to the second main surface 512b.

[0164] The first main surface 512a is preferably curved across each of the first side surface 512c, the second side surface 512d, the third side surface 512e, and the fourth side surface 512f, and the second main surface 512b is preferably curved across each of the first side surface 512c, the second side surface 512d, the third side surface 512e, and the fourth side surface 512f.

[0165] Each of the first side surface 512c, the second side surface 512d, the third side surface 512e, and the fourth side surface 512f is curved from the first main surface 12a to the second main surface 12b, and it is preferable that the radius of curvature is 5 / 2 or less of the thickness dimension in the height direction x of the laminate 12 at the center in the longitudinal direction z of the laminate 12.

[0166] A silane coupling agent layer may be provided on the surface of the laminate 512. A silane coupling agent is preferably provided on at least one of the first main surface 512a and the second main surface 512b. More preferably, the silane coupling agent may be provided on both the first main surface 512a and the second main surface 512b. The silane coupling agent may also be provided on the first side surface 512c and the second side surface 512d. In this case, the silane coupling agent is preferably provided on a portion or the entirety of the first side surface 512c and the second side surface 512d where the first external electrode 524a and the second external electrode 524b are not provided.

[0167] The provision of the silane coupling agent layer can prevent the intrusion of moisture, flux, and the like from the outside into the laminate 512. Therefore, when mounting the flux, corrosion due to organic acids contained in the flux can be suppressed, and therefore a decrease in moisture resistance reliability can be suppressed.

[0168] The silane coupling agent layer is preferably made of a fluorine-based silane coupling agent or a carbon-based silane coupling agent.

[0169] The fluorine-based silane coupling agent contained in the silane coupling agent layer is CF3-(CF2) n1 A silane coupling agent represented by —R—Si(O—R′)3 (where n1 is an integer of 0 or more, R is a substituent containing Si or O or an alkylene group, and R′ is an alkyl group) is preferred. For example, n1 may be an integer of 0 or more and 7 or less. R′ may be a methyl group or an ethyl group.

[0170] The silane coupling agent contains at least one alkoxy group, which is a reactive group, and one or more perfluoroalkyl groups.

[0171] Examples of fluorine-based silane coupling agents include CF3(CF2)5(CH2)2Si(OCH3)3, CF3(CF2)3(CH2)2Si(OCH3)3, CF3(CF2)3(CH2)2Si(OC2H5)3, CF3(CF2)7(CH2)2Si(OCH3)3, and CF3CH2O(CH2). 15 Si(OCH3)3, CF3(CH2)2Si(CH3)2(CH2) 15 Si(OCH3)3, CF3(CF2)3(CH2)2Si(CH3)2(CH2)9Si(OCH3)3, CF3COO(CH2) 15 Si(OCH3)3, CF3(CF2)5(CH2)2Si(OC2H5)3, CF3(CF2)7(CH2)2Si(CH3)2(CH2)9Si(OC2H5)3, CF3(CF2)7(CH2)2Si(CH3)2(CH2)6Si(OC2H5)3, CF3(CF2)7(CH2)2Si(OC2H5)3, CF3CH2O(CH2) 15 Si(OC2H5)3, CF3COO(CH2) 15 Si(OC2H5)3, CF3(CF2)4CONH(CH2)3Si(OCH3)3, CF3(CF2)7CONH(CH2)3Si(OCH3)3, CF3(CF2)5CONH(CH2)3Si(OC2H5)3, or CF3(CF2)7CONH(CH2)3Si(OC2H5)3 can be used.

[0172] The carbon-based silane coupling agent contained in the silane coupling agent layer is (RO)3Si-(CH2) n2A silane coupling agent represented by —CH3 (where n2 is an integer of 0 to 17, and R is a methyl group or an ethyl group) is preferred. Examples of carbon-based silane coupling agents that can be used include Shin-Etsu Chemical's KBM-3103C (decyltrimethoxysilane), KBM-13 (methyltrimethoxysilane), KBE-13 (methyltriethoxysilane), KBM-3033 (n-propyltrimethoxysilane), KBE-3033 (n-propyltriethoxysilane), KBM-3063 (hexyltrimethoxysilane), and KBE-3063 (hexyltriethoxysilane), and Tokyo Chemical Industry Co., Ltd. (TCI)'s octadecyltrimethoxysilane.

[0173] As carbon-based silane coupling agents other than those mentioned above, the following silane coupling agents can also be used: Shin-Etsu Chemical: KBM-103 (phenylmethoxysilane), KBM-3066 (1,6-bis(trimethoxysilyl)hexane), KBM-9659 (tris-(trimethoxysilylpropyl)isocyanurate)

[0174] 8 to 11, the internal electrode layers 516 include a plurality of first internal electrode layers 516a and a plurality of second internal electrode layers 516b. The first internal electrode layers 516a and the second internal electrode layers 516b are alternately stacked in a direction connecting the first main surface 512a and the second main surface 512b with the dielectric layer 514 interposed therebetween.

[0175] The first internal electrode layer 516a is disposed on the surface of the dielectric layer 514. The first internal electrode layer 516a faces the first main surface 512a and the second main surface 512b, has a first opposing electrode portion 518a facing the second internal electrode layer 516b, and is laminated in the direction connecting the first main surface 512a and the second main surface 512b.

[0176] The second internal electrode layer 516b is disposed on a surface of a dielectric layer 514 different from the surface of the dielectric layer 514 on which the first internal electrode layer 516a is disposed. The second internal electrode layer 516b has a second opposing electrode portion 518b opposing the first main surface 512a and the second main surface 512b, and is laminated in the direction connecting the first main surface 512a and the second main surface 512b.

[0177] 10 and 12a to 12d, the first internal electrode layer 516a is extended by a first extension electrode portion 520a to the first side surface 512c and the third side surface 512e of the laminate 512, and is extended by a second extension electrode portion 520b to the second side surface 512d and the fourth side surface 512f of the laminate 512. The width of the first extension electrode portion 520a extended to the first side surface 512c may be approximately equal to the width of the first extension electrode portion 520a extended to the third side surface 512e, and the width of the second extension electrode portion 520b extended to the second side surface 512d may be approximately equal to the width of the second extension electrode portion 520b extended to the fourth side surface 512f.

[0178] That is, the first extraction electrode portion 520 a is extracted to the first side surface 512 c of the laminate 512 , and the second extraction electrode portion 520 b is extracted to the second side surface 512 d of the laminate 512 .

[0179] 10 and 12a to 12d, the second internal electrode layer 516b is extended by a third extension electrode portion 521a to the first side surface 512c and the fourth side surface 512f of the laminate 512, and is extended by a fourth extension electrode portion 521b to the second side surface 512d and the third side surface 512e of the laminate 512. The width over which the third extension electrode portion 521a is extended to the first side surface 512c may be approximately equal to the width over which it is extended to the fourth side surface 512f, and the width over which the fourth extension electrode portion 521b is extended to the second side surface 512d may be approximately equal to the width over which it is extended to the third side surface 512e.

[0180] That is, the third extraction electrode portion 521 a is extracted to the fourth side surface 512 f side of the laminate 512 , and the fourth extraction electrode portion 521 b is extracted to the third side surface 512 e side of the laminate 512 .

[0181] Furthermore, when the multilayer ceramic capacitor 510 is viewed from the stacking direction, it is preferable that a straight line connecting the first extraction electrode portion 520a and the second extraction electrode portion 520b of the first internal electrode layer 516a intersects with a straight line connecting the third extraction electrode portion 521a and the fourth extraction electrode portion 521b of the second internal electrode layer 516b.

[0182] Furthermore, on the first side surface 512c, the second side surface 512d, the third side surface 512e and the fourth side surface 512f of the laminate 512, it is preferable that the first extraction electrode portion 520a of the first internal electrode layer 516a and the fourth extraction electrode portion 521b of the second internal electrode layer 516b are extracted to opposing positions, and that the second extraction electrode portion 520b of the first internal electrode layer 516a and the third extraction electrode portion 521a of the second internal electrode layer 516b are extracted to opposing positions.

[0183] As shown in Figures 14 and 15, the first extraction electrode portion 520a may be configured to extract the first internal electrode layer 516a only to the first side surface 512c of the laminate 512, and the second extraction electrode portion 520b may be configured to extract the first internal electrode layer 516a only to the second side surface 512d of the laminate 512.

[0184] Also, as shown in Figures 14 and 15, the third extraction electrode portion 521a may be configured to extract the first internal electrode layer 516a only to the fourth side surface 512f of the laminate 512, and the fourth extraction electrode portion 521b may be configured to extract the first internal electrode layer 516a only to the third side surface 512e of the laminate 512.

[0185] As shown in FIG. 10, the laminate 512 also includes an end (L gap) 522b of the laminate 512 formed between one end in the longitudinal direction z of the first opposing electrode portion 518a and the third side surface 512e, and between the other end in the longitudinal direction z of the second opposing electrode portion 518b and the fourth side surface 512f.

[0186] Furthermore, as shown in FIG. 10, the laminate 512 includes a side portion (W gap) 522a of the laminate 512 formed between one end in the width direction y of the first opposing electrode portion 518a and the first side surface 512c, and between the other end in the width direction y of the second opposing electrode portion 518b and the second side surface 512d.

[0187] In the laminate 512, the dielectric layer 514 for the effective layer portion 515a may be disposed so as to be sandwiched between the first internal electrode layers 516a and 516a. In this case, the first internal electrode layers 516a and 516a are disposed continuously with the dielectric layer 514 for the effective layer portion 515a interposed therebetween.

[0188] Furthermore, the dielectric layer 514 for the effective layer portion 515a may be disposed so as to be sandwiched between the second internal electrode layers 516b and 516b. In this case, the second internal electrode layers 516b and 516b are disposed continuously with the dielectric layer 514 for the effective layer portion 515a interposed therebetween.

[0189] The shape of the first opposing electrode portion 518a of the first internal electrode layer 516a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed at an angle in plan view (tapered). Alternatively, the first opposing electrode portion 518a may be tapered in plan view, with a slope increasing in either direction.

[0190] The shapes of the first lead electrode portion 520a and the second lead electrode portion 520b of the first internal electrode layer 516a are not particularly limited, but are preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the shape may be tapered in plan view, with a slope increasing toward either side.

[0191] The shape of the second opposing electrode portion 518b of the second internal electrode layer 516b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second opposing electrode portion 518b may be tapered in plan view, with a slope increasing in either direction.

[0192] The shapes of the third lead electrode portion 521a and the fourth lead electrode portion 521b of the second internal electrode layer 16b are not particularly limited, but are preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the shape may be tapered in plan view, with a slope increasing toward either side.

[0193] The material of the internal electrode layer 516 can be, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an appropriate conductive material containing one of these metals, such as an Ag-Pd alloy, but is not limited to these.

[0194] Furthermore, the number of stacked first internal electrode layers 516a and second internal electrode layers 516b can be changed as appropriate depending on the size, etc. Increasing the number of first internal electrode layers 516a can prevent the DC resistance from increasing.

[0195] The first internal electrode layers 516a may be stacked continuously in the height direction x, or the first internal electrode layers 516a and the second internal electrode layers 516b may be stacked alternately.

[0196] In the laminate 512, a first dummy electrode layer may be disposed on an extension line of the first lead electrode portion 520a of the first internal electrode layer 516a in the height direction x.

[0197] A second dummy electrode layer may be disposed on an extension line of the second lead electrode portion 520b of the first internal electrode layer 516a in the height direction x.

[0198] A third dummy electrode layer may be disposed on an extension line of the third lead electrode portion 521a of the second internal electrode layer 516b in the height direction x.

[0199] A fourth dummy electrode layer may be disposed on an extension line of the fourth lead electrode portion 521b of the second internal electrode layer 516b in the height direction x.

[0200] The first dummy electrode layer and the second dummy electrode layer may be disposed on the first outer layer portion 515b1 and the second outer layer portion 515b2.

[0201] The first dummy electrode layer is preferably disposed on the same plane as the second internal electrode layer 516b and has the same thickness as the second internal electrode layer 516b. In this case, the first dummy electrode layer and the second internal electrode layer 516b are not electrically connected to each other.

[0202] The second dummy electrode layer is preferably disposed on the same plane as the second internal electrode layer 516b and has the same thickness as the second internal electrode layer 516b. In this case, the second dummy electrode layer and the second internal electrode layer 516b are not electrically connected to each other.

[0203] The third dummy electrode layer is preferably disposed on the same plane as the first internal electrode layer 516a and has the same thickness as the first internal electrode layer 516a. In this case, the third dummy electrode layer and the first internal electrode layer 516a are not electrically connected to each other.

[0204] The fourth dummy electrode layer is preferably disposed on the same plane as the first internal electrode layer 516a and has the same thickness as the first internal electrode layer 516a. In this case, the fourth dummy electrode layer and the first internal electrode layer 516a are not electrically connected to each other.

[0205] Reducing the coverage of the first dummy electrode and the second dummy electrode can shorten the current path and also serve as a starting point for plating when forming a direct plating layer, which will be described later, thereby forming a uniform plating film.

[0206] The first lead electrode portion 520a and the second lead electrode portion 520b of the first internal electrode layer 516a may be curved.

[0207] The third lead electrode portion 521a and the fourth lead electrode portion 521b of the second internal electrode layer 516b may be curved.

[0208] In this case, the mounting surface may be curved toward either the first main surface 512 a or the second main surface 512 b. In this case, the current path can be shortened by making the mounting surface the curved surface.

[0209] Of the first internal electrode layers 516a extended to the first side surface 512c and the third side surface 512e, and the second side surface 512d and the fourth side surface 512f, the distance between the one located closest to the first main surface 512a and the one located closest to the second main surface 512b may be shorter than the distance between the first opposing electrode portions 518a of the first internal electrode layer 516a located closest to the first main surface 512a and the one located closest to the second main surface 512b.

[0210] Of the second internal electrode layers 516b extended to the second side surface 512d and the fourth side surface 512f and the first side surface 512c and the third side surface 512e, the distance between the one located closest to the first main surface 512a and the one located closest to the second main surface 512b may be shorter than the distance between the second opposing electrode portions 518b of the second internal electrode layer 516b located closest to the first main surface 512a and the one located closest to the second main surface 512b.

[0211] In order to increase the capacitance of the capacitor, it is necessary to increase the area of ​​each of the first internal electrode layer 516a and the second internal electrode layer 516b of the internal electrode layer 516, and therefore it is preferable that the LW surface coverage of each of the first internal electrode layer 16a and the second internal electrode layer 16b is 90% or more. The LW surface coverage is defined as the ratio of the area inside the edge of the first internal electrode layer 516a or the second internal electrode layer 516b when viewed from the LW surface of the laminate 512 minus the area of ​​the void.

[0212] The higher the LW surface coverage, the higher the capacitance of the capacitor. However, even if the LW surface coverage is low, the dielectric layers 514 are bonded together via gaps, which increases the bonding strength between the layers and makes delamination less likely to occur.

[0213] The first internal electrode layer 516a preferably has a uniform thickness, but the thickness of the edge portion of the first internal electrode layer 516a may be thicker than the thickness of the central portion. By making the edge portion thicker than the central portion, coverage is improved, the current path is shortened, and the ESL characteristics are improved.

[0214] The thickness of the edge portion of the first internal electrode layer 516a may be thinner than the thickness of the central portion. By making the edge portion thinner than the central portion, the step corresponding to the thickness of the first internal electrode layer 516a is alleviated, and structural defects are suppressed.

[0215] Similarly, the second internal electrode layer 516b preferably has a uniform thickness, but the thickness of the edge portion of the second internal electrode layer 516b may be thicker than the thickness of the central portion. By making the edge portion thicker than the central portion, coverage is improved, the current path is shortened, and the ESL characteristics are improved.

[0216] The thickness of the edge portion of the second internal electrode layer 516b may be thicker than the thickness of the central portion. The thickness of the edge portion of the second internal electrode layer 516b may be thinner than the thickness of the central portion. By making the edge portion thinner than the central portion, the step corresponding to the thickness of the second internal electrode layer 516b is alleviated, and structural defects are suppressed.

[0217] The thickness of each of the first internal electrode layer 516a and the second internal electrode layer 516b of the internal electrode layer 516 is preferably, for example, about 0.1 μm or more and 0.8 μm or less.

[0218] The total number of the first internal electrode layers 516a and the second internal electrode layers 516b of the internal electrode layers 516 is preferably about 20 to 60.

[0219] 7 to 10, external electrodes 524, 525 are disposed on the laminate 512. The thickness of the external electrodes 524, 525 is preferably, for example, about 1 μm or more and 30.0 μm or less.

[0220] The external electrode 524 includes a base electrode layer 526 and a plating layer 528 formed to cover the base electrode layer 526 .

[0221] The external electrode 525 includes a base electrode layer 527 and a plating layer 529 formed to cover the base electrode layer 527 .

[0222] The external electrode 524 includes a first external electrode 524a and a second external electrode 524b.

[0223] The first external electrode 524a is disposed so as to cover the first lead electrode portion 520a on the first side surface 512c and the third side surface 512e, and so as to cover parts of the first main surface 512a and the second main surface 512b. The first external electrode 524a is electrically connected to the first lead electrode portion 520a of the first internal electrode layer 516a.

[0224] The first external electrode 524a may be disposed so as to cover the first extraction electrode portion 520a only on the first side surface 512c.

[0225] The second external electrode 524b is disposed so as to cover the second lead electrode portion 520b on the second side surface 512d and the fourth side surface 512f, and to cover parts of the first main surface 512a and the second main surface 512b. The second external electrode 524b is electrically connected to the second lead electrode portion 520b of the first internal electrode layer 516a.

[0226] The second external electrode 524b may be disposed so as to cover the second extraction electrode portion 520b only on the second side surface 512d.

[0227] The external electrode 525 includes a third external electrode 525a and a fourth external electrode 525b.

[0228] The third external electrode 525a is disposed so as to cover the third lead electrode portion 521a on the first side surface 512c and the fourth side surface 512f, and so as to cover parts of the first main surface 512a and the second main surface 512b. The third external electrode 525a is electrically connected to the third lead electrode portion 521a of the second internal electrode layer 516b.

[0229] The third external electrode 525a may be disposed so as to cover the third extraction electrode portion 521a only on the fourth side surface 512f.

[0230] The fourth external electrode 525b is disposed so as to cover the fourth lead electrode portion 521b on the second side surface 512d and the third side surface 512e, and to cover parts of the first main surface 512a and the second main surface 512b. The fourth external electrode 525b is electrically connected to the fourth lead electrode portion 521b of the second internal electrode layer 516b.

[0231] The fourth external electrode 525b may be disposed so as to cover the fourth extraction electrode portion 521b only on the third side surface 512e.

[0232] In the laminate 512, a capacitance is formed by the first opposing electrode portion 518a of the first internal electrode layer 516a and the second opposing electrode portion 518b of the second internal electrode layer 516b opposing each other via the dielectric layer 514. Therefore, a capacitance can be obtained between the first external electrode 524a and the second external electrode 524b to which the first internal electrode layer 516a is connected and the third external electrode 525a and the fourth external electrode 525b to which the second internal electrode layer 516b is connected, thereby exhibiting the characteristics of a capacitor.

[0233] (Base Electrode Layer) The base electrode layer 526 has a first base electrode layer 526a and a second base electrode layer 526b.

[0234] The first base electrode layer 526a is arranged so as to cover the first extraction electrode portion 520a on the first side surface 512c and the third side surface 512e, and is arranged so as to cover parts of the first main surface 512a and the second main surface 512b.

[0235] The second base electrode layer 526b is arranged so as to cover the second extraction electrode portion 520b on the second side surface 512d and the fourth side surface 512f, and is arranged so as to cover parts of the first main surface 512a and the second main surface 512b.

[0236] The base electrode layer 527 includes a third base electrode layer 527a and a fourth base electrode layer 527b.

[0237] The third base electrode layer 527a is arranged so as to cover the third extraction electrode portion 521a on the first side surface 512c and the fourth side surface 512f, and is arranged so as to cover parts of the first main surface 512a and the second main surface 512b.

[0238] The fourth base electrode layer 527b is arranged so as to cover the fourth extraction electrode portion 521b on the second side surface 512d and the third side surface 512e, and is arranged so as to cover parts of the first main surface 512a and the second main surface 512b.

[0239] The first underlying electrode layer 526a, the second underlying electrode layer 526b, the third underlying electrode layer 527a, and the fourth underlying electrode layer 527b each include at least one selected from a baked layer, a thin film layer, a fired electrode layer, and the like.

[0240] (In the case of a baking layer) The base electrode layer 526 as a baking layer contains a glass component and a metal. The glass component contains at least one element selected from B, Si, Ba, Mg, Al, Li, and the like.

[0241] The metal of the baking layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, and AU.

[0242] The baking layer may be a multi-layer.

[0243] The baked layer is formed by applying a conductive paste containing glass and metal to the laminate and baking it, and may be baked simultaneously with the internal electrode layer 516 or may be baked after the internal electrode layer 516 has been baked.

[0244] In the case of a baked layer, the thickness of the first base electrode layer 526a located on the first side surface 512c and the third side surface 512e at the center in the height direction x is preferably, for example, 1 μm to 11 μm, and the thickness of the second base electrode layer 526b located on the second side surface 512d and the fourth side surface 512f at the center in the height direction x is preferably 1 μm to 11 μm.

[0245] Furthermore, when the first base electrode layer 526a as a baking layer is provided on the first main surface 512a and the second main surface 512b, it is preferable that the thickness of the first base electrode layer 526a located on the first main surface 512a and the second main surface 512b at the center in the height direction x is, for example, not less than 1 μm and not more than 11 μm.

[0246] Furthermore, when the second base electrode layer 526b as a baking layer is provided on the first main surface 512a and the second main surface 512b, it is preferable that the thickness of the second base electrode layer 526b located on the first main surface 12a and the second main surface 12b at the center in the height direction x is, for example, 1 μm or more and 11 μm or less.

[0247] In the case of a baked layer, the thickness of the third base electrode layer 527a located on the first side surface 512c and the fourth side surface 512f at the center in the height direction x is preferably, for example, 1 μm or more and 11 μm or less, and the thickness of the fourth base electrode layer 527b located on the second side surface 512d and the third side surface 512e at the center in the height direction x is preferably 1 μm or more and 11 μm or less.

[0248] Furthermore, when the third base electrode layer 527a as a baking layer is provided on the first main surface 512a and the second main surface 512b, it is preferable that the thickness of the third base electrode layer 527a located on the first main surface 512a and the second main surface 512b at the center in the height direction x is, for example, 1 μm or more and 11 μm or less.

[0249] Furthermore, when the fourth base electrode layer 527b as a baking layer is provided on the first main surface 512a and the second main surface 512b, it is preferable that the thickness of the fourth base electrode layer 527b located on the first main surface 12a and the second main surface 12b at the center in the height direction x is, for example, 1 μm or more and 11 μm or less.

[0250] (In the case of thin film layers) The base electrode layers 526, 527 formed from thin film layers are preferably formed by a thin film formation method such as sputtering or vapor deposition. In particular, the base electrode layers 526, 527 formed from thin film layers are preferably sputtered electrodes formed by sputtering. When thin film layers are formed by sputtering, the thin film layers can be detected, for example, by a calibration curve method for the relevant metal species using a fluorescent X-ray device. Alternatively, thin film layers can be detected from actual observation images of a cross section of a component taken with an FIB using a scanning microscope. Electrodes formed by sputtering will be described below.

[0251] As shown in FIG. 16(a), the base electrode layers 526 and 527 formed of thin film layers by sputtering are layers on which metal particles are deposited.

[0252] In the base electrode layer 526 formed of a thin film layer by sputtering, the first base electrode layer 526a is located on parts of the first and second main surfaces 512a and 512b, as well as on parts of corners where the first main surface 512a, the first side surface 512c, and the third side surface 512e intersect and on parts of corners where the second main surface 512b, the first side surface 512c, and the third side surface 512e intersect. Specifically, it is preferable that the first base electrode layer 526a be located from the first main surface 512a to 50% of the thickness of the first outer layer portion 515b1 and from the second main surface 512b to 50% of the thickness of the second outer layer portion 515b2.

[0253] Although not shown, in the base electrode layer 526 formed of a thin film layer by sputtering, the second base electrode layer 526b is located on parts of the first and second main surfaces 512a, 512b, and also on parts of corners where the first main surface 512a, the second side surface 512d, and the fourth side surface 512f intersect, and on parts of corners where the second main surface 512b, the second side surface 512d, and the fourth side surface 512f intersect. Specifically, it is preferable that the second base electrode layer 526b be located from the first main surface 512a to 50% of the thickness of the first outer layer portion 515b1 and from the second main surface 512b to 50% of the thickness of the second outer layer portion 515b2.

[0254] Furthermore, although not shown, in the base electrode layer 527 formed of a thin film layer by sputtering, the third base electrode layer 527a is located on parts of the first and second main surfaces 512a and 512b, as well as on parts of corners where the first main surface 512a, the first side surface 512c, and the fourth side surface 512f intersect and on parts of corners where the second main surface 512b, the first side surface 512c, and the fourth side surface 512f intersect. Specifically, it is preferable that the third base electrode layer 527a be located from the first main surface 512a to 50% of the thickness of the first outer layer portion 515b1 and from the second main surface 512b to 50% of the thickness of the second outer layer portion 515b2.

[0255] 16( a), in the base electrode layer 527 formed of a thin film layer by sputtering, the fourth base electrode layer 527b is located on parts of the first and second main surfaces 512a and 512b, as well as on parts of corners where the first main surface 512a, the second side surface 512d, and the third side surface 512e intersect and on parts of corners where the second main surface 512b, the second side surface 512d, and the third side surface 512e intersect. Specifically, it is preferable that the fourth base electrode layer 527b be located from the first main surface 512a to 50% of the thickness of the first outer layer portion 515b1 and from the second main surface 512b to 50% of the thickness of the second outer layer portion 515b2.

[0256] Conventionally, thin film layers are arranged only on the first main surface 512a and the second main surface 512b, so if the outer layer is thick, the distance between the internal electrode layer 16 and the thin film layers, that is, the base electrode layers 526 and 527, becomes large, and there is a risk that the direct plating layer, which will be described later, will become depressed. However, if the thin film layer is arranged so that it extends around to part of the side surface, the direct plating layer can be formed to have a uniform thickness when arranged, which makes it possible to improve moisture resistance.

[0257] The base electrode layers 526 and 527 formed of thin film layers may be located only on the first main surface 512 a. In this case, although not shown, the shape of the external electrodes is generally L-shaped, so that the dimension in the stacking direction can be reduced by the thickness of the external electrodes.

[0258] Furthermore, the base electrode layers 526, 527 formed of thin film layers may be located only on a portion of the first main surface 512a and the second main surface 512b, and may not extend around the first side surface 512c, the second side surface 512d, the third side surface 512e, and the fourth side surface 512f.

[0259] The base electrode layers 526 and 527 formed of thin film layers have a thickness of 1 μm or less in the height direction x connecting the first main surface 512 a and the second main surface 512 b.

[0260] (In the Case of Fired Electrode Layer) The base electrode layers 526 and 527 formed by the fired electrode layer are layers containing a metal component and a dielectric material that is the same component as the dielectric layer 14 .

[0261] The base electrode layers 526, 527 formed by the fired electrode layers are arranged on the first main surface 512a and the second main surface 512b, as well as the first side surface 512c, the second side surface 512d, the third side surface 512e and the fourth side surface 512f, and may be fired simultaneously with the laminate 512, or the firing process may be performed after firing the laminate 512.

[0262] As shown in Figure 17(a), in the base electrode layer 526 formed from the fired electrode layer, it is preferable that the first base electrode layer 526a is located only on a portion of the first main surface 512a and the second main surface 512b, and is arranged so as not to wrap around each of the first side surface 512c and the third side surface 512e.

[0263] Although not shown, in the base electrode layer 526 formed from a fired electrode layer, it is preferable that the second base electrode layer 526b is located only on a portion of the first main surface 512a and the second main surface 512b, and is arranged so as not to wrap around each of the second side surface 512d and the fourth side surface 512f.

[0264] Furthermore, although not shown, in the base electrode layer 527 formed from a fired electrode layer, it is preferable that the third base electrode layer 527a is located only on a portion of the first main surface 512a and the second main surface 512b, and is arranged so as not to wrap around each of the first side surface 512c and the fourth side surface 512f.

[0265] Similarly, as shown in Figure 17(a), in the base electrode layer 527 formed from a fired electrode layer, it is preferable that the fourth base electrode layer 527b is located only on a portion of the first main surface 512a and the second main surface 512b, and is arranged so as not to wrap around each of the second side surface 512d and the third side surface 512e.

[0266] The base electrode layers 526 and 527 formed of fired electrode layers may be located only on the first main surface 512 a. In this case, although not shown, the shape of the external electrodes is generally L-shaped, so that the dimension in the stacking direction can be reduced by the thickness of the external electrodes.

[0267] In addition, the base electrode layers 526, 527 formed by firing electrode layers using a screen printing method may be located on a portion of the first main surface 512a and the second main surface 512b, and may also wrap around each of the first side surface 512c, the second side surface 512d, the third side surface 512e, and the fourth side surface 512f.

[0268] 18(a), the base electrode layers 526 formed of fired electrode layers may be separately disposed on the first principal surface 512a, the second principal surface 512b, and the side surface. Similarly, the base electrode layers 527 formed of fired electrode layers may be separately disposed on the first principal surface 512a, the second principal surface 512b, and the side surface.

[0269] The base electrode layers 526, 527 formed of fired electrode layers may be arranged discontinuously. Here, discontinuous means that the first base electrode layer 526a of the base electrode layer 526 is in a state where smearing occurs on the first main surface 512a, the second main surface 512b, the first side surface 512c, and the third side surface 512e, and that the second base electrode layer 526b of the base electrode layer 526 is in a state where smearing occurs on the first main surface 512a, the second main surface 512b, the first side surface 512c, and the fourth side surface 512f. It also means that the third base electrode layer 527a of the base electrode layer 527 has blurred portions on the first main surface 512a, the second main surface 512b, the second side surface 512d, and the third side surface 512e, and that the fourth base electrode layer 527b of the base electrode layer 527 has blurred portions on the first main surface 512a, the second main surface 512b, the second side surface 512d, and the fourth side surface 512f.

[0270] When the base electrode layers 526, 527 formed by the fired electrode layers are arranged discontinuously, the surface area of ​​the conductive component increases, improving the adhesion of the direct plating layer described below.

[0271] However, as shown in FIG. 8, etc., the base electrode layers 526, 527 formed by fired electrode layers arranged on the first main surface 512a and the second main surface 512b may be arranged over a portion of the first side surface 512c, the second side surface 512d, the third side surface 512e, and the fourth side surface 512f, as appropriate.

[0272] This reduces the distance between either the internal electrode layer 16 closest to the first main surface 512a or the second main surface 512b, which is the starting point of plating for the direct plating layer described later, and the base electrode layers 526, 527, so that the thickness of the direct plating layer can be formed to be uniform even on the first outer layer portion 515b1 and the second outer layer portion 515b2, thereby improving moisture resistance.

[0273] (Plating Layer) As shown in FIG. 10, the plating layer 528 includes a first plating layer 528a and a second plating layer 528b.

[0274] The first plating layer 528a is disposed so as to cover the first base electrode layer 526a.

[0275] The second plating layer 528b is disposed so as to cover the second base electrode layer 526b.

[0276] As shown in FIG. 10, the plating layer 529 includes a third plating layer 529a and a fourth plating layer 529b.

[0277] The third plating layer 529a is disposed so as to cover the third base electrode layer 527a.

[0278] The fourth plating layer 529b is disposed so as to cover the fourth base electrode layer 527b.

[0279] The plating layer 528 includes at least one selected from, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, and Au.

[0280] Similarly, the plating layer 529 includes at least one selected from, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, and Au.

[0281] The plating layer 528 may be formed of multiple layers. In this embodiment, the plating layer 528 has a two-layer structure of Ni plating and Sn plating, and includes a lower plating layer 530 which is a Ni plating layer that covers the base electrode layer 526, and an upper plating layer 532 which is a Sn plating layer that is arranged to cover the lower plating layer 530. Similarly, the plating layer 529 includes a lower plating layer 531 and an upper plating layer 533 that is arranged to cover the base electrode layer 527 and the lower plating layer 531.

[0282] The Ni plating layer can prevent the base electrode layers 526, 527 from being eroded by solder when mounting the multilayer ceramic capacitor, and the Sn plating improves the wettability of the solder when mounting the multilayer ceramic capacitor, making it easier to mount.

[0283] When the plating layers 528 and 529 have a three-layer structure, they are preferably laminated in the order of Sn plating, Ni plating, and Sn plating.

[0284] The lower plating layer 530 includes a first lower plating layer 530a and a second lower plating layer 530b.

[0285] The first lower layer plating layer 530a is arranged on the surface of the laminate 512 so as to cover the first base electrode layer 526a arranged on the first main surface 512a, the second main surface 512b, the first side surface 512c and the third side surface 512e.

[0286] The second lower plating layer 530b is disposed on the surface of the laminate 512 so as to cover the second base electrode layer 526b exposed on the first main surface 512a, the second main surface 512b, the second side surface 512d and the fourth side surface 512f.

[0287] The lower plating layer 531 includes a third lower plating layer 531a and a fourth lower plating layer 531b.

[0288] The third lower plating layer 531a is disposed on the surface of the laminate 512 so as to cover the third base electrode layer 527ab exposed on the first main surface 512a, the second main surface 512b, the first side surface 512c, and the fourth side surface 512f.

[0289] The fourth lower plating layer 531b is disposed on the surface of the laminate 512 so as to cover the fourth base electrode layer 527b exposed on the first main surface 512a, the second main surface 512b, the second side surface 512d and the third side surface 512e.

[0290] The upper plating layer 532 has a first upper plating layer 532a and a second upper plating layer 532b.

[0291] The first upper plating layer 532a is disposed so as to cover the first lower plating layer 530a. Specifically, the first upper plating layer 532a is disposed on the first side surface 512c and the third side surface 512e of the surface of the first lower plating layer 530a, and is provided so as to extend to the first main surface 512a and the second main surface 512b of the surface of the first lower plating layer 530a.

[0292] The second upper plating layer 532b is disposed so as to cover the second lower plating layer 530b. Specifically, the second upper plating layer 532b is disposed on the second side surface 512d and the fourth side surface 512f of the surface of the second lower plating layer 530b, and is provided so as to extend to the first main surface 512a and the second main surface 512b of the surface of the second lower plating layer 530b.

[0293] The upper plating layer 533 includes a third upper plating layer 533a and a fourth upper plating layer 533b.

[0294] The third upper plating layer 533a is disposed so as to cover the third lower plating layer 531a. Specifically, the third upper plating layer 533a is disposed on the first side surface 512c and the fourth side surface 512f of the surface of the third lower plating layer 531a, and is provided so as to extend to the first main surface 512a and the second main surface 512b of the surface of the third lower plating layer 531a.

[0295] The fourth upper plating layer 533b is disposed so as to cover the fourth lower plating layer 531b. Specifically, the fourth upper plating layer 533b is disposed on the second side surface 512d and the third side surface 512e of the surface of the fourth lower plating layer 531b, and is provided so as to extend to the first main surface 512a and the second main surface 512b of the surface of the fourth lower plating layer 531b.

[0296] The thickness of each of the plating layers 528 and 529 is preferably 1 μm or more and 11 μm or less.

[0297] (In the case of direct plating layers) In the external electrodes 524, 525, the plating layers 540, 541 may be formed directly between the base electrode layers 526, 527 and the plating layers 528, 529. That is, in the multilayer ceramic capacitor, the plating layers 540, 541 may be arranged so as to cover the base electrode layers 526, 527 on the main surfaces 512a, 512b, and may be arranged so as to be electrically connected to the first internal electrode layer 516a or the second internal electrode layer 516b on the side surfaces 512c, 512d. In such a case, the plating layers may be formed directly after a catalyst is provided on the surfaces of the base electrode layers 526, 527 and the laminate 512 as a pretreatment.

[0298] 16(b) and 17(b) are examples in which plating layers 540, 541 are formed directly between the base electrode layers 526, 527 and the plating layers 528, 529. That is, the direct plating layers 540, 541 cover the base electrode layers 526, 527 on the main surfaces 512a, 512b side, and cover the internal electrode layer 516 on the side surfaces 521c, 512b side. In addition, the direct plating layers 540, 541 shown in FIG. 18(b) cover the base electrode layers 526, 527 on the main surfaces 512a, 512b side and the side surfaces 521c, 512b side.

[0299] More specifically, as shown in Figures 16(b) and 17(b), the direct plating layer 540a is arranged so as to cover the first base electrode layer 526a arranged on the first main surface 512a and the second main surface 512b, and is also arranged on the surface of the first side surface 512c so as to be electrically connected to at least the first internal electrode layer 516a exposed on the first side surface 512c.

[0300] Similarly, although not shown, the direct plating layer 540b is arranged so as to cover the second base electrode layer 526b arranged on the first main surface 512a and the second main surface 512b, and is also arranged on the surface of the second side surface 512d so as to be electrically connected to at least the first internal electrode layer 516a exposed on the second side surface 512d.

[0301] Similarly, although not shown, the direct plating layer 541b is arranged so as to cover the third base electrode layer 527a arranged on the first main surface 512a and the second main surface 512b, and is also arranged on the surface of the first side surface 512c so as to be electrically connected to the second internal electrode layer 516b exposed on at least the first side surface 512c.

[0302] Similarly, as shown in Figures 16(b) and 17(b), the direct plating layer 541a is arranged so as to cover the fourth base electrode layer 527b arranged on the first main surface 512a and the second main surface 512b, and is also arranged on the surface of the second side surface 512d so as to be electrically connected to at least the second internal electrode layer 516b exposed on the second side surface 512d.

[0303] The direct plating layer preferably contains at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, Zn, etc., or an alloy containing such a metal.

[0304] For example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, it is preferable that the direct plating layer be formed using Cu, which has good bonding properties with Ni.

[0305] The thickness of each direct plating layer is preferably 1 μm or more and 11 μm or less.

[0306] Preferably, the direct plating layer does not contain glass, and the metal content per unit volume of the direct plating layer is preferably 99% by volume or more.

[0307] When a plating layer is directly formed, since each of the first side surface 512c, the second side surface 512d, the third side surface 512e, and the fourth side surface 512f is curved, the exposed area of ​​the internal electrode layer 16 increases compared to when each side surface is flat, and the time required for plating formation can be shortened. In addition, the probability of contact between the media and the metal component when forming the plating can be improved.

[0308] The dimension in the length direction z of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 524, 525 is defined as dimension L, the dimension in the height direction x of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 524, 525 is defined as dimension T, and the dimension in the width direction y of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 524, 525 is defined as dimension W.

[0309] The dimensions of the multilayer ceramic capacitor 10 are preferably such that the L dimension in the length direction z is 0.1 mm to 6.0 mm, the T dimension in the height direction x is 10 μm to 300 μm, and the W dimension in the width direction y is 0.1 mm to 6.0 mm.

[0310] In the present embodiment, each of the first side surface 512c, the second side surface 512d, the third side surface 512e, and the fourth side surface 512f is curved from the first main surface 12a to the second main surface 12b. The radius of curvature is preferably 5 / 2 or less of the thickness dimension in the height direction x of the laminate 12 at the center in the length direction z of the laminate 12.

[0311] This increases the exposed area on the first side surface 512c, the second side surface 512d, the third side surface 512e, and the fourth side surface 512f of the internal electrode layer 516, thereby increasing the adhesive strength between the conductive components of the external electrodes 524, 525 and the laminate 512. Furthermore, because the exposed area of ​​the conductive components of the external electrodes 524, 525 is increased, the ESR can be kept small.

[0312] The curvature radii of the first side surface 512c, the second side surface 512d, the third side surface 512e, and the fourth side surface 512f of the laminate 512 can be measured by the same measuring method as in the first embodiment.

[0313] When the end surface exposed for measurement includes the external electrodes 524 and 525, the radius of curvature of the first side surface 512c is measured based on the edge of the first opposing electrode portion 518a and the second opposing electrode portion 518b that are not extended to the first side surface 512c, and the radius of curvature of the second side surface 512d is measured based on the edge of the first opposing electrode portion 518a and the second opposing electrode portion 518b that are not extended to the second side surface 512d. The same standard is used for the radii of curvature of the third side surface 512e and the fourth side surface 512f. The radius of curvature is defined starting from a point 5% inward from each standard toward the corresponding side surface.

[0314] Furthermore, when the end face exposed for measurement does not include the external electrodes 524, 525, the radius of curvature of the first side surface 512 c is measured using the edge portions of the first opposing electrode portion 518 a and the second opposing electrode portion 518 b on the first side surface 512 c side as the reference, and the radius of curvature of the second side surface 512 d is measured using the edge portions of the first opposing electrode portion 518 a and the second opposing electrode portion 518 b on the second side surface 512 d side as the reference. The radius of curvature is defined starting from a point 5% in from each reference point toward each side surface.

[0315] 2. Method for Manufacturing the Multilayer Ceramic Capacitor A method for manufacturing a multilayer ceramic capacitor, which is an example of the multilayer ceramic capacitor according to the second embodiment, will now be described.

[0316] First, a dielectric sheet and a conductive paste for the internal electrodes are prepared. The dielectric sheet and the conductive paste for the internal electrode layers contain a binder (e.g., a known organic binder) and a solvent (e.g., a known organic binder).

[0317] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, screen printing or gravure printing, to form an internal electrode pattern. Specifically, a conductive paste layer is formed by applying a paste made of a conductive material to the dielectric sheet by a method such as the printing method described above. The conductive paste is, for example, a paste made of a metal powder to which an organic binder and an organic solvent have been added. Regarding the dielectric sheets, outer layer dielectric sheets on which no internal electrode patterns are printed are also produced.

[0318] As a result, a dielectric sheet on which an internal electrode pattern corresponding to the first internal electrode layer 516a is formed and a dielectric sheet on which an internal electrode pattern corresponding to the second internal electrode layer 516b is formed are prepared.

[0319] More specifically, a screen plate for printing the first internal electrode layer 516a and a screen plate for printing the second internal electrode layer 516b are prepared separately, and the internal electrode layers of the present invention can be printed using a printer that can print the two types of screen plates separately.

[0320] A laminate sheet is produced using the dielectric sheets on which these internal electrode patterns are formed. That is, a predetermined number of dielectric sheets for outer layers on which no internal electrode patterns are formed are stacked to form a portion that will become the first outer layer portion 515b1 on the first main surface 512a side. On top of that, dielectric sheets on which internal electrode patterns corresponding to the first internal electrode layer 516a are formed and dielectric sheets on which internal electrode patterns corresponding to the second internal electrode layer 516b are formed are alternately stacked to form a portion that will become the effective layer portion 515a, and further on top of that, a predetermined number of dielectric sheets for outer layers on which no internal electrode patterns are formed are stacked to form a portion that will become the second outer layer portion 515b2. In this way, the laminate sheet is produced.

[0321] Furthermore, the laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0322] Next, the laminated block is cut to a predetermined size to cut out laminated chips.

[0323] Next, a laminated chip having the desired shape is formed by barrel polishing. Specifically, the diameter of the barrel polishing media is preferably in the range of 0.2 m to 0.7 m, the media volume is preferably in the range of 200 cc to 700 cc, and the media is rotated not only in one direction but also in multiple directions. In this way, barrel polishing is performed until the entire end face of the laminated chip is rounded. Furthermore, it is preferable to adjust the media diameter according to the T dimension, and to perform sandblasting in addition to barrel polishing.

[0324] Next, the laminated chip is fired to produce laminate 512. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0325] Subsequently, base electrode layers 526 and 527 are formed on the first and second main surfaces 512a and 512b of the laminate 512 and on parts of the first, second, third, and fourth side surfaces 512c, 512d, 512e, and 512f.

[0326] (When the base electrode layer is a baked layer) A conductive paste that will become the base electrode layer is applied to a portion of each of the first side surface 512c, the second side surface 512d, the third side surface 512e, and the fourth side surface 512f of the laminate 512, thereby forming a first base electrode layer 526a and a second base electrode layer 526b of the base electrode layer 526, and a third base electrode layer 527a and a fourth base electrode layer 527b of the base electrode layer 527.

[0327] When forming the baking layer, a conductive paste containing a glass component and a metal is applied by a method such as dipping, and then a baking process is performed to form the base electrode layer. The baking process temperature is preferably 700° C. or higher and 900° C. or lower.

[0328] Furthermore, by using the DIP method, it is possible to form the coating so that it extends not only to any of the first side surface 512c, the second side surface 512d, the third side surface 512e, and the fourth side surface 512f, which are the coating targets, but also to the first main surface 512a and the second main surface 512b, as well as to parts of these side surfaces or the side surfaces adjacent to the main surfaces.

[0329] (When the base electrode layer is a thin film layer) When the base electrode layer is formed as a thin film layer, masking or the like is performed, and base electrode layers 526 and 527 are formed in the areas where external electrodes 524 and 525 are to be formed by a thin film formation method such as sputtering or vapor deposition.

[0330] The base electrode layers 526 and 527 formed from thin film layers are layers of metal particles deposited to a thickness of 1 μm or less.

[0331] At this time, it is preferable that the thin film layer is directly bonded to the plating layer disposed so as to be bonded to the internal electrode layer 16 .

[0332] (When the base electrode layer is a fired electrode layer) When the base electrode layer is formed from a fired electrode layer, before firing the laminated chip, a base electrode layer made of a fired electrode layer is arranged at the desired positions on each of the first main surface 512a and the second main surface 512b, and the first side surface 512c, the second side surface 512d, the third side surface 512e, and the fourth side surface 512f by a method such as screen printing, and then the laminated chip is fired.

[0333] The firing temperature at this time is preferably 700° C. or higher and 1400° C. or lower. By firing the laminated chip and the fired electrode layer simultaneously, contact between the laminated chip and the fired electrode layer is improved, making peeling less likely to occur.

[0334] For example, when a base electrode layer that is a fired electrode layer is formed by screen printing, it is preferably joined to a direct plating layer that is arranged so as to be joined to the internal electrode layer 16. In this case, the base electrode layer that is a fired electrode layer by screen printing may have the same components as the internal electrode layer 16. When the components are the same, the laminate 512 may be fired after the base electrode layer is arranged, as described above, or the baking treatment may be performed after firing the laminate 512.

[0335] Finally, a plating layer is formed. The plating layer may be formed on the surface of the base electrode layer or directly on the laminate. More specifically, a Ni plating layer (base plating layer) and a Sn plating layer are formed on the base electrode layer. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0336] In this manner, the multilayer ceramic capacitor 510 shown in FIG. 7 can be manufactured.

[0337] According to the method for manufacturing a multilayer ceramic capacitor according to the present embodiment described above, it is possible to manufacture a high-quality multilayer ceramic capacitor according to the present invention that has high humidity resistance and can improve the adhesive strength between the conductive components of the external electrodes and the internal electrodes and can keep the ESR low.

[0338] C. Experimental Example A multilayer ceramic capacitor sample was fabricated according to the manufacturing method of the first embodiment described above, and an ESR test was carried out.

[0339] 1 to 3, multilayer ceramic capacitors with the following specifications were prepared as experimental examples: Ceramic material: BaTiO3 Capacitance: 220 nF Rated voltage: 4 V External electrode structure Base electrode layer: Electrode containing conductive metal (Cu) and glass component Thickness of base electrode layer at the center in the longitudinal direction of the base electrode layer located on the first and second main surfaces, the first and second side surfaces: 3 μm Metal layer consisting of plating layer: Two-layer formation of Ni plating layer + Sn plating layer Ni plating layer thickness: Thickness of Ni plating layer at the center in the longitudinal direction of the Ni plating layer located on the first and second main surfaces, the first and second side surfaces: 3 μm Sn plating layer thickness: Thickness of Sn plating layer at the center in the longitudinal direction of the Sn plating layer located on the first and second main surfaces, the first and second side surfaces: 3 μm

[0340] Before forming the base electrode layer, laminates with different degrees of curvature at the end faces were prepared for sample Nos. 2 to 6, by changing the radius of curvature of the end faces as shown in Table 1. Then, a base electrode layer (Cu), a Ni plating layer, and a Sn plating layer were formed on the laminates of sample Nos. 1 to 6 before the formation of the external electrodes, to prepare multilayer ceramic capacitors for each of sample Nos. 1 to 6.

[0341] (b) ESR Test Before measuring ESR, each sample of multilayer ceramic capacitor was heat treated in an air atmosphere at 150°C for 1 hour, then mounted on a measurement board. 24±2 hours after the heat treatment, the ESR was measured using a network analyzer at a measurement frequency of 1 MHz. 100 samples were measured, and the average value was used as the table value. Using sample number 1 as the standard, the ESR was judged as follows: ◯: Less than 97% of the ESR of sample number 1 -: Greater than 97% of the ESR of sample number 1.

[0342] (c) Results Table 1 shows the results of the ESR test for Sample Nos. 1 to 6.

[0343] According to Table 1, in the samples of sample numbers 3 to 6, the radius of curvature was 5 / 2 or less of the thickness dimension in the height direction x of the laminate 12 at the center in the length direction z of the laminate 12, and therefore, good ESR measurement results of 97% or less were obtained compared to the ESR of sample number 1.

[0344] On the other hand, in the case of sample No. 2, the radius of curvature was 5 / 2 or more of the thickness dimension in the height direction x of the laminate 12 at the center in the length direction z of the laminate 12, and therefore the measurement result of ESR was greater than 97% of the ESR of sample No. 1.

[0345] From the above, in each of samples No. 3 to No. 6, the first end face 12e and the second end face 12f of the laminate 12 are each curved from the first main surface 12a to the second main surface 12b, and the radius of curvature is 5 / 2 or less of the thickness dimension in the height direction x of the laminate 12 at the center in the length direction z of the laminate 12, thereby increasing the exposed area of ​​the internal electrode layer 16 on the first end face 12e and the second end face 12f, thereby increasing the adhesive strength between the conductive component of the external electrode 24 and the laminate 12. Furthermore, because the exposed area of ​​the conductive component of the external electrode 24 is increased, an effect of suppressing ESR to a low level was obtained.

[0346] Although the above-described embodiment and each modified example only show shapes that are bilaterally symmetrical when viewed from the front, the external shape of the multilayer ceramic electronic component according to the present invention can be modified in various ways depending on the object to be mounted and the desired performance. The present invention also includes appropriate combinations of all or part of the configurations of the above-described embodiment and each modified example.

[0347] For example, the first main surface 12a of the laminate 12 of the multilayer ceramic capacitor 10 may be curved from the first side surface 12c to the second side surface 12d, or may be curved from the first end surface 12e to the second end surface 12f. Similarly, the second main surface 12b of the laminate 12 may be curved from the first side surface 12c to the second side surface 12d, or may be curved from the first end surface 12e to the second end surface 12f. Furthermore, the first main surface 512a of the laminate 512 of the multilayer ceramic capacitor 510 may be curved from the first side surface 512c to the second side surface 512d, or may be curved from the third side surface 512e to the fourth side surface 512f. Similarly, the second main surface 512b of the laminate 512 may be curved from the first side surface 512c to the second side surface 512d, or from the third side surface 512e to the fourth side surface 512f.

[0348] In other words, various modifications can be made to the above-described embodiments and variants in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and these modifications are included in the present invention.

[0349] <1> A multilayer ceramic capacitor comprising: a laminate including a plurality of dielectric layers stacked one on top of the other, the laminate including first and second main surfaces opposing each other in a height direction which is a stacking direction of the dielectric layers, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, first end faces and second end faces opposing each other in a length direction perpendicular to the height direction and the width direction, first internal electrode layers stacked alternately with the plurality of dielectric layers and exposed at the first end faces, and second internal electrode layers stacked alternately with the plurality of dielectric layers and exposed at the second end faces; a first external electrode provided on the first end faces; and a second external electrode provided on the second end faces, the first end faces and the second end faces each curved from the first main surface to the second main surface, and the radius of curvature of each of the first end faces and the second end faces is 5 / 2 or less of a thickness of the laminate in the height direction at a center part of the laminate in the length direction.

[0350] <2> A laminate including a plurality of dielectric layers stacked together, the laminate including: first and second main surfaces opposing each other in a height direction which is a stacking direction of the dielectric layers; first and second side surfaces opposing each other in a width direction perpendicular to the height direction; first and second side surfaces opposing each other in a width direction perpendicular to the height direction; third and fourth side surfaces opposing each other in a length direction perpendicular to the height direction and the width direction; first internal electrode layers stacked alternately with the plurality of dielectric layers and exposed on at least two or more of the first side surface, the second side surface, the third side surface, and the fourth side surface; and second internal electrode layers stacked alternately with the plurality of dielectric layers and exposed on at least two or more of the first side surface, the second side surface, the third side surface, and the fourth side surface; a first external electrode connected to the first internal electrode layer; and a second external electrode connected to the second internal electrode layer, The multilayer ceramic capacitor, wherein each of the first side surface, the second side surface, the third side surface, and the fourth side surface is curved from the first main surface to the second main surface.

[0351] <3> The multilayer ceramic capacitor according to <2>, wherein the first main surface is curved across the first side surface, the second side surface, the third side surface, and the fourth side surface, and the second main surface is curved across the first side surface, the second side surface, the third side surface, and the fourth side surface.

[0352] <4> The multilayer ceramic capacitor according to <2> or <3>, wherein the radius of curvature of each of the first end face, the second end face, the third end face, and the fourth side face is 5 / 2 or less of the thickness of the laminate in a height direction at a central portion in a longitudinal direction of the laminate.

[0353] <5> The multilayer ceramic capacitor according to <1>, wherein the thickness of the laminate in the height direction is 300 μm or less.

[0354] <6> The multilayer ceramic capacitor according to any one of <2> to <4>, wherein the thickness of the laminate in the height direction is 300 μm or less.

[0355] <7> The multilayer ceramic capacitor according to <6>, wherein the first external electrode has: a first thin film layer disposed on the first main surface; and a first direct plating layer disposed so as to be connected to the first internal electrode layer and covering a part of the first thin film layer; and the second external electrode has: a second thin film layer disposed on the first main surface; and a second direct plating layer disposed so as to be connected to the second internal electrode layer and covering a part of the second thin film layer.

[0356] <8> The multilayer ceramic capacitor according to <7>, wherein the thin film layer is arranged so as to wrap around from the first main surface to a portion of each of the first side surface, the second side surface, the third side surface, and the fourth side surface.

[0357] <9> The multilayer ceramic capacitor according to <8>, wherein the thin film layer is directly connected to at least one of the first internal electrode layer and the second internal electrode layer.

[0358] <10> The multilayer ceramic capacitor according to <6>, wherein the first external electrode has: a first fired electrode layer containing a metal component and a dielectric material arranged on the first principal surface or the second principal surface; and a first base electrode layer arranged so as to be connected to the first internal electrode layer and covering a part of the first fired electrode layer; and the second external electrode has: a second fired electrode layer containing a metal component and a dielectric material arranged on the first principal surface or the second principal surface; and a second base electrode layer arranged so as to be connected to the second internal electrode layer and covering a part of the second fired electrode layer.

[0359] <11> The multilayer ceramic capacitor according to <10>, wherein each of the first fired electrode layer and the second fired electrode layer is discontinuously disposed in the length direction or the width direction.

[0360] <12> The multilayer ceramic capacitor according to <10> or <11>, wherein the first fired electrode layer and the second fired electrode layer are disposed on the first side surface, the second side surface, the third side surface, and the fourth side surface, respectively.

[0361] The present invention relates to a multilayer ceramic capacitor, and in particular, can be used as a multilayer ceramic capacitor having external electrodes with a multilayer structure.

[0362] 10, 510 Multilayer ceramic capacitor 12, 512 Laminate 12a, 512a First main surface 12b, 512b Second main surface 12c, 512c First side surface 12d, 512d Second side surface 12e First end surface 12f Second end surface 14, 514 Dielectric layer 15a, 515a Effective layer portion 15b1, 515b1 First outer layer portion 15b2, 515b2 Second outer layer portion 16, 516 Internal electrode layer 16a, 516a First internal electrode layer 16b, 516b Second internal electrode layer 18a, 518a First opposing electrode portion 18b, 518b Second opposing electrode portion 18b1, 522b End portion 20a, 520a First extraction electrode portion 20b, 520b Second lead electrode portion 22a W gap 22b L gap 24, 524, 525 External electrode 24a, 524a First external electrode 24b, 524b Second external electrode 26, 526, 527 Base electrode layer 26a, 526a First base electrode layer 26b, 526b Second base electrode layer 28, 528, 529 Plating layer 28a, 528a First plating layer 28b, 528b Second plating layer 30, 530, 531 Base plating layer 30a, 530a First base plating layer 30b, 530b Second base plating layer 32, 532, 533 Top plating layer 32a, 532a First top plating layer 32b, 532b Second upper plating layer 512e Third side surface 512f Fourth side surface 521a Third lead electrode portion 521b Fourth lead electrode portion 522a Side portion 525a Third external electrode 525b Fourth external electrode 527a Third base electrode layer 527b Fourth base electrode layer 529a Third plating layer 529b Fourth plating layer 531a Third lower plating layer 531b Fourth lower plating layer 533a Third upper plating layer 533b Fourth upper plating layer

Claims

1. the dielectric layer includes a plurality of dielectric layers stacked together, and has a first main surface and a second main surface that face each other in a height direction, which is a stacking direction of the dielectric layers; a first side surface and a second side surface that face each other in a width direction perpendicular to the height direction; a first end surface and a second end surface that face each other in a length direction perpendicular to the height direction and the width direction; first internal electrode layers that are stacked alternately with the plurality of dielectric layers and exposed at the first end surface; and second internal electrode layers that are stacked alternately with the plurality of dielectric layers and exposed at the second end surface. a laminate comprising: a first external electrode provided on the first end surface; a second external electrode provided on the second end surface, each of the first end surface and the second end surface is curved from the first main surface to the second main surface; a radius of curvature of each of the first end face and the second end face is 5 / 2 or less of a thickness in a height direction of the laminate at a central portion in a length direction of the laminate.

2. a first main surface and a second main surface facing each other in a height direction, which is a stacking direction of the dielectric layers; a first side surface and a second side surface facing each other in a width direction perpendicular to the height direction; a first side surface and a second side surface facing each other in a width direction perpendicular to the height direction; a third side surface and a fourth side surface facing each other in a length direction perpendicular to the height direction and the width direction; first internal electrode layers that are alternately stacked with the plurality of dielectric layers and exposed on at least two or more of the first side surface, the second side surface, the third side surface, and the fourth side surface; and second internal electrode layers that are alternately stacked with the plurality of dielectric layers and exposed on at least two or more of the first side surface, the second side surface, the third side surface, and the fourth side surface. a laminate comprising: a first external electrode connected to the first internal electrode layer; a second external electrode connected to the second internal electrode layer, The multilayer ceramic capacitor, wherein each of the first side surface, the second side surface, the third side surface, and the fourth side surface is curved from the first main surface to the second main surface.

3. the first main surface is curved across each of the first side surface, the second side surface, the third side surface, and the fourth side surface; 3. The multilayer ceramic capacitor according to claim 2, wherein the second main surface is curved across each of the first side surface, the second side surface, the third side surface, and the fourth side surface.

4. 4. The multilayer ceramic capacitor according to claim 2, wherein the radius of curvature of each of the first end face, the second end face, the third end face, and the fourth side face is 5 / 2 or less of the thickness in a height direction of the laminate at a central portion in a longitudinal direction of the laminate.

5. 2. The multilayer ceramic capacitor according to claim 1, wherein the thickness of the laminate in the height direction is 300 [mu]m or less.

6. 4. The multilayer ceramic capacitor according to claim 2, wherein the thickness of the laminate in the height direction is 300 [mu]m or less.

7. The first external electrode is a first thin film layer disposed on the first major surface; a first direct plating layer disposed so as to be connected to the first internal electrode layer and covering a part of the first thin film layer; The second external electrode is a second thin film layer disposed on the first major surface; 7. The multilayer ceramic capacitor according to claim 6, further comprising: a second direct plating layer disposed so as to be connected to said second internal electrode layer and covering a portion of said second thin film layer.

8. 8. The multilayer ceramic capacitor according to claim 7, wherein the thin film layer is disposed so as to extend from the first main surface around a portion of each of the first side surface, the second side surface, the third side surface, and the fourth side surface.

9. 9. The multilayer ceramic capacitor according to claim 8, wherein the thin film layer is directly connected to at least one of the first internal electrode layer and the second internal electrode layer.

10. The first external electrode is a first fired electrode layer comprising a metal component and a dielectric material disposed on the first major surface or the second major surface; a first base electrode layer that is arranged so as to be connected to the first internal electrode layer and that covers a part of the first fired electrode layer, The second external electrode is a second fired electrode layer comprising a metal component and a dielectric material disposed on the first major surface or the second major surface; 7. The multilayer ceramic capacitor according to claim 6, further comprising: a second base electrode layer disposed so as to be connected to said second internal electrode layer and covering a part of said second fired electrode layer.

11. 11. The multilayer ceramic capacitor according to claim 10, wherein each of the first fired electrode layer and the second fired electrode layer is discontinuously arranged in the length direction or the width direction.

12. The multilayer ceramic capacitor according to claim 10 , wherein the first fired electrode layer and the second fired electrode layer are disposed on the first side surface, the second side surface, the third side surface, and the fourth side surface, respectively.