Semiconductor memory device

Abstract

This semiconductor memory device (MD) includes memory cells (11) and a write circuit (2). The memory cell includes P-type drive transistors (TPM0, TPM1), N-type load transistors (TNM0, TNM1), and P-type access transistors (TPM2, TPM3) connected to a bit line pair (BL, BLB). The write circuit (2) includes a column selection circuit (5) having P-type transistors (TP0, TP1), and a pre-discharge circuit (4) having N-type transistors (TN0, TN1).

Description

semiconductor memory device

[0001] The present disclosure relates to a semiconductor memory device, and more particularly to an SRAM (Static Random Access Memory).

[0002] SRAM is widely used as one of the main memories mounted in semiconductor integrated circuit devices.

[0003] As a conventional technique, for example, Patent Document 1 discloses a semiconductor memory device in which, among the transistors constituting an SRAM memory cell, a transfer gate (access transistor) is constituted by a P-type transistor.

[0004] JP 2009-176407 A

[0005] However, while the prior art including Patent Document 1 shows a circuit diagram of a memory cell in which the transfer gate is composed of a P-type transistor, it does not disclose peripheral circuits of an SRAM that uses this memory cell.

[0006] This disclosure relates to peripheral circuits of an SRAM that uses SRAM memory cells that use P-type transistors as access transistors, and in particular to circuits related to writing to the SRAM.

[0007] In a first aspect of the present disclosure, a semiconductor memory device includes a memory cell and a write circuit, and the memory cell includes a first P-type transistor having a gate connected to a first node, a source connected to a first power supply, and a drain connected to a second node; a first N-type transistor having a gate connected to the first node, a source connected to a second power supply, and a drain connected to the second node; a second P-type transistor having a gate connected to the second node, a source connected to the first power supply, and a drain connected to the first node; a second N-type transistor having a gate connected to the second node, a source connected to the second power supply, and a drain connected to the first node; and a third P-type transistor provided between the first node and a first bit line, the gate of which is connected to a word line, and a fourth P-type transistor provided between the first node and a second bit line, the gate of which is connected to the word line; and the write circuit comprises a column selection circuit having a fifth P-type transistor provided between the first bit line and the first power supply and a sixth P-type transistor provided between the second bit line and the first power supply, and a pre-discharge circuit having a third N-type transistor provided between the first bit line and the second power supply and a fourth N-type transistor provided between the second bit line and the second power supply.

[0008] According to the present disclosure, a peripheral circuit for an SRAM is provided that uses an SRAM memory cell that uses a P-type transistor as an access transistor.

[0009] FIG. 1 is a diagram showing an example of the configuration of a memory cell array constituting a semiconductor memory device according to a first embodiment; FIG. 2 is a diagram showing an example of the configuration of a write circuit constituting a semiconductor memory device according to the first embodiment; FIG. 3 is a timing chart showing an example of the operation of a semiconductor memory device according to the first embodiment; FIG. 4 is a diagram showing a modified example of a memory cell array according to the first embodiment; FIG. 5 is a diagram showing a modified example of a write circuit constituting a semiconductor memory device according to a second embodiment; FIG. 6 is a timing chart showing an example of the operation of a semiconductor memory device according to the second embodiment; FIG. 7 is a diagram for explaining a write assist operation of a semiconductor memory device according to the second embodiment;

[0010] Hereinafter, embodiments will be described with reference to the drawings. In the following description, a signal line (node) and a signal passing through the signal line (node) may be described using the same reference numeral. Similarly, a power supply node and a voltage supplied to the power supply node may be described using the same reference numeral. In this disclosure, the term "connection" is used to refer to a direct connection between two elements, as well as an indirect connection between two elements via an element such as a transistor.

[0011] 1 and 2 show an example of the configuration of a semiconductor memory device MD according to this embodiment. The semiconductor memory device MD according to this embodiment is a single column memory device, and includes a memory cell array 1 shown in FIG. 1 and a write circuit 2 shown in FIG.

[0012] [Memory Cell Array] In this embodiment, the memory cell array 1 includes a plurality of memory cells 11 arranged in an array of n rows (n is a natural number) by m sets (m is a natural number). The memory cells 11 in each row are connected to different word lines WLB[0] to WLB[n-1]. In other words, in this example, the memory cell array 1 is configured by n word lines WLB[0] to WLB[n-1] and n×m memory cells 11. Note that FIG. 1 illustrates one set of the m sets of memory cells 11. In the following description, when the word lines WLB[0] to WLB[n-1] are not distinguished from one another, they may be simply referred to as "word lines WLB."

[0013] [Memory Cell] The memory cell 11 includes P-type drive transistors TPM0 and TPM1, N-type load transistors TNM0 and TNM1, and P-type access transistors TPM2 and TPM3.

[0014] The drive transistor TPM0 (corresponding to a first P-type transistor) has a gate connected to a node DB (corresponding to a first node), a source connected to a power supply VDD (corresponding to a first power supply), and a drain connected to a node D (corresponding to a second node). The load transistor TNM0 (corresponding to a first N-type transistor) has a gate connected to the node DB, a source connected to a ground VSS (corresponding to a second power supply), and a drain connected to the node D. In other words, the drive transistor TPM0 and the load transistor TNM0 are connected in series between the power supply VDD and the ground VSS.

[0015] The drive transistor TPM1 (corresponding to a second P-type transistor) has a gate connected to node D, a source connected to the power supply VDD, and a drain connected to node DB. The load transistor TNM1 (corresponding to a second N-type transistor) has a gate connected to node D, a source connected to ground VSS, and a drain connected to node DB. That is, the drive transistor TPM1 and the load transistor TNM1 are connected in series between the power supply VDD and ground VSS. The drive transistors TPM0 and TPM1 and the load transistors TNM0 and TNM1 form a latch.

[0016] The access transistor TPM2 (corresponding to a third P-type transistor) is provided between the node D and the bit line BL (corresponding to a first bit line), and has its gate connected to the word line WLB. The access transistor TPM3 (corresponding to a fourth P-type transistor) is provided between the node DB and the bit line BLB (corresponding to a second bit line), and has its gate connected to the word line WLB. In the following description, the pair of the bit line BL and the bit line BLB may be referred to as the "bit line pair BL, BLB."

[0017] [Write Circuit] A write circuit 2 shown in Fig. 2 is connected to the bit line pair BL, BLB of the memory cell array 1. A write circuit 2 is provided for each set of memory cell arrays 1. That is, in this example, m write circuits 2 are provided for m sets of memory cells 11. Note that Fig. 2 illustrates one write circuit 2.

[0018] The write circuit 2 includes a pull-down circuit 3 , a pre-discharge circuit 4 , a column selection circuit 5 , and a write driver 6 .

[0019] [Pull-down Circuit] When one of the bit lines BL and BLB is at 'H' (high level), the pull-down circuit 3 sets the other bit line to 'L' (low level). In the following, a high-level signal will be simply referred to as 'H', and a low-level signal will be simply referred to as 'L'.

[0020] In this example, the pull-down circuit 3 includes N-type transistors TNW0 and TNW1. The transistor TNW0 is provided between the bit line BL and ground VSS, and has its gate connected to the bit line BLB. The transistor TNW1 is provided between the bit line BLB and ground VSS, and has its gate connected to the bit line BL.

[0021] [Pre-discharge Circuit] The pre-discharge circuit 4 includes N-type transistors TNEQ, TN0, and TN1. The transistor TNEQ (corresponding to a fifth N-type transistor) is provided between the bit line BL and the bit line BLB. The transistor TN0 (corresponding to a third N-type transistor) is provided between the bit line BL and ground VSS. The transistor TN1 (corresponding to a fourth N-type transistor) is provided between the bit line BLB and ground VSS. A pre-discharge control signal NPCG is supplied to the gates of the transistors TNEQ, TN0, and TN1.

[0022] When the memory cell 11 is in an inactive state, if the pre-discharge control signal NPCG goes high, the pre-discharge circuit 4 turns on the transistors TN0 and TN1 to discharge the bit line pair BL and BLB to low.

[0023] [Column Selection Circuit] The column selection circuit 5 includes P-type transistors TP0 and TP1. The transistor TP0 (corresponding to the fifth P-type transistor) is provided between the power supply VDD and the bit line BL, and has its gate supplied with the output signal WC0 of the write driver 6. The transistor TP1 (corresponding to the sixth P-type transistor) is provided between the power supply VDD and the bit line BLB, and has its gate supplied with the output signal WC1 of the write driver 6.

[0024] In the column selection circuit 5, either the transistor TP0 or TP1 is turned on based on the output signals WC0 and WC1 of the write driver 6, and the column selection circuit 5 selects the bit line (BL or BLB) to be written to.

[0025] [Write Driver] The write driver 6 is in a write state when the write control signal WRITE is 'H', and outputs output signals WC0 and WC1 that select the bit line (BL or BLB) to be written to in accordance with the write data WD. Here, the output signals WC0 and WC1 are signals that are not 'L' (selected state) at the same time.

[0026] In this example, the write driver 6 includes two-input NAND circuits 60 and 61 and an inverter 62. The NAND circuit 60 receives an inverted signal of the write data WD and a write control signal WRITE as inputs, and outputs an output signal WC0. The NAND circuit 61 receives the write data WD and the write control signal WRITE as inputs, and outputs an output signal WC1.

[0027] (Data Write Operation) Next, the operation of writing data to the memory cell 11 will be described with reference to FIG. 3. In the following description, for convenience, only the reference symbols of signals may be used. For example, the signal on the bit line BL may be simply described using only the reference symbol "BL." The same applies to other signals, and also to the modified examples and other embodiments described below.

[0028] (Operation Example 1-1) First, a write operation from D='L' to 'H' and DB='H' to 'L' to the memory cell 11 in the upper row of FIG. 1 will be described (see the left side of FIG. 3).

[0029] Before the start of the write operation, WLB[n-1] = NPCG = WD = 'H'. As a result, the pre-discharge circuit 4 is in a pre-discharged state (transistors TN0 and TN1 are on), and BL = BLB = 'L'. Also, WRITE = 'L', and transistors TP0 and TP1 are off. In the memory cell 11, the drive transistor TPM1 and load transistor TNM0 are on, and D = 'L' and DB = 'H'.

[0030] Now, the operation of switching to the write mode is performed.

[0031] Specifically, when WLB[n-1] is set to "L", the access transistors TPM2 and TPM3 are turned on, allowing the memory cell 11 to access the bit line pair BL and BLB.

[0032] By setting NPCG to 'L', the transistors TN0 and TN1 of the pre-discharge circuit 4 are turned off, and the discharge (fixed to 'L') of the bit line pair BL and BLB is released.

[0033] By setting WD='L' and WRITE='H', the transistor TP0 of the column selection circuit 5 is turned on and BL='H'. At this time, the transistor TP1 of the column selection circuit 5 is turned off and the transistor TNW1 of the pull-down circuit 3 is turned on, so BLB remains at 'L'.

[0034] When BL='H' with the access transistors TPM2 and TPM3 turned on, D is rewritten from 'L' to 'H' and DB is rewritten from 'H' to 'L'. Then, when writing to the memory cell 11 is completed, WLB[n-1] is set to 'H'. This turns off the access transistors TPM2 and TPM3, and D='H' and DB='L' are maintained.

[0035] (Operation Example 1-2) Next, a write operation from D='H' to 'L' and DB='L' to 'H' for the memory cell 11 in the upper row of Fig. 1 will be described (see the right side of Fig. 3). Here, the differences from the above "Operation Example 1-1" will be mainly described.

[0036] In the operation of switching to the write mode, as in Operation Example 1-1, when WLB[n-1] is set to "L", the access transistors TPM2 and TPM3 are turned on. Also, when WD is set to "H" and WRITE is set to "H", the transistor TP1 of the column selection circuit 5 is turned on, BLB is set to "H", and BL is set to "L".

[0037] When BLB='H' with the access transistors TPM2 and TPM3 turned on, DB is rewritten from 'L' to 'H' and D is rewritten from 'H' to 'L'. Then, when writing to the memory cell 11 is completed, WLB[n-1] is set to 'H'. This turns off the access transistors TPM2 and TPM3, and D='L' and DB='H' are maintained.

[0038] --Modification 1-- Here, a modification of the semiconductor memory device MD according to the first embodiment will be described. The semiconductor memory device MD of this modification is a multi-column type.

[0039] Fig. 4 is a diagram of this modified example corresponding to Fig. 1, and Fig. 5 is a diagram of this modified example corresponding to Fig. 2. In Fig. 4, components corresponding to those in Fig. 1 are assigned the same reference numerals as in Fig. 1. Similarly, in Fig. 5, components corresponding to those in Fig. 2 are assigned the same reference numerals as in Fig. 2. Here, differences from the first embodiment (single column) will be mainly described.

[0040] [Memory Cell Array] In this modification, the memory cell array 1 includes a plurality of memory cells 11 arranged in an array of n rows (n is a natural number) × c columns (c is a natural number) × m sets (m is a natural number). Note that FIG. 4 illustrates one set of the m sets of memory cells 11.

[0041] 4, the memory cells 11 in each row are connected to different word lines WLB[0] to WLB[n-1]. The memory cells 11 in each column are connected to different bit line pairs BL[0] to BL[c-1], BLB[0] to BLB[c-1]. That is, the memory cell array 1 is composed of n word lines WLB[0] to WLB[n-1], c bit line pairs BL[0] to BL[c-1], BLB[0] to BLB[c-1], and n×c×m memory cells 11.

[0042] In the following description, as with the word line WLB, when the bit lines BL[0] to BL[c-1] are not distinguished from one another, they may be simply referred to as "bit lines BL." The same applies to the bit line BLB and the bit line pair BL, BLB.

[0043] 5, in the write circuit 2 of this modification, each column is provided with a pull-down circuit 3, a pre-discharge circuit 4, and a column selection circuit 5. The pull-down circuit 3 and the pre-discharge circuit 4 have the same configurations as those in the first embodiment (for example, the configurations in FIG. 2).

[0044] [Column Selection Circuit] In this modification, compared to the single-column write circuit 2 shown in Fig. 2, a bit line address signal NCAD[0:c-1] is added to select a memory cell column to be written to. In addition, with the addition of the bit line address signal NCAD[0:c-1], the configuration of the column selection circuit 5 is different from that shown in Fig. 2.

[0045] In this modification, the column selection circuit 5 has a function of selecting a column to which data is to be written, in addition to a function of selecting a bit line (BL or BLB) to be written. Specifically, data is written to the memory cells 11 connected to the bit line pair BL, BLB of the column (0 to c-1) selected by the bit line address signal NCAD[0:c-1].

[0046] In this modification, the column selection circuit 5 includes, in addition to the above-mentioned transistors TP0 and TP1, P-type transistors TP2 and TP3 and N-type transistors TN2 and TN3.

[0047] The source of transistor TP2 is connected to power supply VDD and the drain is connected to the gate of transistor TP0. The source of transistor TN2 is connected to bit line address signal NCAD and the drain is connected to the gate of transistor TP0. The output signal WC0 of write driver 6 is applied to the gates of transistors TP2 and TN2.

[0048] The source of transistor TP3 is connected to power supply VDD and the drain is connected to the gate of transistor TP1. The source of transistor TN3 is connected to bit line address signal NCAD and the drain is connected to the gate of transistor TP1. The output signal WC1 of write driver 6 is applied to the gates of transistors TP3 and TN3.

[0049] [Write Driver] In this modification, an inverter 64 is provided between the NAND circuit 60 and the output node WC0, and an inverter 65 is provided between the NAND circuit 61 and the output node WC1 in the write driver 6. As a result, the polarities of the output signals WC0 and WC1 are inverted from those in the first embodiment.

[0050] (Data write operation) The write operation of this modified example differs from that of the first embodiment described above in that data is written to the memory cell 11 connected to the bit line pair BL, BLB of the column (0 to c-1) selected by the bit line address signal NCAD[0:c-1].

[0051] Other operations are the same as those described above with reference to Figure 3. Specifically, a switchover operation from the state before the start of the write operation to the write mode is performed. Then, WD is set to 'L' or 'H' and WRITE is set to 'H', thereby performing a write to the memory cell 11. After that, when the write is completed, WLB[n-1] is set to 'H' and the written data is retained.

[0052] Second Embodiment Here, a semiconductor memory device MD according to a second embodiment will be described.

[0053] The semiconductor memory device MD of this embodiment is a single column, and the configuration of the memory cell array 1 is the same as that of the first embodiment (for example, the configuration in FIG. 1).

[0054] Fig. 6 is a diagram of this embodiment corresponding to Fig. 2. In Fig. 6, components corresponding to those in Fig. 2 are assigned the same reference numerals as in Fig. 2. Here, differences from the first embodiment will be mainly described.

[0055] This embodiment differs from the first embodiment in that the write circuit 2 includes a voltage control circuit 7 in addition to a pull-down circuit 3, a pre-discharge circuit 4, a column selection circuit 5 and a write driver 6.

[0056] Also, the second embodiment differs from the first embodiment in that the bit line BL is connected to the internal power supply line WVDD via a transistor TP0, and the bit line BLB is connected to the internal power supply line WVDD via a transistor TP1. In other words, the internal power supply line WVDD supplies a high-level voltage to the bit line pair BL, BLB.

[0057] [Voltage Control Circuit] The voltage control circuit 7 controls the voltage of the internal power supply line WVDD via the capacitance element NCAP. More specifically, the voltage control circuit 7 has a function of making the high-potential side bit line (BL or BLB) higher in potential than the power supply voltage VDD in response to the boost control signal WTA by the action of the capacitance element NCAP connected to the internal power supply line WVDD.

[0058] Between the power supply VDD and the internal power supply line WVDD, there is provided a P-type transistor TPU (corresponding to a seventh P-type transistor) that is turned on / off by a boost control signal WTA. In other words, the P-type transistor TPU has the function of controlling the voltage of the internal power supply line WVDD to the power supply voltage VDD.

[0059] A buffer 71 for delaying the boost control signal WTA is provided between the capacitive element NCAP and the boost control signal WTA. The output of the buffer 71 and the capacitive element NCAP are connected at a node WACP.

[0060] 6 shows an example in which the capacitance element NCAP is configured with an N-type transistor (corresponding to a sixth N-type transistor). However, the capacitance element NCAP is not limited to an N-type transistor. For example, the capacitance element NCAP may be configured with a P-type transistor, or may be configured with elements other than transistors, wiring, etc.

[0061] (Data Write Operation) Next, the operation of writing data to the memory cell 11 will be described with reference to Fig. 7. This embodiment differs from the first embodiment in that there is a boost mode period between the operation of switching to the write mode and the writing of data to the memory cell 11. Here, the differences from the first embodiment will be mainly described.

[0062] (Operation Example 2-1) First, a write operation from D='L' to 'H' and DB='H' to 'L' to the memory cell 11 in the upper row of FIG. 1 will be described (see the left side of FIG. 7).

[0063] As in FIG. 3, a switching operation is performed from the state before the start of the write operation to the write mode.

[0064] Specifically, in the operation of switching to the write mode, WTA is set to 'L', the transistor TPU is turned on, and the voltage of the internal power supply line WVDD becomes VDD. Furthermore, WLB[n-1] is set to 'L', NPCG is set to 'L', WD is set to 'L', and WRITE is set to 'H', so that BL becomes 'H' and BLB remains 'L'.

[0065] In the next boost mode, when WTA goes high, the transistor TPU is turned off, disconnecting the internal power supply line WVDD and the bit line BL from the power supply VDD and putting them into a floating state. Then, after a delay time set by the buffer 71 has elapsed since WTA went high, WACP goes from low to high, causing the capacitance element NCAP to charge the wiring capacitance of the internal power supply line WVDD, etc., and raising the voltages of the internal power supply line WVDD and the bit line BL above the power supply voltage VDD. This increases the conductance, i.e., the driving capability, of the access transistor TPM2, increasing the amount of current flowing from the bit line BL to the node D, and raising the voltage of the node D more than in the configuration of the first embodiment.

[0066] Then, when the potential of D rises to the threshold value of the load transistor TNM1, the load transistor TNM1 turns on, and DB is rewritten from 'H' to 'L'. Furthermore, the drive transistor TPM0 turns on, and D is rewritten from 'L' to 'H'. When writing to the memory cell 11 is completed, WLB[n-1] is set to 'H'. This turns off the access transistors TPM2 and TPM3, and D='H' and DB='L' are maintained.

[0067] The effects of providing the voltage control circuit 7 of this embodiment will be described in detail with reference to Fig. 8. In Fig. 8, BL is indicated by a thick line and BLB is indicated by a thin line. Also, D is indicated by a thick line and DB is indicated by a thin line. The same applies to Fig. 13, which will be described later.

[0068] First, when the conductance of the access transistor TPM2 is set to a sufficient value, the memory cell 11 operates without any problems as described in the first embodiment (see "Normal Operation" in FIG. 8).

[0069] On the other hand, if the conductance (driving capability) of the access transistor TPM2 is relatively low, the access transistor TPM2 turns on, but the amount of current flowing from the bit line BL to the node D is not sufficiently ensured. As a result, the voltage of D may not rise to the threshold voltage of the load transistor TNM1, and the load transistor TNM1 may not turn on. In this case, it is not possible to rewrite D from 'L' to 'H' and DB from 'H' to 'L' (see "Malfunction" in FIG. 8).

[0070] In such a case, the conductance, i.e., the driving capability, of the access transistor TPM2 can be increased by providing the voltage control circuit 7. This increases the amount of current flowing from the bit line BL to the node D, and the voltage of the node D becomes higher than when the voltage control circuit 7 is not provided, making it easier to turn on the load transistor TNM1. In other words, providing the voltage control circuit 7 assists writing to the memory cell 11, enabling normal writing (see "During write assist operation" in FIG. 8).

[0071] (Operation Example 2-2) Next, a write operation from D='H' to 'L' and DB='L' to 'H' in the memory cell 11 in the upper row of Fig. 1 will be described (see the right side of Fig. 7). Here, the differences from the above "Operation Example 2-1" will be mainly described.

[0072] In the operation of switching to the write mode, similarly to the operation example 2-1, WTA is set to 'L', the transistor TPU is turned on, and the voltage of the internal power supply line WVDD becomes VDD. Also, in addition to WLB[n-1]='L', NPCG='L', and WRITE='H', WD='H' is set, so that BLB becomes 'H' and BL remains 'L'.

[0073] In the next boost mode operation, when WTA goes high, the transistor TPU is turned off, disconnecting the internal power supply line WVDD and the bit line BLB from the power supply VDD and putting them into a floating state. Then, after a delay time set by the buffer 71 has elapsed since WTA went high, WACP goes from low to high, causing the capacitance element NCAP to charge the wiring capacitance of the internal power supply line WVDD, and the voltages of the internal power supply line WVDD and the bit line BLB to rise above the power supply voltage VDD. This increases the conductance, i.e., the driving capability, of the access transistor TPM3, increasing the amount of current flowing from the bit line BLB to the node DB, and raising the voltage of the node DB more than in the configuration of the first embodiment.

[0074] Then, when the potential of DB rises to the threshold value of the load transistor TNM0, the load transistor TNM0 turns on, and D is rewritten from 'H' to 'L'. Furthermore, the drive transistor TPM1 turns on, and DB is rewritten from 'L' to 'H'. When writing to the memory cell 11 is completed, WLB[n-1] is set to 'H'. This turns off the access transistors TPM2 and TPM3, and D='L' and DB='H' are maintained.

[0075] --Modification 2-- Here, a modification of the semiconductor memory device MD according to the second embodiment will be described.

[0076] The semiconductor memory device MD of this modification is a multi-column type, and the configuration of the memory cell array 1 is the same as that of the first modification of the first embodiment (for example, the configuration in FIG. 4).

[0077] Fig. 9 is a diagram of this modified example, corresponding to Fig. 6. In Fig. 9, the same reference numerals are used for the components corresponding to Fig. 6. Here, the differences from the second embodiment (single column) will be mainly described.

[0078] 9, in the write circuit 2 of this modification, each column is provided with a pull-down circuit 3, a pre-discharge circuit 4, and a column selection circuit 5. The pull-down circuit 3 and the pre-discharge circuit 4 are the same as those in the second embodiment (for example, the configuration in FIG. 6).

[0079] [Column Selection Circuit] Compared to the single-column write circuit 2 shown in FIG. 6, this modification adds a bit line address signal NCAD[0:c-1] to select a memory cell column to be written to. The addition of the bit line address signal NCAD[0:c-1] also changes the configuration of the column selection circuit 5. The configuration shown in FIG. 9 is the same as the column selection circuit 5 of the first modification of the first embodiment (see FIG. 5) and has the same functions. That is, the column selection circuit 5 has the function of selecting a bit line (BL or BLB) to be written to, as well as the function of selecting a column from multiple columns to which data is to be written.

[0080] [Write Driver] In this modification, an inverter 64 is provided between the NAND circuit 60 and the output node WC0, and an inverter 65 is provided between the NAND circuit 61 and the output node WC1 in the write driver 6. As a result, the polarities of the output signals WC0 and WC1 are inverted from those in the second embodiment.

[0081] (Data write operation) The write operation of this modified example differs from the second embodiment in that data is written to the memory cell 11 connected to the bit line pair BL, BLB of the column (0 to c-1) selected by the bit line address signal NCAD[0:c-1].

[0082] Other operations are the same as those described above with reference to FIG. 7, and a switching operation is performed from the state before the start of the write operation to the write mode. Then, after the operation in the boost mode, writing to the memory cell 11 is performed. After that, when writing is completed, WLB[n-1] is set to 'H' and the written data is retained.

[0083] Third Embodiment Here, a semiconductor memory device MD according to a third embodiment will be described. The semiconductor memory device MD of this embodiment is a single column.

[0084] Fig. 10 is a diagram of this embodiment corresponding to Fig. 1, and Fig. 11 is a diagram of this embodiment corresponding to Fig. 6. In Fig. 10, components corresponding to those in Fig. 1 are assigned the same reference numerals. Similarly, in Fig. 11, components corresponding to those in Fig. 6 are assigned the same reference numerals. Here, differences from the previous embodiments (particularly the second embodiment) will be mainly described.

[0085] 10 , this embodiment differs from the first and second embodiments in that the sources of the load transistors TNM0 and TNM1 are connected to a common internal ground line MCVSS (corresponding to an internal power supply line) in each memory cell 11 that constitutes the memory cell array 1. The voltage of the internal ground line MCVSS is controlled by the write circuit 2.

[0086] As shown in FIG. 11, the configuration of the voltage control circuit 7 in this embodiment is different from that in the second embodiment.

[0087] [Voltage Control Circuit] The voltage control circuit 7 controls the voltage of the internal ground line MCVSS connected to the memory cell 11. Furthermore, when writing to the memory cell, the voltage control circuit 7 is configured to make the potential of the internal ground line MCVSS higher than the ground VSS.

[0088] The voltage control circuit 7 includes P-type transistors TPU, TPWA0, and TPWA1, and an N-type transistor TND.

[0089] The transistor TPU has a source connected to the power supply VDD, a drain connected to the sources of the transistors TPWA0 and TPWA1, and a gate to which a boost control signal NWTA is applied. The boost control signal NWTA has a polarity that is inverted from that of the boost control signal WTA in the second embodiment.

[0090] The sources and drains of the transistors TPWA0 and TPWA1 are connected to each other. The gate of the transistor TPWA0 is connected to an output node WC0 of the write driver 6, and the gate of the transistor TPWA1 is connected to an output node WC1 of the write driver 6.

[0091] The transistor TND (corresponding to a fifth N-type transistor) has a gate connected to the power supply VDD, a source connected to the ground VSS, and a drain connected to the internal ground line MCVSS and the drains of the transistors TPWA0 and TPWA1.

[0092] (Data Write Operation) Next, the data write operation to the memory cell 11 will be described with reference to Fig. 12. Here, the differences from the second embodiment (see Fig. 7) will be mainly described.

[0093] (Operation Example 3-1) First, a write operation from D='L' to 'H' and DB='H' to 'L' to the memory cell 11 in the upper row of FIG. 10 will be described (see the left side of FIG. 12).

[0094] As in FIG. 7, a switching operation is performed from the state before the start of the write operation to the write mode.

[0095] Specifically, in the operation of switching to the write mode, NWTA is set to 'H', and the transistor TPU is turned off. The transistor TND is turned on, so the voltage of the internal ground line MCVSS becomes VSS.

[0096] By setting WD='L' and WRITE='H', the transistor TP0 is turned on, and BL='H'. At this time, the transistor TP1 is turned off, so the transistor TNW1 of the pull-down circuit 3 is turned on, and BLB='L'.

[0097] In the next boost mode, when NWTA goes low, transistor TPU is turned on, which in turn turns on transistor TPWA0. This causes the voltage of internal ground line MCVSS to be divided by the on-resistances of transistors TPU, TPWA0, and TND, and rises from ground potential VSS. This reduces the conductance, i.e., the driving capability, of load transistor TNM0. This causes the voltage at node D to be higher than when voltage control circuit 7 is not provided (e.g., in the first embodiment).

[0098] Then, when the potential of D rises to the threshold value of the load transistor TNM1, the load transistor TNM1 turns on, and DB is rewritten from 'H' to 'L'. Furthermore, the drive transistor TPM0 turns on, and D is rewritten from 'L' to 'H'. When writing to the memory cell 11 is completed, WLB[n-1] is set to 'H'. This turns off the access transistors TPM2 and TPM3, and D='H' and DB='L' are maintained.

[0099] The effects of providing the voltage control circuit 7 of this embodiment will be described with reference to FIG.

[0100] First, when the conductance of the access transistor TPM2 is set to a sufficient value, the memory cell 11 operates without any problems as described in the first embodiment (see "Normal Operation" in FIG. 13).

[0101] On the other hand, if the conductance (driving capability) of the access transistor TPM2 is relatively low, the access transistor TPM2 turns on, but the amount of current flowing from the bit line BL to the node D is not sufficiently ensured. As a result, the voltage of D may not rise to the threshold voltage of the load transistor TNM1, and the load transistor TNM1 may not turn on. In this case, it is not possible to rewrite D from 'L' to 'H' and DB from 'H' to 'L' (see "During Malfunction" in FIG. 13).

[0102] In such a case, by providing the voltage control circuit 7 and raising the internal ground line MCVSS, i.e., the source voltage of the load transistor TNM0, the voltage at node D becomes higher than when the voltage control circuit 7 is not provided, making it easier to turn on the load transistor TNM1. In other words, by providing the voltage control circuit 7, writing to the memory cell 11 is assisted, and normal writing can be achieved (see "During write assist operation" in FIG. 13).

[0103] (Operation Example 3-2) Next, a write operation from D='H' to 'L' and DB='L' to 'H' for the memory cell 11 in the upper row of Fig. 10 will be described (see the right side of Fig. 12). Here, the differences from the above "Operation Example 3-1" will be mainly described.

[0104] In the operation of switching to the write mode, as in the operation example 3-1, NWTA is set to 'H' and the transistor TPU is turned off. Since the transistor TND is on, the voltage of the internal ground line MCVSS becomes VSS.

[0105] By setting WD="H" and WRITE="H", the transistor TP1 is turned on and BLB="H". At this time, the transistor TP0 is turned off, so the transistor TNW0 of the pull-down circuit 3 is turned on and BL="L".

[0106] In the next boost mode, when NWTA goes low, transistor TPU is turned on, which in turn turns on transistor TPWA1. As a result, the voltage of internal ground line MCVSS is divided by the on-resistances of transistors TPU, TPWA1, and TND, and rises from ground potential VSS. This reduces the conductance, i.e., the driving capability, of load transistor TNM1. This results in a higher voltage at node DB than in the case where voltage control circuit 7 is not provided (e.g., the first embodiment).

[0107] Then, when the potential of DB rises to the threshold value of the load transistor TNM0, the load transistor TNM0 turns on, and D is rewritten from 'H' to 'L'. Furthermore, the drive transistor TPM1 turns on, and DB is rewritten from 'L' to 'H'. When writing to the memory cell 11 is completed, WLB[n-1] is set to 'H'. This turns off the access transistors TPM2 and TPM3, and D='L' and DB='H' are maintained.

[0108] --Modification 3-- Here, a modification of the semiconductor memory device MD according to the third embodiment will be described.

[0109] The semiconductor memory device MD of this modification is a multi-column type.

[0110] Fig. 14 is a diagram of this embodiment corresponding to Fig. 10, and Fig. 15 is a diagram of this embodiment corresponding to Fig. 11. In Fig. 14, components corresponding to those in Fig. 10 are assigned the same reference numerals. Similarly, in Fig. 15, components corresponding to those in Fig. 11 are assigned the same reference numerals. Here, the differences from the third embodiment (single column) and the modified example of the second embodiment (multi-column) will be mainly described.

[0111] [Memory Cell Array] In this modification, the memory cell array 1 includes a plurality of memory cells 11 arranged in an array of n rows (n is a natural number) × c columns (c is a natural number) × m sets (m is a natural number). Note that FIG. 14 illustrates one set of the m sets of memory cells 11.

[0112] 14, the memory cells 11 in each column are connected to different bit line pairs BL[0] to BL[c-1], BLB[0] to BLB[c-1] and internal ground lines MCVSS[0] to MCVSS[c-1]. For example, the memory cells 11 in the 0th column are connected to a common bit line pair BL[0], BLB[0] and a common internal ground line MCVSS[0]. The same applies to the 1st to (c-1)th columns.

[0113] 15, in the write circuit 2 of this modification, each column is provided with a pull-down circuit 3, a pre-discharge circuit 4, a column selection circuit 5, and a voltage control circuit 7. The configurations of the pull-down circuit 3, the pre-discharge circuit 4, and the write driver 6 are the same as those of the modification of the second embodiment (for example, the configuration of FIG. 9).

[0114] [Column Selection Circuit] In this modification, compared to the single-column write circuit 2 shown in FIG. 11 , a bit line address signal NCAD[0:c−1] is added to select a memory cell column to be written to. The addition of the bit line address signal NCAD[0:c−1] also changes the configuration of the column selection circuit 5. The configuration of the column selection circuit 5 shown in FIG. 15 is substantially the same as that of the column selection circuit 5 of Modification 2 of the second embodiment (see FIG. 9 ), and has similar functions. That is, in this modification, the column selection circuit 5 also has the function of selecting a bit line (BL or BLB) to be written to, as well as the function of selecting a column from multiple columns to which data is to be written.

[0115] In this modification, the gates of the transistors TP0 and TPWA0, which are provided in the same column, are connected to each other, and the gates of the transistors TP1 and TPWA1 are connected to each other.

[0116] The configuration of the voltage control circuit 7 shown in FIG. 15 is similar to the configuration of the third embodiment (see FIG. 11), and has similar functions.

[0117] (Data write operation) The write operation of this modified example differs from the third embodiment in that data is written to the memory cell 11 connected to the bit line pair BL, BLB of the column (0 to c-1) selected by the bit line address signal NCAD[0:c-1].

[0118] Other operations are the same as those described above with reference to FIG. 12, and a switching operation is performed from the state before the start of the write operation to the write mode. Then, after the operation in the boost mode, writing to the memory cell 11 is performed. After that, when writing is completed, WLB[n-1] is set to 'H' and the written data is retained.

[0119] It should be noted that the technology disclosed herein is not limited to the configurations described in the above embodiments, and can be applied to embodiments in which appropriate modifications, substitutions, additions, omissions, etc. Furthermore, the components described in the above embodiments can be combined to create new embodiments.

[0120] The present disclosure is extremely useful because it can provide a peripheral circuit for an SRAM that uses an SRAM memory cell that uses a P-type transistor as the access transistor.

[0121] MD Semiconductor memory device 1 Memory cell array 2 Write circuit 4 Pre-discharge circuit 5 Column selection circuit 7 Voltage control circuit 11 Memory cell BL Bit line (first bit line) BLB Bit line (second bit line) D Node (second node) DB Node (first node) MCVSS Internal ground line (internal power supply line) NCAP Capacitor element TN0 Transistor (third N-type transistor) TN1 Transistor (fourth N-type transistor) TNEQ Transistor (fifth N-type transistor) TNM0 Load transistor (first N-type transistor) TNM1 Load transistor (second N-type transistor) TP0 Transistor (fifth P-type transistor) TP1 Transistor (sixth P-type transistor) TPM0 Drive transistor (first P-type transistor) TPM1 Drive transistor (second P-type transistor) TPM2 Access transistor (third P-type transistor) TPM3 Access transistor (fourth P-type transistor) TPU Transistor (seventh P-type transistor) VDD Power supply (first power supply) VSS Ground (second power supply) WLB Word line WVDD Internal power supply line

Claims

1. a memory cell and a write circuit; The memory cell a first P-type transistor having a gate connected to a first node, a source connected to a first power supply, and a drain connected to a second node; a first N-type transistor having a gate connected to the first node, a source connected to a second power supply, and a drain connected to the second node; a second P-type transistor having a gate connected to the second node, a source connected to the first power supply, and a drain connected to the first node; a second N-type transistor having a gate connected to the second node, a source connected to the second power supply, and a drain connected to the first node; a third P-type transistor provided between the second node and the first bit line, the gate of which is connected to the word line; a fourth P-type transistor provided between the first node and a second bit line, the gate of which is connected to the word line; The write circuit a column selection circuit including a fifth P-type transistor provided between the first bit line and the first power supply, and a sixth P-type transistor provided between the second bit line and the first power supply; a pre-discharge circuit having a third N-type transistor provided between the first bit line and the second power supply, and a fourth N-type transistor provided between the second bit line and the second power supply. A semiconductor memory device characterized by:

2. 2. The semiconductor memory device according to claim 1, The pre-discharge circuit includes a fifth N-type transistor provided between the first bit line and the second bit line. A semiconductor memory device characterized by:

3. 2. The semiconductor memory device according to claim 1, a memory cell array configured with a plurality of columns, each of which is a unit of memory cells connected to a common first bit line and a common second bit line; The column selection circuit is configured to operate the fifth P-type transistor and / or the sixth P-type transistor of a column to which data is to be written, selected from the plurality of columns. A semiconductor memory device characterized by:

4. a memory cell and a write circuit; The memory cell a first P-type transistor having a gate connected to a first node, a source connected to a first power supply, and a drain connected to a second node; a first N-type transistor having a gate connected to the first node, a source connected to a second power supply, and a drain connected to the second node; a second P-type transistor having a gate connected to the second node, a source connected to the first power supply, and a drain connected to the first node; a second N-type transistor having a gate connected to the second node, a source connected to the second power supply, and a drain connected to the first node; a third P-type transistor provided between the second node and the first bit line, the gate of which is connected to the word line; a fourth P-type transistor provided between the first node and a second bit line, the gate of which is connected to the word line; The write circuit a column selection circuit including a fifth P-type transistor provided between the first bit line and an internal power supply line, and a sixth P-type transistor provided between the second bit line and the internal power supply line; a pre-discharge circuit including a third N-type transistor provided between the first bit line and the second power supply, and a fourth N-type transistor provided between the second bit line and the second power supply; a voltage control circuit having a seventh P-type transistor provided between the first power supply and the internal power supply line, and a capacitance element that makes the potential of the internal power supply line higher than the first power supply when writing to the memory cell; A semiconductor memory device characterized by:

5. 5. The semiconductor memory device according to claim 4, The pre-discharge circuit includes a fifth N-type transistor provided between the first bit line and the second bit line. A semiconductor memory device characterized by:

6. 5. The semiconductor memory device according to claim 4, The capacitive element is formed of a sixth N-type transistor. A semiconductor memory device characterized by:

7. 5. The semiconductor memory device according to claim 4, a memory cell array configured with a plurality of columns, each of which is a unit of memory cells connected to a common first bit line and a common second bit line; The column selection circuit is configured to operate the fifth P-type transistor and / or the sixth P-type transistor of a column to which data is to be written, selected from the plurality of columns. A semiconductor memory device characterized by:

8. a memory cell and a write circuit; The memory cell a first P-type transistor having a gate connected to a first node, a source connected to a first power supply, and a drain connected to a second node; a first N-type transistor having a gate connected to the first node, a source connected to an internal power supply line, and a drain connected to the second node; a second P-type transistor having a gate connected to the second node, a source connected to the first power supply, and a drain connected to the first node; a second N-type transistor having a gate connected to the second node, a source connected to the internal power supply line, and a drain connected to the first node; a third P-type transistor provided between the second node and the first bit line, the gate of which is connected to the word line; a fourth P-type transistor provided between the first node and a second bit line, the gate of which is connected to the word line; The write circuit a column selection circuit including a fifth P-type transistor provided between the first bit line and the first power supply, and a sixth P-type transistor provided between the second bit line and the first power supply; a pre-discharge circuit including a third N-type transistor provided between the first bit line and a second power supply, and a fourth N-type transistor provided between the second bit line and the second power supply; a voltage control circuit including a fifth N-type transistor provided between the second power supply and the internal power supply line, and a seventh P-type transistor for setting the potential of the internal power supply line to a potential higher than that of the second power supply when writing to the memory cell; A semiconductor memory device characterized by:

9. 9. The semiconductor memory device according to claim 8, The pre-discharge circuit includes a sixth N-type transistor provided between the first bit line and the second bit line. A semiconductor memory device characterized by:

10. 9. The semiconductor memory device according to claim 8, a memory cell array configured with a plurality of columns, each of which is a unit of memory cells connected to a common first bit line and a common second bit line; The column selection circuit is configured to operate the fifth P-type transistor and / or the sixth P-type transistor of a column to which data is to be written, selected from the plurality of columns. A semiconductor memory device characterized by: