Multilayer ceramic electronic component

Abstract

Provided is a multilayer ceramic capacitor that can be reliably mounted on a wiring board and can suppress the occurrence of an acoustic noise.　This multilayer ceramic electronic component comprises: a laminate 2 including an inner layer part 11 in which dielectric layers 14 and internal electrode layers 15 are alternately laminated, the laminate 2 having two main surfaces A opposing each other in a lamination direction T, and two end surfaces C opposing each other in a length direction L; two external electrodes 3 which are connected to the internal electrode layers 15 respectively at the two end faces C, and which cover the end faces C and part of the two main surfaces A continuous therefrom and opposing each other; and two spacers 4 disposed on one of the two main surfaces A so as to sandwich the external electrodes 3 between the main surface A and the two spacers 4. When, of the two surfaces formed in each of the spacers 4 and opposing each other in the lamination direction T, the surface not sandwiching the external electrode is defined as a second main surface SA2, the angle of the second main surface SA2 of the spacer 4 with respect to the main surface of the laminate 2 on which the spacer is disposed is five degrees or less when viewed from the width direction.

Description

Multilayer ceramic electronic components

[0001] The present invention relates to a multilayer ceramic electronic component such as a multilayer ceramic capacitor.

[0002] A multilayer ceramic capacitor has an inner layer portion in which dielectric layers and internal electrodes are alternately stacked, and dielectric layers are disposed on the top and bottom of the inner layer portion as outer layers to form a rectangular parallelepiped laminate, and external electrodes are provided on both longitudinal end faces of the laminate to form a capacitor body.

[0003] Furthermore, in order to suppress the occurrence of so-called "squeak noise," a multilayer ceramic capacitor is known that includes a spacer formed on the side of the capacitor body that is mounted on the substrate so as to cover part of the external electrodes.

[0004] However, depending on the shape of the spacer, it may be difficult to mount the multilayer ceramic capacitor on the wiring board, or if the heated and melted solder during mounting runs along the surface of the spacer and rises high in the height direction of the multilayer ceramic capacitor, the expansion and contraction vibration of the inner layer is propagated to the wiring board, making it difficult to suppress the occurrence of acoustic noise.

[0005] Therefore, there is a need to develop a multilayer ceramic capacitor that can be reliably mounted on a wiring board and that can suppress the generation of acoustic noise.

[0006] Japanese Patent Application Laid-Open No. 2015-216337

[0007] An object of the present invention is to provide a multilayer ceramic capacitor that can be reliably mounted on a wiring board and that can suppress the generation of acoustic noise.

[0008] The inventors have discovered that in a multilayer ceramic capacitor having a spacer, if the second main surface of the spacer that is joined to the land of the wiring board is arranged at an angle of 5 degrees or less, as viewed in the width direction, with respect to the main surface of the laminate on which the spacer is arranged, the gap between the land of the wiring board and the spacer is reduced, thereby enabling the multilayer ceramic capacitor to be mounted reliably, and have completed the present invention.

[0009] That is, the present invention provides a multilayer ceramic electronic component comprising: a laminate including an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked, the laminate having two main surfaces opposing each other in a stacking direction, two end faces opposing each other in a length direction intersecting the stacking direction, and two side surfaces opposing each other in a width direction intersecting the stacking direction and the length direction; two external electrodes connected to the internal electrode layers on each of the two end faces, and covering parts of the end faces and two opposing main faces adjacent thereto; and two spacers arranged on one of the two main faces of the laminate with the external electrodes sandwiched therebetween, wherein, of the two surfaces of the spacer opposing each other in the stacking direction, the surface sandwiching the external electrodes is defined as a first main surface and the surface not sandwiching the external electrodes is defined as a second main surface, and the angle of the second main surface of the spacer with respect to the main surface of the laminate on which the spacer is arranged is 5 degrees or less when viewed from the width direction.

[0010] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can be reliably mounted on a wiring board and that can suppress noise generation.

[0011] 1 is a diagram showing the appearance of a multilayer ceramic capacitor 1. FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III in FIG. 1. FIG. 4 is a schematic view of spacers of various shapes as viewed from the width direction W. FIG. 5 is an enlarged cross-sectional view of the spacer 4 shown in FIG. 2. FIG. 6 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor 1. FIG. 7 is a diagram illustrating a laminate manufacturing step S1, a base electrode layer forming step S2, and a first plating layer forming step S3. FIG. 8 is a diagram illustrating a spacer arranging step S4 and a second plating layer forming step S5. FIG. 9 is a cross-sectional view of a multilayer ceramic capacitor 1 in which a second plating layer 32 is not arranged. FIG. 10 is a cross-sectional view of a multilayer ceramic capacitor 1 provided with a reinforcing material 50. FIG. 11 is a diagram illustrating a reinforcing material arranging step S6.

[0012] Hereinafter, a multilayer ceramic capacitor 1 will be described as an embodiment of the multilayer ceramic electronic component of the present invention, but the present invention is not limited thereto. Furthermore, the drawings may be drawn in a simplified and schematic manner to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match the dimensional ratios of those components described in the specification. Furthermore, components described in the specification may be omitted in the drawings, or the number of components may be omitted.

[0013] Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 1 according to an embodiment. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 according to an embodiment taken along line II-II in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 according to an embodiment taken along line III-III in Fig. 1.

[0014] The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape and includes a capacitor body 1A including a laminate 2 and a pair of external electrodes 3 provided on both ends of the laminate 2, and a spacer 4 attached to the capacitor body 1A. The laminate 2 also includes an inner layer portion 11 in which dielectric layers 14 and internal electrode layers 15 are laminated.

[0015] In the following description, the terms used to represent the orientation of the multilayer ceramic capacitor 1 are: a length direction L, which is the direction in which a pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1; a stacking direction T, which is the direction in which the dielectric layers 14 and the internal electrode layers 15 are stacked; and a width direction W, which is the direction intersecting both the length direction L and the stacking direction T. In the embodiment, the width direction W is perpendicular to both the length direction L and the stacking direction T.

[0016] (Outer Surfaces of Laminate 2) Of the six outer surfaces of the laminate 2, a pair of outer surfaces facing each other in the stacking direction T will be referred to as the first main surface A1 and the second main surface A2, a pair of outer surfaces facing each other in the width direction W will be referred to as the first side surface B1 and the second side surface B2, and a pair of outer surfaces facing each other in the length direction L will be referred to as the first end surface C1 and the second end surface C2. Note that when there is no need to particularly distinguish between the first main surface A1 and the second main surface A2, they will be collectively referred to as the main surface A; when there is no need to particularly distinguish between the first side surface B1 and the second side surface B2, they will be collectively referred to as the side surface B; and when there is no need to particularly distinguish between the first end surface C1 and the second end surface C2, they will be collectively referred to as the end surface C.

[0017] The laminate 2 preferably has rounded ridges R1 including corners. The ridges R1 are the portions where two surfaces of the laminate 2, i.e., the main surface A and the side surface B, the main surface A and the end surface C, or the side surface B and the end surface C, intersect.

[0018] (Laminate 2) The laminate 2 includes an inner layer portion 11 that forms capacitance, an outer layer portion 12 that is arranged to sandwich the inner layer portion 11 in the stacking direction T, and a side gap portion 16 that is arranged to sandwich the inner layer portion 11 and the outer layer portion 12 in the width direction W.

[0019] (Inner Layer Portion 11) The inner layer portion 11 includes dielectric layers 14 and internal electrode layers 15 alternately stacked along the stacking direction T.

[0020] (Dielectric Layer 14) The dielectric layer 14 is made of a ceramic material, such as BaTiO ３ A dielectric ceramic containing the above as its main component is used.

[0021] (Internal Electrode Layer 15) The internal electrode layer 15 includes a plurality of first internal electrode layers 15a and a plurality of second internal electrode layers 15b. The first internal electrode layers 15a and the second internal electrode layers 15b are alternately arranged. The first internal electrode layer 15a includes a first opposing portion 152a opposing the second internal electrode layer 15b and a first lead portion 151a extending from the first opposing portion 152a toward the first end face C1. An end of the first lead portion 151a is exposed at the first end face C1 and electrically connected to the first external electrode 3a described below. The second internal electrode layer 15b includes a second opposing portion 152b opposing the first internal electrode layer 15a and a second lead portion 151b extending from the second opposing portion 152b to the second end face C2. An end of the second lead portion 151b is electrically connected to the second external electrode 3b described below. Charges are stored in the first opposing portions 152a of the first internal electrode layers 15a and the second opposing portions 152b of the second internal electrode layers 15b.

[0022] The internal electrode layers 15 are preferably formed from a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), a silver-palladium (Ag-Pd) alloy, or gold (Au).

[0023] (Outer Layer Portion 12) The outer layer portion 12 can be formed from the same material as the dielectric layer 14 of the inner layer portion 11.

[0024] (Side gap portion 16) The side gap portion 16 is arranged to sandwich the inner layer portion 11 and the outer layer portion 12 in the width direction W, and includes a first side gap portion 16a that forms the first side surface B1 of the multilayer ceramic capacitor 1, and a second side gap portion 16b that forms the second side surface B2 of the multilayer ceramic capacitor 1. The side gap portion 16 can be formed from the same material as the dielectric layer 14.

[0025] (External electrode 3) The external electrode 3 includes a first external electrode 3a provided on the first end face C1 and a second external electrode 3b provided on the second end face C2. The external electrode 3 covers not only the end face C but also a part of the main face A and the side face B that are continuous with the end face C.

[0026] As described above, the end of the first lead portion 151a of the first internal electrode layer 15a is exposed at the first end face C1 and is electrically connected to the first external electrode 3a. Also, the end of the second lead portion 151b of the second internal electrode layer 15b is exposed at the second end face C2 and is electrically connected to the second external electrode 3b. This results in a structure in which multiple capacitor elements are electrically connected in parallel between the first external electrode 3a and the second external electrode 3b.

[0027] The external electrode 3 includes, for example, a base electrode layer 30 and a first plating layer 31. However, it is not always necessary for the external electrode 3 to have such a layered structure.

[0028] The base electrode layer 30 is formed by, for example, applying and baking a conductive paste containing copper (Cu). The base electrode layer 30 of the embodiment may also contain glass or a ceramic material. However, the configuration of the base electrode layer 30 is not limited to this.

[0029] The first plating layer 31 includes a first nickel (Ni) plating layer 31 a disposed on the surface of the base electrode layer 30, and a first tin (Sn) plating layer 31 b disposed on the surface of the first nickel (Ni) plating layer 31 a. Note that the configuration of the first plating layer 31 is not limited to this.

[0030] (Spacer 4) The spacer 4 includes a pair of first and second spacers 4a and 4b. The first spacer 4a is disposed on one end face C1 in the longitudinal direction L of the second main surface A2, which is the mounting surface of the capacitor body 1A, and the second spacer 4b is disposed on the other end face C2. When the mounting surface of the capacitor body 1A is the first side face B1, the first spacer 4a is disposed on one end face C1 in the longitudinal direction L of the first side face B1, which is the mounting surface of the capacitor body 1A, and the second spacer 4b is disposed on the other end face C2.

[0031] The spacer 4 is disposed on the external electrode 3 of the capacitor body 1A and on the surface of the second main surface A2 of the laminate 2 on which the subsequent external electrode 3 is not disposed. When the substrate mounting surface of the capacitor body 1A is the first side surface B1, the spacer 4 is disposed on the surface of the first side surface B1 of the laminate 2 on which the subsequent external electrode 3 is not disposed.

[0032] The spacer 4 has a substantially rectangular parallelepiped shape, and of the two surfaces formed on the surface facing each other in the stacking direction T, the surface sandwiching the external electrode 3 between the second main surface A2 of the laminate 2 is defined as the first main surface SA1, and the surface not sandwiching the external electrode 3 is defined as the second main surface SA2. The angle of the second main surface SA2 of the spacer 4 relative to the second main surface A2 of the laminate 2 is 5 degrees or less as viewed from the width direction W. This allows the multilayer ceramic capacitor 1 to be positioned with the second main surface SA2 of the spacer 4 substantially parallel to the wiring board. This allows reliable bonding without gaps between the spacer 4 and the lands on the wiring board when soldering. Furthermore, this minimizes the difference in the amount of solder seeping between the two spacers 4 and the second main surface A2 of the laminate 2, thereby suppressing fluctuations in the relative positions of the two spacers 4 caused by solder shrinkage and improving mountability. When the substrate mounting surface of the capacitor body 1A is the first side surface B1, of the two surfaces formed on the surface of the approximately rectangular parallelepiped spacer 4 that face each other in the width direction W, the surface that sandwiches the external electrode 3 between it and the first side surface B1 of the laminate 2 is defined as the first side surface SB1, and the surface that does not sandwich the external electrode 3 is defined as the second side surface SB2, the angle of the second side surface SB2 of the spacer 4 relative to the first side surface B1 of the laminate 2 is 5 degrees or less when viewed from the stacking direction T.

[0033] One method for measuring the angle of the second main surface SA2 of the spacer 4 relative to the second main surface A2 of the laminate 2 is, for example, to polish the spacer 4 perpendicular to the width direction W up to the center of the width direction W, and then photograph the polished surface with a microscope (BX-51) connected to a microscope digital camera (DP22, manufactured by Olympus) at a total magnification of 10x. In the photographed image, the angle formed by a line connecting both ends of the second main surface A2 of the laminate 2 and a line connecting both ends of the second main surface SA2 of the spacer 4 can be measured. If both ends are rounded, the unrounded parts are taken as both ends.

[0034] If the heated and melted solder during mounting runs along the surface of the spacer 4, rises high in a direction perpendicular to the mounting surface of the multilayer ceramic capacitor 1, and wets and rises up the surface of the external electrode 3 along the end face C, the expansion and contraction vibration of the inner layer portion 11 will propagate to the wiring board, making it difficult to suppress the generation of acoustic noise. For this reason, when viewing the spacer 4 from the width direction W, it is preferable that the length W1 in the length direction L of the first main surface SA1 of the spacer 4 be 95% or less or 105% or more of the length W3 in the length direction L of the second main surface SA2 of the spacer 4. This makes it possible to prevent the melted solder from running down the surface of the spacer 4 and wetting and rising up.

[0035] Furthermore, when the spacer 4 is viewed from the width direction W, the length W2 of the central portion in the length direction L in the stacking direction T is preferably shorter than the length W1 of the first main surface SA1 in the length direction L and the length W3 of the second main surface SA2 in the length direction L. For example, as shown in the schematic diagrams of FIG. 4, a shape that can be expressed as a relationship W1<W2<W3 ( FIG. 4(b) ), a shape that can be expressed as a relationship W1>W2>W3 ( FIG. 4(c) ), or a shape that can be expressed as a relationship W1>W2 and W2<W3 ( FIG. 4(d) ) can prevent molten solder from running down the surface of the spacer 4 and wetting up. Furthermore, such a shape of the spacer increases the bonding area with the reinforcing material (described later), thereby improving the bonding strength between the spacer and the multilayer ceramic capacitor. The same applies when the substrate mounting surface of the capacitor body 1A is the first side surface B1.

[0036] As a method for measuring W1, W2, and W3, for example, the spacer 4 is polished perpendicular to the width direction W up to the center of the width direction W, and the polished surface is photographed with a microscope (BX-51) connected to a microscope digital camera (DP22, manufactured by Olympus) at a total magnification of 10. The length of each portion is measured from the photographed image.

[0037] Although the second plating layer 32 is disposed so as to cover the spacer 4 and the external electrode 3, this is not limiting, and the second plating layer 32 does not necessarily have to be disposed on the spacer 4 and the external electrode 3 ( FIG. 9 ). When the second plating layer 32 is disposed so as to cover the spacer 4 and the external electrode 3, the second plating layer 32 includes a second nickel (Ni) plating layer 32a and a second tin (Sn) plating layer 32b disposed on the surface of the second nickel (Ni) plating layer 32a. The second plating layer 32 is disposed on the outer surface of the first tin (Sn) plating layer 31b of the first plating layer 31 in areas where the spacer 4 is not disposed, and is disposed on the outer surface of the spacer 4 in areas where the spacer 4 is disposed. Note that the configuration of the second plating layer 32 is not limited to this. The second plating layer 32 improves the adhesive strength between the spacer 4 and the capacitor body 1A.

[0038] In the embodiment, the external electrode 3 is configured by the base electrode layer 30 and the first plating layer 31 covering it, and the spacer 4 is disposed on the surface of the first plating layer 31, but the first plating layer 31 is not necessarily required. For example, the spacer 4 may be disposed on the surface of the base electrode layer 30, and the second plating layer 32 may be disposed so as to cover the spacer 4 and the base electrode layer 30. By disposing the second plating layer 32, the adhesive strength between the spacer 4 and the base electrode layer 30 is improved, and the second plating layer 32 fills the gaps P exposed on the surface of the spacer 4, thereby improving the mechanical strength of the spacer 4.

[0039] The spacer 4 contains either copper (Cu) or nickel (Ni) and tin (Sn) as metal powder. The copper (Cu) and nickel (Ni) may be coated with silver (Ag). An intermetallic compound formed by adding tin (Sn) to either copper (Cu) or nickel (Ni) can reliably maintain the shape of the spacer 4 without deformation due to heat even when soldering is performed when mounting the multilayer ceramic capacitor 1 on a wiring board. In particular, an intermetallic compound formed by adding tin (Sn) to an alloy of copper (Cu) and nickel (Ni) is preferred as a component for forming the spacer 4.

[0040] Phenolic resin may be contained in the metal region MP formed by the metal powder. The phenolic resin coats the particles of the intermetallic compound and is scattered so as to fill the gaps between the particles. The phenolic resin may not completely coat the particles of the intermetallic compound. Furthermore, by using phenolic resin, the amount of gas generated during the heat treatment for forming the spacer 4 can be reduced, thereby reducing the voids P within the spacer 4. The phenolic resin may be exposed to the surface of the spacer 4 and coat at least a portion of the surface of the spacer 4. By coating the surface of the spacer 4 with phenolic resin, the smoothness of the surface of the spacer 4 is improved, and the mechanical strength of the spacer 4 can be increased.

[0041] Examples of the phenol resin include novolac-type phenol resins such as phenol novolac resin, phenol aralkyl resin, cresol novolac resin, tert-butylphenol novolac resin, and nonylphenol novolac resin; resol-type phenol resin; and polyoxystyrene such as polyparaoxystyrene.

[0042] The area ratio of the phenolic resin is preferably 1% to 20% inclusive, and particularly preferably 5% to 15% inclusive, in the LT cross section perpendicular to the width direction W of the spacer 4. If it is less than 1%, the effect of the phenolic resin cannot be fully exerted, and if it exceeds 20%, the adhesive strength of the spacer to the external electrode may decrease.

[0043] The percentage of the area occupied by the phenolic resin can be calculated, for example, by polishing the spacer 4 in the width direction W up to the center of the width direction W, and then photographing the polished surface with a microscope (BX-51) at a total magnification of 50x using a digital camera for microscopes (Olympus DP22). The obtained photographed image is binarized to separate it into metal regions MP and resin regions RP, and the percentage of the area occupied by the phenolic resin can be calculated from the areas of the metal regions MP, metal powder MF, resin regions RP, and voids P using the formula: Area of ​​Resin Regions RP / (Area of ​​Metal Regions MP + Area of ​​Metal Powder MF + Area of ​​Resin Regions RP + Area of ​​Voids P) × 100.

[0044] 5, metal powder MF may be contained in the resin region RP formed by the phenolic resin. The metal powder MF inhibits the shrinkage of the phenolic resin, and the shrinkage stress caused by the phenolic resin can be alleviated.

[0045] The spacer 4 preferably has a porosity of 20% or less in a region Z extending from the interface with the external electrode 3 to a depth of 5 μm. By keeping the porosity low, the bonding area of ​​the spacer 4 that is bonded to the external electrode 3 increases, improving the bonding strength with the external electrode 3.

[0046] The porosity (%) can be calculated, for example, by polishing the spacer 4 in the width direction W up to the center of the width direction W, and then photographing the polished surface with a microscope (BX-51) at a total magnification of 50 times and a digital camera for microscopes (DP22 manufactured by Olympus). The obtained photographed image is binarized to separate it into metal regions MP and voids P, and the porosity (%) can be calculated from the areas of the metal regions MP, metal powder MF, resin regions RP, and voids P using the formula: void ratio (%) = area of ​​voids P / (area of ​​metal regions MP + area of ​​metal powder MF + area of ​​resin regions RP + area of ​​voids P) × 100.

[0047] The maximum diameter of the voids P formed inside the spacer 4 is preferably ½ or less of the maximum dimension of the thickness of the spacer 4 in the stacking direction T. If it is greater than ½, cracks are more likely to occur starting from the voids P, reducing the strength of the spacer 4. When the substrate mounting surface of the capacitor body 1A is the first side surface B1, the maximum diameter of the voids P formed inside the spacer 4 is preferably ½ or less of the maximum dimension of the thickness of the spacer 4 in the width direction W.

[0048] Although the above description shows an example of the material of the spacer 4 containing an intermetallic compound and a phenolic resin, the present invention is not limited to this and the spacer 4 may contain other metal components, or may contain a resin other than the phenolic resin, such as an epoxy resin or a rosin, or a glass component. The spacer 4 may also be formed without containing a resin.

[0049] When the spacers 4 are formed smaller than the external electrodes 3 in a plan view from the stacking direction T, it is preferable to provide an orientation discriminator on at least a portion of the spacer 4. The orientation discriminator indicates the orientation so that the second main surface A2 on which the spacers 4 are arranged faces the wiring board when the multilayer ceramic capacitor 1 is mounted on the wiring board. The orientation discriminator can be implemented by coloring the spacers 4 in a color different from that of the external electrodes 3, printing a mark for discriminating the orientation, such as a QR code (registered trademark), or providing a recess in a portion of the laminate. As a coloring method, a phenolic resin contained in the spacers 4 may be exposed on the surface of the spacers 4, so that the spacers 4 have a color different from that of the external electrodes 3. The orientation discriminator may also be provided even when the spacers 4 are larger than the external electrodes 3.

[0050] 10 , a reinforcing material 50 can be disposed between the first spacer 4 a and the second spacer 4 b so as to cover at least a portion of at least one of the first spacer 4 a and the second spacer 4 b and at least a portion of the second main surface A2 or the first side surface B1 of the laminate 2. By disposing the reinforcing material 50, the adhesive strength between the spacer 4 and the external electrode 3 and between the spacer 4 and the laminate 2 can be improved.

[0051] The reinforcing material 50 can be arranged continuously between the first spacer 4a and the second spacer 4b, but does not necessarily have to be arranged continuously. For example, the reinforcing material 50 may be arranged in two parts: one covering a portion of the first spacer 4a and a portion of the second main surface A2 or the first side surface B1 of the laminate 2, and the other covering a portion of the second spacer 4b and a portion of the second main surface A2 or the first side surface B1 of the laminate 2.

[0052] The reinforcing material 50 can be formed from an insulating resin. The surface of the insulating resin may be coated with an insulating water-repellent agent. By forming the reinforcing material from an insulating resin, the flexural strength is improved, and by coating it with an insulating water-repellent agent, the moisture resistance is improved. The insulating resin may contain ceramics, glass, etc., or may be formed only from a water-repellent agent.

[0053] The material of the reinforcing material 50 may be mainly composed of epoxy resin, which may be combined with phenolic resin as a hardener. Other hardeners that may be used include acid anhydride-based, amine-based, and ester-based hardeners. A hardening accelerator may also be added to the epoxy resin.

[0054] The reinforcing material 50 can be arranged so as to cover the side peripheral surface SW of the spacer 4. In this case, it is preferable that the reinforcing material 50 covers the side peripheral surface SW of the spacer 4 to a height of 5% or more of the length of the spacer 4 in the stacking direction T, while covering the second main surface A2 or the first side surface B1 of the laminate 2. Covering the spacer 4 with the reinforcing material 50 in this manner improves the mechanical strength, and in particular improves the impact resistance when an impact is applied to the multilayer ceramic capacitor 1.

[0055] (Manufacturing Method of Multilayer Ceramic Capacitor 1) FIG. 6 is a flowchart illustrating a manufacturing method of the multilayer ceramic capacitor 1. The manufacturing method of the multilayer ceramic capacitor 1 includes a laminate manufacturing process S1, a base electrode layer forming process S2, a first plating layer forming process S3, a spacer arranging process S4, and a second plating layer forming process S5. Furthermore, the multilayer ceramic capacitor 1 can be provided with a reinforcing material 50 by undergoing a reinforcing material arranging process S6 after the spacer arranging process S4. FIG. 7 is a diagram illustrating the laminate manufacturing process S1, the base electrode layer forming process S2, and the first plating layer forming process S3. FIG. 8 is a diagram illustrating the spacer arranging process S4 and the second plating layer forming process S5. FIG. 11 is a diagram illustrating the reinforcing material arranging process S6.

[0056] (Laminate manufacturing process S1) A ceramic slurry containing ceramic powder, a binder, and a solvent is formed into a sheet on the surface of a carrier film using a die coater, gravure coater, microgravure coater, or the like to prepare a ceramic green sheet 101 for lamination that will become the dielectric layer 14. Next, a conductive paste is printed in strips on the ceramic green sheet 101 for lamination by screen printing, inkjet printing, gravure printing, or the like, and a conductive pattern 102 that will become the internal electrode layer 15 is printed on the surface of the ceramic green sheet 101 for lamination to prepare a material sheet 103.

[0057] 7( a), a plurality of material sheets 103 are stacked so that the conductive patterns 102 face in the same direction and are offset, for example, by half a pitch, in the longitudinal direction between adjacent material sheets 103. Furthermore, outer layer ceramic green sheets 112 that will become the outer layer portions 12 are stacked on both sides of the plurality of stacked material sheets 103.

[0058] The stacked material sheets 103 and the outer layer ceramic green sheets 112 are pressed together by a hydrostatic press or the like to form a mother block 110 shown in FIG. 7(b).

[0059] Next, the mother block 110 is cut along cutting lines X and Y intersecting with cutting line X shown in FIG. 7(b) to produce a plurality of unfired laminates 2 shown in FIG. 7(c).

[0060] (Base electrode layer forming step S2) Subsequently, a conductive paste containing copper (Cu) is applied to and baked on the end face C of the laminate 2 to form the base electrode layer 30. The base electrode layer 30 is formed so as to cover not only the end faces C on both sides of the laminate 2, but also the main face A and side face B of the laminate 2, and to cover a part of the end face C side of the main face A. However, the present invention is not limited to this, and the base electrode layer may contain other metals or other components, and two base electrode layers may be provided.

[0061] (First plating layer forming process S3) Next, a first nickel (Ni) plating layer 31a and a first tin (Sn) plating layer 31b disposed on the surface of the first nickel (Ni) plating layer 31a are formed on the surface of the base electrode layer 30, thereby producing the capacitor body 1A shown in FIG. 7(d).

[0062] (Spacer Arrangement Step S4) A spacer manufacturing paste 41 used for manufacturing spacers is prepared. The spacer manufacturing paste 41 contains metals made of copper (Cu), nickel (Ni), tin (Sn), and silver (Ag), a phenol resin, a solvent, and an additive.

[0063] Examples of the phenol resin include novolac-type phenol resins such as phenol novolac resin, phenol aralkyl resin, cresol novolac resin, tert-butylphenol novolac resin, and nonylphenol novolac resin; resol-type phenol resin; and polyoxystyrene such as polyparaoxystyrene.

[0064] To form the spacers 4, for example, a holding substrate 40 as shown in Fig. 8 is used. A spacer manufacturing paste 41 is placed on the holding substrate 40 by screen printing, dispensing, or the like.

[0065] 8(b), the capacitor body 1A is mounted on the upper surface of the holding substrate 40 with the second main surface A2 facing the holding substrate 40. At this time, the external electrodes 3 of the capacitor body 1A and the spacer manufacturing paste 41 are aligned, and the spacer manufacturing paste 41 adheres to the capacitor body 1A.

[0066] In this state, a heating step is carried out. When at least a portion of the metal in the paste generates an intermetallic compound to form the metal region MP, some of the phenolic resin is taken into the metal region MP and some is expelled from the metal region MP while hardening, forming the spacer 4 bonded to the capacitor body 1A.

[0067] Thereafter, the capacitor body 1A is separated from the holding substrate 40 together with the spacers 4, resulting in the state shown in Fig. 8(c). Note that the manufacturing method is not limited to this, and the spacers may be formed by applying a spacer manufacturing paste in a desired shape directly on the surface of the capacitor body 1A and then performing a heat treatment.

[0068] In order to adjust the spacer 4 to a predetermined shape, for example, the following method can be adopted.

[0069] In the case of a shape represented by the relationship W1<W2<W3, after printing the spacer manufacturing paste on the unsintered laminate 2 by screen printing or the like, a smooth plate-shaped jig is pressed against the printed surface. The height of the jig is adjusted to increase the amount of pressure applied to the spacer manufacturing paste, and then heat treatment is performed. In the case of a shape represented by the relationship W1>W2>W3, after printing the spacer manufacturing paste on the unsintered laminate 2 by screen printing or the like, a smooth plate-shaped jig is pressed against the printed surface. The height of the jig is adjusted to decrease the amount of pressure applied to the spacer manufacturing paste, and then heat treatment is performed. In the case of a shape represented by the relationship W1>W2 and W2<W3, after printing the spacer manufacturing paste on the unsintered laminate 2 by screen printing or the like, a smooth plate-shaped jig is pressed against the spacer manufacturing paste while adjusting its height, and then heat treatment is performed while the jig is moved in the direction away from the spacer manufacturing paste so as not to separate from it.

[0070] Although the above description shows an example of the material of the spacer 4 containing an intermetallic compound and a phenolic resin, the present invention is not limited to this and the spacer 4 may contain other metal components, or may contain a resin other than the phenolic resin, such as an epoxy resin or a rosin, or a glass component. The spacer 4 may also be formed without containing a resin.

[0071] (Second plating layer forming process S5) Next, a second nickel (Ni) plating layer 32a is formed on the exposed portion of the first tin (Sn) plating layer 31b in the capacitor body 1A and on the surface of the spacer 4, and a second tin (Sn) plating layer 32b may further be formed on the outer periphery of the second nickel (Ni) plating layer 32a.

[0072] (Reinforcing material placement step S6) Figure 11 is a diagram illustrating the reinforcing material placement step S6. After the spacer placement step S4, the surface of the capacitor body 1A on which the spacers 4 are placed is cleaned with a solvent. As shown in Figure 11(a), after cleaning is completed, the capacitor body 1A on which the spacers 4 are placed is aligned so that the spacers 4 face upward.

[0073] 11(b), an insulating resin layer that will become the central portion 51 of the reinforcing material 50 is formed between the first spacer 4a and the second spacer 4b using a dispenser or squeegee printing on the capacitor body 1A on which the spacer 4 is arranged. The amount of insulating resin that spreads onto the side surface of the spacer 4 can be adjusted by adjusting the amount of insulating resin.

[0074] When the insulating resin is to be allowed to penetrate into the interface between the spacer 4 and the laminate 2, the insulating resin can be placed and then evacuated. The amount of penetration can be controlled by changing the time and pressure of the evacuation.

[0075] 11(c), an insulating resin may be applied so as to cover the outer periphery of the capacitor body 1A and the outer periphery of the spacer 4. The applied insulating resin is then heated at 100 to 200°C for 20 to 80 minutes, whereby the insulating resin hardens and a covering portion made of the reinforcing material 50 is formed on the outer periphery of the capacitor body 1A and the side circumferential surface SW of the spacer 4. Through the above steps, the multilayer ceramic capacitor 1 is manufactured.

[0076] In the embodiment, the reinforcing material 50 is shown to directly cover the surface of the spacer 4, but this is not necessarily limited to such a configuration. For example, the second plating layer 32 may be formed on the surface of the spacer 4, and the reinforcing material 50 may be arranged so that it covers the surface of the second plating layer 32 and the side surface SW of the spacer 4.

[0077] Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments and can be embodied in various forms without departing from the spirit of the present invention. The present invention includes the following combinations.

[0078] <1> A multilayer ceramic electronic component comprising: a laminate including an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked, the laminate having two main surfaces opposing each other in a stacking direction, two end faces opposing each other in a length direction intersecting the stacking direction, and two side surfaces opposing each other in a width direction intersecting the stacking direction and the length direction; two external electrodes connected to the internal electrode layers on each of the two end faces and covering parts of the end faces and two opposing main faces successively adjacent thereto; and two spacers disposed on one of the two main faces of the laminate with the external electrodes sandwiched therebetween, wherein, of the two surfaces of the spacer opposing each other in the stacking direction, a surface sandwiching the external electrodes is defined as a first main surface and a surface not sandwiching the external electrodes is defined as a second main surface, and an angle of the second main surface of the spacer with respect to the main surface of the laminate on which the spacer is disposed is 5 degrees or less as viewed in the width direction. <2> The multilayer ceramic electronic component according to <1>, wherein, when the spacer is viewed from the width direction, the length in the length direction of the first main surface is 95% or less or 105% or more of the length in the length direction of the second main surface. <3> The multilayer ceramic electronic component according to <1> or <2>, wherein, when the spacer is viewed from the width direction, the length in the length direction of a central portion in the stacking direction is shorter than the length in the length direction of the first main surface and the length in the length direction of the second main surface. <4> The multilayer ceramic electronic component according to any one of <1> to <3>, wherein the spacer contains a resin. <5> The ceramic capacitor according to any one of <1> to <4>, wherein the spacer contains copper and glass. <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the spacer contains a phenolic resin. <7> The multilayer ceramic capacitor according to <1> to <6>, wherein the spacer contains an epoxy resin. <8> The multilayer ceramic capacitor according to <1> to <7>, wherein the spacer contains rosin. <9> The multilayer ceramic electronic component according to any one of <1> to <8>, wherein a reinforcing material is disposed between the two spacers, the reinforcing material covering at least a portion of the two spacers and at least a portion of the main surface of the laminate.<10> The multilayer ceramic electronic component according to <9>, wherein the reinforcing material covers side peripheral surfaces of the two spacers. <11> A multilayer ceramic electronic component comprising: a laminate including an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked, the laminate having two main surfaces opposing each other in a stacking direction, two end faces opposing each other in a length direction intersecting the stacking direction, and two side surfaces opposing each other in a width direction intersecting the stacking direction and the length direction; two external electrodes connected to the internal electrode layers on each of the two end faces and covering parts of the end faces and the two side surfaces adjacent thereto; and two spacers arranged on one of the two side surfaces of the laminate with the external electrode sandwiched therebetween, wherein, when one of the two surfaces of the spacer opposing each other in the width direction is defined as a first side surface and the other of the two surfaces not sandwiching the external electrode is defined as a second side surface, an angle of the second side surface of the spacer with respect to the side surface of the laminate on which the spacer is arranged is 5 degrees or less as viewed from the width direction. <12> The multilayer ceramic electronic component according to <11>, wherein, when the spacer is viewed from the stacking direction, the length of the first side surface in the length direction is 95% or less or 105% or more of the length of the second side surface in the length direction. <13> The multilayer ceramic electronic component according to <11> or <12>, wherein, when the spacer is viewed from the stacking direction, the length of the widthwise central portion is shorter than the length of the first side surface in the length direction and the length of the second side surface in the length direction. <14> The multilayer ceramic electronic component according to any one of <11> to <13>, wherein the spacer contains a resin. <15> The ceramic capacitor according to any one of <11> to <14>, wherein the spacer contains copper and glass. <16> The multilayer ceramic capacitor according to any one of <11> to <15>, wherein the spacer contains a phenolic resin. <17> The multilayer ceramic capacitor according to any one of <11> to <16>, wherein the spacer contains an epoxy resin. <18> The multilayer ceramic capacitor according to any one of <11> to <17>, wherein the spacer contains rosin.<19> The multilayer ceramic electronic component according to any one of <11> to <18>, wherein a reinforcing material is disposed between the two spacers, the reinforcing material covering at least a portion of the two spacers and at least a portion of the side surfaces of the laminate. <20> The multilayer ceramic electronic component according to <19>, wherein the reinforcing material covers the side peripheral surfaces of the two spacers.

[0079] A Principal surface A1 First principal surface A2 Second principal surface B Side surface C End surface MF Metal powder MP Metal region P Gap RP Resin region SA1 First principal surface SA2 Second principal surface SW Peripheral side surface 1 Multilayer ceramic capacitor 1A Capacitor body 2 Laminate 3 External electrode 4 Spacer 11 Inner layer portion 12 Outer layer portion 14 Dielectric layer 15 Internal electrode layer 30 Base electrode layer 31 First plating layer 32 Second plating layer 40 Holding substrate 41 Spacer manufacturing paste 50 Reinforcing material 51 Center portion

Claims

1. a laminate including an inner layer portion in which dielectric layers and internal electrode layers are alternately laminated, the laminate having two main surfaces opposing each other in a lamination direction, two end faces opposing each other in a length direction intersecting the lamination direction, and two side surfaces opposing each other in a width direction intersecting the lamination direction and the length direction; two external electrodes connected to the internal electrode layers on the two end faces, respectively, and covering parts of the end faces and two opposing main faces; two spacers arranged on one of the two main surfaces of the laminate with the external electrode sandwiched therebetween, When, of two surfaces formed on the spacer and facing each other in the stacking direction, the surface sandwiching the external electrode is defined as a first main surface and the surface not sandwiching the external electrode is defined as a second main surface, a multilayer ceramic electronic component in which the angle of the second main surface of the spacer relative to the main surface of the laminate on which the spacer is disposed is 5 degrees or less when viewed from the width direction;

2. 2. The multilayer ceramic electronic component according to claim 1, wherein, when the spacer is viewed from the width direction, the length of the first main surface in the longitudinal direction is 95% or less or 105% or more of the length of the second main surface in the longitudinal direction.

3. 3. The multilayer ceramic electronic component according to claim 1, wherein, when the spacer is viewed from the width direction, the length in the longitudinal direction of a central portion in the stacking direction is shorter than the length in the longitudinal direction of the first main surface and the length in the longitudinal direction of the second main surface.

4. 3. The multilayer ceramic electronic component according to claim 1, wherein the spacer contains a resin.

5. 3. The multilayer ceramic electronic component according to claim 1, wherein said spacer contains copper and glass.

6. 3. The multilayer ceramic electronic component according to claim 1, wherein the spacer contains a phenolic resin.

7. 3. The multilayer ceramic electronic component according to claim 1, wherein said spacer contains an epoxy resin.

8. 3. The multilayer ceramic electronic component according to claim 1, wherein the spacer contains rosin.

9. 3. The multilayer ceramic electronic component according to claim 1, further comprising a reinforcing material disposed between said two spacers, said reinforcing material covering at least a portion of said two spacers and at least a portion of said main surface of said laminate.

10. 10. The multilayer ceramic electronic component according to claim 9, wherein the reinforcing material covers side peripheral surfaces of the two spacers.

11. a laminate including an inner layer portion in which dielectric layers and internal electrode layers are alternately laminated, the laminate having two main surfaces opposing each other in a lamination direction, two end faces opposing each other in a length direction intersecting the lamination direction, and two side surfaces opposing each other in a width direction intersecting the lamination direction and the length direction; two external electrodes connected to the internal electrode layers on the two end faces, respectively, and covering the end faces and parts of two side faces facing each other; two spacers disposed on one of the two side surfaces of the laminate with the external electrode sandwiched therebetween; When, of two surfaces formed on the spacer and facing each other in the width direction, the surface sandwiching the external electrode is defined as a first side surface, and the surface not sandwiching the external electrode is defined as a second side surface, a multilayer ceramic electronic component in which the angle of the second side surface of the spacer relative to the side surface of the laminate on which the spacer is disposed is 5 degrees or less when viewed from the stacking direction;

12. 12. The multilayer ceramic electronic component according to claim 11, wherein, when the spacer is viewed from the stacking direction, the length of the first side surface in the longitudinal direction is 95% or less or 105% or more of the length of the second side surface in the longitudinal direction.

13. 13. The multilayer ceramic electronic component according to claim 11, wherein, when the spacer is viewed from the stacking direction, the length in the longitudinal direction of the widthwise central portion is shorter than the length in the longitudinal direction of the first side surface and the length in the longitudinal direction of the second side surface.

14. 13. The multilayer ceramic electronic component according to claim 11, wherein the spacer contains a resin.

15. 13. The multilayer ceramic electronic component according to claim 11, wherein the spacer contains copper and glass.

16. 13. The multilayer ceramic electronic component according to claim 11, wherein the spacer contains a phenolic resin.

17. 13. The multilayer ceramic electronic component according to claim 11, wherein the spacer contains an epoxy resin.

18. 13. The multilayer ceramic electronic component according to claim 11, wherein the spacer contains rosin.

19. 13. The multilayer ceramic electronic component according to claim 11, further comprising a reinforcing material disposed between the two spacers, the reinforcing material covering at least a portion of the two spacers and at least a portion of the side surfaces of the laminate.

20. 20. The multilayer ceramic electronic component according to claim 19, wherein the reinforcing material covers side peripheral surfaces of the two spacers.