Semiconductor device and method for manufacturing same

Abstract

This semiconductor device (1) is provided with a substrate (101), a channel layer (103), a nitride semiconductor layer (104) that includes a barrier layer (105), a source electrode (201), a drain electrode (202), a gate electrode (203), and an insulating layer (300). The gate electrode (203) comprises a junction part (203a) and a drain-side overhang part (203d). The insulating layer (300) comprises an In-situ Si3N4 film (301) and an Ex-situ Si3N4 film (302). This semiconductor device satisfies at least one of (a) the halogen concentration of the In-situ Si3N4 film (301) is lower than the halogen concentration of the Ex-situ Si3 N4 film (302), and (b) the interfacial oxygen concentration between the In-situ Si3N4 film (301) and the nitride semiconductor layer (104) is lower than the interfacial oxygen concentration between the Ex-situ Si3N4 film (302) and the In-situ Si3N4 film (301).

Description

Semiconductor device and manufacturing method thereof

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof.

[0002] In recent years, development of GaN high electron mobility transistors (HEMTs) for use in power amplifiers for high frequency wireless communications has been progressing. GaN HEMTs have the following three main physical property characteristics:

[0003] Specifically, these are an electron carrier transport mechanism that utilizes the high mobility of two-dimensional electron gas (hereinafter referred to as 2DEG (Two Dimensional Electron Gas)), high voltage resistance due to the wide band gap properties of the semiconductor, and high current drivability due to the high piezoelectric effect. These features make GaN HEMTs ideal devices for applications that satisfy both high speed and high output characteristics, and their application to high frequency wireless base stations, high speed charging, etc. is progressing.

[0004] As mentioned above, the GaN HEMT is characterized by its high saturation current due to the piezoelectric effect. To maximize its performance, a silicon nitride film (Si ３ N ４ It is effective to form a protective film using a silicon dioxide film, which is generally dense. ３ N ４ However, the Si film, which serves as a protective film for the epitaxial substrate, tends to have a strong piezoelectric stress. ３ N ４ In the film, a current collapse phenomenon occurs due to impurity levels, which is characteristic of GaN HEMTs. ３ N ４ The film is made of Si with few impurity levels at the interface with the epitaxial surface. ３ N ４ It is also required to be a membrane.

[0005] Here, we will briefly explain the current collapse phenomenon. First, the epitaxially grown semiconductor surface and Si ３ N ４The phenomenon begins when hot electron carriers generated by high-voltage operation are captured by impurity levels formed at the interface with the film, causing a negative charge. Next, electrons traveling through the 2DEG see this negative fixed charge close to the channel they are traveling through, and this fixed charge becomes a scattering factor for the traveling electrons. This results in a deterioration in saturation velocity and on-resistance characteristics, a phenomenon known as current collapse.

[0006] Si that meets the conditions of being dense and having few interface states ３ N ４ The film is made of Si, which is continuously grown in a growth furnace on an epitaxial substrate. ３ N ４ Generally, this Si ３ N ４ The film is in-situ Si ３ N ４ On the GaN epitaxial layer, a Si film is formed to compensate for the N vacancies on the surface during the process. ３ N ４ The film is laminated. In-situ Si ３ N ４ In the case of a film, Si ３ N ４ By epitaxially growing Si, the epitaxial surface is not exposed to air, so there are few N defects. ３ N ４ The film is a normal Si ３ N ４ Compared to the in-situ Si film, it has the feature of having fewer impurity levels caused by N vacancies, which reduces surface traps. ３ N ４ The technology for applying the film to a GaN HEMT is disclosed in Non-Patent Documents 1 and 2.

[0007] J. Derluyn et al., “Low Leakage High Breakdown E-Mode DHFET on Si by Selective Removal of In-Situ Grown Si3N4”, IEEE, 2009, IEDM09, pp. 157-160F. Medjdoub et al., “Low On-Resistance High-Breakdown Normally Off AlN / GaN / AlGaN DHFET on Si Substrate”, IEEE Electron Device Letters, Feb. 2010, Vol. 31, No. 2, pp. 111-113

[0008] However, in-situ Si ３ N ４ When a film is provided, there are advantages such as a high saturation current and good collapse characteristics, but there are also the following disadvantages as counter effects. ３ N ４ There is a mechanical issue in that the strong piezoelectric stress of the film causes the wafer to warp.

[0009] Therefore, an object of the present disclosure is to provide a semiconductor device having high drive current characteristics and low wafer warpage characteristics, and a method for manufacturing the same.

[0010] A semiconductor device according to one aspect of the present disclosure includes: a substrate; a channel layer formed above the substrate and made of a nitride semiconductor containing Ga; a nitride semiconductor layer formed above the channel layer, the nitride semiconductor layer having a band gap larger than that of the channel layer and including a barrier layer containing Ga; a source electrode and a drain electrode formed above the substrate and spaced apart from each other; gate electrodes formed above the barrier layer and between the source electrode and the drain electrode and spaced apart from each other; and an insulating layer formed above the nitride semiconductor layer between the gate electrode and the drain electrode, the insulating layer includes a junction portion that forms a Schottky junction with the semiconductor layer, and a first protruding portion that protrudes further toward the drain electrode than the junction portion, the insulating layer including a first insulating film that is located between the first protruding portion and the nitride semiconductor layer and that is made of silicon nitride and that covers and contacts the nitride semiconductor layer, and a second insulating film that is located between the first protruding portion and the first insulating film, and the insulating layer satisfies at least one of the following: (a) a halogen concentration of the first insulating film is lower than a halogen concentration of the second insulating film; and (b) an oxygen concentration at the interface between the first insulating film and the nitride semiconductor layer is lower than an oxygen concentration at the interface between the second insulating film and the first insulating film.

[0011] a second step of forming an insulating layer to cover the nitride semiconductor layer; a third step of removing a portion of the insulating layer to expose a portion of the nitride semiconductor layer; a fourth step of forming a source electrode and a drain electrode above the substrate at a distance from each other; and a fifth step of forming gate electrodes between the source electrode and the drain electrode at a distance from each other, the gate electrodes being in contact with the exposed portion of the nitride semiconductor layer and covering a portion of the insulating layer that is closer to the drain electrode than the exposed portion;

[0012] According to the present disclosure, it is possible to provide a semiconductor device having high drive current characteristics and low wafer warpage characteristics, and a method for manufacturing the same.

[0013] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. ３ N ４ 3 is a graph showing the relationship between the film thickness and the carrier concentration of the 2DEG. ３ N ４ 4 is a diagram showing the relationship between the film thickness and the warpage of the wafer. FIG. 4 is a cross-sectional view of a semiconductor device according to a second embodiment. FIG. 5 is a cross-sectional view of a semiconductor device according to a third embodiment. FIG. 6 is a cross-sectional view of a semiconductor device according to a fourth embodiment. FIG. 7 is a cross-sectional view of an in-situ Si ３ N ４9A is a diagram showing current characteristics of a semiconductor device with respect to a combination of film thickness and barrier layer thickness. FIG. 8 is a cross-sectional view of a semiconductor device for supplementary explanation of the current characteristics shown in FIG. 7. FIG. 9A is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to a third embodiment. FIG. 9B is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to the third embodiment. FIG. 9C is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to the third embodiment. FIG. 9D is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to the third embodiment. FIG. 9E is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to the third embodiment. FIG. 9F is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to the third embodiment. FIG. 9G is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to the third embodiment. FIG. 9H is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to the third embodiment. FIG. 9I is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to the third embodiment. FIG. 9J is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to the third embodiment. FIG. 9K is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to the third embodiment. FIG. 10A is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to the fourth embodiment. FIG. 10B is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to the fourth embodiment. FIG. 10C is a cross-sectional view illustrating one step of the method for manufacturing a semiconductor device according to the fourth embodiment.

[0014] (Summary of the Present Disclosure) Hereinafter, embodiments will be specifically described with reference to the drawings.

[0015] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0016] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0017] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, such as rectangle, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0018] Furthermore, in this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between the two components, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0019] In this specification and drawings, the x-axis, y-axis, and z-axis refer to the three axes of a three-dimensional Cartesian coordinate system. Specifically, the x-axis and y-axis are two axes parallel to the main surface (top surface) of a substrate included in a semiconductor device, and the z-axis is a direction perpendicular to this main surface. Specifically, the direction in which the source electrode, gate electrode, and drain electrode are arranged in this order, i.e., the so-called gate length direction, is the x-axis. In the embodiments described below, the positive direction of the z-axis may be referred to as "upward," and the negative direction of the z-axis may be referred to as "downward." In this specification, unless otherwise specified, the source electrode side or source side refers to the negative side (negative direction) of the x-axis, and the drain electrode side or drain side refers to the positive side (positive direction) of the x-axis. In this specification, the term "planar view" refers to the main surface (top surface) of a substrate included in a semiconductor device viewed from the positive direction of the z-axis, unless otherwise specified.

[0020] In this specification, a group III nitride semiconductor is a semiconductor containing one or more group III elements and nitrogen. Examples of group III elements include aluminum (Al), gallium (Ga), and indium (In). Examples of group III nitride semiconductors include GaN, AlN, InN, AlGaN, InGaN, and AlInGaN. Group III nitride semiconductors may also contain one or more elements other than group III elements, such as silicon (Si) and phosphorus (P). In the following description, unless otherwise specified, the term "AlInGaN" means that the group III nitride semiconductor contains all of Al, In, Ga, and N. The same applies to other designations such as AlGaN and GaN.

[0021] Furthermore, a layer made of material A such as a Group III nitride semiconductor such as GaN or AlGaN, silicon nitride or silicon oxide, and a layer constituted by material A mean that the layer contains substantially only material A. However, the layer may contain other elements as impurities, such as elements that are unavoidable in the manufacturing process, at a rate of 1 at % or less.

[0022] In this specification, the composition ratio (composition rate) of a group III element in a nitride semiconductor (layer) refers to the ratio of the number of atoms of a target group III element among a plurality of group III elements contained in the nitride semiconductor. ａ In ｂ Ga ｃ In the case where the nitride semiconductor layer is made of N (a+b+c=1, a≧0, b≧0, c≧0), the Al composition ratio of the nitride semiconductor layer can be expressed as a / (a+b+c). Similarly, the In composition ratio and the Ga composition ratio can be expressed as b / (a+b+c) and c / (a+b+c), respectively.

[0023] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0024] First Embodiment First, a semiconductor device according to a first embodiment will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view of a semiconductor device 1 according to the present embodiment.

[0025] As shown in FIG. 1 , the semiconductor device 1 includes a substrate 101, a buffer layer 102, a channel layer 103, and a nitride semiconductor layer 104. The nitride semiconductor layer 104 includes a barrier layer 105 and a cap layer 106. A 2DEG 107 is formed near the interface between the channel layer 103 and the barrier layer 105. The buffer layer 102, the channel layer 103, the barrier layer 105, and the cap layer 106 are epitaxial layers (also called epilayers) formed by epitaxial growth. The semiconductor device 1 also includes a source electrode 201, a drain electrode 202, a gate electrode 203, a source field plate 204, barrier metals 205s and 205d, and wiring metals 206s and 206d. The semiconductor device 1 also includes insulating layers 300 and 305. The insulating layer 300 is formed by in-situ Si ３ N ４ Film 301 and Ex-situ Si ３ N ４ and a membrane 302.

[0026] The substrate 101 is a substrate made of Si. Alternatively, the substrate 101 may be an SOI (Silicon on Insulator) substrate. Furthermore, the substrate 101 may be a substrate made of SiC, sapphire, diamond, GaN, AlN, or the like.

[0027] The buffer layer 102 is provided above the substrate 101. For example, the buffer layer 102 is provided in contact with the upper surface of the substrate 101. The buffer layer 102 is, for example, a layer made of a group III nitride semiconductor. As an example, the buffer layer 102 has a multi-layer structure of AlN and AlGaN, each having a thickness of 2 μm. The buffer layer 102 may alternatively be made of a single layer or multiple layers of a group III nitride semiconductor such as GaN, AlGaN, AlN, InGaN, or AlInGaN.

[0028] The provision of the buffer layer 102 can reduce adverse effects such as crystal dislocations and lattice defects caused by the difference in lattice spacing between the substrate 101 and the channel layer 103. Furthermore, even if the substrate 101 has defects, the provision of the buffer layer 102 can suppress the effects of the defects on the channel layer 103. This reduces defects in the channel layer 103, improves crystallinity, and increases electron mobility in the channel layer 103. The buffer layer 102 does not necessarily have to be provided.

[0029] The channel layer 103 is provided above the substrate 101. Specifically, the channel layer 103 is provided in contact with the upper surface of the buffer layer 102. The channel layer 103 is a layer made of a nitride semiconductor containing Ga elements. For example, the channel layer 103 is made of GaN. The film thickness of the channel layer 103 is, for example, 50 nm to 300 nm, and is 200 nm as an example. Note that the channel layer 103 is not limited to GaN, and may be made of a group III nitride semiconductor such as InGaN, AlGaN, or AlInGaN. Furthermore, the channel layer 103 may contain n-type impurities. The film thickness of the channel layer 103 is not limited to the above example.

[0030] The barrier layer 105 is provided above the channel layer 103. Specifically, the barrier layer 105 is provided in contact with the upper surface of the channel layer 103. Note that a spacer layer made of AlN and having a film thickness of, for example, about 1 nm may be provided between the barrier layer 105 and the channel layer 103. In this way, the channel layer 103 and the barrier layer 105 do not need to be in contact with each other.

[0031] The barrier layer 105 has a band gap larger than that of the channel layer 103 and is a layer made of a nitride semiconductor containing Ga. The barrier layer 105 is made of, for example, AlGaN. The Al composition ratio of the barrier layer 105 is, for example, 10% to 30%, but may be 20% to 30%. The Al composition ratio of the barrier layer 105 is, for example, 25% or less. The thickness of the barrier layer 105 is 7 nm to 10 nm, for example, 9 nm. The thickness of the barrier layer 105 may be 15 nm or less, 20 nm or less, or 30 nm or less. The barrier layer 105 is not limited to AlGaN, and may be made of a group III nitride semiconductor such as AlInGaN. The barrier layer 105 may also contain n-type impurities.

[0032] By including Ga elements in the barrier layer 105, the lattice spacing of the barrier layer 105 is more easily relaxed than when the barrier layer 105 is made of AlN that does not include Ga elements. This makes it possible to prevent cracks and the like from occurring in the barrier layer 105. Furthermore, it is possible to prevent warpage of the wafer. This improves the quality of the semiconductor device 1.

[0033] A high concentration of 2DEG 107 is generated on the channel layer 103 side of the heterointerface between the barrier layer 105 and the channel layer 103 due to the piezoelectric stress of the barrier layer 105 on the channel layer 103. The 2DEG 107 is used as a channel of a transistor.

[0034] The cap layer 106 covers and contacts the upper surface of the barrier layer 105. The cap layer 106 is a layer made of a group III nitride semiconductor. The cap layer 106 is made of, for example, GaN. The thickness of the cap layer 106 is, for example, not less than about 1 nm and not more than about 2 nm. By providing the cap layer 106, oxidation of Al in the barrier layer 105 can be suppressed. Note that the cap layer 106 does not necessarily have to be provided.

[0035] The source electrode 201 and the drain electrode 202 are provided above the substrate 101 with a gap between them. Specifically, the source electrode 201 and the drain electrode 202 are provided so as to face each other with the gate electrode 203 sandwiched therebetween.

[0036] The source electrode 201 and the drain electrode 202 are formed using a conductive material. For example, the source electrode 201 and the drain electrode 202 are multilayer electrode films having a laminated structure in which a Ti film and an Al film are stacked in order, but this is not limited thereto. The source electrode 201 and the drain electrode 202 may be alloy layers formed by annealing a laminated structure of a Ti film and an Al film at a temperature of 500°C or higher. The source electrode 201 and the drain electrode 202 may also be a transition metal or a nitride or carbide of a transition metal. Specifically, the source electrode 201 and the drain electrode 202 may be Ta, Hf, W, Ni, TiN, TaN, HfN, WN, TiC, TaC, HfC, Au, Cu, etc., or may be a compound containing these elements, or may be a multilayer electrode film having a laminated structure.

[0037] The source electrode 201 and the drain electrode 202 are also called ohmic electrodes, and are electrically connected to the 2DEG 107 through an ohmic connection. In this embodiment, the source electrode 201 and the drain electrode 202 are provided so as to be in contact with the 2DEG 107.

[0038] Specifically, the semiconductor device 1 has two recesses that penetrate the cap layer 106 and the barrier layer 105 and reach the channel layer 103. The two recesses are also referred to as a source opening and a drain opening, respectively. The source electrode 201 is provided so as to contact and cover the inner surface of the source opening, and the drain electrode 202 is provided so as to contact and cover the inner surface of the drain opening. The bottom surface of each of the two recesses is located below the interface between the channel layer 103 and the barrier layer 105. Therefore, the 2DEG 107 is exposed on the side surface of each of the two recesses. The source electrode 201 and the drain electrode 202 are each in contact with the 2DEG 107 on the side surface of the recess. This reduces the channel contact resistance. Note that instead of the recesses, source contact regions and drain contact regions with low resistance may be provided by adding n-type impurities to portions of the cap layer 106, the barrier layer 105, and the channel layer 103. The source contact region and the drain contact region may be formed by, for example, plasma treatment, ion implantation, crystal regrowth, or the like.

[0039] The source electrode 201 and the drain electrode 202 are each covered with an insulating film (specifically, the insulating layer 305 before the openings are formed) during the manufacturing process of the semiconductor device 1. In order to ensure contact with the source electrode 201 and the drain electrode 202, openings are formed in the insulating layer 305, and wiring metals 206s and 206d are connected to the source electrode 201 and the drain electrode 202, respectively, through the openings. The wiring metals 206s and 206d are formed using, for example, low-resistance Au.

[0040] Furthermore, when the wiring metal 206s containing Au comes into contact with the source electrode 201 containing Al, a reaction between the materials may occur in a high-temperature environment. To avoid this reaction, a barrier metal 205s is provided between the source electrode 201 and the wiring metal 206s. Similarly, a barrier metal 205d is provided between the drain electrode 202 and the wiring metal 206d. The barrier metals 205d and 205s are formed using a material containing a high-melting-point metal that is unlikely to react even at high temperatures. For example, the barrier metals 205d and 205s are TiN films. Note that the barrier metals 205d and 205s and the wiring metals 206d and 206s do not necessarily have to be provided. For example, the source electrode 201 and the drain electrode 202 may also function as wiring.

[0041] The gate electrode 203 is provided above the barrier layer 105, between the source electrode 201 and the drain electrode 202, and spaced apart from each other. In this embodiment, the gate electrode 203 has a multilayer structure including a lower gate electrode portion 203L and an upper gate electrode portion 203U.

[0042] The gate electrode lower portion 203L is formed using a conductive material capable of forming a Schottky junction with a nitride semiconductor containing Ga. For example, the gate electrode lower portion 203L is formed using Ni, Ti, TiN, TaN, W, Pd, or the like. The gate electrode lower portion 203L is located at the bottom layer of the multi-layer gate electrode 203 and is in contact with the cap layer 106 and the insulating layer 300. The thickness of the gate electrode lower portion 203L is, for example, 10 nm to 50 nm, and is 50 nm as an example, but is not limited to this.

[0043] The upper gate electrode portion 203U is formed using a material having a lower resistivity than the lower gate electrode portion 203L. For example, the upper gate electrode portion 203U is formed using Au or Al. The upper gate electrode portion 203U is provided so as to contact and cover the upper surface of the lower gate electrode portion 203L. The thickness of the upper gate electrode portion 203U is, for example, 450 nm to 650 nm, and is 500 nm as an example, but is not limited to this. In a plan view, the shape and size of the upper gate electrode portion 203U are substantially the same as the shape and size of the lower gate electrode portion 203L.

[0044] In this way, by having the gate electrode 203 have a multilayer structure, it is possible to reduce the gate resistance Rg in the y-axis direction while ensuring a Schottky junction. The reduced gate resistance Rg can improve high-frequency gain. Note that the gate electrode 203 does not have to have a multilayer structure, and may have a single-layer structure formed using a conductive material that can form a Schottky junction with a nitride semiconductor containing Ga.

[0045] The gate electrode 203 has a so-called T-gate structure. Specifically, the gate electrode 203 includes a junction 203 a, a drain-side extension 203 d, and a source-side extension 203 s. The drain-side extension 203 d and the source-side extension 203 s are also called gate field plates.

[0046] The junction 203a forms a Schottky junction with the nitride semiconductor layer 104. Specifically, the junction 203a is a portion of the lower surface of the gate electrode lower portion 203L that is in contact with the cap layer 106. If the cap layer 106 is not provided, the junction 203a becomes a portion of the lower surface of the gate electrode lower portion 203L that is in contact with the barrier layer 105.

[0047] The drain side extension 203d is an example of a first extension, and is a portion that extends further toward the drain electrode 202 than the junction portion 203a. The drain side extension 203d corresponds to one arm of the T in the T-shaped gate structure.

[0048] The source-side protruding portion 203s is an example of a second protruding portion, and is a portion that protrudes further toward the source electrode 201 than the junction portion 203a. The source-side protruding portion 203s corresponds to one arm of the T in the T-shaped gate structure.

[0049] In this embodiment, the drain-side extending portion 203 d and the source-side extending portion 203 s have the same extending length. Specifically, the cross-sectional shape of the gate electrode 203 in the x-z cross section is symmetrical with respect to a line passing through the center of the junction 203 a and parallel to the z-axis.

[0050] The protrusion length of the protrusion is the distance along the x-axis direction from the starting point to the tip of the protrusion. The starting point of the protrusion can be regarded as the outline of the junction 203a in a plan view. The tip of the protrusion is the position farthest from the starting point in the protrusion direction of the protrusion. The protrusion direction is the positive direction of the x-axis for the drain-side protrusion 203d and the negative direction of the x-axis for the source-side protrusion 203s.

[0051] The drain-side extension 203d and the source-side extension 203s each have a multilayer structure of an upper gate electrode portion 203U and a lower gate electrode portion 203L, but are not limited to this. For example, the drain-side extension 203d and the source-side extension 203s may each have only the low-resistance upper gate electrode portion 203U. That is, the lower gate electrode portion 203L may be provided only in the portion where the gate electrode 203 contacts the cap layer 106 (or the barrier layer 105) (the portion corresponding to the junction 203a).

[0052] The distance along the x-axis from the drain side end of the junction 203a to the drain electrode 202 is called the gate-drain distance Lgd. The distance along the x-axis from the source side end of the junction 203a to the source electrode 201 is called the gate-source distance Lgs. In this embodiment, Lgs<Lgd. For example, Lgd is 3.2 μm and Lgs is 1.3 μm. By making the gate-drain distance Lgd longer than the gate-source distance Lgs, it is possible to alleviate the electric field concentration between the gate and the drain. Note that it is not essential to satisfy Lgs<Lgd; Lgs=Lgd or Lgs>Lgd may also be satisfied.

[0053] The source field plate 204 is provided above the gate electrode 203, and is set to the same potential as the source electrode 201. Specifically, the source field plate 204 is provided above the insulating layer 305. The source field plate 204 is provided so that at least a portion thereof is located between the gate electrode 203 and the drain electrode 202 in a planar view. In the example shown in FIG. 1 , the source field plate 204 is arranged so that a portion thereof overlaps the gate electrode 203 in a planar view. The source field plate 204 is electrically insulated from the gate electrode 203 and the drain electrode 202, and is set to the potential (source potential) applied to the source electrode 201.

[0054] During operation of the semiconductor device 1, a high voltage of approximately 100 V to 150 V is applied to the drain electrode 202. At this time, a high electric field is applied between the drain electrode 202 and the gate electrode 203. Specifically, electric field lines from the drain electrode 202 concentrate at the end of the drain-side extension 203 d of the gate electrode 203, increasing the peak value of the electric field and reducing reliability. By providing the source field plate 204, this peak value of the electric field can be reduced. The source field plate 204 can alleviate the high electric field peak by dispersing it in the x-axis direction. This improves the gate-drain breakdown voltage and reliability by suppressing gate leakage current.

[0055] The source field plate 204 is formed using a conductive material. The source field plate 204 has a multilayer electrode film configuration, for example, a laminated structure in which a TiN film and an Al film are stacked in order. The thickness of the source field plate 204 is, for example, 500 nm, but is not limited to this. The source field plate 204 is not limited to a laminated structure of a TiN film and an Al film, and may also be a transition metal nitride or carbide formed by sputtering. Specifically, the source field plate 204 may be made of Ti, Ta, W, Ni, TiN, TaN, WN, W, Au, Cu, etc., or a compound containing these elements, or a multilayer electrode film consisting of a multilayer structure. As an example, the source field plate 204 has a multilayer structure in which Ti, TiN, and Al are stacked in this order from the bottom up. Alternatively, the source field plate 204 may include Au in the top layer.

[0056] The insulating layer 305 is provided between the gate electrode 203 and the source field plate 204. Specifically, the insulating layer 305 is provided so as to cover the entire area of ​​the semiconductor device 1. The insulating layer 305 has openings for ensuring contact with each of the source electrode 201 and the drain electrode 202.

[0057] The insulating layer 305 is, for example, a Si layer having a thickness of 110 nm. ３ N ４ The insulating layer 305 is made of Si ３ N ４ Not limited to, SiO ２ , SiON may also be used. ３ N ４ Alternatively, the stress may be controlled by changing the composition ratio of Si or N. The insulating layer 305 and the source field plate 204 do not necessarily have to be provided.

[0058] The insulating layer 300 is provided above the nitride semiconductor layer 104, between the gate electrode 203 and the drain electrode 202. Specifically, the insulating layer 300 contacts and covers the upper surface of the cap layer 106 between the gate electrode 203 and the drain electrode 202. The insulating layer 300 is provided over the entire range from the drain-side end of the junction 203 a to the drain electrode 202.

[0059] In this embodiment, the insulating layer 300 is also provided between the gate electrode 203 and the source electrode 201. Specifically, the insulating layer 300 contacts and covers the upper surface of the cap layer 106 between the gate electrode 203 and the source electrode 201. The insulating layer 300 is provided over the entire range from the source-side end of the junction 203 a to the source electrode 201.

[0060] The insulating layer 300 has a laminated structure of a plurality of insulating layers. Specifically, the insulating layer 300 is an in-situ Si ３ N ４ Film 301 and Ex-situ Si ３ N ４ and a membrane 302.

[0061] In-situ Si ３ N ４ The film 301 is an example of a first insulating film made of silicon nitride, and is located between the drain-side extension 203d and the nitride semiconductor layer 104, and covers and contacts the nitride semiconductor layer 104. ３ N ４ The film 301 overlaps the drain-side protrusion 203d in plan view. ３ N ４ The film 301 is the bottom layer of the insulating layer 300 having a laminated structure. ３ N ４ The film 301 contacts and covers the cap layer 106 between the gate electrode 203 and the drain electrode 202 over the entire area from the drain-side end of the junction 203 a to the drain electrode 202 .

[0062] In addition, in this embodiment, in-situ Si ３ N４ The film 301 is also provided between the gate electrode 203 and the source electrode 201. ３ N ４ The film 301 overlaps the source-side protrusion 203s in plan view. ３ N ４ The film 301 contacts and covers the cap layer 106 over the entire area ranging from the source side end of the junction 203 a to the source electrode 201 .

[0063] Ex-situ Si ３ N ４ The film 302 is an example of a second insulating film made of silicon nitride, and is formed between the drain-side extension 203d and the in-situ Si ３ N ４ It is located between the film 301. Specifically, ex-situ Si ３ N ４ The film 302 overlaps the drain side protrusion 203d in plan view and is in contact with the lower surface of the drain side protrusion 203d. ３ N ４ The film 302 is formed by in-situ Si deposition over the entire area from the drain side end of the junction 203a to the drain electrode 202. ３ N ４ It contacts and covers the membrane 301 .

[0064] In this embodiment, ex-situ Si ３ N ４ The film 302 is also provided between the gate electrode 203 and the source electrode 201. Specifically, the ex-situ Si ３ N ４ The film 302 overlaps the source-side overhang 203s in plan view and is in contact with the lower surface of the source-side overhang 203s. ３ N ４ The film 302 is formed by in-situ Si deposition over the entire area from the source side end of the junction 203a to the source electrode 201. ３ N ４ It contacts and covers the membrane 301 .

[0065] In-situ Si ３ N ４ The thickness of the film 301 is, for example, 15 nm or more, but may be 20 nm or more. ３ N ４ The thickness of the film 301 is 30 nm or less, but may be 25 nm or less. ３ N ４ The film 301 has a substantially uniform thickness.

[0066] Ex-situ Si ３ N ４ The film 302 has a thickness of, for example, 30 nm or more and 60 nm or less. ３ N ４ The thickness of the film 302 is determined by In-situ Si ３ N ４ The thickness is equal to or greater than the thickness of the film 301. In this embodiment, the ex-situ Si ３ N ４ The film 302 has a substantially uniform thickness.

[0067] In-situ Si ３ N ４ Film 301 and Ex-situ Si ３ N ４ The manufacturing methods for the film 302 are different. ３ N ４ The film 301 is formed continuously after epitaxial growth of the nitride semiconductor without exposure to the atmosphere. ３ N ４ The film 301 is a film continuously laminated on a nitride semiconductor layer grown in an epitaxial growth furnace, such as a MOCVD (Metal Organic Chemical Vapor Deposition) furnace.

[0068] In contrast, ex-situ Si ３ N ４ The film 302 is in-situ Si ３ N ４After the formation of the film 301, the film is removed from the epitaxial growth furnace and exposed to the atmosphere. ３ N ４ The film 302 is formed by, for example, a low-pressure chemical vapor deposition (LPCVD) method.

[0069] Due to differences in manufacturing methods, in-situ Si ３ N ４ Film 301 and Ex-situ Si ３ N ４ The film quality is different from that of the film 302. Specifically, the in-situ Si ３ N ４ The film 301 is ex-situ Si ３ N ４ It is a film denser than the film 302. For example, in-situ Si ３ N ４ The film density of the film 301 is ３ N ４ The film density is greater than that of the film 302 .

[0070] In addition, in-situ Si ３ N ４ Film 301 and Ex-situ Si ３ N ４ A difference occurs in at least one of the halogen concentration and the interface oxygen concentration between the film 302 and the film 302. For example, in this embodiment, (a) In-situ Si ３ N ４ The halogen concentration of the film 301 is Ex-situ Si ３ N ４ (b) the halogen concentration is lower than that of the film 302; and ３ N ４ The oxygen concentration at the interface between the film 301 and the nitride semiconductor layer 104 is in-situ Si ３ N ４ Film 301 and Ex-situ Si ３ N ４ The oxygen concentration at the interface with the film 302 is lower than that at the interface with the film 302. ３ N ４ The halogen concentration of the film 301 is 1×10１８ atom / cm ３ and Ex-situ Si ３ N ４ The halogen concentration of the film 302 is 1×10 １８ atom / cm ３ and (d) In-situ Si ３ N ４ The oxygen concentration at the interface between the film 301 and the nitride semiconductor layer 104 is 1×10 ２０ atom / cm ３ and In-situ Si ３ N ４ Film 301 and Ex-situ Si ３ N ４ The oxygen concentration at the interface with the film 302 is 1×10 ２０ atom / cm ３ It satisfies at least one of the following:

[0071] Table 1 shows the in-situ Si ３ N ４ and Ex-situ Si ３ N ４ The halogen concentration and the interface oxygen concentration are shown. ３ N ４ and Ex-situ Si ３ N ４ 1 shows the results of composition analysis by secondary ion mass spectroscopy (SIMS) for the laminated structure of Example 1. The halogen concentration is specifically the chlorine (Cl) concentration.

[0072]

[0073] As can be seen from Table 1, in-situ Si ３ N ４ The film 301 is characterized by a low halogen concentration and a low oxygen concentration at the interface with the epitaxially grown semiconductor (the cap layer 106 in this embodiment). This is because the film is a laminated film grown in an epitaxial growth furnace and is not exposed to air. After epitaxial growth, the film is exposed to Cl 2 contained in the ambient air of the process site in the clean room. ２This is because halogens such as Cl and oxygen are difficult to incorporate. ２ is used as a dry etching gas in the process, and a small amount of it may unintentionally enter the atmosphere.

[0074] In this way, in-situ Si with little impurities such as halogen or oxygen ３ N ４ The film 301 has the effect of reducing the interface state with the semiconductor and reducing the influence on the 2DEG 107. These effects also result in high collapse resistance. ３ N ４ By providing the film 301 on the nitride semiconductor layer 104, good collapse characteristics can be realized, and high drive current characteristics can be obtained.

[0075] FIG. 2 shows the Si ３ N ４ 2 is a diagram showing the relationship between the film thickness and the carrier concentration of the 2DEG 107. ３ N ４ The case where a film was formed on the nitride semiconductor layer 104 (Example) and the case where an ex-situ Si ３ N ４ 2, the horizontal axis represents the Si ３ N ４ The vertical axis represents the film thickness, and the vertical axis represents the carrier concentration of the 2DEG 107 obtained by Hall measurement.

[0076] As shown in FIG. ３ N ４ The film is ex-situ Si ３ N ４ Since the carrier concentration is significantly higher than that of the in-situ Si film, the saturation current of the transistor is higher. The higher the saturation current, the higher the output power and gain characteristics of the transistor. ３ N ４ The thicker the film, the higher the carrier concentration and the higher the saturation current, which can improve the high output and gain characteristics of the transistor.

[0077] On the other hand, in-situ Si ３ N ４ If the film thickness is large, warping of the wafer becomes a problem. ３ N ４ 3 is a graph showing the relationship between the film thickness and the warpage of the wafer. ３ N ４ The vertical axis represents the thickness of the film, and the vertical axis represents the amount of warpage of the wafer. Note that Figure 3 shows the measurement results for a 6-inch wafer.

[0078] As shown in FIG. ３ N ４ Films and Ex-situ Si ３ N ４ In either case, the larger the film thickness, the greater the amount of warping of the wafer. When the amount of warping of the wafer increases, cracks may occur on the periphery of the wafer, deteriorating the quality of the semiconductor device 1. For this reason, the Si ３ N ４ It is necessary to set an upper limit (critical film thickness) for the film thickness. For example, in the case of a 6-inch wafer, the film thickness when the amount of warpage of the wafer becomes 15 μm is regarded as the critical film thickness, as shown in FIG. 3. In this case, the in-situ Si ３ N ４ The critical thickness of the film is 25 nm.

[0079] When compared at the same film thickness, In-situ Si ３ N ４ The amount of warpage when the ex-situ Si film is provided is ３ N ４ In other words, from the viewpoint of suppressing wafer warpage, the amount of warpage is larger than that when an in-situ Si film is provided. ３ N ４ Ex-situ Si ３ N ４ It can be seen that the membrane is more advantageous.

[0080] Therefore, in this embodiment, the insulating layer 300 provided on the nitride semiconductor layer 104 is an in-situ Si ３ N ４ Film 301 and Ex-situ Si３ N ４ This provides a laminated structure with the in-situ Si ３ N ４ Compared with the case where the film 301 is provided alone, the ex-situ Si ３ N ４ The provision of the film 302 increases the piezoelectric stress, thereby increasing the electron carrier concentration in the 2DEG 107. As a result, the saturation current of the transistor can be increased. Note that the saturation current is determined by the saturation velocity of electrons, and therefore depends more on the electron carrier concentration than on the mobility, which has a greater effect at low voltages. In this way, this embodiment can achieve high drive current characteristics and low wafer warpage characteristics.

[0081] As shown in FIG. 3, in order to suppress the amount of warpage of the wafer, ex-situ Si ３ N ４ There is also an upper limit (critical thickness) to the film thickness. ３ N ４ The critical thickness of the film is 60 nm. ３ N ４ Film 301 and Ex-situ Si ３ N ４ Since it has a laminated structure with the film 302, in-situ Si ３ N ４ The thickness of the film 301 is T ｉｎ and Ex-situ Si ３ N ４ The thickness of the film 302 is T ｅｘ In this case, the following formula (1) is satisfied.

[0082] (1) f(T ｉｎ ) + g(T ｅｘ )≦15 μm

[0083] Note that f(T ｉｎ ) is In-situ Si ３ N ４ The thickness T of the film 301 ｉｎ is a function that expresses the relationship between the amount of warpage of the wafer and the ｅｘ ) is ex-situ Si ３ N４ The thickness T of the film 302 ｉｎ is a function that represents the relationship between the wafer warpage and T ｉｎ is 25 nm or less, and T ｅｘ is 60 nm or less. ｉｎ and T ｅｘ By increasing the piezo stress by increasing the .theta., it is possible to realize a high drive current characteristic and a low wafer warpage characteristic.

[0084] As mentioned above, in-situ Si ３ N ４ The film 301 is effective against the collapse phenomenon. ３ N ４ The effect of the membrane 302 on the collapse phenomenon is explained below.

[0085] In-situ Si ３ N ４ The film 301 is stacked until the influence of the epitaxial surface disappears, and then ex-situ Si ３ N ４ Even if the film 302 is laminated, the collapse deterioration is small. ３ N ４ The film 302 has a large number of impurity levels, but also has a characteristic that the film has a large leakage current. ３ N ４ A mechanism of conduction occurs in which electrons hop between impurity levels along the leakage current flowing through the film 302. As a result, fewer electrons are effectively captured in the impurity levels and remain as fixed charges, thereby suppressing the collapse phenomenon.

[0086] In addition, in-situ Si ３ N ４ The film 301 is ex-situ Si ３ N ４ Although it is less than the film 302, it has a certain amount of impurity levels. ３ N ４ There is a risk that electrons may be trapped in the impurity level of the film 301. In contrast, in this embodiment,３ N ４ Ex-situ Si deposited on the film 301 ３ N ４ Through the leak path of the film 302, the in-situ Si ３ N ４ It is possible to conduct electrons trapped in the impurity level of the film 301. In this respect, the in-situ Si ３ N ４ The laminated structure is more effective in suppressing the collapse phenomenon than providing the film 301 alone, and can improve the driving current characteristics.

[0087] In addition, ex-situ Si ３ N ４ If the film 302 is provided directly on the epitaxial surface, the leakage current will be too large to be ignored. ３ N ４ A film 301 is provided, and an in-situ Si ３ N ４ Ex-situ Si on the film 301 ３ N ４ By providing the film 302, it is possible to achieve high drive current characteristics and low wafer warpage characteristics.

[0088] In addition, in-situ Si ３ N ４ Film 301 and Ex-situ Si ３ N ４ The layered structure with the film 302 can increase the distance between the drain-side protruding portion 203d of the gate electrode 203 and the 2DEG 107. This can reduce the gate-drain capacitance Cgd, thereby improving the gain.

[0089] (Embodiment 2) Next, embodiment 2 will be described. In embodiment 2, ex-situ Si ３ N ４ SiO on the film ２ The provision of the film is the main difference from embodiment 1. The following description will focus on the differences from embodiment 1, and description of commonalities will be omitted or simplified.

[0090] 4 is a cross-sectional view of the semiconductor device 2 according to the present embodiment. As shown in FIG. 4, the semiconductor device 2 is different from the semiconductor device 1 shown in FIG. 1 in that the insulating layer 300 is made of SiO ２ The difference is that it further includes a membrane 303 .

[0091] SiO ２ The film 303 is an example of a third insulating film made of silicon oxide, and is formed between the drain-side extension 203d and the ex-situ Si ３ N ４ It is located between the film 302. ２ The film 303 is the top layer of the insulating layer 300 having a laminated structure. ２ The film 303 is in contact with the drain-side protrusion 203d. ２ The film 303 overlaps the drain side extension 203d in a plan view and is in contact with the lower surface of the drain side extension 203d. ２ The film 303 is formed between the gate electrode 203 and the drain electrode 202, and is formed by ex-situ Si ３ N ４ It contacts and covers the membrane 302 .

[0092] In this embodiment, SiO ２ The film 303 is also provided between the gate electrode 203 and the source electrode 201. Specifically, the film 303 is made of SiO ２ The film 303 overlaps the source side extension 203s in plan view and is in contact with the lower surface of the source side extension 203s. ２ The film 303 is formed by ex-situ Si in the entire area ranging from the source side end of the junction 203a to the source electrode 201. ３ N ４ It contacts and covers the membrane 302 .

[0093] SiO ２ The thickness of the film 303 is, for example, 10 nm to 100 nm, for example, 50 nm. ２ The film 303 has a substantially uniform thickness.

[0094] Si３ N ４ The relative dielectric constant of SiO is about 7. ２ The relative dielectric constant of SiO is about 4. ２ The film 303 is made of in-situ Si ３ N ４ Film 301 and Ex-situ Si ３ N ４ The dielectric constant of the SiO film 302 is lower than that of the SiO film 302. ２ The gate-drain capacitance Cgd can be reduced by providing the film 303. The reduced gate-drain capacitance Cgd can improve the high frequency gain characteristics and efficiency performance of the transistor.

[0095] Third Embodiment Next, a third embodiment will be described. The second embodiment is mainly different from the first embodiment in that a sidewall structure is provided at the gate portion. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0096] 5 is a cross-sectional view of the semiconductor device 3 according to the present embodiment. As shown in FIG. 5, the semiconductor device 3 is different from the semiconductor device 1 shown in FIG. 1 in that the insulating layer 300 is formed by the sidewalls 304d and 304s and the ex-situ Si ３ N ４ 3. The difference is that it further includes a membrane 306.

[0097] The sidewall 304d is formed by in-situ Si ３ N ４ The sidewall 304d is a drain-side sidewall, and is formed between the junction 203a and the in-situ Si ３ N ４ It is provided between the drain electrode 202 and the portion of the film 301 on the drain electrode 202 side.

[0098] The sidewall 304s is formed by an in-situ Si ３ N ４The sidewall 304s is a sidewall on the source side, and is formed between the junction 203a and the in-situ Si ３ N ４ It is provided between the source electrode 201 and the portion of the film 301 on the source electrode 201 side.

[0099] The sidewalls 304d and 304s are both made of silicon nitride. Specifically, the sidewalls 304d and 304s are made of ex-situ silicon nitride. ３ N ４ and are formed in the same process.

[0100] The film quality of each of the sidewalls 304d and 304s is ex-situ Si. ３ N ４ The film quality is different from that of the film 302. Specifically, the sidewalls 304d and 304s are made of ex-situ Si ３ N ４ The film is denser than the film 302. For example, the film density of each of the sidewalls 304d and 304s is ３ N ４ The film density is smaller than that of the film 302. The sidewalls 304d and 304s are made of ex-situ Si ３ N ４ This film is formed in a different process from that of the film 302. The specific method of formation will be described later.

[0101] Ex-situ Si ３ N ４ The film 306 is ex-situ Si ３ N ４ It is provided above the film 302. Specifically, ex-situ Si ３ N ４ The film 306 is provided at a position that does not overlap the drain-side protruding portion 203d of the gate electrode 203 in a plan view. ３ N ４ The film 306 is provided so as to be in contact with the drain electrode 202 .

[0102] In addition, ex-situ Si ３ N ４The film 306 is also provided on the source electrode 201 side. ３ N ４ The film 306 is provided at a position that does not overlap the source-side protruding portion 203s of the gate electrode 203. More specifically, the ex-situ Si ３ N ４ The film 306 is provided so as to be in contact with the source electrode 201 .

[0103] Ex-situ Si ３ N ４ The film quality of the film 306 is ex-situ Si ３ N ４ The film quality is different from that of the film 302. Specifically, ex-situ Si ３ N ４ The film 306 is ex-situ Si ３ N ４ It is a film that is more sparse than film 302. For example, ex-situ Si ３ N ４ The film density of the film 306 is ３ N ４ The film density is smaller than that of the film 302. ３ N ４ The film 306 can be formed in the same process as the sidewalls 304d and 304s.

[0104] Ex-situ Si ３ N ４ By providing the film 306, the insulating layer 300 has a larger film thickness in the vicinity of the drain electrode 202 than in the vicinity of the gate electrode 203. ３ N ４ More electric charges are generated by piezoelectric polarization directly below the film 306. ３ N ４ The carrier concentration of the 2DEG 107 increases directly below the film 306. ３ N ４Since the film 306 is provided so as to be in contact with the drain electrode 202, the carrier concentration of the portion of the 2DEG 107 that is in contact with the drain electrode 202 increases. This reduces the contact resistance between the drain electrode 202 and the 2DEG 107. This reduces the on-resistance, thereby achieving high drive current characteristics.

[0105] In addition, ex-situ Si ３ N ４ The film 306 is provided so as to be in contact with the source electrode 201 as well, thereby reducing the contact resistance between the source electrode 201 and the 2DEG 107. This reduces the on-resistance, thereby achieving high drive current characteristics.

[0106] In addition, ex-situ Si ３ N ４ The film 306 may be formed in a different process from the sidewalls 304d and 304s. ３ N ４ The film quality of the film 306 is ex-situ Si ３ N ４ The film quality may be the same as that of the film 302. Alternatively, ex-situ Si ３ N ４ The film 306 is ex-situ Si ３ N ４ It may be a film denser than the film 302. ３ N ４ The membrane 306 may not be provided.

[0107] In this embodiment, the side walls 304d and 304s are made of ex-situ Si. ３ N ４ Since it is formed using In-situ Si ３ N ４ A difference occurs in at least one of the halogen concentration and the interface oxygen concentration between the film 301 and the sidewalls 304d and 304s. ３ N ４ (b) the halogen concentration of the film 301 is lower than that of the sidewalls 304d and 304s; and３ N ４ The oxygen concentration at the interface between the film 301 and the nitride semiconductor layer 104 is lower than the oxygen concentration at the interface between the sidewalls 304d and 304s and the nitride semiconductor layer 104. Specifically, (c) In-situ Si ３ N ４ The halogen concentration of the film 301 is 1×10 １８ atom / cm ３ and the halogen concentration of the sidewalls 304d and 304s is less than 1×10 １８ atom / cm ３ and (d) In-situ Si ３ N ４ The oxygen concentration at the interface between the film 301 and the nitride semiconductor layer 104 is 1×10 ２０ atom / cm ３ and the oxygen concentration at the interface between the sidewalls 304d and 304s and the nitride semiconductor layer 104 is less than 1×10 ２０ atom / cm ３ In addition, the ex-situ Si ３ N ４ Membrane 306 and In-situ Si ３ N ４ A similar relationship holds true for membrane 301 .

[0108] When the sidewalls 304d and 304s are not provided, in-situ Si ３ N ４ Film 301 and Ex-situ Si ３ N ４ The width of the gate opening formed by removing a part of the film 302 corresponds to the gate length Lg. Therefore, it is not possible to realize a gate length Lg smaller than the minimum value of the processing limit of the gate opening.

[0109] In contrast, in the semiconductor device 3 according to this embodiment, the sidewalls 304d and 304s are provided, thereby enabling the gate length Lg to be shortened. For example, the gate length Lg can be set to 0.25 μm or less. The gate length Lg is the length of the junction 203a along the arrangement direction (x-axis direction) of the source electrode 201, gate electrode 203 (specifically, junction 203a), and drain electrode 202. For example, the length of each of the sidewalls 304d and 304s in the x-axis direction can be set to 0.10 μm, enabling Lg to be set to 0.19 μm. In other words, the gate length Lg can be shortened to approximately half of the width of the gate opening of 0.39 μm.

[0110] By shortening the gate length Lg, a phenomenon called a short channel effect, in which it becomes difficult to cut off (pinch off) the drive current when turned off, can become a problem in the direction directly below the gate electrode 203. In this embodiment, both the sidewalls 304d and 304s are made of ex-situ Si ３ N ４ Therefore, in-situ Si ３ N ４ The piezoelectric stress is weaker than that of the gate electrode 203. Therefore, the piezoelectric charge directly below the sidewalls 304d and 304s is reduced in the 2DEG 107. As a result, the width of the 2DEG 107 in the z-axis direction is narrowed, and the current blocking (pinch-off) characteristics during modulation of the gate electrode 203 are improved.

[0111] (Fourth embodiment) Next, a fourth embodiment will be described. In the fourth embodiment, ３ N ４ SiO on the film ２ The main difference between the third embodiment and the second embodiment is that a sidewall structure is provided at the gate portion of the fourth embodiment. The following description will focus on the differences with the second or third embodiment, and the description of the commonalities will be omitted or simplified.

[0112] 6 is a cross-sectional view of a semiconductor device 4 according to the present embodiment. As shown in FIG. 6, the semiconductor device 4 is different from the semiconductor device 3 shown in FIG. 5 in that the insulating layer 300 is made of SiO ２ The difference is that it further includes a membrane 303 .

[0113] SiO ２ The film 303 is made of SiO contained in the insulating layer 300 of the semiconductor device 2 according to the second embodiment. ２ The film 303 is the same as the film 303. Therefore, according to the semiconductor device 4 of this embodiment, similarly to the second embodiment, it is possible to reduce the gate-drain capacitance Cgd and improve the high frequency gain characteristics and efficiency performance. Specifically, this is useful when handling signals in a frequency band of 5 GHz or more.

[0114] Furthermore, according to the semiconductor device 4 of this embodiment, as in the third embodiment, ex-situ Si ３ N ４ Therefore, the current blocking (pinch-off) characteristics during modulation of the gate electrode 203 are improved.

[0115] Next, data measured on a prototype of the semiconductor device 4 according to this embodiment will be described with reference to FIGS. 7 and 8. FIG. 7 shows the in-situ Si ３ N ４ The thickness T of the film 301 ｉｎ and the thickness T of the barrier layer 105 ｂａ 8 is a cross-sectional view of the semiconductor device 4 for supplementary explanation of the current characteristics shown in FIG.

[0116] In Figure 7, the values ​​written next to the plots in each figure indicate the saturation current value in the upper row and the leakage current value between the gate and drain in the lower row. Table 2 below shows the data shown in Figure 7.

[0117]

[0118] The gate length Lg of each sample was set to 0.25 μm. The barrier layer 105 was made of Al ｘ Ga １－ｘThe film was an N film, and the Al composition ratio x was set to 0.28. The saturation current was a value obtained by measuring the current flowing from the drain electrode 202 to the source electrode 201 when a drain voltage of 5 V was applied between the drain electrode 202 and the source electrode 201. The leakage current was a value obtained by measuring the leakage current flowing from the drain electrode 202 to the gate electrode 203 when the potential difference between the drain electrode 202 and the gate electrode 203 was 150 V. The gate-drain distance Lgd was set to 3 μm. The longer Lgd is, the more the electric field concentration is alleviated, reducing the leakage current, but there is a problem in that the on-resistance increases.

[0119] When the semiconductor device 4 is applied to a power amplifier, it is desirable that the saturation current is high and the leakage current is low. Generally, a semiconductor device with a saturation current of 920 mA / mm or more and a leakage current of 10 μA / mm or less is suitable for a power amplifier.

[0120] In-situ Si ３ N ４ The thickness T of the film 301 ｉｎ and the thickness T of the barrier layer 105 ｂａ Under these conditions, it is possible to achieve both a high saturation current and a low leakage current, which have traditionally been in a contradictory relationship. This mechanism will be explained below using Table 3 and referring to FIG. 8. Table 3 shows the characteristics of regions 601 to 603 shown in FIG. 8.

[0121]

[0122] First, attention is focused on region 601. Region 601 is a region directly below junction 203a, which is the contact surface between gate electrode 203 and nitride semiconductor layer 104. In region 601, the thinner the barrier layer 105, the weaker the piezoelectric stress of the barrier layer 105 on the channel layer 103. As a result, leakage current can also be suppressed. In other words, it is desirable to thin the barrier layer 105 directly below junction 203a of gate electrode 203.

[0123] However, since the barrier layer 105 is thinned even in the region 603 between the gate and drain, which is the main region through which electron carriers travel, a high saturation current cannot be expected in this state. Therefore, in the present disclosure, in the region 603, the thinned barrier layer 105 is thinned by in-situ Si ３ N ４ The film 301 is laminated. ３ N ４ By utilizing the high piezoelectric stress of the film 301, the carrier concentration of the 2DEG 107 can be increased, and the drain current can be increased.

[0124] As explained with reference to FIGS. 2 and 3, in-situ Si ３ N ４ Since there is a limit to the thickness of the film 301 alone, ex-situ Si ３ N ４ The film 302 is then laminated, thereby realizing a high saturation current while suppressing wafer warpage.

[0125] When the sidewalls 304s and 304d are provided and the gate length Lg is short as in this embodiment, a short channel effect occurs. Specifically, a high drain current flows from the drain electrode 202 side to the region 601, making it difficult to block it with the gate electrode 203. This is a phenomenon called punch-through due to gate shortening.

[0126] Therefore, in the semiconductor device 4 according to the present embodiment, the sidewalls 304s and 304d of the region 602 are formed by ex-situ Si ３ N ４ As a result, the piezoelectric effect can be weakened in the region 602, making it possible to cut off a high drain current.

[0127] As described above, according to the semiconductor device 4 of this embodiment, the barrier layer 105, the in-situ Si ３ N ４ Membrane 301, Ex-situ Si ３ N ４The film 302 and the sidewalls 304s and 304d realize a structure in which the advantages and disadvantages of each film are complemented. This makes it possible to achieve both a high saturation current and a low leakage current, which have traditionally been contradictory, and also to achieve low wafer warpage. In other words, the semiconductor device 4 according to this embodiment can provide a GaN HEMT that has high performance and high reliability with low leakage current. Note that although the semiconductor device 4 is given as an example, the same applies to the semiconductor devices 1 to 3 according to the first to third embodiments.

[0128] Referring to FIG. 7 and Table 2, in terms of the saturation current of 920 mA / mm or more, the In-situ Si ３ N ４ The thickness T of the film 301 ｉｎ In addition, from the viewpoint of wafer warpage, the film thickness T ｉｎ From the viewpoint of a leakage current of 10 μA / mm or less, the thickness T ｂａ must be 10 nm or less.

[0129] From the above, it can be seen that in-situ Si ３ N ４ The thickness T of the film 301 ｉｎ is in the range of 10 nm to 25 nm, and the thickness T ｂａ By keeping the thickness of the in-situ Si film at 10 nm or less, it is possible to achieve both a high saturation current and a low leakage current, and to realize low wafer warpage. ３ N ４ The thickness T of the film 301 ｉｎ The thickness T of the barrier layer 105 may be smaller than 10 nm or may be larger than 25 nm. ｂａ may be greater than 10 nm and less than 7 nm.

[0130] (Manufacturing Method) Next, a manufacturing method for the semiconductor devices 1 to 4 according to the above-described first to fourth embodiments will be described.

[0131] The manufacturing method of semiconductor devices 1 to 4 includes a first step of forming, in order, a channel layer 103 and a nitride semiconductor layer 104 including a barrier layer 105 above a substrate 101 by epitaxial growth; a second step of forming an insulating layer 300 so as to cover the nitride semiconductor layer 104; a third step of removing a part of the insulating layer 300 to expose a part of the nitride semiconductor layer 104; a fourth step of forming a source electrode 201 and a drain electrode 202 above the substrate 101 at a distance from each other; and a fifth step of forming a gate electrode 203 between the source electrode 201 and the drain electrode 202 at a distance from each other so as to be in contact with the exposed part of the nitride semiconductor layer 104 and to cover a part of the insulating layer 300 that is located closer to the drain electrode 202 than the exposed part.

[0132] The second step is to form an in-situ Si film that covers the nitride semiconductor layer 104 in contact with the nitride semiconductor layer 104 without exposing it to the atmosphere after the first step. ３ N ４ A process of forming a film 301 and an in-situ Si ３ N ４ After forming the film 301, the film is exposed to the atmosphere and then in-situ Si ３ N ４ Ex-situ Si film 301 ３ N ４ and forming a film 302.

[0133] 9A to 9K, which are cross-sectional views illustrating a step in the manufacturing method of semiconductor device 3 according to the third embodiment.

[0134] The manufacturing method of semiconductor device 3 described below is the core of the manufacturing methods of semiconductor devices 1, 2, and 4 according to other embodiments. Each of semiconductor devices 1, 2, and 4 can be easily manufactured by simply omitting or modifying part of the manufacturing method of semiconductor device 3 described below.

[0135] First, as shown in FIG. 9A , a GaN wafer is prepared by epitaxially growing a nitride semiconductor. More specifically, a buffer layer 102, a channel layer 103, a barrier layer 105, and a cap layer 106 are sequentially formed on a substrate 101. For example, nitride semiconductors such as GaN and AlGaN are epitaxially grown in this order. The epitaxial growth is performed in a growth furnace based on, for example, the MOCVD method. The buffer layer 102, the channel layer 103, the barrier layer 105, and the cap layer 106 can be formed by adjusting the type and flow rate of the introduced gas.

[0136] Furthermore, following the formation of the cap layer 106, an in-situ Si ３ N ４ Specifically, after the epitaxial growth of the nitride semiconductor, silicon nitride is epitaxially grown in the same growth furnace without exposure to the atmosphere. As a result, an in-situ Si ３ N ４ Since the upper surface of the cap layer 106 (nitride semiconductor layer 104) is not exposed to the atmosphere, an in-situ Si ３ N ４ The oxygen concentration at the interface between the film 301 and the cap layer 106 is reduced. ３ N ４ The halogen concentration in the film 301 is reduced.

[0137] Next, as shown in FIG. 9B, in-situ Si ３ N ４ Ex-situ Si on the film 301 ３ N ４ A film 302 is formed. Specifically, an in-situ Si ３ N ４ The GaN wafer on which the film 301 is formed is taken out of the growth furnace, and the GaN wafer is exposed to the atmosphere. ３ N ４ After cleaning the upper surface of the film 301 with an acid such as hydrofluoric acid, ex-situ Si ３ N ４ Forming a film 302. Ex-situ Si３ N ４ The film 302 is formed by, for example, low pressure chemical vapor deposition (LPCVD).

[0138] The film formation temperature in the LPCVD method is about 800° C. Therefore, ex-situ Si formed by the LPCVD method ３ N ４ The film density of the film 302 is determined by In-situ Si ３ N ４ Although the film density is lower than that of the film 301, the Si film is formed by the plasma CVD method at a temperature of about 300°C to 500°C. ３ N ４ Therefore, ex-situ Si ３ N ４ The film 302 also has a medium stress. ３ N ４ The film 301 has a critical thickness due to wafer warpage, so it is more useful as a film that compensates for piezoelectric stress. ３ N ４ The film 302 is a Si film formed by ordinary plasma CVD. ３ N ４ It goes without saying that it may be a membrane.

[0139] Next, although not shown in the figure, boron ions (B ＋ By implanting ions that passivate nitride semiconductors such as GaN, regions other than the transistor formation region (also called the active region) are passivated, enabling electrical isolation between elements within the GaN wafer.

[0140] Next, as shown in Figure 9C, a source electrode 201 and a drain electrode 202 are formed. Note that the following Figures 9C to 9K only show one transistor formation region in the GaN wafer. In each figure, the unillustrated portions to the left of the source electrode 201 (negative side of the x-axis) and to the right of the drain electrode 202 (positive side of the x-axis) become insulating isolation regions. The same applies to Figures 10B and 10C, which will be described later.

[0141] In the process of forming the source electrode 201 and the drain electrode 202, first, ex-situ Si ３ N ４ Film 302 and In-situ Si ３ N ４ A portion of each of the films 301 is removed by etching to form an opening (contact hole). Furthermore, following the formation of the contact hole, the cap layer 106, the barrier layer 105, and the channel layer 103 are etched away until the 2DEG 107 is exposed, thereby forming a recess. The etching is performed by, for example, dry etching. A metal film is deposited by sputtering or vapor deposition so as to cover the inner surface of the recess, and then the metal film is patterned to form the source electrode 201 and the drain electrode 202. The patterning is performed by, for example, etching or lift-off. The semiconductor and the metal are then alloyed at a temperature of approximately 500° C. to 600° C., thereby bringing the source electrode 201 and the drain electrode 202 into ohmic contact with the channel layer 103.

[0142] 9D, a gate opening is formed in the gate region 401 for forming a gate. The length of the gate region 401 in the x-axis direction is, for example, 0.39 μm. ３ N ４ A positive photoresist is applied onto the film 302, and a gate region 401 is opened in the applied photoresist. ４ By dry etching with plasma ions containing ３ N ４ Film 302 and In-situ Si ３ N ４ The portions of each of the films 301 exposed in the gate regions 401 are removed.

[0143] Next, as shown in FIG. 9E, ex-situ Si is deposited on the entire surface including the opening of the gate region 401. ３ N ４ A film 307 is formed. Ex-situ Si ３ N ４The film 307 is formed by, for example, a plasma CVD method, but may also be formed by an LPCVD method. ３ N ４ The film 307 is formed on the sidewalls 304s and 304d and on the ex-situ Si ３ N ４ This is a silicon nitride film that is the basis of the film 306. Specifically, ex-situ Si ３ N ４ The film 307 is in-situ Si ３ N ４ Film 301 and Ex-situ Si ３ N ４ The film is formed to the same thickness as the total film thickness of the film 302. For example, in-situ Si ３ N ４ The film 301 has a thickness of 20 nm and is ex-situ Si ３ N ４ When the thickness of the film 302 is 30 nm, the ex-situ Si ３ N ４ The thickness of the film 307 is set to 50 nm. By making the film thickness uniform, the height of the sidewalls 304s and 304d and the in-situ Si ３ N ４ Film 301 and Ex-situ Si ３ N ４ The height (total film thickness) of the film 302 can be made uniform.

[0144] Next, as shown in FIG. 9F, a photoresist 501 having an opening of a predetermined shape is formed, and then a CF ４ By performing anisotropic dry etching with plasma ions containing ３ N ４ The photoresist 501 is shaped to cover the source electrode 201 and the drain electrode 202, but not to cover at least the gate region 401. The etching amount is determined by the amount of the deposited ex-situ Si ３ N ４ The thickness of the film 307 is, for example, 50 nm. The photoresist 501 is a positive type, but may also be a negative type.

[0145] As a result of the anisotropic etching, sidewalls 304s and 304d are formed, as shown in Figure 9G. The sidewalls 304s and 304d are formed by ex-situ Si ３ N ４ This is the portion of the film 307 that remains unremoved along the opening wall in the gate region 401 .

[0146] Ex-situ Si ３ N ４ Since the etching process of the film 307 is anisotropic etching, the shape of the top surfaces of the sidewalls 304s and 304d is similar to that of the ex-situ Si ３ N ４ The shape of the top surface of the film 307 is transferred to the sidewall 304. This shape is generally called the sidewall shape. By forming the sidewalls 304s and 304d in the gate region 401, the length of the exposed portion of the nitride semiconductor layer 104 in the gate region 401 (so-called gate length Lg) is shortened. Specifically, the gate length Lg is shortened from 0.39 μm to 0.19 μm.

[0147] When the length of the gate region 401 is 0.4 μm, it is possible to form a gate opening using i-line photolithography, which is a common optical exposure method. On the other hand, it is difficult to form a gate opening if the length is 0.25 μm or less. In contrast, by forming the sidewalls 304s and 304d, it is possible to easily shorten the gate length Lg.

[0148] 9H, the photoresist 501 is removed with an organic solvent such as acetone, so that the portions covering the source electrode 201 and the drain electrode 202 are left with ex-situ Si ３ N ４ A portion of the film 307 remains.

[0149] Next, as shown in FIG. 9I , the gate electrode 203 is formed. Specifically, a first conductive film made of a material that forms a Schottky junction with the nitride semiconductor is formed as the gate electrode lower portion 203L, and a second conductive film made of a material that has a lower resistivity than the first conductive film is formed as the gate electrode upper portion 203U. For example, the first and second conductive films may be successively formed over the entire surface by sputtering or the like, and then a resist mask may be formed and unnecessary portions may be removed by dry etching. Alternatively, the gate electrode 203 may be formed by a lift-off method. Specifically, a resist film having an opening corresponding to the gate electrode 203 may be formed, and then the first and second conductive films may be successively vapor-deposited, and the resist film may be removed together with the first and second conductive films provided on the resist film.

[0150] The thicker the gate electrode upper portion 203U, the more reduced the gate resistance Rg can be expected. However, due to the skin effect of metal, current flows only through the surface (skin portion) at high frequencies. Therefore, a thicker gate electrode upper portion 203U is not necessarily better. For an Al gate electrode upper portion 203U, a thickness of approximately 450 nm is sufficient for currently used frequency bands. Furthermore, increasing the thickness of the gate electrode upper portion 203U may be subject to constraints such as film formation time, etching time, and the thickness of the photoresist mask. For example, when depositing Al by sputtering, the thicker the film, the longer the film formation and etching time. This may result in burn-in of the resist mask, making it difficult to remove. Furthermore, when depositing the film by evaporation lift-off, poor lift-off properties are likely to result in shape anomalies. For this reason, the thickness of the gate electrode upper portion 203U is limited to a maximum of approximately 650 nm.

[0151] 9J, an insulating layer 305 is formed to protect the gate electrode 203. The insulating layer 305 is formed, for example, by ex-situ Si by plasma CVD or LPCVD. ３ N ４ Form a film.

[0152] Next, as shown in FIG. 9K, the source field plate 204 is formed by depositing a metal film by sputtering and removing it by dry etching. Alternatively, the source field plate 204 may be formed by a vapor deposition lift-off method. When Au is used, the vapor deposition lift-off method is used because dry etching is not possible.

[0153] Next, in order to ensure electrical connection with the source electrode 201 and the drain electrode 202, first, an insulating layer 305 and an ex-situ Si ３ N ４ Openings are formed in the film 307. The openings are formed by forming a photoresist having openings so as to expose the source electrode 201 and the drain electrode 202, and then forming a CF ４ The ex-situ Si semiconductor layer is formed by dry etching using plasma ions containing . ３ N ４ The film 307 is the ex-situ Si film shown in FIG. ３ N ４ This forms a film 306. Thereafter, barrier metals 205s and 205d and wiring metals 206s and 206d having predetermined shapes are formed to cover the openings. The barrier metals 205s and 205d and the wiring metals 206s and 206d are formed by sputtering and dry etching, or a deposition lift-off method, or the like.

[0154] Through the above steps, the semiconductor device 3 shown in FIG. 5 can be manufactured.

[0155] 1, the process of forming the sidewalls 304s and 304d can be omitted. Specifically, the processes described with reference to FIGS. 9E to 9H can be omitted. After forming the gate region 401 as shown in FIG. 9D, the gate electrode 203 can be formed as shown in FIG. 9J.

[0156] Furthermore, the semiconductor device 2 or 4 according to the second or fourth embodiment can also be manufactured through steps that are substantially the same as the manufacturing method of the semiconductor device 3. Below, differences between the manufacturing method of the semiconductor device 3 and the manufacturing method of the semiconductor device 4 will be described with reference to Figures 10A to 10C. Figures 10A to 10C are each a cross-sectional view for explaining one step of the manufacturing method of the semiconductor device 4 according to the fourth embodiment.

[0157] In the manufacturing method of the semiconductor device 4, in-situ Si ３ N ４ The steps up to the formation of the film 301 are the same as those in the manufacturing method of the semiconductor device 3, and are as described with reference to FIG. ３ N ４ Ex-situ Si on the film 301 ３ N ４ film 302 and SiO ２ Specifically, an in-situ Si film 303 is formed. ３ N ４ The GaN wafer on which the film 301 is formed is taken out of the growth furnace, and the GaN wafer is exposed to the atmosphere. ３ N ４ After cleaning the upper surface of the film 301 with an acid such as hydrofluoric acid, ex-situ Si ３ N ４ Film 302 and SiO ２ The film 303 is continuously formed. ３ N ４ Film 302 and SiO ２ The film 303 is formed by, for example, a plasma CVD method. ３ N ４ The film 302 is formed by the LPCVD method, and SiO ２ The film 303 may be formed by a plasma CVD method.

[0158] 10B, a source electrode 201 and a drain electrode 202 are formed. Before the source electrode 201 and the drain electrode 202 are formed, a process for passivating regions other than the transistor formation region is carried out.

[0159] In the process of forming the source electrode 201 and the drain electrode 202, ex-situ Si ３ N ４ Film 302 and In-situ Si ３ N ４ Not only the film 301 but also SiO ２ The difference is that a part of the film 303 is also removed. The formation and patterning of the metal film, as well as the alloying and other processes, are the same as those in the method for manufacturing the semiconductor device 3.

[0160] 10C, a gate opening is formed in the gate region 401 for forming a gate. In the formation of the gate opening, ex-situ Si ３ N ４ Film 302 and In-situ Si ３ N ４ Not only the film 301 but also SiO ２ The difference is that a part of the film 303 is also removed. ２ The film 303 is removed by, for example, CF ４ This is done by dry etching using gas.

[0161] The subsequent steps are the same as those in the method for manufacturing the semiconductor device 3. Specifically, the steps described with reference to Figures 9E to 9K are performed.

[0162] 4, the process of forming the sidewalls 304s and 304d can be omitted. Specifically, the processes described with reference to FIGS. 9E to 9H can be omitted. After forming the gate region 401 as shown in FIG. 10C, the gate electrode 203 can be formed as shown in FIG. 9J.

[0163] (Summary) The features of the semiconductor device described based on the above embodiment will be described below.

[0164] A semiconductor device according to a first aspect of the present disclosure includes: a substrate; a channel layer made of a nitride semiconductor containing Ga provided above the substrate; a nitride semiconductor layer provided above the channel layer, the nitride semiconductor layer including a barrier layer having a band gap larger than that of the channel layer and containing Ga; a source electrode and a drain electrode provided above the substrate and spaced apart from each other; gate electrodes provided above the barrier layer and between the source electrode and the drain electrode and spaced apart from each other; and an insulating layer provided above the nitride semiconductor layer between the gate electrode and the drain electrode, the insulating layer includes a junction portion that forms a Schottky junction with the semiconductor layer, and a first protruding portion that protrudes further toward the drain electrode than the junction portion, the insulating layer including a first insulating film that is located between the first protruding portion and the nitride semiconductor layer and that is made of silicon nitride and that covers and contacts the nitride semiconductor layer, and a second insulating film that is located between the first protruding portion and the first insulating film, and the insulating layer satisfies at least one of the following: (a) a halogen concentration of the first insulating film is lower than a halogen concentration of the second insulating film; and (b) an oxygen concentration at the interface between the first insulating film and the nitride semiconductor layer is lower than an oxygen concentration at the interface between the second insulating film and the first insulating film.

[0165] As a result, since a laminated structure of the first insulating film and the second insulating film is provided, it is possible to realize a semiconductor device having high drive current characteristics and low wafer warpage characteristics.

[0166] A semiconductor device according to a second aspect of the present disclosure is the semiconductor device according to the first aspect, wherein (c) the halogen concentration of the first insulating film is 1×10 １８ atom / cm ３ and the halogen concentration of the second insulating film is less than 1×10 １８ atom / cm ３ (d) the oxygen concentration at the interface between the first insulating film and the nitride semiconductor layer is greater than 1×10 ２０ atom / cm ３ and the oxygen concentration at the interface between the second insulating film and the first insulating film is less than 1×10 ２０ atom / cm ３It satisfies at least one of the following:

[0167] This allows for in-situ Si ３ N ４ The film is a first insulating film, and ３ N ４ Since the film is provided as the second insulating film, the in-situ Si ３ N ４ Ex-situ Si while utilizing the high piezoelectric stress of the film ３ N ４ The wafer warpage suppression effect of the film can be effectively utilized. ３ N ４ By utilizing the lateral hopping of electrons in the film, the accumulation of fixed charges can be suppressed, thereby suppressing current collapse. Therefore, according to this aspect, a semiconductor device having high drive current characteristics and low wafer warpage characteristics can be realized.

[0168] A semiconductor device according to a third aspect of the present disclosure is a semiconductor device according to the first or second aspect, wherein the insulating layer further includes a third insulating film made of silicon oxide, located between the first protrusion and the second insulating film and in contact with the first protrusion.

[0169] This allows the third insulating film made of silicon oxide, which has a low dielectric constant, to reduce the gate-drain capacitance Cgd, thereby improving the high frequency gain characteristics and efficiency performance of the transistor.

[0170] A semiconductor device according to a fourth aspect of the present disclosure is a semiconductor device according to any one of the first to third aspects, wherein the thickness of the first insulating film is 10 nm or more, and the thickness of the barrier layer is 7 nm or more.

[0171] This makes it possible to achieve a high drive current and a low leakage current.

[0172] A semiconductor device according to a fifth aspect of the present disclosure is the semiconductor device according to the fourth aspect, wherein the barrier layer has a film thickness of 10 nm or less.

[0173] This makes it possible to achieve a high drive current and a low leakage current.

[0174] A semiconductor device according to a sixth aspect of the present disclosure is the semiconductor device according to the fourth or fifth aspect, wherein the first insulating film has a thickness of 25 nm or less.

[0175] This makes it possible to achieve a high drive current, a low leakage current, and low wafer warpage characteristics.

[0176] A semiconductor device according to a seventh aspect of the present disclosure is the semiconductor device according to any one of the first to sixth aspects, wherein the insulating layer further includes a sidewall made of silicon nitride provided between the junction and the first insulating film, and at least one of the following is satisfied: (e) a halogen concentration in the first insulating film is lower than a halogen concentration in the sidewall; and (f) an oxygen concentration at an interface between the first insulating film and the nitride semiconductor layer is lower than an oxygen concentration at an interface between the sidewall and the nitride semiconductor layer.

[0177] This allows the gate length to be shortened, the carrier concentration of the 2DEG directly below the sidewall to be reduced, and cutoff control by the gate can be facilitated.

[0178] A semiconductor device according to an eighth aspect of the present disclosure is the semiconductor device according to the seventh aspect, wherein the sidewall has a film quality different from that of the second insulating film.

[0179] This makes it possible to reduce the carrier concentration of the 2DEG directly below the sidewall, facilitating cutoff control by the gate.

[0180] a fourth step of forming a source electrode and a drain electrode spaced apart from each other above the substrate; and a fifth step of forming gate electrodes between the source electrode and the drain electrode spaced apart from each other above the substrate, the gate electrodes being in contact with the exposed portions of the nitride semiconductor layer and covering portions of the insulating layer that are closer to the drain electrode than the exposed portions. The fifth step includes the steps of: forming, after the first step, a first insulating film made of silicon nitride that covers and contacts the nitride semiconductor layer without exposing the nitride semiconductor layer to the atmosphere; and forming, after the first insulating film has been formed, a second insulating film made of silicon nitride above the first insulating film, after exposing the nitride semiconductor layer to the atmosphere.

[0181] This makes it possible to manufacture a semiconductor device having high drive current characteristics and low wafer warpage characteristics.

[0182] A semiconductor device manufacturing method according to a tenth aspect of the present disclosure is the semiconductor device manufacturing method according to the ninth aspect, wherein in the second step, the second insulating film is formed by an LPCVD method.

[0183] This allows for ex-situ Si ３ N ４ The piezoelectric stress of the film can also be increased, which increases the carrier concentration of the 2DEG and further increases the drive current.

[0184] While the semiconductor device and the manufacturing method thereof according to one or more aspects have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and forms constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0185] For example, in each embodiment, the insulating layer 300 does not have to be provided between the source electrode 201 and the gate electrode 203. Alternatively, an in-situ Si ３ N ４ A film 301 is provided, and ex-situ Si ３ N ４ The membrane 302 may not be provided.

[0186] The insulating layer 300 may not be provided in a portion between the drain electrode 202 and the gate electrode 203. Specifically, the insulating layer 300 may be provided at least in a range overlapping with the drain side extension 203d in a plan view. The insulating layer 300 may not be provided in a range from the drain side end of the drain side extension 203d to the drain electrode 202 in a plan view. Alternatively, the insulating layer 300 may be provided in an in-situ Si ３ N ４ A film 301 is provided, and ex-situ Si ３ N ４ The membrane 302 may not be provided.

[0187] In addition, although the source electrode 201 and the drain electrode 202 are formed so as to be embedded in the barrier layer 105 and the channel layer 103, respectively, this is not limitative. The source electrode 201 and the drain electrode 202 may be provided on the upper surface of the barrier layer 105 or the cap layer 106. In other words, the source electrode 201 and the drain electrode 202 do not need to be in contact with the 2DEG 107.

[0188] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents.

[0189] The present disclosure can be used, for example, in a power amplifier for high-output or high-frequency applications, a wireless communication base station or terminal device in which the power amplifier is used, or a wireless power supply device that transmits power using microwaves.

[0190] 1, 2, 3, 4 Semiconductor device 101 Substrate 102 Buffer layer 103 Channel layer 104 Nitride semiconductor layer 105 Barrier layer 106 Cap layer 107 2DEG 201 Source electrode 202 Drain electrode 203 Gate electrode 203L Lower part of gate electrode 203U Upper part of gate electrode 203a Junction 203d Drain side extension 203s Source side extension 204 Source field plate 205d, 205s Barrier metal 206d, 206s Wiring metal 300, 305 Insulating layer 301 In-situ Si ３ N ４ Membrane 302, 306, 307 Ex-situ Si ３ N ４ Film 303 SiO ２ Films 304s, 304d Sidewall 401 Gate region 501 Photoresist 601, 602, 603 Region

Claims

1. A substrate; a channel layer made of a nitride semiconductor containing Ga provided above the substrate; a nitride semiconductor layer provided above the channel layer, the nitride semiconductor layer including a barrier layer having a band gap larger than that of the channel layer and containing Ga elements; a source electrode and a drain electrode spaced apart above the substrate; a gate electrode provided above the barrier layer between the source electrode and the drain electrode and spaced apart from each other; an insulating layer provided above the nitride semiconductor layer between the gate electrode and the drain electrode; The gate electrode is a junction portion that forms a Schottky junction with the nitride semiconductor layer; a first protruding portion that protrudes further toward the drain electrode than the junction portion, The insulating layer is a first insulating film made of silicon nitride located between the first protruding portion and the nitride semiconductor layer and covering and in contact with the nitride semiconductor layer; a second insulating film made of silicon nitride and located between the first protruding portion and the first insulating film, (a) the halogen concentration of the first insulating film is lower than the halogen concentration of the second insulating film; and, (b) an oxygen concentration at the interface between the first insulating film and the nitride semiconductor layer is lower than an oxygen concentration at the interface between the second insulating film and the first insulating film; At least one of the following is satisfied: the insulating layer further includes a sidewall made of silicon nitride provided between the junction and the first insulating film, (e) the halogen concentration of the first insulating film is lower than the halogen concentration of the sidewall; and, (f) an oxygen concentration at the interface between the first insulating film and the nitride semiconductor layer is lower than an oxygen concentration at the interface between the sidewall and the nitride semiconductor layer; At least one of the following is satisfied: Semiconductor device.

2. (c) the halogen concentration of the first insulating film is 1×10 １８ atom / cm ３ and the halogen concentration of the second insulating film is less than 1×10 １８ atom / cm ３ Something bigger, and, (d) the oxygen concentration at the interface between the first insulating film and the nitride semiconductor layer is 1×10 ２０ atom / cm ３ and the oxygen concentration at the interface between the second insulating film and the first insulating film is less than 1×10 ２０ atom / cm ３ Something bigger, At least one of the following is satisfied: The semiconductor device according to claim 1 .

3. the insulating layer further includes a third insulating film made of silicon oxide, located between the first overhanging portion and the second insulating film and in contact with the first overhanging portion; The semiconductor device according to claim 1 .

4. The first insulating film has a thickness of 10 nm or more, The barrier layer has a thickness of 7 nm or more. The semiconductor device according to claim 1 .

5. The barrier layer has a thickness of 10 nm or less. The semiconductor device according to claim 4 .

6. The first insulating film has a thickness of 25 nm or less. The semiconductor device according to claim 4 .

7. the sidewall has a film quality different from that of the second insulating film; The semiconductor device according to claim 1 .

8. a first step of forming, in order above a substrate by epitaxial growth, a channel layer made of a nitride semiconductor containing Ga, and a nitride semiconductor layer including a barrier layer having a larger band gap than the channel layer and containing Ga; a second step of forming an insulating layer so as to cover the nitride semiconductor layer; a third step of removing a portion of the insulating layer to expose a portion of the nitride semiconductor layer; a fourth step of forming a source electrode and a drain electrode spaced apart from each other above the substrate; a fifth step of forming a gate electrode between the source electrode and the drain electrode at a distance from each other so as to be in contact with the exposed portion of the nitride semiconductor layer and to cover a portion of the insulating layer that is located closer to the drain electrode than the exposed portion, The second step comprises: forming a first insulating film made of silicon nitride that covers and contacts the nitride semiconductor layer without exposing the nitride semiconductor layer to the atmosphere after the first step; and forming a second insulating film made of silicon nitride above the first insulating film after exposing the first insulating film to the atmosphere. A method for manufacturing a semiconductor device.

9. In the second step, the second insulating film is formed by a low pressure chemical vapor deposition (LPCVD) method. The method for manufacturing a semiconductor device according to claim 8 .