Semiconductor device

Abstract

A semiconductor device (1) is provided with: a substrate (101); a channel layer (103); a nitride semiconductor layer (104) including a barrier layer (105); a source electrode (201); a drain electrode (202); a gate electrode (203); a drain-side insulating layer (300d); and a source-side insulating layer (300s). The gate electrode (203) includes a junction part (203a), a drain-side overhang part (203d), and a source-side overhang part (203s). The overhang length of the source-side overhang part (203s) is longer than the overhang length of the drain-side overhang part (203d). The lower surface (203sa) of the source-side overhang part (203s) has a step. The height Hgs of an end part (203ss) of the lower surface (203sa) of the source-side overhang part (203s) is higher than the height Hgd of an end part (203dd) of the lower surface (203da) of the drain-side overhang part (203d).

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] In recent years, development of GaN high electron mobility transistors (HEMTs) for use in power amplifiers for high frequency wireless communications has been progressing. GaN HEMTs have the following three main physical property characteristics:

[0003] Specifically, these are an electron carrier transport mechanism that utilizes the high mobility of two-dimensional electron gas (hereinafter referred to as 2DEG (Two Dimensional Electron Gas)), high voltage resistance due to the wide band gap properties of the semiconductor, and high current drivability due to the high piezoelectric effect. These features make GaN HEMTs ideal devices for applications that satisfy both high speed and high output characteristics, and their application to high frequency wireless base stations, high speed charging, etc. is progressing.

[0004] The performance required for power amplifiers for high frequency applications can be divided into two categories: gain performance and efficiency performance. Of these, reducing gate resistance is effective for improving gain performance. Increasing the cross-sectional area of ​​the gate electrode is effective for reducing gate resistance.

[0005] However, increasing the cross-sectional area of ​​the gate electrode increases the area where the 2DEG faces the gate electrode, which results in a trade-off between the gate-source parasitic capacitance Cgs and the gate-drain parasitic capacitance Cgd.

[0006] Patent Documents 1 and 2 disclose a structure in which the cross-sectional area of ​​the gate electrode is increased on the source electrode side and decreased on the drain electrode side in order to reduce the parasitic capacitance Cgd between the gate and drain. Patent Document 3 discloses a gate electrode provided with protruding regions that extend to both the source electrode and drain electrode sides at a height that is some distance from the 2DEG.

[0007] JP-A-3-66136, JP-A-7-307349, JP-A-2023-95789

[0008] However, the techniques disclosed in Patent Documents 1 and 2 are unable to reduce the parasitic capacitance Cgs between the gate and source. Furthermore, the technique disclosed in Patent Document 3 is able to increase the distance between the protruding region and the 2DEG, but there is room for improvement in reducing the parasitic capacitances Cgs and Cgd. As frequencies continue to increase, such as in 6G communications, which are expected to become more widespread in the future, it is desirable to avoid the trade-off between gate resistance and the parasitic capacitances Cgs and Cgd and improve gain performance.

[0009] Therefore, an object of the present disclosure is to provide a semiconductor device that can improve gain performance.

[0010] A semiconductor device according to one aspect of the present disclosure includes a substrate, a channel layer made of a nitride semiconductor containing Ga provided above the substrate, a nitride semiconductor layer provided above the channel layer, the nitride semiconductor layer having a band gap larger than that of the channel layer and including the barrier layer containing Ga, a source electrode and a drain electrode provided above the substrate and spaced apart from each other, gate electrodes provided above the barrier layer and between the source electrode and the drain electrode and spaced apart from each other, a drain-side insulating layer provided above the nitride semiconductor layer between the gate electrode and the drain electrode, and and a source-side insulating layer provided above the nitride semiconductor layer, wherein the gate electrode includes a junction portion that forms a Schottky junction with the nitride semiconductor layer, a first protruding portion that protrudes further toward the drain electrode than the junction, and a second protruding portion that protrudes further toward the source electrode than the junction, wherein the protruding length of the second protruding portion is longer than the protruding length of the first protruding portion, a lower surface of the second protruding portion has a step, and a height from the upper surface of the nitride semiconductor layer of an end portion of the lower surface of the second protruding portion that is closest to the source electrode is greater than a height from the upper surface of the nitride semiconductor layer of an end portion of the lower surface of the first protruding portion that is closest to the drain electrode.

[0011] According to the semiconductor device according to the present disclosure, gain performance can be improved.

[0012] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view of a semiconductor device according to a second embodiment. FIG. 3 is a cross-sectional view of a semiconductor device according to a third embodiment. FIG. 4 is a cross-sectional view of a semiconductor device according to a fourth embodiment. FIG. 5 is a cross-sectional view of a semiconductor device according to a fifth embodiment. FIG. 6A is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to a first embodiment. FIG. 6B is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to a first embodiment. FIG. 6C is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to a first embodiment. FIG. 6D is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to a first embodiment. FIG. 6E is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to a first embodiment. FIG. 6F is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to a first embodiment. FIG. 6G is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to a first embodiment. FIG. 6H is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to a first embodiment. FIG. 6I is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to a first embodiment. FIG. 7A is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to a fifth embodiment. FIG. 7B is a cross-sectional view for explaining one step of a method for manufacturing a semiconductor device according to a fifth embodiment. FIG. 7C is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the fifth embodiment. FIG. 7D is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the fifth embodiment. FIG. 7E is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the fifth embodiment. FIG. 7F is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the fifth embodiment. FIG. 7G is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the fifth embodiment. FIG. 7H is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the fifth embodiment. FIG. 7I is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the fifth embodiment. FIG. 7J is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the fifth embodiment. FIG. 8 is a small signal equivalent circuit diagram of the semiconductor device according to each embodiment. FIG. 9 is a diagram illustrating gain improvement.Fig. 10 is a cross-sectional view of a semiconductor device according to a comparative example. Fig. 11 is a diagram showing a comparison of the drain voltage dependency of gate resistance between the comparative example and the example. Fig. 12 is a diagram showing a comparison of the drain voltage dependency of gate-source parasitic capacitance between the comparative example and the example. Fig. 13 is a diagram showing a comparison of the drain voltage dependency of switching frequency between the comparative example and the example.

[0013] (Summary of the Present Disclosure) Hereinafter, embodiments will be specifically described with reference to the drawings.

[0014] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0015] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0016] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, such as rectangle, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0017] Furthermore, in this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between the two components, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0018] In this specification and drawings, the x-axis, y-axis, and z-axis refer to the three axes of a three-dimensional Cartesian coordinate system. Specifically, the x-axis and y-axis are two axes parallel to the main surface (top surface) of a substrate included in a semiconductor device, and the z-axis is a direction perpendicular to this main surface. Specifically, the direction in which the source electrode, gate electrode, and drain electrode are arranged in this order, i.e., the so-called gate length direction, is the x-axis. In the embodiments described below, the positive direction of the z-axis may be referred to as "upward," and the negative direction of the z-axis may be referred to as "downward." In this specification, unless otherwise specified, the source electrode side or source side refers to the negative side (negative direction) of the x-axis, and the drain electrode side or drain side refers to the positive side (positive direction) of the x-axis. In this specification, the term "planar view" refers to the main surface (top surface) of a substrate included in a semiconductor device viewed from the positive direction of the z-axis, unless otherwise specified.

[0019] In this specification, a group III nitride semiconductor is a semiconductor containing one or more group III elements and nitrogen. Examples of group III elements include aluminum (Al), gallium (Ga), and indium (In). Examples of group III nitride semiconductors include GaN, AlN, InN, AlGaN, InGaN, and AlInGaN. Group III nitride semiconductors may also contain one or more elements other than group III elements, such as silicon (Si) and phosphorus (P). In the following description, unless otherwise specified, the term "AlInGaN" means that the group III nitride semiconductor contains all of Al, In, Ga, and N. The same applies to other designations such as AlGaN and GaN.

[0020] Furthermore, a layer made of material A such as a Group III nitride semiconductor such as GaN or AlGaN, silicon nitride or silicon oxide, and a layer constituted by material A mean that the layer contains substantially only material A. However, the layer may contain other elements as impurities, such as elements that are unavoidable in the manufacturing process, at a rate of 1 at % or less.

[0021] In this specification, the composition ratio (composition rate) of a group III element in a nitride semiconductor (layer) refers to the ratio of the number of atoms of a target group III element among a plurality of group III elements contained in the nitride semiconductor. ａ In ｂ Ga ｃ In the case where the nitride semiconductor layer is made of N (a+b+c=1, a≧0, b≧0, c≧0), the Al composition ratio of the nitride semiconductor layer can be expressed as a / (a+b+c). Similarly, the In composition ratio and the Ga composition ratio can be expressed as b / (a+b+c) and c / (a+b+c), respectively.

[0022] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0023] First Embodiment First, a semiconductor device according to a first embodiment will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view of a semiconductor device 1 according to the present embodiment.

[0024] As shown in FIG. 1 , the semiconductor device 1 includes a substrate 101, a buffer layer 102, a channel layer 103, and a nitride semiconductor layer 104. The nitride semiconductor layer 104 includes a barrier layer 105 and a cap layer 106. A 2DEG 107 is formed near the interface between the channel layer 103 and the barrier layer 105. The buffer layer 102, the channel layer 103, the barrier layer 105, and the cap layer 106 are epitaxial layers (also called epilayers) formed by epitaxial growth. The semiconductor device 1 also includes a source electrode 201, a drain electrode 202, a gate electrode 203, a source field plate 204, barrier metals 205s and 205d, and wiring metals 206s and 206d. The semiconductor device 1 also includes a drain-side insulating layer 300d, a source-side insulating layer 300s, and an insulating layer 305. The source-side insulating layer 300s includes a first insulating film 301s, a second insulating film 302s, and a sidewall 304s. The drain-side insulating layer 300d includes a third insulating film 301d, a fourth insulating film 302d, and a sidewall 304d.

[0025] The substrate 101 is a substrate made of Si. Alternatively, the substrate 101 may be an SOI (Silicon on Insulator) substrate. Furthermore, the substrate 101 may be a substrate made of SiC, sapphire, diamond, GaN, AlN, or the like.

[0026] The buffer layer 102 is provided above the substrate 101. For example, the buffer layer 102 is provided in contact with the upper surface of the substrate 101. The buffer layer 102 is, for example, a layer made of a group III nitride semiconductor. As an example, the buffer layer 102 has a multi-layer structure of AlN and AlGaN, each having a thickness of 2 μm. The buffer layer 102 may alternatively be made of a single layer or multiple layers of a group III nitride semiconductor such as GaN, AlGaN, AlN, InGaN, or AlInGaN.

[0027] The provision of the buffer layer 102 can reduce adverse effects such as crystal dislocations and lattice defects caused by the difference in lattice spacing between the substrate 101 and the channel layer 103. Furthermore, even if the substrate 101 has defects, the provision of the buffer layer 102 can suppress the effects of the defects on the channel layer 103. This reduces defects in the channel layer 103, improves crystallinity, and increases electron mobility in the channel layer 103. The buffer layer 102 does not necessarily have to be provided.

[0028] The channel layer 103 is provided above the substrate 101. Specifically, the channel layer 103 is provided in contact with the upper surface of the buffer layer 102. The channel layer 103 is a layer made of a nitride semiconductor containing Ga elements. For example, the channel layer 103 is made of GaN. The film thickness of the channel layer 103 is, for example, 50 nm to 300 nm, and is 200 nm as an example. Note that the channel layer 103 is not limited to GaN, and may be made of a group III nitride semiconductor such as InGaN, AlGaN, or AlInGaN. Furthermore, the channel layer 103 may contain n-type impurities. The film thickness of the channel layer 103 is not limited to the above example.

[0029] The barrier layer 105 is provided above the channel layer 103. Specifically, the barrier layer 105 is provided in contact with the upper surface of the channel layer 103. Note that a spacer layer made of AlN and having a film thickness of, for example, about 1 nm may be provided between the barrier layer 105 and the channel layer 103. In this way, the channel layer 103 and the barrier layer 105 do not need to be in contact with each other.

[0030] The barrier layer 105 has a band gap larger than that of the channel layer 103 and is a layer made of a nitride semiconductor containing Ga. The barrier layer 105 is made of, for example, AlGaN. The Al composition ratio of the barrier layer 105 is, for example, 10% to 30%, but may be 20% to 30%. The Al composition ratio of the barrier layer 105 is, for example, 25% or less. The thickness of the barrier layer 105 is 7 nm to 10 nm, for example, 9 nm. The thickness of the barrier layer 105 may be 15 nm or less, 20 nm or less, or 30 nm or less. The barrier layer 105 is not limited to AlGaN, and may be made of a group III nitride semiconductor such as AlInGaN. The barrier layer 105 may also contain n-type impurities.

[0031] By including Ga elements in the barrier layer 105, the lattice spacing of the barrier layer 105 is more easily relaxed than when the barrier layer 105 is made of AlN that does not include Ga elements. This makes it possible to prevent cracks and the like from occurring in the barrier layer 105. Furthermore, it is possible to prevent warpage of the wafer. This improves the quality of the semiconductor device 1.

[0032] A high concentration of 2DEG 107 is generated on the channel layer 103 side of the heterointerface between the barrier layer 105 and the channel layer 103 due to the piezoelectric stress of the barrier layer 105 on the channel layer 103. The 2DEG 107 is used as a channel of a transistor.

[0033] The cap layer 106 covers and contacts the upper surface of the barrier layer 105. The cap layer 106 is a layer made of a group III nitride semiconductor. The cap layer 106 is made of, for example, GaN. The thickness of the cap layer 106 is, for example, not less than about 1 nm and not more than about 2 nm. By providing the cap layer 106, oxidation of Al in the barrier layer 105 can be suppressed. Note that the cap layer 106 does not necessarily have to be provided.

[0034] The source electrode 201 and the drain electrode 202 are provided above the substrate 101 with a gap between them. Specifically, the source electrode 201 and the drain electrode 202 are provided so as to face each other with the gate electrode 203 sandwiched therebetween.

[0035] The source electrode 201 and the drain electrode 202 are formed using a conductive material. For example, the source electrode 201 and the drain electrode 202 are multilayer electrode films having a laminated structure in which a Ti film and an Al film are stacked in order, but this is not limited thereto. The source electrode 201 and the drain electrode 202 may be alloy layers formed by annealing a laminated structure of a Ti film and an Al film at a temperature of 500°C or higher. The source electrode 201 and the drain electrode 202 may also be a transition metal or a nitride or carbide of a transition metal. Specifically, the source electrode 201 and the drain electrode 202 may be Ta, Hf, W, Ni, TiN, TaN, HfN, WN, TiC, TaC, HfC, Au, Cu, etc., or may be a compound containing these elements, or may be a multilayer electrode film having a laminated structure.

[0036] The source electrode 201 and the drain electrode 202 are also called ohmic electrodes, and are electrically connected to the 2DEG 107 through an ohmic connection. In this embodiment, the source electrode 201 and the drain electrode 202 are provided so as to be in contact with the 2DEG 107.

[0037] Specifically, the semiconductor device 1 has two recesses that penetrate the cap layer 106 and the barrier layer 105 and reach the channel layer 103. The two recesses are also referred to as a source opening and a drain opening, respectively. The source electrode 201 is provided so as to contact and cover the inner surface of the source opening, and the drain electrode 202 is provided so as to contact and cover the inner surface of the drain opening. The bottom surface of each of the two recesses is located below the interface between the channel layer 103 and the barrier layer 105. Therefore, the 2DEG 107 is exposed on the side surface of each of the two recesses. The source electrode 201 and the drain electrode 202 are each in contact with the 2DEG 107 on the side surface of the recess. This reduces the channel contact resistance. Note that instead of the recesses, source contact regions and drain contact regions with low resistance may be provided by adding n-type impurities to portions of the cap layer 106, the barrier layer 105, and the channel layer 103. The source contact region and the drain contact region may be formed by, for example, plasma treatment, ion implantation, crystal regrowth, or the like.

[0038] The source electrode 201 and the drain electrode 202 are each covered with an insulating film (specifically, the insulating layer 305 before the openings are formed) during the manufacturing process of the semiconductor device 1. In order to ensure contact with the source electrode 201 and the drain electrode 202, openings are formed in the insulating layer 305, and wiring metals 206s and 206d are connected to the source electrode 201 and the drain electrode 202, respectively, through the openings. The wiring metals 206s and 206d are formed using, for example, low-resistance Au.

[0039] Furthermore, when the wiring metal 206s containing Au comes into contact with the source electrode 201 containing Al, a reaction between the materials may occur in a high-temperature environment. To avoid this reaction, a barrier metal 205s is provided between the source electrode 201 and the wiring metal 206s. Similarly, a barrier metal 205d is provided between the drain electrode 202 and the wiring metal 206d. The barrier metals 205d and 205s are formed using a material containing a high-melting-point metal that is unlikely to react even at high temperatures. For example, the barrier metals 205d and 205s are TiN films. Note that the barrier metals 205d and 205s and the wiring metals 206d and 206s do not necessarily have to be provided. For example, the source electrode 201 and the drain electrode 202 may also function as wiring.

[0040] The gate electrode 203 is provided above the barrier layer 105, between the source electrode 201 and the drain electrode 202, and spaced apart from each other. In this embodiment, the gate electrode 203 has a multilayer structure including a lower gate electrode portion 203L and an upper gate electrode portion 203U.

[0041] The gate electrode lower portion 203L is formed using a conductive material capable of forming a Schottky junction with a nitride semiconductor containing Ga. For example, the gate electrode lower portion 203L is formed using Ni, Ti, TiN, TaN, W, Pd, or the like. The gate electrode lower portion 203L is located at the bottom layer of the multilayer gate electrode 203 and is in contact with the cap layer 106, the drain-side insulating layer 300d, and the source-side insulating layer 300s. The thickness of the gate electrode lower portion 203L is, for example, 25 nm to 100 nm, and is 50 nm, but is not limited to this.

[0042] The upper gate electrode portion 203U is formed using a material having a lower resistivity than the lower gate electrode portion 203L. For example, the upper gate electrode portion 203U is formed using Au or Al. The upper gate electrode portion 203U is provided so as to contact and cover the upper surface of the lower gate electrode portion 203L. The thickness of the upper gate electrode portion 203U is, for example, 450 nm to 650 nm, and is 500 nm as an example, but is not limited to this. In a plan view, the shape and size of the upper gate electrode portion 203U are substantially the same as the shape and size of the lower gate electrode portion 203L.

[0043] In this way, by having the gate electrode 203 have a multilayer structure, it is possible to reduce the gate resistance Rg in the y-axis direction while ensuring a Schottky junction. The reduced gate resistance Rg can improve high-frequency gain. Note that the gate electrode 203 does not have to have a multilayer structure, and may have a single-layer structure formed using a conductive material that can form a Schottky junction with a nitride semiconductor containing Ga.

[0044] The gate electrode 203 has a so-called T-gate structure. Specifically, the gate electrode 203 includes a junction 203 a, a drain-side extension 203 d, and a source-side extension 203 s. The drain-side extension 203 d and the source-side extension 203 s are also called gate field plates.

[0045] The junction 203a forms a Schottky junction with the nitride semiconductor layer 104. Specifically, the junction 203a is a portion of the lower surface of the gate electrode lower portion 203L that is in contact with the cap layer 106. If the cap layer 106 is not provided, the junction 203a becomes a portion of the lower surface of the gate electrode lower portion 203L that is in contact with the barrier layer 105.

[0046] The drain side extension 203d is an example of a first extension, and is a portion that extends further toward the drain electrode 202 than the junction portion 203a. The drain side extension 203d corresponds to one arm of the T in the T-shaped gate structure.

[0047] The source-side protruding portion 203s is an example of a second protruding portion, and is a portion that protrudes further toward the source electrode 201 than the junction portion 203a. The source-side protruding portion 203s corresponds to one arm of the T in the T-shaped gate structure.

[0048] The semiconductor device 1 according to this embodiment is characterized by the cross-sectional shape of the gate electrode 203. The specifics of this will be described later.

[0049] The source field plate 204 is provided above the gate electrode 203, and is set to the same potential as the source electrode 201. Specifically, the source field plate 204 is provided above the insulating layer 305. The source field plate 204 is provided so that at least a portion thereof is located between the gate electrode 203 and the drain electrode 202 in a planar view. In the example shown in FIG. 1 , the source field plate 204 is arranged so that a portion thereof overlaps the gate electrode 203 in a planar view. The source field plate 204 is electrically insulated from the gate electrode 203 and the drain electrode 202, and is set to the potential (source potential) applied to the source electrode 201.

[0050] During operation of the semiconductor device 1, a high voltage of approximately 100 V to 150 V is applied to the drain electrode 202. At this time, a high electric field is applied between the drain electrode 202 and the gate electrode 203. Specifically, electric field lines from the drain electrode 202 concentrate at the end of the drain-side extension 203 d of the gate electrode 203, increasing the peak value of the electric field and reducing reliability. By providing the source field plate 204, this peak value of the electric field can be reduced. The source field plate 204 can alleviate the high electric field peak by dispersing it in the x-axis direction. This improves the gate-drain breakdown voltage and reliability by suppressing gate leakage current.

[0051] The source field plate 204 is formed using a conductive material. The source field plate 204 has a multilayer electrode film configuration, for example, a laminated structure in which a TiN film and an Al film are stacked in order. The thickness of the source field plate 204 is, for example, 500 nm, but is not limited to this. The source field plate 204 is not limited to a laminated structure of a TiN film and an Al film, and may also be a transition metal nitride or carbide formed by sputtering. Specifically, the source field plate 204 may be made of Ti, Ta, W, Ni, TiN, TaN, WN, W, Au, Cu, etc., or a compound containing these elements, or a multilayer electrode film consisting of a multilayer structure. As an example, the source field plate 204 has a multilayer structure in which Ti, TiN, and Al are stacked in this order from the bottom up. Alternatively, the source field plate 204 may include Au in the top layer.

[0052] The insulating layer 305 is provided between the gate electrode 203 and the source field plate 204. Specifically, the insulating layer 305 is provided so as to cover the entire area of ​​the semiconductor device 1. The insulating layer 305 has openings for ensuring contact with each of the source electrode 201 and the drain electrode 202.

[0053] The insulating layer 305 is, for example, a Si layer having a thickness of 110 nm. ３ N ４ The insulating layer 305 is made of Si ３ N ４ Not limited to, SiO ２ , SiON may also be used. ３ N ４ Alternatively, the stress may be controlled by changing the composition ratio of Si or N. The insulating layer 305 and the source field plate 204 do not necessarily have to be provided.

[0054] The drain-side insulating layer 300d is provided above the nitride semiconductor layer 104, between the gate electrode 203 and the drain electrode 202. The drain-side insulating layer 300d overlaps the drain-side protrusion 203d in a plan view. Specifically, the drain-side insulating layer 300d contacts and covers the upper surface of the cap layer 106 between the gate electrode 203 and the drain electrode 202. The drain-side insulating layer 300d is provided over the entire range from the drain-side end of the junction 203a to the drain electrode 202.

[0055] The drain-side insulating layer 300d includes a third insulating film 301d, a fourth insulating film 302d, and a sidewall 304d. Note that the fourth insulating film 302d and the sidewall 304d do not necessarily have to be provided.

[0056] The third insulating film 301d is located between the drain side extension 203d of the gate electrode 203 and the nitride semiconductor layer 104. Specifically, the third insulating film 301d overlaps the drain side extension 203d in a plan view and is in contact with the lower surface 203da of the drain side extension 203d. The third insulating film 301d also contacts and covers the nitride semiconductor layer 104 in a range from the position where it overlaps the drain side extension 203d in a plan view of the substrate 101 to the drain electrode 202. The third insulating film 301d is made of, for example, silicon nitride (Si ３ N ４ )

[0057] The fourth insulating film 302d is provided above the third insulating film 301d. In a plan view of the substrate 101, the fourth insulating film 302d does not overlap the drain-side protruding portion 203d. For example, the fourth insulating film 302d is in contact with the drain electrode 202. In a plan view, the fourth insulating film 302d is provided so as to overlap the drain electrode 202 and extend toward the gate electrode 203. The fourth insulating film 302d is made of, for example, Si ３ N ４ However, silicon oxide (SiO ２ ) or silicon oxynitride (SiON).

[0058] The sidewall 304d is provided between the junction 203a of the gate electrode 203 and the third insulating film 301d. The sidewall 304d is made of, for example, Si ３ N ４ The sidewall 304d is formed in the same process as the fourth insulating film 302d. By providing the sidewall 304d, the gate length Lg can be shortened.

[0059] The source-side insulating layer 300s is provided above the nitride semiconductor layer 104, between the gate electrode 203 and the source electrode 201. The source-side insulating layer 300s overlaps the source-side protrusion 203s in a plan view. Specifically, the source-side insulating layer 300s contacts and covers the upper surface of the cap layer 106 between the gate electrode 203 and the source electrode 201. The source-side insulating layer 300s is provided over the entire range from the source-side end of the junction 203a to the source electrode 201.

[0060] The source-side insulating layer 300s includes a first insulating film 301s, a second insulating film 302s, and a sidewall 304s. Note that the sidewall 304s does not necessarily have to be provided.

[0061] The first insulating film 301s is located between the source-side overhang 203s of the gate electrode 203 and the nitride semiconductor layer 104. Specifically, the first insulating film 301s overlaps the source-side overhang 203s in a plan view and is in contact with the lower surface 203sa of the source-side overhang 203s. The first insulating film 301s contacts and covers the nitride semiconductor layer 104 in a range from the position where it overlaps the source-side overhang 203s in a plan view of the substrate 101 to the source electrode 201. The first insulating film 301s is made of, for example, Si ３ N ４ It consists of:

[0062] The first insulating film 301s can be formed in the same process as the third insulating film 301d on the drain electrode 202 side. Therefore, the first insulating film 301s has the same film thickness and film quality as the third insulating film 301d. For example, the film thickness of each of the first insulating film 301s and the third insulating film 301d is 50 nm to 150 nm, and is 100 nm as an example, but is not limited to this.

[0063] The second insulating film 302s is located between the source-side overhang 203s and the first insulating film 301s. Specifically, the second insulating film 302s overlaps the source-side overhang 203s in a plan view and is in contact with the lower surface 203sa of the source-side overhang 203s. The second insulating film 302s contacts and covers the first insulating film 301s in a range from the position where it overlaps the source-side overhang 203s to the source electrode 201 in a plan view of the substrate 101. The second insulating film 302s is made of, for example, Si ３ N ４ However, SiO ２ Alternatively, the second insulating film 302s may be made of SiON. ２ If a film is included, SiO ２ is Si ３ N ４ Therefore, the parasitic capacitance Cgs between the gate and source can be further reduced.

[0064] The end of the second insulating film 302s on the drain electrode 202 side (positive side of the x-axis) is set back more toward the source electrode 201 side (negative side of the x-axis) than the end of the first insulating film 301s on the drain electrode 202 side. Therefore, a part of the upper surface of the first insulating film 301s is not covered by the second insulating film 302s and is in contact with the lower surface 203sa of the source-side overhang 203s of the gate electrode 203. Due to the setback of the end of the second insulating film 302s, a step is formed on the lower surface 203sa of the source-side overhang 203s of the gate electrode 203.

[0065] The second insulating film 302s can be formed in the same process as the fourth insulating film 302d on the drain electrode 202 side. Therefore, the second insulating film 302s has the same film thickness and film quality as the fourth insulating film 302d. For example, the film thickness of each of the second insulating film 302s and the fourth insulating film 302d is 50 nm to 150 nm, and is 100 nm as an example, but is not limited to this.

[0066] The sidewall 304s is provided between the junction 203a of the gate electrode 203 and the first insulating film 301s. The sidewall 304s is made of, for example, Si ３ N ４ The sidewalls 304s are formed in the same process as the second insulating film 302s. By providing the sidewalls 304s, the gate length Lg can be shortened.

[0067] Next, a specific description will be given of the characteristic cross-sectional configuration of the gate electrode 203 in the semiconductor device 1 according to this embodiment.

[0068] In this embodiment, the cross-sectional shape of the gate electrode 203 is asymmetric in the xz cross section. Specifically, the overhang length of the source-side overhang 203s is longer than the overhang length of the drain-side overhang 203d. For example, as shown in FIG. 1 , the overhang length of the drain-side overhang 203d is G1. In contrast, the overhang length of the source-side overhang 203s is G1+G2. For example, G1 is 0.10 μm or more and 0.25 μm or less, e.g., 0.15 μm. Furthermore, G2 is 0.30 μm or more and 0.50 μm or less, e.g., 0.45 μm.

[0069] The protrusion length of the protrusion is the distance along the x-axis direction from the starting point to the tip of the protrusion. The starting point of the protrusion can be considered as the outline of the junction 203a in a plan view. The tip of the protrusion is the position farthest from the starting point in the protrusion direction of the protrusion. The protrusion direction is the positive direction of the x-axis for the drain-side protrusion 203d and the negative direction of the x-axis for the source-side protrusion 203s.

[0070] By providing the drain-side extension 203d and the source-side extension 203s, the cross-sectional area of ​​the gate electrode 203 can be increased while shortening the gate length Lg. This allows the gate resistance Rg to be reduced, improving the gain performance at high frequencies. Furthermore, by making the extension length of the drain-side extension 203d shorter than the extension length of the source-side extension 203s, the opposing area between the gate electrode 203 and the 2DEG 107 connected to the drain electrode 202 is reduced. This allows the gate-drain parasitic capacitance Cgd to be reduced.

[0071] On the other hand, since the overhang length of the source-side overhang 203s is longer than the overhang length of the drain-side overhang 203d, the opposing area between the gate electrode 203 and the 2DEG 107 connected to the source electrode 201 becomes larger. This can increase the gate-source parasitic capacitance Cgs. In contrast, in this embodiment, the lower surface 203sa of the source-side overhang 203s of the gate electrode 203 has a step. The lower surface 203da of the drain-side overhang 203d does not have a step.

[0072] 1 , the lower surface 203sa of the source-side overhang 203s includes an upper step 203sb, a lower step 203sc, and a sidewall 203sd. The upper step 203sb is the portion of the lower surface 203sa of the source-side overhang 203s that contacts the upper surface of the second insulating film 302s. The lower step 203sc is the portion of the lower surface 203sa that contacts the upper surface of the first insulating film 301s. The sidewall 203sd is the portion that connects the upper step 203sb and the lower step 203sc and contacts the side surface of the second insulating film 302s.

[0073] The sidewall portion 203sd is, for example, perpendicular to the main surface (xy plane) of the substrate 101. Alternatively, the sidewall portion 203sd may be an inclined surface inclined with respect to the substrate 101. The inclination angle of the sidewall portion 203sd (the angle it forms with respect to the xy plane) is, for example, 45 degrees or more. By providing the sidewall portion 203sd, the upper step portion 203sb and the lower step portion 203sc are discontinuous. In other words, a step is provided on the lower surface 203sa of the source-side protrusion 203s.

[0074] The lower surface 203sa of the source-side overhang 203s has a step, which increases the distance from the nitride semiconductor layer 104 (and the 2DEG 107). Specifically, as shown in FIG. 1 , the height Hgs of the end 203ss of the lower surface 203sa of the source-side overhang 203s, which is closest to the source electrode 201, from the upper surface of the nitride semiconductor layer 104 is greater than the height Hgd of the end 203dd of the lower surface 203da of the drain-side overhang 203d, which is closest to the drain electrode 202. That is, Hgs > Hgd is satisfied. Hgs corresponds to the total film thickness of the first insulating film 301s and the second insulating film 302s. Hgd corresponds to the film thickness of the third insulating film 301d.

[0075] This increases the distance between the source-side extension 203s and the 2DEG 107, thereby reducing the gate-source parasitic capacitance Cgs. That is, it is possible to suppress an increase in the parasitic capacitance Cgs that accompanies an increase in the opposing area between the source-side extension 203s and the 2DEG 107. Therefore, according to this embodiment, it is possible to achieve both a reduction in the gate resistance Rg and a reduction in the parasitic capacitances Cgs and Cgd.

[0076] Furthermore, in this embodiment, the thickness of the drain-side extension 203d and the source-side extension 203s of the gate electrode 203 are constant and equal to each other. Specifically, the thickness of the gate electrode 203 is constant regardless of the location. The thickness of the gate electrode 203 is the distance between the bottom surface and the top surface of the gate electrode 203 in the z-axis direction. Since the thickness of the gate electrode 203 is constant, the cross-sectional shapes of the bottom surface and the top surface of the gate electrode 203 are the same. The constant thickness of the gate electrode 203 increases the cross-sectional area of ​​the gate electrode 203, thereby reducing the gate resistance Rg. This improves the high-frequency gain performance of the semiconductor device 1. The thickness Gh of the gate electrode 203 is, for example, not limited to, 500 nm or more and 700 nm or less.

[0077] Typically, when the gate electrode 203 is formed, over-etching is likely to occur, particularly at both ends, resulting in a slight deformation of the cross-sectional shape. As a result, the thickness of the gate electrode 203 may be thinner at both ends. For this reason, in this specification, "constant" thickness means that the thickness can be considered to be substantially constant, and does not necessarily mean that the thickness values ​​at all locations are completely equal. For example, when the thickness is measured at multiple positions on the gate electrode 203, the thickness is also considered to be constant if the difference between the maximum and minimum measured values ​​is 10% or less of the average measured value.

[0078] The drain-side extension 203d and the source-side extension 203s each have a multilayer structure of an upper gate electrode portion 203U and a lower gate electrode portion 203L, but are not limited to this. For example, the drain-side extension 203d and the source-side extension 203s may each have only the low-resistance upper gate electrode portion 203U. That is, the lower gate electrode portion 203L may be provided only in the portion where the gate electrode 203 contacts the cap layer 106 (or the barrier layer 105) (the portion corresponding to the junction 203a).

[0079] The distance along the x-axis from the drain side end of the junction 203a to the drain electrode 202 is called the gate-drain distance Lgd. The distance along the x-axis from the source side end of the junction 203a to the source electrode 201 is called the gate-source distance Lgs. In this embodiment, Lgs<Lgd. For example, Lgd is 3.2 μm and Lgs is 1.3 μm. By making the gate-drain distance Lgd longer than the gate-source distance Lgs, it is possible to alleviate the electric field concentration between the gate and the drain. Note that it is not essential to satisfy Lgs<Lgd; Lgs=Lgd or Lgs>Lgd may also be satisfied.

[0080] (Embodiment 2) Next, embodiment 2 will be described. In embodiment 2, the main difference from embodiment 1 is that the first insulating film on the source side and the third insulating film on the drain side each have a stacked structure. The following description will focus on the differences from embodiment 1, and description of commonalities will be omitted or simplified.

[0081] Fig. 2 is a cross-sectional view of a semiconductor device 2 according to the present embodiment. As shown in Fig. 2, the semiconductor device 2 differs from the semiconductor device 1 shown in Fig. 1 in that the source-side insulating layer 300s includes a first insulating film 311s instead of the first insulating film 301s, and the drain-side insulating layer 300d includes a third insulating film 311d instead of the third insulating film 301d. The first insulating film 311s and the third insulating film 311d each have a stacked structure.

[0082] Specifically, the first insulating film 311s is made of Si ３ N ４ film 312s and SiO ２ The third insulating film 311d includes a Si ３ N ４ film 312d and SiO ２ and a membrane 313d.

[0083] Si ３ N ４ The film 312s contacts and covers the nitride semiconductor layer 104. In this embodiment, Si ３ N ４ The film 312s contacts and covers the nitride semiconductor layer 104 in a range from the position overlapping the source-side protruding portion 203s to the source electrode 201 in a plan view of the substrate 101.

[0084] SiO ２ The film 313s is Si ３ N ４ In this embodiment, the SiO ２ The film 313s is Si ３ N ４ The entire upper surface of the film 312s is covered. ３ N ４ The upper surface of the film 312s is not in contact with the lower surface 203sa of the source side extension 203s of the gate electrode 203. ２ The upper surface of the film 313s is in contact with the lower step portion 203sc of the lower surface 203sa.

[0085] Si ３ N ４ The film 312d is in contact with and covers the nitride semiconductor layer 104. In this embodiment, Si ３ N４ The film 312d contacts and covers the nitride semiconductor layer 104 in a range from the position overlapping the drain-side extension 203d to the drain electrode 202 in a plan view of the substrate 101.

[0086] Si ３ N ４ The film 312d is Si ３ N ４ It can be formed in the same process as the film 312s. ３ N ４ The film 312d is Si ３ N ４ The film thickness and film quality are the same as those of the film 312s. For example, Si ３ N ４ The thickness of each of the films 312d and 312s is, for example, 10 nm or more and 100 nm or less, and is, for example, 50 nm. ３ N ４ Films 312d and 312s have a substantially uniform thickness.

[0087] SiO ２ The film 313d is Si ３ N ４ In this embodiment, the SiO ２ The film 313d is Si ３ N ４ The entire upper surface of the film 312d is covered. ３ N ４ The upper surface of the film 312d is not in contact with the lower surface 203da of the drain side extension 203d of the gate electrode 203. ２ The upper surface of the film 313d is in contact with the lower surface 203da.

[0088] SiO ２ The film 313d is made of SiO ２ It can be formed in the same process as the film 313s. ２ The film 313d is made of SiO ２ The film thickness and film quality are the same as those of the film 313s. For example, SiO ２ The thickness of each of the films 313d and 313s is, for example, 10 nm to 100 nm, and is, for example, 50 nm. ２Films 313d and 313s have a substantially uniform thickness.

[0089] Si ３ N ４ The relative dielectric constant of SiO is about 7. ２ The relative dielectric constant of SiO is about 4. ２ The films 313d and 313s are Si ３ N ４ The dielectric constant of the SiO 2 film 312d is lower than that of the SiO 2 film 312s. ２ By providing the film 313d, the parasitic capacitance Cgd between the gate and the drain can be reduced. ２ By providing the film 313s, the parasitic capacitance Cgs between the gate and the source can be reduced, and the parasitic capacitance Cgd between the gate and the drain can be reduced, thereby improving the high frequency gain performance and efficiency performance of the transistor.

[0090] In this embodiment, one of the first insulating film 311s on the source electrode 201 side and the third insulating film 311d on the drain electrode 202 side is made of Si, as in the first embodiment. ３ N ４ It may also have a single layer structure of SiO ２ The film 313d is provided only at a position overlapping the drain side protrusion 203d in a plan view, and does not have to be provided at a position not overlapping the drain side protrusion 203d. ２ The film 313s may be provided only at a position overlapping the source side protrusion 203s in a plan view, and may not be provided at a position not overlapping the source side protrusion 203s.

[0091] Next, a third embodiment will be described. The third embodiment is mainly different from the first embodiment in that the fourth insulating film extends toward the gate electrode. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0092] 3 is a cross-sectional view of a semiconductor device 3 according to this embodiment. As shown in FIG. 3, the semiconductor device 3 differs from the semiconductor device 1 in that the fourth insulating film 302d extends toward the gate electrode 203.

[0093] For example, the distance in the x-axis direction between the end of the fourth insulating film 302d on the gate electrode 203 side and the end of the drain-side protrusion 203d of the gate electrode 203 is, for example, ¼ to ¾, and as an example, ½, of the gate-drain distance Lgd. For example, when the gate-drain distance Lgd is 3 μm, the distance in the x-axis direction between the end of the fourth insulating film 302d on the gate electrode 203 side and the end of the drain-side protrusion 203d of the gate electrode 203 is 1.5 μm.

[0094] Directly below the fourth insulating film 302d, the carrier concentration of the 2DEG 107 can be increased due to the effect of increased piezoelectric stress. As a result, the electrical resistance of the 2DEG 107 in the x-axis direction is reduced. By extending the fourth insulating film 302d toward the gate electrode 203, the region of the 2DEG 107 where the electrical resistance is reduced increases, thereby reducing the on-resistance Ron of the transistor. The semiconductor device 3 is useful when the operating voltage is low.

[0095] (Fourth Embodiment) Next, a fourth embodiment will be described. The fourth embodiment is mainly different from the second embodiment in that the number of steps on the underside of the source-side extension of the gate electrode is increased. The following description will focus on the differences from the second embodiment, and the description of the commonalities will be omitted or simplified.

[0096] 4 is a cross-sectional view of a semiconductor device 4 according to the present embodiment. As shown in Fig. 4, the semiconductor device 4 differs from the semiconductor device 2 in that the source-side insulating layer 300s further includes a fifth insulating film 303s and a sidewall 306s, and the drain-side insulating layer 300d further includes a sixth insulating film 303d and a sidewall 306d. The drain-side end of the source-side insulating layer 300s is formed in a three-step staircase shape.

[0097] The fifth insulating film 303s overlaps the source-side extending portion 203s in a plan view, and is located between the first insulating film 311s and the second insulating film 302s. Specifically, the fifth insulating film 303s contacts and covers the first insulating film 311s in a range from the position overlapping the source-side extending portion 203s to the source electrode 201 in a plan view of the substrate 101. The fifth insulating film 303s is made of, for example, Si ３ N ４ However, SiO ２ Alternatively, it may be made of SiON.

[0098] The end of the fifth insulating film 303s on the drain electrode 202 side (positive side of the x-axis) is set back closer to the source electrode 201 side (negative side of the x-axis) than the end of the first insulating film 311s on the drain electrode 202 side. Therefore, a part of the upper surface of the first insulating film 311s is not covered by the fifth insulating film 303s and is in contact with the lower surface of the source-side protrusion 203s of the gate electrode 203.

[0099] The upper surface of the fifth insulating film 303s is covered with the second insulating film 302s except for a portion that contacts the lower surface of the source-side overhang 203s. In this embodiment, the second insulating film 302s contacts and covers the upper surface of the fifth insulating film 303s. The end of the second insulating film 302s on the gate electrode 203 side is set back toward the source electrode 201 with respect to the end of the fifth insulating film 303s on the gate electrode 203 side.

[0100] The sidewall 306s is provided on the upper surface of the first insulating film 311s so as to contact the end surface of the fifth insulating film 303s. In the example shown in FIG. 4, the sidewall 306s covers the upper surface of the first insulating film 311s up to the end on the drain electrode 202 side, and is provided so as to contact or be integrated with the sidewall 304s, but this is not limiting. The sidewall 306s may not cover a part of the upper surface of the first insulating film 311s. The sidewall 306s is made of, for example, Si ３ N ４ The sidewall 306s is formed in the same process as the second insulating film 302s and the sidewall 304s.

[0101] The sixth insulating film 303d is provided between the third insulating film 311d and the fourth insulating film 302d. In a plan view of the substrate 101, the sixth insulating film 303d does not overlap the drain-side protruding portion 203d of the gate electrode 203. The sixth insulating film 303d is in contact with the drain electrode 202 and is provided so as to extend toward the gate electrode 203. The sixth insulating film 303d is made of, for example, Si ３ N ４ However, SiO ２ Alternatively, it may be made of SiON.

[0102] The sixth insulating film 303d can be formed in the same process as the fifth insulating film 303s on the source electrode 201 side. Therefore, the sixth insulating film 303d has the same film thickness and film quality as the fifth insulating film 303s. For example, the film thickness of each of the sixth insulating film 303d and the fifth insulating film 303s is 50 nm to 100 nm, for example, 100 nm, but is not limited to this.

[0103] The sidewall 306d is provided on the upper surface of the third insulating film 311d so as to contact the end surface of the sixth insulating film 303d. The sidewall 306d is made of, for example, Si ３ N ４ The sidewall 306d is formed in the same process as the fourth insulating film 302d and the sidewall 304d.

[0104] In this embodiment, three insulating films, namely, a first insulating film 311s, a fifth insulating film 303s, and a second insulating film 302s, are formed in a stepped shape at a position overlapping the source-side extension 203s in a plan view. As a result, three steps are formed on the lower surface of the source-side extension 203s. This makes it possible to further increase the height Hgs of the end 203ss of the lower surface of the source-side extension 203s on the source electrode 201 side. As a result, it is possible to further reduce the parasitic capacitance Cgs between the gate and source.

[0105] Furthermore, three insulating films, namely, a third insulating film 311d, a sixth insulating film 303d, and a fourth insulating film 302d, are stacked near the drain electrode 202. This increases the piezoelectric stress, thereby increasing the carrier concentration of the 2DEG 107 near the drain electrode 202. This reduces the on-resistance Ron of the transistor.

[0106] In this embodiment, similarly to the second embodiment, the first insulating film 311s and the third insulating film 311d are made of Si ３ N ４ Film and SiO ２ The second insulating film 302s and the fourth insulating film 302d, or the fifth insulating film 303s and the sixth insulating film 303d may have a laminated structure with a Si film. ３ N ４ Film and SiO ２ The number of layers of each insulating film may be three or more. In addition, one of the fifth insulating film 303s and the sixth insulating film 303d may not be provided.

[0107] (Embodiment 5) Next, embodiment 5 will be described. In embodiment 5, the main difference from embodiment 4 is that the fourth insulating film and the sixth insulating film extend toward the gate electrode side. The following description will focus on the differences with embodiment 4, and the description of the commonalities will be omitted or simplified.

[0108] 5 is a cross-sectional view of a semiconductor device 5 according to the present embodiment. As shown in FIG. 5, the semiconductor device 5 differs from the semiconductor device 4 in that the fourth insulating film 302d and the sixth insulating film 303d extend toward the gate electrode 203.

[0109] For example, the distance in the x-axis direction between the end of the sixth insulating film 303d on the gate electrode 203 side and the end of the drain-side protrusion 203d of the gate electrode 203 is, for example, ¼ to ¾ of the gate-drain distance Lgd, and is, for example, ½. The same applies to the fourth insulating film 302d.

[0110] Directly below the sixth insulating film 303d and the fourth insulating film 302d, the carrier concentration of the 2DEG 107 can be increased due to the effect of increased piezoelectric stress. As a result, the electrical resistance of the 2DEG 107 in the x-axis direction is reduced. Since the sixth insulating film 303d and the fourth insulating film 302d extend toward the gate electrode 203, the region where the electrical resistance of the 2DEG 107 is reduced increases, thereby reducing the on-resistance Ron of the transistor. The semiconductor device 5 is useful when the operating voltage is low.

[0111] (Manufacturing Method) Next, a manufacturing method for the semiconductor devices 1 to 5 according to the first to fifth embodiments will be described.

[0112] 6A to 6I, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described below. Each of FIGS. 6A to 6I is a cross-sectional view for explaining one step of the method for manufacturing the semiconductor device 1 according to the first embodiment.

[0113] First, as shown in FIG. 6A , a GaN wafer is prepared by epitaxially growing a nitride semiconductor. More specifically, a buffer layer 102, a channel layer 103, a barrier layer 105, and a cap layer 106 are sequentially formed on a substrate 101. For example, nitride semiconductors such as GaN and AlGaN are epitaxially grown in this order. The epitaxial growth is performed in a growth furnace, for example, based on the MOCVD (Metal Organic Chemical Vapor Deposition) method. The buffer layer 102, the channel layer 103, the barrier layer 105, and the cap layer 106 can be formed by adjusting the type and flow rate of the introduced gases.

[0114] Furthermore, after cleaning the upper surface of the cap layer 106 with an acid such as hydrofluoric acid, Si ３ N ４The insulating film 301 is formed by, for example, plasma CVD or LPCVD (Low-Pressure Chemical Vapor Deposition). Alternatively, the insulating film 301 may be formed continuously from the formation of the cap layer 106 in a MOCVD growth furnace without exposure to the atmosphere. After epitaxial growth of the nitride semiconductor, the insulating film 301 is formed by crystal growth of Si without exposure to the atmosphere. ３ N ４ The film is in-situ Si ３ N ４ The Si film formed after exposure to the atmosphere is called a ３ N ４ The film is ex-situ Si ３ N ４ is called the membrane.

[0115] Next, although not shown in the figure, boron ions (B ＋ By implanting ions that passivate nitride semiconductors such as GaN, regions other than the transistor formation region (also called the active region) are passivated, enabling electrical isolation between elements within the GaN wafer.

[0116] Next, as shown in FIG. 6B, a source electrode 201 and a drain electrode 202 are formed. Note that the following FIGS. 6B to 6I only show one transistor formation region in the GaN wafer. In each figure, the unillustrated portions to the left of the source electrode 201 (negative side of the x-axis) and to the right of the drain electrode 202 (positive side of the x-axis) become insulating isolation regions. The same applies to FIGS. 7B to 7J, which will be described later.

[0117] In the process of forming the source electrode 201 and the drain electrode 202, first, a portion of the insulating film 301 is removed by etching to form an opening (contact hole). Subsequently to the formation of the contact hole, the cap layer 106, the barrier layer 105, and the channel layer 103 are etched away until the 2DEG 107 is exposed, thereby forming a recess. The etching is performed, for example, by dry etching. A metal film is deposited by sputtering or vapor deposition so as to cover the inner surface of the formed recess, and then the metal film is patterned to form the source electrode 201 and the drain electrode 202. The patterning is performed, for example, by etching or lift-off. The semiconductor and the metal are then alloyed at a temperature of approximately 500° C. to 600° C., thereby bringing each of the source electrode 201 and the drain electrode 202 into ohmic contact with the channel layer 103.

[0118] Next, as shown in FIG. 6C, a gate opening is formed in a gate region 401 for forming a gate. The length of the gate region 401 in the x-axis direction is, for example, 0.39 μm. Specifically, a positive photoresist is applied onto the insulating film 301, and an opening is formed in the applied photoresist in the gate region 401. CF ４ The portion of the insulating film 301 exposed in the gate region 401 is removed by dry etching using plasma ions containing . This forms a first insulating film 301s on the source electrode 201 side and a third insulating film 301d on the drain electrode 202 side.

[0119] Next, as shown in FIG. 6D, a Si film is formed on the entire surface including the opening of the gate region 401. ３ N ４The insulating film 302 is formed by, for example, plasma CVD, but may also be formed by LPCVD. The insulating film 302 is a silicon nitride film that forms the base of the sidewalls 304s and 304d, as well as the second insulating film 302s and the fourth insulating film 302d. Specifically, the insulating film 302 is formed to the same thickness (e.g., 100 nm) as the first insulating film 301s and the third insulating film 301d. By making the film thicknesses uniform, the heights of the sidewalls 304s and 304d, the first insulating film 301s, and the third insulating film 301d can be made uniform.

[0120] Next, as shown in FIG. 6E, a photoresist 501 having an opening of a predetermined shape is formed, and then a CF ４ Anisotropic dry etching is performed using plasma ions containing , thereby removing the insulating film 302 exposed in the openings of the photoresist 501. The photoresist 501 has a shape that covers the source electrode 201 and the drain electrode 202, but does not cover at least the gate region 401. The etching amount is the thickness of the deposited insulating film 302, and is, for example, 100 nm.

[0121] When the gate region 401 is used as a reference, the opening of the photoresist 501 is larger on the drain side than on the source side. The photoresist 501 covers the area close to the gate region 401 on the source side, and covers only the area near the drain electrode 202 on the drain side. The shape and size of the opening of the photoresist 501 are determined according to the shape and size between the ends of the second insulating film 302s and the fourth insulating film 302d on the gate electrode 203 side. The photoresist 501 is positive-type, but may also be negative-type. After dry etching, the photoresist 501 is removed with an organic solvent such as acetone.

[0122] As a result of the dry etching, the second insulating film 302s, the fourth insulating film 302d, and the sidewalls 304s and 304d are formed, as shown in FIG. 6F. As a result of the asymmetry of the photoresist 501 with respect to the gate region 401, the second insulating film 302s on the source side is formed larger than the fourth insulating film 302d on the drain side. That is, the distance from the second insulating film 302s on the source side to the gate region 401 is shorter than the distance from the fourth insulating film 302d on the drain side to the gate region 401.

[0123] The sidewalls 304s and 304d are portions of the insulating film 302 that remain unremoved along the opening walls in the gate region 401. Because the etching process is anisotropic etching, the shape of the upper surfaces of the sidewalls 304s and 304d is a shape that is a transfer of the shape of the upper surface of the insulating film 302. This shape is generally referred to as the sidewall shape. By forming the sidewalls 304s and 304d in the gate region 401, the length of the exposed portion of the nitride semiconductor layer 104 in the gate region 401 (so-called gate length Lg) is shortened. Specifically, the gate length Lg is shortened from 0.39 μm to 0.19 μm.

[0124] When the length of the gate region 401 is 0.4 μm, it is possible to form a gate opening using i-line photolithography, which is a common optical exposure method. On the other hand, it is difficult to form a gate opening if the length is 0.25 μm or less. In contrast, by forming the sidewalls 304s and 304d, it is possible to easily shorten the gate length Lg.

[0125] Next, as shown in FIG. 6G , the gate electrode 203 is formed. Specifically, a first conductive film made of a material that forms a Schottky junction with the nitride semiconductor is formed as the gate electrode lower portion 203L, and a second conductive film made of a material that has a lower resistivity than the first conductive film is formed as the gate electrode upper portion 203U. For example, the first and second conductive films may be successively formed over the entire surface by sputtering or the like, and then a resist mask may be formed and unnecessary portions may be removed by dry etching. Alternatively, the gate electrode 203 may be formed by a lift-off method. Specifically, a resist film having an opening corresponding to the gate electrode 203 may be formed, and then the first and second conductive films may be successively vapor-deposited, and the resist film may be removed together with the first and second conductive films provided on the resist film.

[0126] The thicker the gate electrode upper portion 203U, the more reduced the gate resistance Rg can be expected. However, due to the skin effect of metal, current flows only through the surface (skin portion) at high frequencies. Therefore, a thicker gate electrode upper portion 203U is not necessarily better. For an Al gate electrode upper portion 203U, a thickness of approximately 450 nm is sufficient for currently used frequency bands. Furthermore, increasing the thickness of the gate electrode upper portion 203U may be subject to constraints such as film formation time, etching time, and the thickness of the photoresist mask. For example, when depositing Al by sputtering, the thicker the film, the longer the film formation and etching time. This may result in burn-in of the resist mask, making it difficult to remove. Furthermore, when depositing the film by evaporation lift-off, poor lift-off properties are likely to result in shape anomalies. For this reason, the thickness of the gate electrode upper portion 203U is limited to a maximum of approximately 650 nm.

[0127] 6H, an insulating layer 305 is formed to protect the gate electrode 203. For example, the insulating layer 305 is formed of a Si film by plasma CVD or LPCVD. ３ N ４ Form a film.

[0128] Next, as shown in FIG. 6I, the source field plate 204 is formed by depositing a metal film by sputtering and removing it by dry etching. Alternatively, the source field plate 204 may be formed by a deposition lift-off method. When Au is used, the deposition lift-off method is used because dry etching is not possible.

[0129] Next, in order to ensure electrical connection with the source electrode 201 and the drain electrode 202, openings are first formed in the insulating layer 305, the second insulating film 302s, and the fourth insulating film 302d. The openings are formed by forming a photoresist having openings so as to expose the source electrode 201 and the drain electrode 202, and then by using a CF ４ The openings are then covered with barrier metals 205s and 205d and wiring metals 206s and 206d having predetermined shapes. The barrier metals 205s and 205d and the wiring metals 206s and 206d are formed by sputtering and dry etching, or a deposition lift-off method, or the like.

[0130] Through the above steps, the semiconductor device 1 shown in FIG. 1 can be manufactured.

[0131] The semiconductor devices 2 and 3 according to the second and third embodiments are manufactured by modifying some of the steps included in the manufacturing method of the semiconductor device 1 described above. In the case of the semiconductor device 2, in the step described with reference to FIG. ３ N ４ Following the formation of the insulating film 301 made of SiO ２ The source electrode 201 and the drain electrode 202, and the gate region 401 may be formed by a plasma CVD method or the like. ２ Membrane and Si ３ N ４ The insulating film 301 may be continuously etched.

[0132] 6E, the shape of the photoresist 501 may be changed. Specifically, the portion of the photoresist 501 that overlaps with the third insulating film 301d on the drain side in a plan view may be enlarged to be closer to the gate region 401.

[0133] Next, a method for manufacturing the semiconductor device 5 according to the fifth embodiment will be described with reference to Figures 7A to 7J. Each of Figures 7A to 7J is a cross-sectional view for explaining one step of the method for manufacturing the semiconductor device 5 according to the fifth embodiment.

[0134] First, as shown in Fig. 7A, a GaN wafer is prepared on which a nitride semiconductor is epitaxially grown. A Si layer is formed on the cap layer 106, which is the top layer of the epitaxial growth. ３ N ４ an insulating film 312 made of SiO ２ and an insulating film 313 made of Si ３ N ４ The insulating film 312 is formed by in-situ Si ３ N ４ It may be a film, ex-situ Si ３ N ４ The insulating film 313 is formed by, for example, a plasma CVD method. The insulating film 303 is formed by, for example, an LPCVD method, but may be formed by an atmospheric pressure CVD method. For example, the thicknesses of the insulating films 312, 313, and 303 are 50 nm, 50 nm, and 100 nm, respectively, but are not limited to this.

[0135] 7B, a source electrode 201 and a drain electrode 202 are formed. Before the source electrode 201 and the drain electrode 202 are formed, a process for passivating regions other than the transistor formation region is carried out.

[0136] In the process of forming the source electrode 201 and the drain electrode 202, portions of each of the insulating films 303, 313, and 312 are removed to form contact holes. The formation and patterning of the metal film, as well as the alloying and other processes, are the same as in the manufacturing method of the semiconductor device 1. Note that when the lower surface of the source-side extension 203s of the gate electrode 203 has a three-stage structure, the distance between the gate electrode 203 and the source electrode 201 becomes shorter. If the gate electrode 203 and the source electrode 201 are too close, the parasitic capacitance to the side surface of the source electrode 201 increases. For this reason, the distance between the gate and the source is made longer, for example, by 0.2 μm, compared to when the lower surface of the source-side extension 203s has a two-stage structure.

[0137] Next, Si ３ N ４ 7C, the insulating film 303 is patterned to form a fifth insulating film 303s and a sixth insulating film 303d. Specifically, a part of the insulating film 303 is removed by anisotropic dry etching. The dry etching is performed using, for example, CF ４ It is performed by plasma ions of the gas CF ４ The gas is Si ３ N ４ and SiO ２ There is a difference in etching rate between CF and CF, and they have selective removal properties. ４ The gas is Si ３ N ４ The etching rate for SiO is fast. ２ Therefore, the etching rate is slow. ２ The insulating film 313 made of Si functions as an etch stopper layer. ３ N ４ After removing the insulating film 303 made of SiO 2 , the progress of etching can be stopped by the insulating film 313. Therefore, the shape shown in FIG. 7C can be easily formed. ２ The insulating film 313 is useful for forming a gate electrode 203 having a three-stage structure on the lower surface. ３ N ４In this case, the gate electrode 203 having a three-stage bottom surface can be formed by strictly controlling the etching time and film thickness.

[0138] Next, as shown in FIG. 7D, a gate opening is formed in the gate region 401 for forming a gate. In the formation of the gate opening, a SiO ２ and an insulating film 313 made of Si ３ N ４ The insulating film 312 made of, for example, CF is removed. ４ This is done by dry etching using SiO ２ The etching rate for Si ３ N ４ Although the etching rate is slower than that for SiO ２ The insulating film 313 made of Si is etchable because it has a thickness of about 50 nm at most. ３ N ４ Film 312s and SiO ２ film 313s (first insulating film 311s) and the Si ３ N ４ Film 312d and SiO ２ A film 313d (third insulating film 311d) is formed.

[0139] Next, as shown in FIG. 7E, a Si film is formed on the entire surface including the opening of the gate region 401. ３ N ４The insulating film 302 is formed by, for example, plasma CVD, but may also be formed by LPCVD. The insulating film 302 is a silicon nitride film that serves as the base for the sidewalls 304s, 304d, 306s, and 306d, as well as the second insulating film 302s and the fourth insulating film 302d. Specifically, the insulating film 302 is formed to the same thickness (e.g., 100 nm) as the first insulating film 311s and the third insulating film 311d. By making the film thicknesses uniform, the heights of the sidewalls 304s and 304d, the first insulating film 311s, and the third insulating film 311d can be made uniform. Furthermore, by making the film thicknesses of the fifth insulating film 303s and the sixth insulating film 303d the same as the film thickness of the insulating film 302, the heights of the sidewalls 306s and 306d, the fifth insulating film 303s, and the sixth insulating film 303d can be made uniform.

[0140] Next, as shown in FIG. 7F, a photoresist 501 having an opening of a predetermined shape is formed, and then a CF ４ Anisotropic dry etching is performed using plasma ions containing , thereby removing the insulating film 302 exposed in the openings of the photoresist 501. The photoresist 501 has a shape that covers the source electrode 201 and the drain electrode 202, but does not cover at least the gate region 401. The etching amount is the thickness of the deposited insulating film 302, and is, for example, 50 nm.

[0141] 7G, the dry etching results in the formation of the second insulating film 302s, the fourth insulating film 302d, and the sidewalls 304s, 304d, 306s, and 306d. As a result of the asymmetry of the photoresist 501 with respect to the gate region 401, the second insulating film 302s on the source side is formed larger than the fourth insulating film 302d on the drain side. That is, the distance from the second insulating film 302s on the source side to the gate region 401 is shorter than the distance from the fourth insulating film 302d on the drain side to the gate region 401.

[0142] Next, as shown in FIG. 7H , the gate electrode 203 is formed. The specific formation method is the same as the method described with reference to FIG. 6G . In the example shown in FIG. 7H , three insulating films, namely, the first insulating film 311s, the fifth insulating film 303s, and the second insulating film 302s, are arranged in a stepped pattern on the source electrode 201 side of the gate region 401. Therefore, by forming the gate electrode 203 so as to cover the ends of these three insulating films, a step can be formed on the underside of the source-side protrusion 203s of the gate electrode 203.

[0143] 7I, an insulating layer 305 is formed to protect the gate electrode 203. For example, the insulating layer 305 is formed of a Si film by plasma CVD or LPCVD. ３ N ４ Form a film.

[0144] Next, as shown in FIG. 7J, the source field plate 204 is formed by depositing a metal film by sputtering and removing it by dry etching. Alternatively, the source field plate 204 may be formed by a vapor deposition lift-off method. When Au is used, the vapor deposition lift-off method is used because dry etching is not possible.

[0145] Next, in order to ensure electrical connection with the source electrode 201 and the drain electrode 202, openings are first formed in the insulating layer 305, the second insulating film 302s, and the fourth insulating film 302d. The openings are formed by forming a photoresist having openings so as to expose the source electrode 201 and the drain electrode 202, and then by using a CF ４ The openings are then covered with barrier metals 205s and 205d and wiring metals 206s and 206d having predetermined shapes. The barrier metals 205s and 205d and the wiring metals 206s and 206d are formed by sputtering and dry etching, or a deposition lift-off method, or the like.

[0146] Through the above steps, the semiconductor device 5 shown in FIG. 5 can be manufactured.

[0147] The semiconductor device 4 according to the fourth embodiment is manufactured by modifying some of the steps included in the manufacturing method of the semiconductor device 5 described above. In the case of the semiconductor device 4, in the step described with reference to FIG. 7C , the sixth insulating film 303d remaining on the drain electrode 202 side can be made smaller. Also, in the step described with reference to FIG. 7F , the shape of the photoresist 501 can be changed. Specifically, the portion of the photoresist 501 that overlaps with the third insulating film 311d on the drain side in a plan view can be made larger to move closer to the gate region 401. Note that the sixth insulating film 303d and the third insulating film 311d may also be completely removed.

[0148] (Effects, etc.) Next, effects, etc. of the semiconductor device according to the present disclosure will be described. Data measured on a prototype of the semiconductor device 2 according to the second embodiment will be described below with reference to FIGS.

[0149] 8 is a small-signal equivalent circuit diagram of the semiconductor device 2 (transistor). By actually measuring the S parameters of the transistor, it is possible to extract each parameter in the equivalent circuit shown in FIG. 8. Specifically, it is possible to obtain the gate resistance Rg and the parasitic capacitances Cgs and Cds that are the object of reduction in this disclosure.

[0150] In the equivalent circuit shown in FIG. 8 , the gate resistance Rg is the main component of the resistance Ri. Hereinafter, for simplicity, the resistance Ri is considered to be the gate resistance Rg. Note that the gate resistance Rg can be calculated more accurately by separating and measuring the intrinsic resistance portion between the gate electrode 203 and the 2DEG 107 (cold measurement method). However, since multiple measurements and calculations are required, Ri is simply considered to be Rg.

[0151] 9 is a diagram for explaining gain improvement, in which the horizontal axis represents frequency and the vertical axis represents gain.

[0152] The maximum stable gain (MSG) and the maximum available gain (MAG) are used as indices for comparing the gain of semiconductor devices. Both MSG and MAG are quantities determined from S parameters, and are therefore convenient indices for devices.

[0153] Specifically, MSG and MAG are represented by the following formulas (1) and (2), respectively.

[0154]

[0155] Note that MAG cannot be defined unless K>1, so MSG is used in the range of K≦1. K is called Kurokawa's stability coefficient and is an index of stabilization against transistor oscillation. While K>1 is the desirable condition, it can be corrected by the circuit or usage, so it can also be used when K<1. For this reason, MSG is effective when applying devices to actual circuits.

[0156] Since MAG measurements are performed at high frequencies, they are limited by the upper frequency limit of the measuring instrument. For frequencies above the measurement limit, extrapolation is performed with a slope of 6 dB / oct. This slope is based on the model that in the high frequency range, gain is inversely proportional to the square of frequency.

[0157] The maximum oscillation frequency fmax is the frequency at which the minimum gain when MAG is extrapolated, i.e., 0 dB. fmax is required to be sufficiently high relative to the application frequency, for example, at least three times the application frequency. Note that the original definition of fmax is the frequency at which Mason's maximum unilateral gain Mu is 0 dB, and this coincides with the maximum oscillation frequency determined from MAG.

[0158] Generally, the higher the switching frequency Freq@K=1 between MSG and MAG, the higher the fmax becomes. Therefore, it becomes possible to compare the superiority or inferiority of the gain at the switching frequency Freq@K=1.

[0159] Below, the results of comparing the example and the comparative example with respect to the resistance Ri (corresponding to the gate resistance Rg), the parasitic capacitance Cgs, and the switching frequency Freq@K=1 will be described. As described above, the example is a prototype having the configuration of the semiconductor device 2 shown in FIG. 2. The comparative example is a prototype having the configuration of the semiconductor device 2x shown in FIG. 10.

[0160] The semiconductor device 2x according to the comparative example differs from the semiconductor device 2 in the cross-sectional shape of the gate electrode 203x. Specifically, no step is formed on the lower surface of the source-side overhang 203sx of the gate electrode 203x, and the height Hgs of the source-side end of the lower surface of the source-side overhang 203sx is the same as the height Hgd of the drain-side end of the lower surface of the drain-side overhang 203d. In the source-side insulating layer 300sx, a sidewall 304s and a first insulating film 311s are provided between the source-side overhang 203sx and the nitride semiconductor layer 104, but a second insulating film 302s is not provided.

[0161] The extension length of the source-side extension 203sx is approximately 0.2 μm longer than the extension length of the drain-side extension 203d. In order to reduce the gate resistance Rg, it is desirable to increase the cross-sectional area of ​​the gate electrode 203, but extending it toward the drain electrode 202 side causes problems such as reduced gain and efficiency due to an increase in parasitic capacitance Cgd between the gate and drain. By extending it toward the source electrode 201 side, the parasitic capacitance Cgs between the gate and source increases, but the effect of improving gain characteristics is obtained by reducing the gate resistance Rg.

[0162] FIG. 11 is a graph comparing the drain voltage dependence of gate resistance Ri (Rg) between the comparative example and the example. In FIG. 11, voltages such as "5V" written near each plot represent drain voltages. This also applies to FIGS. 12 and 13 described below. The drain voltage corresponds to the potential difference between the source electrode 201 and the drain electrode 202. As shown in FIG. 11, when comparing the gate resistance Ri at each drain voltage, it can be seen that the example was able to reduce the gate resistance Ri compared to the comparative example.

[0163] 12 is a graph comparing the drain voltage dependence of the gate-source parasitic capacitance Cgs between the comparative example and the example. As shown in FIG. 12, it can be seen that the parasitic capacitance Cgs is almost the same between the comparative example and the example. That is, in the example, although the opposing area between the source-side extension 203s of the gate electrode 203 and the 2DEG 107 is increased, the increase in parasitic capacitance Cgs can be suppressed by providing a step on the lower surface.

[0164] 13 is a graph comparing the drain voltage dependence of the switching frequency Freq@K=1 between the comparative example and the example. As shown in FIG. 13, the switching frequency Freq@K=1 is higher in the example than in the comparative example at each drain voltage. When the drain voltage is 28 V, the switching frequency Freq@K=1 is lowest, but still achieves a high value of 10 GHz or more, which is double digits. In other words, it can be seen that a stable gain is obtained even at 10 GHz.

[0165] As described above, the structure of the gate electrode 203 according to the present disclosure can achieve both a reduction in gate resistance and suppression or reduction of increases in the parasitic capacitances Cgs and Cgd, thereby improving the gain performance over a wide frequency range.

[0166] While the improvement in gain performance has been described here based on an embodiment having the structure of semiconductor device 2, the gain performance can be similarly improved for semiconductor devices 1, 3 to 5. That is, in all of semiconductor devices 1, 3 to 5, the lower surface 203sa of the source-side extension 203s of the gate electrode 203 has a step, so that it is possible to achieve both a reduction in gate resistance and suppression or reduction of increases in parasitic capacitances Cgs and Cgd. Therefore, semiconductor devices 1, 3 to 5 can improve gain performance over a wide frequency range.

[0167] (Summary) The features of the semiconductor device described based on the above embodiment will be described below.

[0168] A semiconductor device according to a first aspect of the present disclosure includes a substrate, a channel layer made of a nitride semiconductor containing Ga and provided above the substrate, a nitride semiconductor layer provided above the channel layer, the nitride semiconductor layer having a larger band gap than the channel layer and including a barrier layer containing Ga, a source electrode and a drain electrode provided above the substrate and spaced apart from each other, gate electrodes provided above the barrier layer and between the source electrode and the drain electrode and spaced apart from each other, a drain-side insulating layer provided above the nitride semiconductor layer between the gate electrode and the drain electrode, and a gate insulating layer provided above the nitride semiconductor layer between the gate electrode and the source electrode. and a source-side insulating layer provided above the nitride semiconductor layer, wherein the gate electrode includes a junction portion that forms a Schottky junction with the nitride semiconductor layer, a first protruding portion that protrudes further toward the drain electrode than the junction, and a second protruding portion that protrudes further toward the source electrode than the junction, wherein the protruding length of the second protruding portion is longer than the protruding length of the first protruding portion, a lower surface of the second protruding portion has a step, and the height of the end of the lower surface of the second protruding portion closest to the source electrode from the upper surface of the nitride semiconductor layer is greater than the height of the end of the lower surface of the first protruding portion closest to the drain electrode from the upper surface of the nitride semiconductor layer.

[0169] As a result, by forming the gate electrode to extend longer toward the source side than the drain side, it is possible to suppress an increase in parasitic capacitance Cgd and increase the cross-sectional area of ​​the gate electrode. Increasing the cross-sectional area of ​​the gate electrode makes it possible to reduce gate resistance Rg. Furthermore, by providing a step on the underside of the second protruding portion on the source side, it is possible to suppress an increase in parasitic capacitance Cgs. In this way, by reducing gate resistance Rg and suppressing an increase in parasitic capacitances Cgd and Cgs, it is possible to improve the gain performance of the transistor.

[0170] A semiconductor device according to a second aspect of the present disclosure is the semiconductor device according to the first aspect, wherein the thickness of the first protruding portion and the thickness of the second protruding portion are constant and equal to each other.

[0171] This allows the cross-sectional area of ​​the gate electrode to be increased, and the gate resistance Rg to be further reduced.

[0172] A semiconductor device according to a third aspect of the present disclosure is the semiconductor device according to the first or second aspect, wherein the source-side insulating layer includes a first insulating film located between the second protrusion and the nitride semiconductor layer, and a second insulating film located between the second protrusion and the first insulating film, and an end of the second insulating film on the drain electrode side is set back toward the source electrode than an end of the first insulating film on the drain electrode side.

[0173] This allows a step to be formed in the source-side insulating layer by the stacked structure of the first insulating film and the second insulating film. By forming the gate electrode so as to cover the step in the source-side insulating layer, a step can be formed with high precision on the underside of the second protruding portion on the source side of the gate electrode.

[0174] A semiconductor device according to a fourth aspect of the present disclosure is the semiconductor device according to the third aspect, wherein the second insulating film is thicker than the first insulating film.

[0175] This makes it possible to further reduce the parasitic capacitance Cgs by making the second insulating film thicker.

[0176] A semiconductor device according to a fifth aspect of the present disclosure is the semiconductor device according to the third or fourth aspect, wherein the second insulating film includes a silicon oxide film.

[0177] This allows the SiO ２ By using the above, the parasitic capacitance Cgs can be further reduced.

[0178] A semiconductor device according to a sixth aspect of the present disclosure is the semiconductor device according to any one of the third to fifth aspects, wherein the first insulating film includes a silicon nitride film that covers and contacts the nitride semiconductor layer, and a silicon oxide film provided above the silicon nitride film.

[0179] This allows the SiO ２ By using the above, the parasitic capacitance Cgs can be further reduced.

[0180] A semiconductor device according to a seventh aspect of the present disclosure is a semiconductor device according to any one of the third to sixth aspects, wherein the drain-side insulating layer includes a third insulating film that contacts and covers the nitride semiconductor layer in a range from a position that overlaps the first protrusion portion in a planar view of the substrate to the drain electrode, and a fourth insulating film provided above the third insulating film, and the fourth insulating film does not overlap the first protrusion portion in a planar view of the substrate.

[0181] As a result, since the drain-side insulating layer has a laminated structure, the piezoelectric stress increases directly below the laminated portion, increasing the carrier concentration, thereby reducing the on-resistance Ron.

[0182] A semiconductor device according to an eighth aspect of the present disclosure is a semiconductor device according to the seventh aspect, wherein the drain-side insulating layer further includes a sixth insulating film provided between the third insulating film and the fourth insulating film, and the sixth insulating film does not overlap the first protrusion portion in a planar view of the substrate.

[0183] This can further enhance the effect of reducing the on-resistance Ron.

[0184] A semiconductor device according to a ninth aspect of the present disclosure is the semiconductor device according to the seventh or eighth aspect, wherein the third insulating film includes a silicon nitride film that covers and contacts the nitride semiconductor layer, and a silicon oxide film provided above the silicon nitride film.

[0185] This allows the SiO ２ By using this, the parasitic capacitance Cgd can be further reduced.

[0186] A semiconductor device according to a tenth aspect of the present disclosure is a semiconductor device according to any one of the third to ninth aspects, wherein the source-side insulating layer further includes a fifth insulating film that overlaps the second protrusion portion in a planar view of the substrate and is located between the first insulating film and the second insulating film, and the drain electrode side end of the fifth insulating film is set back toward the source electrode from the drain electrode side end of the first insulating film, and the drain electrode side end of the second insulating film is set back toward the source electrode from the drain electrode side end of the fifth insulating film.

[0187] This increases the number of stacked insulating films included in the source-side insulating layer, thereby increasing the number of steps on the underside of the second protruding portion on the source side of the gate electrode, thereby further enhancing the effect of reducing the parasitic capacitance Cgs.

[0188] While the semiconductor device according to one or more aspects has been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0189] For example, the drain-side insulating layer 300d does not have to be provided in a portion between the drain electrode 202 and the gate electrode 203. Specifically, the drain-side insulating layer 300d only needs to be provided in at least a range that overlaps with the drain-side extension 203d in a planar view. The drain-side insulating layer 300d does not have to be provided in a range from the end 203dd of the drain-side extension 203d on the drain electrode 202 side to the drain electrode 202 in a planar view.

[0190] The source-side insulating layer 300s does not have to be provided in a portion between the source electrode 201 and the gate electrode 203. Specifically, the source-side insulating layer 300s only needs to be provided in at least a range that overlaps with the source-side overhang 203s in plan view. The source-side insulating layer 300s does not have to be provided in a range from the end 203ss of the source-side overhang 203s on the source electrode 201 side to the source electrode 201 in plan view.

[0191] The first insulating film 301s and the third insulating film 301d are made of Si, which has different film properties. ３ N ４ The film may have a laminated structure. ３ N ４ Similarly, the films 312s and 312d are Si films with different film properties. ３ N ４ The laminated structure may have a laminated structure of films, for example, an in-situ Si ３ N ４ Membranes and in-situ Si ３ N ４ Ex-situ Si provided above the film ３ N ４ and a membrane.

[0192] In-situ Si ３ N ４ The film is a Si film grown continuously without exposure to the atmosphere in a growth furnace for epitaxial growth of nitride semiconductors. ３ N ４ The film consists of ex-situ Si ３ N ４ The film is in-situ Si ３ N ４ Si formed by exposure to air after film formation ３ N ４ The film consists of ex-situ Si ３ N ４ The film is formed by, for example, LPCVD or atmospheric pressure CVD.

[0193] Due to differences in manufacturing methods, in-situ Si ３ N ４ Film and Ex-situ Si３ N ４ The film quality is different between the in-situ Si film and the ３ N ４ The film is ex-situ Si ３ N ４ It is a denser film than the in-situ Si film. ３ N ４ The film density of the film is ３ N ４ It is greater than the film density of the film.

[0194] In addition, in-situ Si ３ N ４ Film and Ex-situ Si ３ N ４ There is a difference in at least one of the halogen concentration and the interface oxygen concentration between the film and the in-situ Si film. ３ N ４ The halogen concentration of the film is Ex-situ Si ３ N ４ (b) the halogen concentration is lower than that of the in-situ Si film; ３ N ４ The oxygen concentration at the interface between the film and the nitride semiconductor layer 104 is ３ N ４ Film and Ex-situ Si ３ N ４ The oxygen concentration at the interface with the film is lower than that at the interface with the film. ３ N ４ The halogen concentration of the film is 1×10 １８ atom / cm ３ and Ex-situ Si ３ N ４ The halogen concentration of the film is 1×10 １８ atom / cm ３ and (d) In-situ Si ３ N ４ The oxygen concentration at the interface between the film and the nitride semiconductor layer 104 is 1×10 ２０ atom / cm ３ and In-situ Si ３ N ４ Film and Ex-situ Si３ N ４ The oxygen concentration at the interface with the film is 1×10 ２０ atom / cm ３ It satisfies at least one of the following:

[0195] In-situ Si ３ N ４ The thickness of the film is, for example, 15 nm or more, but is not limited to this. ３ N ４ The thickness of the film may be 20 nm or more. ３ N ４ The thickness of the film is 30 nm or less, but may be 25 nm or less.

[0196] Ex-situ Si ３ N ４ The thickness of the film is, for example, 30 nm or more and 60 nm or less. ３ N ４ The film thickness is In-situ Si ３ N ４ The thickness is equal to or greater than the thickness of the film.

[0197] The drain-side insulating layer 300d and / or the source-side insulating layer 300s are formed by in-situ Si ３ N ４ The membrane and the ex-situ Si layer provided thereon ３ N ４ By having a laminated structure with the film, in-situ Si ３ N ４ Ex-situ Si while utilizing the high piezoelectric stress of the film ３ N ４ The wafer warpage suppression effect of the film can be effectively utilized. ３ N ４ The lateral hopping of electrons in the film can be utilized to suppress the accumulation of fixed charges, thereby suppressing current collapse. Therefore, the semiconductor device according to the present disclosure can achieve a semiconductor device having high drive current characteristics and low wafer warpage characteristics.

[0198] In addition, although the source electrode 201 and the drain electrode 202 are formed so as to be embedded in the barrier layer 105 and the channel layer 103, respectively, this is not limitative. The source electrode 201 and the drain electrode 202 may be provided on the upper surface of the barrier layer 105 or the cap layer 106. In other words, the source electrode 201 and the drain electrode 202 do not need to be in contact with the 2DEG 107.

[0199] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents.

[0200] The present disclosure can be used, for example, in a power amplifier for high-output or high-frequency applications, a wireless communication base station or terminal device in which the power amplifier is used, or a wireless power supply device that transmits power using microwaves.

[0201] 1, 2, 3, 4, 5 Semiconductor device 101 Substrate 102 Buffer layer 103 Channel layer 104 Nitride semiconductor layer 105 Barrier layer 106 Cap layer 107 2DEG 201 Source electrode 202 Drain electrode 203 Gate electrode 203L Lower part of gate electrode 203U Upper part of gate electrode 203a Junction 203d Drain side extension 203s Source side extension 203da, 203sa Lower surface 203dd, 203ss End 203sb Upper step 203sc Lower step 203sd Side wall 204 Source field plate 205d, 205s Barrier metal 206d, 206s Wiring metal 300d Drain side insulating layer 300s Source side insulating layer 301, 302, 303, 312, 313 Insulating films 301d, 311d Third insulating film 301s, 311s First insulating film 302d Fourth insulating film 302s Second insulating film 303d Sixth insulating film 303s Fifth insulating film 304d, 304s, 306d, 306s Sidewall 305 Insulating layer 312d, 312s Si ３ N ４ Film 313d, 313s SiO ２ Film 401 Gate region 501 Photoresist

Claims

1. A substrate; a channel layer made of a nitride semiconductor containing Ga provided above the substrate; a nitride semiconductor layer provided above the channel layer, the nitride semiconductor layer including a barrier layer having a band gap larger than that of the channel layer and containing Ga elements; a source electrode and a drain electrode spaced apart above the substrate; a gate electrode provided above the barrier layer between the source electrode and the drain electrode and spaced apart from each other; a drain-side insulating layer provided above the nitride semiconductor layer between the gate electrode and the drain electrode; a source-side insulating layer provided above the nitride semiconductor layer between the gate electrode and the source electrode, The gate electrode is a junction portion that forms a Schottky junction with the nitride semiconductor layer; a first protruding portion protruding toward the drain electrode side beyond the junction portion; a second protruding portion that protrudes further toward the source electrode than the junction portion, The protrusion length of the second protrusion portion is longer than the protrusion length of the first protrusion portion, The lower surface of the second protruding portion has a step, a height from the upper surface of the nitride semiconductor layer of an end of a lower surface of the second protruding portion that is closest to the source electrode is greater than a height from the upper surface of the nitride semiconductor layer of an end of a lower surface of the first protruding portion that is closest to the drain electrode; In a plan view of the substrate, the gate electrode and the source electrode do not overlap each other. Semiconductor device.

2. The thickness of the first overhanging portion and the thickness of the second overhanging portion are constant and equal to each other. The semiconductor device according to claim 1 .

3. The source-side insulating layer is a first insulating film located between the second protruding portion and the nitride semiconductor layer; a second insulating film located between the second protruding portion and the first insulating film, an end of the second insulating film on the drain electrode side is set back toward the source electrode side with respect to an end of the first insulating film on the drain electrode side; 3. The semiconductor device according to claim 1.

4. The thickness of the second insulating film is greater than the thickness of the first insulating film. The semiconductor device according to claim 3 .

5. the second insulating film includes a silicon oxide film; The semiconductor device according to claim 3 .

6. The first insulating film is a silicon nitride film covering and in contact with the nitride semiconductor layer; a silicon oxide film provided above the silicon nitride film, The semiconductor device according to claim 3 .

7. The drain-side insulating layer is a third insulating film that covers and contacts the nitride semiconductor layer in a range from a position that overlaps the first protruding portion to the drain electrode in a plan view of the substrate; a fourth insulating film provided above the third insulating film, the fourth insulating film does not overlap the first protruding portion in a plan view of the substrate; The semiconductor device according to claim 3 .

8. the drain-side insulating layer further includes a sixth insulating film provided between the third insulating film and the fourth insulating film, the sixth insulating film does not overlap the first protruding portion in a plan view of the substrate; The semiconductor device according to claim 7 .

9. The third insulating film is a silicon nitride film covering and in contact with the nitride semiconductor layer; a silicon oxide film provided above the silicon nitride film, The semiconductor device according to claim 7 .

10. the source-side insulating layer further includes a fifth insulating film that overlaps the second protruding portion in a plan view of the substrate and is located between the first insulating film and the second insulating film, an end of the fifth insulating film on the drain electrode side is set back toward the source electrode side with respect to an end of the first insulating film on the drain electrode side; an end of the second insulating film on the drain electrode side is set back toward the source electrode side with respect to an end of the fifth insulating film on the drain electrode side; The semiconductor device according to claim 3 .