Semiconductor device, battery module, electric power module, and electric vehicle

Abstract

This semiconductor device includes: a low-voltage-side frame to which is connected a low-voltage chip driven by input voltage and which is connected to a ground potential; and a high-voltage-side frame which is insulated from the low-voltage-side frame and to which is connected a high-voltage chip which is supplied with a supply voltage having a higher voltage than the input voltage. The high-voltage-side frame is connected to a reference potential.

Description

Semiconductor device, battery module, electric power module and electric vehicle

[0001] The present invention relates to a semiconductor device, and more particularly to a battery module having the semiconductor device, an electric power module using the battery module, and an electric vehicle using the electric power module.

[0002] 2. Description of the Related Art In semiconductor packages, a configuration in which a plurality of chips are attached to a common frame is known (see, for example, Japanese Patent Application Laid-Open No. 2003-122998).

[0003] Japanese Patent Application Laid-Open No. 2019-169512

[0004] It is desirable to further reduce the influence of noise generated during operation of other chips.

[0005] In order to achieve the above object, the present disclosure provides a semiconductor device having a low-voltage side frame connected to a low-voltage chip driven by an input voltage and connected to ground potential, and a high-voltage side frame connected to a high-voltage chip insulated from the low-voltage side frame and supplied with a supply voltage higher than the input voltage, the high-voltage side frame being connected to a reference potential.

[0006] According to the present disclosure, it is possible to reduce the influence of noise generated in one of the low-voltage chip and the high-voltage chip on the operation of the other chip.

[0007] Fig. 1 is a schematic configuration diagram of an electric vehicle. Fig. 2 is a schematic layout diagram of a battery module as viewed from above. Fig. 3 is a configuration diagram showing a schematic configuration of a battery module. Fig. 4 is a front cross-sectional view of the semiconductor device shown in Fig. 1. Fig. 5 is a diagram showing a schematic configuration of a semiconductor device of a modified example.

[0008] In this specification, a MOS (Metal Oxide Semiconductor field effect transistor) refers to a transistor whose gate structure is made up of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value, an insulating layer, and a P-channel, N-channel, or intrinsic semiconductor layer. In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of a metal, an oxide, and a semiconductor.

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this specification, when it is stated that elements are connected to each other, this includes not only a mechanical connection but also an electrical connection, in other words, a state in which electricity flows. Therefore, "connect" includes an "electrical connection."

[0010] In addition, there are cases where a device is configured so that it can obtain electricity to operate by connecting it to an element or terminal at a certain potential. In such cases, it is explained that the connected device is supplied with a voltage that is the potential difference between the reference potential given to the element or terminal and the potential of the element.

[0011] <Electric vehicle A> Fig. 1 is a schematic diagram of the electric vehicle A. In the electric vehicle A, an electric power module 600 is attached to an axle Ax to which wheels Wh are attached. The electric power module 600 is configured to use electric energy to rotate the axle Ax and propel the electric vehicle A.

[0012] As shown in FIG. 1 , the electric power module 600 includes a battery module 300 , a motor 400 , and a motor control unit (MCU) 500 .

[0013] The motor 400 is an example of a drive source, and a rotating shaft (not shown) is directly or indirectly connected to the axle Ax. In many cases, the electric vehicle A is configured to use an AC motor as the motor 400. Because the battery 200 is a DC motor, the motor control unit 500 is configured to convert the DC current of the battery 200 into AC and supply it to the motor 400. The motor control unit 500 is also configured to control the current supplied to adjust the rotation speed, torque, etc. of the motor 400.

[0014] Even when a DC motor is used as the motor 400, the motor control unit 500 is configured to control the rotation speed, torque, etc. of the motor 400.

[0015] <Battery Module 300> Next, details of the battery module 300 will be described with reference to the drawings. Fig. 2 is a schematic layout diagram of the battery module 300 as seen from above. Fig. 3 is a configuration diagram showing the schematic configuration of the battery module 300. Fig. 4 is a front cross-sectional view of the semiconductor device 100 shown in Fig. 1. Note that in the cross-sectional view of the semiconductor device 100 shown in Fig. 4, the connection terminal Nd1, pad 26, pad 43, and wire 5 hidden by the package Pg are shown in the same cross section for ease of explanation.

[0016] The battery module 300 includes the semiconductor device 100 and a battery 200. The battery 200 generates a high supply voltage, such as 400 V, required to drive the motor 400. The battery module 300 is connected to a motor control unit 500.

[0017] In electric vehicle A, battery module 300 is connected to motor control unit 500. Battery module 300 directly supplies the supply voltage from battery 200 to motor control unit 500. Battery module 300 also steps down the supply voltage output from battery 200 to an operating voltage Vs, such as 10 V, 5 V, or 3.3 V, for driving a control circuit (not shown) of motor control unit 500, and supplies the voltage to motor control unit 500.

[0018] 2 and 3, the battery 200 has a positive electrode 201 and a negative electrode 202. The battery 200 is configured such that the potential of the positive electrode 201 is higher than the potential of the negative electrode 202 by the amount of the supply voltage. In other words, the potentials of the positive electrode 201 and the negative electrode 202 of the battery 200 vary depending on the circuit to which they are connected.

[0019] <Semiconductor device 100> Next, the configuration of the semiconductor device 100 will be described. The semiconductor device 100 supplies an operating voltage Vs, which is a stepped-down voltage supplied from the battery 200, to the motor control unit 500. The semiconductor device 100 is also configured to supply voltages other than the operating voltage Vs to the motor control unit 500. The motor control unit 500 is driven by the operating voltage Vs supplied from the semiconductor device 100, and can determine the state of the battery module 300 based on the other voltages supplied from the semiconductor device 100.

[0020] As shown in Figures 2 to 4, the semiconductor device 100 has a low-voltage side frame 1, a low-voltage chip 2, a high-voltage side frame 3, a high-voltage chip 4, and connection terminals Nd1 to Nd17. As shown in Figures 2 and 4, the low-voltage side frame 1, the low-voltage chip 2, the high-voltage side frame 3, and the high-voltage chip 4 of the semiconductor device 100 are sealed in a resin package Pg. Furthermore, portions of the connection terminals Nd1 to Nd17 are also sealed in the package Pg. In other words, the connection terminals Nd1 to Nd17 have portions exposed to the outside of the package Pg. All of the connection terminals Nd1 to Nd17 are conductive.

[0021] The high-voltage side frame 3 is made of a conductive plate material. As shown in FIG. 2 , the connection terminals Nd3 and Nd4 are integrally formed with the high-voltage side frame 3. The high-voltage side frame 3 is connected to the ground potential GND via the connection terminals Nd3 and Nd4. Alternatively, the connection terminals Nd3 and Nd4 may be arranged apart from the high-voltage side frame 3, and may be connected to the high-voltage side frame 3 by wires. As long as the connection terminals Nd3 and Nd4 are reliably connected to the high-voltage side frame 3, the connection method is not limited.

[0022] The connection terminal Nd1 and the connection terminal Nd2 are respectively connected to the positive electrode 201 and the negative electrode 202 of the battery 200. The connection terminal Nd1 and the connection terminal Nd2 are connected to a high-voltage chip 4 connected to a high-voltage frame 3 by a conductive wire 5. The positive electrode 201 of the battery 200 and the connection terminal Nd1, and the negative electrode terminal 202 of the battery and the connection terminal Nd2 are respectively connected by wires.

[0023] In the battery module 300, the supply voltage from the battery 200 is supplied to the connection terminals Nd1 and Nd2 of the semiconductor device 100. At this time, the potential of the connection terminal Nd1 is higher than the potential of the connection terminal Nd2 by the amount of the supply voltage.

[0024] The low-voltage side frame 1 is made of a conductive plate material, similar to the high-voltage side frame 3. The connection terminals Nd5 and Nd17 are formed integrally with the low-voltage side frame 1. The low-voltage side frame 1 is connected to the ground potential GND via the connection terminals Nd5 and Nd17. Note that the connection terminals Nd5 and Nd17 may be arranged separately from the low-voltage side frame 1, and may be connected to the low-voltage side frame 1 by connecting the connection terminals Nd5 and Nd17 with wires. The connection method is not limited as long as the connection terminals Nd5 and Nd17 are reliably connected to the low-voltage side frame 1.

[0025] The connection terminals Nd6 to Nd16 are connected to the low-voltage chip 2 connected to the low-voltage side frame 1 via conductive wires 5.

[0026] The low-voltage side frame 1 is configured to be insulated from the high-voltage side frame 3. More specifically, the low-voltage side frame 1 and the high-voltage side frame 3 are not electrically connected, and are configured to be spaced apart enough that if noise occurs in one frame, the other frame is not affected by that noise.

[0027] In the semiconductor device 100 of the present disclosure, the low-voltage side frame 1 and the high-voltage side frame 3 are insulated from each other, but both have a reference potential of the ground potential GND.

[0028] The low-voltage chip 2 is connected to the ground potential GND by being connected to the low-voltage side frame 1. In other words, the ground potential GND is the reference potential of the low-voltage chip 2.

[0029] 3, the low-voltage chip 2 receives an input voltage Vin and is driven by the input voltage Vin. The input voltage Vin is a voltage for driving the circuitry of the semiconductor device 100 and is supplied from a voltage source (not shown). Note that the voltage source may be a battery separate from the battery 200, or may include a power supply circuit that steps down the voltage supplied by the battery 200.

[0030] The low-voltage chip 2 is supplied with an operating voltage Vs from the high-voltage chip 4. The operating voltage Vs is one of the output voltages output from the semiconductor device 100, and is a voltage for driving the circuit included in the motor control unit 500 in the electric power module 600 of the present disclosure. The semiconductor device 100 also outputs a first confirmation voltage Vc1, a second confirmation voltage Vc2, and a check voltage PNVOUT, which are used by the motor control unit 500 to detect the supply voltage applied to the high-voltage chip 4. The semiconductor device 100 also outputs a voltage Vft for checking the operating state of the semiconductor device 100.

[0031] The low-voltage chip 2 is an amplifier chip and includes a UVLO (Under Voltage Lock Out) circuit 21, an inspection circuit 22, a constant voltage circuit 23, a check amplifier 24, and a fault signal output circuit 25. As shown in Figure 2, the low-voltage chip 2 is connected to connection terminals Nd6 to Nd16. The low-voltage chip 2 is connected to each connection terminal by wires 5 connecting pads 26 provided on the outer surface of the low-voltage chip 2 to the connection terminals.

[0032] The specifications of the semiconductor device 100 prescribe an appropriate voltage range for the input voltage Vin. The UVLO circuit 21 compares the input voltage Vin with a predetermined UVLO determination voltage that is lower than the lower limit of that voltage range, and outputs a UVLO signal Sv. The UVLO signal Sv is at a high level when the input voltage Vin is equal to or lower than the UVLO determination voltage, and is at a low level otherwise. A state in which the input voltage Vin is equal to or lower than the UVLO determination voltage indicates an undervoltage abnormality state in which the input voltage Vin is too low. In other words, the UVLO circuit 21 outputs a high-level UVLO signal Sv when an undervoltage abnormality state occurs.

[0033] The inspection circuit 22 is connected to the connection terminals Nd15 and Nd16 connected to the ground potential GND, and compares the ground potential GND input from each of the connection terminals Nd15 and Nd16 with a threshold value to output a TEST signal St. The inspection circuit 22 is configured so that the TEST signal St becomes high level when at least one of the signals input from each of the connection terminals Nd15 and Nd16 is high level.

[0034] The constant voltage circuit 23 is a circuit that generates a voltage to be output to the outside of the semiconductor device 100. The constant voltage circuit 23 can generate a voltage different from the input voltage Vin. The voltage generated by the constant voltage circuit 23 is input to the check amplifier 24.

[0035] The non-inverting input terminal (+) of the check amplifier 24 is supplied with a first check voltage Vc1 supplied from a connection point P2 having a higher potential than the potential of a connection point P1 to which a voltage-dividing terminal 42 (described later) of the high-voltage chip 4 is connected. The inverting input terminal (-) is supplied with a second check voltage Vc2 supplied from a connection point P3 having a lower potential than the potential of the connection point P1 to which the voltage-dividing terminal 42 is connected. Here, the first check voltage Vc1 is a voltage higher than the operating voltage Vs by the voltage across a resistor 41 (described later) of the high-voltage chip 4. The second check voltage Vc2 is a voltage lower than the operating voltage Vs by the voltage across the resistor 41.

[0036] The check amplifier 24 compares the first check voltage Vc1 with the second check voltage Vc2 and outputs the result as a check voltage PNVOUT. In the semiconductor device 100 shown in FIG. 3, the check voltage PNVOUT is output to the connection terminal Nd12. The check voltage PNVOUT is disturbed when noise is superimposed on at least one of the first check voltage Vc1 and the second check voltage Vc2. The motor control unit 500 can determine whether the operating voltage Vs is being stably output by measuring the disturbance in the check voltage PNVOUT.

[0037] In the semiconductor device 100 of the present disclosure, the first confirmation voltage Vc1, the check voltage PNVOUT, and the second confirmation voltage Vc2 are output to the connection terminals Nd11, Nd12, and Nd13, respectively (see FIG. 3).

[0038] The connection terminals Nd11, Nd12, and Nd13 are each connected to the ground potential GND via a resistor and a capacitor. The voltages at the junctions between the resistors and capacitors connected to the connection terminals Nd11, Nd12, and Nd13 are input to the motor control unit 500. Based on these voltages, the motor control unit 500 determines the states of the first confirmation voltage Vc1, the check voltage PNVOUT, and the second confirmation voltage Vc2, and detects the supply voltage applied to the high-voltage chip 4.

[0039] The fault signal output circuit 25 includes an OR circuit 251 and a switching element 252. The UVLO signal Sv and the TEST signal St are input to the OR circuit 251. The OR circuit 251 outputs a fault signal Sft based on the UVLO signal Sv and the TEST signal St. The switching element 252 is an n-channel MOS transistor in this example. The drain of the switching element 252 is connected to a connection terminal Nd6. The connection terminal Nd6 is connected to the input voltage Vin via a resistor.

[0040] The source of the switching element 252 is connected to the ground potential GND. A fault signal Sft is input to the gate of the switching element 252. When the fault signal Sft is at a low level, the switching element 252 is controlled to be OFF. At this time, the potential of the connection terminal Nd6 is at a high level. When the fault signal Sft is at a high level, the switching element 252 is controlled to be ON, and the potential of the connection terminal Nd6 is at a low level. The connection terminal Nd6 is connected to the motor control unit 500, and a voltage Vft based on the potential of the connection terminal Nd6 is input to the motor control unit 500.

[0041] When no abnormality is detected by the UVLO circuit 21 and the inspection circuit 22, the UVLO signal Sv and the TEST signal St are both at Lo level, and the OR circuit 251 of the fault signal output circuit 25 outputs a Lo level fault signal Sft. As a result, the switching element 252 is controlled to be OFF, and at this time, the potential of the connection terminal Nd6 is at Hi level.

[0042] On the other hand, if an abnormality is detected in at least one of the UVLO circuit 21 and the inspection circuit 22, at least one of the UVLO signal Sv and the TEST signal St is at Hi level, and the OR circuit 251 of the fault signal output circuit 25 outputs a Hi level fault signal Sft. As a result, the switching element 252 is controlled to be ON, and the potential of the connection terminal Nd6 becomes Lo level.

[0043] The motor control unit 500 determines that no abnormality has occurred in the semiconductor device 100 when the voltage Vft is at a high level, and determines that an abnormality has occurred when the voltage Vft is at a low level. Note that the motor control unit 500 may also determine that an abnormality has occurred in the low-voltage chip 2 based on the connection terminal Nd6.

[0044] The switching element 252 is not limited to an n-channel MOS transistor, but may be a p-channel MOS transistor. In this case, the potential level of the connection terminal Nd6 of the switching element 252 due to the fault signal Sft is inverted from that when an n-channel MOS transistor is used. That is, when a low-level fault signal Sft is input, the switching element 252 is turned on, and the potential of the connection terminal Nd6 becomes low. When the fault signal Sft is otherwise, the potential of the connection terminal Nd6 becomes high. Therefore, the determination of an abnormality based on the voltage Vft by the motor control unit 500 is reversed from that when an n-channel MOS transistor is used.

[0045] The above describes the configuration of the low-voltage chip 2, but in actual circuits, circuits and elements other than those described above are often wired. For example, if a switching element that switches at high speed is included, switching noise may be superimposed on the low-voltage chip 2 and the low-voltage side frame 1 to which the low-voltage chip 2 is connected. The high-voltage side frame 3 is insulated from the low-voltage side frame 1 and is therefore less susceptible to switching noise.

[0046] The high-voltage chip 4 is a resistor chip having eight resistors 41. The eight resistors 41 are connected in series. The high-voltage chip 4 is connected to the connection terminals Nd1 and Nd2. The high-voltage side frame 3 is configured so as not to be directly connected to the connection terminals Nd1 and Nd2.

[0047] The connection terminal Nd1 is connected to a first end of the series-connected resistor 41 of the high-voltage chip 4, and the connection terminal Nd2 is connected to a second end of the series-connected resistor 41. As a result, a supply voltage is applied to both ends of the high-voltage chip 4 by the connection terminals Nd1 and Nd2.

[0048] That is, a supply voltage is applied across multiple resistors 41 connected in series in the high-voltage chip 4. The high-voltage chip 4 has a voltage-dividing terminal 42 that divides the supply voltage to extract a predetermined voltage. The voltage-dividing terminal 42 is connected to a connection point between the resistors 41 that can divide the supply voltage to a desired voltage. In the high-voltage chip 4 of the present disclosure, the voltage-dividing terminal 42 is connected to a connection point P1 between the fourth and fifth resistors 41 from the connection terminal Nd1. The voltage-dividing terminal 42 divides the supply voltage using the combined resistance of the resistors 41 located closer to the connection terminal Nd1 than the voltage-dividing terminal 42 and the combined resistance of the resistors 41 located closer to the connection terminal Nd2.

[0049] The high-voltage chip 4 is connected to the high-voltage side frame 3. The high-voltage chip 4 is connected to the high-voltage side frame 3 so that the potential of one of the connection points where the resistors 41 are connected to each other is connected to the high-voltage side frame 3 and becomes the reference potential. In the high-voltage chip 4 of the semiconductor device 100 of the present disclosure, the connection point P0 connected to the connection terminal Nd2 of the resistor 41 is connected to the reference potential.

[0050] As described above, battery 200 is configured to apply a voltage to a circuit so that the positive electrode 201 has a potential difference equal to the supply voltage relative to negative electrode 202. In semiconductor device 100 of the present disclosure, positive electrode 201 is connected to a first end of high-voltage chip 4, negative electrode 202 is connected to a second end, and connection point P0, which is the second end, is set to ground potential GND, which is a reference potential. As a result, the potential of voltage-dividing terminal 42 becomes operating potential Vps, which has a potential difference equal to the voltage divided by resistor 41 of high-voltage chip 4 from ground potential GND.

[0051] The voltage dividing terminal 42 is connected to the connection terminal Nd10, and the potential of the connection terminal Nd10 is the operating potential Vps. The connection terminal Nd10 is connected to the ground potential via a resistor and a capacitor, and in the semiconductor device 100, an operating voltage Vs based on the potential at the connection point between the resistor and capacitor connected to the connection terminal Nd10 is supplied to the motor control unit 500.

[0052] In the semiconductor device 100 of the present disclosure, the voltage-dividing terminal 42 is connected to the connection terminal Nd10 via a circuit inside the low-voltage chip 2. The low-voltage chip 2 may have a circuit configured to monitor the operating potential Vps of the voltage-dividing terminal 42. This allows the low-voltage chip 2 to detect, for example, a drop in the supply voltage of the battery 200 or an over-discharge state. The low-voltage chip 2 may notify the motor control unit 500 of the detection result, or may have a circuit configured to stop the supply of power to the outside by itself. Alternatively, the voltage-dividing terminal 42 may be connected directly to the connection terminal Nd10 without going through the low-voltage chip 2.

[0053] As described above, in the semiconductor device 100, the first confirmation voltage Vc1 and the second confirmation voltage Vc2 are extracted from the high-voltage chip 4. The first confirmation voltage Vc1 is extracted based on the potential at the connection point P2 between the third resistor 41 and the fourth resistor 41 from the connection terminal Nd1 side. The second confirmation voltage Vc2 is extracted based on the potential at the connection point P3 between the fifth resistor 41 and the sixth resistor 41 from the connection terminal Nd1 side. In the semiconductor device 100 of the present disclosure, the fourth resistor 41 and the fifth resistor 41 from the connection terminal Nd1 side have the same resistance value.

[0054] In the high-voltage chip 4, the resistance value of each resistor 41 is determined so that the required voltage can be stably extracted. The resistance values ​​of the multiple resistors 41 may all be the same or may be different. The number of resistors 41 is not limited to eight.

[0055] In the high-voltage chip 4, the operating voltage Vs can be supplied by changing at least one of the connection points between the resistors 41 to which the voltage-dividing terminals 42 are connected and the connection points between the resistors 41 to which the high-voltage side frame 3 is connected. Note that the high-voltage chip 4 may be configured to have a plurality of voltage-dividing terminals 42 so that voltages of different values ​​can be supplied. The semiconductor device 100 has the general configuration described above.

[0056] In the semiconductor device 100 of the present disclosure, the high-voltage chip 4 has one end of the resistors 41 connected in series connected to ground potential, which is the reference potential, but this is not limited to this. For example, the connection point between the first and second resistors 41 from the connection terminal Nd2 side may be connected to the reference potential. In this case, the potential difference between the connection terminals Nd1 and Nd2 is the supply voltage, but the potential of the connection terminal Nd2 is lower than the reference potential by the voltage drop of the first resistor 41 from the connection terminal Nd2 side. As a result, the potential of the voltage-dividing terminal 42 is similarly lower. In this way, by changing the terminal used as the reference potential, it is possible to change the potential of the voltage-dividing terminal 42 and the operating voltage Vs extracted by the voltage-dividing terminal 42.

[0057] The semiconductor device 100 is sealed in, for example, a resin package Pg. As shown in Figure 4, in the semiconductor device 100, the high-voltage chip 4 is disposed on the upper surface of the high-voltage frame 3. Therefore, the bottom surface, which is the first surface 4d of the high-voltage chip 4, is in contact with the high-voltage frame 3, and a predetermined connection point of the high-voltage chip 4 is connected to the high-voltage frame 3.

[0058] In the semiconductor device 100, the wires 5 connecting the connection terminals Nd1 and Nd2 to the high-voltage chip 4 are connected to pads 43 exposed on the upper surface, which is the second surface 4u of the high-voltage chip 4, opposite the first surface 4d in the thickness direction. The wires 5 are held in place by the resin that constitutes the package Pg. As a result, the wires 5 are not in contact with the high-voltage frame 3. In other words, the supply voltage supplied via the connection terminals Nd1 and Nd2 is not supplied to the high-voltage frame 3, but is supplied only to the high-voltage chip 4.

[0059] In other words, the high-voltage side frame 3 is insulated from the connection terminals Nd1 and Nd2. This makes it difficult for noise to affect the reference potential of the high-voltage side frame 3, even if noise is superimposed on the positive electrode 201 and the negative electrode 202 of the battery 200. The stabilization of the potential of the voltage-divider terminal 42 allows a stable operating voltage Vs to be output.

[0060] Furthermore, the low-voltage chip 2 connected to the low-voltage side frame 1 may be equipped with multiple switching elements. When the switching elements are controlled to switch at high speed, switching noise may occur in the low-voltage side frame 1. Because the high-voltage side frame 3 is insulated from the low-voltage side frame 1, the reference potential of the high-voltage side frame 3 is not affected by the switching noise generated in the low-voltage side frame 1. Therefore, the voltage output from the high-voltage chip 4 can be prevented from being affected by the noise generated in the low-voltage chip 2.

[0061] As described above, by having the configuration of the semiconductor device 100, the motor control unit 500 can obtain the supply voltage of the battery 200 based on the stable operating voltage Vs, and therefore can obtain an accurate value of the battery 200, thereby improving the accuracy of driving the motor 400.

[0062] Note that noise other than switching noise may occur as noise superimposed on the potential of low-voltage side frame 1. Because high-voltage side frame 3 is insulated from low-voltage side frame 1, the reference potential of high-voltage side frame 3 is less susceptible to the influence of noise generated in low-voltage side frame 1 and low-voltage chip 2. In other words, the output supplied from high-voltage chip 4 is less susceptible to the influence of noise generated in low-voltage chip 2, and can be output at a stable voltage.

[0063] <Modification> Fig. 5 is a diagram showing a schematic configuration of a semiconductor device 100a according to a modification. The semiconductor device 100a shown in Fig. 5 differs from the semiconductor device 100 shown in Fig. 1 in terms of the reference potential and the connection point to which the reference potential is applied. Other than this, the semiconductor device 100a has the same configuration as the semiconductor device 100. Therefore, parts of the semiconductor device 100a that are substantially the same as those of the semiconductor device 100 are given the same reference numerals, and detailed descriptions of the same parts will be omitted.

[0064] 5, the connection terminals Nd3 and Nd4 are connected to a first reference potential Vc having a stable potential difference with respect to the ground potential GND. The connection terminals Nd3 and Nd4 are connected to the high-voltage side frame 3, similar to the semiconductor device 100. As a result, the reference potential of the high-voltage side frame 3 becomes the first reference potential Vc.

[0065] The high-voltage chip 4a is connected to the high-voltage side frame 3 at a connection point P4 between the second and third resistors 41 from the side connected to the connection terminal Nd2, and the potential at the connection point P4 of the high-voltage chip 4a becomes the first reference potential Vc, which is the reference potential. As a result, the semiconductor device 100a is configured so that the operating voltage Vs, which is the same as that of the semiconductor device 100, with the ground potential GND as its reference potential, is taken out from the voltage-dividing terminal 42.

[0066] It is preferable that the potential difference between the first reference potential Vc and the ground potential GND is smaller than the input voltage Vin. However, the first reference potential Vc is not limited to the above, and a stable potential can be widely adopted in a device to which the semiconductor device 100 is attached.

[0067] <Others> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present invention is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0068] The semiconductor device (100) described above has a low-voltage side frame (1) to which a low-voltage chip (2) driven by an input voltage (Vin) is connected and which is also connected to ground potential (GND), and a high-voltage side frame (3) to which a high-voltage chip (4) insulated from the low-voltage side frame (1) and supplied with a supply voltage higher than the input voltage (Vin) is connected, and the high-voltage side frame (4) is configured to be connected to a reference potential (first configuration).

[0069] In the semiconductor device (100) of the first configuration, the high-voltage chip (4) is a resistor chip having a configuration including a plurality of resistors (41) connected in series, and the low-voltage chip (2) is a configuration (second configuration) consisting of an amplifier chip on which electronic components are mounted.

[0070] In the semiconductor device (100) of the first or second configuration, the high-voltage chip (4) has a configuration (third configuration) in which a first surface (4d) is connected to the high-voltage side frame, and a supply voltage is supplied to a second surface (4u) on the opposite side of the thickness direction from the first surface (4d).

[0071] In the semiconductor device (100) of any one of the first to third configurations, the reference potential is the ground potential (GND) (fourth configuration).

[0072] In the semiconductor device (100a) of any of the first to third configurations, the potential difference between the reference potential (Vs) and the ground potential (GND) is equal to the input voltage (Vin) (fifth configuration).

[0073] In a semiconductor device (100, 100a) of any of the first to fifth configurations described above, the low-voltage side frame (1) and the high-voltage side frame (3) are integrally formed with connection terminals (Nd5, Nd17, Nd3, Nd4) connected to a reference potential, and the connection terminals (Nd5, Nd17) integrally formed with the low-voltage side frame (1) and the connection terminals (Nd3, Nd4) integrally formed with the high-voltage side frame (3) are insulated (sixth configuration).

[0074] In the semiconductor device (100, 100a) of any of the first to sixth configurations, the high-voltage side frame (3) is insulated from the terminals (Nd1, Nd2) that supply voltage to the high-voltage chip (4) (seventh configuration).

[0075] In the semiconductor device (100, 100a) of any of the first to seventh configurations, at least the low-voltage side frame (1), the low-voltage chip (2), the high-voltage side frame (3), and the high-voltage chip (4) are contained in a resin-sealed package (Pg) (eighth configuration).

[0076] A battery module (300) having a semiconductor device (100, 100a) of any one of the first to eighth configurations, and a configuration (ninth configuration) having a battery (200) configured to be able to supply a supply voltage to a high-voltage chip (4).

[0077] An electric power module (600) having the battery module (300) of the ninth configuration, and a configuration (tenth configuration) having a driving source (400) configured to receive power from the battery module (300).

[0078] This is an eleventh configuration (eleventh configuration) having an electric vehicle (A) having the electric power module (600) of the tenth configuration.

[0079] A Electric vehicle Ax Axle Wh Wheel 100, 100a Semiconductor device 200 Battery 201 Positive electrode 202 Negative electrode 300 Battery module 400 Motor 500 Motor control unit 600 Electric power module 1 Low-voltage side frame 2 Low-voltage chip 21 UVLO circuit 22 Inspection circuit 23 Constant voltage circuit 24 Check amplifier 25 Fault signal output circuit 251 OR circuit 252 Switching element 26 Pad 3 High-voltage side frame 4, 4a High-voltage chip 4d First surface 4u Second surface 41 Resistor 42 Voltage divider terminal 43 Pad 5 Wire Nd1 to Nd17 Connection terminal P0 to P4 Connection point Pg Package

Claims

1. a low-voltage side frame to which a low-voltage chip driven by an input voltage is connected and which is also connected to a ground potential; a high-voltage side frame configured to be connected to a high-voltage chip insulated from the low-voltage side frame and supplied with a supply voltage higher than the input voltage; The high-voltage side frame is connected to a reference potential.

2. the high-voltage chip is a resistor chip having a configuration including a plurality of resistors connected in series; 2. The semiconductor device according to claim 1, wherein the low-voltage chip is an amplifier chip on which electronic components are mounted.

3. 2. The semiconductor device according to claim 1, wherein the high-voltage chip has a first surface connected to the high-voltage frame, and a second surface opposite to the first surface in the thickness direction to receive the supply voltage.

4. 2. The semiconductor device according to claim 1, wherein the reference potential is a ground potential.

5. 2. The semiconductor device according to claim 1, wherein the potential difference between the reference potential and the ground potential is equal to an input voltage.

6. the low-voltage side frame and the high-voltage side frame are integrally formed with a connection terminal connected to the reference potential, 2. The semiconductor device according to claim 1, wherein the connection terminal formed integrally with the low-voltage side frame and the connection terminal formed integrally with the high-voltage side frame are insulated from each other.

7. 2. The semiconductor device according to claim 1, wherein the high-voltage side frame is insulated from a connection terminal that supplies the supply voltage to the high-voltage chip.

8. 2. The semiconductor device according to claim 1, wherein at least the low-voltage side frame, the low-voltage chip, the high-voltage side frame, and the high-voltage chip are contained in a resin-sealed package.

9. A semiconductor device according to any one of claims 1 to 8; a battery configured to supply the supply voltage to the high-voltage chip.

10. The battery module according to claim 9 ; and a drive source configured to receive power from the battery module.

11. An electric vehicle configured with the electric power module of claim 10.

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