Semiconductor device and method for manufacturing same

Abstract

This semiconductor device comprises: a chip having a main surface; a first-conductivity-type drift region formed in a surface layer part of the main surface; and a second-conductivity-type body region that is formed in a tapered shape on the surface layer part of the drift region such that the width in the horizontal direction decreases toward the thickness direction, and that has a peripheral edge part inclined in an oblique direction with respect to the main surface.

Description

Semiconductor device and manufacturing method thereof

[0001] This application claims priority to Patent Application No. 2023-056619 filed with the Japan Patent Office on March 30, 2023, the entire contents of which are incorporated herein by reference. The present disclosure relates to a semiconductor device and a manufacturing method thereof.

[0002] Patent Document 1 (US2013 / 0193447A1) discloses a semiconductor device having a body region.

[0003] US Patent Application Publication No. 2013 / 0193447

[0004] [Summary] The present disclosure provides a semiconductor device having a novel configuration and a method for manufacturing the same.

[0005] The present disclosure provides a semiconductor device including a chip having a main surface, a drift region of a first conductivity type formed in a surface layer portion of the main surface, and a body region of a second conductivity type formed in a tapered shape in the surface layer portion of the drift region so that its horizontal width decreases in a thickness direction, and having a peripheral portion inclined obliquely with respect to the main surface.

[0006] The present disclosure provides a semiconductor device including: a chip having a main surface; a drift region of a first conductivity type formed in a surface layer portion of the main surface; a body region of a second conductivity type formed in a surface layer portion of the drift region; and a contact region of the second conductivity type formed in the surface layer portion of the body region and having an impurity concentration higher than the impurity concentration of the body region, wherein the body region includes a high concentration region formed in a thickness range below the contact region, and a low concentration region formed in a region on the peripheral side of the high concentration region within the thickness range.

[0007] The present disclosure provides a method for manufacturing a semiconductor device, including the steps of: preparing a wafer having a drift region of a first conductivity type in a surface layer portion of a main surface; and implanting impurities of a second conductivity type into the surface layer portion of the drift region so that the horizontal implantation range decreases in the thickness direction, thereby forming a body region of the second conductivity type having a peripheral portion inclined obliquely with respect to the main surface.

[0008] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a plan view showing an example layout of a first main surface. FIG. 4 is an enlarged plan view showing a main portion of the first main surface. FIG. 5 is an enlarged plan view showing further main portions of the first main surface. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5. FIG. 7 is an enlarged cross-sectional view showing a main portion of the region shown in FIG. 6. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5. FIG. 9 is an enlarged cross-sectional view showing a main portion of the region shown in FIG. 8. FIG. 10A is an enlarged cross-sectional view showing a body structure according to a first embodiment. FIG. 10B is an enlarged cross-sectional view showing a body structure according to a second embodiment. FIG. 10C is an enlarged cross-sectional view showing a body structure according to a third embodiment. FIG. 10D is an enlarged cross-sectional view showing a body structure according to a fourth embodiment. FIG. 10E is an enlarged cross-sectional view showing a body structure according to a fifth embodiment. FIG. 10F is an enlarged cross-sectional view showing a body structure according to a sixth embodiment. FIG. 11A is a graph showing a concentration gradient in a first region of the body structure. FIG. 11B is a graph showing a concentration gradient in a second region of the body structure. FIG. 12 is a schematic diagram showing a wafer used in manufacturing a semiconductor device. FIG. 13A is a cross-sectional view showing a method for manufacturing a semiconductor device. FIG. 13B is a cross-sectional view showing a process after FIG. 13A. FIG. 13C is a cross-sectional view showing a process after FIG. 13B. FIG. 13D is a cross-sectional view showing a process after FIG. 13C. FIG. 13E is a cross-sectional view showing a process after FIG. 13D. FIG. 13F is a cross-sectional view showing a process after FIG. 13E. FIG. 13G is a cross-sectional view showing a process after FIG. 13F. FIG. 13H is a cross-sectional view showing a process after FIG. 13G. FIG. 14 is an enlarged cross-sectional view showing a body structure according to a reference example. FIG. 15A is a graph showing a concentration gradient in a first region of the body structure according to a reference example. FIG. 15B is a graph showing a concentration gradient in a second region of the body structure according to a reference example. FIG. 16 is a cross-sectional view showing a semiconductor device according to the second embodiment. 17A to 17C are cross-sectional views showing modifications of the field region, Fig. 18A to 18C are cross-sectional views showing first and second modifications of the source pad electrode, and Fig. 19A to 19C are cross-sectional views showing second modifications of the source pad electrode.

[0010] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0011] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0012] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0013] FIG. 1 is a plan view showing a semiconductor device 1A according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1. FIG. 3 is a plan view showing an example layout of a first main surface 3. FIG. 4 is an enlarged plan view showing a main portion of the first main surface 3. FIG. 5 is an enlarged plan view showing further main portions of the first main surface 3. FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 5. FIG. 7 is an enlarged cross-sectional view showing a main portion of the region shown in FIG. 6. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 5. FIG. 9 is an enlarged cross-sectional view showing a main portion of the region shown in FIG. 8.

[0014] 1 to 9, semiconductor device 1A is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a vertical structure. Semiconductor device 1A is a SiC semiconductor device having a chip 2 including a SiC single crystal. Chip 2 may be referred to as a "SiC chip" or a "semiconductor chip."

[0015] In this embodiment, the chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 is made of 4H-SiC single crystal, but the chip 2 may be made of another polytype.

[0016] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0017] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0018] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0019] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. Hereinafter, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0020] The chip 2 (first main surface 3 and second main surface 4) has an off-axis angle inclined at a predetermined angle in a predetermined off-axis direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off-axis direction by the off-axis angle. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off-axis angle.

[0021] The off-direction is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0022] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0023] In this embodiment, the chip 2 has a stacked structure including a first semiconductor layer 6 and a second semiconductor layer 7. The first semiconductor layer 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal) and has the off direction and off angle described above. The first semiconductor layer 6 forms the second main surface 4 and forms parts of the first to fourth side surfaces 5A to 5D.

[0024] The first semiconductor layer 6 may have a thickness of 10 μm or more and 500 μm or less. The thickness of the first semiconductor layer 6 may have a value belonging to at least one of the ranges of 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or more, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0025] The second semiconductor layer 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal), and is stacked on the first semiconductor layer 6. The second semiconductor layer 7 has the off direction and off angle described above. The second semiconductor layer 7 forms the first main surface 3 and forms parts of the first to fourth side surfaces 5A to 5D. The second semiconductor layer 7 preferably has a thickness less than that of the first semiconductor layer 6. Of course, the thickness of the second semiconductor layer 7 may be greater than the thickness of the first semiconductor layer 6.

[0026] The thickness of the second semiconductor layer 7 may be 5 μm or more and 50 μm or less. The thickness of the second semiconductor layer 7 may have a value belonging to at least one of the ranges of 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or more and 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or more, and 45 μm or more and 50 μm or less.

[0027] The semiconductor device 1A includes an active region 8 set on the chip 2 (first main surface 3). The active region 8 is set in an inner portion of the chip 2 (first main surface 3). The active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated.

[0028] The active region 8 is set in the interior of the chip 2 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in plan view. The active region 8 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in plan view. The plane area of ​​the active region 8 is preferably 50% to 90% of the plane area of ​​the first main surface 3.

[0029] The semiconductor device 1A includes a peripheral region 9 set outside the active region 8 in the chip 2. The peripheral region 9 is a region that does not include a device structure (transistor structure Tr). The peripheral region 9 is set in the peripheral portion of the chip 2 (first main surface 3). That is, the peripheral region 9 is provided in the region between the periphery of the chip 2 and the active region 8 in a planar view. The peripheral region 9 extends in a strip shape along the active region 8 in a planar view, and is set in the shape of a polygonal ring (a square ring in this embodiment) that surrounds the active region 8.

[0030] The semiconductor device 1A includes an n-type drain region 10 formed in the surface layer portion of the second main surface 4 in the active region 8. The drain region 10 may be referred to as a "first region," a "first semiconductor region," or the like. A drain potential as a high potential (first potential) is applied to the drain region 10. The drain region 10 may be referred to as a "first region," a "first semiconductor region," or the like. The drain region 10 has a size of 5×10 １７ cm －３ 3x10 or more １９ cm －３ The following impurity concentrations may be present:

[0031] The drain region 10 extends in a layer shape along the second main surface 4. The drain region 10 is formed over the entire area of ​​the active region 8. The drain region 10 is drawn from the active region 8 to the peripheral region 9, and has a portion in the peripheral region 9 that is located in a surface layer portion of the second main surface 4. The drain region 10 is drawn from the active region 8 to the peripheral region 9 over the entire periphery. The drain region 10 is exposed from at least one of the first to fourth side surfaces 5A to 5D. In this embodiment, the drain region 10 is exposed from the entire periphery of the first to fourth side surfaces 5A to 5D.

[0032] The drain region 10 is formed in the first semiconductor layer 6. The drain region 10 is formed throughout the thickness range between the lower end (second main surface 4) of the first semiconductor layer 6 and the upper end (second semiconductor layer 7) of the first semiconductor layer 6, and is connected to the second semiconductor layer 7. The drain region 10 is formed using the n-type first semiconductor layer 6, and has a thickness corresponding to the thickness of the first semiconductor layer 6. Of course, the drain region 10 may also be formed by introducing n-type impurities into the surface layer portion of the second main surface 4 of the chip 2.

[0033] The semiconductor device 1A includes an n-type drift region 11 formed in the surface layer portion of the first main surface 3 in the active region 8. The drift region 11 may also be referred to as a "second region," a "second semiconductor region," or the like. The drift region 11 has an impurity concentration lower than the impurity concentration of the drain region 10.

[0034] The drift region 11 extends in a layered form along the first main surface 3 and is electrically connected to the drain region 10 inside the chip 2. The drift region 11 is formed throughout the active region 8. In this embodiment, the drift region 11 extends from the active region 8 to the peripheral region 9, and has a portion in the peripheral region 9 that is located in the surface layer of the first main surface 3.

[0035] The drift region 11 extends from the active region 8 to the peripheral region 9 along the entire periphery. The drift region 11 is preferably exposed from at least one of the first to fourth side surfaces 5A to 5D. In this embodiment, the drift region 11 is exposed from the entire periphery of the first to fourth side surfaces 5A to 5D.

[0036] The drift region 11 is formed in the second semiconductor layer 7. The drift region 11 is formed throughout the thickness range between the upper end (drain region 10) of the first semiconductor layer 6 and the upper end (first main surface 3) of the second semiconductor layer 7, and is connected to the first semiconductor layer 6 (drain region 10). In this embodiment, the drift region 11 is formed using the n-type second semiconductor layer 7, and has a thickness corresponding to the thickness of the second semiconductor layer 7. Of course, the drift region 11 may also be formed by introducing n-type impurities into the surface layer portion of the first main surface 3 of the chip 2 (second semiconductor layer 7).

[0037] The semiconductor device 1A includes a plurality of body structures 12 formed in a surface layer portion of the first main surface 3 in the active region 8. The body structures 12 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the body structures 12 are arranged in stripes extending in the second direction Y. The extending direction of the body structures 12 also coincides with the off-direction of the SiC single crystal.

[0038] 10A , a specific configuration of one body structure 12 will be described. Fig. 10A is an enlarged cross-sectional view showing the body structure 12 according to the first embodiment. Referring to Fig. 10A , the body structure 12 includes a p-type body region 13 formed in a surface layer portion of the first main surface 3.

[0039] The body region 13 is formed in the surface layer of the drift region 11 as the main body portion of the body structure 12. That is, the multiple body regions 13 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. A source potential is applied to the body region 13 as a low potential (second potential) different from a high potential (first potential). The body region 13 forms a pn junction with the drift region 11 and expands a depletion layer in the drift region 11 when a reverse bias voltage is applied.

[0040] The body region 13 has an upper end on the first main surface 3 side and a lower end on the bottom side of the drift region 11. The lower end of the body region 13 is the bottom of the body region 13. The upper end of the body region 13 is exposed from the first main surface 3. The lower end of the body region 13 is formed at a distance from the bottom of the drift region 11 towards the first main surface 3 and faces the drain region 10 across a part of the drift region 11. The lower end of the body region 13 is preferably formed at a distance from the middle of the drift region 11 towards the first main surface 3. Of course, the body region 13 may cross the depth position of the middle part of the drift region 11 in the thickness direction.

[0041] The body regions 13 each have a body width WB in the horizontal direction (first direction X in this embodiment). The maximum value of the body width WB may be 1 μm or more and 10 μm or less. The maximum value of the body width WB may be a value belonging to at least one of the following ranges: 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, and 9 μm or more and 10 μm or less. The maximum value of the body width WB is preferably 2 μm or more and 5 μm or less.

[0042] The body region 13 may have a body thickness TB of 0.1 μm to 2.5 μm in the vertical direction Z. The body thickness TB is also the depth of the body region 13. The body thickness TB may have a value belonging to at least one of the following ranges: 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.25 μm, and 2.25 μm to 2.5 μm. The body thickness TB is preferably 0.5 μm to 1.5 μm. FIG. 10A illustrates an example in which the body thickness TB is 0.7 μm to 0.8 μm.

[0043] The body region 13 is formed in a tapered shape in the surface layer portion of the drift region 11 so that the body width WB decreases in the thickness direction, and has a peripheral edge portion that is inclined obliquely with respect to the first main surface 3. In other words, the peripheral edge portion of the body region 13 is inclined obliquely toward the center portion of the lower end portion of the body region 13. As long as the inclination of the peripheral edge portion is maintained, the body width WB does not necessarily have to decrease monotonically in the thickness direction, and may gradually increase or decrease.

[0044] Therefore, the term "inclined in an oblique direction" includes a configuration in which a straight line (diagonal line) connecting two points on the peripheral edge within a predetermined thickness range in a cross-sectional view is inclined with respect to the first main surface 3. For example, the predetermined thickness range may be a thickness range of at least ¼, at least ⅓, or at least ½ of the body thickness TB. Of course, the predetermined thickness range may be the body thickness TB. In this case, the term "inclined in an oblique direction" includes a configuration in which a straight line connecting the upper end of the peripheral edge and the lower end of the peripheral edge is inclined with respect to the first main surface 3 in a cross-sectional view.

[0045] The horizontal distance between two points on the periphery within a predetermined thickness range is defined as the body gradient GB. The body gradient GB within the predetermined thickness range may be 0.05 μm to 0.5 μm. The body gradient GB may have a value within at least one of the following ranges: 0.05 μm to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.3 μm, 0.3 μm to 0.4 μm, and 0.4 μm to 0.5 μm.

[0046] The inclination angle formed by a straight line (diagonal line) connecting two points on the peripheral edge with a vertical line may be 5° or more and 45° or less. The inclination angle may have a value belonging to at least one of the ranges of 5° or more and 10° or less, 10° or more and 15° or less, 15° or more and 20° or less, 20° or more and 25° or less, 25° or more and 30° or less, 30° or more and 35° or less, 35° or more and 40° or less, and 40° or more and 45° or less. The inclination angle is preferably 10° or more and 30° or less. The inclination angle is particularly preferably 15° or more and 25° or less.

[0047] In this embodiment, the body region 13 is formed such that the body width WB decreases in the thickness direction starting from the upper end. That is, the peripheral edge of the body region 13 is inclined obliquely from the upper end toward the lower end. It is preferable that the body width WB decreases at least from the upper end to the middle portion. That is, it is preferable that the peripheral edge of the body region 13 is inclined obliquely at least from the upper end to the middle portion.

[0048] It is particularly preferable that the body width WB decreases from the upper end side toward the lower end side throughout the entire thickness range between the upper end and the lower end, i.e., it is particularly preferable that the periphery of the body region 13 slopes obliquely from the upper end side toward the lower end side throughout the entire thickness range between the upper end and the lower end.

[0049] The body region 13 may have a maximum body width WB at the upper end or a region near the upper end (e.g., within a 10% thickness range from the upper end). The body region 13 may have a minimum body width WB at the lower end or a region near the lower end (e.g., within a 10% thickness range from the lower end). The peripheral edge portion is preferably connected to the lower end portion in an arc-like (circular) shape in a cross-sectional view. That is, the body region 13 preferably has an edge portion that connects the peripheral edge portion and the lower end portion in an arc-like (circular) shape.

[0050] When the upper end of the periphery of body region 13 is set as a reference position (0 μm point), the periphery of body region 13 is inclined obliquely with respect to first main surface 3 within a thickness range of 0.5 μm from first main surface 3. That is, body region 13 does not extend in a direction perpendicular to first main surface 3 within the thickness range of 0.5 μm. In other words, the portion of the periphery of body region 13 located at the 0.5 μm point is located inward of body region 13 relative to the upper end of the periphery and does not overlap with the upper end in the vertical direction Z.

[0051] The peripheral portion of the body region 13 has a body gradient GB of 0.05 μm to 0.25 μm within the 0.5 μm thickness range. The body gradient GB within the 0.5 μm thickness range is the horizontal change in the peripheral portion at a thickness of 0.5 μm relative to the top edge of the peripheral portion. Figure 10A illustrates an example of the body gradient GB within the 0.5 μm thickness range.

[0052] The body gradient GB in the 0.5 μm thickness range may have a value belonging to at least one of the ranges of 0.05 μm to 0.1 μm, 0.1 μm to 0.15 μm, 0.15 μm to 0.2 μm, and 0.2 μm to 0.25 μm. The body gradient GB is preferably 0.1 μm to 0.2 μm. The body gradient GB in the 0.5 μm thickness range is particularly preferably greater than 0.1 μm and less than 0.15 μm.

[0053] In this embodiment, the peripheral portion of the body region 13 has a sub-inclined portion 14 on the upper end side and a main inclined portion 15 on the lower end side. The sub-inclined portion 14 may be referred to as a "first inclined portion" or an "upper inclined portion," and the main inclined portion 15 may be referred to as a "second inclined portion" or a "lower inclined portion." The sub-inclined portion 14 is formed in a region closer to the first main surface 3 than the intermediate portion of the body region 13. The sub-inclined portion 14 forms a surface portion of the body region 13 and is exposed from the first main surface 3.

[0054] The sub-inclined portion 14 is an overhanging portion that protrudes horizontally from the peripheral edge of the upper end of the body region 13 along the first main surface 3. The sub-inclined portion 14 is formed by a portion of the body region 13 where the body width WB monotonically decreases, and is inclined obliquely with respect to the first main surface 3. In this embodiment, the sub-inclined portion 14 overhangs in an arc shape (circular arc shape). The sub-inclined portion 14 has a first inclination angle with respect to the first main surface 3 that is relatively gentle.

[0055] The sub-inclined portion 14 prevents a relatively narrow body width WB from being formed at the upper end of the body region 13, and prevents the upper end of the peripheral portion from being recessed inward of the body region 13. In other words, the sub-inclined portion 14 prevents the formation of a short channel portion at the upper end of the body region 13.

[0056] The sub-inclined portion 14 may have a width (protruding width) of 0.01 μm or more and 0.25 μm or less in the horizontal direction. The width of the sub-inclined portion 14 is the horizontal width based on a vertical line passing through the lower end of the sub-inclined portion 14 in the vertical direction Z. The width of the sub-inclined portion 14 decreases monotonically in the thickness direction.

[0057] The width of the sub-inclined portion 14 may have a value belonging to at least one of the ranges of 0.01 μm to 0.05 μm, 0.05 μm to 0.1 μm, 0.1 μm to 0.15 μm, 0.15 μm to 0.2 μm, and 0.2 μm to 0.25 μm. In this embodiment, the width of the sub-inclined portion 14 is 0.15 μm or less.

[0058] The sub-inclined portion 14 may have a thickness of 0.01 μm or more and 0.25 μm or less in the vertical direction Z. The thickness of the protruding portion may have a value belonging to at least one of the ranges of 0.01 μm or more and 0.05 μm or less, 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.15 μm or less, 0.15 μm or more and 0.2 μm or less, and 0.2 μm or more and 0.25 μm or less. In this embodiment, the thickness of the sub-inclined portion 14 is 0.15 μm or less.

[0059] The main inclined portion 15 is formed in a region on the lower end side of the sub-inclined portion 14. The main inclined portion 15 has a thickness greater than that of the sub-inclined portion 14 and forms a major portion of the body region 13. The main inclined portion 15 forms a body gradient GB together with the sub-inclined portion 14. For example, the main inclined portion 15 forms a body gradient GB in a thickness range of 0.5 μm together with the sub-inclined portion 14.

[0060] In this embodiment, the main inclined portion 15 is formed by a portion of the body region 13 where the body width WB decreases substantially monotonically, and is inclined obliquely with respect to the first main surface 3. The main inclined portion 15 is located inward of the body region 13 with respect to the sub-inclined portion 14, and has a second inclination angle with respect to the first main surface 3 that is steeper than the first inclination angle of the sub-inclined portion 14. For example, when a horizontal line (X-line) extending along the horizontal direction (first direction X) is used as a reference, the second inclination angle has a value greater than the first inclination angle. In other words, when a vertical line extending along the vertical direction Z is used as a reference, the second inclination angle has a value smaller than the first inclination angle.

[0061] The body structure 12 includes a plurality of n-type source regions 16, 17 formed in a surface layer portion of the body region 13. A source potential is applied to the plurality of source regions 16, 17. The plurality of source regions 16, 17 include a first source region 16 located on one side in the first direction X (the third side surface 5C side) and a second source region 17 located on the other side in the first direction X (the fourth side surface 5D side). In this embodiment, one first source region 16 is formed on one end side of the body region 13, and one second source region 17 is formed on the other end side of the body region 13.

[0062] The first source region 16 is formed at an interval from one end to the other end of the body region 13. The second source region 17 is formed at an interval from the first source region 16 to the other end of the body region 13. The second source region 17 is formed at an interval from the other end to one end of the body region 13.

[0063] The configuration of one of the source regions 16, 17 will be specifically described below. The source regions 16, 17 extend in a strip shape along the extension direction of the body region 13. The source regions 16, 17 are formed spaced apart inward from both end portions of the body region 13 in the second direction Y. In other words, the source regions 16, 17 expose both end portions of the body region 13 from the first main surface 3 (see FIG. 5 ).

[0064] The source regions 16 and 17 are formed at an interval from the lower end of the body region 13 toward the first main surface 3, and face the drift region 11 across a part of the body region 13. Specifically, the source regions 16 and 17 have a thickness that crosses the depth position of the sub-inclined portion 14 in the thickness direction.

[0065] The source regions 16, 17 are formed spaced inward from the sub-inclined portion 14 and have portions that face the sub-inclined portion 14 in the horizontal direction. The source regions 16, 17 are formed spaced inward from the main inclined portion 15 and have portions that face the main inclined portion 15 in the horizontal direction.

[0066] The intermediate portions of the source regions 16, 17 are located closer to the main inclined portion 15 than the depth position of the sub-inclined portion 14, and face the main inclined portion 15 in the horizontal direction. In the horizontal direction, the distance between the source regions 16, 17 and the main inclined portion 15 is smaller than the distance between the source regions 16, 17 and the sub-inclined portion 14.

[0067] The source regions 16 and 17 have peripheral portions that protrude in an arc shape (circular arc shape) toward the peripheral portion of the body region 13. The tip portions of the source regions 16 and 17 may face the first main surface 3 in the thickness direction via a part of the body region 13. Of course, the peripheral portions of the source regions 16 and 17 may have tip portions that are exposed from the first main surface 3 in the thickness direction without being via the body region 13. In this case, the peripheral portions of the source regions 16 and 17 may slope downward in a linear or curved manner from the first main surface 3 toward the inside of the lower end of the body region 13. Of course, the peripheral portions of the source regions 16 and 17 may extend approximately perpendicular to the first main surface 3.

[0068] When a plurality of first source regions 16 are formed in the body region 13, the plurality of first source regions 16 may be formed at intervals in the extension direction of the body region 13. In this case, each of the first source regions 16 may be formed in a strip shape extending in the second direction Y. When a plurality of second source regions 17 are formed in the body region 13, the plurality of second source regions 17 may be formed at intervals in the extension direction of the body region 13. In this case, each of the second source regions 17 may be formed in a strip shape extending in the second direction Y.

[0069] The body structure 12 includes a plurality of p-type contact regions 18 formed in a region different from the source regions 16 and 17 in a surface layer portion of the body region 13. The contact regions 18 may also be referred to as "back gate regions." A source potential is applied to the plurality of contact regions 18. In this embodiment, one contact region 18 is interposed in a region between the first source region 16 and the second source region 17 in the surface layer portion of the body region 13 and is electrically connected to the body region 13.

[0070] The contact regions 18 extend in a strip shape along the extension direction of the body region 13 (the source regions 16, 17). The contact regions 18 are formed spaced apart inward from both end portions of the body region 13 in the second direction Y. In other words, the contact regions 18 expose both end portions of the body region 13 from the first main surface 3 (see FIG. 5 ).

[0071] In this embodiment, the contact region 18 has a width smaller than that of the source regions 16 and 17. Of course, the width of the contact region 18 may be larger than that of the source regions 16 and 17. The contact region 18 is formed at a distance from the lower end of the body region 13 toward the first main surface 3, and faces the drift region 11 with a part of the body region 13 interposed therebetween. Specifically, the contact region 18 has a thickness that crosses the depth position of the sub-inclined portion 14 in the thickness direction.

[0072] The contact region 18 has a portion that faces the sub-inclined portion 14 in the horizontal direction with the source regions 16 and 17 interposed therebetween, and a portion that faces the main inclined portion 15 in the horizontal direction with the source regions 16 and 17 interposed therebetween. The middle portion of the contact region 18 is located closer to the main inclined portion 15 than the depth position of the sub-inclined portion 14, and faces the main inclined portion 15 in the horizontal direction.

[0073] In this embodiment, the contact region 18 has a thickness greater than that of the source regions 16, 17, and has a bottom located closer to the lower end of the body region 13 than the bottoms of the source regions 16, 17. In other words, the bottom of the contact region 18 faces the main inclined portion 15 in the horizontal direction without passing through the source regions 16, 17. The contact region 18 has a peripheral portion that protrudes in an arc shape (circular arc shape) toward the peripheral edge of the body region 13.

[0074] The tip of contact region 18 may face first main surface 3 in the thickness direction via parts of source regions 16, 17. Of course, the peripheral edge of contact region 18 may have a tip that is exposed from first main surface 3 in the thickness direction without being sandwiched between source regions 16, 17. In this case, the peripheral edge of contact region 18 may slope downward in a linear or curved manner from first main surface 3 toward the inside of the lower end of body region 13. Of course, the peripheral edge of contact region 18 may extend approximately perpendicular to first main surface 3.

[0075] When multiple contact regions 18 are formed in the body region 13, the multiple contact regions 18 may be formed at intervals in the extension direction of the body region 13. In this case, each contact region 18 may be formed in a strip shape extending in the second direction Y.

[0076] The body structure 12 may have the configuration shown in Figures 10B to 10F. Figure 10B is an enlarged cross-sectional view showing the body structure 12 according to a second embodiment. Figure 10C is an enlarged cross-sectional view showing the body structure 12 according to a third embodiment. Figure 10D is an enlarged cross-sectional view showing the body structure 12 according to a fourth embodiment. Figure 10E is an enlarged cross-sectional view showing the body structure 12 according to a fifth embodiment. Figure 10F is an enlarged cross-sectional view showing the body structure 12 according to a sixth embodiment.

[0077] 10B, the body structure 12 according to the second embodiment has a configuration obtained by modifying the configuration of the body region 13 according to the first embodiment. In this embodiment, the body region 13 includes a main inclined portion 15 having undulations.

[0078] Specifically, the main inclined portion 15 has multiple (at least two) bulging portions 19 that bulge out horizontally and are arranged in multiple stages in the thickness direction. The multiple bulging portions 19 are regions in which the rate of change (amount of reduction) of the body width WB changes in the thickness direction. The multiple bulging portions 19 may bulge out in an arc shape (circular arc shape). The bulging portions 19 may also be referred to as "bulging portions," "protruding portions," "curved portions," "extending portions," etc.

[0079] The body region 13 (main inclined portion 15) may include at least one or more bulging portions 19 formed by portions of the body region 13 where the body width WB decreases almost monotonically. The body region 13 (main inclined portion 15) may include at least one or more bulging portions 19 formed by portions of the body region 13 where the body width WB gradually increases or decreases.

[0080] The plurality of bulges 19 are formed so as to start from the lower end of the sub-inclined portion 14 and sequentially set back inward of the body region 13 from the upper end side to the lower end side, forming undulations with repeated protrusions and depressions along the inclination direction. In other words, with respect to the lower bulge 19 and the upper bulge 19, the tip of the lower bulge 19 is positioned more inward of the body region 13 than the tip of the upper bulge 19.

[0081] The multiple bulging portions 19 may have different thicknesses. That is, the main inclined portion 15 may include one bulging portion 19 having a relatively small thickness (depth) and another bulging portion 19 having a thickness (depth) greater than the first bulging portion 19. The other bulging portion 19 may be located closer to the upper end than the first bulging portion 19, or may be located closer to the lower end than the first bulging portion 19.

[0082] The thickness of each bulge 19 may be 0.05 μm or more and 0.5 μm or less. The thickness of each bulge 19 may have a value belonging to at least one of the ranges of 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.3 μm or less, 0.3 μm or more and 0.4 μm or less, and 0.4 μm or more and 0.5 μm or less.

[0083] As an example, in this embodiment, the multiple bulge portions 19 include a first bulge portion 19A, a second bulge portion 19B, and a third bulge portion 19C formed in this order from the upper end side to the lower end side. The first bulge portion 19A is formed directly below the sub-inclined portion 14. The first bulge portion 19A is formed by a portion of the body region 13 where the body width WB decreases almost monotonically, and has an end portion set back inward of the body region 13 with respect to the tip end of the sub-inclined portion 14.

[0084] In this embodiment, the end of the first bulge portion 19A does not face the sub-inclined portion 14 in the thickness direction. Of course, the first bulge portion 19A may be formed by a portion where the body width WB gradually increases or decreases, and may face the sub-inclined portion 14 in the thickness direction. The first bulge portion 19A has a first thickness that is greater than the thickness of the sub-inclined portion 14. Of course, the first thickness may be less than the thickness of the sub-inclined portion 14.

[0085] The second bulge portion 19B is formed directly below the first bulge portion 19A. The second bulge portion 19B is formed by a portion of the body region 13 where the body width WB decreases substantially monotonically, and has an end portion set back inward of the body region 13 relative to the end portion of the first bulge portion 19A. In this embodiment, the second bulge portion 19B does not face the first bulge portion 19A in the thickness direction.

[0086] Of course, the second bulge 19B may be formed by a portion where the body width WB gradually increases or decreases, and may be opposite the first bulge 19A in the thickness direction. The first bulge 19A has a second thickness that is less than the first thickness of the first bulge 19A. Of course, the second thickness may be greater than the first thickness.

[0087] The third bulge portion 19C is formed directly below the second bulge portion 19B. The third bulge portion 19C is formed by a portion of the body region 13 where the body width WB decreases substantially monotonically, and has an end portion set back inward of the body region 13 with respect to the end portion of the second bulge portion 19B. In this embodiment, the third bulge portion 19C does not face the second bulge portion 19B in the thickness direction.

[0088] Of course, the third bulge portion 19C may be formed by a portion where the body width WB gradually increases or decreases, and may face the second bulge portion 19B in the thickness direction. The third bulge portion 19C forms an edge portion of the body region 13 and is connected to the lower end of the body region 13 in an arc-like (circular) shape. The third bulge portion 19C has a third thickness that is greater than the second thickness of the second bulge portion 19B. Of course, the third thickness may be less than the second thickness. The third thickness may be greater than the first thickness or less than the first thickness.

[0089] The source regions 16, 17 are formed at a distance from the depth position of at least the lowest bulge 19 (i.e., the third bulge 19C) toward the first main surface 3, and are horizontally opposed to at least one bulge 19. In this embodiment, the source regions 16, 17 are formed at a distance from the depth position of the second bulge 19B toward the first main surface 3.

[0090] The source regions 16 and 17 have a portion that faces the sub-inclined portion 14 in the horizontal direction and a portion that faces the first bulge portion 19A in the horizontal direction. Of course, the source regions 16 and 17 may have a thickness that crosses the depth position of the second bulge portion 19B and have a portion that faces the second bulge portion 19B in the horizontal direction.

[0091] The contact region 18 is formed at a distance from the depth position of at least the lowest bulge 19 (i.e., the third bulge 19C) toward the first main surface 3, and faces at least one bulge 19 in the horizontal direction. In this embodiment, the contact region 18 is formed at a distance from the depth position of the second bulge 19B toward the first main surface 3.

[0092] The contact region 18 has a portion facing the sub-inclined portion 14 in the horizontal direction across the source regions 16 and 17, and a portion facing the first bulge portion 19A in the horizontal direction across the source regions 16 and 17. Of course, the contact region 18 may have a thickness that crosses the depth position of the second bulge portion 19B and may have a portion facing the second bulge portion 19B in the horizontal direction.

[0093] 10C , the body structure 12 according to the third embodiment has a plurality of bulging portions 19, similar to the body region 13 according to the second embodiment. In this embodiment, the plurality of bulging portions 19 includes a first bulging portion 19A and a second bulging portion 19B formed in this order from the upper end side to the lower end side.

[0094] The first bulge 19A is formed directly below the sub-inclined portion 14. The first bulge 19A is formed by a portion of the body region 13 where the body width WB decreases substantially monotonically, and has an end portion that is set back inward of the body region 13 with respect to the tip end of the sub-inclined portion 14. The first bulge 19A has a first thickness that is greater than the thickness of the sub-inclined portion 14. Of course, the first thickness may be less than the thickness of the sub-inclined portion 14.

[0095] The second bulge portion 19B is formed directly below the first bulge portion 19A. The second bulge portion 19B is formed by a portion of the body region 13 where the body width WB gradually increases and decreases, and has an end portion set back inward of the body region 13 relative to the end portion of the first bulge portion 19A. The second bulge portion 19B forms an edge portion of the body region 13 and is connected to the lower end portion of the body region 13 in an arc-like (circular) shape. The second bulge portion 19B has a second thickness that is greater than the thickness of the sub-inclined portion 14. The second thickness may be greater than the first thickness or less than the first thickness.

[0096] The second bulge portion 19B forms a recessed portion 20A that is recessed horizontally toward the inside of the body region 13 at the boundary (connection) with the first bulge portion 19A, and faces the first bulge portion 19A in the thickness direction across the recessed portion 20A. When a vertical line is set that passes through the end of the second bulge portion 19B in the vertical direction Z in a cross-sectional view, the recessed portion 20A has an end that is recessed inward of the body region 13 relative to the vertical line. A configuration in which the recessed portion 20A is eliminated corresponds to the body region 13 according to the second embodiment.

[0097] The source regions 16, 17 are preferably formed at least at a distance from the depth position of the recess 20A toward the first main surface 3 and facing at least one bulge 19 in the horizontal direction. In this embodiment, the source regions 16, 17 are formed at a distance from the depth position of the end of the recess 20A toward the first main surface 3. The source regions 16, 17 have a portion facing the sub-inclined portion 14 in the horizontal direction and a portion facing the first bulge 19A in the horizontal direction. The source regions 16, 17 do not have a portion facing the recess 20A (second bulge 19B) in the horizontal direction.

[0098] Preferably, contact region 18 is formed at least at a distance from the depth position of recess 20A toward first main surface 3, and faces at least one bulge 19 in the horizontal direction across source regions 16, 17. In this embodiment, contact region 18 is formed at a distance from the depth position of the end of recess 20A toward first main surface 3.

[0099] The contact region 18 has a portion facing the sub-inclined portion 14 in the horizontal direction across the source regions 16 and 17, and a portion facing the first bulge portion 19A in the horizontal direction across the source regions 16 and 17. The contact region 18 does not have a portion facing the recessed portion 20A (second bulge portion 19B) in the horizontal direction.

[0100] 10D , the body structure 12 according to the fourth embodiment has a modified first bulge portion 19A in the body region 13 according to the third embodiment. In this embodiment, the first bulge portion 19A is formed by a portion of the body region 13 where the body width WB gradually increases and decreases, and has an end portion set back inward of the body region 13 relative to the tip end of the sub-inclined portion 14. In this embodiment, the end portion of the first bulge portion 19A faces the sub-inclined portion 14 in the thickness direction. The first bulge portion 19A has a first thickness that is greater than the thickness of the sub-inclined portion 14. Of course, the first thickness may be less than the thickness of the sub-inclined portion 14.

[0101] The first bulge 19A forms a recess 20B that is recessed horizontally toward the inside of the body region 13 at the boundary (connection) with the sub-inclined portion 14, and faces the sub-inclined portion 14 across the recess 20B. When a vertical line is set that passes through the end of the first bulge 19A in the vertical direction Z in a cross-sectional view, the recess 20B has an end that is recessed inward of the body region 13 relative to the vertical line. The end of the recess 20B is positioned closer to the sub-inclined portion 14 than the end of the recess 20A in the horizontal direction. A configuration in which the recess 20A and the recess 20B are eliminated corresponds to the body region 13 according to the second embodiment.

[0102] The source regions 16, 17 have a portion facing the sub-inclined portion 14 in the horizontal direction and a portion facing the first bulge portion 19A in the horizontal direction. In this embodiment, the source regions 16, 17 face the recessed portion 20B in the horizontal direction. The contact region 18 has a portion facing the sub-inclined portion 14 with the source regions 16, 17 sandwiched between them in the horizontal direction, and a portion facing the first bulge portion 19A with the source regions 16, 17 sandwiched between them in the horizontal direction. In this embodiment, the contact region 18 faces the recessed portion 20B with the source regions 16, 17 sandwiched between them in the horizontal direction.

[0103] 10E , the body structure 12 according to the fifth embodiment has a modified sub-inclined portion 14 of the body region 13 according to the first embodiment. In this embodiment, the sub-inclined portion 14 is formed by a portion of the body region 13 where the body width WB decreases substantially monotonically, and does not protrude horizontally but is inclined obliquely at a first inclination angle from the first main surface 3. In this embodiment, the sub-inclined portion 14 also suppresses the formation of a short channel portion at the upper end of the body region 13.

[0104] On the other hand, the main inclined portion 15 has a second inclination angle that is approximately equal to the first inclination angle, and has a portion that slopes obliquely continuously from the sub inclined portion 14 along the inclination direction of the sub inclined portion 14. The sub inclined portion 14 according to the fifth embodiment is also applicable to the body structures 12 according to the first to fourth embodiments.

[0105] 10F , the body structure 12 according to the sixth embodiment includes a narrowing portion 21 that forms a short channel portion instead of the sub-inclined portion 14. Specifically, the narrowing portion 21 is formed by a portion of the body region 13 at the upper end thereof where the body width WB increases (gradually increases) in the thickness direction. The narrowing portion 21 has a portion that is obliquely inclined with respect to the first main surface 3 in the surface layer portion of the drift region 11, and faces the first main surface 3 across a part of the drift region 11.

[0106] On the other hand, the main inclined portion 15 is formed by a portion where the body width WB decreases from the tip of the narrowed portion 21, and is inclined obliquely with respect to the first main surface 3. In this embodiment, the aforementioned body gradient GB is applied to the main inclined portion 15 with the tip of the narrowed portion 21 as the reference position (0 μm point).

[0107] The source regions 16, 17 are formed in the surface layer portion of the body region 13 at a distance from the base end of the narrowed portion 21. The source regions 16, 17 form a relatively narrow short channel portion between the narrowed portion 21 and the source regions 16, 17, and form a relatively wide channel portion between the main slope portion 15 and the source regions 16, 17.

[0108] If the short channel portion is not a problem, the body structure 12 according to the sixth embodiment may be adopted. The narrowed portion 21 according to the sixth embodiment is also applicable to the body structures 12 according to the first to fifth embodiments. The following description is based on the premise that a configuration includes a sub-inclined portion 14, but the sub-inclined portion 14 can be replaced with the narrowed portion 21. A specific configuration in this case can be obtained by replacing the "sub-inclined portion 14" with the "narrowed portion 21" as necessary in the following description.

[0109] 11A is a graph showing the concentration gradient in the first region of the body structure 12. The first region of the body structure 12 is a region in the body region 13 in the second direction Y where neither the source regions 16, 17 nor the contact region 18 are formed. For example, the second region of the body structure 12 is the two end portions of the body region 13 in the second direction Y (see also FIG. 5 ). In FIG. 11A , the vertical axis represents the impurity concentration, and the horizontal axis represents the body width WB. FIG. 11A shows an example where the body width WB is 2.6 μm.

[0110] 11A shows a first concentration distribution A1 (thin line), a second concentration distribution A2 (thin dashed line), a third concentration distribution A3 (thick line), and a fourth concentration distribution A4 (thick dashed line). The first concentration distribution A1 shows the horizontal concentration distribution at a thickness of 0.15 μm in the body region 13 (see FIG. 10A). The second concentration distribution A2 shows the horizontal concentration distribution at a thickness of 0.30 μm in the body region 13 (see FIG. 10A).

[0111] The third concentration distribution A3 shows the horizontal concentration distribution at a thickness of 0.45 μm in the body region 13 (see FIG. 10A). The fourth concentration distribution A4 shows the horizontal concentration distribution at a thickness of 0.60 μm in the body region 13 (see FIG. 10A). In this example, the middle part of the body region 13 is at a thickness of 0.35 μm. The first to fourth concentration distributions A1 to A4 show the n-type impurity concentrations in the drift region 11 and the p-type impurity concentrations in the body region 13.

[0112] The n-type impurity concentration of the drift region 11 is 1×10 １６ cm －３ 5x10 or more １７ cm －３ The body region 13 has a p-type impurity concentration higher than the n-type impurity concentration of the drift region 11. The p-type impurity concentration of the body region 13 may be 1×10 １７ cm －３ 1x10 or more １９ cm －３ The body region 13 preferably contains aluminum as a trivalent element.

[0113] Referring to the first to fourth concentration distributions A1 to A4, the body region 13 has a first concentration gradient portion 22 (see the upward arrow portion) and a second concentration gradient portion 23 (see the downward arrow portion) in the thickness direction. The first concentration gradient portion 22 is a region in which the p-type impurity concentration gradually increases from the upper end toward the middle portion. The second concentration gradient portion 23 is a region in which the p-type impurity concentration gradually decreases from the first concentration gradient portion 22 toward the lower end.

[0114] That is, the p-type impurity concentration at the lower end side of the body region 13 is lower than the p-type impurity concentration at the upper end side of the body region 13. For example, in this embodiment, the p-type impurity concentration at the upper end side of the body region 13 in a thickness range of more than 0.15 μm and not more than 0.60 μm is higher than the p-type impurity concentration at the upper end side of the body region 13 in a thickness range of not more than 0.15 μm.

[0115] The body region 13 has a concentration gradient that gradually decreases from the inner side toward the peripheral edge side in the horizontal direction. Specifically, the body region 13 includes a first high concentration region 24, a low concentration region 25, and a second high concentration region 26 in the horizontal direction. The first high concentration region 24 is formed in the inner part of the body region 13. The first high concentration region 24 forms a concentration gradient that is convex and curved upward (in the positive direction), and includes a first maximum value P1 of the p-type impurity concentration.

[0116] The first high-concentration region 24 has a concentration gradient in which the p-type impurity concentration gradually increases and decreases in the thickness direction, following the first concentration gradient portion 22 and the second concentration gradient portion 23. That is, the first high-concentration region 24 has a concentration gradient in which the p-type impurity concentration gradually increases (monotonically increases) in a region above the intermediate portion and gradually decreases (monotonically decreases) in a region below the intermediate portion. The first high-concentration region 24 forms a convex concentration gradient including the first maximum value P1 in both the region above the intermediate portion and the region below the intermediate portion.

[0117] The first high-concentration region 24 preferably occupies an area of ​​1 / 10 to 1 / 2 of the body region 13 in the horizontal direction. The area occupied by the first high-concentration region 24 may be 1 / 5 or more. The area occupied by the first high-concentration region 24 is preferably 1 / 4 or more.

[0118] The low-concentration region 25 is formed in a region closer to the peripheral edge of the body region 13 than the first high-concentration region 24, and forms a concentration gradient that gradually decreases from the first high-concentration region 24. The low-concentration region 25 is a region having a p-type impurity concentration lower than the p-type impurity concentration of the first high-concentration region 24. Specifically, the p-type impurity concentration of the low-concentration region 25 is lower than a first maximum value P1. The low-concentration region 25 forms a concentration gradient that is concave and curved downward (in the negative direction) in the surface portion of the body region 13, and includes a minimum value P2 of the p-type impurity concentration (see first concentration distribution A1).

[0119] The low-concentration region 25 has a concentration gradient in which the p-type impurity concentration gradually increases and decreases in the thickness direction, following the first concentration gradient portion 22 and the second concentration gradient portion 23. That is, the low-concentration region 25 has a concentration gradient in which the p-type impurity concentration gradually increases (monotonically increases) in a region closer to the upper end than the intermediate portion and gradually decreases (monotonically decreases) in the thickness direction in a region closer to the lower end than the intermediate portion.

[0120] The low-concentration region 25 has a concave concentration gradient including a minimum value P2 in the region upper than the intermediate portion (see the first concentration distribution A1). The low-concentration region 25 forms a gradual region in the region lower than the intermediate portion that has a concentration decrease rate that is smaller than the concentration decrease rate in the region upper than the intermediate portion, and does not have a concave concentration gradient (minimum value P2).

[0121] Therefore, the concentration difference between the first high-concentration region 24 and the low-concentration region 25 gradually decreases toward the bottom end of the body region 13. That is, the concentration difference at the bottom end is less than the concentration difference at the top end. The low-concentration region 25 forms the main slope 15 and is electrically connected to the drift region 11.

[0122] The second high-concentration region 26 is formed in the peripheral portion of the body region 13 (see first concentration distribution A1). The second high-concentration region 26 is formed closer to the peripheral portion of the body region 13 than the low-concentration region 25, forming a concentration gradient that gradually increases from the low-concentration region 25. The second high-concentration region 26 has a convex concentration gradient that includes a second maximum value P3 of the p-type impurity concentration. The second maximum value P3 is greater than the minimum value P2. In this embodiment, the second maximum value P3 is greater than the first maximum value P1. Of course, the second maximum value P3 may be less than the first maximum value P1.

[0123] The second high-concentration region 26 is formed only in the peripheral portion of the body region 13 in the surface portion of the body region 13, and is not formed in the region on the lower end side of the body region 13. Specifically, the second high-concentration region 26 forms the sub-inclined portion 14. In other words, the sub-inclined portion 14 is a region that includes the second high-concentration region 26 and protrudes outward from the main inclined portion 15.

[0124] The second high-concentration region 26 has a concentration gradient that gradually decreases in the thickness direction. The concentration difference between the low-concentration region 25 and the second high-concentration region 26 gradually decreases from the sub-slope portion 14 toward the main slope portion 15 and becomes almost zero at the main slope portion 15. In other words, the second high-concentration region 26 forms almost the entire sub-slope portion 14. The second high-concentration region 26 may partially form a part (upper portion) of the main slope portion 15. The second high-concentration region 26 may form only the sub-slope portion 14 and not the main slope portion 15.

[0125] The second high-concentration region 26 is connected to the drift region 11 in a region closer to the upper end than the intermediate portion. The body region 13 does not necessarily have to have the second high-concentration region 26, and the low-concentration region 25 may be formed in the upper end of the periphery of the body region 13. In other words, the sub-inclined portion 14 may be formed by the low-concentration region 25.

[0126] 11B is a graph showing the concentration gradient in the second region of the body structure 12. The second region of the body structure 12 is a region in the body region 13 in the second direction Y where both the source regions 16, 17 and the contact region 18 are formed. For example, the second region of the body structure 12 is a middle portion of the body region 13 in the second direction Y. In FIG. 11B, the vertical axis represents the impurity concentration, and the horizontal axis represents the body width WB.

[0127] 11B shows a first concentration distribution B1 (thin line), a second concentration distribution B2 (thin dashed line), a third concentration distribution B3 (thick line), and a fourth concentration distribution B4 (thick dashed line). The first concentration distribution B1 has a concentration distribution in which the n-type impurity concentration of the source regions 16 and 17 and the p-type impurity concentration of the contact region 18 are added to the first concentration distribution A1.

[0128] The second concentration distribution B2 has a concentration distribution in which the n-type impurity concentration on the bottom side of the source regions 16 and 17 and the p-type impurity concentration on the bottom side of the contact region 18 are added to the second concentration distribution A2. The third and fourth concentration distributions B3 and B4 correspond to the third and fourth concentration distributions A3 and A4, respectively.

[0129] The source regions 16, 17 have an n-type impurity concentration higher than the n-type impurity concentration of the drift region 11. The n-type impurity concentration of the source regions 16, 17 is higher than the p-type impurity concentration of the body region 13. The n-type impurity concentration of the source regions 16, 17 is higher than the p-type impurity concentration of the low-concentration region 25 (minimum value P2). The n-type impurity concentration of the source regions 16, 17 is higher than the p-type impurity concentration of the first high-concentration region 24 (first maximum value P1). The n-type impurity concentration of the source regions 16, 17 is higher than the p-type impurity concentration of the second high-concentration region 26 (second maximum value P3).

[0130] The n-type impurity concentration of the source regions 16 and 17 is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ The source regions 16 and 17 may have a thickness of 0.1 μm or more and 0.45 μm or less. The source regions 16 and 17 preferably contain phosphorus as a pentavalent element. The source regions 16 and 17 may have a thickness of 0.1 μm or more and 0.45 μm or less. The thickness of the source regions 16 and 17 is preferably 0.35 μm or less.

[0131] The contact region 18 has a p-type impurity concentration higher than the p-type impurity concentration of the body region 13. The p-type impurity concentration of the contact region 18 is higher than the p-type impurity concentration of the low-concentration region 25 (minimum value P2). The p-type impurity concentration of the contact region 18 is higher than the p-type impurity concentration of the first high-concentration region 24 (first maximum value P1). The p-type impurity concentration of the contact region 18 is higher than the p-type impurity concentration of the second high-concentration region 26 (second maximum value P3).

[0132] In this embodiment, the p-type impurity concentration of the contact region 18 is higher than the n-type impurity concentration of the source regions 16 and 17. Of course, the p-type impurity concentration of the contact region 18 may be lower than the n-type impurity concentration of the source regions 16 and 17. The p-type impurity concentration of the contact region 18 is 1×10 １９ cm －３ 1x10 or more ２１ cm －３The contact region 18 may have a thickness of 0.1 μm or more and 0.45 μm or less. The contact region 18 preferably contains aluminum as a trivalent element. The contact region 18 may have a thickness of 0.1 μm or more and 0.45 μm or less. The thickness of the contact region 18 is preferably 0.4 μm or less.

[0133] With reference to the first and second concentration distributions B1 and B2, the source regions 16 and 17 are formed in the low concentration region 25 of the body region 13. Specifically, the source regions 16 and 17 are formed in the low concentration region 25 of the body region 13, shifted inward with respect to the first high concentration region 24 and the second high concentration region 26 of the body region 13.

[0134] This prevents the n-type impurity concentrations of the source regions 16, 17 from being canceled out by the p-type impurity concentrations of the first high concentration region 24 and the second high concentration region 26. Both ends of the source regions 16, 17 may partially overlap the first high concentration region 24 and the second high concentration region 26.

[0135] Of course, both ends of the source regions 16, 17 may be formed with a space inward from the first high concentration region 24 and the second high concentration region 26. In the second concentration distribution B2, the p-type impurity concentration of the low concentration region 25 is lower than in the case of the second concentration distribution A2 because the p-type impurity concentration of the low concentration region 25 is offset by the n-type impurity concentration on the bottom side of the source regions 16, 17.

[0136] On the other hand, the contact region 18 is formed in the first high concentration region 24 of the body region 13. Specifically, the contact region 18 is formed in the first high concentration region 24 of the body region 13, shifted inward with respect to the low concentration region 25 and the second high concentration region 26 of the body region 13. As a result, the p-type impurity concentration of the contact region 18 is increased by the first high concentration region 24.

[0137] That is, the first high-concentration region 24 improves the ohmic contact of the contact region 18 with the body region 13. In the second concentration distribution B2, the p-type impurity concentration of the first high-concentration region 24 is increased compared to the second concentration distribution A2 because the p-type impurity concentration on the bottom side of the contact region 18 is added to the p-type impurity concentration of the first high-concentration region 24.

[0138] With reference to the third to fourth concentration distributions B3 to B4, the body region 13 has a first high concentration region 24 in a thickness range below the contact region 18. The first high concentration region 24 has a concentration gradient that gradually decreases in the thickness direction in the thickness range below the contact region 18. Specifically, the first high concentration region 24 has a concentration gradient that monotonically decreases from the bottom of the contact region 18 toward the lower end of the body region 13. The concentration of the first high concentration region 24 on the lower end side of the body region 13 is lower than the concentration of the first high concentration region 24 on the bottom side of the contact region 18.

[0139] The body region 13 has a low concentration region 25 in a region closer to the periphery of the body region 13 than the first high concentration region 24 in a thickness range below the contact region 18. Specifically, the body region 13 has the low concentration region 25 in a thickness range below the source regions 16 and 17.

[0140] The low-concentration region 25 has a concentration gradient in which the impurity concentration gradually decreases in the thickness direction in the thickness range below the source regions 16 and 17. Specifically, the low-concentration region 25 has a concentration gradient that monotonically decreases from the bottom of the source regions 16 and 17 (excluding the offset portion) toward the lower end of the body region 13. The concentration of the low-concentration region 25 on the lower end side of the body region 13 is lower than the concentration of the low-concentration region 25 on the bottom side of the source regions 16 and 17.

[0141] In the thickness range below the contact region 18, the concentration decrease rate of the low concentration region 25 is smaller than the concentration decrease rate of the high concentration region. Therefore, the concentration difference between the high concentration region and the low concentration region 25 gradually decreases toward the bottom end of the body region 13. In other words, in the thickness range below the contact region 18, the concentration difference on the bottom end side of the body region 13 is less than the concentration difference on the bottom side of the contact region 18.

[0142] 6 , 7 , and 10A again, semiconductor device 1A includes a plurality of n-type surface drift regions 27 formed in a surface portion of first main surface 3. In this embodiment, each of the plurality of surface drift regions 27 is made up of a portion of drift region 11. Of course, the plurality of surface drift regions 27 may have an n-type impurity concentration higher than the n-type impurity concentration of drift region 11, or may have an n-type impurity concentration lower than the n-type impurity concentration of drift region 11.

[0143] The multiple surface drift regions 27 are partitioned into regions between multiple body regions 13 adjacent in the first direction X in the surface portion of the drift region 11. That is, the multiple surface drift regions 27 are arranged at intervals in the first direction X and are each formed in a band shape extending in the second direction Y. The multiple surface drift regions 27 are also formed in a stripe shape extending in the second direction Y. The configuration of one surface drift region 27 will be described below.

[0144] The surface drift region 27 has a drift width WD of 0.1 μm or more and 5 μm or less in the horizontal direction (first direction X in this embodiment). The drift width WD is preferably less than the body width. Of course, the drift width WD may be larger than the body width WB. The drift width WD is preferably 0.2 μm or more and 2 μm or less.

[0145] The drift width WD may have a value belonging to at least one of the ranges of 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0146] The surface drift region 27 is partitioned into regions between the body regions 13 so that the drift width WD increases in the thickness direction in accordance with the cross-sectional shape of the body regions 13. When the body regions 13 have multiple bulge portions 19, the surface drift region 27 has portions partitioned by the multiple bulge portions 19 (see FIGS. 10B to 10D).

[0147] The surface drift region 27 is formed such that the drift width WD increases in the thickness direction starting from the upper end of the body region 13. In other words, the drift width WD increases from the upper end side toward the lower end side throughout the entire thickness range between the upper and lower ends of the body region 13.

[0148] The surface drift region 27 forms an n-type (pnp-type) JFET structure together with the body regions 13 located on both sides. The surface drift region 27 forms a current path that spreads in the thickness direction in the region between the body regions 13, thereby reducing the current confinement effect. In other words, the JFET resistance component of the JFET structure is reduced due to the cross-sectional shape of the peripheral portions of the body regions 13 (i.e., the cross-sectional shape of the surface drift region 27). Furthermore, the surface drift region 27 reduces the current density in the region between the body regions 13 and alleviates electric field concentration in the peripheral portions of the body regions 13.

[0149] The semiconductor device 1A includes a plurality of p-type channel regions 28, 29 formed in a surface layer portion of the first main surface 3. In this embodiment, the plurality of channel regions 28, 29 are arranged at intervals in the first direction X and are each formed in a band shape extending in the second direction Y. The plurality of channel regions 28, 29 are also arranged in a stripe shape extending in the second direction Y.

[0150] The plurality of channel regions 28, 29 are formed in a surface layer portion of the body region 13 due to the plurality of source regions 16, 17. Specifically, the plurality of channel regions 28, 29 include a first channel region 28 on one side in the first direction X and a second channel region 29 on the other side in the first direction X. The first channel region 28 is formed in a surface layer portion of the body region 13 due to the first source region 16. The second channel region 29 is formed in a surface layer portion of the body region 13 due to the second source region 17.

[0151] The channel regions 28, 29 are formed in the surface portion of the body region 13 in a region between the peripheral portion of the body region 13 (the plurality of surface drift regions 27) and the source regions 16, 17. That is, the channel regions 28, 29 have a portion formed along the sub-inclined portion 14 and a portion formed along the upper end of the main inclined portion 15.

[0152] The semiconductor device 1A includes a plurality of planar electrode type gate structures 30 arranged on the first main surface 3 in the active region 8. The plurality of gate structures 30 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of gate structures 30 are arranged in stripes extending in the second direction Y. The extending direction of the plurality of gate structures 30 also coincides with the off-direction of the SiC single crystal.

[0153] Each gate structure 30 covers the periphery of at least one body region 13. Specifically, each gate structure 30 covers at least one sub-tilt portion 14. Each gate structure 30 covers the periphery of at least one body region 13, at least one source region 16, 17, and one surface drift region 27 so as to be positioned above at least one channel region 28, 29.

[0154] In this embodiment, each gate structure 30 is arranged across one surface drift region 27 and straddling the peripheral portions (sub-inclined portions 14) of two adjacent body regions 13, and covers a plurality of channel regions 28, 29. Specifically, each gate structure 30 is arranged across the first source region 16 on one body region 13 side and the second source region 17 on the other body region 13 side, and covers the first source region 16, the second source region 17, the surface drift region 27, the first channel region 28, and the second channel region 29.

[0155] Each gate structure 30 partially covers the first source region 16 while being spaced apart from the contact region 18, and exposes a part of the first source region 16 and the contact region 18 from the first main surface 3. Each gate structure 30 partially covers the second source region 17 while being spaced apart from the contact region 18, and exposes a part of the second source region 17 and the contact region 18 from the first main surface 3.

[0156] The configuration of one gate structure 30 will be described below. The gate structure 30 has a stacked structure including an insulating film 31 and a gate electrode 32. The insulating film 31 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 31 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 31 include a silicon oxide film made of an oxide of the chip 2.

[0157] The insulating film 31 covers the first main surface 3 in a film-like manner. The insulating film 31 covers the peripheral edge of at least one body region 13. Specifically, the insulating film 31 covers at least one sub-inclined portion 14. The insulating film 31 faces the entire sub-inclined portion 14 and the entire main inclined portion 15 in the stacking direction (vertical direction Z).

[0158] The insulating film 31 covers the peripheral portion of at least one body region 13, at least one source region 16, 17, and one surface drift region 27 so as to be positioned above at least one channel region 28, 29. In this embodiment, the insulating film 31 is arranged across one surface drift region 27 to straddle the peripheral portions (sub-inclined portions 14) of two adjacent body regions 13, and covers the multiple channel regions 28, 29.

[0159] Specifically, the insulating film 31 is arranged to straddle the first source region 16 on one body region 13 side and the second source region 17 on the other body region 13 side, and covers the first source region 16, the second source region 17, the surface drift region 27, the first channel region 28, and the second channel region 29.

[0160] The insulating film 31 partially covers the first source region 16 at a distance from the contact region 18, and exposes a part of the first source region 16 and the contact region 18 from the first main surface 3. The insulating film 31 partially covers the second source region 17 at a distance from the contact region 18, and exposes a part of the second source region 17 and the contact region 18 from the first main surface 3.

[0161] The insulating film 31 may have a thickness of 10 nm or more and 150 nm or less. The thickness of the insulating film 31 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less. The thickness of the insulating film 31 is preferably 25 nm or more and 75 nm or less.

[0162] The gate electrode 32 is disposed on the insulating film 31. A gate potential is applied to the gate electrode 32 as a control potential. The gate electrode 32 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The conductivity type of the gate electrode 32 is adjusted according to the gate threshold voltage to be achieved.

[0163] The gate electrode 32 is formed in a strip shape extending in the second direction Y. In this embodiment, the gate electrode 32 is formed spaced inward from both ends of the insulating film 31 in the first direction X, exposing both ends of the insulating film 31. The gate electrode 32 covers the peripheral edge of at least one body region 13 with the insulating film 31 in between. Specifically, the gate electrode 32 covers at least one sub-inclined portion 14 with the insulating film 31 in between. The gate electrode 32 faces the entire sub-inclined portion 14 and the entire main inclined portion 15 in the stacking direction (vertical direction Z) with the insulating film 31 in between.

[0164] The gate electrode 32 is disposed on the insulating film 31 so as to face at least one of the channel regions 28, 29. Specifically, the gate electrode 32 covers the peripheral portion of at least one of the body regions 13, at least one of the source regions 16, 17, and one of the surface drift regions 27, with the insulating film 31 sandwiched therebetween. In this embodiment, the gate electrode 32 is disposed so as to cross one of the surface drift regions 27 and straddle the peripheral portions (sub-inclined portions 14) of two adjacent body regions 13, and faces the plurality of channel regions 28, 29 with the insulating film 31 sandwiched therebetween.

[0165] Specifically, the gate electrode 32 is arranged to straddle the first source region 16 on one body region 13 side and the second source region 17 on the other body region 13 side, and covers the first source region 16, the second source region 17, the surface drift region 27, the first channel region 28, and the second channel region 29 with the insulating film 31 sandwiched therebetween.

[0166] The gate electrode 32 responds to a gate potential to control the inversion and non-inversion of the channel regions 28, 29. When a gate potential is applied to the gate electrode 32, the channel regions 28, 29 are turned on, and a drain current flows between the drift region 11 and the source regions 16, 17 via the channel regions 28, 29 (body region 13). In this way, a planar gate type transistor structure Tr including the drift region 11 is formed in the inner part (active region 8) of the chip 2.

[0167] 4 to 9, semiconductor device 1A includes a p-type outer body region 35 formed in a surface layer portion of first main surface 3 in peripheral region 9. Outer body region 35 is formed in a surface layer portion of drift region 11. Outer body region 35 has a p-type impurity concentration higher than the n-type impurity concentration of drift region 11. The p-type impurity concentration of outer body region 35 is 1×10 １７ cm －３ 1x10 or more １９ cm －３ It may be the following:

[0168] The outer body region 35 is preferably formed simultaneously with the body region 13 and has a p-type impurity concentration approximately equal to the p-type impurity concentration of the body region 13. In this case, the outer body region 35 preferably has a concentration gradient similar to the concentration gradient of the body region 13. Of course, the p-type impurity concentration of the outer body region 35 may be lower than the p-type impurity concentration of the body region 13 or higher than the p-type impurity concentration of the body region 13.

[0169] The outer body region 35 is formed in a surface layer portion of the drift region 11 at a distance from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) toward the active region 8, and extends in a strip shape along the active region 8. The outer body region 35 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view, and partitions the body regions 13 (active regions 8) from multiple directions.

[0170] In this embodiment, the outer body region 35 collectively surrounds the multiple body regions 13 (active regions 8) in a plan view and is partitioned into a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3. In other words, the outer body region 35 forms the boundary between the active regions 8 and the peripheral region 9. The outer body region 35 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4 ).

[0171] The outer body region 35 is exposed from the first main surface 3. The outer body region 35 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3, and faces the drain region 10 across a part of the drift region 11. The outer body region 35 is preferably formed at a distance from the middle of the drift region 11 toward the first main surface 3. Of course, the outer body region 35 may cross the depth position of the middle of the drift region 11 in the thickness direction.

[0172] The outer body region 35 has an inner edge portion on the active region 8 side and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer body region 35 is connected to the body regions 13 in a portion extending in the first direction X, and defines the body regions 13 and the surface drift regions 27 in the surface portion of the drift region 11.

[0173] That is, the outer body region 35 is electrically connected to the plurality of body regions 13. As a result, a source potential is applied to the outer body region 35 via the plurality of body regions 13. The outer body region 35 forms a pn junction with the drift region 11, and expands a depletion layer into the drift region 11 when a reverse bias voltage is applied.

[0174] The outer body region 35 is connected to the plurality of body regions 13 at intervals from the source regions 16, 17 in the second direction Y. Therefore, the outer body region 35 does not have the source regions 16, 17 in its surface portion. Furthermore, the outer body region 35 is connected to the plurality of body regions 13 at intervals from the contact region 18 in the second direction Y. Therefore, the outer body region 35 does not have the contact region 18 in its surface portion.

[0175] The outer body region 35 preferably has a width greater than that of the body region 13. The width of the outer body region 35 is the width in a direction perpendicular to the extension direction. Of course, the width of the outer body region 35 may be approximately equal to the width of the body region 13 or may be less than the thickness of the body region 13.

[0176] The ratio of the width of the outer body region 35 to the width of the body region 13 may be 1 or greater and 50 or less. The width ratio may have a value belonging to at least one of the ranges of 1 or greater and 10 or less, 10 or greater and 20 or less, 20 or greater and 30 or less, 30 or greater and 40 or less, and 40 or greater and 50 or less. The width ratio is preferably 10 or greater. The width ratio is preferably 20 or greater and 40 or less.

[0177] The outer body region 35 preferably has a thickness (depth) approximately equal to the thickness (depth) of the body region 13. Of course, the thickness of the outer body region 35 may be less than the thickness of the body region 13 or may be greater than the thickness of the body region 13.

[0178] The semiconductor device 1A includes a p-type termination region 40 formed on the first main surface 3 in the peripheral region 9. The termination region 40 may also be referred to as a "well region" or "termination well region." The termination region 40 is formed in the surface layer of the drift region 11 in the peripheral region 9. The p-type impurity concentration of the termination region 40 is 1×10 １７ cm －３ 1x10 or more ２０ cm －３ It may be the following:

[0179] Termination region 40 may have a p-type impurity concentration different from the p-type impurity concentration of body region 13. The p-type impurity concentration of termination region 40 may be higher than the p-type impurity concentration of body region 13, or may be lower than the p-type impurity concentration of body region 13. Of course, the p-type impurity concentration of termination region 40 may be approximately equal to the p-type impurity concentration of body region 13.

[0180] The termination region 40 may have a p-type impurity concentration different from the p-type impurity concentration of the outer body region 35. The p-type impurity concentration of the termination region 40 may be higher than the p-type impurity concentration of the outer body region 35, or may be lower than the p-type impurity concentration of the outer body region 35. Of course, the p-type impurity concentration of the termination region 40 may be approximately equal to the p-type impurity concentration of the outer body region 35.

[0181] Termination region 40 is spaced inward from the periphery of first main surface 3 and is formed in a region between the periphery of first main surface 3 and outer body region 35. Termination region 40 extends in a band shape along outer body region 35 in a plan view. Termination region 40 has a portion extending in a band shape in first direction X and a portion extending in a band shape in second direction Y in a plan view, and defines active region 8 from multiple directions.

[0182] In this embodiment, termination region 40 surrounds outer body region 35 (active region 8 and multiple body regions 13) in plan view and is defined as a polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of first main surface 3. Termination region 40 may have an edge portion that connects the portion extending in first direction X and the portion extending in second direction Y in plan view in an arc shape (preferably a quadrant arc shape) (see FIG. 4 ).

[0183] The termination region 40 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3, and faces the drain region 10 across a portion of the drift region 11. The termination region 40 is preferably formed at a distance from the middle of the drift region 11 toward the first main surface 3. Of course, the termination region 40 may cross the depth position of the middle of the drift region 11 in the thickness direction. The termination region 40 may have a thickness (depth) approximately equal to the thickness (depth) of the outer body region 35. The thickness of the termination region 40 may be greater than or less than the thickness of the outer body region 35.

[0184] The termination region 40 has an inner edge on the active region 8 side and an outer edge on the peripheral side of the first main surface 3. The inner edge of the termination region 40 is connected to the outer edge of the outer body region 35 in the surface layer portion of the drift region 11. This electrically connects the termination region 40 to the outer body region 35. The termination region 40 is also electrically connected to the plurality of body regions 13 via the outer body region 35. The termination region 40 forms a pn junction with the drift region 11, and expands a depletion layer in the drift region 11 when a reverse bias voltage is applied.

[0185] In this embodiment, the inner edge of the termination region 40 is connected around the entire periphery to the outer edge of the outer body region 35. When the termination region 40 has a p-type impurity concentration substantially equal to the p-type impurity concentration of the outer body region 35, the termination region 40 may be considered to be part (a lead-out portion) of the outer body region 35.

[0186] The termination region 40 (inner edge portion) has an overlap region 41 that overlaps the outer edge portion of the outer body region 35 in the surface layer portion of the drift region 11. The overlap region 41 is a high-concentration region that includes the outer edge portion of the outer body region 35 and the inner edge portion of the termination region 40. In other words, the overlap region 41 includes both the p-type impurities of the outer body region 35 and the p-type impurities of the termination region 40, and has a p-type impurity concentration that is higher than both the p-type impurity concentration of the outer body region 35 and the p-type impurity concentration of the termination region 40.

[0187] The p-type impurity concentration of the overlap region 41 is higher than the p-type impurity concentration of the body region 13. The p-type impurity concentration of the overlap region 41 may be lower than the p-type impurity concentration of the contact region 18. Of course, the p-type impurity concentration of the overlap region 41 may be higher than the p-type impurity concentration of the contact region 18.

[0188] The overlap region 41 extends in a band shape along the outer body region 35 in a plan view. The overlap region 41 has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y in a plan view, and defines the active region 8 from multiple directions. In this embodiment, the overlap region 41 is defined in the shape of a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3.

[0189] The overlap region 41 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in a plan view (see FIG. 4 ). The width of the overlap region 41 is preferably greater than the width of the body region 13. Of course, the width of the overlap region 41 may be less than the width of the body region 13.

[0190] The semiconductor device 1A may have a relatively high-concentration p-type well region (46) instead of the overlap region 41. In this case, the well region (46) has a p-type impurity concentration higher than both the p-type impurity concentration of the outer body region 35 and the p-type impurity concentration of the termination region 40.

[0191] The p-type impurity concentration of the well region (46) is higher than the p-type impurity concentration of the body region 13. The p-type impurity concentration of the well region (46) may be approximately equal to the p-type impurity concentration of the contact region 18. Of course, the p-type impurity concentration of the well region (46) may be lower than the p-type impurity concentration of the contact region 18 or higher than the p-type impurity concentration of the contact region 18.

[0192] The well region (46) may be formed in either or both of the surface layer portion of the outer body region 35 and the surface layer portion of the termination region 40. Such a configuration is effective when the termination region 40 has a p-type impurity concentration substantially equal to the p-type impurity concentration of the outer body region 35 and is formed as part of the outer body region 35 (the drawn portion).

[0193] The semiconductor device 1A includes at least one p-type field region 42 formed in the outer peripheral region 9 in a surface layer portion of the first main surface 3. The plurality of field regions 42 may be formed in an electrically floating state. The plurality of field regions 42 may be fixed to the source potential.

[0194] The number of field regions 42 is arbitrary. The number of field regions 42 may be 1 or more and 20 or less. The number of field regions 42 may have a value belonging to at least one of the ranges of 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 15 or less, and 15 or more and 20 or less. The number of field regions 42 is typically 1 or more and 8 or less. In this embodiment, the semiconductor device 1A includes three field regions 42.

[0195] The plurality of field regions 42 are formed in a surface layer portion of the drift region 11. The plurality of field regions 42 are formed in a region between the periphery of the first main surface 3 and the plurality of body regions 13 (active regions 8) at intervals inward from the periphery of the first main surface 3. Specifically, the plurality of field regions 42 are formed in a region between the periphery of the first main surface 3 and the outer body region 35. More specifically, the plurality of field regions 42 are arranged in a region between the periphery of the first main surface 3 and the termination region 40 at intervals from the outer edge of the termination region 40 toward the periphery of the first main surface 3.

[0196] The field regions 42 are formed in a band-like shape extending along the body regions 13 (termination regions 40) in a plan view. Each of the field regions 42 has a portion extending in a band-like shape in the first direction X and a portion extending in a band-like shape in the second direction Y. In this embodiment, the field regions 42 are formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) surrounding the body regions 13 (termination regions 40) in a plan view. The field regions 42 may have edge portions that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) (see FIG. 4 ).

[0197] The multiple field regions 42 are formed at intervals from the depth position of the bottom of the drift region 11 toward the first main surface 3. The multiple field regions 42 are preferably formed at intervals from the depth position of the middle part of the drift region 11 toward the first main surface 3. Of course, the multiple field regions 42 may cross the depth position of the middle part of the drift region 11 in the thickness direction. The multiple field regions 42 each form a pn junction with the drift region 11, and expand the depletion layer toward the drift region 11 when a reverse bias voltage is applied.

[0198] The width, depth, spacing, p-type impurity concentration, etc. of the multiple field regions 42 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The width of the multiple field regions 42 may be approximately constant or may be non-uniform. The width of the multiple field regions 42 may gradually increase toward the periphery of the first main surface 3. The width of the multiple field regions 42 may gradually decrease toward the periphery of the first main surface 3.

[0199] The depth of the multiple field regions 42 may be approximately constant or may be non-uniform. The depth of the multiple field regions 42 may gradually increase toward the peripheral edge of the first main surface 3. The depth of the multiple field regions 42 may gradually decrease toward the peripheral edge of the first main surface 3. Of course, the multiple field regions 42 may have a relatively shallow portion and a deep portion that is deeper than the shallow portion. The shallow portion may be formed on the inward side, and the deep portion may be formed on the peripheral edge side. The shallow portion may be formed on the peripheral edge side, and the deep portion may be formed on the inward side.

[0200] The spacing between the multiple field regions 42 may be substantially uniform or may be non-uniform. The spacing between the multiple field regions 42 may gradually increase toward the periphery of the first main surface 3. The spacing between the multiple field regions 42 may gradually decrease toward the periphery of the first main surface 3.

[0201] The p-type impurity concentrations of the plurality of field regions 42 may be approximately constant or may be non-uniform. The p-type impurity concentrations of the plurality of field regions 42 may gradually increase toward the periphery of the first main surface 3. The p-type impurity concentrations of the plurality of field regions 42 may gradually decrease toward the periphery of the first main surface 3.

[0202] The multiple field regions 42 may be formed simultaneously with the body region 13 and may have a p-type impurity concentration substantially equal to the p-type impurity concentration of the body region 13. In this case, the multiple field regions 42 may have a concentration gradient similar to the concentration gradient of the body region 13. The p-type impurity concentration of the multiple field regions 42 may be higher than the p-type impurity concentration of the body region 13 (outer body region 35) or lower than the p-type impurity concentration of the body region 13 (outer body region 35).

[0203] The p-type impurity concentrations of the plurality of field regions 42 may be approximately equal to the p-type impurity concentration of the termination region 40. The p-type impurity concentrations of the plurality of field regions 42 may be higher than the p-type impurity concentration of the termination region 40, or may be lower than the p-type impurity concentration of the termination region 40. The p-type impurity concentrations of the plurality of field regions 42 may be 1×10 １７ cm －３ 1x10 or more ２０ cm －３ It may be the following:

[0204] The semiconductor device 1A includes a peripheral insulating film 43 that covers the first main surface 3 in the peripheral region 9. The peripheral insulating film 43 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the peripheral insulating film 43 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the peripheral insulating film 43 includes a silicon oxide film made of an oxide of the chip 2. The peripheral insulating film 43 is preferably made of the same type of insulating material as the insulating material of the insulating film 31. The peripheral insulating film 43 preferably has a thickness approximately equal to that of the insulating film 31.

[0205] The peripheral insulating film 43 covers the first main surface 3 in the peripheral region 9. The peripheral insulating film 43 collectively covers the drift region 11, the outer body region 35, the termination region 40, and the plurality of field regions 42. The peripheral insulating film 43 is connected to the plurality of insulating films 31 on the active region 8 side. Specifically, the peripheral insulating film 43 is formed integrally with the plurality of insulating films 31, and together with the plurality of insulating films 31, forms a single insulating film.

[0206] The semiconductor device 1A includes a gate wiring 44 arranged on the first main surface 3 in the peripheral region 9. The gate wiring 44 is selectively routed on the first main surface 3 and has a portion that extends in a different direction from the multiple gate electrodes 32. The gate wiring 44 is connected to the multiple gate electrodes 32 and applies gate signals to the multiple gate electrodes 32. The gate wiring 44 may also be referred to as a "second gate electrode" or the like.

[0207] The gate wiring 44 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The gate wiring 44 preferably has the same conductivity type as the gate electrode 32.

[0208] Gate wiring 44 is arranged on peripheral insulating film 43 in peripheral region 9 at a distance from the periphery of first main surface 3 toward active region 8. In this embodiment, gate wiring 44 is arranged at a distance from termination region 40 toward active region 8, and is arranged on a portion of peripheral insulating film 43 that covers outer body region 35. In other words, gate wiring 44 faces outer body region 35 across peripheral insulating film 43. Gate wiring 44 may be arranged at a position facing termination region 40 in the stacking direction.

[0209] The gate wiring 44 extends in a strip shape along the plurality of body regions 13 (active regions 8) in a plan view. The gate wiring 44 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view, and defines the plurality of body regions 13 (active regions 8) from multiple directions. In this embodiment, the gate wiring 44 surrounds the plurality of body regions 13 (active regions 8) in a plan view and defines the plurality of body regions 13 (active regions 8) in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3. The gate wiring 44 may be either terminated or endless.

[0210] In this embodiment, the gate wiring 44 extends in a strip shape (annular shape in this embodiment) along the outer body region 35 in a plan view, and faces the outer body region 35 across the entire stacking direction, with the peripheral insulating film 43 sandwiched therebetween. The gate wiring 44 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view (see FIG. 4 ).

[0211] The gate wiring 44 is formed to be narrower than the outer body region 35 in a plan view, and is disposed above the outer body region 35 at a distance from the inner and outer edges of the outer body region 35. That is, in this embodiment, the multiple gate electrodes 32 are extended up to above the outer body region 35, and the gate wiring 44 is connected to the multiple gate electrodes 32 above the outer body region 35.

[0212] The thickness of the gate wiring 44 is preferably approximately equal to the thickness of the gate electrode 32. The width of the gate wiring 44 is preferably greater than the width of the gate electrode 32. The width of the gate wiring 44 is the width in a direction perpendicular to the extending direction. For example, the ratio of the width of the gate wiring 44 to the width of the gate electrode 32 may be 1 or more and 50 or less.

[0213] The width ratio may have a value belonging to at least one of the ranges of 1 to 10, 10 to 20, 20 to 30, 30 to 40, and 40 to 50. The width ratio may be 5 or greater. The width ratio may be 20 to 40. Of course, the width of the gate interconnect 44 may be equal to or less than the width of the gate electrode 32. The width of the gate interconnect 44 may be greater than the width of the outer body region 35.

[0214] The semiconductor device 1A includes an insulating interlayer film 50 covering the first main surface 3. The interlayer film 50 may also be referred to as an "interlayer insulating film," "intermediate insulating film," or the like. The interlayer film 50 has an insulating surface 51 extending along the first main surface 3. The interlayer film 50 collectively covers the active region 8 and the peripheral region 9 on the first main surface 3.

[0215] The interlayer film 50 covers the plurality of gate structures 30 in the active region 8. The interlayer film 50 collectively covers the drift region 11, the outer body region 35, the termination region 40, and the plurality of field regions 42 in the peripheral region 9, with a peripheral insulating film 43 sandwiched therebetween. The interlayer film 50 covers the gate wiring 44 in the peripheral region 9. The interlayer film 50 is continuous with the first to fourth side surfaces 5A to 5D. The interlayer film 50 may be formed spaced inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral portion of the first main surface 3 (drift region 11).

[0216] In this embodiment, the interlayer film 50 has a layered structure including a first oxide film 52 (first insulating film) and a second oxide film 53 (second insulating film), which are layered in this order from the first main surface 3 side. That is, the interlayer film 50 has an insulating surface 51 formed by the second oxide film 53. The first oxide film 52 has a single-layer structure made of a silicon oxide film with no added impurities. The first oxide film 52 may also be referred to as an NSG film (nondoped silicate glass film). In this embodiment, the first oxide film 52 has a thickness less than that of the gate electrode 32. Of course, the thickness of the first oxide film 52 may be greater than that of the gate electrode 32.

[0217] The first oxide film 52 collectively covers the active region 8 and the peripheral region 9. The first oxide film 52 collectively covers the plurality of gate structures 30 in the active region 8. The first oxide film 52 covers both the insulating film 31 and the gate electrode 32 of each gate structure 30 in a film-like manner.

[0218] The first oxide film 52 has a portion that covers the insulating film 31 (first main surface 3) in a film-like manner along the horizontal direction. The first oxide film 52 covers the insulating film 31 at a distance from the height position of the electrode surface (upper end) of the gate electrode 32 toward the insulating film 31. The first oxide film 52 has a portion that extends in a film-like manner in the stacking direction along the sidewall of the gate electrode 32.

[0219] The first oxide film 52 has a portion that covers the electrode surface of the gate electrode 32 in a film-like manner along the horizontal direction. The first oxide film 52 preferably has arc corners that are curved in an arc shape in the portion that covers the corners of the gate electrode 32. The arc corners may have a center of curvature on the gate electrode 32 side.

[0220] In the peripheral region 9, the first oxide film 52 collectively covers the drift region 11, the outer body region 35, the termination region 40, and the plurality of field regions 42 with the peripheral insulating film 43 sandwiched therebetween. The first oxide film 52 also covers the gate wiring 44 in the peripheral region 9.

[0221] The first oxide film 52 has a portion that covers the peripheral insulating film 43 (first main surface 3) in a film-like manner along the horizontal direction. The first oxide film 52 covers the peripheral insulating film 43 at a distance from the height position of the wiring surface (upper end) of the gate wiring 44 toward the peripheral insulating film 43. The first oxide film 52 has a portion that extends in a film-like manner in the stacking direction along the sidewall of the gate wiring 44.

[0222] The first oxide film 52 has a portion that horizontally covers the wiring surface of the gate wiring 44 in a film-like manner. The first oxide film 52 preferably has an arc corner portion that is curved in an arc shape in the portion that covers the corner portion of the gate wiring 44. The arc corner portion may have a center of curvature on the gate wiring 44 side.

[0223] The second oxide film 53 may have a single-layer structure made of a silicon oxide film containing phosphorus, or a multilayer structure including a silicon oxide film containing phosphorus. The silicon oxide film containing phosphorus may contain boron. The silicon oxide film containing phosphorus may be called a PSG film (Phosphorus Silicon Glass Film). The silicon oxide film containing both phosphorus and boron may be called a BPSG film (Boron Phosphorus Silicon Glass Film).

[0224] The second oxide film 53 may have a single layer structure made of a PSG film or a BPSG film stacked on the first oxide film 52. The second oxide film 53 may have a layered structure including a PSG film stacked on the first oxide film 52 and a BPSG film stacked on the PSG film. The second oxide film 53 may have a layered structure including a BPSG film stacked on the first oxide film 52 and a PSG film stacked on the BPSG film.

[0225] In this embodiment, the second oxide film 53 has a single-layer structure made of, for example, a PSG film. The thickness of the second oxide film 53 may be greater than the thickness of the first oxide film 52. The thickness of the second oxide film 53 may be less than the thickness of the first oxide film 52. The thickness of the second oxide film 53 may be greater than the thickness of the gate electrode 32. The thickness of the second oxide film 53 may be less than the thickness of the gate electrode 32.

[0226] The second oxide film 53 covers the first oxide film 52 in a film-like manner, and collectively covers the active region 8 and the peripheral region 9 with the first oxide film 52 sandwiched therebetween. The second oxide film 53 collectively covers the plurality of gate structures 30 in the active region 8 with the first oxide film 52 sandwiched therebetween. Specifically, the second oxide film 53 covers both the insulating film 31 and the gate electrode 32 in a film-like manner with the first oxide film 52 sandwiched therebetween.

[0227] The second oxide film 53 has a portion that covers the insulating film 31 with the first oxide film 52 sandwiched therebetween. The second oxide film 53 extends in the stacking direction along the sidewall of the gate electrode 32 in a film-like shape, and has a portion that covers the sidewall of the gate electrode 32 with the first oxide film 52 sandwiched therebetween. The second oxide film 53 extends in the horizontal direction along the electrode surface of the gate electrode 32 in a film-like shape, and has a portion that covers the electrode surface of the gate electrode 32 with the first oxide film 52 sandwiched therebetween. The second oxide film 53 preferably has an arc corner portion that is curved in an arc shape in a portion that covers the corner of the gate electrode 32. The arc corner portion may have a center of curvature on the gate electrode 32 side.

[0228] In the peripheral region 9, the second oxide film 53 collectively covers the drift region 11, the outer body region 35, the termination region 40, and the plurality of field regions 42, sandwiching the peripheral insulating film 43 and the first oxide film 52. In the peripheral region 9, the second oxide film 53 covers the gate wiring 44, sandwiching the first oxide film 52.

[0229] The second oxide film 53 has a portion that covers the peripheral insulating film 43 with the first oxide film 52 sandwiched therebetween. The second oxide film 53 extends in the stacking direction along the sidewall of the gate wiring 44 in the form of a film, and has a portion that covers the sidewall of the gate wiring 44 with the first oxide film 52 sandwiched therebetween. The second oxide film 53 extends in the horizontal direction along the wiring surface of the gate wiring 44 in the form of a film, and has a portion that covers the wiring surface of the gate wiring 44 with the first oxide film 52 sandwiched therebetween. The second oxide film 53 preferably has an arc corner portion that is curved in an arc shape in the portion that covers the corner of the gate wiring 44. The arc corner portion may have a center of curvature on the gate wiring 44 side.

[0230] The semiconductor device 1A includes a plurality of source openings 54 formed in the interlayer film 50 in the active region 8. The plurality of source openings 54 are formed in regions on the sides of the plurality of gate electrodes 32 at intervals from the plurality of gate electrodes 32, respectively, and expose the first main surface 3 (chip 2). Specifically, the plurality of source openings 54 penetrate the insulating film 31 and the interlayer film 50 in regions between the plurality of gate electrodes 32.

[0231] The plurality of source openings 54 penetrate both the first oxide film 52 and the second oxide film 53, and have wall surfaces defined by both the first oxide film 52 and the second oxide film 53. The plurality of source openings 54 each have an opening end defined by a circular arc corner portion of the interlayer film 50. The plurality of source openings 54 expose the corresponding plurality of source regions 16, 17 and contact regions 18, respectively.

[0232] In this embodiment, the source openings 54 are formed at intervals in the first direction X and in the shape of bands extending in the second direction Y. That is, the source openings 54 are formed in the shape of stripes extending in the second direction Y. The source openings 54 are formed at intervals from the gate wiring 44 in the second direction Y. That is, the source openings 54 are formed in a region surrounded by the gate electrodes 32 and the gate wiring 44.

[0233] A plurality of source openings 54 may be formed in a region between two gate structures 30 adjacent to each other in the first direction X. In this case, the plurality of source openings 54 may be formed in a line at intervals in the second direction Y. Furthermore, in this case, each source opening 54 may be formed in a quadrilateral shape (square shape) in a plan view, a rectangular shape extending in the first direction X, a rectangular shape extending in the second direction Y, a hexagonal shape, a circular shape, or the like.

[0234] The source opening 54 may have a width W of 0.1 μm or more and 3 μm or less. The width W of the source opening 54 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, 2.25 μm or more and 2.5 μm or less, 2.5 μm or more and 2.75 μm or less, and 2.75 μm or more and 3 μm or less. The width W of the source opening 54 is preferably 0.2 μm or more and 1 μm or less.

[0235] The source opening 54 may have a depth D of 0.1 μm or more and 2 μm or less. The depth D of the source opening 54 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or more, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The depth D of the source opening 54 is preferably 0.5 μm or more and 1 μm or less.

[0236] The source opening 54 preferably has an aspect ratio D / W of 0.5 to 3. The aspect ratio D / W is defined by the ratio of the depth D of the source opening 54 to the width W of the source opening 54. The aspect ratio D / W may have a value belonging to at least one of the ranges of 0.5 to 0.75, 0.75 to 1, 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3.

[0237] The aspect ratio D / W is preferably greater than 1. That is, the source openings 54 preferably have a depth D greater than their width W and are each formed in a vertically elongated shape in cross section. With this configuration, the gate structures 30 are arranged at a narrow pitch. The aspect ratio D / W of the vertically elongated source openings 54 is preferably greater than 1 and equal to or less than 2.

[0238] The semiconductor device 1A includes a plurality of source recesses 55 formed in the first main surface 3 in portions exposed from the plurality of source openings 54. The semiconductor device 1A does not necessarily have to have the source recesses 55. Therefore, a configuration not including the source recesses 55 may be employed.

[0239] The plurality of source recesses 55 each have a planar shape that matches the planar shape of the corresponding source opening 54, and are recessed from the first main surface 3 toward the second main surface 4. The plurality of source recesses 55 are formed at intervals from the lower end of the corresponding body region 13 toward the first main surface 3, and expose the corresponding plurality of source regions 16, 17 and contact regions 18, respectively.

[0240] Specifically, the source recesses 55 are formed at intervals from the bottoms of the corresponding source regions 16, 17 (contact regions 18) toward the first main surface 3. The source recesses 55 face at least the sub-inclined portion 14 in the horizontal direction. Of course, the source recesses 55 may face both the sub-inclined portion 14 and the main inclined portion 15 in the horizontal direction.

[0241] The semiconductor device 1A includes at least one (in this embodiment, multiple) outer openings 56 formed in the interlayer film 50 in the peripheral region 9. The multiple outer openings 56 are formed in a portion of the interlayer film 50 that covers the termination region 40. The multiple outer openings 56 penetrate the interlayer film 50 to expose the termination region 40. In this embodiment, the multiple outer openings 56 are formed in a portion of the interlayer film 50 that covers the overlap region 41 of the termination region 40 to expose the overlap region 41.

[0242] The outer openings 56 may expose the outer body region 35 instead of or in addition to the termination region 40 (overlap region 41). The outer openings 56 penetrate both the first oxide film 52 and the second oxide film 53 and have wall surfaces defined by both the first oxide film 52 and the second oxide film 53. The outer openings 56 each have an opening end defined by a circular arc corner portion of the interlayer film 50.

[0243] The outer openings 56 are spaced apart along the termination region 40 (overlap region 41) (see FIGS. 4 and 5). The outer openings 56 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view. The outer openings 56 may be formed in a strip shape extending along the termination region 40 (overlap region 41) in a plan view. The outer openings 56 may have an aspect ratio D / W (= 0.5 to 3, preferably greater than 1), similar to the source openings 54.

[0244] The semiconductor device 1A may have a single outer opening 56. The single outer opening 56 may be formed in a strip shape extending along the termination region 40 (overlap region 41). The single outer opening 56 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.

[0245] The single outer opening 56 may be formed in the shape of an ended or endless polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The single outer opening 56 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) following the termination region 40 (overlapping region 41) in a plan view (see FIG. 4 ).

[0246] The semiconductor device 1A includes a plurality of outer recesses 57 formed in the portions of the first main surface 3 that are exposed from the plurality of outer openings 56. The semiconductor device 1A does not necessarily have to have the outer recesses 57. Therefore, a configuration that does not have the outer recesses 57 may be adopted.

[0247] The outer recesses 57 each have a planar shape that matches the planar shape of the corresponding outer opening 56, and are recessed from the first main surface 3 toward the second main surface 4. The outer recesses 57 are formed at intervals from the bottom of the termination region 40 (overlap region 41) toward the first main surface 3, and each exposes the termination region 40 (overlap region 41). The outer recesses 57 may have a depth approximately equal to the depth of the source recess 55. When a single outer opening 56 is formed, a single outer recess 57 that matches the planar shape of the single outer opening 56 is formed.

[0248] The semiconductor device 1A includes at least one gate opening 58 (in this embodiment, multiple gate openings 58) formed in the interlayer film 50 in the peripheral region 9. The multiple gate openings 58 are formed in a portion of the interlayer film 50 that covers the gate wiring 44. The multiple gate openings 58 penetrate the interlayer film 50 to expose the gate wiring 44. The multiple gate openings 58 penetrate both the first oxide film 52 and the second oxide film 53, and have wall surfaces defined by both the first oxide film 52 and the second oxide film 53. Each of the multiple gate openings 58 has an opening end defined by a circular arc corner portion of the interlayer film 50.

[0249] The multiple gate openings 58 are formed at intervals along the gate wiring 44 (see FIGS. 4 and 5). The multiple gate openings 58 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view. The multiple gate openings 58 may be formed in a strip shape extending along the gate wiring 44 in a plan view. Like the source openings 54, the gate openings 58 may have an aspect ratio D / W (= 0.5 to 3, preferably greater than 1).

[0250] The semiconductor device 1A may have a single gate opening 58. The single gate opening 58 may be formed in a strip shape extending along the gate wiring 44. The single gate opening 58 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.

[0251] The single gate opening 58 may be formed in the shape of an ended or endless polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The single gate opening 58 may have an edge portion that connects a portion extending in the first direction X and a portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in plan view, following the gate wiring 44 (see FIG. 4 ).

[0252] 1 and other figures, the semiconductor device 1A includes a source pad electrode 60 disposed on an interlayer film 50. The source pad electrode 60 is a terminal electrode to which a source potential is applied from the outside. The source pad electrode 60 may also be referred to as a "first pad electrode," a "first main surface electrode," a "first terminal electrode," or the like.

[0253] The source pad electrode 60 is disposed on a portion of the interlayer film 50 that covers the active region 8. The source pad electrode 60 covers the plurality of gate electrodes 32 with the interlayer film 50 in between, and is electrically separated from the plurality of gate electrodes 32 by the interlayer film 50. The source pad electrode 60 is electrically connected to the plurality of body regions 13, the plurality of source regions 16 and 17, the contact region 18, etc. via the plurality of source openings 54.

[0254] In this embodiment, the source pad electrode 60 has a first pad portion 60a, a second pad portion 60b, and a third pad portion 60c. The first pad portion 60a has a relatively large planar area and forms the main body of the source pad electrode 60. In this embodiment, the first pad portion 60a is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the active region 8. The first pad portion 60a covers the multiple gate electrodes 32 with the interlayer film 50 sandwiched therebetween, and is electrically connected to the multiple body regions 13 and the like via the multiple source openings 54.

[0255] The second pad portion 60b has a planar area smaller than that of the first pad portion 60a, and extends in a strip shape (rectangular shape) from one end of the first pad portion 60a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The second pad portion 60b covers the plurality of gate electrodes 32 with the interlayer film 50 sandwiched therebetween, and is electrically connected to the plurality of body regions 13 and the like via the plurality of source openings 54.

[0256] The third pad portion 60c has a planar area smaller than that of the first pad portion 60a, and is drawn out in a strip shape (rectangular shape) from the other end of the first pad portion 60a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 60b in the second direction Y. The third pad portion 60c covers the plurality of gate electrodes 32 with the interlayer film 50 interposed therebetween, and is electrically connected to the plurality of body regions 13 etc. via the plurality of source openings 54.

[0257] The planar area of ​​the third pad portion 60c may be approximately equal to the planar area of ​​the second pad portion 60b. Of course, the planar area of ​​the third pad portion 60c may be larger than the planar area of ​​the second pad portion 60b, or may be smaller than the planar area of ​​the second pad portion 60b. Either or both of the second pad portion 60b and the third pad portion 60c may be used as a terminal portion for monitoring a current.

[0258] The source pad electrode 60 does not necessarily have to have both the second pad portion 60b and the third pad portion 60c at the same time. The source pad electrode 60 may have only one of the second pad portion 60b and the third pad portion 60c. Of course, the source pad electrode 60 may be composed of only the first pad portion 60a, and may not have the second pad portion 60b or the third pad portion 60c.

[0259] 6 and 7 , the source pad electrode 60 includes a first underlying electrode film 61, a plurality of first buried electrodes 62, and a first main electrode film 63. The first underlying electrode film 61 may be referred to as a "source underlying electrode film," the first buried electrodes 62 may be referred to as "source buried electrodes," and the first main electrode film 63 may be referred to as a "source main electrode film."

[0260] The first underlying electrode film 61 forms a lower layer of the source pad electrode 60 (first pad portion 60a, second pad portion 60b, and third pad portion 60c), and covers the interlayer film 50 in the active region 8. The first underlying electrode film 61 collectively covers the region of the interlayer film 50 where the multiple source openings 54 are formed, and extends from above the insulating surface 51 into the multiple source openings 54.

[0261] The first base electrode film 61 has a portion that covers the insulating surface 51 in a film-like manner and a portion that covers the wall surfaces of the plurality of source openings 54 in a film-like manner. The first base electrode film 61 may have a portion that covers the gate wiring 44 with the interlayer film 50 sandwiched therebetween. The first base electrode film 61 may be formed at a distance inward from the gate wiring 44 in a plan view.

[0262] In this embodiment, the first underlying electrode film 61 has a layered structure including a first electrode film 64 layered on the interlayer film 50 and a second electrode film 65 layered on the first electrode film 64. In this embodiment, the first electrode film 64 includes a Ti film, and the second electrode film 65 includes a TiN film. The first underlying electrode film 61 does not necessarily have to have a layered structure, and may have a single-layer structure consisting of either the first electrode film 64 (Ti film) or the second electrode film 65 (TiN film).

[0263] The thickness of the first electrode film 64 may be 10 nm or more and 100 nm or less. The thickness of the first electrode film 64 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0264] The thickness of the second electrode film 65 may be 50 nm or more and 200 nm or less. The thickness of the second electrode film 65 may have a value belonging to at least one of the ranges of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the second electrode film 65 is preferably greater than the thickness of the first electrode film 64.

[0265] The first electrode film 64 collectively covers the region of the interlayer film 50 where the multiple source openings 54 are formed, and extends into the multiple source openings 54 from above the insulating surface 51. The first electrode film 64 has a portion that covers the insulating surface 51 in a film-like manner and a portion that covers the wall surfaces of the multiple source openings 54 in a film-like manner. The first electrode film 64 directly covers the insulating surface 51 (second oxide film 53), and faces the multiple gate electrodes 32 with the interlayer film 50 in between.

[0266] The first electrode film 64 covers the arc corner portion of the interlayer film 50 (second oxide film 53) in a film-like manner, following the arc corner portion, and extends into the source opening 54. The first electrode film 64 has a portion that extends in an arc shape at the arc corner portion. This improves the film formability of the first electrode film 64 on the interlayer film 50 (wall surface of the source opening 54).

[0267] The first electrode film 64 extends along the wall surface of the source opening 54 and covers the insulating film 31, the first oxide film 52, and the second oxide film 53. The first electrode film 64 faces the side wall of the gate electrode 32 with the interlayer film 50 interposed therebetween. The first electrode film 64 covers the first main surface 3 in a film-like manner at the bottom of each source opening 54 and is electrically connected to the first main surface 3. Specifically, the first electrode film 64 has a portion that covers the source recess 55 in a film-like manner at the bottom of each source opening 54 and is electrically connected to the body region 13, the plurality of source regions 16 and 17, and the contact region 18.

[0268] The first electrode film 64 may cover the source recess 55 in a film-like manner at a distance from the height position of the first main surface 3 toward the bottom of the source recess 55. The first electrode film 64 may have a portion located on the bottom side of the source recess 55 relative to the height position of the first main surface 3, and a portion located on the insulating film 31 side relative to the height position of the first main surface 3.

[0269] The second electrode film 65 collectively covers the region of the interlayer film 50 on the first electrode film 64 where the plurality of source openings 54 are formed. The second electrode film 65 has a portion that covers the insulating surface 51 with the first electrode film 64 in between, and a portion that covers the wall surfaces of the plurality of source openings 54 with the first electrode film 64 in between.

[0270] The second electrode film 65, in a portion covering the insulating surface 51, faces the multiple gate electrodes 32 with the first electrode film 64 and the interlayer film 50 sandwiched therebetween. The second electrode film 65, following the first electrode film 64, covers the arc corner portion of the interlayer film 50 (second oxide film 53) in a film-like manner and extends into the source opening 54. The second electrode film 65 has a portion that extends in an arc shape at the arc corner portion of the interlayer film 50. This improves the film formability of the second electrode film 65 on the interlayer film 50 (wall surface of the source opening 54).

[0271] The second electrode film 65 extends along the wall surface of the source opening 54 and covers the insulating film 31, the first oxide film 52, and the second oxide film 53 with the first electrode film 64 sandwiched between them. The second electrode film 65 faces the side wall of the gate electrode 32 with the first electrode film 64 and the interlayer film 50 sandwiched between them. The second electrode film 65 has a portion that covers the source recess 55 in a film-like manner at the bottom of each source opening 54 with the first electrode film 64 sandwiched between them, and is electrically connected to the body region 13, the plurality of source regions 16, 17, and the contact region 18 via the first electrode film 64.

[0272] When the first electrode film 64 is located on the bottom side of the source recess 55 relative to the first main surface 3, the second electrode film 65 may have a portion located within the source recess 55. When the first electrode film 64 has a portion located above the first main surface 3, the entire second electrode film 65 is located above the source recess 55.

[0273] The multiple first buried electrodes 62 form an intermediate layer of the source pad electrode 60 (first pad portion 60a, second pad portion 60b, and third pad portion 60c) and are buried in the multiple source openings 54, respectively. The first buried electrodes 62 contain a conductive material different from the conductive material of the first underlying electrode film 61. The first buried electrodes 62 contain at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy. In this embodiment, the first buried electrodes 62 contain tungsten.

[0274] In this embodiment, the multiple first buried electrodes 62 are buried in a one-to-one correspondence with the multiple source openings 54 via a single first base electrode film 61. The multiple first buried electrodes 62 are electrically connected to the first main surface 3 (chip 2) within the multiple source openings 54. Specifically, the first buried electrodes 62 are electrically connected to the multiple source regions 16, 17 and contact regions 18 via the first base electrode film 61. The configuration of one first buried electrode 62 will be described below.

[0275] The first buried electrode 62 has a first buried electrode surface 66 exposed from the source opening 54, exposing the insulating surface 51. The first buried electrode surface 66 may be referred to as a "source buried electrode film." The first buried electrode 62 is buried in the source opening 54 at a distance from the insulating surface 51 toward the first main surface 3, exposing a portion of the first base electrode film 61 (second electrode film 65) that covers the insulating surface 51.

[0276] The first buried electrode 62 covers the first oxide film 52 and the second oxide film 53 with the first base electrode film 61 sandwiched therebetween. The first buried electrode 62 faces the sidewall of the gate electrode 32 in the horizontal direction. When the first base electrode film 61 is located on the bottom side of the source recess 55 with respect to the first main surface 3, the first buried electrode 62 may have a portion located within the source recess 55. When the first base electrode film 61 has a portion located above the first main surface 3, the entire first buried electrode 62 is located above the source recess 55.

[0277] The first buried electrode surface 66 is located closer to the first main surface 3 than the insulating surface 51, and does not have a portion that faces the electrode surface of the gate electrode 32 with the interlayer film 50 sandwiched therebetween in the stacking direction (vertical direction Z). In this embodiment, the first buried electrode surface 66 has a portion that covers the arc corner portion of the interlayer film 50 with the first base electrode film 61 sandwiched therebetween.

[0278] Of course, the first buried electrode surface 66 may be located below the arc corner of the interlayer film 50. The first buried electrode surface 66 is located closer to the insulating surface 51 than the height position of the first oxide film 52. The first buried electrode surface 66 is preferably located above the electrode surface of the gate electrode 32.

[0279] The first buried electrode surface 66 has a recess in its center that recesses toward the first main surface 3 (chip 2). The bottom of the recess is preferably located closer to the insulating surface 51 than the height of the electrode surface of the gate electrode 32. Of course, a part (e.g., recess) or the entire first buried electrode surface 66 may be located lower than the electrode surface of the gate electrode 32. A part (e.g., recess) or the entire first buried electrode surface 66 may be located closer to the insulating surface 51 than the height of the first oxide film 52.

[0280] The first main electrode film 63 forms an upper layer of the source pad electrode 60 (the first pad portion 60 a, the second pad portion 60 b, and the third pad portion 60 c), and covers the first base electrode film 61 and the plurality of first buried electrodes 62 in a film form. The first main electrode film 63 contains a conductive material different from the conductive material of the first base electrode film 61 and the conductive material of the first buried electrodes 62.

[0281] The first main electrode film 63 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The first main electrode film 63 has a thickness greater than the thickness (total thickness) of the first underlying electrode film 61. The first main electrode film 63 has a thickness greater than the thickness of the first buried electrode 62.

[0282] The thickness of the first main electrode film 63 may be 0.5 μm or more and 5 μm or less. The thickness of the first main electrode film 63 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0283] The first main electrode film 63 is mechanically and electrically connected to the first underlying electrode film 61 in a portion covering the insulating surface 51, and faces the plurality of gate electrodes 32 across the first underlying electrode film 61 and the interlayer film 50. The first main electrode film 63 is mechanically and electrically connected to the plurality of first buried electrodes 62 in a portion covering the plurality of source openings 54. As a result, the first main electrode film 63 is electrically connected to the plurality of body regions 13, the plurality of source regions 16, 17, contact region 18, etc. via both the first underlying electrode film 61 and the plurality of first buried electrodes 62.

[0284] The first main electrode film 63 is connected to the first buried electrode surface 66 at a height position on the first main surface 3 side relative to the height position of the insulating surface 51. The first main electrode film 63 has a portion covering a recess in the first buried electrode surface 66. The first main electrode film 63 may have a portion covering a circular corner portion of the interlayer film 50 with the first base electrode film 61 sandwiched therebetween.

[0285] The first main electrode film 63 is connected to the first buried electrode surface 66 above the height position of the first oxide film 52. In this embodiment, the first main electrode film 63 is connected to the first buried electrode surface 66 above the electrode surface of the gate electrode 32. In other words, the first main electrode film 63 does not have a portion that faces the gate electrode 32 in the horizontal direction. When the first buried electrode surface 66 is located below the height position of the electrode surface of the gate electrode 32 and the height position of the first oxide film 52, the first main electrode film 63 may have a portion that faces the gate electrode 32 in the horizontal direction.

[0286] The film formation properties of the first main electrode film 63 for the multiple source openings 54 are improved by the multiple first buried electrodes 62. This ensures an appropriate current path between the first main surface 3 and the first main electrode film 63. Such a configuration is effective in suppressing film formation defects caused by the multiple source openings 54 and reducing wiring resistance.

[0287] The semiconductor device 1A includes a plurality of first silicide portions 67 formed on the surface portions of the first main surface 3 that are exposed from the plurality of source openings 54. The plurality of first silicide portions 67 are formed in film form along the wall surfaces (side walls and bottom walls) of the plurality of source recesses 55, and are mechanically and electrically connected to the first underlying electrode film 61. In other words, the plurality of first silicide portions 67 are formed in the surface layer portions of the plurality of body regions 13, and electrically connect the plurality of first buried electrodes 62 to the plurality of body regions 13 via the first underlying electrode film 61.

[0288] The first silicide portion 67 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide. The first silicide portion 67 is preferably made of Ti silicide, Ni silicide, or Co silicide.

[0289] Semiconductor device 1A includes source finger electrodes 68 extending from source pad electrode 60 onto peripheral region 9. Source finger electrodes 68 transmit a source potential applied to source pad electrode 60 to peripheral region 9. In this embodiment, source finger electrodes 68 are routed from a portion of source pad electrode 60 (first pad portion 60 a) on the fourth side surface 5D side onto a portion of interlayer film 50 covering peripheral region 9.

[0290] Source finger electrodes 68 are extended onto termination region 40 and electrically connected to termination region 40 through a plurality of outer openings 56. Specifically, source finger electrodes 68 are electrically connected to overlap region 41 of termination region 40 through a plurality of outer openings 56.

[0291] The source finger electrodes 68 extend in a strip shape along the termination region 40 (overlap region 41). In plan view, the source finger electrodes 68 have a strip-like portion extending in the first direction X and a strip-like portion extending in the second direction Y. In this embodiment, the source finger electrodes 68 are formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surround the source pad electrode 60. The source finger electrodes 68 may have edge portions that connect the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in plan view (see FIG. 4 ).

[0292] Like the source pad electrode 60, the source finger electrode 68 includes a first underlying electrode film 61, a plurality of first buried electrodes 62, and a first main electrode film 63. The first underlying electrode film 61 forms a lower layer portion of the source finger electrode 68 and covers the interlayer film 50 in the peripheral region 9. The first underlying electrode film 61 collectively covers the region of the interlayer film 50 in which the plurality of outer openings 56 are formed, and extends into the plurality of outer openings 56 from above the insulating surface 51. The first underlying electrode film 61 has a portion that covers the insulating surface 51 in a film-like manner and a portion that covers the wall surfaces of the plurality of outer openings 56 in a film-like manner.

[0293] Similar to the source pad electrode 60, the first base electrode film 61 has a laminated structure including a first electrode film 64 and a second electrode film 65. The first electrode film 64 collectively covers the region of the interlayer film 50 where the multiple outer openings 56 are formed, and extends into the multiple outer openings 56 from above the insulating surface 51. The first electrode film 64 has a portion that covers the insulating surface 51 in a film-like manner and a portion that covers the wall surfaces of the multiple outer openings 56 in a film-like manner.

[0294] The first electrode film 64 covers the arcuate corners of the interlayer film 50 (second oxide film 53) in a film-like manner, following the arcuate corners of the interlayer film 50 (second oxide film 53), and extends into the outer opening 56. The first electrode film 64 has a portion that extends in an arcuate shape at the arcuate corners. This improves the film-forming ability of the first electrode film 64 on the interlayer film 50 (wall surface of the outer opening 56). The first electrode film 64 extends along the wall surface of the outer opening 56 and covers the peripheral insulating film 43, the first oxide film 52, and the second oxide film 53.

[0295] The first electrode film 64 covers the first main surface 3 in a film-like manner at the bottom of each outer opening 56, and is electrically connected to the first main surface 3 (chip 2). Specifically, the first electrode film 64 has a portion that covers the outer recess 57 in a film-like manner at the bottom of each outer opening 56, and is electrically connected to the termination region 40 (overlap region 41) within the outer recess 57.

[0296] The first electrode film 64 may cover the outer recess 57 in a film-like manner at a distance from the height position of the first main surface 3 toward the bottom of the outer recess 57. The first electrode film 64 may have a portion located on the bottom side of the outer recess 57 relative to the height position of the first main surface 3, and a portion located on the peripheral insulating film 43 side relative to the height position of the first main surface 3.

[0297] The second electrode film 65 is disposed on the first electrode film 64 and collectively covers the region of the interlayer film 50 where the multiple outer openings 56 are formed. The second electrode film 65 has a portion that covers the insulating surface 51 with the first electrode film 64 in between, and a portion that covers the wall surfaces of the multiple outer openings 56 with the first electrode film 64 in between.

[0298] The second electrode film 65, following the first electrode film 64, covers the arc corners of the interlayer film 50 (second oxide film 53) in a film-like manner and extends into the outer opening 56. The second electrode film 65 has a portion that extends in an arc shape at the arc corners of the interlayer film 50 (second oxide film 53). This improves the film formability of the second electrode film 65 on the interlayer film 50 (wall surface of the outer opening 56). The second electrode film 65 extends along the wall surface of the outer opening 56 and covers the peripheral insulating film 43, the first oxide film 52, and the second oxide film 53 with the first electrode film 64 sandwiched between them.

[0299] The second electrode film 65 has a portion that covers the outer recess 57 in a film-like manner at the bottom of each outer opening 56, sandwiching the first electrode film 64 therebetween, and is electrically connected to the termination region 40 (overlapping region 41) via the first electrode film 64. When the first electrode film 64 is located on the bottom side of the outer recess 57 with respect to the first main surface 3, the second electrode film 65 may have a portion that is located within the outer recess 57. When the first electrode film 64 has a portion that is located above the first main surface 3, the entire second electrode film 65 is located above the outer recess 57.

[0300] The multiple first buried electrodes 62 form middle layers of the source finger electrodes 68 and are buried in the multiple outer openings 56, respectively. In this embodiment, the multiple first buried electrodes 62 are buried in the multiple outer openings 56 in a one-to-one correspondence via a single first base electrode film 61. The multiple first buried electrodes 62 are electrically connected to the termination region 40 (overlap region 41) via the first base electrode film 61.

[0301] The first buried electrode 62 has a first buried electrode surface 66 exposed from the outer opening 56, exposing the insulating surface 51. Specifically, the first buried electrode 62 is buried in the outer opening 56 at a distance from the insulating surface 51 toward the first main surface 3, exposing a portion of the first base electrode film 61 (second electrode film 65) that covers the insulating surface 51. In other words, the first buried electrode surface 66 is located closer to the first main surface 3 than the insulating surface 51.

[0302] The first buried electrode 62 covers the first oxide film 52 and the second oxide film 53 with the first base electrode film 61 sandwiched therebetween. The first buried electrode 62 has a portion that covers the arc corner portion of the interlayer film 50 with the first base electrode film 61 sandwiched therebetween. The first buried electrode 62 may be embedded at a distance from the arc corner portion of the interlayer film 50 toward the peripheral insulating film 43, with the entire arc corner portion exposed. The first buried electrode surface 66 is located closer to the insulating surface 51 than the height position of the first oxide film 52 in the outer opening 56. Of course, the first buried electrode surface 66 may also be located closer to the peripheral insulating film 43 than the height position of the first oxide film 52.

[0303] When the first underlying electrode film 61 is located on the bottom side of the outer recess 57 with respect to the first main surface 3, the first buried electrode 62 may have a portion located within the outer recess 57. When the first underlying electrode film 61 has a portion located above the first main surface 3, the entire first buried electrode 62 is located above the outer recess 57.

[0304] The first main electrode film 63 forms an upper layer of the source finger electrode 68 and covers the first base electrode film 61 and the plurality of first buried electrodes 62 in a film-like manner. The first main electrode film 63 is mechanically and electrically connected to the first base electrode film 61 in the portion covering the insulating surface 51, and is mechanically and electrically connected to the plurality of first buried electrodes 62 in the portion covering the plurality of outer openings 56. The first main electrode film 63 is electrically connected to the termination region 40 (overlap region 41) via the first base electrode film 61 and the plurality of first buried electrodes 62.

[0305] The first main electrode film 63 is connected to the first buried electrode surface 66 at a height position closer to the first main surface 3 than the height position of the insulating surface 51. The first main electrode film 63 is connected to the first buried electrode surface 66 at a height position higher than the height position of the first oxide film 52. The first main electrode film 63 has a portion that covers the recess of the first buried electrode surface 66.

[0306] The first main electrode film 63 may have a portion that covers the arc corner portion of the interlayer film 50 with the first base electrode film 61 sandwiched therebetween. When the first buried electrode 62 is located below the first oxide film 52, the first main electrode film 63 may be connected to the first buried electrode 62 in a region below the first oxide film 52.

[0307] The film formation properties of the first main electrode film 63 in the outer openings 56 are improved by the first buried electrodes 62. This ensures an appropriate current path between the termination region 40 (overlap region 41) and the first main electrode film 63. Such a configuration is effective in suppressing film formation defects caused by the outer openings 56 and reducing wiring resistance.

[0308] The semiconductor device 1A includes a plurality of second silicide portions 69 formed on the surface portions of the first main surface 3 that are exposed from the plurality of outer openings 56. The plurality of second silicide portions 69 are formed in film form along the wall surfaces (side walls and bottom walls) of the plurality of outer recesses 57, and are mechanically and electrically connected to the first underlying electrode film 61. In other words, the plurality of second silicide portions 69 are formed in the surface layer portion of the termination region 40 (overlap region 41), and electrically connect the plurality of first buried electrodes 62 to the termination region 40 (overlap region 41) via the first underlying electrode film 61.

[0309] The second silicide portion 69 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide. The second silicide portion 69 is preferably made of Ti silicide, Ni silicide, or Co silicide. The second silicide portion 69 is particularly preferably made of the same type of silicide as the first silicide portion 67.

[0310] The semiconductor device 1A includes gate finger electrodes 70 selectively routed on the interlayer film 50. The gate finger electrodes 70 transmit a gate potential to the gate wiring 44. The gate finger electrodes 70 are routed on a portion of the interlayer film 50 that covers the gate wiring 44 (i.e., on the outer periphery region 9), and are electrically connected to the gate wiring 44 via a plurality of gate openings 58.

[0311] The gate finger electrode 70 is disposed in a region between the source pad electrode 60 and the source finger electrode 68 at a distance from the source pad electrode 60 and the source finger electrode 68. The gate finger electrode 70 extends in a strip shape along the gate wiring 44. The gate finger electrode 70 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in plan view.

[0312] In this embodiment, the gate finger electrode 70 is formed in a band shape with four sides parallel to the periphery of the first main surface 3 and surrounds the source pad electrode 60. The gate finger electrode 70 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in a plan view (see FIG. 4 ). The gate finger electrode 70 has a pair of open ends on the fourth side surface 5D side through which the source finger electrode 68 passes.

[0313] 8 and 9 , the gate finger electrode 70 includes a second underlying electrode film 71, at least one (in this embodiment, a plurality) second buried electrodes 72, and a second main electrode film 73. The second underlying electrode film 71 may be referred to as a "gate underlying electrode film," the second buried electrode 72 may be referred to as a "gate buried electrode," and the second main electrode film 73 may be referred to as a "gate main electrode film."

[0314] The second base electrode film 71 forms a lower layer of the gate finger electrode 70, and covers the interlayer film 50 in the peripheral region 9. The second base electrode film 71 collectively covers the region of the interlayer film 50 where the multiple gate openings 58 are formed, and extends into the multiple gate openings 58 from above the insulating surface 51. The second base electrode film 71 has a portion that covers the insulating surface 51 in a film-like manner, and a portion that covers the wall surfaces of the multiple gate openings 58 in a film-like manner.

[0315] The second base electrode film 71 has a layered structure including a first electrode film 74 layered on the interlayer film 50, and a second electrode film 75 layered on the first electrode film 74. It is preferable that the first electrode film 74 contains the same type of conductive material as the first electrode film 64 on the source side, and the second electrode film 75 contains the same type of conductive material as the second electrode film 65 on the source side. In this embodiment, the first electrode film 74 contains a Ti film, and the second electrode film 75 contains a TiN film.

[0316] The second base electrode film 71 does not necessarily have to have a laminated structure, and may have a single-layer structure consisting of either the first electrode film 74 (Ti film) or the second electrode film 75 (TiN film). The first electrode film 74 may have a thickness approximately equal to that of the first electrode film 64 on the source side. The second electrode film 75 may have a thickness approximately equal to that of the second electrode film 65 on the source side.

[0317] The first electrode film 74 collectively covers the region of the interlayer film 50 where the multiple gate openings 58 are formed, and extends into the multiple gate openings 58 from above the insulating surface 51. In other words, the first electrode film 74 has a portion that covers the insulating surface 51 in a film-like manner and a portion that covers the wall surfaces of the multiple gate openings 58 in a film-like manner.

[0318] The first electrode film 74 covers the arcuate corners of the interlayer film 50 (second oxide film 53) in a film-like manner, following the arcuate corners, and extends into the gate opening 58. The first electrode film 74 has a portion that extends in an arcuate shape at the arcuate corners. This improves the film-forming properties of the first electrode film 74 on the interlayer film 50 (wall surface of the gate opening 58).

[0319] The first electrode film 74 extends along the wall surface of the gate opening 58 and covers the first oxide film 52 and the second oxide film 53. The first electrode film 74 covers the gate wiring 44 at the bottom of each gate opening 58 in a film-like manner and is electrically connected to the gate wiring 44.

[0320] The second electrode film 75 collectively covers, in a film form, the region of the interlayer film 50 on the first electrode film 74 where the multiple gate openings 58 are formed. That is, the second electrode film 75 has a portion that covers the insulating surface 51 with the first electrode film 74 in between, and a portion that covers the wall surfaces of the multiple gate openings 58 with the first electrode film 74 in between.

[0321] The second electrode film 75, following the example of the first electrode film 74, covers the arc corners of the interlayer film 50 (second oxide film 53) in a film-like manner and extends into the gate opening 58. The second electrode film 75 has a portion that extends in an arc shape at the arc corners of the interlayer film 50 (second oxide film 53). This improves the film formability of the second electrode film 75 on the interlayer film 50 (wall surface of the gate opening 58).

[0322] The second electrode film 75 extends along the wall surface of the gate opening 58 and covers the first oxide film 52 and the second oxide film 53 with the first electrode film 74 sandwiched therebetween. The second electrode film 75 has a portion at the bottom of each gate opening 58 that covers the gate wiring 44 in a film-like manner with the first electrode film 74 sandwiched therebetween, and is electrically connected to the gate wiring 44 via the first electrode film 74.

[0323] The multiple second buried electrodes 72 form a middle layer of the gate finger electrode 70 and are buried in the multiple gate openings 58, respectively. The second buried electrodes 72 contain a conductive material different from the conductive material of the second base electrode film 71. The second buried electrodes 72 contain at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy. The second buried electrodes 72 preferably contain the same type of conductive material as the conductive material of the first buried electrodes 62. In this embodiment, the second buried electrodes 72 contain tungsten.

[0324] In this embodiment, the second buried electrodes 72 are buried in one-to-one correspondence with the gate openings 58 via a single second base electrode film 71. The second buried electrodes 72 are electrically connected to the gate wiring 44 via the second base electrode film 71 in the gate openings 58.

[0325] The second buried electrode 72 has a second buried electrode surface 76 exposed from the gate opening 58, exposing the insulating surface 51. The second buried electrode surface 76 may be referred to as a "gate buried electrode surface." The second buried electrode 72 is buried in the gate opening 58 at a distance from the insulating surface 51 toward the first main surface 3, exposing a portion of the second base electrode film 71 (second electrode film 75) that covers the insulating surface 51. In other words, the second buried electrode surface 76 is located closer to the first main surface 3 than the insulating surface 51.

[0326] The second buried electrode 72 covers the first oxide film 52 and the second oxide film 53 with the second base electrode film 71 sandwiched therebetween. The second buried electrode 72 has a portion that covers the arc corner portion of the interlayer film 50 with the second base electrode film 71 sandwiched therebetween. The second buried electrode 72 may be embedded at a distance from the arc corner portion of the interlayer film 50 toward the gate wiring 44, with the entire arc corner portion exposed. The second buried electrode surface 76 is located closer to the insulating surface 51 than the height position of the first oxide film 52. Of course, the second buried electrode surface 76 may also be located closer to the gate wiring 44 than the height position of the first oxide film 52.

[0327] The second main electrode film 73 forms an upper layer of the gate finger electrode 70, and covers the second base electrode film 71 and the plurality of second buried electrodes 72 in a film form. The second main electrode film 73 contains a conductive material different from the conductive material of the second base electrode film 71 and the conductive material of the second buried electrodes 72.

[0328] The second main electrode film 73 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The second main electrode film 73 preferably includes the same type of conductive material as the conductive material of the first main electrode film 63. The second main electrode film 73 may have a thickness approximately equal to that of the first main electrode film 63.

[0329] The second main electrode film 73 is mechanically and electrically connected to the second base electrode film 71 in a portion covering the insulating surface 51, and is mechanically and electrically connected to the plurality of second buried electrodes 72 in a portion covering the plurality of gate openings 58. As a result, the second main electrode film 73 is electrically connected to the gate wiring 44 via the second base electrode film 71 and the plurality of second buried electrodes 72.

[0330] The second main electrode film 73 is connected to the second buried electrode 72 at a height position closer to the first main surface 3 than the height position of the insulating surface 51. The second main electrode film 73 is connected to the second buried electrode surface 76 above the height position of the first oxide film 52. The second main electrode film 73 has a portion that covers the recess of the second buried electrode surface 76.

[0331] The second main electrode film 73 may have a portion that covers the arc corner portion of the interlayer film 50 with the second base electrode film 71 sandwiched therebetween. When the second buried electrode 72 is located below the first oxide film 52, the second main electrode film 73 may be connected to the second buried electrode 72 in a region below the first oxide film 52.

[0332] The film formation properties of the second main electrode film 73 for the multiple gate openings 58 are improved by the multiple second buried electrodes 72. This ensures an appropriate current path between the gate wiring 44 and the second main electrode film 73. This configuration is effective in suppressing film formation defects caused by the multiple gate openings 58 and reducing wiring resistance.

[0333] The semiconductor device 1A includes a gate pad electrode 80 disposed on the interlayer film 50. The gate pad electrode 80 is a terminal electrode to which a gate potential is applied from the outside. The gate pad electrode 80 may also be referred to as a "second pad electrode," a "second main surface electrode," a "second terminal electrode," or the like. The gate pad electrode 80 is disposed in a region between the source pad electrode 60 and the source finger electrodes 68 and spaced apart from the source pad electrode 60 and the source finger electrodes 68.

[0334] In this embodiment, the gate pad electrode 80 is disposed in a region on the third side surface 5C side of the first pad portion 60a, and is sandwiched between the second pad portion 60b and the third pad portion 60c. That is, the gate pad electrode 80 faces the first pad portion 60a in the first direction X, and faces the second pad portion 60b and the third pad portion 60c in the second direction Y.

[0335] The gate pad electrode 80 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate pad electrode 80 has a planar area less than that of the source pad electrode 60 (first pad portion 60a). The gate pad electrode 80 may have a planar area less than that of the second pad portion 60b (third pad portion 60c).

[0336] The gate pad electrode 80 is disposed on a portion covering the active region 8 and the peripheral region 9, and is connected to the gate finger electrode 70. The gate pad electrode 80 may cover the plurality of gate electrodes 32 with the interlayer film 50 interposed therebetween, or may cover the gate wiring 44 with the interlayer film 50 interposed therebetween.

[0337] Similar to the gate finger electrode 70, the gate pad electrode 80 includes a second base electrode film 71 and a second main electrode film 73. The second base electrode film 71 forms a lower layer of the gate pad electrode 80 and covers the interlayer film 50 in a film-like manner. Similar to the gate finger electrode 70, the second base electrode film 71 has a layered structure including a first electrode film 74 and a second electrode film 75. The first electrode film 74 covers the interlayer film 50 in a film-like manner, and the second electrode film 75 covers the first electrode film 74 in a film-like manner. The second main electrode film 73 forms an upper layer of the gate pad electrode 80 and covers the second base electrode film 71 in a film-like manner.

[0338] Although not specifically shown in the drawings, the gate pad electrode 80 may have a plurality of second buried electrodes 72, similar to the gate finger electrode 70. In this case, the gate pad electrode 80 may be electrically connected to the gate wiring 44 via the plurality of second buried electrodes 72, similar to the gate finger electrode 70.

[0339] When a plurality of gate electrodes 32 are disposed below the gate pad electrode 80, the gate pad electrode 80 may be electrically connected to the plurality of gate electrodes 32 via a plurality of second buried electrodes 72. Of course, the gate pad electrode 80 does not have to have a plurality of second buried electrodes 72. In other words, the gate pad electrode 80 does not have to have an electrical connection portion to the plurality of gate electrodes 32 and an electrical connection portion to the gate wiring 44 in the region directly below it.

[0340] The gate potential applied to the gate pad electrode 80 is applied to the gate wiring 44 via the gate finger electrode 70. The gate potential is transmitted to the plurality of gate electrodes 32 via a wiring path (current path) along the gate wiring 44. This turns on the plurality of gate electrodes 32, controlling the on / off of the plurality of channel regions 28, 29.

[0341] The semiconductor device 1A includes a drain pad electrode 85 covering the second main surface 4. The drain pad electrode 85 is a terminal electrode to which a drain potential is applied from the outside. The drain pad electrode 85 may also be referred to as a "third pad electrode," a "third main surface electrode," a "third terminal electrode," or the like. The drain pad electrode 85 is electrically connected to the drain region 10. The drain pad electrode 85 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). The drain pad electrode 85 may also partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.

[0342] The breakdown voltage that can be applied between the source pad electrode 60 and the drain pad electrode 85 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0343] 12 is a schematic diagram showing a wafer 100 used in the manufacture of semiconductor device 1A. Referring to FIG. 12, wafer 100 is a base material of chip 2 and includes SiC single crystal. Wafer 100 is formed in a flat disk shape. Of course, wafer 100 may also be formed in a flat rectangular parallelepiped shape. Wafer 100 has a first wafer main surface 101 on one side, a second wafer main surface 102 on the other side, and a wafer side surface 103 connecting first wafer main surface 101 and second wafer main surface 102.

[0344] The first wafer main surface 101 corresponds to the first main surface 3 of the chip 2, and the second wafer main surface 102 corresponds to the second main surface 4 of the chip 2. The first wafer main surface 101 and the second wafer main surface 102 are formed by the c-plane of the SiC single crystal. The first wafer main surface 101 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 102 is formed by the carbon surface of the SiC single crystal. The wafer 100 (the first wafer main surface 101 and the second wafer main surface 102) has the off-direction and off-angle described above.

[0345] The wafer 100 has a mark 104 on the wafer side surface 103 that indicates the crystal orientation of the SiC single crystal. The mark 104 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is linearly cut out in a plan view. The orientation notch is a cutout that is concave (e.g., tapered) toward the center of the first wafer main surface 101 in a plan view.

[0346] The mark 104 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The mark 104 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.

[0347] In this embodiment, wafer 100 has a stacked structure including a first semiconductor layer 6 and a second semiconductor layer 7. First semiconductor layer 6 is made of a semiconductor wafer (SiC wafer) including SiC single crystal (semiconductor single crystal) and has the off-orientation and off-angle described above. First semiconductor layer 6 forms second wafer main surface 102 and wafer side surface 103.

[0348] The second semiconductor layer 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal) and is stacked on the first semiconductor layer 6. That is, in this embodiment, the wafer 100 is made of an epitaxial wafer (a so-called epi-wafer) having a stacked structure including a semiconductor wafer and an epitaxial layer. The second semiconductor layer 7 has the off direction and off angle described above. The second semiconductor layer 7 forms the first wafer main surface 101 and wafer side surface 103.

[0349] The wafer 100 includes a drain region 10 in a region (surface layer portion) on the second wafer main surface 102 side. The drain region 10 is formed in a layer shape extending along the second wafer main surface 102. In this embodiment, the drain region 10 is formed by the first semiconductor layer 6.

[0350] The wafer 100 includes a drift region 11 in a region (surface layer portion) on the first wafer main surface 101 side. The drift region 11 is formed in a layer shape extending along the first wafer main surface 101 and is electrically connected to the drain region 10. In this embodiment, the drift region 11 is formed by the second semiconductor layer 7.

[0351] The wafer 100 includes a plurality of device regions 105 and a plurality of cutting lines 106. For example, the plurality of device regions 105 and the plurality of cutting lines 106 are defined by alignment marks or the like formed on the first wafer main surface 101. Each device region 105 corresponds to a semiconductor device 1A. Each of the plurality of device regions 105 is set to have a quadrangular shape in a plan view.

[0352] In this embodiment, the multiple device regions 105 are set in a matrix along the first direction X and the second direction Y in a plan view. The multiple device regions 105 are set at intervals inward from the periphery of the first wafer main surface 101 in a plan view. The multiple cutting lines 106 are set in a lattice pattern extending along the first direction X and the second direction Y to partition the multiple device regions 105.

[0353] 13A to 13H are cross-sectional views showing a manufacturing method of the semiconductor device 1 A. Each of the cross-sections shows a part of the active region 8 (the part where the body structure 12 is formed) in one device region 105.

[0354] 13A, first, the aforementioned wafer 100 preparation step is performed. Next, referring to FIG. 13B, a first mask 111 having a predetermined layout is formed. The first mask 111 is formed on the first wafer main surface 101. The first mask 111 has a plurality of openings 112 that expose regions where a plurality of body regions 13 are to be formed.

[0355] The first mask 111 may include either or both of an inorganic mask (a so-called hard mask) and an organic mask (a so-called soft mask). The first mask 111 may have a single-layer structure made of an inorganic mask or an organic mask. The first mask 111 may have a layered structure including an inorganic mask and an organic mask layered in this order on the first wafer main surface 101 side.

[0356] The first mask 111 may include at least one of a silicon oxide film, a silicon nitride film, and a polysilicon film as an inorganic mask, or may include a positive or negative type photosensitive resin film (i.e., a resist film) as an organic mask.

[0357] 13C , a body region 13 formation step is performed. In this step, a p-type impurity (trivalent element) is implanted into the surface layer of the drift region 11 by ion implantation through the opening 112 (first mask 111). The p-type impurity (trivalent element) is preferably aluminum. The p-type impurity is implanted into the surface layer of the drift region 11 so that the horizontal implantation range decreases in the thickness direction. This forms a body region 13 having a peripheral portion that is inclined obliquely relative to the first wafer main surface 101.

[0358] Specifically, the p-type impurity is implanted into the surface layer of the drift region 11 by oblique ion implantation at an implantation angle that is oblique with respect to the first wafer main surface 101. When a vertical line extending along the vertical direction Z is set as a reference angle (0°), the implantation angle is the irradiation angle of the p-type impurity with respect to the vertical line.

[0359] In the oblique ion implantation method, p-type impurities are implanted at positive and negative implantation angles relative to the vertical line. The positive and negative implantation angles are defined relative to each other. Therefore, when one side of the horizontal direction (first direction X in this embodiment) relative to the vertical line is defined as a positive implantation angle, the other side of the horizontal direction (first direction X in this embodiment) relative to the vertical line is defined as a negative implantation angle.

[0360] In the oblique ion implantation method, the p-type impurity is also introduced into a region of drift region 11 directly below first mask 111. Some of the p-type impurity may pass through the lower end of first mask 111 and be implanted into a surface layer portion of drift region 11. The p-type impurity is implanted in an arc shape (circular arc shape) starting from the lower end of opening 112 of first mask 111.

[0361] This appropriately forms the body region 13 having a peripheral portion that is inclined in an oblique direction (i.e., the sub-inclined portion 14 and the main inclined portion 15). In addition, by introducing the p-type impurity at positive and negative implantation angles, a duplicated implantation site of the p-type impurity is generated in the inner portion (middle portion) of the opening 112, and a first heavily doped region 24, a lightly doped region 25, and a second heavily doped region 26 are formed.

[0362] The p-type impurity may be implanted in a single step at a target depth position in the surface layer of drift region 11. The p-type impurity is preferably implanted in multiple steps at different implantation angles at different target depth positions in the surface layer of drift region 11. In either the single-step implantation step or the multi-step implantation step, the p-type impurity implantation step may include a step of implanting the p-type impurity multiple times at the same target depth position in drift region 11 under the same or different process conditions.

[0363] That is, the "single-stage implantation process" herein refers to a process of implanting p-type impurities once or multiple times at the same target depth position to form body region 13. On the other hand, the "multi-stage implantation process" refers to a process of implanting p-type impurities once or multiple times at multiple target depth positions to form body region 13.

[0364] The number of injection stages (number of target depth positions) of p-type impurities in the multistage injection process may be two, three, four, five, six, seven, eight, nine, or ten. The number of injection stages is preferably two or more and five or less. In the multistage injection process, p-type impurities are injected into different target depth positions so that the injection sites of the p-type impurities overlap in the thickness direction. This forms the body region 13 having a concentration gradient (first concentration gradient portion 22 and second concentration gradient portion 23) that gradually increases and decreases in the thickness direction.

[0365] When p-type impurities are implanted deep into the drift region 11 in the multistage implantation process, capture of the p-type impurities by the drift region 11 and offset of the p-type impurity concentration are taken into consideration, thereby suppressing an undesirable decrease in the p-type impurity concentration at the bottom end of the body region 13. For example, in the multistage implantation process, the dose (impurity concentration) of the p-type impurity in the drift region 11 is adjusted to increase as the implantation location becomes deeper. The dose is adjusted appropriately depending on the p-type impurity concentration of the body region 13 to be formed.

[0366] In the multistage implantation process, the implantation energy of the p-type impurity into the drift region 11 is adjusted so as to increase as the implantation location becomes deeper. The implantation energy is 50 KeV or more and 1000 KeV or less, and is adjusted appropriately depending on the target depth position at which the p-type impurity concentration is to be implanted.

[0367] In a deep region of the drift region 11, the implantation range of the p-type impurity can be expanded in the horizontal direction due to process conditions (dose amount and implantation energy). Therefore, in the multistage implantation process, the implantation angle of the p-type impurity with respect to the drift region 11 is adjusted to become smaller as the implantation location becomes deeper. In other words, in the multistage implantation process, the implantation angle of the p-type impurity with respect to the drift region 11 is adjusted to become larger as the implantation location becomes shallower.

[0368] This appropriately limits the expansion range (implantation range) of the p-type impurity in the deep region, and prevents the lower end region of the body region 13 from extending outward beyond the upper end region of the body region 13. In other words, the body region 13 is appropriately formed to have a tapered shape in the thickness direction. For example, the body region 13 can have a maximum body width WB at the upper end or a region near the upper end. Also, the body region 13 can have a minimum body width WB at the lower end or a region near the lower end.

[0369] The implantation angle of the p-type impurity is preferably set to be equal to or greater than 0° and equal to or less than 45°, taking into consideration shadowing by the first mask 111. The p-type impurity may be implanted in a single step or in multiple steps at a first implantation angle to a first target depth position where a region below the intermediate portion of the body region 13 is to be formed. When the p-type impurity is implanted in multiple steps to the first target depth position, the first implantation angle is adjusted to decrease as the implantation position becomes deeper.

[0370] The first implantation angle may be greater than or equal to 0° and less than or equal to 20°. The first implantation angle may be set to a value belonging to at least one of the ranges of greater than or equal to 2.5°, greater than or equal to 2.5°, less than or equal to 5°, greater than or equal to 5°, less than or equal to 7.5°, less than or equal to 7.5°, less than or equal to 10°, less than or equal to 10°, less than or equal to 12.5°, less than or equal to 12.5°, less than or equal to 15°, less than or equal to 15°, less than or equal to 17.5°, and less than or equal to 17.5°. The first implantation angle is preferably greater than 0° and less than 10°.

[0371] When multi-stage implantation is performed at the first target depth position, the first implantation angle with respect to the deepest portion may be 0° or more and 5° or less. The first implantation angle with respect to regions other than the deepest portion may be greater than 0° and 10° or less. The first implantation angle allows the main inclined portion 15 of the body region 13 to be appropriately formed.

[0372] The p-type impurity may be implanted in a single step or multiple steps at a second implantation angle equal to or less than the first implantation angle to a second target depth position where a region above the intermediate portion of the body region 13 is to be formed. The second implantation angle is preferably less than the first implantation angle. When the p-type impurity is implanted in multiple steps to the second target depth position, the second implantation angle is adjusted to decrease as the implantation position becomes deeper.

[0373] The second implantation angle may be 10° or greater and 45° or less. The second implantation angle may be set to a value belonging to at least one of the following ranges: 10° or greater and 15° or less, 15° or greater and 20° or less, 20° or greater and 25° or less, 25° or greater and 30° or less, 30° or greater and 35° or less, 35° or greater and 40° or less, 40° or greater and 45° or less, and 45° or greater and 50° or less. The second implantation angle is preferably 5° or greater and 30° or less. The second implantation angle is particularly preferably 10° or greater and 25° or less. The second implantation angle allows the sub-inclined portion 14 of the body region 13 to be appropriately formed.

[0374] When the body region 13 is formed by only a single-stage implantation process, the implantation angle of the p-type impurity may be 5° or more and 30° or less. In this case, the implantation angle is preferably 10° or more and 25° or less. The body region 13 according to the first to sixth embodiments (see FIGS. 10A to 10F) and the concentration profiles of the body region 13 (see FIGS. 11A and 11B) can be obtained by appropriately adjusting the process conditions.

[0375] Although not specifically illustrated, the process of forming the body region 13 may include a process of forming the outer body region 35. In this case, the opening 112 of the first mask 111 may expose a region where the outer body region 35 is to be formed in addition to a region where the body region 13 is to be formed.

[0376] In this case, the p-type impurity step (oblique ion implantation step) includes a step of implanting p-type impurities into the region where the outer body region 35 is to be formed through the opening 112. This step forms the outer body region 35 having a concentration gradient similar to that of the body region 13.

[0377] 13D , a step of forming a second mask 113 having a predetermined layout is performed. In this embodiment, the second mask 113 is used in combination with the first mask 111 and is placed on the first wafer main surface 101 within the openings 112 of the first mask 111. The second mask 113, together with the first mask 111, defines a plurality of inner openings 114 within the openings 112. The plurality of inner openings 114 expose regions where a plurality of source regions 16, 17 are to be formed.

[0378] The second mask 113 may include either or both of an inorganic mask (a so-called hard mask) and an organic mask (a so-called soft mask). The second mask 113 may have a single-layer structure made of an inorganic mask or an organic mask. The second mask 113 may have a layered structure including an inorganic mask and an organic mask layered in this order on the second wafer main surface 102 side.

[0379] The second mask 113 may include at least one of a silicon oxide film, a silicon nitride film, and a polysilicon film as an inorganic mask, or may include a positive or negative type photosensitive resin film (i.e., a resist film) as an organic mask.

[0380] The second mask 113 preferably contains a mask material different from the mask material of the first mask 111. The second mask 113 may have a thickness greater than the thickness of the first mask 111. Of course, the second mask 113 may have a thickness less than the thickness of the first mask 111.

[0381] Next, a process for forming a plurality of source regions 16, 17 is performed. In this process, n-type impurities (pentavalent elements) are implanted into the surface layer of the body region 13 by ion implantation through the plurality of inner openings 114 (first mask 111 and second mask 113). The n-type impurities (pentavalent elements) are preferably phosphorus. The n-type impurities are introduced substantially perpendicular to the first wafer main surface 101 by vertical ion implantation. This forms a plurality of source regions 16, 17.

[0382] The first mask 111 and the second mask 113 are removed after the step of forming the source regions 16 and 17. Of course, the first mask 111 may be removed after the step of forming the body region 13 and before the step of forming the source regions 16 and 17. In this case, the second mask 113 is formed having a plurality of inner openings 114 that expose regions where the source regions 16 and 17 are to be formed.

[0383] 13E , a step of forming a third mask 115 having a predetermined layout is performed. The third mask 115 is placed on the first wafer main surface 101. The third mask 115 has a plurality of openings 116 that expose regions where a plurality of contact regions 18 are to be formed. The third mask 115 may include either or both of an inorganic mask (a so-called hard mask) and an organic mask (a so-called soft mask). The third mask 115 may be formed from the same mask material as the second mask 113.

[0384] Next, a contact region 18 formation process is performed. In this process, p-type impurities (trivalent elements) are implanted into the surface layer of the body region 13 by ion implantation through the multiple openings 116 (third mask 115). The p-type impurities (trivalent elements) are preferably aluminum. The p-type impurities are introduced substantially perpendicular to the first wafer main surface 101 by vertical ion implantation. This forms the contact region 18. After the contact region 18 formation process, the third mask 115 is removed. Through the fixation process including the above, the body structure 12 is formed.

[0385] 13F, a step of forming an insulating film 31 is performed. The insulating film 31 is formed in a film shape on the first wafer main surface 101. The insulating film 31 may be formed by a CVD (Chemical Vapor Deposition) method or an oxidation treatment method (for example, a thermal oxidation treatment method).

[0386] 13G, a step of forming a base electrode 117 that serves as a base of gate electrode 32 is performed. Base electrode 117 is formed in the form of a film on insulating film 31. Base electrode 117 may be formed by a CVD method.

[0387] 13H , a step of forming a fourth mask 118 having a predetermined layout is performed. The fourth mask 118 is disposed on the base electrode 117 and has an opening 119 that exposes regions other than the region where the gate electrode 32 is to be formed. The fourth mask 118 may include either or both of an inorganic mask (a so-called hard mask) and an organic mask (a so-called soft mask). The fourth mask 118 may be formed from the same mask material as the second mask 113, etc.

[0388] Next, unnecessary portions of the base electrode 117 are removed by etching through the openings 119 (fourth mask 118) until the insulating film 31 is exposed. The etching method may be either or both of wet etching and dry etching.

[0389] As a result, the gate electrode 32 is formed on the insulating film 31. Thereafter, the steps of forming the remaining components are sequentially carried out, and the wafer 100 is cut along the cutting lines 106. In this way, a plurality of semiconductor devices 1A are cut out from one wafer 100. The semiconductor device 1A is manufactured through the steps including those described above.

[0390] 14 is an enlarged cross-sectional view showing a body structure 120 according to a reference example (hereinafter simply referred to as the "body structure 120"). The body structure 120 includes a body region 121 according to the reference example (hereinafter simply referred to as the "body region 121") instead of the body region 13. The body region 121 is formed by single-stage or multi-stage implantation (multi-stage implantation in this embodiment) of p-type impurities at different depth positions in the surface layer of the drift region 11 by vertical ion implantation via a first mask 111 in the p-type impurity implantation step shown in FIG. 13C.

[0391] The body region 121 is formed in the surface layer portion of the drift region 11 so that the body width WB does not decrease in the thickness direction, and does not have a peripheral portion that is inclined in an oblique direction (i.e., a body gradient GB). The peripheral portion of the body region 121 extends in a direction perpendicular to the first main surface 3 (i.e., the vertical direction Z), and does not have either the sub-inclined portion 14 or the main-inclined portion 15.

[0392] For example, when a vertical line Lz (see the two-dot chain line) is set passing through the upper end of the peripheral portion in the vertical direction Z, the body region 121 has a portion located on the vertical line Lz in a thickness range of at least 1 / 2 (=50%) of the body thickness TB. In this example, the body region 121 has an area other than the area near the lower end located on the vertical line Lz. For example, in the body region 121, an area of ​​at least 4 / 5 (=80%) of the body thickness TB is located on the vertical line Lz.

[0393] In this example, the body region 121 has multiple bulging portions 122 that extend horizontally, similar to the bulging portions 19 of the body region 13 according to the second to fourth embodiments (see FIGS. 10B to 10C ). In the region near the bottom of the body region 121, p-type impurities are implanted with greater implantation energy and at a relatively higher concentration than in the region near the top. On the other hand, with vertical ion implantation, the implantation range of the p-type impurities is not controlled. Therefore, the implantation range of the p-type impurities expands horizontally as the implantation depth increases due to process conditions.

[0394] Therefore, unlike the bulge portion 19 of the body region 13, the multiple bulge portions 122 are formed in multiple stages so as to protrude outward in sequence from the upper end side to the lower end side, forming undulations with repeated concave and convex portions. That is, in this example, the body region 121 is formed in a tapered shape so that the body width WB increases in the thickness direction. Even when p-type impurities are implanted in one stage by vertical ion implantation, the implantation range of the p-type impurities is expanded horizontally in the region on the lower end side of the body region 121 for the same reason as for the lowest bulge portion 122.

[0395] 15A is a graph showing the concentration gradient in the first region of the body structure 120 according to the reference example. The graph in FIG. 15A corresponds to the graph in FIG. 11A. The first region of the body structure 120 is a region in the body region 121 in the second direction Y where neither the source regions 16, 17 nor the contact region 18 are formed. For example, the second region of the body structure 120 is located at both ends of the body region 121 in the second direction Y. In FIG. 15A, the vertical axis represents the impurity concentration, and the horizontal axis represents the body width WB.

[0396] 15A shows a first reference density distribution RA1 (thin line), a second reference density distribution RA2 (thin dashed line), a third reference density distribution RA3 (thick line), and a fourth reference density distribution RA4 (thick dashed line). The first to fourth reference density distributions RA1 to RA4 are to be compared with the above-mentioned first to fourth density distributions A1 to A4, respectively (see FIG. 11A).

[0397] With reference to the first to fourth reference concentration distributions RA1 to RA4, the body region 121 has a substantially constant p-type impurity concentration in both the thickness direction and the horizontal direction, and does not have a concentration gradient. That is, the body region 121 does not have the first concentration gradient portion 22 or the second concentration gradient portion 23. The body region 121 also does not have the first high concentration region 24, the low concentration region 25, or the second high concentration region 26.

[0398] As can be seen from the first to fourth reference concentration distributions RA1 to RA4, the periphery of the body region 121 is located on the same line. In other words, the periphery of the body region 121 is located on a vertical line Lz that extends perpendicular to the first main surface 3 in the thickness direction, and does not have a body gradient GB.

[0399] 15B is a graph showing the concentration gradient in the second region of the body structure 120 according to the reference example. The graph in FIG. 15B corresponds to the graph in FIG. 11B. The second region of the body structure 120 is a region in the body region 121 in the second direction Y where both the source regions 16, 17 and the contact region 18 are formed. For example, the second region of the body structure 120 is a middle portion of the body region 121 in the second direction Y. In FIG. 15B, the vertical axis represents the impurity concentration, and the horizontal axis represents the body width WB.

[0400] 15B shows a first reference concentration distribution RB1 (thin line), a second reference concentration distribution RB2 (thin dashed line), a third reference concentration distribution RB3 (thick line), and a fourth reference concentration distribution RB4 (thick dashed line). The first reference concentration distribution RB1 has a concentration distribution in which the n-type impurity concentration of the source regions 16 and 17 and the p-type impurity concentration of the contact region 18 are added to the first reference concentration distribution RA1.

[0401] The second reference concentration distribution RB2 has a concentration distribution in which the n-type impurity concentration on the bottom side of the source regions 16 and 17 and the p-type impurity concentration on the bottom side of the contact region 18 are added to the second reference concentration distribution RA2. The third and fourth reference concentration distributions RB3 and RB4 correspond to the third and fourth reference concentration distributions RA3 and RA4, respectively. The first to fourth reference concentration distributions RB1 to RB4 are to be contrasted with the above-mentioned first to fourth concentration distributions B1 to B4 (see FIG. 11B), respectively.

[0402] With reference to the first to fourth reference concentration distributions RB1 to RB4, the body region 121 has a substantially constant p-type impurity concentration in both the thickness direction and the horizontal direction in the second region as well, and does not have a concentration gradient. That is, the body region 121 does not have the first concentration gradient portion 22 or the second concentration gradient portion 23 in the second region. Furthermore, the body region 121 does not have the first high concentration region 24, the low concentration region 25, or the second high concentration region 26 in the second region.

[0403] As can be seen from the first to fourth reference concentration distributions RB1 to RB4, the periphery of the body region 121 is also located on the same line in the second region. That is, the periphery of the body region 121 is located on a vertical line Lz that extends perpendicular to the first main surface 3 in the thickness direction in the second region, and does not have a body gradient GB.

[0404] When the body regions 121 are formed, the surface drift region 27 is formed so that the drift width WD decreases in the thickness direction along the periphery of the body regions 121 (see FIG. 14 ). Therefore, the surface drift region 27 forms a current path that narrows in the thickness direction in the region between the body regions 121, exhibiting a current confinement effect. As a result, the JFET resistance component increases. Furthermore, the current density in the region between the body regions 121 increases, and the electric field concentrates in the periphery of the body regions 121.

[0405] In contrast, semiconductor device 1A includes a chip 2, an n-type drift region 11, and a p-type body region 13. Chip 2 has a first main surface 3. Drift region 11 is formed in a surface layer portion of first main surface 3. Body region 13 is formed in a tapered shape in the surface layer portion of drift region 11 so that its horizontal width (WB) decreases in the thickness direction, and has a peripheral portion that is inclined obliquely with respect to first main surface 3.

[0406] This configuration provides a semiconductor device 1A having a novel configuration for the body region 13. In this semiconductor device 1A, the current path near the body region 13 in the surface layer portion of the drift region 11 is expanded in the horizontal direction by the peripheral portion of the body region 13.

[0407] This suppresses an increase in resistance near the periphery of the body region 13. Furthermore, the current density near the periphery of the body region 13 is reduced, and electric field concentration in the periphery of the body region 13 is alleviated. This improves electrical characteristics. The chip 2 preferably includes a SiC single crystal. This configuration provides a SiC semiconductor device having a novel configuration for the body region 13.

[0408] The body region 13 is preferably formed so that its width decreases in the thickness direction starting from the upper end on the first main surface 3 side. That is, the body region 13 preferably has a peripheral portion that is inclined obliquely starting from the upper end. With this configuration, the current path near the body region 13 is expanded in the horizontal direction starting from the upper end of the body region 13. This appropriately suppresses an increase in resistance near the peripheral portion of the body region 13 and appropriately alleviates electric field concentration in the peripheral portion of the body region 13.

[0409] It is preferable that the body region 13 has a thickness of 0.5 μm or more, and has a gradient (GB) such that, when the upper end of the peripheral edge is taken as the reference position, the horizontal change in the peripheral edge at the 0.5 μm thickness position is 0.05 μm or more.

[0410] The body region 13 may have a concentration gradient that gradually decreases in the thickness direction. The body region 13 may have a first high concentration region 24 on the inner side and a low concentration region 25 on the peripheral side in the horizontal direction, and may have a concentration gradient that gradually decreases from the first high concentration region 24 to the low concentration region 25. The first high concentration region 24 may have a portion formed in a region below the central portion of the body region 13. The low concentration region 25 may have a portion formed in a region below the central portion of the body region 13.

[0411] The first high-concentration region 24 may have a concentration gradient that gradually decreases in the thickness direction. The low-concentration region 25 may have a concentration gradient that gradually decreases in the thickness direction. The concentration difference between the first high-concentration region 24 and the low-concentration region 25 may gradually decrease toward the bottom of the body region 13. The peripheral portion of the body region 13 may have multiple bulges 19 that protrude horizontally in multiple stages in the thickness direction.

[0412] The semiconductor device 1A may include a plurality of body regions 13 formed at intervals in a surface layer portion of the drift region 11. In this case, the semiconductor device 1A may include an n-type surface drift region 27 partitioned in a region between the plurality of body regions 13 in the surface layer portion of the drift region 11. The surface drift region 27 is partitioned so that its horizontal width (WD) gradually increases in the thickness direction, and forms a JFET structure together with the plurality of body regions 13.

[0413] With this configuration, the surface drift region 27 forms a current path that spreads in the thickness direction in the region between the body regions 13, reducing current constriction. This reduces the JFET resistance component of the JFET structure. Furthermore, the surface drift region 27 reduces the current density in the region between the body regions 13, mitigating electric field concentration around the periphery of the body regions 13.

[0414] The semiconductor device 1A may include n-type source regions 16, 17. The source regions 16, 17 may have an n-type impurity concentration higher than the n-type impurity concentration of the drift region 11 and may be formed in a surface layer portion of the body region 13. The semiconductor device 1A may include a p-type contact region 18. The contact region 18 may have a p-type impurity concentration higher than the p-type impurity concentration of the body region 13 and may be formed in a surface layer portion of the body region 13.

[0415] From another perspective, the semiconductor device 1A may include a chip 2, an n-type drift region 11, a p-type body region 13, and a p-type contact region 18. The chip 2 has a first main surface 3. The drift region 11 is formed in a surface layer portion of the first main surface 3. The body region 13 is formed in a surface layer portion of the drift region 11. The contact region 18 has a p-type impurity concentration higher than the p-type impurity concentration of the body region 13, and is formed in the surface layer portion of the body region 13.

[0416] In this configuration, the body region 13 includes a first high concentration region 24 in a thickness range below the contact region 18. The body region 13 includes a low concentration region 25 formed in a region on the peripheral side of the first high concentration region 24 in a thickness range below the contact region 18. With this configuration, the ohmic properties of the contact region 18 are improved by the first high concentration region 24.

[0417] The first high-concentration region 24 preferably has a p-type impurity concentration lower than the p-type impurity concentration of the contact region 18. The low-concentration region 25 preferably has a p-type impurity concentration lower than the p-type impurity concentration of the first high-concentration region 24. This configuration ensures the proper function of the body region 13.

[0418] The semiconductor device 1A may include n-type source regions 16, 17 formed in the surface layer portion of the body region 13. In this case, the low concentration region 25 is preferably formed in a thickness range below the source regions 16, 17. This configuration prevents the n-type impurity concentration of the source regions 16, 17 from being offset by the p-type impurity concentration of the first high concentration region 24. Therefore, the function of the source regions 16, 17 is ensured appropriately.

[0419] The body region 13 may have a peripheral portion that is inclined obliquely with respect to the first main surface 3. With this configuration, the current path near the body region 13 in the surface layer portion of the drift region 11 is expanded horizontally by the peripheral portion of the body region 13. This suppresses an increase in the resistance value near the body region 13.

[0420] 16 is a cross-sectional view showing a semiconductor device 1B according to the second embodiment. The semiconductor device 1B includes a plurality of p-type column regions 130 formed in the drift region 11 within a thickness range below a plurality of body regions 13.

[0421] The column regions 130 have a p-type impurity concentration lower than the p-type impurity concentration of the contact region 18. The column regions 130 may have a p-type impurity concentration lower than the p-type impurity concentration of the body region 13. The column regions 130 may have a p-type impurity concentration lower than the p-type impurity concentration of the body region 13. １６cm －３ 5x10 or more １７ cm －３ It may be the following:

[0422] The column regions 130 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. That is, the column regions 130 are formed in stripes extending in the second direction Y along the body regions 13. The extending direction of the body structures 12 coincides with the off-direction of the SiC single crystal.

[0423] The multiple column regions 130 are formed in a columnar shape extending in the thickness direction in a cross-sectional view, and overlap the multiple body regions 13 in a one-to-one correspondence. The multiple column regions 130 may have a single-layer structure consisting of a single p-type impurity region, or may have a layered structure in which multiple p-type impurity regions are layered in the thickness direction. The configuration of one column region 130 will be specifically described below.

[0424] The column region 130 has a column width WC that is less than the body width WB of the body region 13, and is formed at a distance inward from the peripheral portion (main inclined portion 15) of the body region 13 (see also FIGS. 7 and 10A). This suppresses electrical interference of the column region 130 with the peripheral portion of the body region 13. For example, the column width WC is greater than the width of the contact region 18. The column width WC is adjusted appropriately according to the body width WB.

[0425] The column region 130 has a column thickness TC that is larger than the body thickness TB of the body region 13 (see also FIGS. 7 and 10A). For example, the column thickness TC is smaller than the thickness of the drift region 11. The column thickness TC is adjusted appropriately depending on the thickness of the drift region 11.

[0426] The column region 130 crosses the intermediate portion of the drift region 11 in the thickness direction. The column region 130 has a lower end and an upper end. The lower end of the column region 130 is located closer to the bottom of the drift region 11 than the intermediate portion of the drift region 11. The lower end of the column region 130 may be formed with a gap from the bottom of the drift region 11 toward the body region 13. The lower end of the column region 130 may cross the bottom of the drift region 11 and be located in the surface layer of the drain region 10.

[0427] The upper end of the column region 130 is located closer to the bottom (lower end) of the body region 13 than the middle part of the drift region 11. The upper end of the column region 130 is preferably connected to the bottom of the body region 13. In other words, the column region 130 is preferably electrically connected to the body region 13. Of course, the upper end of the column region 130 may be formed at a distance from the bottom of the body region 13 toward the bottom of the drift region 11, and may face the body region 13 with a part of the drift region 11 in between.

[0428] The semiconductor device 1B includes a plurality of n-type intermediate drift regions 131 formed in the drift region 11. Each of the plurality of intermediate drift regions 131 is made up of an area defined by a plurality of column regions 130 in the drift region 11.

[0429] The intermediate drift region 131 may have an n-type impurity concentration higher than the n-type impurity concentration of the drift region 11, or may have an n-type impurity concentration lower than the n-type impurity concentration of the drift region 11. The intermediate drift region 131 may have an n-type impurity concentration higher than the n-type impurity concentration of the surface drift region 27, or may have an n-type impurity concentration lower than the n-type impurity concentration of the surface drift region 27.

[0430] The intermediate drift regions 131 are arranged alternately with the column regions 130 in the first direction X, and are each formed in a strip shape extending in the second direction Y. That is, the intermediate drift regions 131 are formed in stripes extending in the second direction Y along the column regions 130. The extending direction of the intermediate drift regions 131 coincides with the off-direction of the SiC single crystal.

[0431] The intermediate drift regions 131 are formed in a columnar shape extending in the thickness direction in a cross-sectional view, and are connected in one-to-one correspondence to the surface drift regions 27. Each of the intermediate drift regions 131 has an intermediate drift width WDM that is larger than the drift width WD of the surface drift regions 27, and has both ends connected to two body regions 13 adjacent to each other in the first direction X.

[0432] The intermediate drift regions 131 form charge-balanced pn junctions together with the column regions 130 in a thickness range below the body region 13. The charge-balanced state means that, for adjacent column regions 130, a depletion layer extending from one pn junction and a depletion layer extending from the other pn junction are connected within the intermediate drift regions 131. As a result, the intermediate drift regions 131 and the column regions 130 form a superjunction structure in the region below the body region 13.

[0433] The process of forming the plurality of column regions 130 includes a mask formation process and a p-type impurity implantation process. In the mask formation process, a mask having openings that expose regions where the plurality of column regions 130 are to be formed is formed on the first wafer main surface 101. In the p-type impurity implantation process, p-type impurities are implanted into the drift region 11 by ion implantation through the mask.

[0434] The ion implantation method is preferably a channeling ion implantation method. In the channeling ion implantation step, p-type impurities are implanted along a channel axis (e.g., the c-axis) of the crystal axes of the chip 2 (second semiconductor layer 7) along which atomic rows are sparse. The p-type impurities are implanted deep into the drift region 11 while repeatedly undergoing small-angle scattering due to the channeling effect. In other words, the channeling implantation method reduces the probability of collision of trivalent elements with atomic rows of the SiC single crystal. This results in the formation of multiple column regions 130.

[0435] The step of forming the column region 130 may be performed after the step of forming the body region 13. In this case, the column region 130 is formed inside the drift region 11 so as to be connected to the body region 13 in the thickness direction. The step of forming the column region 130 is preferably performed before the step of forming the body region 13. In this case, in the step of forming the body region 13, the body region 13 is formed in the surface layer portion of the drift region 11 so as to be connected to the column region 130 in the thickness direction.

[0436] According to this process order, the process of forming the body region 13 is performed after the process of forming the column region 130, which suppresses deformation of the body region 13 (particularly deformation of the peripheral portion of the body region 13) caused by the process of implanting the p-type impurity into the column region 130. Furthermore, according to this process order, change in concentration of the body region 13 caused by the process of implanting the p-type impurity into the column region 130 is suppressed.

[0437] As described above, the semiconductor device 1B includes a p-type column region 130 in addition to the configuration of the semiconductor device 1A. The column region 130 is formed in the drift region 11 within a thickness range below the body region 13. This configuration provides a superjunction type semiconductor device 1B in which an increase in resistance value near the body region 13 is suppressed. When the chip 2 includes a SiC single crystal, a superjunction type SiC semiconductor device having a novel configuration for the body region 13 is provided.

[0438] In this embodiment, an example has been shown in which the multiple column regions 130 (multiple intermediate drift regions 131) are formed in stripes extending in the second direction Y along the multiple body regions 13. However, the multiple column regions 130 may be formed in stripes extending in the first direction X and arranged at intervals in the second direction Y. In other words, the extending direction of the multiple column regions 130 may intersect (specifically, be perpendicular to) the off-direction of the SiC single crystal. In this case, the multiple column regions 130 intersect (specifically, be perpendicular to) the multiple body regions 13.

[0439] Of course, the column regions 130 (the intermediate drift regions 131) may be arranged at intervals in an intersecting direction that intersects both the first direction X and the second direction Y, and may each be formed in a strip shape extending in an orthogonal direction that is perpendicular to the intersecting direction. In other words, the extending direction of the column regions 130 may intersect with the off-direction of the SiC single crystal. In this case, the column regions 130 intersect with the body regions 13.

[0440] In this embodiment, an example has been shown in which the plurality of body regions 13 (body structures 12) are formed in stripes extending in the second direction Y. However, the plurality of body regions 13 may be formed in stripes extending in the first direction X and arranged at intervals in the second direction Y. That is, the plurality of body regions 13 may be formed in stripes extending in the first direction X. Furthermore, the extending direction of the plurality of body regions 13 may intersect (specifically, be perpendicular to) the off-direction of the SiC single crystal.

[0441] In this case, the multiple column regions 130 (multiple intermediate drift regions 131) may be formed in stripes extending in the first direction X and arranged at intervals in the second direction Y. In other words, the multiple column regions 130 (multiple intermediate drift regions 131) may be formed in stripes extending in the first direction X along the multiple body regions 13.

[0442] Of course, the column regions 130 may be arranged at intervals in the first direction X and each formed in a band shape extending in the second direction Y. In other words, the column regions 130 may be formed in a stripe shape extending in the second direction Y. Furthermore, the extending direction of the column regions 130 may coincide with the off-direction of the SiC single crystal.

[0443] In this case, the plurality of column regions 130 intersect (specifically, orthogonal to) the plurality of body regions 13. Of course, the plurality of column regions 130 (the plurality of intermediate drift regions 131) may be arranged at intervals in an intersecting direction that intersects both the first direction X and the second direction Y, and may each be formed in a strip shape extending in an orthogonal direction that is orthogonal to the intersecting direction.

[0444] Modified examples that can be applied to the semiconductor devices 1A and 1B according to the first and second embodiments are shown below. Fig. 17 is a cross-sectional view showing a modified example of the field region 42. Fig. 17 illustrates a configuration in which the field region 42 according to the modified example is applied to the semiconductor device 1A. Of course, the field region 42 according to the modified example can also be applied to the semiconductor device 1B.

[0445] In the above-described embodiments, examples have been shown in which a plurality of field regions 42 are formed in the surface layer portion of the drift region 11. However, as shown in FIG. 17 , a single field region 42 may be formed in the surface layer portion of the drift region 11.

[0446] The single field region 42 is formed in a region between the periphery of the first main surface 3 and the plurality of body regions 13 (active regions 8), spaced inward from the periphery of the first main surface 3. Specifically, the single field region 42 is formed in a region between the periphery of the first main surface 3 and the outer body region 35. More specifically, the single field region 42 is formed in a region between the periphery of the first main surface 3 and the termination region 40.

[0447] The single field region 42 is formed in a band shape extending along the multiple body regions 13 (termination region 40) in plan view. The single field region 42 has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y. In this embodiment, the single field region 42 is formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) surrounding the multiple body regions 13 (termination region 40) in plan view. The single field region 42 may have edge portions connecting the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) (see FIG. 4 ).

[0448] The ratio of the width of a single field region 42 to the perimeter width may be 0.1 or more and less than 1. The perimeter width is the width of the perimeter region 9. The width of the perimeter region 9 may be defined by the width between the periphery of the first major surface 3 and the active region 8 (e.g., the inner edge of the outer body region 35). The width ratio may have a value belonging to at least one of the ranges of 0.1 to 0.2, 0.2 to 0.4, 0.4 to 0.6, 0.6 to 0.8, and 0.8 to less than 1.

[0449] The single field region 42 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3, and faces the drain region 10 across a part of the drift region 11. The single field region 42 is preferably formed at a distance from a depth position of the middle part of the drift region 11 toward the first main surface 3. Of course, the single field region 42 may cross the depth position of the middle part of the drift region 11 in the thickness direction.

[0450] The single field region 42 has an inner edge on the termination region 40 side and an outer edge on the peripheral side of the first main surface 3. In this embodiment, the inner edge of the single field region 42 is connected to the outer edge of the termination region 40. This electrically connects the single field region 42 to the termination region 40. In this embodiment, the inner edge of the single field region 42 is connected to the outer edge of the termination region 40 around the entire periphery.

[0451] The p-type impurity concentration of the single field region 42 is the same as that of the semiconductor device 1 A. When the single field region 42 has a p-type impurity concentration substantially equal to that of the termination region 40, the single field region 42 may be extended from the termination region 40 to the surface layer of the drift region 11 as an extension portion of the termination region 40.

[0452] That is, termination region 40 may have a single field region 42 as an extension portion. Of course, the p-type impurity concentration of single field region 42 may be different from the p-type impurity concentration of termination region 40. Furthermore, single field region 42 may be formed at a distance from termination region 40.

[0453] 18 is a cross-sectional view showing a first modified example of a source pad electrode 60. Fig. 18 illustrates a configuration in which the source pad electrode 60 according to the modified example is applied to a semiconductor device 1A. Of course, the field region 42 according to the modified example can also be applied to a semiconductor device 1B.

[0454] In the above-described embodiments, the plurality of first buried electrodes 62 are buried in the plurality of source openings 54 so as to expose the insulating surface 51. However, as shown in FIG. 18 , the source pad electrode 60 may have the plurality of first buried electrodes 62 that are drawn out from the plurality of source openings 54 onto the insulating surface 51 and cover the insulating surface 51.

[0455] The plurality of first buried electrodes 62 cover the first base electrode film 61 on the insulating surface 51, and have portions that cover the insulating surface 51 with the first base electrode film 61 sandwiched between them. That is, the plurality of first buried electrodes 62 each have a first buried electrode surface 66 that is exposed from the plurality of source openings 54 above the insulating surface 51. The plurality of first buried electrodes 62 have portions that face the gate electrode 32 with the first base electrode film 61 and the interlayer film 50 sandwiched between them in the stacking direction (vertical direction Z).

[0456] The multiple first buried electrodes 62 are integrated on the insulating surface 51 to form a single intermediate electrode 135. The intermediate electrode 135 (the multiple first buried electrodes 62) covers the entire area of ​​the first base electrode film 61. The electrode surface (first buried electrode surface 66) of the intermediate electrode 135 is located above the insulating surface 51.

[0457] In this embodiment, the first main electrode film 63 is mechanically and electrically connected to the first buried electrode surfaces 66 of the plurality of first buried electrodes 62 (intermediate electrodes 135) above the insulating surface 51. The first main electrode film 63 has a portion that faces the insulating surface 51 with the plurality of first buried electrodes 62 (intermediate electrodes 135) in between. In this embodiment, the first main electrode film 63 does not have a mechanical connection portion to the first base electrode film 61.

[0458] The configuration of the multiple first buried electrodes 62 (intermediate electrodes 135) according to the modified example is also applicable to the multiple first buried electrodes 62 of the source finger electrodes 68. Similarly, the configuration of the multiple first buried electrodes 62 (intermediate electrodes 135) according to the modified example is also applicable to the multiple second buried electrodes 72 of the gate finger electrodes 70.

[0459] 19 is a cross-sectional view showing a second modified example of the source pad electrode 60. In FIG. 19, a configuration in which the source pad electrode 60 according to the modified example is applied to the semiconductor device 1A is illustrated. Of course, the field region 42 according to the modified example can also be applied to the semiconductor device 1B.

[0460] In the above-described embodiments, the source pad electrode 60 has a plurality of first buried electrodes 62. However, the source pad electrode 60 does not necessarily have to have the first buried electrodes 62. In this case, the first main electrode film 63 of the source pad electrode 60 extends from above the interlayer film 50 into the plurality of source openings 54 and is electrically connected to the body region 13 and the like within the plurality of source openings 54.

[0461] Similarly, the source finger electrodes 68 do not necessarily have to have the first buried electrodes 62. In this case, the first main electrode films 63 of the source finger electrodes 68 extend from above the interlayer film 50 into the outer openings 56, and are electrically connected to the termination region 40 (overlap region 41) within the outer openings 56.

[0462] Similarly, the gate finger electrode 70 does not necessarily have to have the second buried electrode 72. In this case, the second main electrode film 73 of the gate finger electrode 70 penetrates into the multiple gate openings 58 from above the interlayer film 50 and is electrically connected to the gate wiring 44 within the multiple gate openings 58.

[0463] The semiconductor devices 1A and 1B may have the first buried electrodes 62 associated with the source pad electrodes 60, but may not have the first buried electrodes 62 associated with the source finger electrodes 68. The semiconductor devices 1A and 1B may have the first buried electrodes 62 associated with the source finger electrodes 68, but may not have the first buried electrodes 62 associated with the source pad electrodes 60.

[0464] The semiconductor devices 1A and 1B may have the first buried electrode 62 associated with the source pad electrode 60 but may not have the second buried electrode 72. The semiconductor devices 1A and 1B may have the second buried electrode 72 but may not have the first buried electrode 62 associated with the source pad electrode 60. The semiconductor devices 1A and 1B may have the first buried electrode 62 associated with the source finger electrodes 68 but may not have the second buried electrode 72. The semiconductor devices 1A and 1B may have the second buried electrode 72 but may not have the first buried electrode 62 associated with the source finger electrodes 68.

[0465] The above-described embodiments (including variations) may be implemented in other forms. For example, the above-described embodiments may employ a configuration in which the relationship between the a-axis direction and the m-axis direction is interchanged. A specific configuration in this case can be obtained by interchangeably positioning the "a-axis direction (off-direction)" and the "m-axis direction (direction perpendicular to the off-direction)" in the above description and accompanying drawings.

[0466] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of an “n-type” semiconductor region is inverted to “p-type” and the conductivity type of a “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0467] In the above-described embodiments, the chip 2 includes a SiC single crystal. However, the chip 2 may include a wide bandgap semiconductor single crystal other than a SiC single crystal. A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of silicon. Examples of wide bandgap semiconductor single crystals include gallium nitride, gallium oxide, and diamond. Of course, the chip 2 may also include a silicon single crystal.

[0468] Similarly, the first semiconductor layer 6 may include a single crystal of a wide bandgap semiconductor other than a SiC single crystal. The first semiconductor layer 6 may include gallium nitride, gallium oxide, diamond, etc. Of course, the first semiconductor layer 6 may also include a silicon single crystal.

[0469] Similarly, the second semiconductor layer 7 may contain a single crystal of a wide bandgap semiconductor other than a SiC single crystal. The second semiconductor layer 7 may contain gallium nitride, gallium oxide, diamond, etc. Of course, the second semiconductor layer 7 may also contain a silicon single crystal.

[0470] In the above-described embodiments, an n-type drain region 10 is shown. However, a p-type collector region (10) may be adopted instead of the n-type drain region 10. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, in the above description, the "source" of the MISFET structure is replaced with the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced with the "collector" of the IGBT structure. The p-type collector region (10) may be an impurity region containing p-type impurities implanted into the surface layer of the second main surface 4 of the n-type chip 2 (n-type chip 2) by ion implantation.

[0471] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the above-mentioned embodiments. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," "semiconductor rectifier device," etc., as necessary.

[0472] [A1] A semiconductor device (1A, 1B) including: a chip (2) having a main surface (3); a drift region (11) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3); and a body region (13) of a second conductivity type (p-type) formed in a tapered shape in the surface layer portion of the drift region (11) so that its horizontal width (WB) decreases in the thickness direction, and having a peripheral portion inclined obliquely with respect to the main surface (3).

[0473] [A2] The semiconductor device (1A, 1B) according to A1, wherein the chip (2) includes a SiC single crystal.

[0474] [A3] The semiconductor device (1A, 1B) described in A1 or A2, wherein the body region (13) is formed so that the width (WB) decreases in the thickness direction starting from the upper end on the main surface (3) side, and has the peripheral portion inclined obliquely starting from the upper end.

[0475] [A4] The semiconductor device (1A, 1B) described in A3, wherein the body region (13) has a thickness (TB) of 0.5 μm or more, and has a gradient (GB) in which the horizontal change in the peripheral portion at a thickness position of 0.5 μm is 0.05 μm or more when the upper end of the peripheral portion is taken as a reference position.

[0476] [A5] The semiconductor device (1A, 1B) according to any one of A1 to A4, wherein the body region (13) has a concentration gradient that gradually decreases in the thickness direction.

[0477] [A6] The semiconductor device (1A, 1B) described in any one of A1 to A5, wherein the body region (13) has, in the horizontal direction, an inner high concentration region (24) and a peripheral low concentration region (25), and has a concentration gradient that gradually decreases from the high concentration region (24) toward the low concentration region (25).

[0478] [A7] The semiconductor device (1A, 1B) described in A6, wherein the high concentration region (24) has a portion formed below the intermediate portion of the body region (13), and the low concentration region (25) has a portion formed below the intermediate portion of the body region (13).

[0479] [A8] The semiconductor device (1A, 1B) according to A7, wherein the concentration difference between the high concentration region (24) and the low concentration region (25) gradually decreases toward the bottom of the body region (13).

[0480] [A9] A semiconductor device (1A, 1B) described in any one of A1 to A8, wherein the peripheral portion of the body region (13) has a plurality of bulge portions (19) extending in the horizontal direction in multiple stages along the thickness direction.

[0481] [A10] The semiconductor device (1A, 1B) according to any one of A1 to A9, further including: a plurality of body regions (13) formed at intervals in a surface layer portion of the drift region (11); and a first conductivity type (n-type) surface drift region (27) partitioned into regions between the plurality of body regions (13) in the surface layer portion of the drift region (11) so that the horizontal width (WD) increases in the thickness direction, and forming a JFET structure with the plurality of body regions (13).

[0482] [A11] The semiconductor device (1A, 1B) according to any one of A1 to A10, further including: a first conductivity type (n-type) impurity region (16, 17) formed in a surface layer portion of the body region (13) and having an impurity concentration higher than the impurity concentration of the drift region (11); and a second conductivity type (p-type) contact region (18) formed in a surface layer portion of the body region (13) and having an impurity concentration higher than the impurity concentration of the body region (13).

[0483] [A12] A semiconductor device (1A, 1B) according to any one of A1 to A11, including a column region (130) of a second conductivity type (p-type) formed in the drift region (11) in a thickness range below the body region (13).

[0484] [A13] A semiconductor device (1A, 1B) including: a chip (2) having a main surface (3); a drift region (11) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3); a body region (13) of a second conductivity type (p-type) formed in a surface layer portion of the drift region (11); and a contact region (18) of the second conductivity type (p-type) formed in a surface layer portion of the body region (13) and having an impurity concentration higher than the impurity concentration of the body region (13), wherein the body region (13) includes a high concentration region (24) formed in a thickness range below the contact region (18), and a low concentration region (25) formed in a region on the peripheral side of the high concentration region (24) within the thickness range.

[0485] [A14] A semiconductor device (1A, 1B) according to A13, wherein the high concentration region (24) has an impurity concentration lower than the impurity concentration of the contact region (18), and the low concentration region (25) has an impurity concentration lower than the impurity concentration of the high concentration region (24).

[0486] [A15] The semiconductor device (1A, 1B) according to A13 or A14, wherein the body region (13) has a peripheral portion inclined obliquely with respect to the main surface (3).

[0487] [A16] A method for manufacturing a semiconductor device (1A, 1B), comprising the steps of: preparing a wafer (100) having a drift region (11) of a first conductivity type (n-type) in a surface layer portion of a main surface (101); and implanting impurities of a second conductivity type (p-type) into the surface layer portion of the drift region (11) so that the horizontal implantation range decreases in the thickness direction, thereby forming a body region (13) of the second conductivity type (p-type) having a peripheral portion inclined obliquely with respect to the main surface (101).

[0488] [A17] A method for manufacturing a semiconductor device (1A, 1B) according to A16, wherein the step of forming the body region (13) includes a step of implanting the impurity into a surface layer portion of the drift region (11) by oblique ion implantation.

[0489] [A18] A method for manufacturing a semiconductor device (1A, 1B) according to A17, wherein the step of forming the body region (13) includes a step of implanting the impurity in multiple stages at different depth positions in the surface layer of the drift region (11) at different implantation angles.

[0490] [A19] A method for manufacturing a semiconductor device (1A, 1B) according to any one of A16 to A18, further comprising the step of forming a mask (111) having an opening (112) on the main surface (101), and the step of forming the body region (13) comprises the step of injecting the impurity into a surface layer portion of the drift region (11) through the opening (112) of the mask (111).

[0491] [A20] A method for manufacturing a semiconductor device (1A, 1B) according to A19, wherein the step of forming the body region (13) includes a step of injecting the impurity into a region of the surface layer of the drift region (11) directly below the mask (111).

[0492] Although specific embodiments have been described in detail above, these are merely examples that clarify the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification, the order of the embodiment examples, the order of the modified examples, etc.

[0493] 1A Semiconductor device 1B Semiconductor device 2 Chip 3 First main surface 11 Drift region 13 Body region 16 First source region 17 Second source region 18 Contact region 19 Bulging portion 24 Highly doped region 25 Lowly doped region 27 Surface drift region 100 Wafer 101 First wafer main surface 111 First mask 112 Opening 130 Column region GB Body gradient TB Body thickness WB Body width WD Drift width

Claims

1. a chip having a major surface; a first conductivity type drift region formed in a surface layer portion of the main surface; a body region of a second conductivity type formed in a tapered shape in a surface layer portion of the drift region so that its horizontal width decreases in a thickness direction, and having a peripheral portion inclined obliquely with respect to the main surface.

2. The semiconductor device according to claim 1 , wherein the chip includes a SiC single crystal.

3. 2. The semiconductor device according to claim 1, wherein the body region is formed so that the width thereof decreases in the thickness direction from an upper end portion on the main surface side, and the peripheral edge portion is inclined obliquely from the upper end portion.

4. 4. The semiconductor device according to claim 3, wherein the body region has a thickness of 0.5 μm or more, and when the upper end of the peripheral edge portion is taken as a reference position, the peripheral edge portion has a gradient such that a change in the horizontal direction at a thickness position of 0.5 μm is 0.05 μm or more.

5. 2. The semiconductor device according to claim 1, wherein said body region has a concentration gradient that gradually decreases in said thickness direction.

6. 2. The semiconductor device according to claim 1, wherein the body region has a high concentration region on an inner side and a low concentration region on a peripheral side in the horizontal direction, and has a concentration gradient that gradually decreases from the high concentration region toward the low concentration region.

7. the high concentration region has a portion formed below a middle portion of the body region, 7. The semiconductor device according to claim 6, wherein said low concentration region has a portion formed below said intermediate portion of said body region.

8. the high-concentration region has a concentration gradient that gradually decreases in the thickness direction, 7. The semiconductor device according to claim 6, wherein said low concentration region has a concentration gradient that gradually decreases in said thickness direction.

9. 2. The semiconductor device according to claim 1, wherein said peripheral edge of said body region has a plurality of bulging portions extending in said horizontal direction and arranged in multiple steps along said thickness direction.

10. a plurality of the body regions formed at intervals on a surface layer portion of the drift region; 10. The semiconductor device according to claim 1, further comprising: a first conductivity type surface drift region that is partitioned into regions between the plurality of body regions so that the horizontal width increases in the thickness direction in a surface layer portion of the drift region, and that forms a JFET structure together with the plurality of body regions.

11. an impurity region of a first conductivity type formed in a surface layer portion of the body region and having an impurity concentration higher than an impurity concentration of the drift region; 10. The semiconductor device according to claim 1, further comprising: a second conductivity type contact region formed in a surface layer portion of the body region and having an impurity concentration higher than an impurity concentration of the body region.

12. 10. The semiconductor device according to claim 1, further comprising a column region of the second conductivity type formed in the drift region within a thickness range below the body region.

13. a chip having a major surface; a first conductivity type drift region formed in a surface layer portion of the main surface; a body region of a second conductivity type formed in a surface layer portion of the drift region; a second conductivity type contact region formed in a surface layer portion of the body region and having an impurity concentration higher than an impurity concentration of the body region; The semiconductor device, wherein the body region includes a high concentration region formed in a thickness range below the contact region, and a low concentration region formed in a region on the peripheral side of the high concentration region within the thickness range.

14. the high concentration region has an impurity concentration lower than the impurity concentration of the contact region; 14. The semiconductor device according to claim 13, wherein said low concentration region has an impurity concentration lower than an impurity concentration of said high concentration region.

15. 15. The semiconductor device according to claim 13, wherein said body region has a peripheral edge portion inclined obliquely with respect to said main surface.

16. preparing a wafer having a first conductivity type drift region in a surface layer portion of a main surface; and implanting impurities of a second conductivity type into a surface layer portion of the drift region so that a horizontal implantation range decreases in a thickness direction, thereby forming a body region of the second conductivity type having a peripheral portion inclined obliquely with respect to the main surface.

17. 17. The method for manufacturing a semiconductor device according to claim 16, wherein said forming said body region includes the step of implanting said impurity into a surface layer portion of said drift region by oblique ion implantation.

18. 18. The method for manufacturing a semiconductor device according to claim 17, wherein the step of forming the body region includes the step of implanting the impurity into different depth positions of the surface layer portion of the drift region in multiple stages at different implantation angles.

19. forming a mask having an opening on the major surface; 19. The method for manufacturing a semiconductor device according to claim 16, wherein the step of forming the body region includes the step of implanting the impurity into a surface layer portion of the drift region through the opening of the mask.

20. 20. The method for manufacturing a semiconductor device according to claim 19, wherein the step of forming the body region includes the step of implanting the impurity into a region of a surface layer portion of the drift region directly below the mask.