Semiconductor device

Abstract

This semiconductor device comprises: one and the other wire groups spaced apart from each other in a first direction X, and each including a plurality of first lower wires and a plurality of second lower wires which are arrayed in stripes extending in the first direction X; a first pad wire disposed on the one and the other wire groups, and electrically connected to at least one of the first lower wires of each wire group; and a second pad wire disposed on the one and the other wire groups, and spaced apart from the first pad wire in a second direction Y intersecting the first direction X, the second pad wire being electrically connected to at least one of the second lower wires of each wire group.

Description

Semiconductor Devices

[0001] This application claims priority based on Patent Application No. 2023-056610 filed with the Japan Patent Office on March 30, 2023, Patent Application No. 2023-056611 filed with the Japan Patent Office on March 30, 2023, Patent Application No. 2023-056612 filed with the Japan Patent Office on March 30, 2023, and Patent Application No. 2023-056613 filed with the Japan Patent Office on March 30, 2023, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD This disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US2008 / 0093638A1) discloses a semiconductor device including a source pad electrode, a drain pad electrode, and multiple source and drain electrodes arranged two-dimensionally on the same insulating film. The multiple source electrodes are extended from the source pad electrode onto the insulating film in a comb-like shape and electrically connected to a source region through the insulating film.

[0003] The plurality of drain electrodes are extended from the drain pad electrode onto the insulating film in a comb-like shape that meshes with the plurality of source electrodes, and are electrically connected to the drain region through the insulating film. This semiconductor device has a relatively long wiring distance and a relatively high wiring resistance between the source pad electrode and the drain pad electrode.

[0004] US Patent Application Publication No. 2008 / 0093638

[0005] The present disclosure provides a semiconductor device having a novel wiring layout.

[0006] [Summary] The present disclosure provides a semiconductor device including: a wiring group including a plurality of first lower wirings and a plurality of second lower wirings arranged in stripes extending in a first direction X; a first pad wiring arranged on at least one of the first lower wirings; a second pad wiring arranged on at least one of the second lower wirings at a distance from the first pad wiring in a second direction Y intersecting the first direction X; at least one first outgoing wiring drawn from the first pad wiring in the second direction Y and electrically connected to at least one of the first lower wirings in a region between the first pad wiring and the second pad wiring; and at least one second outgoing wiring drawn from the second pad wiring in the second direction Y and electrically connected to at least one of the second lower wirings in a region between the first pad wiring and the second pad wiring.

[0007] The present disclosure provides a semiconductor device including: one and other wiring groups arranged at an interval in a first direction X, the one and other wiring groups including a plurality of first lower wirings and a plurality of second lower wirings arranged in stripes extending in the first direction X; a first pad wiring arranged on the one and other wiring groups and electrically connected to at least one of the first lower wirings of each of the wiring groups; and a second pad wiring arranged on the one and other wiring groups at an interval from the first pad wiring in a second direction Y intersecting the first direction X, and electrically connected to at least one of the second lower wirings of each of the wiring groups.

[0008] The present disclosure provides a semiconductor device including one and another wiring groups arranged at a distance from each other, the one and other wiring groups each including a plurality of first lower wirings and a plurality of second lower wirings; an inter-wiring area partitioned between the one and other wiring groups; a first pad wiring arranged on the inter-wiring area; a second pad wiring arranged on the inter-wiring area and spaced apart from the first pad wiring; a first outgoing wiring drawn from the first pad wiring to an area outside the inter-wiring area and electrically connected to the first lower wiring of one of the wiring groups; and a second outgoing wiring drawn from the second pad wiring to an area outside the inter-wiring area so as to face the first outgoing wiring across the inter-wiring area and electrically connected to the second lower wiring of the other of the wiring groups.

[0009] The present disclosure provides a semiconductor device including: a plurality of wiring groups arranged at intervals in a first direction X, each of the wiring groups including a plurality of first lower wirings and a plurality of second lower wirings; an inter-wiring region partitioned into a strip shape extending in a second direction Y intersecting the first direction X between the plurality of wiring groups; an intermediate wiring arranged in the inter-wiring region and electrically isolated from the plurality of wiring groups; and an intermediate pad wiring arranged on the intermediate wiring, electrically isolated from the plurality of wiring groups, and electrically connected to the intermediate wiring.

[0010] The present disclosure provides a semiconductor device including a chip, a plurality of active regions formed in the chip at intervals in a first direction X, a strip-shaped boundary region formed between the plurality of active regions in the chip and extending in a second direction Y intersecting the first direction X, an intermediate wiring arranged on the boundary region, and an intermediate pad wiring arranged on the intermediate wiring and electrically connected to the intermediate wiring.

[0011] the first pad wiring disposed on at least one of the first lower wirings; a second pad wiring disposed on at least one of the second lower wirings at a distance from the first pad wiring in a second direction Y intersecting the first direction X; an inter-pad region defined between the first pad wiring and the second pad wiring; a first side wiring drawn from the first pad wiring to a region facing the inter-pad region on one side in the first direction X and electrically connected to at least one of the first lower wirings passing through the inter-pad region; and a second side wiring drawn from the second pad wiring to a region facing the inter-pad region on one side in the first direction X and electrically connected to at least one of the second lower wirings passing through the inter-pad region.

[0012] The present disclosure provides a semiconductor device including: a chip having a first main surface on one side and a second main surface on the other side; a base layer of a first conductivity type formed within the chip on the second main surface side; a drift layer of a second conductivity type formed within the chip on the first main surface side; a plurality of trench electrode type gate structures formed on the first main surface so as to be positioned within the drift layer; a plurality of drain source regions of the second conductivity type formed in regions between the plurality of gate structures in a surface layer portion of the drift layer; and a plurality of impurity regions of the first conductivity type formed in regions along lower ends of the plurality of gate structures.

[0013] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0014] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example layout of a first main surface. FIG. 4 is an enlarged plan view showing a main portion of the first main surface. FIG. 5 is an enlarged plan view showing a main portion of the first main surface. FIG. 6 is an enlarged plan view showing a main portion of the first main surface. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5 . FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5 . FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 5 . FIG. 10 is a cross-sectional view taken along line XX in FIG. 5 . FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 6 . FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 6 . FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 6 . FIG. 14 is a plan view showing an example layout of first-layer wiring. FIG. 15 is a plan view showing an example layout of second-layer wiring. FIG. 16A is an enlarged plan view showing a first wiring unit according to a first example. FIG. 16B is an enlarged plan view showing a first wiring unit according to a second example. FIG. 16C is an enlarged plan view showing a first wiring unit according to a third example. FIG. 16D is an enlarged plan view showing a first wiring unit according to a fourth example. FIG. 16E is an enlarged plan view showing a first wiring unit according to a fifth example. FIG. 16F is an enlarged plan view showing a first wiring unit according to a sixth example. FIG. 16G is an enlarged plan view showing a first wiring unit according to a seventh example. FIG. 16H is an enlarged plan view showing a first wiring unit according to an eighth example. FIG. 16I is an enlarged plan view showing a first wiring unit according to a ninth example. FIG. 16J is an enlarged plan view showing a first wiring unit according to a tenth example. FIG. 17A is an enlarged plan view showing a second wiring unit according to the first example. FIG. 17B is an enlarged plan view showing a second wiring unit according to the second example. Fig. 17C is an enlarged plan view showing a second wiring unit according to a third example. Fig. 18 is an enlarged plan view showing an example of a third wiring unit. Fig. 19 is an enlarged plan view showing an example of a fourth wiring unit. Fig. 20 is an enlarged plan view showing a first wiring unit of a semiconductor device according to a second embodiment. Fig. 21 is an enlarged plan view showing a main part of the first wiring unit shown in Fig. 20. Fig. 22 is a plan view showing a first layout example of second layer wiring of a semiconductor device according to a third embodiment.FIG. 23 is a plan view showing a second layout example of the second-layer wiring shown in FIG. 22. FIG. 24 is an enlarged plan view showing a main portion of the second-layer wiring shown in FIG. 23. FIG. 25 is an enlarged plan view showing a main portion of the second-layer wiring shown in FIG. 23. FIG. 26 is an enlarged plan view showing a main portion of the second-layer wiring shown in FIG. 23. FIG. 27 is an enlarged plan view showing a main portion of the second-layer wiring shown in FIG. 23. FIG. 28 is a plan view showing a first modified example of the semiconductor device according to the first to third embodiments. FIG. 29 is an enlarged plan view showing a main portion of the second-layer wiring. FIG. 30 is a plan view showing a second modified example of the semiconductor device according to the first to third embodiments. FIG. 31 is a plan view showing a semiconductor device according to the fourth embodiment. FIG. 32 is a cross-sectional view taken along line XXXII-XXXII shown in FIG. 31. FIG. 33 is a plan view showing a layout example of the first main surface. FIG. 34 is an enlarged plan view showing a main portion of the first main surface. FIG. 35 is an enlarged plan view showing a main portion of the first main surface. FIG. 36 is a cross-sectional view taken along line XXXVI-XXXVI shown in FIG. 35 . FIG. 37 is a cross-sectional view taken along line XXXVII-XXXVII shown in FIG. 35 . FIG. 38 is a cross-sectional view taken along line XXXVIII-XXXVIII shown in FIG. 35 . FIG. 39 is a cross-sectional view taken along line XXXIX-XXXIX shown in FIG. 35 . FIG. 40 is a plan view showing an example layout of first-layer wiring. FIG. 41 is a plan view showing an example layout of second-layer wiring. FIG. 42A is an enlarged plan view showing a first wiring unit according to a first example. FIG. 42B is an enlarged plan view showing a first wiring unit according to a second example. FIG. 42C is an enlarged plan view showing a first wiring unit according to a third example. FIG. 42D is an enlarged plan view showing a first wiring unit according to a fourth example. FIG. 42E is an enlarged plan view showing a first wiring unit according to a fifth example. FIG. 42F is an enlarged plan view showing a first wiring unit according to a sixth example. Fig. 42G is an enlarged plan view showing a first wiring unit according to a seventh example. Fig. 42H is an enlarged plan view showing a first wiring unit according to an eighth example. Fig. 42I is an enlarged plan view showing a first wiring unit according to a ninth example. Fig. 42J is an enlarged plan view showing a first wiring unit according to a tenth example. Fig. 43A is an enlarged plan view showing a second wiring unit according to a first example. Fig. 43B is an enlarged plan view showing a second wiring unit according to a second example. Fig. 43C is an enlarged plan view showing a second wiring unit according to a third example.Fig. 44 is an enlarged plan view showing an example of a third wiring unit, Fig. 45 is an enlarged plan view showing an example of a fourth wiring unit, and Fig. 46 is a plan view showing a modification of the semiconductor device in accordance with the fourth embodiment.

[0015] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0016] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0017] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0018] Fig. 1 is a plan view showing a semiconductor device 1A according to a first embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a first main surface 3. Fig. 4 is an enlarged plan view showing a main portion of the first main surface 3. Fig. 5 is an enlarged plan view showing a main portion of the first main surface 3 (a main portion different from Fig. 4). Fig. 6 is an enlarged plan view showing a main portion of the first main surface 3 (a main portion different from Figs. 4 and 5).

[0019] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 5. FIG. 10 is a cross-sectional view taken along line XX in FIG. 5. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 6. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 6. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 6. FIG. 14 is a plan view showing an example layout of first-layer wiring 74. FIG. 15 is a plan view showing an example layout of second-layer wiring 75.

[0020] The semiconductor device 1A is a semiconductor switching device having a lateral drain-source common transistor structure Tr (field effect transistor) as an example of a device structure. With reference to FIGS. 1 to 15 , the semiconductor device 1A includes a chip 2 having a hexahedral shape (specifically, a rectangular parallelepiped shape). The chip 2 may also be referred to as a "semiconductor chip." In this embodiment, the chip 2 has a single-layer structure made of a silicon single crystal substrate (semiconductor substrate).

[0021] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the chip 2.

[0022] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X. In the following description, one side of the first direction X refers to the third side surface 5C side, and the other side of the first direction X refers to the fourth side surface 5D side. Furthermore, one side of the second direction Y refers to the first side surface 5A side, and the other side of the second direction Y refers to the second side surface 5B side.

[0023] The semiconductor device 1A includes a plurality of (six in this embodiment) active regions 6 provided on the first main surface 3 at intervals in the first direction X. The plurality of active regions 6 are arranged as first to sixth active regions 6A to 6F in order from the third side surface 5C side. Each of the plurality of active regions 6 is a region in which a transistor structure Tr (device structure) is formed.

[0024] The active regions 6 are provided inward of the first main surface 3 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and are each defined as a strip extending in the second direction Y. Specifically, the active regions 6 are each defined as a polygon (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The planar shape of the active regions 6 is arbitrary.

[0025] The semiconductor device 1A includes an outer region 7 provided in an area outside the active regions 6 on the first main surface 3. In this embodiment, the outer region 7 includes a plurality of boundary regions 7a and one peripheral region 7b. The boundary regions 7a are each defined as a strip extending in the second direction Y in an area between the active regions 6 adjacent in the first direction X.

[0026] The peripheral region 7b is provided in a region between the periphery of the first main surface 3 and the multiple active regions 6, and extends in a strip shape along the periphery of the first main surface 3 and the multiple active regions 6. In this embodiment, the peripheral region 7b collectively surrounds the multiple active regions 6 in a plan view and is defined in the shape of a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the chip 2. The peripheral region 7b is connected to the multiple boundary regions 7a.

[0027] The semiconductor device 1A includes a p-type base layer 8 (base region) formed inside the chip 2. The base layer 8 has a density of 1×10 １３ cm －３ 1x10 or more １６ cm －３ The base layer 8 may have the following p-type impurity concentration: A base potential is applied to the base layer 8. The base potential may be a reference potential. The reference potential is a potential that serves as a reference for circuit operation. The reference potential may be a ground potential.

[0028] Base layer 8 is formed across the entire thickness range of chip 2 in the region between first main surface 3 and second main surface 4. Base layer 8 extends in a layered form along first main surface 3 and second main surface 4, forming first main surface 3, second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, chip 2 is made of a p-type semiconductor substrate (p-type semiconductor chip), and base layer 8 is formed using p-type chip 2.

[0029] The base layer 8 may have a thickness of 1 μm or more and 800 μm or less. The thickness of the base layer 8 may have a value belonging to at least one of the ranges of 1 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, 400 μm or more and 500 μm or less, 500 μm or more and 600 μm or less, 600 μm or more and 700 μm or more and 800 μm or less.

[0030] The semiconductor device 1A includes at least one (one in this embodiment) n-type drift layer 9 (drift region) formed in the surface layer portion of the first main surface 3. In this embodiment, the drift layer 9 is an impurity region in which the conductivity type of the base layer 8 is changed from p-type to n-type by ion implantation. Of course, the drift layer 9 may also be an n-type epitaxial layer stacked on a p-type semiconductor substrate (base layer 8). The drift layer 9 has a dopant concentration of 1×10 １４ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration may be as follows:

[0031] The drift layer 9 is formed in the plurality of active regions 6 at intervals from the second main surface 4 (the bottom of the base layer 8) toward the first main surface 3, and extends in a layered form along the first main surface 3. The drift layer 9 is drawn out from the plurality of active regions 6 to the outer region 7, and has a portion located in the outer region 7. In this embodiment, the drift layer 9 is formed in the surface layer portion of the first main surface 3 over the entire area of ​​the first main surface 3, and is exposed from the first to fourth side surfaces 5A to 5D.

[0032] Of course, the drift layer 9 may be formed in the surface layer portion of the first main surface 3 at intervals inward from the first to fourth side surfaces 5A to 5D. Of course, a plurality of drift layers 9 may be formed in a one-to-one correspondence with the plurality of active regions 6. In this case, the plurality of drift layers 9 are formed at intervals in the first direction X so as to be positioned within the plurality of active regions 6, respectively, and are each formed in a strip shape extending in the second direction Y.

[0033] The depth of the drift layer 9 may be 0.1 μm or more and 10 μm or less. The depth of the drift layer 9 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The depth of the drift layer 9 is preferably 2 μm or less.

[0034] The semiconductor device 1A includes outer insulating films 10, 11 that cover the outer surfaces of the chip 2. The outer insulating films 10, 11 include a first outer insulating film 10 and a second outer insulating film 11. The outer insulating films 10, 11 do not necessarily need to include both the first outer insulating film 10 and the second outer insulating film 11 at the same time, and may consist of only one of the first outer insulating film 10 and the second outer insulating film 11. Of course, the presence or absence of the outer insulating films 10, 11 is optional, and a configuration without the outer insulating films 10, 11 may also be employed.

[0035] The first outer insulating film 10 covers the second main surface 4 in a film-like manner. That is, the first outer insulating film 10 covers the base layer 8 exposed from the second main surface 4. In this embodiment, the first outer insulating film 10 covers the entire second main surface 4, and insulates and reinforces the chip 2 from the second main surface 4 side.

[0036] The second outer insulating film 11 covers at least one of the first to fourth side surfaces 5A to 5D in a film-like manner. That is, the second outer insulating film 11 covers the base layer 8 and the drift layer 9 exposed from at least one of the first to fourth side surfaces 5A to 5D. In this embodiment, the second outer insulating film 11 covers all of the first to fourth side surfaces 5A to 5D, insulating and reinforcing the chip 2 from the first to fourth side surfaces 5A to 5D sides. The second outer insulating film 11 is continuous with the first outer insulating film 10 at the periphery of the second main surface 4.

[0037] The outer insulating films 10 and 11 may have a single layer structure or a laminated structure including either or both of an inorganic insulating film and an organic insulating film. When the outer insulating films 10 and 11 having a laminated structure are used, the outer insulating films 10 and 11 may include an inorganic insulating film and an organic insulating film laminated in this order from the chip 2 side.

[0038] For example, the inorganic insulating film may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, and for example, the organic insulating film may include at least one of a polyimide, a polyamide, a polybenzoxazole, and an epoxy resin.

[0039] The semiconductor device 1A includes a plurality of transistor structures Tr formed in a plurality of active regions 6 on the first main surface 3. The configuration of the plurality of transistor structures Tr will be specifically described below. The semiconductor device 1A includes a plurality of trench electrode type gate structures 12 (control terminals) formed on the first main surface 3 in each active region 6. The gate structures 12 may also be referred to as "trench gate structures." A gate potential (gate signal) serving as a control potential is applied to the plurality of gate structures 12.

[0040] The multiple gate structures 12 are formed in strips extending in the first direction X in each active region 6 and are arranged at intervals in the second direction Y. That is, the multiple gate structures 12 are arranged in stripes extending in the first direction X. Each of the multiple gate structures 12 has a first end on one side in the first direction X and a second end on the other side in the first direction X. The first end and the second end are drawn out from the active region 6 to the outer region 7.

[0041] In the first active region 6A, first ends of the plurality of gate structures 12 are led out to the peripheral region 7b, and second ends of the plurality of gate structures 12 are led out to the boundary region 7a. In the second to fifth active regions 6B to 6E, first ends of the plurality of gate structures 12 are led out to one boundary region 7a, and second ends of the plurality of gate structures 12 are led out to the other boundary region 7a. In the sixth active region 6F, first ends of the plurality of gate structures 12 are led out to the boundary region 7a, and second ends of the plurality of gate structures 12 are led out to the peripheral region 7b.

[0042] With respect to the plurality of active regions 6, the plurality of gate structures 12 face each other in the first direction X. That is, with respect to one active region 6 (6A, 6C, 6E) and the other active region 6 (6B, 6D, 6F), first ends of the plurality of gate structures 12 arranged in the other active region 6 face second ends of the plurality of gate structures 12 arranged in the one active region 6 in a one-to-one correspondence.

[0043] In this embodiment, the plurality of gate structures 12 are located within the drift layer 9 in a cross-sectional view. Specifically, the plurality of gate structures 12 are formed at intervals on the first main surface 3 side with respect to the depth position of the bottom of the drift layer 9, and have side walls and a bottom wall located within the drift layer 9. The plurality of gate structures 12 may be formed in a tapered shape in a cross-sectional view, with an opening width narrowing toward the bottom wall.

[0044] The plurality of gate structures 12 may penetrate the bottom of the drift layer 9 to reach the base layer 8. That is, the plurality of gate structures 12 may have a portion (side wall) located in the drift layer 9 and a portion (bottom wall) located in the base layer 8. The bottom walls of the plurality of gate structures 12 preferably have a flat portion extending substantially parallel to the first main surface 3. The bottom walls of the plurality of gate structures 12 may be curved in an arc shape toward the second main surface 4.

[0045] The spacing between the multiple gate structures 12 may be 0.1 μm or more and 5 μm or less. The spacing between the gate structures 12 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The spacing between the gate structures 12 is preferably 3 μm or less.

[0046] The width of the gate structure 12 may be 0.1 μm or more and 5 μm or less. The width of the gate structure 12 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The width of the gate structure 12 is preferably 3 μm or less.

[0047] The depth of the gate structure 12 may be 0.1 μm to 10 μm. The depth of the gate structure 12 may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, and 8 μm to 10 μm. The depth of the gate structure 12 is preferably 3 μm or less.

[0048] The configuration of one gate structure 12 will be described below. The gate structure 12 includes a trench 13, an insulating film 14, a buried electrode 15, and a buried insulator 16. The trench 13 may be referred to as a "gate trench," the insulating film 14 may be referred to as a "gate insulating film," and the buried electrode 15 may be referred to as a "gate electrode." The trench 13 is dug from the first main surface 3 toward the second main surface 4, and defines the sidewalls and bottom wall of the gate structure 12.

[0049] The insulating film 14 covers the wall surface of the trench 13 in a film-like manner. The insulating film 14 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating film 14 preferably has a single-layer structure. The insulating film 14 preferably includes a silicon oxide film made of an oxide of the chip 2.

[0050] The buried electrode 15 is buried in the trench 13 via the insulating film 14. The buried electrode 15 may include conductive polysilicon. The buried electrode 15 includes a buried portion 15a and at least one (in this embodiment, multiple) drawn-out portion 15b.

[0051] The buried portion 15a is buried in the active region 6 on the bottom wall side of the trench 13 at a distance from the first main surface 3 to the bottom wall side of the trench 13. The buried portion 15a is buried in the active region 6 on the bottom wall side of the trench 13 at a distance from the middle portion of the trench 13 to the bottom wall side of the trench 13, and preferably has an electrode surface located closer to the bottom wall side than the middle portion of the trench 13.

[0052] The multiple lead-out portions 15b include a lead-out portion 15b located at a first end of the trench 13 in the outer region 7, and a lead-out portion 15b located at a second end of the trench 13 in the outer region 7. The multiple lead-out portions 15b are led out from the bottom wall side (the buried portion 15a side) of the trench 13 to the opening side of the trench 13. The multiple lead-out portions 15b, together with the buried portion 15a, define an electrode recess 17 on the opening side of the trench 13. The electrode recess 17 extends in a strip shape in the first direction X along the trench 13.

[0053] The plurality of lead portions 15b have electrode surfaces located near the first main surface 3. The electrode surfaces of the lead portions 15b may be formed flush with the first main surface 3. The electrode surfaces of the lead portions 15b may be located closer to the bottom wall of the trench 13 than the first main surface 3. The electrode surfaces of the lead portions 15b may protrude above the first main surface 3.

[0054] The buried insulator 16 is buried on the opening side of the trench 13. Specifically, the buried insulator 16 is buried in the electrode recess 17 and covers the buried portion 15a in the trench 13. The buried insulator 16 may be buried in the trench 13 with the insulating film 14 interposed therebetween. The buried insulator 16 may be buried in the trench 13 without the insulating film 14 interposed therebetween so as to directly cover the sidewall of the trench 13. The buried insulator 16 extends in a strip shape in the first direction X in a plan view. The buried insulator 16 is provided as a field insulator that relieves the electric field with respect to the trench 13. The cross-sectional area of ​​the buried insulator 16 is preferably larger than the cross-sectional area of ​​the buried portion 15a.

[0055] The buried insulator 16 has an insulating surface located near the first main surface 3. The insulating surface may be formed flush with the first main surface 3. The insulating surface may be located on the bottom wall side of the trench 13 with respect to the first main surface 3. The insulating surface may protrude above the first main surface 3.

[0056] The buried insulator 16 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The buried insulator 16 may have a single layer structure. The buried insulator 16 may be formed of the same insulating material as the insulating film 14. In this case, the buried insulator 16 is preferably made of a vapor deposited by a chemical vapor deposition (CVD) method or the like, and has a density different from that of the insulating film 14.

[0057] The semiconductor device 1A includes a plurality of gate units GU1, GU2 in each active region 6. The plurality of gate units GU1, GU2 includes a plurality of first gate units GU1 and a plurality of second gate units GU2.

[0058] Each of the plurality of first gate units GU1 is composed of at least two (two in this embodiment) gate structures 12 adjacent to each other in the second direction Y in each active region 6. The plurality of first gate units GU1 are arranged alternately with the at least two (two in this embodiment) gate structures 12 in the second direction Y in each active region 6.

[0059] With respect to the plurality of active regions 6, the plurality of first gate units GU1 face each other in the first direction X. That is, with respect to one active region 6 (6A, 6C, 6E) and the other active region 6 (6B, 6D, 6F), the plurality of first gate units GU1 arranged in the other active region 6 face the plurality of first gate units GU1 arranged in one active region 6 in a one-to-one correspondence.

[0060] The plurality of second gate units GU2 are each composed of at least two (two in this embodiment) gate structures 12 other than the plurality of gate structures 12 constituting the plurality of first gate units GU1 among the plurality of gate structures 12 in each active region 6. The plurality of second gate units GU2 are each composed of at least two gate structures 12 adjacent to each other in the second direction Y in each active region 6. The plurality of second gate units GU2 are arranged alternately with the plurality of first gate units GU1 in the second direction Y in each active region 6.

[0061] With respect to the plurality of active regions 6, the plurality of second gate units GU2 face each other in the first direction X. That is, with respect to one active region 6 (6A, 6C, 6E) and the other active region 6 (6B, 6D, 6F), the plurality of second gate units GU2 arranged in the other active region 6 face the plurality of second gate units GU2 arranged in one active region 6 in a one-to-one correspondence.

[0062] The semiconductor device 1A includes a plurality of unit spaces US defined as regions between a plurality of first gate units GU1 and a plurality of second gate units GU2 adjacent to each other in the second direction Y in each active region 6. Each unit space US is defined as a region between one gate structure 12 of the first gate unit GU1 and one gate structure 12 of the second gate unit GU2, and includes a drift layer 9.

[0063] The semiconductor device 1A includes a plurality of trench electrode type connection structures 21, 22 formed in the outer region 7 on the first main surface 3. The plurality of connection structures 21, 22 connect at least two gate structures 12 adjacent to each other in the second direction Y. A gate potential is applied to the plurality of connection structures 21, 22. The connection structures 21, 22 may also be referred to as "gate connection structures."

[0064] The plurality of connection structures 21, 22 are connected to first ends and second ends of the plurality of gate structures 12 in the corresponding gate units GU1, GU2, respectively, so that the plurality of connection structures 21, 22, together with the corresponding plurality of gate structures 12, respectively configure a plurality of gate units GU1, GU2 in a ring or ladder shape (in this embodiment, a square ring shape).

[0065] The multiple connection structures 21, 22 include multiple first connection structures 21 arranged on the first end side of the multiple gate structures 12, and multiple second connection structures 22 arranged on the second end side of the multiple gate structures 12.

[0066] The multiple first connection structures 21 are each formed in a strip shape extending in the second direction Y, and are arranged at intervals in the second direction Y. The multiple first connection structures 21 are arranged in a line in the second direction Y. The multiple first connection structures 21 are respectively connected to first ends of the multiple gate structures 12 to be unitized (grouped). In this embodiment, the multiple first connection structures 21 respectively connect the first ends of a pair of gate structures 12 adjacent in the second direction Y.

[0067] The multiple second connection structures 22 are each formed in a strip shape extending in the second direction Y and are arranged at intervals in the second direction Y. The multiple second connection structures 22 are arranged in a line in the second direction Y. The multiple second connection structures 22 are respectively connected to second ends of the multiple gate structures 12 that are united (grouped) by the first connection structure 21. In this embodiment, the multiple second connection structures 22 are respectively connected to second ends of pairs of gate structures 12 adjacent to each other in the second direction Y.

[0068] With respect to the first active region 6A, the multiple first connection structures 21 are respectively connected to the first ends of the multiple gate structures 12 adjacent in the second direction Y in the peripheral region 7b, and the multiple second connection structures 22 are respectively connected to the second ends of the multiple gate structures 12 unitized by the first connection structures 21 in the boundary region 7a.

[0069] With respect to the second to fifth active regions 6B to 6E, the multiple first connection structures 21 are respectively connected to the first ends of the multiple gate structures 12 adjacent in the second direction Y in one boundary region 7a, and the multiple second connection structures 22 are respectively connected to the second ends of the multiple gate structures 12 unitized by the first connection structures 21 in the other boundary region 7a.

[0070] With respect to the sixth active region 6F, the plurality of first connection structures 21 are connected in the boundary region 7a to first ends of the plurality of gate structures 12 adjacent to each other in the second direction Y, and the plurality of second connection structures 22 are connected in the peripheral region 7b to second ends of the plurality of gate structures 12 united by the first connection structures 21. In each boundary region 7a, the plurality of second connection structures 22 are formed at intervals from the plurality of first connection structures 21 in the first direction X, and face the plurality of first connection structures 21 in a one-to-one correspondence in the first direction X.

[0071] In this embodiment, the multiple connection structures 21, 22 are located within the drift layer 9 in a cross-sectional view. Specifically, the multiple connection structures 21, 22 are formed at intervals on the first main surface 3 side with respect to the depth position of the bottom of the drift layer 9, and have side walls and a bottom wall located within the drift layer 9. The multiple connection structures 21, 22 may be formed in a tapered shape in a cross-sectional view, with an opening width narrowing toward the bottom wall.

[0072] The plurality of connection structures 21, 22 may penetrate the bottom of the drift layer 9 to reach the base layer 8 and have a bottom wall located within the base layer 8. That is, the plurality of connection structures 21, 22 may have a portion (side wall) located within the drift layer 9 and a portion (bottom wall) located within the base layer 8. The bottom walls of the plurality of connection structures 21, 22 preferably have a flat portion extending substantially parallel to the first main surface 3. Of course, the bottom walls of the plurality of connection structures 21, 22 may be curved in an arc shape toward the second main surface 4.

[0073] In this embodiment, the width of the connection structures 21, 22 is greater than the width of the gate structure 12. The width of the connection structures 21, 22 may be approximately equal to the width of the gate structure 12. The width of the connection structures 21, 22 may be less than the width of the gate structure 12.

[0074] The width of the connection structures 21, 22 may be 0.1 μm or more and 5 μm or less. The width of the connection structures 21, 22 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or more, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or more, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0075] In this embodiment, the depth of the connection structures 21, 22 is greater than the depth of the gate structure 12. The depth of the connection structures 21, 22 may be approximately equal to the depth of the gate structure 12. The depth of the connection structures 21, 22 may be less than the depth of the gate structure 12.

[0076] The depth of the connection structures 21, 22 may be 0.1 μm or more and 10 μm or less. The depth of the connection structures 21, 22 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less.

[0077] The following describes the configuration of one of the connection structures 21, 22. The connection structures 21, 22 include a connection trench 23, a connection insulating film 24, and a connection electrode 25. The connection trench 23 is dug from the first main surface 3 toward the second main surface 4, and defines the sidewalls and bottom walls of the connection structures 21, 22. The connection trench 23 is connected to multiple trenches 13 adjacent to each other in the second direction Y.

[0078] The connection insulating film 24 coats the wall surface of the connection trench 23 in a film-like manner. The connection insulating film 24 is connected to the insulating film 14 and the buried insulator 16 at the communicating portion between the trench 13 and the connection trench 23. The connection insulating film 24 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The connection insulating film 24 preferably has a single-layer structure. The connection insulating film 24 preferably includes a silicon oxide film made of an oxide of the chip 2. The connection insulating film 24 is preferably formed of the same insulating material as the insulating film 14.

[0079] The connection electrode 25 is buried in the connection trench 23 via the connection insulating film 24. The connection electrode 25 may contain conductive polysilicon. The connection electrode 25 is formed in a strip shape extending in the second direction Y in a plan view, and is connected to the buried electrode 15 at the communicating portion between the trench 13 and the connection trench 23.

[0080] The connection electrode 25 may be regarded as a portion of the buried electrode 15 (the lead-out portion 15b) that is led out into the connection trench 23. The connection portion of the buried electrode 15 and the connection electrode 25 may be regarded as one component of the gate structure 12, or may be regarded as one component of the connection structures 21 and 22.

[0081] The connection electrode 25 has an electrode surface located near the first main surface 3. The electrode surface of the connection electrode 25 may be formed flush with the first main surface 3. The electrode surface of the connection electrode 25 may be located closer to the bottom wall of the connection trench 23 than the first main surface 3. The electrode surface of the connection electrode 25 may protrude above the first main surface 3. It is preferable that the plane area of ​​the electrode surface of the connection electrode 25 is larger than the plane area of ​​the electrode surface of the embedded portion 15a.

[0082] The semiconductor device 1A includes a plurality of mesas 26, 27 that are respectively partitioned into a plurality of active regions 6 on the first main surface 3. The plurality of mesas 26, 27 are respectively partitioned by a plurality of gate units GU1, GU2. That is, each mesa 26, 27 is formed by a portion surrounded by a plurality of gate structures 12 and a plurality of connecting structures 21, 22. The plurality of mesas 26, 27 each extend in a strip shape in the first direction X and are partitioned at intervals in the second direction Y. That is, the plurality of mesas 26, 27 are partitioned in stripes extending in the first direction X.

[0083] The multiple mesas 26, 27 include multiple first mesas 26 and multiple second mesas 27. The multiple first mesas 26 are each defined by the multiple first gate units GU1, and are regions (first application terminals) to which a first drain-source potential is applied as a first potential (high potential).

[0084] With respect to the plurality of active regions 6, the plurality of first mesas 26 face each other in the first direction X. That is, with respect to one active region 6 (6A, 6C, 6E) and the other active region 6 (6B, 6D, 6F), the plurality of first mesas 26 defined in the other active region 6 face the plurality of first mesas 26 defined in the one active region 6 in a one-to-one correspondence.

[0085] The second mesa portions 27 are each defined by the second gate units GU2 and are regions (second application terminals) to which a second drain-source potential is applied as a second potential (lower potential) different from the first potential. That is, the second mesa portions 27 are defined alternately with the first mesa portions 26 in the second direction Y via the unit spaces US. The second drain-source potential may be the same as the base potential or may be a potential different from the base potential.

[0086] With respect to the plurality of active regions 6, the plurality of second mesas 27 face each other in the first direction X. That is, with respect to one active region 6 (6A, 6C, 6E) and the other active region 6 (6B, 6D, 6F), the plurality of second mesas 27 defined in the other active region 6 face the plurality of second mesas 27 defined in the one active region 6 in a one-to-one correspondence.

[0087] The semiconductor device 1A includes a plurality of n-type drain source regions 28, 29 formed in a surface layer portion of the first main surface 3 (drift layer 9) in each active region 6. The plurality of drain source regions 28, 29 are formed in a plurality of mesa portions 26, 27. That is, the plurality of drain source regions 28, 29 are formed in regions between a plurality of gate structures 12 in the corresponding gate units GU1, GU2, respectively. The plurality of drain source regions 28, 29 have an n-type impurity concentration higher than the n-type impurity concentration of the drift layer 9. The n-type impurity concentration of the plurality of drain source regions 28, 29 is 1×10 １６ cm －３ 1x10 or more ２１ cm －３ It may be the following:

[0088] The plurality of drain source regions 28, 29 include a plurality of first drain source regions 28 and a plurality of second drain source regions 29. The plurality of first drain source regions 28 are regions (first application ends) to which a first drain source potential is applied, and are formed in strip shapes extending in the first direction X in the plurality of first mesas 26.

[0089] With respect to the plurality of active regions 6, the plurality of first drain source regions 28 face each other in the first direction X. That is, with respect to one active region 6 (6A, 6C, 6E) and the other active region 6 (6B, 6D, 6F), the plurality of first drain source regions 28 arranged in the other active region 6 face the plurality of first drain source regions 28 arranged in one active region 6 in a one-to-one correspondence.

[0090] The second drain source regions 29 are regions (second application ends) to which the second drain source potential is applied, and are formed in stripes extending in the first direction X in the second mesas 27. That is, the second drain source regions 29 are formed alternately with the first drain source regions 28 in the second direction Y. The drain source regions 28, 29 are also arranged in stripes extending in the first direction X.

[0091] With respect to the plurality of active regions 6, the plurality of second drain source regions 29 face each other in the first direction X. That is, with respect to one active region 6 (6A, 6C, 6E) and the other active region 6 (6B, 6D, 6F), the plurality of second drain source regions 29 arranged in the other active region 6 face the plurality of second drain source regions 29 arranged in one active region 6 in a one-to-one correspondence.

[0092] The following describes the configuration of one drain source region 28, 29. The drain source region 28, 29 is formed at a distance from the bottom walls of the plurality of gate structures 12 toward the first main surface 3, and faces the base layer 8 across a part of the drift layer 9. Specifically, the drain source region 28, 29 is formed at a distance from the depth positions of the electrode surfaces of the plurality of buried electrodes 15 toward the first main surface 3, and faces the plurality of buried insulators 16 in the horizontal direction along the first main surface 3.

[0093] Such a configuration is effective in suppressing a decrease in breakdown voltage caused by a voltage drop between the gate structure 12 and the drain source regions 28, 29. The drain source regions 28, 29 may be in contact with multiple gate structures 12. That is, the drain source regions 28, 29 may be in contact with portions of the multiple gate structures 12 where the buried insulator 16 is disposed.

[0094] The drain source regions 28, 29 are formed at intervals in the first direction X from the first ends and second ends of the plurality of gate structures 12, and do not contact the portions of the plurality of gate structures 12 where the drawn-out portions 15b are arranged. In other words, the drain source regions 28, 29 are formed at intervals in the first direction X from the plurality of connection structures 21, 22 located on both sides. This configuration is effective in suppressing a decrease in breakdown voltage caused by a voltage drop between the ends (connection structures 21, 22) of the gate structure 12 and the drain source regions 28, 29.

[0095] The drain source regions 28, 29 are preferably formed with a region spacing of 0.1 μm to 2 μm from the end (connection structures 21, 22) of the gate structure 12. The region spacing may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm.

[0096] The semiconductor device 1A includes a plurality of trench electrode type isolation structures 31, 32 formed in each active region 6 on the first main surface 3. A gate potential is applied to the plurality of isolation structures 31, 32. The isolation structures 31, 32 may also be referred to as "gate isolation structures." The plurality of isolation structures 31, 32 connects the plurality of gate structures 12 adjacent to each other in the second direction Y in the corresponding gate units GU1, GU2.

[0097] The isolation structures 31, 32 are respectively disposed in regions between ends of the gate structures 12 and the drain source regions 28, 29, and physically and electrically isolate the drain source regions 28, 29 from the ends of the gate structures 12. In other words, the isolation structures 31, 32 physically and electrically isolate the drain source regions 28, 29 from the connection structures 21, 22.

[0098] The multiple isolation structures 31, 32 define the boundary between the active region 6 and the outer region 7 on the first main surface 3, and at the same time increase the creepage distance between the end (connection structures 21, 22) of the gate structure 12 and the drain-source regions 28, 29. In this embodiment, the multiple isolation structures 31, 32 include multiple first isolation structures 31 arranged on the first end side and multiple second isolation structures 32 arranged on the second end side.

[0099] The multiple first isolation structures 31 are arranged at intervals from the multiple first ends (the multiple first connection structures 21) toward the drain-source regions 28, 29. The multiple first isolation structures 31 each extend in a strip shape in the second direction Y, and are connected to the multiple gate structures 12 adjacent to each other in the second direction Y. The multiple first isolation structures 31 are arranged in a line in the second direction Y. The multiple first isolation structures 31 may be connected to the drain-source regions 28, 29.

[0100] The second isolation structures 32 are arranged at intervals from the second ends (second connection structures 22) toward the drain-source regions 28, 29. The second isolation structures 32 each extend in a strip shape in the second direction Y and are connected to the gate structures 12 adjacent to each other in the second direction Y. The second isolation structures 32 are arranged in a line in the second direction Y. The second isolation structures 32 may be connected to the drain-source regions 28, 29.

[0101] In this embodiment, the multiple isolation structures 31, 32 are located within the drift layer 9 in a cross-sectional view. Specifically, the multiple isolation structures 31, 32 are formed at intervals on the first main surface 3 side with respect to the depth position of the bottom of the drift layer 9, and have side walls and a bottom wall located within the drift layer 9. The multiple isolation structures 31, 32 may be formed in a tapered shape in a cross-sectional view, with an opening width narrowing toward the bottom wall.

[0102] The plurality of isolation structures 31, 32 may penetrate the bottom of the drift layer 9 to reach the base layer 8. That is, the plurality of isolation structures 31, 32 may have a portion (side wall) located in the drift layer 9 and a portion (bottom wall) located in the base layer 8. The bottom walls of the plurality of isolation structures 31, 32 preferably have a flat portion extending substantially parallel to the first main surface 3. Of course, the bottom walls of the plurality of isolation structures 31, 32 may be curved in an arc shape toward the second main surface 4.

[0103] In this embodiment, the widths of the isolation structures 31, 32 are less than the widths of the connecting structures 21, 22. The widths of the isolation structures 31, 32 may be approximately equal to the widths of the connecting structures 21, 22. The widths of the isolation structures 31, 32 may be greater than the widths of the connecting structures 21, 22. The widths of the isolation structures 31, 32 may be approximately equal to the width of the gate structure 12. The widths of the isolation structures 31, 32 may be greater than the width of the gate structure 12. The widths of the isolation structures 31, 32 may be less than the width of the gate structure 12.

[0104] The width of isolation structures 31, 32 may be 0.1 μm or more and 5 μm or less. The width of isolation structures 31, 32 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or more, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0105] In this embodiment, the depth of the isolation structures 31, 32 is less than the depth of the connection structures 21, 22. The depth of the isolation structures 31, 32 may be approximately equal to the depth of the connection structures 21, 22. The depth of the isolation structures 31, 32 may be greater than the depth of the connection structures 21, 22. The depth of the isolation structures 31, 32 may be approximately equal to the depth of the gate structure 12. The depth of the isolation structures 31, 32 may be greater than the depth of the gate structure 12. The depth of the isolation structures 31, 32 may be less than the depth of the gate structure 12. For example, the isolation structures 31, 32 may be formed at a distance from a depth position of the middle part of the gate structure 12 toward the first main surface 3.

[0106] The depth of the isolation structures 31, 32 may be 0.1 μm or more and 10 μm or less. The depth of the isolation structures 31, 32 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less.

[0107] The following describes the configuration of one of the isolation structures 31, 32. The isolation structures 31, 32 include an isolation trench 33, an isolation insulating film 34, an isolation electrode 35, and an isolation buried insulator 36. The isolation trench 33 is dug down from the first main surface 3 toward the second main surface 4, and defines the sidewalls and bottom walls of the isolation structures 31, 32. The isolation trench 33 is connected to multiple trenches 13 adjacent to each other in the second direction Y.

[0108] The isolation insulating film 34 coats the wall surface of the isolation trench 33 in a film-like manner. The isolation insulating film 34 is connected to the insulating film 14 and the buried insulator 16 at the communicating portion between the trench 13 and the isolation trench 33. The isolation insulating film 34 can be regarded as a portion of the insulating film 14 that is drawn into the isolation trench 33. The connecting portion between the insulating film 14 and the isolation insulating film 34 may be regarded as one component of the gate structure 12, or may be regarded as one component of the isolation structures 31 and 32.

[0109] The isolation insulating film 34 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The isolation insulating film 34 preferably has a single-layer structure. The isolation insulating film 34 preferably includes a silicon oxide film made of an oxide of the chip 2. The isolation insulating film 34 is preferably formed of the same insulating material as the insulating film 14.

[0110] The isolation electrode 35 is buried in the isolation trench 33 via the isolation insulating film 34. The isolation electrode 35 may include conductive polysilicon. The isolation electrode 35 is buried on the bottom wall side of the trench 13 at a distance from the first main surface 3 to the bottom wall side of the isolation trench 33. The isolation electrode 35 is buried at a distance from the middle part of the isolation trench 33 to the bottom wall side of the isolation trench 33, and preferably has an electrode surface located closer to the bottom wall side than the middle part of the isolation trench 33.

[0111] The isolation electrode 35 is connected to the buried portion 15a at the communicating portion between the trench 13 and the isolation trench 33. The isolation electrode 35 can be regarded as a portion of the buried electrode 15 (buried portion 15a) that is drawn into the isolation trench 33. The connection portion between the buried electrode 15 and the isolation electrode 35 can be regarded as one component of the gate structure 12, or as one component of the isolation structures 31 and 32.

[0112] The electrode surface of the separation electrode 35 is located closer to the bottom wall of the separation trench 33 than the electrode surface of the lead-out portion 15b of the buried electrode 15. The electrode surface of the separation electrode 35 is preferably located at a depth position substantially equal to that of the electrode surface of the buried portion 15a.

[0113] The isolation buried insulator 36 is buried on the opening side of the isolation trench 33. The isolation buried insulator 36 may be buried in the isolation trench 33 with the isolation insulating film 34 sandwiched therebetween. The isolation buried insulator 36 may also be buried in the isolation trench 33 without the isolation insulating film 34 therebetween so as to directly cover the sidewall of the isolation trench 33.

[0114] The isolation buried insulator 36 extends in a strip shape in the second direction Y in a plan view. The isolation buried insulator 36 is connected to the buried insulator 16 at the communicating portion between the trench 13 and the isolation trench 33. The isolation buried insulator 36 is provided as a field insulator that relieves the electric field with respect to the isolation trench 33. The cross-sectional area of ​​the isolation buried insulator 36 is preferably larger than the cross-sectional area of ​​the isolation electrode 35.

[0115] The isolation buried insulator 36 has an insulating surface located near the first main surface 3. The insulating surface may be formed flush with the first main surface 3. The insulating surface may be located on the bottom wall side of the isolation trench 33 with respect to the first main surface 3. The insulating surface may protrude above the first main surface 3.

[0116] The isolation buried insulator 36 may contain at least one of silicon oxide, silicon nitride, and silicon oxynitride. The isolation buried insulator 36 may have a single-layer structure. The isolation buried insulator 36 may be formed of the same insulating material as the isolation insulating film 34. The isolation buried insulator 36 is made of a vapor deposited by a CVD method or the like, and preferably has a density different from that of the isolation insulating film 34. The isolation buried insulator 36 is preferably formed of the same insulating material as the buried insulator 16.

[0117] The isolation structures 31 and 32 may be of a trench insulation type instead of a trench electrode type. In this case, an insulator (silicon oxide, silicon nitride, silicon oxynitride, etc.) is embedded in the isolation trench 33 instead of the isolation electrode 35 via an isolation insulating film 34. In this case, the isolation insulating film 34 may be omitted.

[0118] The semiconductor device 1A includes a plurality of n-type floating regions 37 formed in the outer region 7 in regions between the ends (connection structures 21, 22) of the plurality of gate structures 12 and the plurality of isolation structures 31, 32. The plurality of floating regions 37 include portions of the drift layer 9 that are located in the regions between the ends (connection structures 21, 22) of the plurality of gate structures 12 and the plurality of isolation structures 31, 32, and are formed in an electrically floating state.

[0119] Although not specifically shown in the drawings, the plurality of floating regions 37 may include high-concentration regions in the surface portion of the drift layer 9 that have a higher n-type impurity concentration than the n-type impurity concentration of the drift layer 9. In this case, the n-type impurity concentration of the high-concentration regions may be approximately equal to the n-type impurity concentration of the drain source regions 28, 29. Furthermore, the high-concentration regions may have a depth approximately equal to the depth of the drain source regions 28, 29.

[0120] The semiconductor device 1A includes one or more trench electrode type field structures 42 formed in the outer region 7 of the first main surface 3. The field structures 42 may also be referred to as "trench field structures." The number of field structures 42 is arbitrary and is adjusted depending on the electric field to be relaxed, etc.

[0121] The number of field structures 42 may be 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10. The number of field structures 42 is preferably 5 or less. In this embodiment, the semiconductor device 1A includes three field structures 42. A base potential or a second drain-source potential (low potential) may be applied to the multiple field structures 42. The multiple field structures 42 may be formed in an electrically floating state.

[0122] The plurality of field structures 42 are formed on the first main surface 3 in the peripheral region 7b at intervals from the plurality of gate structures 12 (the plurality of connecting structures 21, 22) toward the periphery of the first main surface 3. The intervals between the plurality of gate structures 12 (the plurality of connecting structures 21, 22) and the innermost field structure 42 (closer to the active region 6) are preferably greater than the intervals between the plurality of gate structures 12. Of course, the intervals between the gate structures 12 and the field structures 42 may be equal to or less than the intervals between the plurality of gate structures 12.

[0123] The multiple field structures 42 are arranged at intervals from one another and extend in a strip shape along the periphery of the first main surface 3. In this embodiment, the multiple field structures 42 collectively surround the multiple active regions 6 (the multiple gate structures 12) in plan view and are formed in the shape of a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the chip 2.

[0124] In this embodiment, the plurality of field structures 42 are located within the drift layer 9 in a cross-sectional view. Specifically, the plurality of field structures 42 are formed at intervals on the first main surface 3 side with respect to the depth position of the bottom of the drift layer 9, and have side walls and a bottom wall located within the drift layer 9. The plurality of field structures 42 may be formed in a tapered shape in a cross-sectional view, with an opening width narrowing toward the bottom wall.

[0125] The plurality of field structures 42 may penetrate the bottom of the drift layer 9 to reach the base layer 8. That is, the plurality of field structures 42 may have a portion (side wall) located in the drift layer 9 and a portion (bottom wall) located in the base layer 8. The bottom walls of the plurality of field structures 42 preferably have a flat portion extending substantially parallel to the first main surface 3. Of course, the bottom walls of the plurality of field structures 42 may be curved in an arc shape toward the second main surface 4.

[0126] The spacing between the field structures 42 may be approximately equal to the spacing between the gate structures 12. The spacing between the field structures 42 may be less than the spacing between the gate structures 12. The spacing between the field structures 42 may be greater than the spacing between the gate structures 12.

[0127] The spacing between the plurality of field structures 42 may be 0.1 μm to 5 μm. The spacing between the field structures 42 may have a value belonging to at least one of the ranges of 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0128] In this embodiment, the width of the field structure 42 is greater than the width of the gate structure 12. The width of the field structure 42 may be less than the width of the gate structure 12. The width of the field structure 42 may be approximately equal to the width of the gate structure 12. The width of the field structure 42 may be approximately equal to the width of the connecting structures 21, 22. The width of the field structure 42 may be greater than the width of the connecting structures 21, 22. The width of the field structure 42 may be less than the width of the connecting structures 21, 22.

[0129] The width of the field structure 42 may be 0.1 μm to 5 μm, or may have a value belonging to at least one of the ranges of 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0130] The depth of the field structure 42, in this embodiment, is greater than the depth of the gate structure 12. The depth of the field structure 42 may be less than the depth of the gate structure 12. The depth of the field structure 42 may be approximately equal to the depth of the gate structure 12. The depth of the field structure 42 may be approximately equal to the depth of the connection structures 21, 22. The depth of the field structure 42 may be greater than the depth of the connection structures 21, 22. The depth of the field structure 42 may be less than the depth of the connection structures 21, 22.

[0131] The depth of the field structure 42 may be 0.1 μm to 10 μm inclusive. The depth of the field structure 42 may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm inclusive, 0.25 μm to 0.5 μm inclusive, 0.5 μm to 1 μm inclusive, 1 μm to 1.5 μm inclusive, 1.5 μm to 2 μm inclusive, 2 μm to 2.5 μm inclusive, 2.5 μm to 3 μm inclusive, 3 μm to 4 μm inclusive, 4 μm to 6 μm inclusive, 6 μm to 8 μm inclusive, and 8 μm to 10 μm inclusive.

[0132] The following describes the configuration of one field structure 42. The field structure 42 includes a field trench 43, a field insulating film 44, and a field electrode 45. The field trench 43 is dug from the first main surface 3 toward the second main surface 4, and defines the sidewalls and bottom wall of the field structure 42.

[0133] The field insulating film 44 coats the wall surface of the field trench 43 in a film-like manner. The field insulating film 44 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The field insulating film 44 preferably has a single-layer structure. The field insulating film 44 preferably includes a silicon oxide film made of an oxide of the chip 2. The field insulating film 44 is preferably formed of the same insulating material as the insulating film 14.

[0134] The field electrode 45 is buried in the field trench 43 via the field insulating film 44. The field electrode 45 may include conductive polysilicon. The field electrode 45 has an electrode surface located on the first main surface 3 side with respect to the electrode surface of the buried portion 15a. The electrode surface of the field electrode 45 is located near the first main surface 3.

[0135] The electrode surface of the field electrode 45 may be formed flush with the first main surface 3. The electrode surface of the field electrode 45 may be located on the bottom wall side of the field trench 43 with respect to the first main surface 3. The electrode surface of the field electrode 45 may protrude above the first main surface 3.

[0136] The field structure 42 may be of a trench isolation type instead of a trench electrode type. In this case, an insulator (silicon oxide, silicon nitride, silicon oxynitride, etc.) is buried in the field trench 43 instead of the field electrode 45 via a field insulating film 44. In this case, the field insulating film 44 may be omitted.

[0137] The semiconductor device 1A includes a plurality of p-type first impurity regions 51 formed in regions along the lower ends of the plurality of gate structures 12 inside the chip 2. The first impurity regions 51 have a p-type impurity concentration higher than the p-type impurity concentration of the base layer 8. The p-type impurity concentration of the first impurity regions 51 is 1×10 １６ cm －３ 1x10 or more １９ cm －３ It may be the following:

[0138] The multiple first impurity regions 51 are formed in one-to-one correspondence with the lower ends of the corresponding gate structures 12 at intervals from the gate structures 12 adjacent to them in the second direction Y. The multiple first impurity regions 51 have portions covering the bottom walls and portions covering the side walls at the lower ends of the corresponding gate structures 12. The multiple first impurity regions 51 extend in a strip shape in the first direction X along the corresponding gate structures 12 in a plan view.

[0139] The plurality of first impurity regions 51 face the buried electrodes 15 at the lower ends of the corresponding gate structures 12, with the insulating film 14 sandwiched therebetween. The plurality of first impurity regions 51 are electrically connected to the drift layer 9 on the first main surface 3 side, and are electrically connected to the base layer 8 on the second main surface 4 side. In this embodiment, the plurality of first impurity regions 51 have a portion on the first main surface 3 side where the conductivity type of the drift layer 9 is converted from n-type to p-type.

[0140] When the bottom walls of the plurality of gate structures 12 are located in the base layer 8, the plurality of first impurity regions 51 may be formed at intervals from the bottom of the drift layer 9 toward the second main surface 4. In this case, the plurality of first impurity regions 51 may face the drift layer 9 with a part of the base layer 8 interposed therebetween.

[0141] Each of the plurality of first impurity regions 51 is formed to be wider than the corresponding gate structure 12. Specifically, each of the plurality of first impurity regions 51 includes a bulging portion that bulges out in an arc shape (circular arc shape) in the horizontal direction (on both sides) from a region below the gate structure 12 in a cross-sectional view. When the gate structure 12 is formed in a tapered shape, the bulging portion faces the sidewall of the gate structure 12 in the thickness direction of the chip 2.

[0142] With respect to the plurality of first impurity regions 51 adjacent to each other in the second direction Y, the bulging portion of one first impurity region 51 is connected to the bulging portion of the other first impurity region 51. In other words, the plurality of first impurity regions 51 are connected to each other in the second direction Y. As a result, the plurality of first impurity regions 51 separate the base layer 8 and the drift layer 9 in the vertical direction in the corresponding active region 6. The connection portions of the plurality of bulging portions may face the plurality of drain-source regions 28, 29 with the drift layer 9 interposed therebetween.

[0143] The portions of the first impurity regions 51 that are located along the lower ends of the gate structures 12 respectively form channels (current paths) of the transistor structures Tr. The inversion and non-inversion of the channels are controlled by the gate structures 12.

[0144] When a gate potential is applied to the plurality of gate structures 12, a first drain-source potential is applied to the first drain-source region 28, and a second drain-source potential is applied to the second drain-source region 29, the plurality of channels are turned on and a drain-source current Ids is generated (see FIG. 6).

[0145] The drain-source current Ids flows from the first drain-source region 28 to the second drain-source region 29 via the drift layer 9 and the plurality of first impurity regions 51. That is, the drain-source current Ids passes in the second direction Y through a region below the plurality of (two in this embodiment) gate structures 12 interposed between the first drain-source region 28 and the second drain-source region 29.

[0146] The first impurity region 51 is formed by introducing p-type impurities into the chip 2 through the bottom wall of the trench 13. In the case of the trench 13 having a flat bottom wall, the p-type impurities can be appropriately introduced into the chip 2. Therefore, the first impurity region 51 (channel) is appropriately formed in a region along the lower end of the gate structure 12.

[0147] The semiconductor device 1A includes a plurality of p-type second impurity regions 52 formed in regions along the lower ends of the plurality of connection structures 21, 22 inside the chip 2. The second impurity regions 52 have a p-type impurity concentration higher than the p-type impurity concentration of the base layer 8. The p-type impurity concentration of the second impurity regions 52 is preferably approximately equal to the p-type impurity concentration of the first impurity region 51. The p-type impurity concentration of the second impurity regions 52 is 1×10 １６ cm －３ 1x10 or more １９ cm －３ It may be the following:

[0148] The plurality of second impurity regions 52 are formed in a one-to-one correspondence with the lower ends of the corresponding connection structures 21, 22. The plurality of second impurity regions 52 have portions covering the bottom walls and portions covering the side walls at the lower ends of the corresponding connection structures 21, 22. The plurality of second impurity regions 52 extend in a strip shape in the second direction Y along the corresponding connection structures 21, 22 in a plan view, and are connected to the first impurity regions 51 at both ends of the corresponding connection structures 21, 22.

[0149] The second impurity regions 52 face the connection electrodes 25 across the connection insulating film 24 at the lower ends of the corresponding connection structures 21, 22. The second impurity regions 52 are electrically connected to the drift layer 9 on the first main surface 3 side, and are electrically connected to the base layer 8 on the second main surface 4 side. In this embodiment, the second impurity regions 52 have a portion on the first main surface 3 side where the conductivity type of the drift layer 9 is converted from n-type to p-type.

[0150] When the bottom walls of the plurality of connection structures 21, 22 are located within the base layer 8, the plurality of second impurity regions 52 may be formed at intervals from the bottom of the drift layer 9 toward the second main surface 4. In this case, the plurality of second impurity regions 52 may face the drift layer 9 with a part of the base layer 8 interposed therebetween.

[0151] In this embodiment, the plurality of connection structures 21, 22 are formed deeper than the plurality of gate structures 12, and the plurality of second impurity regions 52 are formed deeper than the plurality of first impurity regions 51. In other words, the bottoms of the plurality of second impurity regions 52 are located closer to the second main surface 4 than the bottoms of the plurality of first impurity regions 51. Of course, the plurality of connection structures 21, 22 may be formed at a depth substantially equal to that of the plurality of gate structures 12, and the plurality of second impurity regions 52 may be formed at a depth substantially equal to that of the plurality of first impurity regions 51.

[0152] The plurality of second impurity regions 52 are each formed wider than the corresponding connection structures 21, 22. Specifically, like the plurality of first impurity regions 51, the plurality of second impurity regions 52 each include a bulge portion that bulges out in an arc shape (circular arc shape) in the horizontal direction (on both sides) from the region below the connection structures 21, 22 in a cross-sectional view. When the connection structures 21, 22 are formed in a tapered shape, the bulge portion faces the sidewalls of the connection structures 21, 22 in the thickness direction of the chip 2.

[0153] The second impurity region 52 is formed by introducing p-type impurities into the chip 2 through the bottom wall of the connection trench 23. If the connection trench 23 has a flat bottom wall, the p-type impurities can be appropriately introduced into the chip 2. Therefore, the second impurity region 52 is appropriately formed in a region along the lower end of the connection structures 21, 22.

[0154] The semiconductor device 1A includes a plurality of p-type third impurity regions 53 formed in regions along the lower ends of the plurality of isolation structures 31, 32 inside the chip 2. The third impurity regions 53 have a p-type impurity concentration higher than the p-type impurity concentration of the base layer 8. The p-type impurity concentration of the third impurity regions 53 is preferably approximately equal to the p-type impurity concentration of the first impurity region 51. The p-type impurity concentration of the third impurity regions 53 is 1×10 １６ cm －３ 1x10 or more １９ cm －３ It may be the following:

[0155] The plurality of third impurity regions 53 are formed in one-to-one correspondence with the lower ends of the corresponding isolation structures 31, 32. The plurality of third impurity regions 53 have portions covering the bottom walls and portions covering the side walls at the lower ends of the corresponding isolation structures 31, 32. The plurality of third impurity regions 53 extend in a strip shape in the second direction Y along the corresponding isolation structures 31, 32 in a plan view, and are connected to the first impurity regions 51 at both ends of the corresponding isolation structures 31, 32.

[0156] The plurality of third impurity regions 53 face the isolation electrode 35 with the isolation insulating film 34 interposed therebetween at the lower ends of the corresponding isolation structures 31, 32. The plurality of third impurity regions 53 are electrically connected to the drift layer 9 on the first main surface 3 side, and are electrically connected to the base layer 8 on the second main surface 4 side. In this embodiment, the plurality of third impurity regions 53 have a portion on the first main surface 3 side where the conductivity type of the drift layer 9 is converted from n-type to p-type.

[0157] When the bottom walls of the plurality of isolation structures 31, 32 are located in the base layer 8, the plurality of third impurity regions 53 may be formed at intervals from the bottom of the drift layer 9 toward the second main surface 4. In this case, the plurality of third impurity regions 53 may face the drift layer 9 with part of the base layer 8 interposed therebetween.

[0158] In this embodiment, the plurality of isolation structures 31, 32 are formed to a depth approximately equal to that of the plurality of gate structures 12, and the plurality of third impurity regions 53 are formed to a depth approximately equal to that of the plurality of first impurity regions 51. Of course, the plurality of isolation structures 31, 32 may be formed deeper than the plurality of gate structures 12, and the plurality of third impurity regions 53 may be formed deeper than the plurality of first impurity regions 51.

[0159] The plurality of third impurity regions 53 are each formed wider than the corresponding isolation structures 31, 32. Specifically, like the plurality of first impurity regions 51, the plurality of third impurity regions 53 each include a bulging portion that bulges out in an arc shape (circular arc shape) in the horizontal direction (on both sides) from the region below the isolation structures 31, 32 in a cross-sectional view. When the isolation structures 31, 32 are formed in a tapered shape, the bulging portion faces the sidewalls of the isolation structures 31, 32 in the thickness direction of the chip 2.

[0160] The third impurity region 53 is formed by introducing p-type impurities into the chip 2 through the bottom wall of the isolation trench 33. If the isolation trench 33 has a flat bottom wall, the p-type impurities can be appropriately introduced into the chip 2. Therefore, the third impurity region 53 is appropriately formed in a region along the lower end of the isolation structures 31 and 32.

[0161] The semiconductor device 1A includes a plurality of p-type fourth impurity regions 54 formed in regions along the lower ends of the plurality of field structures 42 inside the chip 2. The fourth impurity regions 54 have a p-type impurity concentration higher than the p-type impurity concentration of the base layer 8. The p-type impurity concentration of the fourth impurity regions 54 is preferably approximately equal to the p-type impurity concentration of the first impurity region 51. The p-type impurity concentration of the fourth impurity regions 54 is 1×10 １６ cm －３ 1x10 or more １９ cm －３ It may be the following:

[0162] The multiple fourth impurity regions 54 are formed in one-to-one correspondence with the lower ends of the corresponding field structures 42, spaced apart from the first impurity region 51, the second impurity region 52, and the third impurity region 53. Each of the multiple fourth impurity regions 54 has a portion covering the bottom wall and a portion covering the sidewall at the lower end of the corresponding field structure 42. The multiple fourth impurity regions 54 extend in a band shape along the corresponding field structure 42 in a plan view. Specifically, the multiple fourth impurity regions 54 extend in an annular shape along the corresponding field structure 42 in a plan view.

[0163] The plurality of fourth impurity regions 54 face the field electrode 45 across the field insulating film 44 at the lower end of the corresponding field structure 42. The plurality of fourth impurity regions 54 are electrically connected to the drift layer 9 on the first main surface 3 side, and are electrically connected to the base layer 8 on the second main surface 4 side. In this embodiment, the plurality of fourth impurity regions 54 have a portion on the first main surface 3 side where the conductivity type of the drift layer 9 is converted from n-type to p-type.

[0164] When the bottom walls of the plurality of field structures 42 are located within the base layer 8, the plurality of fourth impurity regions 54 may be formed at intervals from the bottom of the drift layer 9 toward the second main surface 4. In this case, the plurality of fourth impurity regions 54 may face the drift layer 9 with a part of the base layer 8 interposed therebetween.

[0165] In this embodiment, the plurality of field structures 42 are formed deeper than the plurality of gate structures 12, and the plurality of fourth impurity regions 54 are formed deeper than the plurality of first impurity regions 51. In other words, the bottoms of the plurality of fourth impurity regions 54 are located closer to the second main surface 4 than the bottoms of the plurality of first impurity regions 51. Of course, the plurality of field structures 42 may be formed to a depth approximately equal to that of the plurality of gate structures 12, and the plurality of fourth impurity regions 54 may be formed to a depth approximately equal to that of the plurality of first impurity regions 51.

[0166] Each of the plurality of fourth impurity regions 54 is formed to be wider than the corresponding field structure 42. Specifically, like the plurality of first impurity regions 51, each of the plurality of fourth impurity regions 54 includes a bulge portion that bulges out in an arc shape (circular arc shape) in the horizontal direction (on both sides) from the region below the field structure 42 in a cross-sectional view. When the field structure 42 is formed in a tapered shape, the bulge portion faces the sidewall of the field structure 42 in the thickness direction of the chip 2.

[0167] With respect to the plurality of adjacent fourth impurity regions 54, the bulging portion of one fourth impurity region 54 is connected to the bulging portion of the other fourth impurity region 54. As a result, the plurality of fourth impurity regions 54 separate the base layer 8 and the drift layer 9 in the vertical direction in the outer region 7.

[0168] The fourth impurity region 54 is formed by introducing p-type impurities into the chip 2 through the bottom wall of the field trench 43. If the field trench 43 has a flat bottom wall, the p-type impurities can be introduced properly into the chip 2. Therefore, the fourth impurity region 54 is properly formed in a region along the bottom edge of the field structure 42.

[0169] The semiconductor device 1A includes one or more (one in this embodiment) trench electrode type base structures 55 formed in the outer region 7 on the first main surface 3. The base structure 55 may also be referred to as a "trench base structure." A base potential is applied to the base structure 55. The base structure 55 includes a plurality of first base structures 55a and at least one (one in this embodiment) second base structure 55b.

[0170] The multiple first base structures 55a are arranged in the multiple boundary regions 7a, respectively. The multiple first base structures 55a extend in a strip shape in the second direction Y in the corresponding boundary region 7a. Each of the multiple first base structures 55a has a first end on one side in the second direction Y and a second end on the other side in the second direction Y. Of course, the multiple first base structures 55a may also be arranged at intervals in the second direction Y in a corresponding one of the boundary regions 7a.

[0171] Each first base structure 55a is disposed inwardly and spaced apart from the plurality of gate structures 12 adjacent thereto in the first direction X, and faces the plurality of gate structures 12 on both sides in the first direction X. That is, each first base structure 55a is disposed in a region between the plurality of first connection structures 21 and the plurality of second connection structures 22 in the corresponding boundary region 7a, and faces the plurality of connection structures 21, 22 on both sides in the first direction X. As a result, the plurality of first base structures 55a separate the plurality of active regions 6 (the plurality of gate structures 12) on both sides in the first direction X.

[0172] The second base structure 55b is disposed in the peripheral region 7b. The second base structure 55b is disposed in a region between the active regions 6 (the gate structures 12) and the innermost field structure 42, and extends in a strip shape along the active regions 6. In this embodiment, the second base structure 55b has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in plan view, and partitions the active regions 6 from multiple directions.

[0173] In this embodiment, the second base structure 55b collectively surrounds the plurality of active regions 6 (the plurality of gate structures 12) in a plan view and is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2. The second base structure 55b faces the plurality of active regions 6 (the plurality of gate structures 12) in the first direction X and the second direction Y. Of course, the plurality of second base structures 55b may be arranged at intervals in the first direction X and the second direction Y along the plurality of active regions 6 so as to surround the plurality of active regions 6 (the plurality of gate structures 12).

[0174] The second base structure 55b is formed at a distance from the first ends of the plurality of first base structures 55a toward the peripheral edge of the chip 2 (toward the innermost field structure 42) in a region on one side in the second direction Y. In other words, the first ends of the plurality of first base structures 55a are formed as open ends.

[0175] The second base structure 55b is connected to second ends of the plurality of first base structures 55a on the other side in the second direction Y. That is, the second base structure 55b connects the plurality of first base structures 55a in a comb-tooth shape toward the plurality of boundary regions 7a. The second base structure 55b is also formed as an extension portion that is extended from the plurality of first base structures 55a to the outer peripheral region 7b.

[0176] The base structure 55 is located within the drift layer 9 in a cross-sectional view. Specifically, the base structure 55 is formed on the first main surface 3 side with a gap therebetween with respect to the depth position of the bottom of the drift layer 9, and has sidewalls and a bottom wall located within the drift layer 9. The base structure 55 may be formed in a tapered shape in a cross-sectional view, with an opening width narrowing toward the bottom wall. The bottom wall of the base structure 55 may have a flat portion extending approximately parallel to the first main surface 3. Of course, the bottom wall of the base structure 55 may be curved in an arc shape toward the second main surface 4.

[0177] The width of the base structure 55 is preferably less than the width of the field structure 42. The width of the base structure 55 may be greater than the width of the field structure 42. The width of the base structure 55 may be approximately equal to the width of the field structure 42. The width of the base structure 55 is less than the width of the gate structure 12 in this embodiment. The width of the base structure 55 may be greater than the width of the gate structure 12. The width of the base structure 55 may be approximately equal to the width of the gate structure 12.

[0178] The width of the base structure 55 may be 0.1 μm or more and 5 μm or less. The width of the base structure 55 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0179] The depth of the base structure 55 is less than the depth of the field structure 42. In this embodiment, the depth of the base structure 55 is less than the depth of the gate structure 12. The base structure 55 is preferably formed at a distance from the depth position of the electrode surface of the buried portion 15a of the gate structure 12 toward the first main surface 3. The base structure 55 is preferably formed at a distance from the depth position of the intermediate portion of the gate structure 12 toward the first main surface 3. In other words, the bottom wall of the base structure 55 is preferably formed at a depth position that faces the buried insulator 16 in the horizontal direction.

[0180] The depth of the base structure 55 may be 0.1 μm to 10 μm. The depth of the base structure 55 may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, and 8 μm to 10 μm.

[0181] The base structure 55 includes a base trench 56 and a base electrode 57. The base trench 56 is dug from the first main surface 3 toward the second main surface 4, and defines the sidewalls and bottom wall of the base structure 55. The base electrode 57 is buried in the base trench 56 and is electrically connected to the chip 2 within the base trench 56.

[0182] In this embodiment, the base electrode 57 includes a first electrode 58 and a second electrode 59. The first electrode 58 coats the wall surface of the base trench 56 in the form of a film. The first electrode 58 may have a single-layer structure made of a Ti film or a Ti alloy film. The first electrode 58 may have a layered structure including a Ti film and a Ti alloy film layered in this order from the chip 2 side. The Ti alloy film may be a TiN film.

[0183] The second electrode 59 is buried in the base trench 56 via the first electrode 58 and is electrically connected to the chip 2 via the first electrode 58. The second electrode 59 may include at least one of W, Al, an Al alloy, Cu, and a Cu alloy. The Al alloy may include at least one of an AlSi alloy, an AlCu alloy, and an AlSiCu alloy.

[0184] The semiconductor device 1A includes a silicide layer 60 formed in a region along the base structure 55 in the chip 2. The silicide layer 60 is formed in a region along the plurality of first base structures 55a and a region along the second base structure 55b in the chip 2. The silicide layer 60 is formed in a film shape along the wall surfaces (side walls and bottom wall) of the base structure 55, and is mechanically and electrically connected to the base electrode 57.

[0185] The silicide layer 60 is formed in the boundary regions 7a at a distance inward from the gate structures 12 (connection structures 21, 22) adjacent to each other in the first direction X. The silicide layer 60 is formed in the peripheral region 7b at a distance from the gate structures 12 (connection structures 21, 22) and the innermost field structure 42.

[0186] The silicide layer 60 may include at least one of a Ti silicide layer, a Ni silicide layer, a Co silicide layer, a Mo silicide layer, and a W silicide layer. In this embodiment, the silicide layer 60 includes a Ti silicide layer.

[0187] The thickness of the silicide layer 60 may be 1 nm or more and 500 nm or less. The thickness of the silicide layer 60 may have a value belonging to at least one of the ranges of 1 nm or more and 50 nm or less, 50 nm or more and 100 nm or less, 100 nm or more and 200 nm or less, 200 nm or more and 300 nm or less, 300 nm or more and 400 nm or less, and 400 nm or more and 500 nm or less.

[0188] The semiconductor device 1A includes a p-type contact region 61 formed in a region below the base structure 55 in the chip 2. In this embodiment, the contact region 61 is formed by introducing p-type impurities into the drift layer 9. The contact region 61 has a p-type impurity concentration higher than the n-type impurity concentration of the drift layer 9, and converts the conductivity type of the drift layer 9 from n-type to p-type.

[0189] The p-type impurity concentration of the contact region 61 is higher than the p-type impurity concentration of the base layer 8. Of course, the contact region 61 may be formed by introducing p-type impurities into the base layer 8. The p-type impurity concentration of the contact region 61 is 1×10 １６ cm －３ 1x10 or more ２１ cm －３ It may be the following:

[0190] The contact regions 61 extend in a strip shape along the base structures 55. Specifically, the contact regions 61 are formed in regions below the plurality of first base structures 55a and regions below the second base structures 55b within the chip 2. The contact regions 61 extend in a strip shape in the second direction Y along the corresponding first base structures 55a in each boundary region 7a.

[0191] The contact region 61 extends in a strip shape along the second base structure 55b in the peripheral region 7b. The contact region 61 has a portion that extends in a strip shape in the first direction X along the second base structure 55b and a portion that extends in a strip shape in the second direction Y. In this embodiment, the contact region 61 is formed in a polygonal ring shape (a square ring in this embodiment) that extends along the base structure 55b.

[0192] The contact region 61 extends horizontally from the region directly below the base structure 55 and is connected to the plurality of gate structures 12, the plurality of connecting structures 21, 22, and the innermost field structure 42. The contact region 61 extends in the thickness direction of the chip 2 through the thickness range between the base layer 8 and the base structure 55, and penetrates the bottom of the drift layer 9 to reach the base layer 8.

[0193] The contact region 61 has a lower end connected to the base layer 8 and an upper end connected to the base structure 55, and electrically connects the base structure 55 to the base layer 8. In this embodiment, the lower end of the contact region 61 is formed at a distance from the depth position of the bottoms of the first impurity region 51 and the fourth impurity region 54 towards the first main surface 3.

[0194] Of course, the lower end of the contact region 61 may be located lower (closer to the second main surface 4) than the depth positions of the bottoms of the first impurity region 51 and the fourth impurity region 54. The lower end of the contact region 61 may be curved in an arc shape (circular arc shape) toward the second main surface 4.

[0195] The lower end of the contact region 61 may be connected to the first impurity region 51 in a portion along the gate structure 12. The lower end of the contact region 61 may be connected to the second impurity region 52 in a portion along the connecting structures 21 and 22. The lower end of the contact region 61 may be connected to the innermost fourth impurity region 54 in a portion along the innermost field structure 42.

[0196] For example, in the boundary region 7 a, the lower end of the contact region 61 may be connected to the plurality of first impurity regions 51 at portions along the plurality of gate structures 12 adjacent to each other in the first direction X. For example, in the boundary region 7 a, the lower end of the contact region 61 may be connected to the plurality of second impurity regions 52 at portions along the first connection structure 21 and the second connection structure 22 adjacent to each other in the first direction X.

[0197] For example, in peripheral region 7b, the lower end of contact region 61 may be connected to first impurity region 51 and fourth impurity region 54 at portions along gate structure 12 and innermost field structure 42. For example, in peripheral region 7b, the lower end of contact region 61 may be connected to second impurity region 52 and fourth impurity region 54 at portions along connection structures 21, 22 and innermost field structure 42.

[0198] The upper end of the contact region 61 is formed at a distance from the first main surface 3 toward the bottom wall of the base structure 55, and has portions that extend along the sidewalls and bottom wall of the base structure 55. The upper end of the contact region 61 is electrically connected to the sidewalls and bottom wall of the base structure 55 via the silicide layer 60. The upper end of the contact region 61 may be curved in an arc shape (circular arc shape) toward the first main surface 3. In other words, the upper end of the contact region 61 may be formed so as to gradually become more spaced from the first main surface 3 as it moves away from the base structure 55.

[0199] The semiconductor device 1A includes an n-type surface region 62 formed around the base structure 55 in the surface portion of the first main surface 3. The surface region 62 has an n-type impurity concentration higher than the n-type impurity concentration of the drift layer 9. The n-type impurity concentration of the surface region 62 may be higher than the n-type impurity concentration of the drain source regions 28, 29. The n-type impurity concentration of the surface region 62 may be lower than the n-type impurity concentration of the drain source regions 28, 29. The n-type impurity concentration of the surface region 62 is 1×10 １５ cm －３ 1x10 or more ２０ cm －３ It may be the following:

[0200] The surface region 62 extends in a band shape along the base structure 55. Specifically, in this embodiment, the surface region 62 is formed in a region along the plurality of first base structures 55a and a region along the second base structure 55b in the surface layer portion of the first main surface 3. The surface region 62 extends in a band shape in the second direction Y along the corresponding first base structure 55a in each boundary region 7a.

[0201] The surface region 62 extends in a strip shape along the second base structure 55b in the outer peripheral region 7b. The surface region 62 has a portion that extends in a strip shape in the first direction X along the second base structure 55b and a portion that extends in a strip shape in the second direction Y. In this embodiment, the surface region 62 is formed in a polygonal ring shape (a square ring shape in this embodiment) that extends along the second base structure 55b.

[0202] The surface region 62 is formed in a thickness range between the first main surface 3 and the contact region 61. The surface region 62 is electrically connected at its upper end to the base structure 55 via the silicide layer 60, and is electrically connected at its lower end to the contact region 61. In this embodiment, the surface region 62 has a bottom that curves in an arc toward the first main surface 3.

[0203] That is, the surface region 62 is formed so as to become gradually deeper with increasing distance from the base structure 55, and has a shallow portion formed near the base structure 55 and a deep portion formed far from the base structure 55. The shallow portion of the surface region 62 is formed at a distance from the bottom wall of the base structure 55 toward the first main surface 3, and is electrically connected to the side wall of the base structure 55 via the silicide layer 60.

[0204] The deep portion of the surface region 62 is located in a region closer to the second main surface 4 than the depth position of the bottom wall of the base structure 55. The deep portion of the surface region 62 is located in a region closer to the first main surface 3 than the depth positions of the bottom walls of the plurality of gate structures 12 and the plurality of field structures 42. The deep portion of the surface region 62 is preferably located in a region closer to the first main surface 3 than the depth position of the electrode surface of the buried electrode 15.

[0205] It is particularly preferable that the deep portion of the surface region 62 is located in a region closer to the first main surface 3 than the depth position of the intermediate portion of the gate structure 12. The deep portion of the surface region 62 is connected to the plurality of gate structures 12, the plurality of connecting structures 21, 22, and the innermost field structure 42. Of course, the surface region 62 may have a substantially constant depth.

[0206] The surface region 62 may have a concentration gradient in which the n-type impurity concentration gradually decreases in the thickness direction. That is, the n-type impurity concentration of the surface region 62 may gradually decrease from the shallow portion to the deep portion. In this case, the n-type impurity concentration in the deep portion is lower than the n-type impurity concentration in the shallow portion. The n-type impurity concentration in the shallow portion may be approximately equal to the n-type impurity concentration in the multiple drain-source regions 28, 29.

[0207] 7 to 10 , semiconductor device 1A includes an insulating interlayer film 70 covering first main surface 3. Interlayer film 70 may also be referred to as an "interlayer insulating film," "intermediate film," "intermediate insulating film," or the like. Interlayer film 70 has a layered structure including a first interlayer film 71 and a second interlayer film 72 layered in this order from the chip 2 (first main surface 3) side.

[0208] The first interlayer film 71 is an insulating film on which wiring is disposed, and has a single-layer structure made of a single insulating film or a multilayer structure including multiple insulating films. The first interlayer film 71 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first interlayer film 71 collectively covers the multiple active regions 6 and the outer region 7 on the first main surface 3 in a film (layer) shape.

[0209] That is, the first interlayer film 71 collectively covers the plurality of gate structures 12, the plurality of connection structures 21, 22, the plurality of isolation structures 31, 32, the plurality of drain-source regions 28, 29, the plurality of field structures 42, etc. The first interlayer film 71 may cover the outer insulating films 10, 11 on the peripheral edge side of the first main surface 3. The first interlayer film 71 may cover the first main surface 3 at a distance inward from the outer insulating films 10, 11, exposing the outer insulating films 10, 11.

[0210] The second interlayer film 72 is an insulating film on which wiring is disposed above the first interlayer film 71, and has a single-layer structure made of a single insulating film or a laminated structure including multiple insulating films. The second interlayer film 72 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second interlayer film 72 covers the first interlayer film 71 in a film (layer) shape.

[0211] 14 and 15 , the semiconductor device 1A includes a multilayer wiring structure 73 disposed on the chip 2 (first main surface 3). The multilayer wiring structure 73 is formed by utilizing an interlayer film 70. Specifically, the multilayer wiring structure 73 includes first-layer wiring 74 disposed on the lower layer side of the interlayer film 70 and second-layer wiring 75 disposed on the upper layer side of the interlayer film 70. The first-layer wiring 74 is disposed on the first interlayer film 71 and is covered by the second interlayer film 72. The second-layer wiring 75 is disposed on the second interlayer film 72 and crosses the first-layer wiring 74 at an overpass.

[0212] In this embodiment, the multilayer wiring structure 73 is a two-layer structure including a first layer wiring 74 and a second layer wiring 75. That is, the first layer wiring 74 is formed as the bottom wiring of the multilayer wiring structure 73, and the second layer wiring 75 is formed as the top wiring of the multilayer wiring structure 73. The second layer wiring 75 is exposed from the interlayer film 70.

[0213] The multilayer wiring structure 73 need only include a first-layer wiring 74 and a second-layer wiring 75 that face each other in the vertical direction with a portion of the interlayer film 70 (second interlayer film 72) sandwiched therebetween, and the number of layers in the multilayer wiring structure 73 is not limited to two. That is, the multilayer wiring structure 73 may have a stacked structure of three or more layers. For example, if the interlayer film 70 has one or more lower interlayer films below the first interlayer film 71, the multilayer wiring structure 73 may include one or more lower-layer wirings arranged below the first-layer wiring 74.

[0214] The first-layer wiring 74 has a laminated structure including a first electrode 76 and a second electrode 77 laminated in this order from the first interlayer film 71 side. The first electrode 76 covers the first interlayer film 71 in a film-like manner. The first electrode 76 may include either or both of a Ti film and a Ti alloy film. The Ti alloy film may be a TiN film.

[0215] The second electrode 77 covers the first electrode 76 in the form of a film. The second electrode 77 may include at least one of a W film, an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.

[0216] The second-layer wiring 75 has a laminated structure including a first electrode 78 and a second electrode 79 laminated in this order from the second interlayer film 72 side. The first electrode 78 covers the second interlayer film 72 in a film-like manner. The first electrode 78 may include either or both of a Ti film and a Ti alloy film. The Ti alloy film may be a TiN film.

[0217] The second electrode 79 covers the first electrode 78 in the form of a film. The second electrode 79 may include at least one of a W film, an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.

[0218] 14 and other figures, the first layer wiring 74 includes a plurality of wiring groups 80. The plurality of wiring groups 80 are arranged on the plurality of active regions 6 at intervals in the first direction X. The plurality of wiring groups 80 are arranged in one-to-one correspondence with the first to sixth active regions 6A to 6F, and are arranged as first to sixth wiring groups 80A to 80F in order from the third side surface 5C side.

[0219] The first wiring group 80A is arranged on the first active region 6A. The second wiring group 80B is arranged on the second active region 6B at a distance from the first wiring group 80A in the first direction X and faces the first wiring group 80A in the first direction X. The third wiring group 80C is arranged on the third active region 6C at a distance from the second wiring group 80B in the first direction X and faces the second wiring group 80B in the first direction X.

[0220] The fourth wiring group 80D is arranged on the fourth active region 6D at a distance from the third wiring group 80C in the first direction X and faces the third wiring group 80C in the first direction X. The fifth wiring group 80E is arranged on the fifth active region 6E at a distance from the fourth wiring group 80D in the first direction X and faces the fourth wiring group 80D in the first direction X. The sixth wiring group 80F is arranged on the sixth active region 6F at a distance from the fifth wiring group 80E in the first direction X and faces the fifth wiring group 80E in the first direction X.

[0221] The plurality of wiring groups 80 each include a plurality of first lower wirings 81 and a plurality of second lower wirings 82. The first lower wirings 81 transmit a first drain source potential to the first drain source region 28. The second lower wirings 82 transmit a second drain source potential to the second drain source region 29. The first lower wirings 81 may be referred to as "first drain source wirings." The second lower wirings 82 may be referred to as "second drain source wirings."

[0222] The multiple first lower interconnections 81 extend in a strip shape in the first direction X on the corresponding active regions 6 and are arranged at intervals in the second direction Y. That is, the multiple first lower interconnections 81 are arranged in stripes extending in the first direction X. The multiple first lower interconnections 81 are respectively disposed on the multiple first drain source regions 28 (multiple first mesa portions 26) and face the multiple first drain source regions 28 (multiple first mesa portions 26) in a one-to-one correspondence in the stacking direction. The multiple first lower interconnections 81 are each electrically connected to the corresponding first drain source regions 28.

[0223] With respect to the multiple wiring groups 80, the multiple first lower wirings 81 face each other in the first direction X. That is, with respect to one and the other wiring groups 80, the multiple first lower wirings 81 belonging to the other wiring group 80 face the multiple first lower wirings 81 belonging to one wiring group 80 in a one-to-one correspondence.

[0224] The layout of one first lower wiring 81 will be described below. The first lower wiring 81 preferably has both ends located inward (inward of the corresponding active region 6) with respect to both ends (first end and second end) of the corresponding gate structure 12 in the first direction X. The both ends of the first lower wiring 81 are preferably located inward with respect to the multiple connection structures 21, 22.

[0225] Both ends of the first lower wiring 81 may be located in a region between the corresponding connection structures 21, 22 and isolation structures 31, 32, and may face the floating region 37 in the stacking direction. Both ends of the first lower wiring 81 may be located on the corresponding isolation structures 31, 32. Both ends of the first lower wiring 81 may be located inward from the corresponding isolation structures 31, 32, and may be located on the corresponding first drain-source region 28 (first mesa portion 26).

[0226] The first lower wirings 81 may each have a width greater than the width of the corresponding first mesa portion 26 in the second direction Y. That is, the first lower wirings 81 may overlap multiple (two in this embodiment) gate structures 12 located directly below them. In this case, it is preferable that the first lower wirings 81 have a width less than the width of the corresponding first gate unit GU1. Of course, the first lower wirings 81 may have a width less than the width of the first mesa portion 26. Of course, the first lower wirings 81 may have a width greater than the width of the first gate unit GU1.

[0227] The width of the first lower wiring 81 may be 0.1 μm or more and 15 μm or less. The width of the first lower wiring 81 may have a value belonging to at least one of the ranges of 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, 4.5 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, 9 μm to 10 μm, 10 μm to 11 μm, 11 μm to 12 μm, 12 μm to 13 μm, 13 μm to 14 μm, and 14 μm to 15 μm.

[0228] The multiple second lower wirings 82 are each arranged above the corresponding active region 6 at intervals in the second direction Y from the multiple first lower wirings 81. The multiple second lower wirings 82 each extend in a strip shape in the first direction X and are arranged at intervals in the second direction Y. In other words, the multiple second lower wirings 82 are arranged in a stripe shape extending in the first direction X. The multiple second lower wirings 82 are each mixed in regions between the multiple first lower wirings 81. Specifically, the multiple second lower wirings 82 are arranged alternately with the multiple first lower wirings 81 in the second direction Y.

[0229] The second lower wirings 82 are respectively disposed on the second drain source regions 29 (the second mesa portions 27) and face the second drain source regions 29 (the second mesa portions 27) in a one-to-one correspondence in the stacking direction. The second lower wirings 82 are respectively electrically connected to the corresponding second drain source regions 29.

[0230] With respect to the plurality of wiring groups 80, the plurality of second lower wirings 82 face each other in the first direction X. That is, with respect to one and the other wiring groups 80, the plurality of second lower wirings 82 belonging to the other wiring group 80 face the plurality of second lower wirings 82 belonging to one wiring group 80 in a one-to-one correspondence. The plurality of second lower wirings 82 may be arranged at wiring intervals of 0.1 μm or more and 15 μm or less from the plurality of first lower wirings 81 in the second direction Y.

[0231] The wiring spacing may have a value belonging to at least one of the ranges of 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, 4.5 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, 9 μm to 10 μm, 10 μm to 11 μm, 11 μm to 12 μm, 12 μm to 13 μm, 13 μm to 14 μm, and 14 μm to 15 μm.

[0232] The layout of one second lower wiring 82 will be described below. The second lower wiring 82 preferably has both ends positioned inward (inward of the corresponding active region 6) with respect to both ends (first end and second end) of the corresponding gate structure 12 in the first direction X. The both ends of the second lower wiring 82 are preferably positioned inward with respect to the corresponding connection structures 21, 22.

[0233] Both ends of the second lower wiring 82 may be located in a region between the corresponding connection structures 21, 22 and the corresponding isolation structures 31, 32, and may face the floating region 37 in the stacking direction. Both ends of the second lower wiring 82 may be located on the corresponding isolation structures 31, 32. Both ends of the second lower wiring 82 may be located inward from the corresponding isolation structures 31, 32, and may be located on the corresponding second drain-source region 29 (second mesa portion 27).

[0234] The second lower wiring 82 may have a width greater than the width of the corresponding second mesa portion 27 in the second direction Y. That is, the second lower wiring 82 may overlap multiple (two in this embodiment) gate structures 12 located directly below it. In this case, the second lower wiring 82 preferably has a width less than the width of the corresponding second gate unit GU2. Of course, the second lower wiring 82 may have a width less than the width of the second mesa portion 27. Of course, the second lower wiring 82 may have a width greater than the width of the second gate unit GU2.

[0235] The width of the second lower wiring 82 may be 0.1 μm or more and 15 μm or less. The width of the second lower wiring 82 may have a value belonging to at least one of the ranges of 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, 4.5 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, 9 μm to 10 μm, 10 μm to 11 μm, 11 μm to 12 μm, 12 μm to 13 μm, 13 μm to 14 μm, and 14 μm to 15 μm.

[0236] It is preferable that the second lower wiring 82 has a length in the first direction X that is approximately equal to the length of the first lower wiring 81. This configuration suppresses variations in wiring resistance between the first lower wiring 81 and the second lower wiring 82. It is preferable that the second lower wiring 82 has a width in the second direction Y that is approximately equal to the width of the first lower wiring 81. This configuration suppresses variations in wiring resistance between the first lower wiring 81 and the second lower wiring 82.

[0237] Thus, in each wiring group 80, the first drain-source potential is applied to the plurality of first drain-source regions 28 via the plurality of first lower wirings 81, and the second drain-source potential is applied to the second drain-source region 29 via the plurality of second lower wirings 82. In other words, the first drain-source potential and the second drain-source potential are applied alternately in the second direction Y in accordance with the layout of the plurality of first lower wirings 81 and the plurality of second lower wirings 82. Therefore, the drain-source current Ids is input and output alternately in the second direction Y accordingly.

[0238] The semiconductor device 1A (first layer wiring 74) includes a plurality of inter-wiring regions IWR defined in regions between a plurality of wiring groups 80. The plurality of inter-wiring regions IWR are defined as regions between an end of one wiring group 80 and an end of the other wiring group 80. The end of each wiring group 80 is formed by the ends of a plurality of first lower wirings 81 and the ends of a plurality of second lower wirings 82. The inter-wiring region IWR does not have the first lower wirings 81 or the second lower wirings 82.

[0239] The plurality of inter-wiring regions IWR are each partitioned into strips extending in the second direction Y, and expose the first interlayer film 71. The plurality of inter-wiring regions IWR face the plurality of boundary regions 7a in a one-to-one correspondence in the stacking direction, and extend in strips along the corresponding boundary regions 7a. Each inter-wiring region IWR preferably exposes first ends (plurality of first connection structures 21) and second ends (plurality of second connection structures 22) of the plurality of gate structures 12 adjacent to each other in the first direction X in plan view.

[0240] The semiconductor device 1A (first layer wiring 74) includes one or more (one in this embodiment) third lower wirings 83 and one or more (one in this embodiment) fourth lower wirings 84. The third lower wiring 83 transmits a gate potential to the gate structure 12. The fourth lower wiring 84 transmits a base potential to the base structure 55. The third lower wiring 83 may be referred to as a "gate wiring." The fourth lower wiring 84 may be referred to as a "base wiring."

[0241] The third lower wiring 83 is disposed above the outer region 7 at a distance from the plurality of wiring groups 80. The third lower wiring 83 is routed inside and outside the plurality of inter-wiring regions IWR. Specifically, the third lower wiring 83 includes a plurality of first gate wirings 85, a plurality of second gate wirings 86, and at least one (one in this embodiment) third gate wiring 87.

[0242] The plurality of first gate wirings 85 are each arranged on one side of the plurality of active regions 6 in the first direction X. The plurality of first gate wirings 85 extend in a strip-like shape in the second direction Y so as to intersect (orthogonal in this embodiment) with the first ends of the plurality of gate structures 12, and are electrically connected to the first ends of the plurality of gate structures 12.

[0243] That is, the first gate wiring 85 for the first active region 6A extends in a strip shape in the second direction Y in the peripheral region 7b and intersects with first ends of the plurality of gate structures 12. The first gate wiring 85 for the first active region 6A faces the plurality of wiring groups 80 (both the plurality of first lower wirings 81 and the plurality of second lower wirings 82) in the first direction X.

[0244] The plurality of first gate wirings 85 for the second to sixth active regions 6B to 6F extend in strip shapes in the second direction Y in the corresponding boundary regions 7a (inter-wiring regions IWR) and intersect (specifically, perpendicular to) first ends of the plurality of gate structures 12. The first gate wirings 85 for the second to sixth active regions 6B to 6F face the plurality of wiring groups 80 (both the plurality of first lower wirings 81 and the plurality of second lower wirings 82) on both sides in the first direction X.

[0245] In this embodiment, the plurality of first gate wirings 85 extend in a strip shape along the plurality of first connection structures 21 and collectively cover the plurality of first connection structures 21. The plurality of first gate wirings 85 are electrically connected to the plurality of first connection structures 21 and apply a gate potential to the plurality of gate structures 12 via the plurality of first connection structures 21. The plurality of first gate wirings 85 have a first end on one side in the second direction Y and a second end on the other side in the second direction Y.

[0246] In this embodiment, the plurality of first gate wirings 85 are arranged only in the corresponding inter-wiring regions IWR, and do not have any portions located within the wiring groups 80 (regions between the first lower wirings 81 and the second lower wirings 82). In other words, the plurality of first gate wirings 85 do not have any portions that cross adjacent wiring groups 80 in the first direction X. In this embodiment, the plurality of first gate wirings 85 do not have any portions that extend in the first direction X within the inter-wiring regions IWR. Of course, the plurality of first gate wirings 85 may have portions that meander on one side and the other side in the first direction X within the inter-wiring regions IWR.

[0247] The second gate wirings 86 are each disposed on the other side of the active regions 6 in the first direction X, and face the first gate wirings 85 across the active regions 6 corresponding to the first direction X. The second gate wirings 86 extend in a strip shape in the second direction Y so as to intersect (orthogonal in this embodiment) with the second ends of the gate structures 12, and are electrically connected to the second ends of the gate structures 12.

[0248] That is, the second gate wirings 86 for the first to fifth active regions 6B to 6E extend in a strip shape in the second direction Y in the corresponding boundary regions 7a (inter-wire regions IWR) and intersect with second ends of the plurality of gate structures 12. The second gate wirings 86 for the first to fifth active regions 6B to 6E face the plurality of wiring groups 80 (both the plurality of first lower wirings 81 and the plurality of second lower wirings 82) on both sides in the first direction X.

[0249] The second gate wiring 86 for the sixth active region 6F extends in a strip shape in the second direction Y in the peripheral region 7b and intersects (specifically, is perpendicular to) second ends of the plurality of gate structures 12. The second gate wiring 86 for the sixth active region 6F faces the plurality of wiring groups 80 (both the plurality of first lower wirings 81 and the plurality of second lower wirings 82) in the first direction X.

[0250] In this embodiment, the second gate wirings 86 extend in a strip shape along the second connection structures 22, and collectively cover the second connection structures 22. The second gate wirings 86 are electrically connected to the second connection structures 22, and apply a gate potential to the gate structures 12 via the second connection structures 22.

[0251] The second gate wirings 86 are each disposed in the corresponding inter-wiring region IWR at intervals in the first direction X from the first gate wiring 85, and extend substantially parallel to the first gate wiring 85. The second gate wirings 86 each have a first end on one side in the second direction Y and a second end on the other side in the second direction Y.

[0252] The third gate wiring 87 is arranged on the outer peripheral region 7b in a region on one side in the second direction Y of the plurality of wiring groups 80, and faces the plurality of wiring groups 80 in the second direction Y. The third gate wiring 87 extends in a strip shape in the first direction X, and is connected to first ends of the plurality of first gate wirings 85 and first ends of the plurality of second gate wirings 86.

[0253] That is, the third gate wiring 87 connects the plurality of first gate wirings 85 and the plurality of second gate wirings 86 in a comb-tooth shape toward the plurality of inter-wiring regions IWR (boundary region 7a). The third gate wiring 87 is formed as an extension portion extended from the plurality of first gate wirings 85 and the plurality of second gate wirings 86 to the outer circumferential region 7b. The second ends of the plurality of first gate wirings 85 and the second ends of the plurality of second gate wirings 86 are formed as open ends.

[0254] The third gate wiring 87 is arranged in a region between the multiple active regions 6 (multiple gate structures 12) and the innermost field structure 42. The third gate wiring 87 is arranged at a distance from the first ends (open ends) of the multiple first base structures 55a to one side in the second direction Y (the field structure 42 side), and faces the first ends (open ends) of the multiple first base structures 55a in the second direction Y. In other words, the region between the first ends of the multiple first base structures 55a and the second base structure 55b is formed as a wiring path for the third gate wiring 87 (third lower wiring 83).

[0255] The fourth lower wiring 84 is arranged above the outer region 7 at a distance from the plurality of wiring groups 80. The fourth lower wiring 84 is arranged in the outer region 7 at a position overlapping the base structure 55, and is routed inside and outside the plurality of inter-wire regions IWR. Specifically, the fourth lower wiring 84 includes a plurality of first base wirings 88 and at least one (one in this embodiment) second base wiring 89.

[0256] The plurality of first base wirings 88 are respectively disposed on the corresponding first base structures 55 a in the plurality of inter-wire regions IWR (boundary region 7 a) and are electrically connected to the corresponding first base structures 55 a. The plurality of first base wirings 88 are respectively disposed in the regions between the first gate wirings 85 and the second gate wirings 86 in the corresponding inter-wire regions IWR and face the first gate wirings 85 and the second gate wirings 86 on both sides in the first direction X.

[0257] The multiple first base wirings 88 each extend in a strip shape in the second direction Y along the first base structure 55a in a region between the corresponding first gate wirings 85 and second gate wirings 86. Each of the multiple first base wirings 88 has a first end on one side in the second direction Y and a second end on the other side in the second direction Y. The first ends of the multiple first base wirings 88 are formed at a distance from the third lower wiring 83 (third gate wiring 87) on the other side in the second direction Y, and face the third lower wiring 83 (third gate wiring 87) in the second direction Y.

[0258] In this embodiment, the multiple first base wirings 88 are arranged only in the corresponding inter-wire regions IWR, and do not have any portions located within the wiring groups 80 (regions between the first lower wirings 81 and the second lower wirings 82). In other words, the multiple first base wirings 88 do not have any portions that cross adjacent wiring groups 80 in the first direction X. In this embodiment, the multiple first base wirings 88 do not have any portions that extend in the first direction X within the inter-wire regions IWR. Of course, the multiple first base wirings 88 may have portions that meander on one side and the other side of the first direction X within the inter-wire regions IWR.

[0259] The second base wiring 89 is disposed on the second base structure 55b in the peripheral region 7b and is electrically connected to the second base structure 55b. The second base structure 55b is disposed in a region between the active regions 6 (the gate structures 12) and the innermost field structure 42, and extends in a strip shape along the second base structure 55b. Specifically, the second base structure 55b is disposed in a region between the third lower wiring 83 and the innermost field structure 42.

[0260] In this embodiment, the second base structure 55b has a portion extending in a strip shape in the first direction X along the second base structure 55b and a portion extending in a strip shape in the second direction Y. In this embodiment, the second base structure 55b collectively surrounds the plurality of active regions 6 (the plurality of gate structures 12) along the second base structure 55b and is partitioned into a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the chip 2. The second base structure 55b faces the plurality of wiring groups 80 in the first direction X and the second direction Y.

[0261] The second base wiring 89 is connected to second ends of the plurality of first base wirings 88 on the other side in the second direction Y. That is, the second base wiring 89 connects the plurality of first base wirings 88 in a comb-teeth shape toward the plurality of inter-wire regions IWR. The plurality of first base wirings 88 are connected in a comb-teeth shape that meshes with the plurality of first gate wirings 85 and the plurality of second gate wirings 86. The second base wiring 89 is formed as an extension portion that is extended from the plurality of first base wirings 88 to the outer circumferential region 7 b.

[0262] The second base wiring 89 is formed at a distance in the second direction Y from the second ends (open ends) of the plurality of first gate wirings 85 and the second ends (open ends) of the plurality of second gate wirings 86, and faces the second ends (open ends) of the plurality of first gate wirings 85 and the second ends (open ends) of the plurality of second gate wirings 86 in the second direction Y.

[0263] For example, when a base potential is applied to a plurality of field structures 42, the second base wiring 89 (fourth lower wiring 84) collectively covers the plurality of field structures 42 and is electrically connected to the plurality of field structures 42. When the plurality of field structures 42 are formed in an electrically floating state, no electrical connection portion of the second base wiring 89 (fourth lower wiring 84) to the plurality of field structures 42 is formed.

[0264] In this case, the second base wiring 89 (fourth lower wiring 84) may be arranged in a region directly above the plurality of field structures 42, and may face the plurality of field structures 42 across the first interlayer film 71. Of course, the second base wiring 89 (fourth lower wiring 84) may also be arranged inwardly at a distance from the plurality of field structures 42.

[0265] The multilayer wiring structure 73 (semiconductor device 1A) includes a plurality of via electrodes 91 to 94 embedded in a first interlayer film 71. The plurality of via electrodes 91 to 94 includes a plurality of first via electrodes 91, a plurality of second via electrodes 92, a plurality of third via electrodes 93, and at least one fourth via electrode 94 (one in this embodiment).

[0266] The first via electrode 91 is a plug electrode that transmits a first drain source potential to the first drain source region 28. The second via electrode 92 is a plug electrode that transmits a second drain source potential to the second drain source region 29. The third via electrode 93 is a plug electrode that transmits a gate potential to the gate structure 12 (connection structures 21, 22). The fourth via electrode 94 is a plug electrode that transmits a base potential to the base structure 55.

[0267] The first via electrode 91 may be referred to as a "first drain-source via electrode." The second via electrode 92 may be referred to as a "second drain-source via electrode." The third via electrode 93 may be referred to as a "gate via electrode." The fourth via electrode 94 may be referred to as a "base via electrode."

[0268] In this embodiment, the multiple via electrodes 91 to 94 each include a first electrode 95 and a second electrode 96. The first electrode 95 coats the wall surface of the via hole formed in the first interlayer film 71 in the form of a film. The first electrode 95 may include either or both of a Ti film and a Ti alloy film. The Ti alloy film may be a TiN film.

[0269] The second electrode 96 is embedded in the via hole via the first electrode 95. The second electrode 96 may include at least one of W, Al, an Al alloy, Cu, and a Cu alloy. The Al alloy may include at least one of an AlSi alloy, an AlCu alloy, and an AlSiCu alloy.

[0270] The plurality of first via electrodes 91 are interposed in the first interlayer film 71 in regions between the plurality of first drain source regions 28 and the plurality of first lower interconnections 81, and electrically connect the plurality of first lower interconnections 81 to the corresponding first drain source regions 28. The multilayer wiring structure 73 only needs to have at least one first via electrode 91 in the region between one first lower interconnection 81 and one first drain source region 28.

[0271] In this embodiment, a plurality of first via electrodes 91 are interposed in regions between corresponding first lower wirings 81 and first drain-source regions 28, and are arranged at intervals in the first direction X. The first via electrodes 91 may be formed in a triangular, quadrangular, rectangular, polygonal, circular, or elliptical shape in plan view. Of course, the first via electrodes 91 may also be formed in a strip shape (e.g., a rectangular shape) extending in the first direction X.

[0272] The first via electrode 91 may be formed by utilizing the first lower wiring 81. In this case, the first electrode 95 of the first via electrode 91 is formed integrally with the first electrode 76 of the first lower wiring 81, and forms one electrode film together with the first electrode 76. Similarly, the second electrode 96 of the first via electrode 91 is formed integrally with the second electrode 77 of the first lower wiring 81, and forms one electrode together with the second electrode 77.

[0273] The plurality of second via electrodes 92 are interposed in the first interlayer film 71 in regions between the plurality of second drain source regions 29 and the plurality of second lower wirings 82, and electrically connect the plurality of second lower wirings 82 to the corresponding second drain source regions 29. The multilayer wiring structure 73 is only required to have at least one second via electrode 92 in the region between one second lower wiring 82 and one second drain source region 29.

[0274] In this embodiment, a plurality of second via electrodes 92 are interposed in the region between the corresponding first lower wiring 81 and first drain-source region 28, and are arranged at intervals in the first direction X. The second via electrodes 92 may be formed in a triangular, quadrangular, rectangular, polygonal, circular, or elliptical shape in a plan view. Of course, the second via electrodes 92 may also be formed in a strip shape (e.g., a rectangular shape) extending in the first direction X.

[0275] The second via electrode 92 may be formed by utilizing the second lower wiring 82. In this case, the first electrode 95 of the second via electrode 92 is formed integrally with the first electrode 76 of the second lower wiring 82, and forms one electrode film together with the first electrode 76. Similarly, the second electrode 96 of the second via electrode 92 is formed integrally with the second electrode 77 of the second lower wiring 82, and forms one electrode together with the second electrode 77.

[0276] The plurality of third via electrodes 93 are interposed in the first interlayer film 71 in regions between the plurality of gate structures 12 (the plurality of connection structures 21, 22) and the third lower wiring 83, and electrically connect the third lower wiring 83 to the plurality of gate structures 12 (the plurality of connection structures 21, 22). The multilayer wiring structure 73 is only required to have at least one third via electrode 93 for one gate structure 12 (connection structure 21, 22).

[0277] In this embodiment, a plurality of third via electrodes 93 are interposed in a region between one connection structure 21, 22 and the third lower wiring 83, and are arranged at intervals in the second direction Y. The third via electrodes 93 may be formed in a triangular, quadrangular, rectangular, polygonal, circular, or elliptical shape in a plan view. Of course, the third via electrodes 93 may also be formed in a strip shape (e.g., a rectangular shape) extending in the second direction Y.

[0278] In this embodiment, the connection structures 21 and 22 are formed to be wider than the gate structure 12. Therefore, the alignment margin of the third via electrode 93 with the connection structures 21 and 22 is ensured, and the third via electrode 93 is properly connected to the connection structures 21 and 22.

[0279] The third via electrode 93 may be formed by utilizing the third lower wiring 83. In this case, the first electrode 95 of the third via electrode 93 is formed integrally with the first electrode 76 of the third lower wiring 83, and forms one electrode film together with the first electrode 76. Similarly, the second electrode 96 of the third via electrode 93 is formed integrally with the second electrode 77 of the third lower wiring 83, and forms one electrode together with the second electrode 77.

[0280] The fourth via electrode 94 is interposed in a region between the base structure 55 and the fourth lower wiring 84 in the first interlayer film 71, and electrically connects the fourth lower wiring 84 to the base structure 55. The fourth via electrode 94 is formed in a strip shape extending along the base structure 55 in a plan view. In this embodiment, the fourth via electrode 94 has a planar shape that matches the planar shape of the base structure 55 in a planar view. That is, the fourth via electrode 94 has a plurality of portions extending in strip shapes along the plurality of first base structures 55a and a portion extending in strip shape along the second base structure 55b.

[0281] Of course, the multilayer wiring structure 73 may include a plurality of fourth via electrodes 94. In this case, the plurality of fourth via electrodes 94 are arranged at intervals along the base structure 55 (fourth lower wiring 84). In this case, the fourth via electrodes 94 may be formed in a triangular, quadrangular, rectangular, polygonal, circular, or elliptical shape in a plan view. Of course, the fourth via electrodes 94 may be formed in a strip shape with ends extending along the base structure 55 (base wiring).

[0282] The fourth via electrode 94 is mechanically and electrically connected to the base electrode 57. In this embodiment, the fourth via electrode 94 is formed integrally with the base electrode 57. Specifically, the first electrode 95 of the fourth via electrode 94 is formed integrally with the first electrode 58 of the base electrode 57, and forms a single electrode film together with the first electrode 58. Similarly, the second electrode 96 of the fourth via electrode 94 is formed integrally with the second electrode 59 of the base electrode 57, and forms a single electrode together with the second electrode 59.

[0283] The fourth via electrode 94 may be formed by utilizing the fourth lower wiring 84. In this case, the first electrode 95 of the fourth via electrode 94 is formed integrally with the first electrode 76 of the fourth lower wiring 84, and forms one electrode film together with the first electrode 76. Similarly, the second electrode 96 of the fourth via electrode 94 is formed integrally with the second electrode 77 of the fourth lower wiring 84, and forms one electrode together with the second electrode 77.

[0284] When a base potential is applied to the multiple field structures 42, the multiple fourth via electrodes 94 are interposed between the second base wiring 89 (the fourth lower wiring 84) and the multiple field structures 42, electrically connecting the second base wiring 89 (the fourth lower wiring 84) to the multiple field structures 42.

[0285] 15 etc., the second layer wiring 75 includes a plurality of pad wirings 101 to 104. The plurality of pad wirings 101 to 104 includes one or more (plurality in this embodiment) first pad wirings 101, one or more (plurality in this embodiment) second pad wirings 102, one or more (one in this embodiment) third pad wirings 103, and one or more (one in this embodiment) fourth pad wirings 104.

[0286] The first pad wiring 101 applies a first drain-source potential to the first lower wiring 81. The second pad wiring 102 applies a second drain-source potential to the second lower wiring 82. The third pad wiring 103 applies a gate potential to the third lower wiring 83. The fourth pad wiring 104 applies a base potential to the fourth lower wiring 84.

[0287] The first pad wiring 101 may be referred to as a "first drain-source pad wiring." The second pad wiring 102 may be referred to as a "second drain-source pad wiring." The third pad wiring 103 may be referred to as a "gate pad wiring." The fourth pad wiring 104 may be referred to as a "base pad wiring."

[0288] The numbers of first pad wirings 101, second pad wirings 102, third pad wirings 103, and fourth pad wirings 104 are all arbitrary. In this embodiment, the multilayer wiring structure 73 (semiconductor device 1A) includes ten first pad wirings 101, ten second pad wirings 102, one third pad wiring 103, and one fourth pad wiring 104. In other words, the total number of the first to fourth pad wirings 101 to 104 is 22.

[0289] The pad wirings 101 to 104 are respectively arranged in a plurality of arrangement regions 105 set in the interlayer film 70 (see also FIG. 1 ). The arrangement regions 105 may also be referred to as "pad arrangement regions." The arrangement regions 105 are rectangular virtual regions set in a matrix (5 rows and 5 columns in this embodiment) along the first direction X and the second direction Y in a plan view. Each of the arrangement regions 105 is set on a corresponding one of the boundary regions 7 a and straddles two active regions 6 adjacent in the first direction X. The planar area of ​​the arrangement regions 105 is adjusted as appropriate depending on the planar area of ​​the chip 2, the wiring layout of the mounting board, etc.

[0290] The ten first pad wirings 101 are arranged at intervals in the first direction X in five placement regions 105 in the first row and five placement regions 105 in the fourth row. Each first pad wiring 101 is arranged on the boundary region 7 a in the corresponding placement region 105 and straddles two active regions 6 adjacent to each other in the first direction X.

[0291] The ten second pad wirings 102 are arranged at intervals in the first direction X in five placement regions 105 in the second row and five placement regions 105 in the fifth row. Each second pad wiring 102 is arranged on the boundary region 7 a in the corresponding placement region 105 and straddles two active regions 6 adjacent to each other in the first direction X.

[0292] The second pad wirings 102 arranged in the second row are opposed to the first pad wirings 101 arranged in the first row in a one-to-one correspondence in the second direction Y. Similarly, the second pad wirings 102 arranged in the fifth row are opposed to the first pad wirings 101 arranged in the fourth row in a one-to-one correspondence in the second direction Y.

[0293] The third pad wiring 103 is arranged in the third row and fifth column placement region 105. The third pad wiring 103 is set on the boundary region 7a in the corresponding placement region 105 and spans two active regions 6 adjacent in the first direction X. The third pad wiring 103 faces the second pad wiring 102 on one side in the second direction Y and faces the first pad wiring 101 on the other side in the second direction Y.

[0294] The fourth pad wiring 104 is arranged in the third row and first column placement region 105. The fourth pad wiring 104 is set on the boundary region 7a in the corresponding placement region 105 and spans two active regions 6 adjacent in the first direction X. The fourth pad wiring 104 faces the second pad wiring 102 on one side in the second direction Y and faces the first pad wiring 101 on the other side in the second direction Y.

[0295] The surplus placement regions 105 that do not have pad wirings 101 to 104 are set as space regions 106. In this configuration, the three placement regions 105 in the second to fourth columns of the third row are set as space regions 106. That is, the three second pad wirings 102 arranged in the second row face the three first pad wirings 101 arranged in the fourth row in a one-to-one correspondence in the second direction Y, with the three space regions 106 sandwiched between them. The fourth pad wiring 104 faces the third pad wiring 103 in the first direction X, with the three space regions 106 sandwiched between them.

[0296] The second-layer wiring 75 includes a plurality of first wiring units U1, a plurality of second wiring units U2, one third wiring unit U3, and one fourth wiring unit U4. The first to fourth wiring units U1 to U4 are grouped (classified) according to the layout of the first to fourth pad wirings 101 to 104, respectively.

[0297] The multiple first wiring units U1 each include a first pad wiring 101 and a second pad wiring 102 that face each other (closely face each other) in the second direction Y. That is, the second-layer wiring 75 includes ten first wiring units U1. In each first wiring unit U1, the first pad wiring 101 and the second pad wiring 102 are selectively electrically connected to the first lower wiring 81 and the second lower wiring 82 of the multiple wiring groups 80 located directly below it. The multiple first wiring units U1 each have a similar layout except that the first lower wiring 81 and the second lower wiring 82 to be connected are different.

[0298] The second wiring units U2 each include a first pad wiring 101 and a second pad wiring 102 that face each other in the second direction Y with a space region 106 interposed therebetween. That is, the second-layer wiring 75 includes three second wiring units U2. In each second wiring unit U2, the first pad wiring 101 and the second pad wiring 102 are selectively electrically connected to the first lower wiring 81 and the second lower wiring 82 of the wiring group 80 located directly below it.

[0299] The third wiring unit U3 includes a first pad wiring 101, a second pad wiring 102, and a third pad wiring 103 that face each other (closely face each other) in the second direction Y. In the third wiring unit U3, the first pad wiring 101 and the second pad wiring 102 are selectively electrically connected to the first lower wiring 81 and the second lower wiring 82 of the plurality of wiring groups 80 located directly below them. In addition, the third pad wiring 103 is electrically connected to the third lower wiring 83.

[0300] The fourth wiring unit U4 includes a first pad wiring 101, a second pad wiring 102, and a fourth pad wiring 104 that face each other (closely face each other) in the second direction Y. In the fourth wiring unit U4, the first pad wiring 101 and the second pad wiring 102 are selectively electrically connected to the first lower wiring 81 and the second lower wiring 82 of the plurality of wiring groups 80 located directly below them. In addition, the fourth pad wiring 104 is electrically connected to the fourth lower wiring 84.

[0301] 16A to 16J are enlarged plan views showing the first wiring unit U1 according to the first to tenth layout examples.

[0302] 16A to 16J illustrate a first wiring unit U1 arranged on the first side surface 5A side of the chip 2. In the following, the first wiring unit U1 shown in Fig. 16A will be described as a basic form example, and the first wiring unit U1 shown in Fig. 16B to 16J will be described as a modified example of the basic form example.

[0303] Unless otherwise specified, the following description will focus on the internal configuration of one first wiring unit U1. In the following description, a first wiring group 80A and a second wiring group 80B are used as two wiring groups 80 on one side and the other side of the first direction X, and the layout of the first wiring unit U1 relative to these wiring groups 80 is illustrated.

[0304] Of course, the following description also applies to the layout of other first wiring units U1 with respect to two adjacent wiring groups 80 of the second to sixth wiring groups 80B to 80F on one side and the other side in the first direction X. A specific configuration in this case can be obtained by replacing the first wiring group 80A and the second wiring group 80B in the following description with two adjacent wiring groups 80 of the second to fifth wiring groups 80B to 80F on one side and the other side in the first direction X.

[0305] 16A (first layout example), the first wiring unit U1 includes a placement region 105 for the first pad wiring 101 and a placement region 105 for the second pad wiring 102. Hereinafter, the placement region 105 for the first pad wiring 101 will be referred to as the "first placement region 105A," and the placement region 105 for the second pad wiring 102 will be referred to as the "second placement region 105B."

[0306] The first placement region 105A is set on one side in the second direction Y in a plan view. The first placement region 105A is set to have a quadrangular (preferably square) shape in a plan view. The first placement region 105A includes a first wiring group 80A and a second wiring group 80B that are adjacent to each other in the first direction X with an inter-wiring region IWR sandwiched therebetween.

[0307] In other words, the first placement region 105A overlaps the first active region 6A and the second active region 6B that are adjacent to each other in the first direction X, with the boundary region 7a sandwiched between them. The first placement region 105A includes at least one first lower wiring 81 belonging to the first wiring group 80A and at least one first lower wiring 81 belonging to the second wiring group 80B.

[0308] Specifically, the first placement area 105A includes at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 belonging to the first wiring group 80A, and at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 belonging to the second wiring group 80B.

[0309] In the first placement area 105A, the number of first lower wirings 81 in the first wiring group 80A, the number of second lower wirings 82 in the first wiring group 80A, the number of first lower wirings 81 in the second wiring group 80B, and the number of second lower wirings 82 in the second wiring group 80B are all arbitrary.

[0310] For example, in first wiring group 80A (second wiring group 80B) in first placement area 105A, the number of first lower wirings 81 (second lower wirings 82) may be equal to or greater than 1 and equal to or less than 1000. For example, in first wiring group 80A (second wiring group 80B) in first placement area 105A, the number of first lower wirings 81 (second lower wirings 82) may have a value belonging to at least one of the ranges of 1 to 50, 50 to 100, 100 to 250, 250 to 500, 500 to 750, and 750 to 1000.

[0311] In the first wiring group 80A in the first placement area 105A, it is preferable that the number of second lower wirings 82 is approximately equal to the number of first lower wirings 81. In the second wiring group 80B in the first placement area 105A, it is preferable that the number of second lower wirings 82 is approximately equal to the number of first lower wirings 81. In the first placement area 105A, it is preferable that the number of first lower wirings 81 in the second wiring group 80B is approximately equal to the number of first lower wirings 81 in the first wiring group 80A. It is also preferable that the number of second lower wirings 82 in the second wiring group 80B is approximately equal to the number of second lower wirings 82 in the first wiring group 80A.

[0312] In this embodiment, in both the first wiring group 80A and the second wiring group 80B, the plurality of second lower wirings 82 are arranged alternately with the plurality of first lower wirings 81. Furthermore, the first lower wirings 81 and the second lower wirings 82 of the second wiring group 80B face the first lower wirings 81 and the second lower wirings 82 of the first wiring group 80A, respectively, in the first direction X.

[0313] Therefore, in the first wiring group 80A in the first placement area 105A, the difference between the number of first lower wirings 81 and the number of second lower wirings 82 is 0 to 1. In addition, in the second wiring group 80B in the first placement area 105A, the difference between the number of first lower wirings 81 and the number of second lower wirings 82 is 0 to 1.

[0314] In the first placement area 105A, the difference between the number of first lower wirings 81 in the first wiring group 80A and the number of first lower wirings 81 in the second wiring group 80B is 0 to 1. In addition, the difference between the number of second lower wirings 82 in the first wiring group 80A and the number of second lower wirings 82 in the second wiring group 80B is 0 to 1.

[0315] The second placement region 105B is set on the other side of the first placement region 105A in the second direction Y in a plan view and is adjacent to the first placement region 105A. The second placement region 105B defines a boundary 107 with the first placement region 105A. The second placement region 105B is set to be quadrangular (preferably square) in a plan view and defines a boundary 107 extending in the first direction X. The plane area of ​​the second placement region 105B is approximately equal to the plane area of ​​the first placement region 105A.

[0316] The second placement region 105B includes a first wiring group 80A and a second wiring group 80B that are adjacent to each other in the first direction X with an inter-wiring region IWR sandwiched between them. In other words, the second placement region 105B overlaps with the first active region 6A and the second active region 6B that are adjacent to each other in the first direction X with a boundary region 7a sandwiched between them. The second placement region 105B includes at least one second lower wiring 82 that belongs to the first wiring group 80A and at least one second lower wiring 82 that belongs to the second wiring group 80B.

[0317] Specifically, the second placement area 105B includes at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 belonging to the first wiring group 80A, and at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 belonging to the second wiring group 80B.

[0318] In the second placement area 105B, the number of first lower wirings 81 in the first wiring group 80A, the number of second lower wirings 82 in the first wiring group 80A, the number of first lower wirings 81 in the second wiring group 80B, and the number of second lower wirings 82 in the second wiring group 80B are all arbitrary.

[0319] For example, in first wiring group 80A (second wiring group 80B) in second placement region 105B, the number of first lower wirings 81 (second lower wirings 82) may be equal to or greater than 1 and equal to or less than 1000. For example, in first wiring group 80A (second wiring group 80B) in second placement region 105B, the number of first lower wirings 81 (second lower wirings 82) may have a value belonging to at least one of the ranges of 1 to 50, 50 to 100, 100 to 250, 250 to 500, 500 to 750, and 750 to 1000.

[0320] In the first wiring group 80A in the second placement region 105B, it is preferable that the number of second lower wirings 82 is approximately equal to the number of first lower wirings 81. In the second wiring group 80B in the second placement region 105B, it is preferable that the number of second lower wirings 82 is approximately equal to the number of first lower wirings 81. In the second placement region 105B, it is preferable that the number of first lower wirings 81 in the second wiring group 80B is approximately equal to the number of first lower wirings 81 in the first wiring group 80A. It is also preferable that the number of second lower wirings 82 in the second wiring group 80B is approximately equal to the number of second lower wirings 82 in the first wiring group 80A.

[0321] In this embodiment, in both the first wiring group 80A and the second wiring group 80B, the plurality of second lower wirings 82 are arranged alternately with the plurality of first lower wirings 81. Furthermore, the first lower wirings 81 and the second lower wirings 82 of the second wiring group 80B face the first lower wirings 81 and the second lower wirings 82 of the first wiring group 80A, respectively, in the first direction X.

[0322] Therefore, in the first wiring group 80A in the second placement area 105B, the difference between the number of first lower wirings 81 and the number of second lower wirings 82 is 0 to 1. Also, in the second wiring group 80B in the second placement area 105B, the difference between the number of first lower wirings 81 and the number of second lower wirings 82 is 0 to 1.

[0323] In the second placement region 105B, the difference between the number of first lower wirings 81 in the first wiring group 80A and the number of first lower wirings 81 in the second wiring group 80B is 0 to 1. In addition, the difference between the number of second lower wirings 82 in the first wiring group 80A and the number of second lower wirings 82 in the second wiring group 80B is 0 to 1.

[0324] It is preferable that the first wiring group 80A in the first placement area 105A and the first wiring group 80A in the second placement area 105B have an equal number of first lower wirings 81 and an equal number of second lower wirings 82. In other words, it is preferable that the wiring resistance of the first wiring group 80A in the second placement area 105B is approximately equal to the wiring resistance of the first wiring group 80A in the first placement area 105A.

[0325] Furthermore, it is preferable that the second wiring group 80B in the first placement area 105A and the second wiring group 80B in the second placement area 105B have an equal number of first lower wirings 81 and an equal number of second lower wirings 82. In other words, it is preferable that the wiring resistance of the second wiring group 80B in the second placement area 105B is approximately equal to the wiring resistance of the second wiring group 80B in the first placement area 105A.

[0326] The first wiring unit U1 includes a first pad wiring 101 arranged in the first placement region 105A. The first pad wiring 101 has a planar area smaller than the planar area of ​​the first placement region 105A. The first pad wiring 101 is arranged at a distance inward from the periphery of the first placement region 105A in a plan view, and is formed in a polygonal shape having four sides parallel to the periphery of the chip 2 (the periphery of the first placement region 105A). The first pad wiring 101 is biased to one side in the first direction X with respect to the center of the boundary 107, and is biased to one side in the second direction Y with respect to the boundary 107.

[0327] The first pad wiring 101 is arranged on the first wiring group 80A and the second wiring group 80B that are adjacent to each other in the first direction X with the inter-wiring region IWR in between. That is, the first pad wiring 101 is arranged on the inter-wiring region IWR and is drawn out onto the first wiring group 80A and the second wiring group 80B that are adjacent to each other in the first direction X. In other words, the first pad wiring 101 is arranged on the first active region 6A and the second active region 6B that are adjacent to each other in the first direction X with the boundary region 7a in between.

[0328] The first pad wiring 101 faces the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR across the second interlayer film 72. The first pad wiring 101 is electrically connected to at least one first lower wiring 81 of the first wiring group 80A and at least one first lower wiring 81 of the second wiring group 80B.

[0329] Specifically, the first pad wiring 101 has a first end on one side in the first direction X and a second end on the other side in the first direction X. The first end of the first pad wiring 101 is disposed on the first wiring group 80A. The first end of the first pad wiring 101 is disposed on at least one (in this embodiment, multiple) first lower wiring 81 of the first wiring group 80A and is electrically connected to at least one (in this embodiment, multiple) first lower wiring 81 of the first wiring group 80A.

[0330] In this embodiment, the first end of the first pad wiring 101 overlaps at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A. The first end of the first pad wiring 101 is electrically isolated from all of the second lower wirings 82 of the first wiring group 80A.

[0331] A second end of the first pad wiring 101 is disposed on the second wiring group 80B. The second end of the first pad wiring 101 is disposed on at least one (in this embodiment, a plurality) first lower wiring 81 of the second wiring group 80B, and is electrically connected to at least one (in this embodiment, a plurality) first lower wiring 81 of the second wiring group 80B.

[0332] In this embodiment, the second end of the first pad wiring 101 overlaps at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the second wiring group 80B. The second end of the first pad wiring 101 is electrically isolated from all of the second lower wirings 82 of the second wiring group 80B.

[0333] The first pad wiring 101 is electrically connected to both the first lower wiring 81 of the first wiring group 80A and the first lower wiring 81 of the second wiring group 80B across the inter-wiring region IWR. Therefore, the current path connecting the first lower wiring 81 of the first wiring group 80A to the first pad wiring 101 is shortened, and the current path connecting the first lower wiring 81 of the second wiring group 80B to the first pad wiring 101 is shortened. This reduces the wiring resistance between the first pad wiring 101 and the first lower wiring 81 of the first wiring group 80A, and reduces the wiring resistance between the first pad wiring 101 and the first lower wiring 81 of the second wiring group 80B.

[0334] Directly below the first pad wiring 101, the number of first lower wirings 81 in the first wiring group 80A, the number of second lower wirings 82 in the first wiring group 80A, the number of first lower wirings 81 in the second wiring group 80B, and the number of second lower wirings 82 in the second wiring group 80B are all arbitrary.

[0335] For example, in first wiring group 80A (second wiring group 80B) directly below first pad wiring 101, the number of first lower wirings 81 (second lower wirings 82) may be 1 or more and 1000 or less. For example, in first wiring group 80A (second wiring group 80B) directly below first pad wiring 101, the number of first lower wirings 81 (second lower wirings 82) may have a value belonging to at least one of the ranges of 1 or more and 50 or less, 50 or more and 100 or less, 100 or more and 250 or less, 250 or more and 500 or less, 500 or more and 750 or less, and 750 or more and 1000 or less.

[0336] In the first wiring group 80A directly below the first pad wiring 101, the number of second lower wirings 82 is preferably approximately equal to the number of first lower wirings 81. In the second wiring group 80B directly below the first pad wiring 101, the number of second lower wirings 82 is preferably approximately equal to the number of first lower wirings 81. Directly below the first pad wiring 101, the number of first lower wirings 81 in the second wiring group 80B is preferably approximately equal to the number of first lower wirings 81 in the first wiring group 80A. Furthermore, the number of second lower wirings 82 in the second wiring group 80B is preferably approximately equal to the number of second lower wirings 82 in the first wiring group 80A.

[0337] In this embodiment, in both the first wiring group 80A and the second wiring group 80B, the plurality of second lower wirings 82 are arranged alternately with the plurality of first lower wirings 81. Furthermore, the first lower wirings 81 and the second lower wirings 82 of the second wiring group 80B face the first lower wirings 81 and the second lower wirings 82 of the first wiring group 80A, respectively, in the first direction X.

[0338] Therefore, in first wiring group 80A directly below first pad wiring 101, the difference between the number of first lower wirings 81 and the number of second lower wirings 82 is 0 to 1. Also, in second wiring group 80B directly below first pad wiring 101, the difference between the number of first lower wirings 81 and the number of second lower wirings 82 is 0 to 1.

[0339] In the first pad wiring 101, the difference between the number of first lower wirings 81 in the first wiring group 80A and the number of first lower wirings 81 in the second wiring group 80B is 0 to 1. In addition, the difference between the number of second lower wirings 82 in the first wiring group 80A and the number of second lower wirings 82 in the second wiring group 80B is 0 to 1.

[0340] That is, in the first wiring group 80A (second wiring group 80B) directly below the first pad wiring 101, variations in wiring resistance between the first lower wirings 81 and the second lower wirings 82 are suppressed. Also, variations in wiring resistance between the first wiring group 80A and the second wiring group 80B are suppressed directly below the first pad wiring 101. With regard to the first wiring group 80A directly below the first end of the first pad wiring 101 and the second wiring group 80B directly below the second end of the first pad wiring 101, it is preferable that the numbers of first lower wirings 81 and second lower wirings 82 are equal to each other.

[0341] The first pad wiring 101 overlaps the third lower wiring 83 in a portion covering the inter-wiring region IWR. In this configuration, the first pad wiring 101 overlaps both the first gate wiring 85 and the second gate wiring 86. The first pad wiring 101 faces the third lower wiring 83 (the first gate wiring 85 and the second gate wiring 86) with the second interlayer film 72 interposed therebetween and is electrically isolated from the third lower wiring 83.

[0342] The first pad wiring 101 overlaps the fourth lower wiring 84 in a portion covering the inter-wiring region IWR. In this embodiment, the first pad wiring 101 overlaps the first base wiring 88. The first pad wiring 101 faces the fourth lower wiring 84 (first base wiring 88) with the second interlayer film 72 interposed therebetween, and is electrically isolated from the fourth lower wiring 84.

[0343] The first wiring unit U1 includes a second pad wiring 102 arranged in the second placement region 105B at a distance from the first pad wiring 101 (first placement region 105A) on the other side in the second direction Y. The second pad wiring 102 has a planar area smaller than the planar area of ​​the second placement region 105B. The second pad wiring 102 is arranged at a distance inward from the periphery of the second placement region 105B in a plan view, and is formed in a polygonal shape having four sides parallel to the periphery of the chip 2 (the periphery of the second placement region 105B).

[0344] The second pad wiring 102 is biased toward the other side in the first direction X with respect to the center of the first pad wiring 101 (the center of the boundary 107), and is biased toward the other side in the second direction Y with respect to the boundary 107. It is preferable that the distance between the second pad wiring 102 and the boundary 107 is approximately equal to the distance between the first pad wiring 101 and the boundary 107. In other words, it is preferable that the boundary 107 is located approximately midway between the first pad wiring 101 and the second pad wiring 102.

[0345] The second pad wiring 102 preferably has a planar layout that is substantially congruent with the planar layout of the first pad wiring 101. In other words, it is preferable that the planar shape of the second pad wiring 102 is substantially equal to the planar shape of the first pad wiring 101, and the planar area of ​​the second pad wiring 102 is substantially equal to the planar area of ​​the first pad wiring 101. The second pad wiring 102 is preferably arranged point-symmetrically with respect to the first pad wiring 101, with the center of the boundary portion 107 as the center.

[0346] The second pad wiring 102 is arranged on the first wiring group 80A and the second wiring group 80B that are adjacent to each other in the first direction X with the inter-wiring region IWR in between. That is, the second pad wiring 102 is arranged on the inter-wiring region IWR and is drawn out onto the first wiring group 80A and the second wiring group 80B that are adjacent to each other in the first direction X. In other words, the second pad wiring 102 is arranged on the first active region 6A and the second active region 6B that are adjacent to each other in the first direction X with the boundary region 7a in between.

[0347] The second pad wiring 102 faces the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR across the second interlayer film 72. The second pad wiring 102 is electrically connected to at least one second lower wiring 82 of the first wiring group 80A and at least one second lower wiring 82 of the second wiring group 80B.

[0348] Specifically, the second pad wiring 102 has a first end on one side in the first direction X and a second end on the other side in the first direction X. The first end of the second pad wiring 102 is disposed on the first wiring group 80A. The first end of the second pad wiring 102 is disposed on at least one (in this embodiment, multiple) second lower wiring 82 of the first wiring group 80A and is electrically connected to at least one (in this embodiment, multiple) second lower wiring 82 of the first wiring group 80A.

[0349] In this embodiment, the first end of the second pad wiring 102 overlaps at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A. The first end of the second pad wiring 102 is electrically isolated from all of the first lower wirings 81 of the first wiring group 80A.

[0350] A second end of the second pad wiring 102 is disposed on the second wiring group 80B. The second end of the second pad wiring 102 is disposed on at least one (in this embodiment, multiple) second lower wiring 82 of the second wiring group 80B, and is electrically connected to at least one (in this embodiment, multiple) second lower wiring 82 of the second wiring group 80B.

[0351] In this embodiment, the second end of the second pad wiring 102 overlaps at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the second wiring group 80B. The second end of the second pad wiring 102 is electrically isolated from all of the first lower wirings 81 of the second wiring group 80B.

[0352] The second pad wiring 102 is electrically connected to both the second lower wiring 82 of the first wiring group 80A and the second lower wiring 82 of the second wiring group 80B across the inter-wiring region IWR. Therefore, the current path connecting the second lower wiring 82 of the first wiring group 80A to the second pad wiring 102 is shortened, and the current path connecting the second lower wiring 82 of the second wiring group 80B to the second pad wiring 102 is shortened. This reduces the wiring resistance between the second pad wiring 102 and the second lower wiring 82 of the first wiring group 80A, and reduces the wiring resistance between the second pad wiring 102 and the second lower wiring 82 of the second wiring group 80B.

[0353] Directly below the second pad wiring 102, the number of first lower wirings 81 of the first wiring group 80A, the number of second lower wirings 82 of the first wiring group 80A, the number of first lower wirings 81 of the second wiring group 80B, and the number of second lower wirings 82 of the second wiring group 80B are all arbitrary.

[0354] For example, in first wiring group 80A (second wiring group 80B) directly below second pad wiring 102, the number of first lower wirings 81 (second lower wirings 82) may be 1 or more and 1000 or less. For example, in first wiring group 80A (second wiring group 80B) directly below second pad wiring 102, the number of first lower wirings 81 (second lower wirings 82) may have a value belonging to at least one of the ranges of 1 or more and 50 or less, 50 or more and 100 or less, 100 or more and 250 or less, 250 or more and 500 or less, 500 or more and 750 or less, and 750 or more and 1000 or less.

[0355] In the first wiring group 80A directly below the second pad wiring 102, the number of second lower wirings 82 is preferably approximately equal to the number of first lower wirings 81. In the second wiring group 80B directly below the second pad wiring 102, the number of second lower wirings 82 is preferably approximately equal to the number of first lower wirings 81. Directly below the second pad wiring 102, the number of first lower wirings 81 in the second wiring group 80B is preferably approximately equal to the number of first lower wirings 81 in the first wiring group 80A. Furthermore, the number of second lower wirings 82 in the second wiring group 80B is preferably approximately equal to the number of second lower wirings 82 in the first wiring group 80A.

[0356] In this embodiment, in both the first wiring group 80A and the second wiring group 80B, the plurality of second lower wirings 82 are arranged alternately with the plurality of first lower wirings 81. Furthermore, the first lower wirings 81 and the second lower wirings 82 of the second wiring group 80B face the first lower wirings 81 and the second lower wirings 82 of the first wiring group 80A, respectively, in the first direction X.

[0357] Therefore, in the first wiring group 80A directly below the second pad wiring 102, the difference between the number of first lower wirings 81 and the number of second lower wirings 82 is 0 to 1. In addition, in the second wiring group 80B directly below the second pad wiring 102, the difference between the number of first lower wirings 81 and the number of second lower wirings 82 is 0 to 1.

[0358] Moreover, directly below the second pad wiring 102, the difference between the number of first lower wirings 81 in the first wiring group 80A and the number of first lower wirings 81 in the second wiring group 80B is 0 to 1. Also, the difference between the number of second lower wirings 82 in the first wiring group 80A and the number of second lower wirings 82 in the second wiring group 80B is 0 to 1.

[0359] That is, in the first wiring group 80A (second wiring group 80B) directly below the second pad wiring 102, variations in wiring resistance between the first lower wirings 81 and the second lower wirings 82 are suppressed. Also, variations in wiring resistance between the first wiring group 80A and the second wiring group 80B are suppressed directly below the second pad wiring 102. With regard to the first wiring group 80A directly below the first end of the second pad wiring 102 and the second wiring group 80B directly below the second end of the second pad wiring 102, it is preferable that the numbers of first lower wirings 81 and second lower wirings 82 are equal to each other.

[0360] It is preferable that the first wiring group 80A directly below the first pad wiring 101 and the first wiring group 80A directly below the second pad wiring 102 have the same number of first lower wirings 81 and the same number of second lower wirings 82. In other words, it is preferable that the wiring resistance of the first wiring group 80A directly below the second pad wiring 102 is approximately equal to the wiring resistance of the first wiring group 80A directly below the first pad wiring 101.

[0361] It is preferable that the second wiring group 80B directly below the first pad wiring 101 and the second wiring group 80B directly below the second pad wiring 102 have the same number of first lower wirings 81 and the same number of second lower wirings 82. In other words, it is preferable that the wiring resistance of the second wiring group 80B directly below the second pad wiring 102 is approximately equal to the wiring resistance of the second wiring group 80B directly below the first pad wiring 101.

[0362] The second pad wiring 102 overlaps the third lower wiring 83 in a portion covering the inter-wiring region IWR. In this configuration, the second pad wiring 102 overlaps both the first gate wiring 85 and the second gate wiring 86. The second pad wiring 102 faces the third lower wiring 83 (the first gate wiring 85 and the second gate wiring 86) with the second interlayer film 72 interposed therebetween, and is electrically isolated from the third lower wiring 83.

[0363] The second pad wiring 102 overlaps the fourth lower wiring 84 in a portion covering the inter-wiring region IWR. In this embodiment, the second pad wiring 102 overlaps the first base wiring 88. The second pad wiring 102 faces the fourth lower wiring 84 (first base wiring 88) with the second interlayer film 72 interposed therebetween, and is electrically isolated from the fourth lower wiring 84.

[0364] The first wiring unit U1 includes a first interconnect structure 108 formed in a region between the first pad wiring 101 and the second pad wiring 102. The first interconnect structure 108 forms a current path for the drain-source current Ids between the first pad wiring 101 and the second pad wiring 102.

[0365] The first interconnect structure 108 includes at least one (in this embodiment, a plurality) first interconnect lines 109 that are extended in the second direction Y from the first pad interconnect 101 toward the second pad interconnect 102. The plurality of first interconnect lines 109 are electrically connected to either or both of the at least one first lower interconnect 81 of the first interconnect group 80A and the at least one first lower interconnect 81 of the second interconnect group 80B in a region between the first pad interconnect 101 and the second pad interconnect 102.

[0366] The plurality of first lead-out wirings 109 include at least one (one in this embodiment) first long wiring 110 that is relatively long, and at least one (plural in this embodiment) first short wiring 111 that is shorter than the first long wiring 110. The first long wiring 110 may be referred to as a "first long lead-out wiring" or a "first main lead-out wiring," etc. The first short wiring 111 may be referred to as a "first short lead-out wiring" or a "first sub lead-out wiring," etc.

[0367] The number of first shorting wires 111 is arbitrary and is adjusted appropriately depending on the size of the first pad wires 101, etc. The number of first shorting wires 111 may be 1 to 50 inclusive. The number of first shorting wires 111 may have a value belonging to at least one of the following ranges: 1 to 5 inclusive, 5 to 10 inclusive, 10 to 20 inclusive, 20 to 30 inclusive, 30 to 40 inclusive, and 40 to 50 inclusive. In this embodiment, two first shorting wires 111 are provided.

[0368] The first long wiring 110 has a width in the first direction X that is less than the width of the first pad wiring 101 (second pad wiring 102), and is drawn out in a strip shape in the second direction Y from a first end of the first pad wiring 101 toward the top of the first wiring group 80A (first active region 6A). The width of the first long wiring 110 is greater than the width of the first lower wiring 81 (second lower wiring 82). In this embodiment, the first long wiring 110 intersects (is perpendicular to) at least one (plural in this embodiment) first lower wiring 81 and at least one (plural in this embodiment) second lower wiring 82 of the first wiring group 80A in the first placement region 105A.

[0369] The first long wiring 110 crosses the boundary 107 in the second direction Y and is drawn out from the first placement region 105A to the second placement region 105B. In this embodiment, the first long wiring 110 intersects (is perpendicular to) at least one (a plurality of in this embodiment) first lower wirings 81 and at least one (a plurality of in this embodiment) second lower wirings 82 in both the first placement region 105A and the second placement region 105B.

[0370] The first long wiring 110 is electrically connected to at least one (plurality in this embodiment) first lower wiring 81 of the first wiring group 80A in the first placement region 105A. Also, the first long wiring 110 is electrically connected to at least one (plurality in this embodiment) first lower wiring 81 of the first wiring group 80A in the second placement region 105B.

[0371] The first long wiring 110 has a first opposing portion 112 that is drawn in the second direction Y to a region that opposes the second pad wiring 102 in the first direction X. The first opposing portion 112 opposes the entire first end portion of the second pad wiring 102 in the first direction X. With respect to the first wiring group 80A, the first opposing portion 112 (first long wiring 110) intersects (is perpendicular to) one or more (preferably all) first lower wirings 81 and one or more (preferably all) second lower wirings 82 that pass directly below the second pad wiring 102 in the first direction X.

[0372] The first opposing portion 112 is electrically connected to a portion of one or more (preferably all) first lower wirings 81 covered by the second pad wiring 102 that is exposed from the second pad wiring 102. On the other hand, the first opposing portion 112 is electrically isolated from one or more (preferably all) second lower wirings 82 that pass directly below the second pad wiring 102.

[0373] The first long wiring 110 forms a current path of the drain-source current Ids together with the second pad wiring 102 opposing (closely opposing) in the first direction X. Specifically, the current path of the drain-source current Ids is formed between the second pad wiring 102 and the first long wiring 110 via the first lower wiring 81 and the second lower wiring 82 passing directly below both the second pad wiring 102 and the first long wiring 110 in the first direction X. Such a layout is effective in reducing the wiring resistance between the first pad wiring 101 and the second pad wiring 102.

[0374] The multiple first short wirings 111 each have a width in the first direction X that is less than the width of the first pad wiring 101 (second pad wiring 102), and are provided in a region on the second end side with respect to the first long wiring 110. The width of the first short wiring 111 may be approximately equal to the width of the first long wiring 110. The width of the first short wiring 111 may be greater than the width of the first long wiring 110. The width of the first short wiring 111 may be less than the width of the first long wiring 110. The width of the first short wiring 111 is greater than the width of the first lower wiring 81 (second lower wiring 82).

[0375] The multiple first shorting wires 111 are arranged at intervals in the first direction X, and are drawn out in a strip shape (rectangular in this embodiment) in the second direction Y from the first pad wire 101 toward the second pad wire 102. The multiple first shorting wires 111 may be drawn out in a trapezoidal shape (preferably an isosceles trapezoidal shape) or a triangular shape (preferably an isosceles triangle shape).

[0376] The multiple first short wirings 111 are arranged in a comb-tooth shape extending in the second direction Y, and face each other in the first direction X. The multiple first short wirings 111 face the first long wiring 110 in the first direction X. The multiple first short wirings 111 are formed at intervals from the second pad wiring 102 toward the first pad wiring 101, and face the second pad wiring 102 in the second direction Y.

[0377] The multiple first shorting wires 111 are electrically connected to at least one (multiple in this embodiment) first lower wire 81 in the region between the first pad wire 101 and the second pad wire 102. Specifically, the multiple first shorting wires 111 include one or more (one in this embodiment) first shorting wires 111 on one side and one or more (one in this embodiment) first shorting wires 111 on the other side. The number of first shorting wires 111 on the other side is preferably equal to the number of first shorting wires 111 on one side.

[0378] The first short-circuiting wiring 111 on one side is drawn from the first pad wiring 101 onto the first wiring group 80A (first active region 6A) and faces the second pad wiring 102 in the second direction Y in the region above the first wiring group 80A. The first short-circuiting wiring 111 on one side is electrically connected to at least one (plurality in this embodiment) first lower wiring 81 of the first wiring group 80A. In this embodiment, the first short-circuiting wiring 111 on one side intersects (is perpendicular to) at least one (plurality in this embodiment) first lower wiring 81 and at least one (plurality in this embodiment) second lower wiring 82 of the first wiring group 80A in the first placement region 105A.

[0379] The first short wiring 111 on one side crosses the boundary 107 in the second direction Y and is drawn out from the first placement region 105A to the second placement region 105B. In this embodiment, the first short wiring 111 on one side intersects (is perpendicular to) at least one (a plurality of in this embodiment) first lower wirings 81 and at least one (a plurality of in this embodiment) second lower wirings 82 in both the first placement region 105A and the second placement region 105B.

[0380] The first short-circuiting wiring 111 on one side is electrically connected to at least one (plurality in this embodiment) first lower wiring 81 of the first wiring group 80A in the first placement region 105A. Also, the first short-circuiting wiring 111 on one side is electrically connected to at least one (plurality in this embodiment) first lower wiring 81 of the first wiring group 80A in the second placement region 105B.

[0381] The first short wiring 111 on one side intersects (is perpendicular to) at least one (plurality in this embodiment) first lower wiring 81 and at least one (plurality in this embodiment) second lower wiring 82 that pass directly below the first long wiring 110 in the first direction X. In other words, the first short wiring 111 on one side is electrically connected to a portion of the at least one (plurality in this embodiment) first lower wiring 81 covered by the first long wiring 110 that is exposed from the first long wiring 110.

[0382] When the multiple first shorting wirings 111 include multiple first shorting wirings 111 on one side, the multiple first shorting wirings 111 on one side are arranged at intervals in the first direction X in the region above the first wiring group 80A. That is, the multiple first shorting wirings 111 on one side are arranged in a comb-teeth shape extending in the second direction Y in the region above the first wiring group 80A.

[0383] The other first short wiring 111 is drawn from the first pad wiring 101 onto the second wiring group 80B (second active region 6B) and faces the second pad wiring 102 in the second direction Y in the region above the second wiring group 80B. The other first short wiring 111 is electrically connected to at least one (plurality in this embodiment) first lower wiring 81 of the second wiring group 80B. In this embodiment, the other first short wiring 111 intersects (is perpendicular to) at least one (plurality in this embodiment) first lower wiring 81 and at least one (plurality in this embodiment) second lower wiring 82 of the second wiring group 80B in the first placement region 105A.

[0384] The other first shorting wiring 111 crosses the boundary 107 in the second direction Y and is drawn out from the first placement region 105A to the second placement region 105B. In this embodiment, the other first shorting wiring 111 intersects (is perpendicular to) at least one (plurality in this embodiment) first lower wiring 81 and at least one (plurality in this embodiment) second lower wiring 82 in both the first placement region 105A and the second placement region 105B.

[0385] The other first short wiring 111 is electrically connected to at least one (plurality in this embodiment) first lower wiring 81 of the second wiring group 80B in the first placement region 105A. Also, the other first short wiring 111 is electrically connected to at least one (plurality in this embodiment) first lower wiring 81 of the second wiring group 80B in the second placement region 105B.

[0386] When the multiple first shorting wirings 111 include multiple other-side first shorting wirings 111, the multiple other-side first shorting wirings 111 are arranged at intervals in the first direction X in the region above the second wiring group 80B. That is, the multiple other-side first shorting wirings 111 are arranged in a comb-tooth shape extending in the second direction Y in the region above the second wiring group 80B.

[0387] Either or both of the first short-circuiting wirings 111 on one side and the other side may overlap the inter-wiring region IWR. In this case, either or both of the first short-circuiting wirings 111 on one side and the other side overlap either or both of the third lower wiring 83 and the fourth lower wiring 84, and are electrically isolated from both of the third lower wiring 83 and the fourth lower wiring 84 by the second interlayer film 72.

[0388] Of course, the plurality of first lead-out wirings 109 may include an intermediate first short-circuit wiring 111 overlapping the inter-wire region IWR. In this case, the intermediate first short-circuit wiring 111 may be led out from a region above the inter-wire region IWR onto both the first wiring group 80A and the second wiring group 80B adjacent to each other in the first direction X.

[0389] The intermediate first short wiring 111 may be electrically connected to at least one (e.g., multiple) first lower wirings 81 of the first wiring group 80A and at least one (e.g., multiple) first lower wirings 81 of the second wiring group 80B.

[0390] The intermediate first short-circuiting wiring 111 may intersect (be perpendicular to) at least one (e.g., multiple) first lower wirings 81 and at least one (e.g., multiple) second lower wirings 82 of the first wiring group 80A in the first placement area 105A. The intermediate first short-circuiting wiring 111 may also intersect (be perpendicular to) at least one (e.g., multiple) first lower wirings 81 and at least one (e.g., multiple) second lower wirings 82 of the second wiring group 80B in the first placement area 105A.

[0391] The intermediate first shorting wiring 111 may cross the boundary 107 in the second direction Y and be drawn from the first placement region 105A to the second placement region 105B. The intermediate first shorting wiring 111 may intersect (be perpendicular to) at least one (e.g., multiple) first lower wirings 81 and at least one (e.g., multiple) second lower wirings 82 of the first wiring group 80A in both the first placement region 105A and the second placement region 105B.

[0392] In addition, the intermediate first short wiring 111 may intersect (orthogonally) with at least one (e.g., multiple) first lower wirings 81 and at least one (e.g., multiple) second lower wirings 82 of the second wiring group 80B in both the first placement area 105A and the second placement area 105B.

[0393] The intermediate first short-circuiting wiring 111 may be electrically connected to at least one (e.g., a plurality) of first lower wirings 81 of the first wiring group 80A and at least one (e.g., a plurality) of first lower wirings 81 of the second wiring group 80B in the first placement region 105A. Furthermore, the intermediate first short-circuiting wiring 111 may be electrically connected to at least one (e.g., a plurality) of first lower wirings 81 of the first wiring group 80A and at least one (e.g., a plurality) of first lower wirings 81 of the second wiring group 80B in the second placement region 105B.

[0394] The intermediate first short-circuiting wiring 111 may overlap the third lower wiring 83 (the first gate wiring 85 and / or the second gate wiring 86) in a portion covering the inter-wiring region IWR. In this case, the intermediate first short-circuiting wiring 111 faces the third lower wiring 83 (the first gate wiring 85 and / or the second gate wiring 86) with the second interlayer film 72 interposed therebetween, and is electrically isolated from the third lower wiring 83.

[0395] The intermediate first short wiring 111 may overlap the fourth lower wiring 84 (first base wiring 88) in the portion covering the inter-wiring region IWR. In this case, the intermediate first short wiring 111 faces the fourth lower wiring 84 (first base wiring 88) with the second interlayer film 72 interposed therebetween and is electrically isolated from the fourth lower wiring 84.

[0396] The first interconnect structure 108 includes at least one (in this embodiment, a plurality of) second interconnect lines 113 that are extended in the second direction Y from the second pad interconnect line 102 toward the first pad interconnect line 101. The plurality of second interconnect lines 113 are electrically connected to either or both of the at least one second lower interconnect line 82 of the first interconnect group 80A and the at least one second lower interconnect line 82 of the second interconnect group 80B in a region between the first pad interconnect line 101 and the second pad interconnect line 102.

[0397] The plurality of second lead-out wirings 113 include at least one (one in this embodiment) second long wiring 114 that is relatively long, and at least one (plural in this embodiment) second short wiring 115 that is shorter than the second long wiring 114. The second long wiring 114 may be referred to as a "second long lead-out wiring," a "second main lead-out wiring," etc. The second short wiring 115 may be referred to as a "second short lead-out wiring," a "second sub lead-out wiring," etc.

[0398] The number of second shorting wires 115 is arbitrary and is adjusted appropriately depending on the size of the second pad wires 102, etc. The number of second shorting wires 115 may be 1 to 50. The number of second shorting wires 115 may have a value belonging to at least one of the ranges of 1 to 5, 5 to 10, 10 to 20, 20 to 30, 30 to 40, and 40 to 50.

[0399] The number of second shorting wires 115 is preferably equal to the number of first shorting wires 111. This configuration suppresses variations in wiring resistance between the first shorting wires 111 and the second shorting wires 115. In this embodiment, two second shorting wires 115 are provided.

[0400] The second long wiring 114 has a width in the first direction X that is less than the width of the second pad wiring 102 (first pad wiring 101), and is drawn out in a strip shape in the second direction Y from the second end of the second pad wiring 102 toward above the second wiring group 80B (second active region 6B). The width of the second long wiring 114 is greater than the width of the second lower wiring 82 (first lower wiring 81). It is preferable that the second long wiring 114 has a width in the first direction X that is approximately equal to the width of the first long wiring 110. With this configuration, variations in wiring resistance between the first long wiring 110 and the second long wiring 114 are suppressed.

[0401] The second long wiring 114 is provided at a distance in the first direction X from the plurality of first outgoing wirings 109 (the first long wiring 110 and the plurality of first short wirings 111) and faces the plurality of first outgoing wirings 109 in the first direction X. In this embodiment, the second long wiring 114 intersects (is perpendicular to) at least one (a plurality in this embodiment) first lower wiring 81 and at least one (a plurality in this embodiment) second lower wiring 82 of the second wiring group 80B in the second placement region 105B.

[0402] The second long wiring 114 crosses the boundary 107 in the second direction Y and is drawn out from the second placement region 105B to the first placement region 105A. In this embodiment, the second long wiring 114 intersects (is perpendicular to) at least one (a plurality of in this embodiment) first lower wirings 81 and at least one (a plurality of in this embodiment) second lower wirings 82 in both the first placement region 105A and the second placement region 105B.

[0403] The second long wiring 114 is electrically connected to at least one (plurality in this embodiment) second lower wiring 82 of the second wiring group 80B in the second placement region 105B. Also, the second long wiring 114 is electrically connected to at least one (plurality in this embodiment) second lower wiring 82 of the second wiring group 80B in the first placement region 105A.

[0404] In the region between the first pad wiring 101 and the second pad wiring 102, the second long wiring 114 intersects (is perpendicular to) one or more (preferably all) first lower wirings 81 and one or more (preferably all) second lower wirings 82 that pass directly below at least one (one in this embodiment) first pull-out wiring 109 (first short wiring 111 on the other side) in the first direction X.

[0405] The second long wiring 114 is electrically connected to a portion of one or more (preferably all) second lower wirings 82 covered by the other-side first short wiring 111 that is exposed from the other-side first short wiring 111. On the other hand, the second long wiring 114 is electrically isolated from one or more (preferably all) first lower wirings 81 that pass directly below the other-side first short wiring 111.

[0406] The second long wiring 114 forms a current path for the drain-source current Ids together with the first short wiring 111 on the other side facing (closely facing) in the first direction X. Specifically, the current path for the drain-source current Ids is formed between the first short wiring 111 and the second long wiring 114 on the other side via the first lower wiring 81 and the second lower wiring 82 that pass in the first direction X directly below both the first short wiring 111 and the second long wiring 114 on the other side. Such a layout is effective in reducing the wiring resistance between the first pad wiring 101 and the second pad wiring 102.

[0407] The second long wiring 114 has a second opposing portion 116 extended in the second direction Y to a region opposing the first pad wiring 101 in the first direction X. The second opposing portion 116 opposes the entire second end portion of the first pad wiring 101 in the first direction X. With respect to the second wiring group 80B, the second opposing portion 116 (second long wiring 114) intersects (is perpendicular to) one or more (preferably all) first lower wirings 81 and one or more (preferably all) second lower wirings 82 that pass directly below the first pad wiring 101 in the first direction X.

[0408] The second opposing portion 116 is electrically connected to a portion of one or more (preferably all) second lower wirings 82 covered by the first pad wiring 101 that is exposed from the first pad wiring 101. On the other hand, the second opposing portion 116 is electrically isolated from one or more (preferably all) first lower wirings 81 that pass directly below the first pad wiring 101.

[0409] The second opposing portion 116 (second long wiring 114) forms a current path for the drain-source current Ids together with the first pad wiring 101 opposing (closely opposing) in the first direction X. Specifically, the current path for the drain-source current Ids is formed between the first pad wiring 101 and the second long wiring 114 via the first lower wiring 81 and the second lower wiring 82 that pass directly below both the first pad wiring 101 and the second long wiring 114 in the first direction X. Such a layout is effective in reducing the wiring resistance between the first pad wiring 101 and the second pad wiring 102.

[0410] The multiple second short wirings 115 each have a width in the first direction X that is less than the width of the second pad wiring 102 (first pad wiring 101), and are provided in a region on the first end side with respect to the second long wiring 114. The width of the second short wiring 115 may be approximately equal to the width of the second long wiring 114. The width of the second short wiring 115 may be greater than the width of the second long wiring 114. The width of the second short wiring 115 may be less than the width of the second long wiring 114.

[0411] The width of the second shorting wiring 115 is larger than the width of the second lower wiring 82 (first lower wiring 81). It is preferable that the width of the second shorting wiring 115 is approximately equal to the width of the first shorting wiring 111. With this configuration, variations in wiring resistance between the first shorting wiring 111 and the second shorting wiring 115 are suppressed.

[0412] The plurality of second shorting wires 115 are arranged at intervals in the first direction X, and are drawn out in a strip shape (rectangular in this embodiment) in the second direction Y from the second pad wire 102 toward the first pad wire 101. The plurality of second shorting wires 115 may be drawn out in a trapezoidal shape (preferably an isosceles trapezoidal shape) or a triangular shape (preferably an isosceles triangle shape).

[0413] The multiple second shorting wires 115 are arranged in a comb-tooth shape extending in the second direction Y, and face each other in the first direction X. The multiple second shorting wires 115 face the multiple first outgoing wires 109 in the first direction X. Specifically, the multiple second shorting wires 115 each enter into a region between the multiple first outgoing wires 109, and extend through the region between the multiple first outgoing wires 109 in the second direction Y.

[0414] That is, the plurality of second lead-out wires 113 include one second shorting wire 115 arranged in a region between the first long wire 110 and the first shorting wire 111, and second shorting wires 115 arranged in regions between the plurality of first shorting wires 111. As a result, the plurality of second shorting wires 115 are arranged alternately with the plurality of first shorting wires 111 in the first direction X. That is, the plurality of second shorting wires 115 are arranged in a comb-tooth shape that meshes with the plurality of first shorting wires 111.

[0415] It is preferable that the second shorting wires 115 have a length in the second direction Y that is approximately equal to the length of the first shorting wires 111. This configuration suppresses variations in wiring resistance between the first shorting wires 111 and the second shorting wires 115. The multiple second shorting wires 115 are formed at intervals from the first pad wires 101 toward the second pad wires 102, and face the first pad wires 101 in the second direction Y.

[0416] The second shorting wiring 115 is electrically connected to at least one (plurality in this embodiment) second lower wiring 82 in the region between the first pad wiring 101 and the second pad wiring 102. Specifically, in this embodiment, the plurality of second shorting wirings 115 include one or more (one in this embodiment) second shorting wirings 115 on one side and one or more (one in this embodiment) second shorting wirings 115 on the other side. The number of second shorting wirings 115 on the other side is preferably equal to the number of second shorting wirings 115 on one side.

[0417] The second short wiring 115 on one side is drawn from the second pad wiring 102 onto the first wiring group 80A (first active region 6A) and faces the first pad wiring 101 in the second direction Y in the region above the first wiring group 80A. The second short wiring 115 on one side is electrically connected to at least one (plurality in this embodiment) second lower wiring 82 of the first wiring group 80A. In this embodiment, the second short wiring 115 on one side intersects (is perpendicular to) at least one (plurality in this embodiment) first lower wiring 81 and at least one (plurality in this embodiment) second lower wiring 82 of the first wiring group 80A in the second placement region 105B.

[0418] The second shorting wiring 115 on one side crosses the boundary 107 in the second direction Y and is drawn out from the second placement region 105B to the first placement region 105A. In this embodiment, the second shorting wiring 115 on one side intersects (is perpendicular to) at least one (a plurality of in this embodiment) first lower wirings 81 and at least one (a plurality of in this embodiment) second lower wirings 82 in both the first placement region 105A and the second placement region 105B.

[0419] The second short wiring 115 on one side is electrically connected to at least one (plurality in this embodiment) second lower wiring 82 of the first wiring group 80A in the second placement region 105B. Also, the second short wiring 115 on one side is electrically connected to at least one (plurality in this embodiment) second lower wiring 82 of the first wiring group 80A in the first placement region 105A.

[0420] The second short wiring 115 on one side intersects (is perpendicular to) one or more first lower wirings 81 and one or more second lower wirings 82 that pass directly below at least one (in this embodiment, multiple) first pull-out wiring 109 (first long wiring 110 and first short wiring 111) in the first direction X with respect to the first wiring group 80A.

[0421] The second short wiring 115 on one side is electrically connected to a portion of one or more (plurality in this embodiment) second lower wirings 82 covered by the plurality of first lead-out wirings 109 that is exposed from the plurality of first lead-out wirings 109. On the other hand, the second short wiring 115 on one side is electrically disconnected from the one or more (plurality in this embodiment) first lower wirings 81 that pass directly below the plurality of first lead-out wirings 109.

[0422] The second short-circuiting wiring 115 on one side forms a current path for the drain-source current Ids together with the plurality of first lead-out wirings 109 that face (closely face) each other in the first direction X. Specifically, the current path for the drain-source current Ids is formed between the plurality of first lead-out wirings 109 and the second short-circuiting wiring 115 on one side via the first lower wiring 81 and the second lower wiring 82 that pass in the first direction X directly below both the plurality of first lead-out wirings 109 and the second short-circuiting wiring 115 on one side. Such a layout is effective in reducing the wiring resistance between the first pad wiring 101 and the second pad wiring 102.

[0423] When the plurality of second shorting wirings 115 includes a plurality of second shorting wirings 115 on one side, the plurality of second shorting wirings 115 on one side are arranged at intervals in the first direction X in the region above the first wiring group 80A. That is, the plurality of second shorting wirings 115 on one side are arranged in a comb-teeth shape extending in the second direction Y in the region above the first wiring group 80A. For example, the plurality of second shorting wirings 115 on one side are arranged in a comb-teeth shape that meshes with the plurality of first shorting wirings 111 on one side in the region above the first wiring group 80A.

[0424] The other-side second shorting wiring 115 is drawn from the second pad wiring 102 onto the second wiring group 80B (second active region 6B) and faces the first pad wiring 101 in the second direction Y in the region above the second wiring group 80B. The other-side second shorting wiring 115 is electrically connected to at least one (plurality in this embodiment) second lower wiring 82 of the second wiring group 80B. In this embodiment, the other-side second shorting wiring 115 intersects (is perpendicular to) at least one (plurality in this embodiment) first lower wiring 81 and at least one (plurality in this embodiment) second lower wiring 82 of the second wiring group 80B in the second placement region 105B.

[0425] The other side second short wiring 115 crosses the boundary 107 in the second direction Y and is drawn out from the second placement region 105B to the first placement region 105A. In this embodiment, the other side second short wiring 115 intersects (is perpendicular to) at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 in both the first placement region 105A and the second placement region 105B.

[0426] The other second short wiring 115 is electrically connected to at least one (plurality in this embodiment) second lower wiring 82 of the second wiring group 80B in the second placement region 105B. Also, the other second short wiring 115 is electrically connected to at least one (plurality in this embodiment) second lower wiring 82 of the second wiring group 80B in the first placement region 105A.

[0427] The second short wiring 115 on the other side intersects (is perpendicular to) at least one (plurality in this embodiment) first lower wiring 81 and at least one (plurality in this embodiment) second lower wiring 82 that pass directly below the second long wiring 114 in the first direction X. In other words, the second short wiring 115 on the other side is electrically connected to a portion of the at least one (plurality in this embodiment) second lower wiring 82 covered by the second long wiring 114 that is exposed from the second long wiring 114.

[0428] The second short wiring 115 on the other side intersects (is perpendicular to) one or more first lower wirings 81 and one or more second lower wirings 82 that pass directly below at least one (one in this embodiment) first pull-out wiring 109 (first short wiring 111 on the other side) in the first direction X, with respect to the second wiring group 80B.

[0429] The second short wiring 115 on the other side is electrically connected to a portion of one or more (plurality in this embodiment) second lower wirings 82 covered by the first outgoing wiring 109 that is exposed from the first short wiring 111 on the other side. On the other hand, the second short wiring 115 on the other side is electrically disconnected from one or more (plurality in this embodiment) first lower wirings 81 that pass directly below the first outgoing wiring 109.

[0430] The second short-circuiting wiring 115 on the other side forms a current path for the drain-source current Ids together with the first lead-out wiring 109 that faces (closely faces) the first direction X. Specifically, the current path for the drain-source current Ids is formed between the first lead-out wiring 109 and the second short-circuiting wiring 115 on the other side via the first lower wiring 81 and the second lower wiring 82 that pass in the first direction X directly below both the first lead-out wiring 109 and the second short-circuiting wiring 115 on the other side. Such a layout is effective in reducing the wiring resistance between the first pad wiring 101 and the second pad wiring 102.

[0431] When the multiple second shorting wirings 115 include multiple other-side second shorting wirings 115, the multiple other-side second shorting wirings 115 are arranged at intervals in the first direction X in the region above the second wiring group 80B. That is, the multiple other-side second shorting wirings 115 are arranged in a comb-teeth shape extending in the second direction Y in the region above the second wiring group 80B. For example, the multiple other-side second shorting wirings 115 are arranged in a comb-teeth shape that meshes with the multiple other-side first shorting wirings 111 in the region above the second wiring group 80B.

[0432] Either or both of the second short-circuiting wirings 115 on one side and the other side may overlap the inter-wiring region IWR. In this case, either or both of the second short-circuiting wirings 115 on one side and the other side overlap either or both of the third lower wiring 83 and the fourth lower wiring 84, and are electrically isolated from both of the third lower wiring 83 and the fourth lower wiring 84 by the second interlayer film 72.

[0433] Of course, the plurality of second lead-out wirings 113 may include intermediate second short-circuit wirings 115 overlapping the inter-wire region IWR, depending on the layout of the first lead-out wirings 109. In this case, the intermediate second short-circuit wiring 115 may be led out from a region above the inter-wire region IWR onto both the first wiring group 80A and the second wiring group 80B adjacent to each other in the first direction X.

[0434] The intermediate second short wiring 115 may be electrically connected to at least one (e.g., multiple) second lower wirings 82 of the first wiring group 80A and at least one (e.g., multiple) second lower wirings 82 of the second wiring group 80B.

[0435] The intermediate second shorting wiring 115 may intersect (be perpendicular to) at least one (e.g., multiple) first lower wirings 81 and at least one (e.g., multiple) second lower wirings 82 of the first wiring group 80A in the second placement region 105B. The intermediate second shorting wiring 115 may also intersect (be perpendicular to) at least one (e.g., multiple) first lower wirings 81 and at least one (e.g., multiple) second lower wirings 82 of the second wiring group 80B in the second placement region 105B.

[0436] The intermediate second shorting wiring 115 may cross the boundary portion 107 in the second direction Y and be drawn from the second placement region 105B to the first placement region 105A. The intermediate second shorting wiring 115 may intersect (be perpendicular to) at least one (e.g., multiple) first lower wirings 81 and at least one (e.g., multiple) second lower wirings 82 of the first wiring group 80A in both the first placement region 105A and the second placement region 105B.

[0437] In addition, the intermediate second short wiring 115 may intersect (orthogonally) with at least one (e.g., multiple) first lower wirings 81 and at least one (e.g., multiple) second lower wirings 82 of the second wiring group 80B in both the first placement area 105A and the second placement area 105B.

[0438] The intermediate second short-circuiting wiring 115 may be electrically connected to at least one (e.g., a plurality) of second lower wirings 82 of the first wiring group 80A and at least one (e.g., a plurality) of second lower wirings 82 of the second wiring group 80B in the first placement region 105A. Furthermore, the intermediate second short-circuiting wiring 115 may be electrically connected to at least one (e.g., a plurality) of second lower wirings 82 of the first wiring group 80A and at least one (e.g., a plurality) of second lower wirings 82 of the second wiring group 80B in the second placement region 105B.

[0439] The intermediate second shorting wiring 115 may be opposed to the first shorting wiring 111 on one side and the first shorting wiring 111 on the other side on both sides in the first direction X. In this case, the intermediate second shorting wiring 115 forms a current path for the drain-source current Ids together with the first shorting wiring 111 on one side and the first shorting wiring 111 on the other side that are opposed (closely opposed) to each other on both sides in the first direction X.

[0440] The intermediate second short-circuiting wiring 115 may overlap the third lower wiring 83 (the first gate wiring 85 and / or the second gate wiring 86) in the portion covering the inter-wiring region IWR. In this case, the intermediate second short-circuiting wiring 115 faces the third lower wiring 83 (the first gate wiring 85 and / or the second gate wiring 86) with the second interlayer film 72 interposed therebetween, and is electrically isolated from the third lower wiring 83.

[0441] The intermediate second short wiring 115 may overlap the fourth lower wiring 84 (first base wiring 88) in the portion covering the inter-wiring region IWR. In this case, the intermediate second short wiring 115 faces the fourth lower wiring 84 (first base wiring 88) with the second interlayer film 72 interposed therebetween, and is electrically isolated from the fourth lower wiring 84.

[0442] Thus, the first wiring unit U1 includes a first upper wiring and a second upper wiring. The first upper wiring includes a first pad wiring 101 and a plurality of first lead-out wirings 109, and the second upper wiring includes a second pad wiring 102 and a plurality of second lead-out wirings 113. In this configuration, it is preferable that the second upper wiring has a planar layout that is substantially congruent with the planar layout of the first upper wiring.

[0443] In other words, it is preferable that the planar shape of the second upper wiring is substantially equal to the planar shape of the first upper wiring, and the planar area of ​​the second upper wiring is substantially equal to the planar area of ​​the first upper wiring. It is preferable that the second upper wiring is arranged point-symmetrically with respect to the first upper wiring, with the center of the boundary portion 107 as the center.

[0444] The first wiring unit U1 includes a wiring slit that electrically separates the first upper wiring and the second upper wiring. The wiring slit is a section defined in a region between the first upper wiring and the second upper wiring, and exposes a part of the interlayer film 70 (the second interlayer film 72).

[0445] The width of the wiring slit may be 0.1 μm or more and 50 μm or less. The width of the wiring slit may have a value belonging to at least one range of 0.1 μm or more and 0.5 μm or less, 0.5 μm to 1 μm or less, 1 μm or more and 1.5 μm or more, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or more and 12.5 μm or more and 15 μm or more and 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or more and 30 μm or less.

[0446] The first wiring unit U1 includes a plurality of first upper via electrodes 117 and a plurality of second upper via electrodes 118 each embedded in the second interlayer film 72. The first upper via electrode 117 is a plug electrode that transmits a first drain-source potential to the first lower wiring 81. The second upper via electrode 118 is a plug electrode that transmits a second drain-source potential to the second lower wiring 82. The first upper via electrode 117 may be referred to as a "first drain-source upper via electrode." The second upper via electrode 118 may be referred to as a "second drain-source upper via electrode."

[0447] The multiple first upper via electrodes 117 are arranged in a matrix with gaps in the first direction X and the second direction Y relative to the multiple first lower wirings 81. Of course, the multiple first upper via electrodes 117 may also be arranged in a staggered manner with gaps in the first direction X and the second direction Y relative to the multiple first lower wirings 81. In this case, the multiple first upper via electrodes 117 connected to one first lower wiring 81 face, in the second direction Y, regions between the multiple first upper via electrodes 117 connected to other first lower wirings 81.

[0448] The multiple second upper via electrodes 118 are arranged in a matrix with gaps in the first direction X and the second direction Y relative to the multiple second lower wirings 82. Of course, the multiple second upper via electrodes 118 may also be arranged in a staggered manner with gaps in the first direction X and the second direction Y relative to the multiple second lower wirings 82. In this case, the multiple second upper via electrodes 118 connected to one second lower wiring 82 face, in the second direction Y, regions between the multiple second upper via electrodes 118 connected to other second lower wirings 82.

[0449] In this embodiment, the first and second upper via electrodes 117 and 118 each include a first electrode 119 and a second electrode 120. The first electrode 119 covers the wall surface of the via hole formed in the second interlayer film 72 in the form of a film. The first electrode 119 may include either or both of a Ti film and a Ti alloy film. The Ti alloy film may be a TiN film.

[0450] The second electrode 120 is embedded in the via hole via the first electrode 119. The second electrode 120 may contain at least one of W, Al, an Al alloy, Cu, and a Cu alloy. The Al alloy may contain at least one of an AlSi alloy, an AlCu alloy, and an AlSiCu alloy.

[0451] The first and second upper via electrodes 117 and 118 may be formed in a triangular, quadrangular, rectangular, polygonal, circular, or elliptical shape in a plan view. Of course, the first and second upper via electrodes 117 and 118 may be formed in a strip shape (e.g., a rectangular shape) extending in the first direction X.

[0452] The plurality of first upper via electrodes 117 are interposed in the second interlayer film 72 in regions between the plurality of first lower wirings 81 and the first pad wirings 101, and electrically connect the first pad wirings 101 to the plurality of first lower wirings 81. The first wiring unit U1 only needs to have at least one first upper via electrode 117 between one first lower wiring 81 and one first pad wiring 101. In this embodiment, the plurality of first upper via electrodes 117 are interposed between one first lower wiring 81 and one first pad wiring 101.

[0453] Furthermore, the multiple first upper via electrodes 117 are interposed in regions between the multiple first lower wirings 81 and the multiple first lead-out wirings 109 in the second interlayer film 72, and electrically connect the multiple first lead-out wirings 109 to the multiple first lower wirings 81. The first wiring unit U1 only needs to have at least one first upper via electrode 117 between one first lower wiring 81 and one first lead-out wiring 109. In this embodiment, the multiple first upper via electrodes 117 are interposed between one first lower wiring 81 and one first lead-out wiring 109.

[0454] The number of first upper via electrodes 117 interposed between one first lower wiring 81 and one first lead wiring 109 is arbitrary. For example, the number of first upper via electrodes 117 may be 1 or more and 50 or less. For example, the number of first upper via electrodes 117 may have a value belonging to at least one of the ranges of 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 20 or less, 20 or more and 30 or less, 30 or more and 40 or less, and 40 or more and 50 or less.

[0455] The first upper via electrode 117 may be formed by utilizing the first pad wiring 101 (first outgoing wiring 109). In this case, the first electrode 119 of the first upper via electrode 117 is formed integrally with the first electrode 78 of the first pad wiring 101 (first outgoing wiring 109) and forms one electrode film together with the first electrode 78. Similarly, the second electrode 120 of the first upper via electrode 117 is formed integrally with the second electrode 79 of the first pad wiring 101 (first outgoing wiring 109) and forms one electrode together with the second electrode 79.

[0456] The plurality of second upper via electrodes 118 are interposed in the second interlayer film 72 in regions between the plurality of second lower wirings 82 and the second pad wirings 102, and electrically connect the second pad wirings 102 to the plurality of second lower wirings 82. The first wiring unit U1 only needs to have at least one second upper via electrode 118 between one second lower wiring 82 and one second pad wiring 102. In this embodiment, the plurality of second upper via electrodes 118 are interposed between one second lower wiring 82 and one second pad wiring 102.

[0457] Furthermore, the plurality of second upper via electrodes 118 are interposed in regions between the plurality of second lower wirings 82 and the plurality of second lead-out wirings 113 in the second interlayer film 72, and electrically connect the plurality of second lead-out wirings 113 to the plurality of second lower wirings 82. The first wiring unit U1 is only required to have at least one second upper via electrode 118 between one second lower wiring 82 and one second lead-out wiring 113. In this embodiment, the plurality of second upper via electrodes 118 are interposed between one second lower wiring 82 and one second lead-out wiring 113.

[0458] The number of second upper via electrodes 118 interposed between one second lower wiring 82 and one second lead-out wiring 113 is arbitrary. For example, the number of second upper via electrodes 118 may be 1 or more and 50 or less. For example, the number of second upper via electrodes 118 may have a value belonging to at least one of the ranges of 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 20 or less, 20 or more and 30 or less, 30 or more and 40 or less, and 40 or more and 50 or less.

[0459] It is preferable that the number of second upper via electrodes 118 connected to one second outgoing wiring 113 is approximately equal to the number of first upper via electrodes 117 connected to one first outgoing wiring 109. It is preferable that the number of second upper via electrodes 118 connected to the second pad wiring 102 is approximately equal to the number of first upper via electrodes 117 connected to the first pad wiring 101.

[0460] It is preferable that the number of second upper via electrodes 118 connected to the second pad wiring 102 and the plurality of second outgoing wirings 113 is approximately equal to the number of first upper via electrodes 117 connected to the first pad wiring 101 and the plurality of first outgoing wirings 109. According to these configurations, variations in wiring resistance are suppressed.

[0461] The second upper via electrode 118 may be formed by utilizing the second pad wiring 102 (second outgoing wiring 113). In this case, the first electrode 119 of the second upper via electrode 118 is formed integrally with the first electrode 78 of the second pad wiring 102 (second outgoing wiring 113) and forms one electrode film together with the first electrode 78. Similarly, the second electrode 120 of the second upper via electrode 118 is formed integrally with the second electrode 79 of the second pad wiring 102 (second outgoing wiring 113) and forms one electrode together with the second electrode 79.

[0462] The first interconnect structure 108 can have various layouts. Second to tenth layout examples will be described below with reference to FIGS. 16B to 16J. Referring to FIG. 16B (second layout example), the first interconnect structure 108 includes a plurality of first outgoing wires 109. The plurality of first outgoing wires 109 includes a first long wire 110 and a single first short wire 111. The layout of the first long wire 110 is similar to that of the first layout example.

[0463] In this embodiment, the first short wiring 111 is drawn out in a triangular shape from a region on the second end side of the first pad wiring 101 relative to the first end (first long wiring 110) of the first pad wiring 101. The first short wiring 111 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in the region between the first pad wiring 101 and the second pad wiring 102.

[0464] In the first placement region 105A, the first shorting wiring 111 covers at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A. In addition, in the first placement region 105A, the first shorting wiring 111 covers at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the second wiring group 80B.

[0465] The first shorting wiring 111 crosses the boundary 107 in the second direction Y and is drawn out from the first placement region 105A to the second placement region 105B. In this embodiment, the first shorting wiring 111 covers at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A in the second placement region 105B.

[0466] In the first placement region 105A, the first shorting wiring 111 is electrically connected to at least one (in this embodiment, multiple) first lower wirings 81 of the first wiring group 80A and at least one (in this embodiment, multiple) first lower wirings 81 of the second wiring group 80B. In addition, the first shorting wiring 111 is electrically connected to at least one (in this embodiment, multiple) first lower wirings 81 of the first wiring group 80A in the second placement region 105B. The first shorting wiring 111 is electrically connected to the corresponding first lower wirings 81 via multiple first upper via electrodes 117, as in the first layout example.

[0467] In the second placement region 105B, the first shorting wiring 111 may cover at least one (in this embodiment, a plurality of) first lower wirings 81 and at least one (in this embodiment, a plurality of) second lower wirings 82 of the second wiring group 80B. In this case, the first shorting wiring 111 may be electrically connected to at least one (in this embodiment, a plurality of) first lower wirings 81 of the second wiring group 80B in the second placement region 105B.

[0468] The first short wiring 111 has a first inclined portion that is inclined obliquely from the second end of the first pad wiring 101 toward the first end of the second pad wiring 102. The extending direction (inclination direction) of the first inclined portion is a direction that intersects both the first direction X and the second direction Y. The first inclined portion crosses the inter-wiring region IWR in the inclined direction. In this embodiment, the intersection (point of intersection) of the first inclined portion and the inter-wiring region IWR is located on the boundary 107.

[0469] The first inclined portion further crosses the boundary portion 107 along the inclined direction and has a tip portion connected to the first long wiring 110 in the second placement region 105B. The first inclined portion is formed in the second placement region 105B at a distance from the second pad wiring 102 toward the first pad wiring 101, and faces the second pad wiring 102 in the second direction Y.

[0470] The first shorting wiring 111 overlaps the third lower wiring 83 in a portion covering the inter-wiring region IWR. In this embodiment, the first shorting wiring 111 overlaps both the first gate wiring 85 and the second gate wiring 86. The first shorting wiring 111 faces the third lower wiring 83 (the first gate wiring 85 and the second gate wiring 86) with the second interlayer film 72 interposed therebetween, and is electrically isolated from the third lower wiring 83.

[0471] The first shorting wiring 111 overlaps the fourth lower wiring 84 in a portion covering the inter-wiring region IWR. In this embodiment, the first shorting wiring 111 overlaps the first base wiring 88. The first shorting wiring 111 faces the fourth lower wiring 84 (first base wiring 88) with the second interlayer film 72 interposed therebetween, and is electrically isolated from the fourth lower wiring 84.

[0472] The first interconnect structure 108 includes a plurality of second outgoing wires 113. The plurality of second outgoing wires 113 include a second long wire 114 and a single second short wire 115. The layout of the second long wire 114 is similar to that of the first layout example.

[0473] In this embodiment, the second short wiring 115 is drawn out in a triangular shape from a region on the first end side of the second pad wiring 102 with respect to the second end (second long wiring 114) of the second pad wiring 102. The second short wiring 115 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in the region between the first pad wiring 101 and the second pad wiring 102.

[0474] In the second placement region 105B, the second shorting wiring 115 covers at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A. In addition, in the second placement region 105B, the second shorting wiring 115 covers at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the second wiring group 80B.

[0475] The second shorting wiring 115 crosses the boundary portion 107 in the second direction Y and is drawn out from the second placement region 105B to the first placement region 105A. In this embodiment, the second shorting wiring 115 covers at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the second wiring group 80B in the first placement region 105A.

[0476] In the second placement region 105B, the second shorting wiring 115 is electrically connected to at least one (a plurality of in this embodiment) second lower wirings 82 of the first wiring group 80A and at least one (a plurality of in this embodiment) second lower wirings 82 of the second wiring group 80B. In addition, the second shorting wiring 115 is electrically connected to at least one (a plurality of in this embodiment) second lower wirings 82 of the second wiring group 80B in the first placement region 105A. The second shorting wiring 115 is electrically connected to the corresponding second lower wirings 82 via a plurality of second upper via electrodes 118, as in the case of the first layout example.

[0477] In the first placement region 105A, the second shorting wiring 115 may cover at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A. In this case, the second shorting wiring 115 may be electrically connected to at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A in the first placement region 105A.

[0478] The second short wiring 115 has a second inclined portion that is obliquely inclined from the first end of the second pad wiring 102 toward the second end of the first pad wiring 101. The extending direction (inclination direction) of the second inclined portion is a direction that intersects both the first direction X and the second direction Y. The second inclined portion crosses the inter-wiring region IWR in the inclined direction. In this embodiment, the intersection (point of intersection) of the second inclined portion and the inter-wiring region IWR is located on the boundary 107.

[0479] The second inclined portion further crosses the boundary portion 107 along the inclined direction and has a tip portion connected to the second long wiring 114 in the first placement region 105A. The second inclined portion is formed at a distance from the first pad wiring 101 toward the second pad wiring 102 in the first placement region 105A, and faces the first pad wiring 101 in the second direction Y.

[0480] The second inclined portion extends along the first inclined portion at a distance from the first inclined portion. The second inclined portion preferably extends substantially parallel to the first inclined portion at a distance from the first inclined portion in the perpendicular direction of the first inclined portion. In other words, the inclination angle of the second inclined portion is preferably substantially equal to the inclination angle of the first inclined portion. The second shorting wiring 115 preferably has a planar layout substantially congruent with the planar layout of the first shorting wiring 111.

[0481] With respect to the first wiring group 80A, the second short wiring 115 covers one or more (preferably all) first lower wirings 81 and one or more (preferably all) second lower wirings 82 that pass directly below the first short wiring 111 in the first direction X.

[0482] On the first wiring group 80A side, the second shorting wire 115 is electrically connected to a portion of one or more (preferably all) second lower wires 82 covered by the first shorting wire 111 that is exposed from the first shorting wire 111. On the other hand, the second shorting wire 115 is electrically isolated from one or more (preferably all) first lower wires 81 that pass directly below the first shorting wire 111.

[0483] Similarly, the second short wiring 115 covers one or more (preferably all) first lower wirings 81 and one or more (preferably all) second lower wirings 82 in the second wiring group 80B that pass directly below the first short wiring 111 in the first direction X.

[0484] On the second wiring group 80B side, the second shorting wiring 115 is electrically connected to a portion of one or more (preferably all) second lower wirings 82 covered by the first shorting wiring 111 that is exposed from the first shorting wiring 111. On the other hand, the second shorting wiring 115 is electrically isolated from one or more (preferably all) first lower wirings 81 that pass directly below the first shorting wiring 111.

[0485] In this way, the second shorting wires 115 form a current path for the drain-source current Ids together with the first shorting wires 111 that face (closely face) in the first direction X in both the first wiring group 80A and the second wiring group 80B.

[0486] The second shorting wiring 115 overlaps the third lower wiring 83 in a portion covering the inter-wiring region IWR. In this embodiment, the second shorting wiring 115 overlaps both the first gate wiring 85 and the second gate wiring 86. The second shorting wiring 115 faces the third lower wiring 83 (the first gate wiring 85 and the second gate wiring 86) with the second interlayer film 72 interposed therebetween, and is electrically isolated from the third lower wiring 83.

[0487] The second shorting wiring 115 overlaps the fourth lower wiring 84 in a portion covering the inter-wiring region IWR. In this embodiment, the second shorting wiring 115 overlaps the first base wiring 88. The second shorting wiring 115 faces the fourth lower wiring 84 (first base wiring 88) with the second interlayer film 72 interposed therebetween, and is electrically isolated from the fourth lower wiring 84.

[0488] 16C (third layout example), first interconnect structure 108 includes a plurality of first outgoing wires 109. The plurality of first outgoing wires 109 includes a first long wire 110 and a single first short wire 111. The layout of first long wire 110 is similar to that of the first layout example.

[0489] The first short wiring 111 is drawn in a triangular shape from a region on the second end side of the first pad wiring 101 relative to the first end (first long wiring 110) of the first pad wiring 101. The first short wiring 111 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in the region between the first pad wiring 101 and the second pad wiring 102.

[0490] In the first placement region 105A, the first shorting wiring 111 covers at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A. In addition, in the first placement region 105A, the first shorting wiring 111 covers at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the second wiring group 80B.

[0491] The first shorting wiring 111 crosses the boundary portion 107 in the second direction Y and is drawn out from the first placement region 105A to the second placement region 105B. In this embodiment, the first shorting wiring 111 covers at least one (a plurality of, in this embodiment) first lower wirings 81 and at least one (a plurality of, in this embodiment) second lower wirings 82 of the second wiring group 80B in the second placement region 105B.

[0492] In the first placement region 105A, the first short-circuiting wiring 111 is electrically connected to at least one (plurality in this embodiment) first lower wiring 81 of the first wiring group 80A and at least one (plurality in this embodiment) first lower wiring 81 of the second wiring group 80B. In addition, in the second placement region 105B, the first short-circuiting wiring 111 is electrically connected to at least one (plurality in this embodiment) first lower wiring 81 of the second wiring group 80B.

[0493] As in the first layout example, the first shorting wiring 111 is electrically connected to the corresponding first lower wiring 81 via a plurality of first upper via electrodes 117. The first shorting wiring 111 may cover at least one (a plurality in this embodiment) first lower wiring 81 and at least one (a plurality in this embodiment) second lower wiring 82 of the first wiring group 80A in the second placement region 105B. In this case, the first shorting wiring 111 may be electrically connected to at least one (a plurality in this embodiment) first lower wiring 81 of the first wiring group 80A in the second placement region 105B.

[0494] In this embodiment, the first short wiring 111 has a first side portion that is drawn in the second direction Y from the second end portion of the first pad wiring 101 toward the second wiring group 80B. The first side portion forms one side that extends in the second direction Y with the second end portion of the first pad wiring 101. The first side portion crosses the boundary portion 107 in the second direction Y and is located in the second placement region 105B. The first side portion is formed in the second placement region 105B at a distance from the second pad wiring 102 toward the first pad wiring 101, and faces the second pad wiring 102 in the second direction Y.

[0495] In this embodiment, the first inclined portion of the first short wiring 111 is obliquely inclined from the first end of the first pad wiring 101 toward the second end of the second pad wiring 102 and faces the first long wiring 110 in the first direction X. The first inclined portion crosses the inter-wiring region IWR in the inclined direction. In this embodiment, the intersection (point of intersection) of the first inclined portion and the inter-wiring region IWR is located on the boundary 107.

[0496] The first inclined portion further crosses the boundary portion 107 along the inclined direction and is connected to the first side portion in the second placement region 105B. In other words, the tip of the first inclined portion is positioned on the same straight line as the second end portion of the first pad wiring 101.

[0497] The first interconnect structure 108 includes a plurality of second outgoing wires 113. The plurality of second outgoing wires 113 include a second long wire 114 and a single second short wire 115. The layout of the second long wire 114 is similar to that of the first layout example.

[0498] The second short wiring 115 is drawn out in a triangular shape from the region on the first end side of the second pad wiring 102, and is arranged in the region between the first long wiring 110 and the first short wiring 111. In the region between the first pad wiring 101 and the second pad wiring 102, the second short wiring 115 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR.

[0499] In the second placement region 105B, the second shorting wiring 115 covers at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A. In addition, in the second placement region 105B, the second shorting wiring 115 covers at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the second wiring group 80B.

[0500] The second shorting wiring 115 crosses the boundary portion 107 in the second direction Y and is drawn out from the second placement region 105B to the first placement region 105A. In this embodiment, the second shorting wiring 115 covers at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A in the first placement region 105A.

[0501] In the second placement region 105B, the second shorting wiring 115 is electrically connected to at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A and at least one (in this embodiment, multiple) second lower wirings 82 of the second wiring group 80B. In addition, the second shorting wiring 115 is electrically connected to at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A in the first placement region 105A.

[0502] As in the first layout example, the second shorting wiring 115 is electrically connected to the corresponding second lower wiring 82 via a plurality of second upper via electrodes 118. The second shorting wiring 115 may cover at least one (a plurality in this embodiment) first lower wiring 81 and at least one (a plurality in this embodiment) second lower wiring 82 of the second wiring group 80B in the first placement region 105A. In this case, the second shorting wiring 115 may be electrically connected to at least one (a plurality in this embodiment) second lower wiring 82 of the second wiring group 80B in the first placement region 105A.

[0503] In this embodiment, the second short wiring 115 has a second side portion that is drawn out in the second direction Y from the first end portion of the second pad wiring 102. The second side portion forms one side that extends in the second direction Y with the first end portion of the second pad wiring 102. The second side portion crosses the boundary portion 107 in the second direction Y and is located in the first placement area 105A. The second side portion is formed in the first placement area 105A from the first pad wiring 101 toward the first wiring group 80A, with a gap toward the second pad wiring 102, and faces the first pad wiring 101 in the second direction Y.

[0504] In this embodiment, the second inclined portion of the second short wiring 115 is obliquely inclined from the second end of the second pad wiring 102 toward the first end of the first pad wiring 101 and faces the second long wiring 114 in the first direction X. The second inclined portion crosses the inter-wiring region IWR in the inclined direction. In this embodiment, the intersection (intersection point) of the second inclined portion and the inter-wiring region IWR is located on the boundary 107.

[0505] The second inclined portion further crosses the boundary portion 107 along the inclined direction and is connected to the second side portion in the first placement region 105 A. In other words, the tip of the second inclined portion is positioned on the same straight line as the first end portion of the second pad wiring 102.

[0506] The second inclined portion extends along the first inclined portion at a distance from the first inclined portion. The second inclined portion preferably extends substantially parallel to the first inclined portion at a distance from the first inclined portion in the perpendicular direction of the first inclined portion. In other words, the inclination angle of the second inclined portion is preferably substantially equal to the inclination angle of the first inclined portion. The second shorting wiring 115 preferably has a planar layout substantially congruent with the planar layout of the first shorting wiring 111.

[0507] As in the second layout example, the second short-circuit wiring 115 forms a current path for the drain-source current Ids together with the first short-circuit wiring 111 that faces (closely faces) in the first direction X in both the first wiring group 80A and the second wiring group 80B.

[0508] 16D (fourth layout example), first interconnect structure 108 includes a plurality of first outgoing wires 109. The plurality of first outgoing wires 109 includes a first long wire 110 and a single first short wire 111. The layout of first long wire 110 is similar to that of the first layout example.

[0509] The first short wiring 111 is drawn out in a trapezoidal (quadrilateral) shape from a region on the second end side of the first pad wiring 101 relative to the first end (first long wiring 110) of the first pad wiring 101. The first short wiring 111 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in the region between the first pad wiring 101 and the second pad wiring 102.

[0510] In the first placement region 105A, the first short-circuiting wiring 111 is electrically connected to at least one (in this embodiment, multiple) first lower wirings 81 of the first wiring group 80A and at least one (in this embodiment, multiple) first lower wirings 81 of the second wiring group 80B. In addition, in the second placement region 105B, the first short-circuiting wiring 111 is electrically connected to at least one (in this embodiment, multiple) first lower wirings 81 of the first wiring group 80A.

[0511] In the second placement region 105B, the first shorting wiring 111 may cover at least one (in this embodiment, a plurality of) first lower wirings 81 and at least one (in this embodiment, a plurality of) second lower wirings 82 of the second wiring group 80B. In this case, the first shorting wiring 111 may be electrically connected to at least one (in this embodiment, a plurality of) first lower wirings 81 of the second wiring group 80B in the second placement region 105B.

[0512] The first short wiring 111 has a first tip portion and a first inclined portion. The first tip portion has a width in the first direction X that is less than the width of the first pad wiring 101 and is located on the second pad wiring 102 side with respect to the first pad wiring 101. The first tip portion extends in the first direction X at least on the first wiring group 80A side and is connected to the first long wiring 110.

[0513] In this embodiment, the first tip portion is located in the second placement region 105B. The first tip portion is formed in the second placement region 105B at a distance from the second pad wiring 102 toward the first pad wiring 101, and faces the first end portion of the second pad wiring 102 in the second direction Y. The first tip portion extends approximately parallel to the first end portion of the second pad wiring 102.

[0514] The first inclined portion is formed at a distance from the second end of the first pad wiring 101 toward the first end of the first pad wiring 101, and exposes the second end of the first pad wiring 101. The first inclined portion is inclined obliquely from the inner portion of the first pad wiring 101 toward the first end of the second pad wiring 102. The extending direction (inclination direction) of the first inclined portion is a direction intersecting both the first direction X and the second direction Y.

[0515] The first inclined portion crosses the inter-wiring region IWR in the inclined direction. In this embodiment, the intersection (point of intersection) of the first inclined portion and the inter-wiring region IWR is located on the boundary 107. The first inclined portion further crosses the boundary 107 along the inclined direction and is connected to a first tip portion in the second placement region 105B. Of course, the extension direction (inclination direction) of the first inclined portion may be the second direction Y. In this case, it is preferable that the first inclined portion extend in the second direction Y above the first wiring group 80A or above the inter-wiring region IWR.

[0516] The first interconnect structure 108 includes a plurality of second outgoing wires 113. The plurality of second outgoing wires 113 include a second long wire 114 and a single second short wire 115. The layout of the second long wire 114 is similar to that of the first layout example.

[0517] The second short wiring 115 is drawn in a trapezoidal (quadrilateral) shape from a region on the first end side of the second pad wiring 102 relative to the second end (second long wiring 114) of the second pad wiring 102. The second short wiring 115 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in the region between the first pad wiring 101 and the second pad wiring 102.

[0518] In the second placement region 105B, the second shorting wiring 115 is electrically connected to at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A and at least one (in this embodiment, multiple) second lower wirings 82 of the second wiring group 80B. In addition, the second shorting wiring 115 is electrically connected to at least one (in this embodiment, multiple) second lower wirings 82 of the second wiring group 80B in the first placement region 105A.

[0519] In the first placement region 105A, the second shorting wiring 115 may cover at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A. In this case, the second shorting wiring 115 may be electrically connected to at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A in the first placement region 105A.

[0520] The second short wiring 115 has a second tip portion and a second inclined portion. The second tip portion has a width in the first direction X that is less than the width of the second pad wiring 102 and is located on the first pad wiring 101 side with respect to the second pad wiring 102. The second tip portion extends in the first direction X at least on the second wiring group 80B side and is connected to the second long wiring 114. It is preferable that the width of the second tip portion is approximately equal to the width of the first tip portion.

[0521] In this embodiment, the second tip portion is located in the first placement region 105A. The second tip portion is formed in the first placement region 105A at a distance from the first pad wiring 101 toward the second pad wiring 102, and faces the second end portion of the first pad wiring 101 in the second direction Y. The second tip portion extends approximately parallel to the second end portion of the first pad wiring 101.

[0522] The second inclined portion is formed at a distance from the first end of the second pad wiring 102 toward the second end of the second pad wiring 102, and exposes the first end of the second pad wiring 102. The second inclined portion is inclined obliquely from the inner portion of the second pad wiring 102 toward the second end of the first pad wiring 101. The extending direction (inclination direction) of the second inclined portion is a direction intersecting both the first direction X and the second direction Y.

[0523] The second inclined portion crosses the inter-wiring region IWR in the inclined direction. In this embodiment, the intersection (point of intersection) of the second inclined portion and the inter-wiring region IWR is located on the boundary 107. The second inclined portion further crosses the boundary 107 along the inclined direction and is connected to a second tip portion in the first placement region 105A. Of course, the extension direction (inclination direction) of the second inclined portion may be the second direction Y. In this case, it is preferable that the second inclined portion extend in the second direction Y above the second wiring group 80B or above the inter-wiring region IWR.

[0524] The second inclined portion extends along the first inclined portion at a distance from the first inclined portion. The second inclined portion preferably extends substantially parallel to the first inclined portion at a distance from the first inclined portion in the perpendicular direction of the first inclined portion. In other words, the inclination angle of the second inclined portion is preferably substantially equal to the inclination angle of the first inclined portion. The second shorting wiring 115 preferably has a planar layout substantially congruent with the planar layout of the first shorting wiring 111.

[0525] As in the second layout example, the second short-circuit wiring 115 forms a current path for the drain-source current Ids together with the first short-circuit wiring 111 that faces (closely faces) in the first direction X in both the first wiring group 80A and the second wiring group 80B.

[0526] 16E (fifth layout example), first interconnect structure 108 includes a plurality of first outgoing wires 109. The plurality of first outgoing wires 109 includes a first long wire 110 and a single first short wire 111. The layout of first long wire 110 is similar to that of the first layout example.

[0527] The first short wiring 111 is drawn out in a trapezoidal (quadrilateral) shape from a region on the second end side of the first pad wiring 101 relative to the first end (first long wiring 110) of the first pad wiring 101. The first short wiring 111 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in the region between the first pad wiring 101 and the second pad wiring 102.

[0528] In the first placement region 105A, the first short-circuiting wiring 111 is electrically connected to at least one (plurality in this embodiment) first lower wiring 81 of the first wiring group 80A and at least one (plurality in this embodiment) first lower wiring 81 of the second wiring group 80B. In addition, in the second placement region 105B, the first short-circuiting wiring 111 is electrically connected to at least one (plurality in this embodiment) first lower wiring 81 of the second wiring group 80B.

[0529] In the second placement region 105B, the first shorting wiring 111 may cover at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A. In this case, the first shorting wiring 111 may be electrically connected to at least one (in this embodiment, multiple) first lower wirings 81 of the first wiring group 80A in the second placement region 105B.

[0530] The first short wiring 111 has a first side portion that is drawn in the second direction Y from the second end portion of the first pad wiring 101 toward the second wiring group 80B. The first side portion forms one side that extends in the second direction Y with the second end portion of the first pad wiring 101. The first side portion crosses the boundary portion 107 in the second direction Y and is located in the second placement region 105B. The first side portion is formed in the second placement region 105B at a distance from the second pad wiring 102 toward the first pad wiring 101, and faces the second pad wiring 102 in the second direction Y.

[0531] The first tip of the first short wiring 111 has a width in the first direction X that is less than the width of the first pad wiring 101 and is located on the second pad wiring 102 side with respect to the first pad wiring 101. The first tip extends in the first direction X at least on the second wiring group 80B side and is connected to the first side. In this embodiment, the first tip is formed in the second placement region 105B at a distance from the second pad wiring 102 toward the first pad wiring 101 and faces the second end of the second pad wiring 102 in the second direction Y. The first tip extends approximately parallel to the second end of the second pad wiring 102.

[0532] In this embodiment, the first inclined portion of the first short wiring 111 is formed at a distance from the first end (first long wiring 110) of the first pad wiring 101 toward the second end of the first pad wiring 101, exposing the first end of the first pad wiring 101. The first inclined portion is inclined obliquely from the inner portion of the first pad wiring 101 toward the second end of the second pad wiring 102. The extending direction (inclination direction) of the first inclined portion is a direction intersecting both the first direction X and the second direction Y.

[0533] The first inclined portion crosses the inter-wiring region IWR in the inclined direction. In this embodiment, the intersection (point of intersection) of the first inclined portion and the inter-wiring region IWR is located on the boundary 107. The first inclined portion further crosses the boundary 107 along the inclined direction and is connected to a first tip portion in the second placement region 105B. Of course, the extension direction (inclination direction) of the first inclined portion may be the second direction Y. In this case, it is preferable that the first inclined portion extend in the second direction Y above the second wiring group 80B or above the inter-wiring region IWR.

[0534] The first interconnect structure 108 includes a plurality of second outgoing wires 113. The plurality of second outgoing wires 113 include a second long wire 114 and a single second short wire 115. The layout of the second long wire 114 is similar to that of the first layout example.

[0535] The second short wiring 115 is drawn out in a trapezoidal (quadrilateral) shape from a region on the first end side of the second pad wiring 102 with respect to the second end (second long wiring 114) of the second pad wiring 102, and is disposed in a region between the first long wiring 110 and the first short wiring 111. In the region between the first pad wiring 101 and the second pad wiring 102, the second short wiring 115 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR.

[0536] In the second placement region 105B, the second shorting wiring 115 is electrically connected to at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A and at least one (in this embodiment, multiple) second lower wirings 82 of the second wiring group 80B. In addition, the second shorting wiring 115 is electrically connected to at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A in the first placement region 105A.

[0537] In the first placement region 105A, the second shorting wiring 115 may cover at least one (in this embodiment, a plurality) first lower wirings 81 and at least one (in this embodiment, a plurality) second lower wirings 82 of the second wiring group 80B. In this case, the second shorting wiring 115 may be electrically connected to at least one (in this embodiment, a plurality) second lower wirings 82 of the second wiring group 80B in the first placement region 105A.

[0538] In this embodiment, the second short wiring 115 has a second side portion that is drawn in the second direction Y from the first end portion of the second pad wiring 102 toward the first wiring group 80A. The second side portion forms one side extending in the second direction Y with the first end portion of the first pad wiring 101. The second side portion crosses the boundary portion 107 in the second direction Y and is located in the first placement region 105A. The second side portion is formed in the first placement region 105A at a distance from the first pad wiring 101 toward the second pad wiring 102, and faces the first pad wiring 101 in the second direction Y.

[0539] The second tip portion has a width in the first direction X that is less than the width of the second pad wiring 102 and is located on the first pad wiring 101 side with respect to the second pad wiring 102. The second tip portion extends in the first direction X at least on the first wiring group 80A side and is connected to the second side. In this embodiment, the second tip portion is formed in the first placement region 105A at a distance from the first pad wiring 101 to the second pad wiring 102 side and faces the first end of the first pad wiring 101 in the second direction Y. The second tip portion extends approximately parallel to the first end of the first pad wiring 101.

[0540] In this embodiment, the second inclined portion is formed at a distance from the second end (second long wire 114) of the second pad wire 102 toward the first end of the second pad wire 102, exposing the second end of the second pad wire 102. The second inclined portion is inclined obliquely from the inner portion of the second pad wire 102 toward the first end of the first pad wire 101. The extending direction (inclination direction) of the second inclined portion is a direction intersecting both the first direction X and the second direction Y.

[0541] The second inclined portion crosses the inter-wiring region IWR in the inclined direction. In this embodiment, the intersection (point of intersection) of the second inclined portion and the inter-wiring region IWR is located on the boundary 107. The second inclined portion crosses the boundary 107 along the inclined direction and is connected to the second tip portion in the first placement region 105A. Of course, the extension direction (inclination direction) of the second inclined portion may be the second direction Y. In this case, it is preferable that the second inclined portion extend in the second direction Y above the first wiring group 80A or above the inter-wiring region IWR.

[0542] As in the third layout example, the second short-circuit wiring 115 forms a current path for the drain-source current Ids together with the first short-circuit wiring 111 that faces (closely faces) in the first direction X in both the first wiring group 80A and the second wiring group 80B.

[0543] 16F (sixth layout example), first interconnect structure 108 includes a plurality of first outgoing wires 109. The plurality of first outgoing wires 109 includes a first long wire 110 and a single first short wire 111. The layout of first long wire 110 is similar to that of the first layout example.

[0544] The first short wiring 111 is drawn out in a stepwise manner of one or multiple steps (multiple steps in this embodiment) from a region on the second end side of the first pad wiring 101 with respect to the first end (first long wiring 110) of the first pad wiring 101. The first short wiring 111 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in the region between the first pad wiring 101 and the second pad wiring 102.

[0545] In the first placement region 105A, the first short-circuiting wiring 111 is electrically connected to at least one (in this embodiment, multiple) first lower wirings 81 of the first wiring group 80A and at least one (in this embodiment, multiple) first lower wirings 81 of the second wiring group 80B. In addition, in the second placement region 105B, the first short-circuiting wiring 111 is electrically connected to at least one (in this embodiment, multiple) first lower wirings 81 of the first wiring group 80A.

[0546] In the second placement region 105B, the first shorting wiring 111 may cover at least one (in this embodiment, a plurality of) first lower wirings 81 and at least one (in this embodiment, a plurality of) second lower wirings 82 of the second wiring group 80B. In this case, the first shorting wiring 111 may be electrically connected to at least one (in this embodiment, a plurality of) first lower wirings 81 of the second wiring group 80B in the second placement region 105B.

[0547] The first short wiring 111 has a first step portion extending in a stepped manner. In this embodiment, the first step portion is drawn out in a stepped manner from the second end side of the first pad wiring 101 toward the first end side of the second pad wiring 102 and connected to the first long wiring 110. The first step portion crosses the inter-wire region IWR and the boundary portion 107 in a stepped manner and is connected to the first long wiring 110 in the second placement region 105B. The first step portion is formed in the second placement region 105B at a distance from the second pad wiring 102 toward the first pad wiring 101 and faces the second pad wiring 102 in the second direction Y.

[0548] The first interconnect structure 108 includes a plurality of second outgoing wires 113. The plurality of second outgoing wires 113 include a second long wire 114 and a single second short wire 115. The layout of the second long wire 114 is similar to that of the first layout example.

[0549] The second short wiring 115 is drawn out in a stepwise manner of one or more steps (multiple steps in this embodiment) from a region on the first end side of the second pad wiring 102 with respect to the second end (second long wiring 114) of the second pad wiring 102. The second short wiring 115 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in the region between the first pad wiring 101 and the second pad wiring 102.

[0550] In the second placement region 105B, the second shorting wiring 115 is electrically connected to at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A and at least one (in this embodiment, multiple) second lower wirings 82 of the second wiring group 80B. In addition, the second shorting wiring 115 is electrically connected to at least one (in this embodiment, multiple) second lower wirings 82 of the second wiring group 80B in the first placement region 105A.

[0551] In the first placement region 105A, the second shorting wiring 115 may cover at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A. In this case, the second shorting wiring 115 may be electrically connected to at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A in the first placement region 105A.

[0552] The second short wiring 115 has a second step portion extending in a stepped manner. In this embodiment, the second step portion is drawn out in a stepped manner from the first end side of the second pad wiring 102 toward the second end side of the first pad wiring 101 and connected to the second long wiring 114. The second step portion crosses the inter-wire region IWR and the boundary portion 107 in a stepped manner and is connected to the second long wiring 114 in the first placement region 105A. The second step portion is formed in the first placement region 105A at a distance from the first pad wiring 101 toward the second pad wiring 102 and faces the first pad wiring 101 in the second direction Y.

[0553] The second step portion extends along the first step portion at a distance from the first step portion. The second step portion preferably extends substantially parallel to the first step portion in both the first direction X and the second direction Y. The second shorting wiring 115 preferably has a planar layout that is substantially congruent with the planar layout of the first shorting wiring 111.

[0554] As in the third layout example, the second short-circuit wiring 115 forms a current path for the drain-source current Ids together with the first short-circuit wiring 111 that faces (closely faces) in the first direction X in both the first wiring group 80A and the second wiring group 80B.

[0555] 16G (seventh layout example), the first short wiring 111 is drawn out in a one-step or multiple-step (multiple-step in this embodiment) staircase shape from a region on the second end side of the first pad wiring 101 with respect to the first end (first long wiring 110) of the first pad wiring 101. The first short wiring 111 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR in the region between the first pad wiring 101 and the second pad wiring 102.

[0556] In the first placement region 105A, the first short-circuiting wiring 111 is electrically connected to at least one (plurality in this embodiment) first lower wiring 81 of the first wiring group 80A and at least one (plurality in this embodiment) first lower wiring 81 of the second wiring group 80B. In addition, in the second placement region 105B, the first short-circuiting wiring 111 is electrically connected to at least one (plurality in this embodiment) first lower wiring 81 of the second wiring group 80B.

[0557] In the second placement region 105B, the first shorting wiring 111 may cover at least one (in this embodiment, a plurality of) first lower wirings 81 and at least one (in this embodiment, a plurality of) second lower wirings 82 of the first wiring group 80A. In this case, the first shorting wiring 111 may be electrically connected to at least one (in this embodiment, a plurality of) first lower wirings 81 of the first wiring group 80A in the second placement region 105B.

[0558] In this embodiment, the first short wiring 111 has a first side portion that is drawn out in the second direction Y from the second end portion of the first pad wiring 101. The first side portion forms one side that extends in the second direction Y with the second end portion of the first pad wiring 101. The first side portion crosses the boundary portion 107 in the second direction Y and is located in the second placement region 105B. The first side portion is formed in the second placement region 105B at a distance from the second pad wiring 102 toward the first pad wiring 101, and faces the second pad wiring 102 in the second direction Y.

[0559] The first short wiring 111 has a first step portion extending in a stepped manner. In this embodiment, the first step portion is drawn out in a stepped manner from the first end side of the first pad wiring 101 toward the second end side of the second pad wiring 102 and connected to the first side portion. Specifically, the first step portion crosses the inter-wire region IWR and the boundary portion 107 in a stepped manner and is connected to the first side portion in the second placement region 105B. The first step portion is formed in the second placement region 105B at a distance from the second pad wiring 102 toward the first pad wiring 101 and faces the second pad wiring 102 in the second direction Y.

[0560] The second shorting wiring 115 is drawn out in a stepwise manner of one or more steps (multiple steps in this embodiment) from the region on the second end side of the second pad wiring 102, and is arranged in the region between the first long wiring 110 and the first shorting wiring 111. In the region between the first pad wiring 101 and the second pad wiring 102, the second shorting wiring 115 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR.

[0561] In the second placement region 105B, the second shorting wiring 115 is electrically connected to at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A and at least one (in this embodiment, multiple) second lower wirings 82 of the second wiring group 80B. In addition, the second shorting wiring 115 is electrically connected to at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A in the first placement region 105A.

[0562] In the first placement region 105A, the second shorting wiring 115 may cover at least one (in this embodiment, a plurality) first lower wirings 81 and at least one (in this embodiment, a plurality) second lower wirings 82 of the second wiring group 80B. In this case, the second shorting wiring 115 may be electrically connected to at least one (in this embodiment, a plurality) second lower wirings 82 of the second wiring group 80B in the first placement region 105A.

[0563] In this embodiment, the second short wiring 115 has a second side portion that is drawn out in the second direction Y from the first end portion of the second pad wiring 102. The second side portion forms one side that extends in the second direction Y with the first end portion of the second pad wiring 102. The second side portion crosses the boundary portion 107 in the second direction Y and is located in the first placement region 105A. The second side portion is formed in the first placement region 105A at a distance from the first pad wiring 101 toward the second pad wiring 102, and faces the first pad wiring 101 in the second direction Y.

[0564] The second short wiring 115 has a second step portion extending in a stepped manner. In this embodiment, the second step portion is drawn out in a stepped manner from the second end side of the second pad wiring 102 toward the first end side of the first pad wiring 101 and connected to the second side portion. Specifically, the second step portion crosses the inter-wire region IWR and the boundary portion 107 in a stepped manner and is connected to the second side portion in the first placement region 105A. The second step portion is formed in the first placement region 105A at a distance from the first pad wiring 101 toward the second pad wiring 102 and faces the first pad wiring 101 in the second direction Y.

[0565] As in the third layout example, the second short-circuit wiring 115 forms a current path for the drain-source current Ids together with the first short-circuit wiring 111 that faces (closely faces) in the first direction X in both the first wiring group 80A and the second wiring group 80B.

[0566] 16H (eighth layout example), first interconnect structure 108 includes a plurality of first outgoing wires 109. The plurality of first outgoing wires 109 includes a first long wire 110 and a single first short wire 111. The layout of first long wire 110 is similar to that of the first layout example.

[0567] The first short wiring 111 is drawn in a polygonal (quadrilateral) shape from a region on the second end side of the first pad wiring 101 relative to the first end (first long wiring 110) of the first pad wiring 101 toward the second pad wiring 102. In the region between the first pad wiring 101 and the second pad wiring 102, the first short wiring 111 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR.

[0568] In this embodiment, the first shorting wiring 111 is formed at a distance from the boundary portion 107 (middle portion) toward the first pad wiring 101, and is not positioned in the second placement region 105B. The first shorting wiring 111 covers at least one (multiple in this embodiment) first lower wiring 81 and at least one (multiple in this embodiment) second lower wiring 82 of the first wiring group 80A in the first placement region 105A. Furthermore, the first shorting wiring 111 covers at least one (multiple in this embodiment) first lower wiring 81 and at least one (multiple in this embodiment) second lower wiring 82 of the second wiring group 80B in the first placement region 105A.

[0569] In the first placement region 105A, the first short-circuiting wiring 111 is electrically connected to at least one (in this embodiment, a plurality) of first lower wirings 81 in the first wiring group 80A and at least one (in this embodiment, a plurality) of first lower wirings 81 in the second wiring group 80B. As in the first layout example, the first short-circuiting wiring 111 is electrically connected to the corresponding first lower wirings 81 via a plurality of first upper via electrodes 117.

[0570] The first interconnect structure 108 includes a plurality of second outgoing wires 113. The plurality of second outgoing wires 113 include a second long wire 114 and a single second short wire 115. The layout of the second long wire 114 is similar to that of the first layout example.

[0571] In this embodiment, the second long wiring 114 is electrically connected to one or more (preferably all) second lower wirings 82 that pass directly below the single first shorting wiring 111 in the first placement region 105A. On the other hand, the second long wiring 114 is electrically isolated from one or more (preferably all) first lower wirings 81 that pass directly below the single first shorting wiring 111. As a result, the second long wiring 114 forms a current path for the drain-source current Ids together with the single first shorting wiring 111 that faces (closely faces) it in the first direction X in the first placement region 105A.

[0572] In this embodiment, the second short wiring 115 is drawn in a polygonal (quadrilateral) shape from a region on the first end side of the second pad wiring 102 relative to the second end (second long wiring 114) of the second pad wiring 102 toward the first pad wiring 101. In the region between the first pad wiring 101 and the second pad wiring 102, the second short wiring 115 covers the first wiring group 80A, the second wiring group 80B, and the inter-wiring region IWR.

[0573] The second shorting wiring 115 is formed at a distance from the boundary 107 (middle portion) toward the second pad wiring 102, and is not positioned in the first placement region 105 A. The second shorting wiring 115 faces the first shorting wiring 111 in the second direction Y across the boundary 107.

[0574] In the second placement region 105B, the second shorting wiring 115 covers at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the first wiring group 80A. In addition, in the second placement region 105B, the second shorting wiring 115 covers at least one (in this embodiment, multiple) first lower wirings 81 and at least one (in this embodiment, multiple) second lower wirings 82 of the second wiring group 80B.

[0575] In the second placement region 105B, the second shorting wiring 115 is electrically connected to at least one (in this embodiment, a plurality) of second lower wirings 82 in the first wiring group 80A and at least one (in this embodiment, a plurality) of second lower wirings 82 in the second wiring group 80B. The second shorting wiring 115 is electrically connected to the corresponding second lower wirings 82 via a plurality of second upper via electrodes 118, as in the second layout example.

[0576] The second short wiring 115 is electrically connected to a portion of one or more second lower wirings 82 covered by the first long wiring 110 on the first wiring group 80A side that is exposed from the first long wiring 110. The second short wiring 115 is electrically connected to a portion of one or more (preferably all) second lower wirings 82 covered by the second long wiring 114 on the second wiring group 80B side that is exposed from the second long wiring 114.

[0577] In this embodiment, the second short wiring 115 is electrically connected to one or more second lower wirings 82 that pass directly below the first long wiring 110 in the second placement region 105B. On the other hand, the second short wiring 115 is electrically disconnected from one or more (preferably all) first lower wirings 81 that pass directly below the first long wiring 110.

[0578] In the second placement region 105B, the second shorting wiring 115 forms a current path of the drain-source current Ids together with the first long wiring 110 that faces (closely faces) in the first direction X. In addition, the second shorting wiring 115 forms a current path of the drain-source current Ids together with the single first shorting wiring 111 that faces (closely faces) in the second direction Y.

[0579] 16I (ninth layout example), the first wiring unit U1 according to the ninth layout example has a modified form of the first pad wiring 101, the second pad wiring 102, and the first interconnect structure 108 according to the first layout example. Fig. 16I shows one first wiring unit U1 that straddles the first wiring group 80A and the second wiring group 80B, and the other first wiring unit U1 that straddles the second wiring group 80B and the third wiring group 80C.

[0580] Hereinafter, the first placement region 105A of one first wiring unit U1 will be referred to as "one first placement region 105A," and the second placement region 105B of one first wiring unit U1 will be referred to as "one second placement region 105B." Furthermore, the first placement region 105A of the other first wiring unit U1 will be referred to as "the other first placement region 105A," and the second placement region 105B of the other first wiring unit U1 will be referred to as "the other second placement region 105B."

[0581] One first wiring unit U1 is disposed above the first wiring group 80A and the second wiring group 80B. That is, the first pad wiring 101 and the second pad wiring 102 of the one first wiring unit U1 are disposed above the first wiring group 80A and the second wiring group 80B, respectively, as in the first layout example. In one first wiring unit U1, one wiring group 80 is the first wiring group 80A, and the other wiring group 80 is the second wiring group 80B.

[0582] The other first wiring unit U1 is disposed above the second wiring group 80B and the third wiring group 80...

Claims

1. one and another wiring group arranged at an interval in a first direction X, the one and another wiring group including a plurality of first lower wirings and a plurality of second lower wirings arranged in stripes extending in the first direction X; a first pad wiring disposed on one and the other of the wiring groups and electrically connected to at least one of the first lower wirings of each of the wiring groups; a second pad wiring arranged on one and the other of the wiring groups at a distance from the first pad wiring in a second direction Y intersecting the first direction X, and electrically connected to at least one second lower wiring of each of the wiring groups.

2. 2. The semiconductor device according to claim 1, wherein each of the wiring groups includes a plurality of the first lower wirings and a plurality of the second lower wirings arranged alternately in the second direction Y.

3. the first pad wiring overlaps both the first lower wiring and the second lower wiring of each of the wiring groups; 2. The semiconductor device according to claim 1, wherein said second pad wiring overlaps both said first lower wiring and said second lower wiring of each of said wiring groups.

4. at least one first lead-out wiring that is led out from the first pad wiring in the second direction Y and is electrically connected to the first lower wiring in a region between the first pad wiring and the second pad wiring; 2. The semiconductor device according to claim 1, further comprising: at least one second lead-out wiring that is led out from the second pad wiring in the second direction Y and is electrically connected to the second lower wiring in a region between the first pad wiring and the second pad wiring.

5. 5. The semiconductor device according to claim 4, wherein at least one of said second lead-out wirings faces said first lead-out wiring in said first direction X.

6. 5. The semiconductor device according to claim 4, wherein at least one of said first lead-out wirings is electrically connected to said first lower wiring of one of said wiring groups.

7. 5. The semiconductor device according to claim 4, wherein at least one of said first lead-out wirings is electrically connected to said first lower wiring of another of said wiring groups.

8. 5. The semiconductor device according to claim 4, wherein at least one of said first lead wirings faces said second pad wiring in said first direction X.

9. 5. The semiconductor device according to claim 4, wherein at least one of said first lead wirings faces said second pad wiring in said second direction Y.

10. 5. The semiconductor device according to claim 4, wherein at least one of said second lead-out wirings is electrically connected to said second lower wiring of one of said wiring groups.

11. 5. The semiconductor device according to claim 4, wherein at least one of said second lead-out wirings is electrically connected to said second lower wiring of the other of said wiring groups.

12. 5. The semiconductor device according to claim 4, wherein at least one of said second lead wirings faces said first pad wiring in said first direction X.

13. 5. The semiconductor device according to claim 4, wherein at least one of said second lead-out wirings faces said first pad wiring in said second direction Y.

14. further including an inter-wiring area defined between one and the other of the wiring groups; the first pad wiring overlaps the inter-wiring region; the second pad wiring overlaps the inter-wiring region; At least one of the first lead-out wirings is led out to a region outside the inter-wiring region, 5. The semiconductor device according to claim 4, wherein at least one of said second lead-out wirings is led out to a region outside said inter-wiring region and faces said first lead-out wiring in said first direction X with said inter-wiring region sandwiched therebetween.

15. At least one of the first lead-out wirings extends in a strip shape along the inter-wiring region, 15. The semiconductor device according to claim 14, wherein at least one of said second lead-out wirings extends in a strip shape along said inter-wiring region.

16. a plurality of the first lead-out wirings are led out from the first pad wiring; 5. The semiconductor device according to claim 4, wherein a plurality of said second lead-out wirings are led out from said second pad wiring.

17. a first pad electrode disposed on the first pad wiring; 17. The semiconductor device according to claim 1, further comprising: a second pad electrode disposed on said second pad wiring.

18. further including intermediate wirings arranged in a region between one and the other of the wiring groups; the first pad wiring overlaps the intermediate wiring; 17. The semiconductor device according to claim 1, wherein the second pad wiring overlaps the intermediate wiring.

19. Chips and a device structure formed on the chip, the device structure including a first application terminal to which a first potential is applied and a second application terminal to which a second potential different from the first potential is applied; the plurality of first lower wirings are electrically connected to the first application terminal on the chip; 17. The semiconductor device according to claim 1, wherein the second lower wirings are electrically connected to the second application terminal on the chip.

20. one and another wiring group arranged at an interval from each other, the one and another wiring group including a plurality of first lower wirings and a plurality of second lower wirings, respectively; an inter-wiring area defined between the one and the other wiring groups; a first pad wiring disposed on the inter-wiring region; a second pad wiring disposed on the inter-wiring region and spaced apart from the first pad wiring; a first lead-out wiring that is led out from the first pad wiring to a region outside the inter-wiring region and is electrically connected to the first lower wiring of one of the wiring groups; a second lead-out wiring that is led out from the second pad wiring to a region outside the inter-wiring region so as to face the first lead-out wiring across the inter-wiring region, and is electrically connected to the second lower wiring of the other of the wiring groups.