Power Amplifier and Bias Circuit

Abstract

A power amplifier according to the present disclosure comprises a plurality of transistors connected in series and a bias circuit, the bias circuit having a step-down circuit that steps down a power supply voltage and a resistance circuit connected to the output of the step-down circuit, the resistance circuit having a plurality of first resistors connected between the gate terminals of adjacent transistors from a second transistor adjacent to a first transistor connected closest to the ground terminal to a final transistor connected closest to the power supply terminal and between the gate terminal of the second transistor and the ground terminal, and the step-down circuit is configured so that the amount of step-down is greater when the control signal has a second value than when the control signal has a first value.

Description

[Technical field]

[0001] The present disclosure relates to power amplifiers and bias circuits. [Background technology]

[0002] Non-Patent Document 1 discloses a technique for operating a complementary metal-oxide-semiconductor (CMOS) as a power amplifier. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] S. Pornpromlikit, et al., A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS, IEEE Transactions on Microwave Theory and Techniques, vol. 58, no. 1, pp. 57-64, Jan. 2010. Summary of the Invention [Problem to be solved by the invention]

[0004] Power amplifiers for mobile terminals mainly use GaAs HBTs (Heterojunction Bipolar Transistors). This is because they can operate with a single power supply in a normally-off mode, and can operate with a 3.7V Li-ion battery voltage. In addition, power amplifiers using GaAs HBTs have a higher power density than GaAs FETs (Field Effect Transistors) in the output power range up to a few watts. This allows the chip area to be reduced when the power amplifier is made into an integrated circuit. Furthermore, they can achieve a much higher yield than GaAs-based FETs.

[0005] However, in recent years, power amplifiers, band-changing switches, and antenna switches generally have a CMOS control circuit that enables digital control in addition to the GaAs HBT in order to simplify control within the terminal. GaAs HBT chips, which are not Si-based, are difficult to integrate with digital control circuits. Furthermore, GaAs HBT chips are more expensive to mass-produce than CMOS chips. Against this background, there has been a strong desire to convert power amplifiers to CMOS.

[0006] The standard voltage of a CMOS FET is 1.2V in a 65nm process and 1.8V in a 0.18μm process, which is considerably lower than the battery voltage of 3.7V. For this reason, the battery voltage cannot be directly used for a power amplifier composed of a single stage of CMOS FET. In this context, as shown in Non-Patent Document 1, for example, stacked type power amplifiers that can operate CMOS as a power amplifier at as high a power supply voltage as possible are attracting attention.

[0007] However, in a stack-type power amplifier, when the gate voltage of a transistor is set to zero in the standby state, there is a possibility that a voltage that significantly exceeds the withstand voltage value may be applied as the gate-drain voltage or drain-source voltage of the transistor.

[0008] An object of the present disclosure is to provide a power amplifier and a bias circuit that can provide a voltage that does not exceed a withstand voltage to a transistor. [Means for solving the problem]

[0009] A power amplifier according to the present disclosure comprises a plurality of transistors each having a source terminal, a drain terminal, and a gate terminal, the plurality of transistors being connected in series between a power supply terminal providing a power supply voltage and a ground terminal by connecting the drain terminals and source terminals of adjacent transistors, and a bias circuit configured to supply a gate voltage to the gate terminals of the plurality of transistors such that the plurality of transistors are in an operating state when a control signal input from outside has a first value and the plurality of transistors are in a standby state when the control signal has a second value, wherein in the operating state, the plurality of transistors amplify a signal input from a gate terminal of a first transistor among the plurality of transistors that is connected closest to the ground terminal side and output the signal from a drain terminal of a final transistor among the plurality of transistors that is connected closest to the power supply terminal side, the bias circuit comprising: a step-down circuit that steps down the power supply voltage; and a resistor circuit connected to an output of the step-down circuit, the resistor circuit comprising a plurality of first resistors connected between the gate terminals of adjacent transistors from a second transistor adjacent to the first transistor to the final transistor among the plurality of transistors and between the gate terminal of the second transistor and the ground terminal, the step-down circuit includes a source follower connected between a terminal for providing the power supply voltage and the resistance circuit, and the bias circuit is configured such that a gate voltage of the source follower is smaller when the control signal has the second value than when the control signal has the first value; The step-down circuit is configured so that the amount of step-down is greater when the control signal has the second value than when the control signal has the first value.

[0010] A bias circuit according to the present disclosure includes a step-down circuit that steps down a power supply voltage, and a resistor circuit connected to an output of the step-down circuit, and is configured to supply gate voltages to gate terminals of a plurality of transistors connected in series between a power supply terminal that provides the power supply voltage and a ground terminal, the plurality of transistors being in an operating state when a control signal input from outside has a first value, and in a standby state when the control signal has a second value, the plurality of transistors in the operating state amplify a signal input from a gate terminal of a first transistor that is connected closest to the ground terminal among the plurality of transistors, and output the signal from a drain terminal of a final transistor that is connected closest to the power supply terminal among the plurality of transistors, the resistor circuit having a plurality of first resistors connected between gate terminals of adjacent transistors from a second transistor adjacent to the first transistor to the final transistor among the plurality of transistors, and between the gate terminal of the second transistor and the ground terminal, the step-down circuit includes a source follower connected between a terminal for providing the power supply voltage and the resistor circuit, and the bias circuit is configured such that a gate voltage of the source follower is smaller when the control signal has the second value than when the control signal has the first value; The step-down circuit is configured so that the amount of step-down is greater when the control signal has the second value than when the control signal has the first value. Effect of the Invention

[0011] In the power amplifier and bias circuit according to the present disclosure, the amount of step-down of the step-down circuit can be changed to provide a gate voltage of the transistor in an operating state and a gate voltage in a standby state, thereby providing a voltage that does not exceed the withstand voltage of the transistor. [Brief description of the drawings]

[0012] [Figure 1] FIG. 2 is a diagram illustrating a circuit configuration of a power amplifier according to a first embodiment. [Diagram 2] FIG. 1 is a diagram illustrating a circuit configuration of a cascode power amplifier according to a comparative example. [Diagram 3] 1A and 1B are diagrams illustrating a bias state of a cascode power amplifier according to a comparative example. [Figure 4] FIG. 2 is a diagram illustrating a configuration of a stacked amplification stage in a four-stage stacked power amplifier. [Diagram 5] 1 is a diagram illustrating an example in which a bias circuit of a cascode type power amplifier according to a comparative example is modified for use in a stack type power amplifier; [Figure 6] 4A and 4B are diagrams illustrating an example of a bias state of the power amplifier according to the first embodiment. [Figure 7] FIG. 11 is a diagram illustrating a circuit configuration of a power amplifier according to a second embodiment. [Figure 8] FIG. 11 is a diagram illustrating a circuit configuration of a power amplifier according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] A power amplifier and a bias circuit according to each embodiment will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and the repeated description may be omitted.

[0014] Embodiment 1 1 is a diagram illustrating a circuit configuration of a power amplifier 100 according to a first embodiment. The power amplifier 100 includes a plurality of transistors Ma1, Ma2, Ma3, and Ma4, and a bias circuit 50. Each of the transistors Ma1 to Ma4 is an FET. Each of the plurality of transistors Ma1 to Ma4 has a source terminal, a drain terminal, and a gate terminal. The plurality of transistors Ma1 to Ma4 are connected in series between a power supply terminal 10 that provides a power supply voltage Vdd and a ground terminal GND by connecting the drain terminal and source terminal of adjacent transistors. The plurality of transistors Ma1 to Ma4 form a stacked type amplification stage 80.

[0015] The CMOS process of the stacked amplifier stage 80 is, for example, 65 nm CMOS, and the standard withstand voltage is, for example, 1.2 V. The transistors Ma1 to Ma5 are 65 nm nMOS with a withstand voltage of 1.2 V. The bias circuit 50 can employ, for example, 5 V CMOS. In the bias circuit 50, the transistors Mc1 to Mc4 are pMOS with a withstand voltage of 5 V, and the transistors Mb1 to Mb4 are nMOS with a withstand voltage of 5 V.

[0016] The capacitors C2 to C4 are capacitances that connect the gates of the stacked transistors Ma2 to Ma4 to GND in an RF (Radio Frequency) manner. The capacitors C2 to C4 do not completely ground the gates in an RF manner, as in a gate-grounded amplifier. The capacitance values ​​of the capacitors C2 to C4 are set so that Vg2 to Vg4 vary in conjunction with the drain voltages of the transistors Ma2 to Ma4 at the operating frequency.

[0017] The bias circuit 50 is configured to supply a gate voltage to the gate terminals of the plurality of transistors Ma1 to Ma4 in response to a control signal Ven input from the outside. When the control signal Ven has a first value, a gate voltage is supplied so that a predetermined bias current Id flows through the plurality of transistors Ma1 to Ma4 and the transistors are in an operating state. When the control signal Ven has a second value, a gate voltage is supplied so that the bias current Id becomes zero and the plurality of transistors Ma1 to Ma4 are in a standby state. This makes it possible to suppress unnecessary current consumption when the power amplifier 100 is not performing an amplification operation. In the example of FIG. 1, the first value of the control signal Ven is High and the second value is Low. The terminal Ven to which the control signal Ven is input is generally also called an enable terminal.

[0018] The bias circuit 50 includes a reference current source Iref for supplying a predetermined current to the first transistor Ma1 in an operating state. The transistors Mc3 and Mc4 form a current mirror. Therefore, a current I1 flows whose value corresponds to the reference current source Iref. The transistors Ma5 and Ma1 form a current mirror. Therefore, a bias current Id whose value corresponds to the current I1 flows.

[0019] In an operating state, the multiple transistors Ma1 to Ma4 amplify a signal input from the gate terminal of the first transistor Ma1, which is connected closest to the ground terminal GND, and output the amplified signal from the drain terminal of the last transistor Ma4, which is connected closest to the power supply terminal 10. A signal is input from the input terminal IN to the gate terminal of the first transistor Ma1 via an input matching circuit 81. The signal output from the drain terminal of the last transistor Ma4 is output from the output terminal OUT to the outside of the power amplifier 100 via an output matching circuit 82.

[0020] In the power amplifier 100, when the power supply voltage Vdd is boosted to, for example, 4.8 V, in order to apply a voltage required as the gate voltage Vg4 of the final transistor Ma4, it is necessary to boost the power supply voltage Vbat of the bias circuit 50 in conjunction with Vdd. That is, the power supply voltage Vbat of the power supply terminal 12 is Vdd. The fact that this link between Vbat and Vdd is necessary differs from the bias circuit 151 of the cascode power amplifier 101 according to the comparative example described later.

[0021] The bias circuit 50 includes a step-down circuit 14 that steps down the power supply voltage Vbat, and a resistor circuit 16 connected to the output of the step-down circuit 14. The resistor circuit 16 includes resistors R1 and R2 connected between the gate terminals of adjacent transistors from the second transistor Ma2 adjacent to the first transistor Ma1 to the final transistor Ma4 among the plurality of transistors Ma1 to Ma4. The resistor circuit 16 further includes a resistor R3 connected between the gate terminal of the second transistor Ma2 and the ground terminal GND.

[0022] The step-down circuit 14 is configured so that the amount of step-down is greater when the control signal Ven has a second value than when it has a first value. This will be described with a specific example. The bias circuit 50 includes a two-value reference current source Icon. The control signal Ven is input to the reference current source Icon via an inverter INV. The reference current source Icon has a function of passing two currents Ia and Ib according to the inverted voltage of the control signal Ven. Here, Ib>Ia. That is, the reference current source Icon passes a first current Ia when the control signal Ven has a first value, and passes a second current Ib larger than the first current Ia when the control signal Ven has a second value.

[0023] The step-down circuit 14 includes a source follower Mb3, which is an nMOS, connected between a power supply terminal 12 that provides a power supply voltage Vbat and a resistor circuit 16. A resistor R4 is connected between the power supply terminal 12 and the gate terminal of the source follower Mb3. The bias circuit 50 also includes a current mirror for passing a current corresponding to the current of the reference current source Icon through the resistor R4. This current mirror is composed of transistors Mc1, Mc2, Mb1, and Mb2. A current I2 having a value corresponding to the current of the reference current source Icon flows through the current mirror composed of the transistors Mc1 and Mc2. A current I3 having a value corresponding to the current I2 flows through the current mirror composed of the transistors Mb1 and Mb2.

[0024] That is, by the current mirror composed of the transistors Mc1, Mc2, Mb1, and Mb2, the current flowing through the resistor R4 is larger when the current of the reference current source Icon is Ib than when it is Ia. In this way, the bias circuit 50 is configured so that the current flowing through the resistor R4 is larger when the control signal Ven has the second value than when it has the first value. In other words, it can be said that the bias circuit 50 is configured so that the gate voltage of the source follower Mb3 is smaller when the control signal Ven has the second value than when it has the first value. The source voltage of the source follower Mb3 follows the gate voltage. Therefore, in the step-down circuit 14, the amount of step-down is larger when the control signal Ven has the second value than when it has the first value.

[0025] The amount of step-down by the step-down circuit 14 when the control signal Ven has a second value is set so that the gate-source voltages of the transistors from the second transistor Ma2 to the final transistor Ma4 are 0 V. This allows the multiple transistors Ma1 to Ma4 to be in an operating state when the control signal Ven has a first value, and in a standby state when the control signal Ven has a second value.

[0026] Next, a problem with a four-stage stacked power amplifier using a 65 nm CMOS process in which the standard voltage of the FET is 1.2 V will be described using a comparative example. Fig. 2 is a diagram illustrating the circuit configuration of a cascode power amplifier 101 according to the comparative example. The cascode power amplifier 101 includes a cascode amplification stage 181 and a bias circuit 151.

[0027] The cascode amplifier stage 181 has cascode-connected transistors Mm11 and Mm12 for power amplification. The gate terminal of the transistor Mm11, which is a common-source amplifier stage, is connected to the gate terminal of the transistor Mn3 via a resistor Rgg1. The transistors Mm11 and Mn3 form a current mirror. This allows a bias to be applied to the transistor Mm11. The gate terminal of the transistor Mm12, which is a common-gate amplifier stage, is connected to the connection point of the transistor Mp4 and the resistor Rgref2 via a resistor Rgg2. In this way, a constant voltage is applied to the gate terminal of the transistor Mm12 via the resistor Rgref2.

[0028] A capacitor Cg1 is connected between the gate terminal of the transistor Mn3 and a ground terminal. A capacitor Cg2 is connected between the gate terminal of the transistor Mm12 and a ground terminal. Iref is a reference current source.

[0029] The transistors Mm11 and Mn3 are manufactured in a 65 nm 1.2 V process. The transistors Mm12 and Mp1 to Mp5 are manufactured in a 5 V withstand process using an oxide film thicker than the 65 nm gate oxide film.

[0030] Next, the operation of the inverter INV and transistors Mp4 and Mp5 that control the ON / OFF of the circuit will be described. When the voltage of terminal Ven is High, transistors Mp4 and Mp5 are ON, and a predetermined drain current flows through transistors Mm11 and Mm12. On the other hand, when the voltage of terminal Ven is Low, transistors Mp4 and Mp5 are OFF, and the drain current of transistors Mm11 and Mm12 becomes 0. At this time, the gate voltage of transistor Mm11 is 0V, and the gate voltage of transistor Mm12 is also 0V. The power supply voltage Vbat of bias circuit 151 is constant at 3.7V, which is the standard voltage of a Li-ion battery.

[0031] Fig. 3 is a diagram for explaining the bias state of the cascode power amplifier 101 according to the comparative example. Fig. 3 shows an example of the voltage state of each node with respect to the power supply voltage Vdd of the cascode power amplifier 101 and the value of the control signal Ven. In Fig. 3, "Operation" indicates the operating state, and "Stand-by" indicates the standby state. For example, assume that the power supply voltage Vdd is boosted to 5V. At this time, as shown in Operation (A), each node and the voltage between the nodes satisfy the withstand voltages of 1.2V and 5V. In Stand-by (A1) and (A2), each node and the voltage between the nodes also satisfy the withstand voltages.

[0032] In contrast, if Vdd is boosted to 6 V, as shown in Stand-by (B1), the drain-source voltage Vds (m12) of transistor Mm12 will be 6 V, exceeding the withstand voltage of 5 V. However, if the boost of Vdd is limited to 5 V, the problem of exceeding the withstand voltage can be avoided.

[0033] FIG. 4 is a diagram for explaining the configuration of a stacked amplifier stage 80 in a four-stage stacked power amplifier. In the stacked amplifier stage 80, fine CMOS are stacked vertically to enable high-output operation. In the stacked amplifier stage 80, a transistor that has a low withstand voltage when used alone is stacked vertically to eliminate insufficient withstand voltage. Furthermore, the 65 nm nMOS has a lower ON resistance and a higher mutual conductance gm than a 5 V withstand voltage nMOS. Therefore, the high-frequency characteristics are better than those when using 5 V transistors. Therefore, higher efficiency and gain can be expected than in the configuration of FIG. 2.

[0034] Furthermore, compared to the 2 GHz and below that was mainstream up until the 4th generation mobile communication systems, the frequency bands that will become mainstream in the 5th generation mobile communication systems will be higher frequencies such as 3.5 GHz and 4.5 GHz. For this reason, it may be difficult to achieve high gain and highly efficient amplification operation in 5V withstand voltage nMOS, which has a thicker gate oxide film than 65nm CMOS.

[0035] In the stacked amplifier stage 80, if it is assumed that the multiple amplifying transistors Ma1 to Ma4 operate evenly, it can operate up to a power supply voltage Vdd of 4.8 V. The standard voltage of a Li-ion battery is 3.7 V, but it is assumed that the voltage is boosted to 4.8 V by a DC-DC converter for high output power operation, and the amplifier operates with an output power of 1 W. Note that Vg1 is connected to the gate of the first transistor Ma1 in a DC manner.

[0036] Next, consider the case where the bias circuit based on the concept shown in Fig. 2 is applied to the stacked amplifier stage 80 in Fig. 4. Fig. 5 is a diagram for explaining an example in which the bias circuit 151 of the cascode power amplifier 101 according to the comparative example is modified for use in a stacked power amplifier. In the bias circuit 152 shown in Fig. 5, resistors Rgref3 and Rgref4 are added in addition to the resistor Rgref2 in Fig. 2. Gate voltages Vg2, Vg3, and Vg4 are generated from the connection node of the resistors Rgref2, Rgref3, and Rgref4.

[0037] When the stacked amplifier stage 80 is combined with the bias circuit 152, a bias is applied to Vg1 to Vg4 in the operating state, so no problems with the withstand voltage arise. However, in the standby state, when Vdd=4.8V, Vbat=4.8V, and Ven=0V, all of the gate voltages Vg1 to Vg4 of the transistors Ma1 to Ma4 become 0V. At this time, 4.8V is applied to the gate-drain voltage and drain-source voltage Vds of the final transistor Ma4. This value significantly exceeds the withstand voltage value of 1.2V. Similarly, when the standard voltage is Vdd=3.7V, Vds=3.7V is applied to the final transistor Ma4, which also exceeds the withstand voltage value.

[0038] Of course, the problem of the nMOS withstand voltage in the standby state can be solved by setting Vdd and Vbat to 0 V at the same time as Ven = 0 V. However, in general, in mobile phone terminals, when the terminal power is not turned off, the control signal Ven is simply set to Low, and Vbat and Vdd are not set to 0 V.

[0039] In contrast, in the power amplifier 100 and bias circuit 50 of this embodiment, it is possible to provide gate voltages for a plurality of transistors Ma2 to Ma4 in the operating state and the standby state by changing the step-down amount of the step-down circuit 14. Therefore, even if the bias current is set to 0 when the power supply voltage Vdd is boosted, it is possible to provide a voltage that does not exceed the withstand voltage for the transistors Ma2 to Ma4.

[0040] This will be explained in more detail. First, the operating state in which the drain current required for the amplification operation flows will be explained. The first transistor Ma1 forms a current mirror with the transistor Ma5, which is the same type of nMOS. This allows a predetermined bias current Id to flow. In this way, the bias current Id of the entire amplifier is determined by the bias current of the first transistor Ma1.

[0041] The source terminal of the source follower Mb3 is connected to the gate terminal of the final transistor Ma4. The gate terminal of the final transistor Ma4 is connected to the gate terminal of the third transistor Ma3 via a resistor R1. The gate terminal of the third transistor Ma3 is connected to the gate terminal of the second transistor Ma2 via a resistor R2.

[0042] The gate voltage Vg(Mb3) of the source follower Mb3 is determined by the amount of step-down R4·I3 due to the resistor R4 and the current I3. As described above, in this embodiment, the amount of step-down R4·I3 is appropriately increased in the standby state compared to the operating state, thereby turning off the transistors Ma2 to Ma4 while maintaining the 1.2V withstand voltage standard. When turning off the transistors Ma1 to Ma4, the value of the reference current source Icon is switched from Ia to Ib. At this time, I3 increases due to the current mirror. As a result, the amount of step-down due to R4·I3 increases, and the gate voltage Vg(Mb3) of the source follower decreases. Accordingly, Vg4, Vg3, and Vg2 decrease, and the transistors Ma2 to Ma4 can be turned off.

[0043] With regard to Vg1, when the transistor Mb4 is turned ON, the gate voltage of the transistor Ma5 becomes 0 V, and the gate voltage Vg1 of the first transistor Ma1 also becomes 0 V. This turns the first transistor Ma1 OFF.

[0044] Fig. 6 is a diagram for explaining an example of the bias state of the power amplifier 100 according to the first embodiment. Fig. 6 shows examples of the bias state in an operation state and a standby state. The power supply voltage Vdd is set to 4.8 V. In addition, the gate-source voltage for causing the transistors Ma1 to Ma4 to flow a predetermined drain current is set to 0.4 V.

[0045] In a stacked power amplifier, the transistors Ma1 to Ma4 have the same gate width, and the same gate-source voltage and drain-source voltage are basically applied to them. Therefore, when Vdd=4.8V, a voltage of 1.2V is applied between the drain and source of each of the transistors Ma1 to Ma4. In this case, since the drain voltage of the first transistor Ma1 is 1.2V, Vg2 requires 1.2+0.4=1.6V. Similarly, Vg3 and Vg4 require 2.8V and 4.0V, respectively.

[0046] Therefore, the gate voltage Vg(Mb3) of the source follower Mb3 should be set so that the source potential of the source follower Mb3 is 4.0V. In the example of Figure 6, the gate-source voltage of the source follower Mb3, which is a 5V withstand voltage nMOS, is set to 0.5V. In addition, the current I4 and the resistance values ​​of the resistors R1, R2, and R3 are set so that Vg4=4.0V, Vg3=2.8V, and Vg2=1.6V. In addition, since Vdd=4.8V and Vg(Mb3)=4.5V, R4·I3=0.3V. Therefore, (R1+R2+R3)·I4=4.0V, (R2+R3)·I4=2.8V, and R3·I4=1.6V hold, so the values ​​of the resistors R1 to R3 are uniquely determined by determining I4.

[0047] In the standby state of FIG. 6, the drain current of transistors Ma1 to Ma4 is set to 0 while maintaining the drain-source voltage of each transistor at 1.2V. Therefore, when Vg1 is set to 0V, the gate-source voltage of transistors Ma2 to Ma4 is also set to 0V. This can be achieved by increasing I3 and changing the step-down amount R4·I3 from 0.3V to 0.7V. At this time, the same current I4 as in the operating state flows through resistors R1 to R3, so Vg4 to Vg2 shift by the increase in the step-down amount. As a result, Vg4=3.6V, Vg3=2.4V, and Vg2=1.2V, and the gate-source voltages of transistors Ma2 to Ma4 are all 0V. In other words, the gate-source voltages of transistors Ma2 to Ma4 are in the same voltage state as the first transistor Ma1. Therefore, the drain current of transistors Ma1 to Ma4 can be set to 0 while satisfying the 1.2V withstand voltage standard.

[0048] In this manner, according to this embodiment, in both the operating state and the standby state, it is possible to easily realize a state in which the idle current required for amplification operation flows and a state in which the drain current is zero while maintaining the withstand voltage specifications of the multiple transistors Ma1 to Ma4.

[0049] In addition, CMOS transistors have achieved low power consumption and high speed operation based on the scaling law. For example, with a gate length of 0.5 μm and a gate oxide film thickness of 130 Å, it can only operate up to 3 GHz, but with a gate length of 0.18 μm and a gate oxide film thickness of 30 Å, it can operate at about 10 GHz. On the other hand, with a gate length of 0.5 μm, it is possible to guarantee operation for 10 years even if up to 5 V is applied, but with a gate length of 0.18 μm, it is necessary to limit the applied voltage to 1.8 V, for example, to guarantee operation for 10 years. If 2.5 to 3 V is applied to a 0.18 μm transistor, the lifespan will be shortened to about 0.5 to 1 year.

[0050] Thus, to guarantee the 10-year operation required for ordinary semiconductor products, it is essential that the voltage between the terminals of the transistors used in the circuit is within the voltage range determined by the CMOS process used. The bias circuit of this embodiment can provide a voltage within the range determined by the process for all transistors. This prevents the life of the power amplifier from being shortened, and maintains the long life guaranteed by the process.

[0051] In addition, in this embodiment, a simple configuration of a step-down circuit 14 consisting of a source follower Mb3 and a resistor R4, and resistor division, can provide an appropriate voltage to a plurality of transistors Ma1 to Ma4. In addition, the amount of step-down of the source follower Mb3 is controlled using a current mirror that reflects the value of the reference current source Icon. Therefore, an appropriate voltage can be provided at low cost with an even simpler configuration. For example, if the gate voltage of each amplification stage is precisely controlled by a digital-to-analog converter (DAC), the voltage during amplification operation and the voltage when OFF can be appropriately applied. However, the area of ​​the bias circuit becomes large, which may lead to an increase in costs. In contrast, in this embodiment, the gate voltage of each amplification stage can be controlled with a small-scale circuit.

[0052] As a modification of this embodiment, the number of series-connected transistors included in the stacked amplifier stage 80 is not limited as long as it is two or more. The configuration of the bias circuit 50 is also not limited to that shown in Fig. 1. The bias circuit 50 may be configured so that the amount of step-down of the step-down circuit 14 is larger when the control signal has a second value than when the control signal has a first value, thereby switching the multiple transistors Ma1 to Ma4 between an operating state and a standby state.

[0053] In addition, in this embodiment, Vdd and Vbat are the same power supply, but Vdd and Vbat may be supplied from different power supplies as long as they have the same voltage value.

[0054] The above-mentioned modifications can be appropriately applied to the power amplifiers and bias circuits according to the following embodiments. Note that the power amplifiers and bias circuits according to the following embodiments have many points in common with the first embodiment, so the following description will focus on the differences from the first embodiment.

[0055] Embodiment 2 7 is a diagram illustrating a circuit configuration of a power amplifier 200 according to the second embodiment. The power amplifier 200 differs from the power amplifier 100 of the first embodiment in the configuration of a bias circuit 250. The bias circuit 250 further includes a current mirror for causing a current corresponding to the current of the reference current source Iref to flow through the resistance circuit 16. The current mirror is composed of a transistor Ma5 and a transistor Ma6 connected between the resistor R3 and the ground terminal GND. The other configurations are the same as those of the first embodiment.

[0056] Transistor Ma6 passes a mirror current of transistor Ma5. The drain terminal of transistor Ma6 is connected to resistor R3. As a result, the value of current I4 is determined by the reference current source Iref and the mirror ratio of transistors Ma5 and Ma6. Note that transistor Mb5, like transistor Mb4, is turned ON in the standby state. As a result, the drain voltage of transistor Ma6 becomes 0V in the standby state.

[0057] In the first embodiment, the value of the current I4 changes between the operating state and the standby state. Therefore, the values ​​of Vg4 to Vg2 may have some error with respect to the target voltage value. In contrast, in the present embodiment, the value of the current I4 is set based on the reference current source Iref. Therefore, even when the gate voltage Vg (Mb3) of the source follower Mb3 changes from 4.5V to 4.1V, the current I4 does not change. That is, the same amount of current flows through the resistance circuit 16 in the operating state and the standby state. Therefore, Vg4 to Vg2 can be set to the target voltage value in both the operating state and the standby state.

[0058] Embodiment 3 8 is a diagram illustrating a circuit configuration of a power amplifier 300 according to the third embodiment. The power amplifier 300 differs from the power amplifier 200 of the second embodiment in the configuration of a bias circuit 350. In the bias circuit 350, transistors Mc5 to Mc8, which are pMOS with a withstand voltage of 5 V, are further added to the paths of the currents I1 to I4. The transistors Mc5 to Mc8 are controlled by a signal from a terminal Ven2.

[0059] In the first and second embodiments, even if the drain currents of the transistors Ma1 to Ma4 become 0, the current on the bias circuit side is not cut off. This is because in the first and second embodiments, the necessary current flows on the bias circuit side and the gate-source voltages of the transistors Ma1 to Ma4 are set to 0, thereby making the bias current Id 0 without exceeding the withstand voltage. However, when the power supply voltage Vdd of the stacked power amplifier is 1.2 V or less, even if the gate voltages Vg2 to Vg4 are set to 0 V when Ven=0 V as in the bias circuit 152 in FIG. 5, a voltage exceeding the withstand voltage is not applied to the transistors Ma1 to Ma4.

[0060] In this embodiment, the bias circuit 350 further includes a circuit that cuts off the current flowing through the resistance circuit 16 when the control signal Ven has a second value, for example, when the power supply voltage Vdd=Vbat is 1.2V or less. The circuit that cuts off the current flowing through the resistance circuit 16 corresponds to the transistors Mc5 to Mc8. When the control signal Ven has the second value, that is, in the standby state, the transistors Mc5 to Mc8 are turned off by the signal Ven2. This makes it possible to completely cut off the current in the bias circuit 350. In the operating state, the transistors Mc5 to Mc8 are turned on by the signal Ven2.

[0061] The technical features described in each embodiment may be used in appropriate combination. [Explanation of symbols]

[0062] 10, 12 power supply terminal, 14 step-down circuit, 16 resistor circuit, 50 bias circuit, 80 stacked amplifier stage, 81 input matching circuit, 82 output matching circuit, 100 power amplifier, 101 cascode power amplifier, 151 bias circuit, 152 bias circuit, 181 cascode amplifier stage, 200 power amplifier, 250 bias circuit, 300 power amplifier, 350 bias circuit, C2, C3, C4, Cg1, Cg2 capacitor, GND ground terminal, Icon reference current source, IN input terminal, INV inverter, Iref reference current source, Ma1 to Ma6 transistors, Mb1, Mb2 transistors, Mb3 source follower, Mb4, Mb5 transistors, Mc1 to Mc8 transistors, Mm11, Mm12 transistors, Mn3 transistor, Mp1 to Mp5 transistors, OUT Output terminal, R1 to R4 resistors, Rgg1, Rgg2 resistors, Rgref2 to Rgref4, Ven, Ven2 terminals

Claims

1. a plurality of transistors each having a source terminal, a drain terminal, and a gate terminal, the drain terminals and source terminals of adjacent transistors being connected together, the plurality of transistors being connected in series between a power supply terminal providing a power supply voltage and a ground terminal; a bias circuit configured to supply a gate voltage to gate terminals of the plurality of transistors such that the plurality of transistors are in an operating state when a control signal input from an external source has a first value, and the plurality of transistors are in a standby state when the control signal has a second value; Equipped with In the operating state, the plurality of transistors amplify a signal input from a gate terminal of a first transistor among the plurality of transistors that is connected closest to the ground terminal, and output the amplified signal from a drain terminal of a last transistor among the plurality of transistors that is connected closest to the power supply terminal, the bias circuit includes a step-down circuit that steps down the power supply voltage, and a resistor circuit connected to an output of the step-down circuit; the resistor circuit has a plurality of first resistors connected between gate terminals of adjacent transistors from a second transistor adjacent to the first transistor to the final transistor among the plurality of transistors, and between the gate terminal of the second transistor and a ground terminal; 2. A power amplifier comprising: a step-down circuit configured to step down a voltage by a larger amount when the control signal has the second value than when the control signal has the first value.

2. the step-down circuit includes a source follower connected between a terminal providing the power supply voltage and the resistor circuit; 2. The power amplifier according to claim 1, wherein the bias circuit is configured such that a gate voltage of the source follower is smaller when the control signal has the second value than when the control signal has the first value.

3. the step-down circuit further includes a second resistor connected between the terminal for providing the power supply voltage and the gate terminal of the source follower; 3. The power amplifier according to claim 2, wherein the bias circuit is configured such that a current flowing through the second resistor is larger when the control signal has the second value than when the control signal has the first value.

4. The bias circuit includes: a first reference current source that flows a first current when the control signal has the first value and flows a second current larger than the first current when the control signal has the second value; a first current mirror for causing a current corresponding to a current of the first reference current source to flow through the second resistor; 4. The power amplifier according to claim 3, comprising:

5. 5. The power amplifier according to claim 1, wherein the amount of step-down of the step-down circuit when the control signal has the second value is set so that the gate-source voltages of transistors from the second transistor to the final transistor are 0 V.

6. 5. The power amplifier according to claim 1, wherein the bias circuit comprises a second reference current source for causing a predetermined current to flow through the first transistor in the operating state.

7. A second reference current source; a second current mirror for causing a current corresponding to a current of the second reference current source to flow through the resistance circuit; 5. The power amplifier according to claim 1, further comprising:

8. 8. The power amplifier according to claim 7, wherein the same amount of current flows through said resistor circuit in said operating state and in said standby state.

9. 5. The power amplifier according to claim 1, wherein the bias circuit further comprises a circuit that cuts off a current flowing through the resistance circuit when the control signal has the second value.

10. a step-down circuit for stepping down a power supply voltage; a resistor circuit connected to an output of the step-down circuit; Equipped with a plurality of transistors connected in series between a power supply terminal for providing the power supply voltage and a ground terminal are configured to supply gate voltages to gate terminals of the plurality of transistors so that the transistors are in an operating state when a control signal input from outside has a first value and in a standby state when the control signal has a second value; In the operating state, the plurality of transistors amplify a signal input from a gate terminal of a first transistor among the plurality of transistors that is connected closest to the ground terminal, and output the amplified signal from a drain terminal of a last transistor among the plurality of transistors that is connected closest to the power supply terminal, the resistor circuit has a plurality of first resistors connected between gate terminals of adjacent transistors from a second transistor adjacent to the first transistor to the final transistor among the plurality of transistors, and between the gate terminal of the second transistor and a ground terminal; 13. A bias circuit comprising: a step-down circuit configured to step down a voltage by a larger amount when the control signal has the second value than when the control signal has the first value.

Images