Drive device for reverse conduction semiconductor switching element and power conversion device using the same

Abstract

A device for driving a reverse conduction semiconductor switching element (90), in which a semiconductor switching element (Z1) and a rectifying element (D1) are connected in reverse parallel and integrated, said device comprising an on-permission signal generation unit (60) that receives an on / off command signal (SIN) that turns on or off the reverse conduction semiconductor switching element (90) to generate an on-permission signal (SGD), and a gate drive unit (70A) that receives the on-permission signal (SGD) and generates a drive voltage to be applied to a gate terminal (Gs) of the semiconductor switching element (Z1). When the voltage between main terminals that is between a first main terminal (Cs) and a second main terminal (Es) of the semiconductor switching element (Z1) during the period in which the reverse conduction semiconductor switching element (90) is turned off is greater than a first reference voltage (VrefH), the on-permission signal (SGD) is set to an on state, and when the voltage between main terminals is smaller than a second reference voltage (VrefL) different from the first reference voltage, the on-permission signal (SGD) is changed to an off state.

Description

Reverse conducting semiconductor switching element driver and power conversion device using the same

[0001] The present disclosure relates to a drive device for a reverse conducting semiconductor switching element and a power conversion device using the same.

[0002] Power conversion devices, including inverter devices and power conversion units and control units that control the power conversion units, achieve power conversion by turning semiconductor switching elements on and off, and are widely used in consumer, industrial, automotive, and electric railway applications. Examples of semiconductor switching elements include voltage-driven semiconductor switching elements, such as insulated-gate bipolar transistors (IGBTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs). Controlling these semiconductor switching elements requires a semiconductor switching element driver. Generally, these semiconductor switching element drivers control the conduction state of the semiconductor switching elements by applying a voltage to the gates of the semiconductor switching elements.

[0003] In recent years, the use of reverse-conducting IGBTs, which integrate an IGBT with a diode connected in antiparallel to the IGBT, has progressed. This contributes to cost reductions through chip size reductions and to the miniaturization of power converters through reduced thermal resistance. In the drive circuits for semiconductor switching elements in power converters, control independent of the load current direction is used to simplify the control of the semiconductor switching elements. It has been common for the gate of a reverse-conducting IGBT to be turned on even when the diode is conducting. However, turning on the gate of the IGBT while the diode is conducting causes a parasitic n-channel MOSFET to operate, resulting in the inhibition of the diode's bipolar operation and an increase in forward voltage. For this reason, it is common to use isolated reverse-conducting IGBTs, which have an isolation region between the IGBT region and the diode region to suppress mutual interference.

[0004] In response to this, there have been attempts to apply non-isolated reverse-conducting IGBTs by devising a driving method that prevents the gate of the reverse-conducting IGBT from being turned on while the diode of the reverse-conducting IGBT is conducting, with the aim of improving current density by reducing the isolation region. One method for non-isolated reverse-conducting IGBTs involves adding a sense diode that monitors the current flowing through the diode when the diode of the reverse-conducting IGBT is conducting, and controlling the gate of the IGBT so that it is not turned on when the diode of the reverse-conducting IGBT is conducting, thereby suppressing an increase in the forward voltage of the diode due to the operation of a parasitic n-channel MOSFET (see, for example, Patent Document 1).

[0005] The method disclosed in Patent Document 1 directly detects the current flowing through the diode, and therefore can accurately prevent gate on while the diode is conducting, but the addition of a monitoring sense diode increases the chip area of ​​the reverse-conducting IGBT, which leads to a problem of increased costs.As a non-isolated reverse-conducting IGBT that does not require such a monitoring sense diode, there is a method in which the gate is turned on based on the main terminal voltage of the reverse-conducting IGBT during a period when the upper arm and lower arm of a leg circuit in which multiple reverse-conducting IGBTs are connected in series are simultaneously turned off, and the gate is kept on until an off command is input from a higher-level control unit to the reverse-conducting IGBT, thereby suppressing an increase in the forward voltage of the diode due to the operation of a parasitic n-channel MOSFET (see, for example, Patent Document 2).

[0006] Incidentally, the operation of a parasitic n-channel MOSFET while the diode is conducting is known to cause a reduction in short-circuit withstand capability, a problem specific to IGBTs. Generally, the upper and lower arms of a leg circuit can be short-circuited in three ways: a Type 1 short-circuit that occurs when the IGBT is turned on, a Type 2 short-circuit that occurs while the IGBT is conducting, and a Type 3 short-circuit that occurs while the IGBT gate is turned on while the diode is conducting. It has been reported that in MOSFET-mode IGBTs, which reduce the efficiency of hole injection from the collector p-channel layer to increase the proportion of electron current, the space charge in the drift layer becomes negative during a short circuit, increasing the electric field strength on the backside, resulting in a reduction in short-circuit withstand capability (see, for example, Non-Patent Document 1). A Type 3 short-circuit in a reverse-conducting IGBT is a similar situation.

[0007] In other words, in a reverse-conducting IGBT, the operation of a parasitic n-channel MOSFET while a diode connected in anti-parallel to the IGBT is conducting poses a new problem in that it reduces the short-circuit withstand capability during this period, and depending on the device design, it is possible that the device may be destroyed due to a time constant that makes it difficult to protect using known short-circuit protection techniques. In particular, while the collector voltage detection (Desat) method, which is a common short-circuit protection technique, is a low-cost and easily applicable technique, it has a long detection delay, making it difficult to protect against type 3 short circuits in reverse-conducting IGBTs, and the adoption of an expensive short-circuit detection method is unavoidable for protection against this short-circuit mode.

[0008] JP 2008-72848 A JP 2014-216932 A

[0009] Simulation studies for short-circuit current crowding of MOSFET-Mode IGBT, ISPSD, 2014

[0010] The method disclosed in Patent Document 1 requires the addition of a monitoring sense diode, which increases the chip area of ​​the reverse-conducting IGBT and leads to increased costs. The method disclosed in Patent Document 2 does not require a monitoring sense diode, but because it determines the collector voltage only when the upper and lower arms of the leg circuit are simultaneously off, it is unable to properly turn on the gate at the timing when the diode conduction changes to the IGBT conduction. Furthermore, because the gate remains on until a command to turn off the reverse-conducting IGBT is issued from the upper control unit, if the current while the gate is on is commutated from the IGBT to the diode, the parasitic n-channel MOSFET operates, inevitably increasing the diode's forward voltage. This forward voltage can reach several tens to several hundreds of volts, not only increasing losses but also posing a reliability issue. Furthermore, the operation of the parasitic n-channel MOSFET when the diode is conducting may reduce the short-circuit withstand capability, potentially reducing the reverse-conducting IGBT's ability to withstand Type 3 short circuits.

[0011] The present disclosure has been made to solve the above-described problems, and aims to suppress gate-on while the diode of a reverse-conducting IGBT is conducting, prevent an increase in the forward voltage of the diode even when current during gate-on is commutated to the diode, and prevent breakdown due to a type 3 short circuit that occurs during the gate-on period while the diode is conducting.

[0012] A drive device for a reverse-conducting semiconductor switching element according to the present disclosure is a drive device for a reverse-conducting semiconductor switching element in which a semiconductor switching element and a rectifying element connected in anti-parallel to the semiconductor switching element are integrated, and the drive device includes an on-enablement signal generation unit that receives an on-off command signal to turn the reverse-conducting semiconductor switching element on or off and generates an on-enablement signal; a gate drive unit that receives the on-enablement signal and generates a drive voltage to be applied to the gate terminal of the semiconductor switching element and generates a drive voltage to be applied to the gate terminal of the semiconductor switching element; and a voltage determination unit that compares a main terminal voltage between first and second main terminals of the semiconductor switching element with a first reference voltage and a second reference voltage different from the first reference voltage, and by logical synthesis of the determination signal from the voltage determination unit and the on-off command signal, if the main terminal voltage during the period in which the reverse-conducting semiconductor switching element is off is greater than the first reference voltage, the on-enablement signal is turned on, and if the main terminal voltage during the period in which the reverse-conducting semiconductor switching element is off is smaller than the second reference voltage, the on-enablement signal is changed to an off state. Furthermore, the power conversion device according to the present disclosure is provided with a reverse conducting semiconductor switching element drive device according to the present disclosure for each of the reverse conducting semiconductor switching elements of the upper arm and the lower arm connected in series.

[0013] The drive device for a reverse conducting semiconductor switching element according to the present disclosure suppresses gate-on while the diode of the reverse conducting semiconductor switching element is conducting, and even if current is commutated to the diode while the gate is on, it is possible to prevent an increase in the forward voltage of the diode and to prevent breakdown due to a type 3 short circuit that occurs during the gate-on period while the diode is conducting.

[0014] 1 is a block diagram showing an example of the configuration of a driver for a reverse conducting semiconductor switching element according to a first embodiment. FIG. 2 is a block diagram showing a specific example of the driver for a reverse conducting semiconductor switching element according to the first embodiment. FIG. 3 is a diagram showing an example of a time chart of each signal in a normal state in the specific example of the driver for a reverse conducting semiconductor switching element according to the first embodiment. FIG. 4 is a diagram showing an example of a time chart of a second voltage determination signal in the specific example of the driver for a reverse conducting semiconductor switching element according to the first embodiment. FIG. 5 is a diagram showing an example of a time chart of each signal in a short circuit in the specific example of the driver for a reverse conducting semiconductor switching element according to the first embodiment. FIG. 6 is a block diagram showing an example of the configuration of a driver for a reverse conducting semiconductor switching element according to a second embodiment. FIG. 7 is a block diagram showing a specific example of the driver for a reverse conducting semiconductor switching element according to the second embodiment. FIG. 8 is a diagram showing an example of a time chart of each signal in a normal state in the specific example of the driver for a reverse conducting semiconductor switching element according to the second embodiment. FIG. 9 is a block diagram showing an example of the configuration of a driver for a reverse conducting semiconductor switching element according to a third embodiment. FIG. 10 is a block diagram showing a specific example of the driver for a reverse conducting semiconductor switching element according to the third embodiment. FIG. 11 is a diagram showing an example of a time chart of each signal in a normal state in the specific example of the driver for a reverse conducting semiconductor switching element according to the third embodiment. Fig. 10 is a block diagram showing a specific example of a drive device for a reverse conducting semiconductor switching element according to embodiment 4. Fig. 11 is a diagram showing an example of a time chart of each signal in a normal state in a specific example of the drive device for a reverse conducting semiconductor switching element according to embodiment 4. Fig. 12 is a diagram showing an example of the configuration of a power conversion device using a drive device for a reverse conducting semiconductor switching element according to embodiment 5. Fig. 13 is a diagram showing an example of the configuration of a power conversion device using a drive device for a reverse conducting semiconductor switching element according to embodiment 6. Fig. 14 is a diagram showing an example of the configuration of a power conversion device using a drive device for a reverse conducting semiconductor switching element according to embodiment 7.

[0015] The present embodiment will be described below with reference to the drawings. In each drawing, the same reference numerals indicate the same or corresponding parts. Note that FIGS. 1 to 17 relate to one embodiment, and the present disclosure is not limited to these drawings.

[0016] Embodiment 1. Figure 1 is a block diagram showing the configuration of a driver 10A for a reverse conducting semiconductor switching element according to embodiment 1. The following example will be described on the assumption that the driver is applied to a configuration of a leg circuit 91 in which a plurality of reverse conducting semiconductor switching elements 90 are connected in series, as shown in Figures 15 to 17. The reverse conducting semiconductor switching element 90 is exemplified as a reverse conducting IGBT in which an IGBT_Z1 and a diode D1 are integrated. The reverse conducting semiconductor switching element 90 has a collector sense terminal Cs as a first main terminal and an emitter control terminal Es as a second main terminal, and controls the conductive or non-conductive state between the collector C and the emitter E in accordance with a gate voltage Vge applied between the gate terminal Gs and the emitter control terminal Es.

[0017] The reverse-conducting semiconductor switching element driver 10A includes a voltage step-down unit 20, a first voltage determination unit 30, a second voltage determination unit 40, a short-circuit detection unit 50, an on-permission signal generation unit 60, and a gate driver 70A. A positive power supply voltage VP generated based on the emitter control terminal Es is applied to the gate terminal Gs as a gate drive power supply. In this embodiment, the voltage applied to the gate terminal Gs during the gate-off period is set to zero. However, the gate drive power supply may be configured to apply a negative power supply voltage VN. In addition to the gate drive power supply, a separate control power supply for operating logic circuits, etc., may also be provided. In this embodiment, a 5V control power supply is provided, but this is not shown for simplicity.

[0018] The reverse conducting semiconductor switching element driver 10A receives an on / off command signal SIN that is sent from a higher-level logic unit such as a microcomputer and that turns on or off the reverse conducting semiconductor switching element 90, generates an appropriate on enable signal SGD for the reverse conducting semiconductor switching element 90 based on the voltage at the collector sense terminal Cs of the reverse conducting semiconductor switching element 90, and has the function of detecting a short circuit in the reverse conducting semiconductor switching element 90 and providing appropriate protection. The voltage at the collector sense terminal Cs, i.e., the main terminal voltage Vce between the first main terminal and the second main terminal, is stepped down by a voltage step-down unit 20 that reduces the voltage to a signal level, and the resulting signals are input to a first voltage determination unit 30 and a second voltage determination unit 40, respectively.

[0019] The first voltage determination unit 30 determines that the input signal SDE is equal to or greater than a first reference value during the period in which the on / off command signal SIN commands off, and transmits a first voltage determination signal SCH to the on-enablement signal generation unit 60. Meanwhile, the second voltage determination unit 40 determines that the voltage of the input signal SDD is equal to or less than a second reference value, and transmits a second voltage determination signal SGC to the on-enablement signal generation unit 60. The on-enablement signal generation unit 60 changes the on-enablement signal SGD to an on state upon generation of the first voltage determination signal SCH and holds this state in an internal holding circuit, and changes the on-enablement signal SGD to an off state upon generation of the second voltage determination signal SGC or when the on-off command signal changes from on to off.

[0020] If the first voltage determination signal SCH is generated for a predetermined period of time or longer during a period in which the on-enable signal SGD indicates an on state, the short-circuit detection unit 50 determines that the reverse-conducting semiconductor switching element 90 is short-circuited, and transmits a short-circuit detection signal SSC, which has been held for a predetermined period of time, to the gate driver 70A and the on-enable signal generator 60. The generated on-enable signal SGD is logically combined with the short-circuit detection signal SSC by the gate driver 70A. If no short circuit is detected, the on-enable signal SGD is current-amplified to drive the gate terminal Gs. If the short-circuit detection unit 50 detects a short circuit, the on-enable signal SGD and the short-circuit detection signal SSC are logically combined within the gate driver 70A, and the gate terminal Gs is controlled to turn off the gate. At the same time, the short-circuit detection signal SSC is transmitted to the on-enable signal generator 60, and the on-enable signal SGD is changed to an off state.

[0021] The gate driver 70A includes a soft shutdown function that adjusts the gate drive force to reduce surge voltages by shutting off short-circuit current as necessary when a short-circuit detection signal SSC is generated. However, for simplicity, the configuration for implementing this function is omitted. Furthermore, the blocks through which signals are transmitted and received and the blocks that are logically synthesized are not limited to those shown in FIG. 1; the combination of blocks and the transmission and reception of signals can be varied in various ways. Furthermore, the on / off command signal SIN is transmitted between the reference potential of a higher-level logic unit, such as a microcontroller, and the emitter reference potential Es. Therefore, the signal is transmitted and received via isolated communication via an optical conversion module, photocoupler, pulse transformer, or other level shift IC. However, this is also omitted for simplicity. Similarly, the gate drive power supply 11 is an isolated power supply, but for simplicity, details of its generation circuitry and other aspects are omitted.

[0022] 2 is a diagram showing a specific example of a drive device 10A for a reverse-conducting semiconductor switching element 90 according to the first embodiment. The voltage step-down unit 20 shown in FIG. 2 reduces the potential at the collector sense terminal Cs through the rectification operation of a high-voltage diode D20 and voltage division by resistors R20 to R22. However, various known configurations can be applied, such as a configuration in which voltage division is performed using resistors alone or a configuration using a constant voltage diode. The first voltage determination unit 30 has filter characteristics defined by a charging time constant of the filter capacitor C30 and the constant current diode D30, and a discharging time constant defined by the filter capacitor C30 and resistors R20 and R22. When the comparator 31 determines that the input signal SDE is greater (higher) than the first reference voltage VrefH, the first voltage determination unit 30 generates a first voltage determination signal SCH. The second voltage determination unit 40 has filter characteristics of a discharge time constant determined by the filter capacitor C40 and resistor R20, and a charge time constant determined by the filter capacitor C40 and resistor R40, and when the comparator 41 determines that the input voltage SDD is smaller (lower) than the second reference voltage VrefL, it generates a second voltage determination signal SGC.

[0023] The on-enablement signal generating unit 60 is logically synthesized so that when the on-off command signal SIN indicates on and the short-circuit detection signal SSC is at low level, the first voltage determination signal SCH is input to the set input of the flip-flop circuit 66 and the on-enablement signal SGD is held at high level. The flip-flop circuit 66 is logically synthesized so that a reset input is received upon generation of the second voltage determination signal SGC, upon the timing when the on-off command signal SIN indicates off, or upon generation of the short-circuit detection signal SSC, and the on-enablement signal SGD is held off.

[0024] The short-circuit detection unit 50 uses an internal logic circuit to filter and mask the first voltage determination signal SCH using a time constant defined by a resistor R50 and a filter capacitor C50. If the voltage exceeds this time constant, the first voltage determination signal SCH is set and input to a flip-flop circuit 51, maintaining a short-circuit detection state. The flip-flop circuit 51 may be reset by a command from a microcomputer or the like, by a predetermined time constant, or by a time-limited flip-flop circuit 51 itself, such as a mono-multivibrator. During the delay period between when the on-off command signal SIN commands an off-to-on transition and when the on-enable signal SGD commands an off-to-on transition as determined by the first voltage determination unit 30, if the first voltage determination signal SCH maintains a high-level state for a period longer than the filter's time constant, a normal state may be erroneously detected as a short circuit. To prevent this, the short-circuit detection input signal SSS is logically combined with the on-enable signal SGD by a diode D50.

[0025] The gate driver 70A generates a buffer input signal GDD by logically combining the on-enable signal SGD and the short-circuit detection signal SSC using an internal logic circuit. The signal is level-shifted from the logic level to the level of the gate drive power supply VP by a level shift circuit 72A, and then the buffer circuit 71A amplifies the current to charge and discharge the gate. The charge and discharge time constant is adjusted by an on-gate resistor R70A and an off-gate resistor R71A. The configuration of the buffer circuit 71A and the method for adjusting the gate charge and discharge are not limited to this, and various configurations are possible, such as a buffer formed of bipolar transistors or a constant current drive circuit.

[0026] FIG. 3 shows an example of a time chart of signals in a normal state in specific example 1 of the drive device 10A for the reverse conducting semiconductor switching element 90 according to the first embodiment. During the period when the load current Im is negative, current flows through the diode D1 of the reverse conducting semiconductor switching element 90. According to the present disclosure, even if the on / off command signal SIN is at a high level during this period, the on-enablement signal SGD can indicate an off state. Furthermore, at time t3, the diode D1 is commutated from conduction to conduction through the IGBT_Z1. Since the on-enablement signal SGD is changed to the on state based on the first voltage determination signal SCH during the period when the IGBT_Z1 is off, appropriate control can be achieved at the timing required for the change from off to on. Conversely, at time t11, the reverse conducting semiconductor switching element 90 transitions from a state in which current flows through the IGBT_Z1 to a state in which current flows through the diode D1. However, because the on-enablement signal SGD was in the on state, the forward voltage of the diode increases, resulting in a large negative collector voltage Vce. This is detected by the second voltage determination unit 40, and at time t12, the on-enable signal SGD is changed to the off state.

[0027] The first reference voltage VrefH, which is the reference value of the first voltage determination unit 30, is preferably set higher than the second reference voltage VrefL, which is the reference value of the second voltage determination unit 40. FIG. 4 explains the reason for this, showing the collector voltage Vce and the second voltage determination signal SGC around time t12 when the current is commutated from IGBT_Z1 to diode D1. FIG. 4A shows waveforms when the first reference voltage VrefH and the second reference voltage VrefL are set equal. Note that the case where the first reference voltage VrefH is smaller than the second reference voltage VrefL is similar and will not be described here. At this time, if an increase in the forward voltage due to the operation of the parasitic n-channel MOSFET is detected at time t12 and the on-enable signal SGD is turned off, the forward voltage becomes small. Therefore, the on-enable signal SGD is again turned on by the determination of the first voltage determination unit 30, and the forward voltage becomes large again. The on-permission start signal SGS, the second voltage input signal SDD, the on-permission stop signal SGR, and the short circuit detection input signal SSS are as shown in the figure.

[0028] In this way, if the voltage Vce across the main terminals of the reverse conducting semiconductor switching element 90 is compared and determined using only a single reference voltage, for example, the method disclosed in Patent Document 2 has the drawback of potentially falling into an oscillation mode. On the other hand, in Figure 4B, by making the first reference voltage VrefH larger than the second reference voltage VrefL and making the difference between them larger than the difference in forward voltages generated when the gate is in an on / off state, it is possible to prevent oscillation of the on enable signal SGD.

[0029] 5 shows an example of a time chart of signals during a short circuit in specific example 1 of drive device 10A for reverse conducting semiconductor switching element 90 according to embodiment 1. When the upper and lower arms constituting the leg circuit are short-circuited at time t9, collector voltage Vce, i.e., first voltage input signal SDE, is maintained at a high level, causing first voltage determination signal SCH to go to a high level for a predetermined time. Accordingly, short-circuit detection signal SSC is generated, and on-enablement signal SGD is changed to an off state. The on-enablement start signal SGS, second voltage input signal SDD, on-enablement stop signal SGR, and short-circuit detection input signal SSS are as shown in the figure.

[0030] As described above, the drive device 10A for the reverse conducting semiconductor switching element 90 according to the first embodiment suppresses gate-on while the diode D1 of the reverse conducting semiconductor switching element 90 is conducting. Even if current during gate-on is commutated to the diode D1, an increase in the forward voltage of the diode D1 can be prevented. This also prevents breakdown due to a Type III short circuit that occurs during the gate-on period when the diode D1 is conducting. In particular, the first voltage determination unit 30 employs a general collector voltage detection (Desat) method, which is used to both change the on-enable signal to an ON state and detect a short circuit. This further reduces costs. Furthermore, because gate-on while the diode D1 is conducting can be suppressed to a very short time, e.g., several hundred nanoseconds, breakdown due to a Type III short circuit, which is a problem with reverse conducting IGBTs, can be reliably prevented. Therefore, a low-cost, highly versatile collector voltage detection method can be applied without the need for an expensive short-circuit detection circuit.

[0031] Second Embodiment. FIG. 6 is a block diagram showing the configuration of a drive device 10B for a reverse conducting semiconductor switching element 90 according to a second embodiment. The second embodiment differs from the first embodiment in that an on / off command signal SIN is input to a gate drive unit 70B. The gate drive unit 70B drives the gate terminal Gs based on the on / off command signal SIN in addition to the on enable signal SGD. The gate drive unit 70B can achieve a drive function for the gate terminal Gs to reduce switching loss by using the operation mode of the reverse conducting semiconductor switching element 90 obtained by comparing these signals. For example, FIG. 7 is a block diagram showing a first specific example of the drive device 10B for a reverse conducting semiconductor switching element. When the on enable signal SGD indicates an off state and the short circuit detection signal SSC does not detect a short circuit, and the on enable signal SGD transitions from the on state to the off state, i.e., when the conduction state of the diode D1 ends, a falling edge pulse generation circuit 76B receiving the on / off command signal SIN generates an on pulse of a predetermined width to turn on the gate for a predetermined period.

[0032] This activates the parasitic n-channel MOSFET of the reverse-conducting semiconductor switching element 90, reducing the internal stored carriers and thereby reducing the recovery current in the subsequent recovery operation, thereby reducing recovery loss. The width of this on-pulse is equal to or greater than the time required to reduce the stored carriers, and is short enough to ignore the effect of an increase in forward voltage on loss. To prevent a Type 3 short circuit, the dead time between the upper and lower arms of the leg circuit must be longer than the width of this on-pulse. Figure 8 shows an example time chart of each signal. At time t13, when the on-off command signal SIN commands OFF while diode D1 is conducting, an on-pulse of a predetermined width is output to the output signal of buffer 1B.

[0033] Third Embodiment. Figure 9 is a block diagram showing a configuration example of a driver 10C for a reverse conducting semiconductor switching element 90 according to a third embodiment. In comparison with the first embodiment, the third embodiment differs from the first embodiment in that the IGBT_Z1 to be driven is a double-gate semiconductor switching element having two gate terminals Gs1 and Gs2, and two gate drivers 70C1 and 70C2 are provided correspondingly. Figure 10 is a block diagram showing a specific example of the driver 10C for such a reverse conducting semiconductor switching element. The first gate driver 70C1 that drives the first gate terminal Gs1 has a falling edge delay circuit 75C1 on its input side, which delays the falling timing of the on-enable signal SGD. The second gate driver 70C2 that drives the second gate terminal Gs2 has a rising edge delay circuit 75C2 on its input side, which delays the rising timing of the on-enable signal SGD.

[0034] 11, the output voltage of buffer 71C1 has a delayed OFF timing relative to the output voltage of buffer 71C2 at times t5 and t8, and the output voltage of buffer 71C2 has a delayed ON timing relative to the output voltage of buffer 71C1 at times t4 and t7. By providing a time difference between the two gate voltages in this way, the double-gate semiconductor switching element can reduce turn-off loss and turn-on loss, and the third embodiment is configured to achieve this.

[0035] Fourth Embodiment. Figure 12 is a block diagram showing an example configuration of a driver 10D for a reverse conducting semiconductor switching element 90 according to a fourth embodiment. While the third embodiment uses a parallel configuration in which cells connected to each gate terminal independently form channels depending on the gate voltages of the double-gate semiconductor switching element, the fourth embodiment differs in that it uses a series split-gate configuration in which a channel is completed when both split gates are turned on. Compared to the driver 10C for a reverse conducting semiconductor switching element according to the third embodiment, the driver 10D for a reverse conducting semiconductor switching element according to the fourth embodiment is configured such that an on / off command signal SIN from a higher-level logic unit is input as an input signal to a first gate driver 70D1, which is one of the gate drivers, instead of an on-enable signal SGD. The second gate driver 70D2 has a configuration equivalent to that of the gate driver 70A according to the first embodiment.

[0036] 13 is a block diagram showing a specific example 1 of a driver 10D for a reverse-conducting semiconductor switching element 90 according to embodiment 4, which differs from embodiment 3 in that an on / off command signal SIN is input as is to a level shift circuit 72D1 of a first gate driver 70D1. As a result, in the time chart of each signal shown in FIG. 14, the on / off command signal SIN is reproduced as is in the buffer 71D1, but the output voltage of the buffer 71D1 is appropriately generated by a method based on a comparison of the main terminal voltage Vce with two reference voltages VrefH and VrefL according to the present disclosure, and therefore the effects of preventing an increase in forward voltage and breakdown due to a type 3 short circuit can also be achieved with such a series-type split-gate semiconductor switching element.

[0037] In the first to fourth embodiments, a drive device for a reverse conducting semiconductor switching element according to the present disclosure has been described. Hereinafter, power conversion devices such as an inverter, a boost converter, and a boost inverter combining these devices using such a drive device for a reverse conducting semiconductor switching element will be described with reference to FIGS. 15 to 17. Power conversion devices such as the inverter shown in FIG. 15, the boost converter shown in FIG. 16, and the boost inverter combining these devices shown in FIG. 17 are configured using one or more leg circuits 91 each consisting of an upper arm and a lower arm in which a plurality of reverse conducting semiconductor switching elements 90 are connected in series. The reverse conducting semiconductor switching element 90 is an example configuration of an IGBT module in which an IGBT and a diode are connected in anti-parallel, and current flows alternately through the IGBT or diode of the upper arm and the diode or IGBT of the lower arm depending on the direction of the load current.

[0038] Fifth Embodiment. Figure 15 is a diagram showing the configuration of an inverter power conversion device according to a fifth embodiment. The power conversion device 100A includes a power converter 101 having a plurality of reverse conducting semiconductor switching elements 90 and a reverse conducting semiconductor switching element driver 10X that drives each of the reverse conducting semiconductor switching elements 90 in the power converter 101. In this case, the power conversion device 100A is an inverter that converts DC power from a DC power supply 94 into AC power and supplies it to an AC motor 92. A reverse conducting semiconductor switching element driver 10A according to the first embodiment is provided for each reverse conducting semiconductor switching element 90, and a group of the individual reverse conducting semiconductor switching element drivers 10A constitutes the driver 10X of this embodiment. The power converter 101 has a three-phase (U, V, W) configuration and is an inverter circuit that includes a smoothing capacitor 93 between DC buses and leg circuits 91 for each phase. The leg circuit 91 of each phase is configured by connecting an upper arm and a lower arm in series, each arm including a reverse conducting semiconductor switching element 90 .

[0039] In this embodiment, each reverse conducting semiconductor switching element 90 in a power converter 101 is driven by a drive device 10X that includes a plurality of reverse conducting semiconductor switching element drive devices 10A according to embodiment 1. This prevents an increase in forward voltage due to gate-on while the diode is conducting, and prevents breakdown due to a type 3 short circuit, resulting in a low-loss, highly reliable power converter 100A. While the power converter 101 is shown as outputting two-level AC voltages (positive and negative), it may also be an inverter capable of outputting multilevel voltages in which any number of reverse conducting semiconductor switching elements 90 are connected in series and parallel. Even in this case, the power converter 101 is configured to include a leg circuit 91 in which upper and lower arms, each of which has a reverse conducting semiconductor switching element 90, are connected in series.

[0040] Sixth Embodiment. Figure 16 is a diagram showing the configuration of a power conversion device of a boost converter according to a sixth embodiment. The power conversion device 100B includes a power converter 102 having a plurality of reverse conducting semiconductor switching elements 90 and a reverse conducting semiconductor switching element driver 10X that drives each of the reverse conducting semiconductor switching elements 90 in the power converter 102. In this case, the power conversion device 100B operates as a boost converter that boosts the DC voltage of a DC power supply 94 and supplies the boosted DC voltage to a DC load 92A. As described above, the reverse conducting semiconductor switching element driver 10X is a collection of individual reverse conducting semiconductor switching element drivers 10A that drive each of the reverse conducting semiconductor switching elements 90. The power converter 102 includes an input-side smoothing capacitor 95, an output-side smoothing capacitor 97, a leg circuit 91, and a boost reactor 96. The leg circuit 91 is configured by connecting an upper arm and a lower arm in series, each arm having a reverse-conducting semiconductor switching element 90. In this case, too, a low-cost configuration can prevent an increase in forward voltage due to gate-on while the diode is conducting, and can prevent breakdown due to a type 3 short circuit, thereby providing a low-loss, highly reliable power conversion device 100B. Note that while a boost converter is shown in Figure 16, the present invention can also be applied to a buck converter or a buck-boost converter that combines a boost converter and a buck converter.

[0041] Seventh Embodiment. FIG. 17 illustrates the configuration of a boost inverter power conversion device that combines an inverter and a boost converter according to a seventh embodiment. The power conversion device 100C includes a main circuit (power converter) in which the power converter 102 shown in FIG. 16 is connected to the DC side of the power converter 101 shown in FIG. 15 , and a drive device 10X that drives a reverse-conducting semiconductor switching element 90. In this case, the power conversion device 100C boosts the DC voltage of a DC power supply 94 using the power converter 102, and the boosted DC power is converted to AC power by the power converter 101 and supplied to an AC motor 92. The power conversion device 100C operates as a boost inverter system and is applied, for example, to electric vehicles. Again, this configuration prevents an increase in forward voltage due to gate-on while the diode is conducting and prevents breakdown due to a type 3 short circuit, resulting in a low-loss and highly reliable power conversion device 100C.

[0042] The power converter 101 in the power conversion device 100C may be an inverter capable of multi-level voltage output. Furthermore, the power converter 102 in the power conversion device 100C is not limited to a boost converter, but may be a buck converter or a buck-boost converter that combines a boost converter and a buck converter. While the reverse conducting semiconductor switching element driver 10A according to the first embodiment is used as the reverse conducting semiconductor switching element driver 10X, the reverse conducting semiconductor switching element drivers 10B to 10D according to the second to fourth embodiments may also be applied, and similar effects can be obtained. In this case, the reverse conducting semiconductor switching element driver 10X is also a collection of the individual reverse conducting semiconductor switching element drivers 10B to 10D that drive the respective reverse conducting semiconductor switching elements 90.

[0043] In each embodiment, the reverse conducting semiconductor switching elements 90 are all described as reverse conducting IGBTs, but a wide band gap semiconductor material may be used for some of the reverse conducting semiconductor switching elements 90. In this case, the switching operation of the reverse conducting semiconductor switching elements 90 can be increased in speed and the boost reactor 96 can be made smaller. The wide band gap semiconductor material can be any of silicon carbide (SiC), gallium nitride, gallium oxide-based materials, and diamond.

[0044] Although the present disclosure describes various exemplary embodiments and specific examples, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless modifications not illustrated are contemplated within the scope of the technology disclosed in this application. For example, modifications of at least one component, additions, or omissions, as well as extraction of at least one component and combinations with components of other embodiments, are also contemplated.

[0045] 10A to 10D, 10X: drive device for reverse conducting semiconductor switching element, 20: voltage step-down unit, 30: first voltage determination unit, 40: second voltage determination unit, 50: short circuit detection unit, 60: on-permission signal generation unit, 70A, 70B: gate drive units, 70C1, 70D1: first gate drive unit, 70C2, 70D2: second gate drive unit, 90: reverse conducting semiconductor switching element, 91: leg circuit, 92: AC motor, 92A: DC load, 93, 95, 97: smoothing capacitor, 94: DC power supply, 96: step-up reactor, 100A to 100C: power conversion device, 101, 102: power converters. SIN: on / off command signal, SDE: first voltage input signal, SCH: first voltage determination signal, SGS: on permission start signal, SDD: second voltage input signal, SGC: second voltage determination signal, SGR: on permission stop signal, SSS: short circuit detection input signal, SSC: short circuit detection signal, SGD: on permission signal, GDD: buffer input signal.

Claims

1. A drive device for a reverse conducting semiconductor switching element, in which a semiconductor switching element having a first main terminal, a second main terminal, and a gate terminal and a rectifying element connected in anti-parallel to the semiconductor switching element are integrated, an on-enablement signal generating unit that receives an on-off command signal that turns on or off the reverse conducting semiconductor switching element and generates an on-enablement signal; a gate driver that receives the on-enable signal and generates a drive voltage to be applied to the gate terminal; a first voltage determination unit including a comparator that receives a main terminal voltage between the first main terminal and the second main terminal, and that compares the main terminal voltage with a first reference voltage; a second voltage determination unit including a comparator that receives the voltage between the main terminals and that compares the voltage between the main terminals with a second reference voltage that is different from the first reference voltage; the on-enablement signal generation unit sets the on-enablement signal to an on state when the voltage between the main terminals during a period in which the reverse conducting semiconductor switching element is off is greater than the first reference voltage, based on a logical combination of a first voltage determination signal from the first voltage determination unit and the on-off command signal, and a logical combination of a second voltage determination signal from the second voltage determination unit and the on-off command signal, and changes the on-enablement signal to an off state when the voltage between the main terminals during a period in which the reverse conducting semiconductor switching element is off is smaller than the second reference voltage.

2. the on-permission signal generation unit includes a state holding circuit, 2. The drive device for a reverse conducting semiconductor switching element according to claim 1, wherein, when the on-enablement signal is changed to an on state, the state-holding circuit holds the on-enablement signal in the on state until the on-enablement signal is changed to an off state or until the on-off command signal instructs off, and when the on-enablement signal is changed to an off state, the state-holding circuit holds the on-enablement signal in the off state until the on-enablement signal is changed to an on state.

3. 2. The drive device for a reverse conducting semiconductor switching element according to claim 1, wherein the first reference voltage of the first voltage determination unit is higher than the second reference voltage.

4. 2. The drive device for a reverse conducting semiconductor switching element according to claim 1, wherein the second reference voltage of the second voltage determination unit is zero or a negative value.

5. a short-circuit detection unit that receives the on-enablement signal and the first voltage determination signal from the first voltage determination unit, and determines a short-circuit state of the reverse conducting semiconductor switching element when the on-enablement signal is in an on state and the voltage between the main terminals is greater than the first reference voltage; 2. The drive device for a reverse conducting semiconductor switching element according to claim 1, wherein the on-enablement signal generation unit receives a detection signal from the short circuit detection unit and, if a short circuit in the reverse conducting semiconductor switching element is detected, changes the on-enablement signal to an off state.

6. 6. The drive device for a reverse conducting semiconductor switching element according to claim 5, wherein the short circuit detection unit includes a state holding circuit that holds a state in which a short circuit of the reverse conducting semiconductor switching element is detected for at least a predetermined period of time.

7. 6. The drive device for a reverse conducting semiconductor switching element according to claim 5, wherein the gate drive unit generates a drive voltage to be applied to the gate terminal by logically combining the detection signal from the short circuit detection unit and the on-enable signal.

8. 2. The drive device for a reverse conducting semiconductor switching element according to claim 1, wherein a voltage step-down unit is provided between the first and second voltage determination units and the first main terminal, and the voltage between the main terminals is reduced and applied to the first and second voltage determination units.

9. A drive device for a reverse conducting semiconductor switching element, which is integrated with a semiconductor switching element having a first main terminal, a second main terminal, and a gate terminal, and a rectifying element connected in anti-parallel to the semiconductor switching element, an on-enablement signal generating unit that receives an on-off command signal that turns on or off the reverse conducting semiconductor switching element and generates an on-enablement signal; a gate driver that receives the on-enable signal and the on-off command signal and generates a drive voltage to be applied to the gate terminal; a voltage determination unit that receives a main terminal voltage between the first main terminal and the second main terminal, and compares the main terminal voltage with a first reference voltage and a second reference voltage different from the first reference voltage, the on-enablement signal generation unit, by logical synthesis of the determination signal from the voltage determination unit and the on-off command signal, sets the on-enablement signal to an on state when the voltage between the main terminals during a period in which the reverse conducting semiconductor switching element is off is greater than the first reference voltage, and changes the on-enablement signal to an off state when the voltage between the main terminals during a period in which the reverse conducting semiconductor switching element is off is smaller than the second reference voltage; a gate driver that sets the on-enablement signal to an on-state for a first holding time when the on-enablement signal is in an off-state and the on-off command signal transitions from an on-state to an off-state.

10. 10. The drive device for a reverse conducting semiconductor switching element according to claim 1 or claim 9, wherein the reverse conducting semiconductor switching element is a multi-gate semiconductor switching element having at least one gate terminal including a first gate terminal and a second gate terminal different from the first gate terminal.

11. the gate driver receives the on-enable signal or the on-off command signal and generates a drive voltage to be applied to the first gate terminal; a second gate driver that receives the on-enable signal and generates a drive voltage to be applied to the second gate terminal; 11. The drive device for a reverse conducting semiconductor switching element according to claim 10, wherein the first and second gate drivers respectively apply drive voltages to the first and second gate terminals at different timings.

12. 12. The drive device for a reverse conducting semiconductor switching element according to claim 11, wherein the first gate drive unit includes a delay circuit that delays the OFF timing of the ON enable signal, and the second gate drive unit includes a delay circuit that delays the ON timing of the ON enable signal.

13. a reverse conducting semiconductor switching element integrated with a semiconductor switching element having a first main terminal, a second main terminal, and a gate terminal, and a rectifying element connected in anti-parallel to the semiconductor switching element; at least one leg circuit in which an upper arm and a lower arm each having the reverse conducting semiconductor switching element are connected in series; a reverse conducting semiconductor switching element drive device provided for each of the reverse conducting semiconductor switching elements of the upper arm and the lower arm; A power conversion device comprising: The drive device for the reverse conducting semiconductor switching element includes: an ON / OFF command signal generating unit that receives an ON / OFF command signal for turning on or off the reverse conducting semiconductor switching element and generates an ON / OFF enable signal; a gate driver that receives the on-enable signal and generates a drive voltage to be applied to the gate terminal; the on-enablement signal generation unit sets the on-enablement signal to an on state when a main terminal voltage between the first main terminal and the second main terminal during a period in which the reverse conducting semiconductor switching element is off is greater than a first reference voltage, and changes the on-enablement signal to an off state when the main terminal voltage is smaller than a second reference voltage different from the first reference voltage, a dead time provided between the on / off command signal for the upper arm and the on / off command signal for the lower arm is set to be longer than a predetermined time, the dead time being a first hold time for holding the on permission signal in an on state when the on / off command signal is in an off state and the on / off command signal transitions from an on state to an off state.

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