Electronic component

Abstract

This electronic component comprises: an object to be coated; an electrode disposed on the object to be coated and having an electrode side wall on the object to be coated; a wire disposed around the electrode on the object to be coated; an insulating inorganic film having an inner covering part covering the electrode so as to expose the electrode side wall, and an outer covering part covering the wire at an interval from the inner covering part; and an insulating organic film spanning both the inner covering part and the outer covering part, and covering the electrode between the inner covering part and the outer covering part.

Description

Electronic Components

[0001] This application claims priority to Patent Application No. 2023-091948 filed with the Japan Patent Office on June 2, 2023, the entire contents of which are incorporated herein by reference. The present disclosure relates to electronic components.

[0002] Patent Document 1 (US2019 / 0080976A1) discloses a semiconductor device including a semiconductor substrate, an interlayer insulating layer, an electrode, an inorganic protective layer, and an organic protective layer. The interlayer insulating layer is formed on the semiconductor substrate and has an opening that exposes the semiconductor substrate. The electrode extends into the opening from above the interlayer insulating layer and is electrically connected to the semiconductor substrate within the opening. The inorganic protective layer covers the edge of the electrode. The organic protective layer covers the electrode and the interlayer insulating layer with the inorganic protective layer sandwiched therebetween.

[0003] US Patent Application Publication No. 2019-0080976

[0004] SUMMARY The present disclosure provides an electronic component having a novel layout.

[0005] The present disclosure provides an electronic component including: an object to be covered; an electrode disposed on the object to be covered and having an electrode sidewall on the object to be covered; wiring disposed around the electrode on the object to be covered; an insulating inorganic film having an inner covering portion that covers the electrode so as to expose the electrode sidewall, and an outer covering portion that covers the wiring at a distance from the inner covering portion; and an insulating organic film that spans the inner covering portion and the outer covering portion and covers the electrode between the inner covering portion and the outer covering portion.

[0006] The present disclosure provides an electronic component including a terminal electrode, wiring arranged around the terminal electrode, an insulating inorganic film covering the wiring at a distance from the terminal electrode, and an insulating organic film having a portion that directly covers the electrode and a portion that covers the wiring with the inorganic film sandwiched between them.

[0007] The present disclosure provides an electronic component including an electrode disposed in a first region having a first electric field, wiring disposed in a second region around the electrode having a second electric field higher than the first electric field, an insulating inorganic film exposing the electrode and covering the wiring, and an insulating organic film having a portion directly covering the electrode and a portion covering the wiring with the inorganic film sandwiched therebetween.

[0008] The present disclosure provides an electronic component including: a chip having a main surface; an active region provided in an inner portion of the main surface; a peripheral region provided on a periphery of the main surface; a device structure formed on the main surface in the active region; an impurity region formed on a surface layer portion of the main surface in the peripheral region; an electrode disposed on the main surface in the active region and electrically connected to the device structure; wiring disposed on the main surface in the peripheral region and electrically connected to the impurity region; an insulating inorganic film exposing the electrode and covering the wiring; and an insulating organic film having a portion directly covering the electrode and a portion covering the wiring with the inorganic film sandwiched therebetween.

[0009] The present disclosure provides an electronic component including: an object to be covered; a gate electrode disposed on the object to be covered and having electrode sidewalls on the object to be covered; gate wiring disposed around the gate electrode on the object to be covered; an insulating inorganic film having an inner covering portion that covers the gate electrode so as to expose the electrode sidewalls, and an outer covering portion that covers the gate wiring at a distance from the inner covering portion; and an insulating organic film that spans the inner covering portion and the outer covering portion and covers the gate electrode between the inner covering portion and the outer covering portion.

[0010] The present disclosure provides an electronic component including: an object to be covered; a source electrode disposed on the object to be covered and having an electrode sidewall on the object to be covered; a gate wiring disposed around the source electrode on the object to be covered; an insulating inorganic film having an inner covering portion that covers the source electrode so as to expose the electrode sidewall, and an outer covering portion that covers the gate wiring at a distance from the inner covering portion; and an insulating organic film that spans the inner covering portion and the outer covering portion and covers the source electrode between the inner covering portion and the outer covering portion.

[0011] The present disclosure provides an electronic component including: an object to be covered; a gate electrode disposed on the object to be covered and having electrode sidewalls on the object to be covered; a source wiring disposed around the gate electrode on the object to be covered; an insulating inorganic film having an inner coating portion that covers the gate electrode so as to expose the electrode sidewalls, and an outer coating portion that covers the source wiring at a distance from the inner coating portion; and an insulating organic film that spans the inner coating portion and the outer coating portion and covers the gate electrode between the inner coating portion and the outer coating portion.

[0012] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0013] FIG. 1 is a plan view showing a semiconductor device. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1 . FIG. 4 is a plan view showing an example layout of a first main surface. FIG. 5 is an enlarged plan view showing a main portion of an active region. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5 . FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5 . FIG. 8 is an enlarged plan view showing a main portion of a first side end region. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 8 . FIG. 10 is a cross-sectional view taken along line XX in FIG. 8 . FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 8 . FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 8 . FIG. 13 is an enlarged plan view showing a main portion of a first termination region. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 13 . FIG. 15 is an enlarged plan view showing a main portion of a third termination region. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 15 . FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 1 . FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 1 . FIG. 19 is a plan view showing an example layout of the main electrode. FIG. 20 is a plan view showing a first example layout of the second inorganic film. FIG. 21 is an enlarged plan view showing a main portion of the second inorganic film. FIG. 22A is a cross-sectional view showing a second example layout of the second inorganic film. FIG. 22B is a cross-sectional view showing a third example layout of the second inorganic film. FIG. 22C is a cross-sectional view showing a fourth example layout of the second inorganic film. FIG. 22D is a cross-sectional view showing a fifth example layout of the second inorganic film. FIG. 22E is a cross-sectional view showing a sixth example layout of the second inorganic film. FIG. 22F is an enlarged plan view showing a seventh example layout of the second inorganic film. FIG. 22G is an enlarged plan view showing an eighth example layout of the second inorganic film. Fig. 22H is an enlarged plan view showing a ninth layout example of the second inorganic film. Fig. 22I is an enlarged plan view showing a tenth layout example of the second inorganic film. Fig. 22J is an enlarged plan view showing an eleventh layout example of the second inorganic film. Fig. 22K is an enlarged plan view showing a twelfth layout example of the second inorganic film. Fig. 22L is a cross-sectional view showing a thirteenth layout example of the second inorganic film. Fig. 22M is a cross-sectional view showing a fourteenth layout example of the second inorganic film. Fig. 22N is a cross-sectional view showing a fifteenth layout example of the second inorganic film.Fig. 22O is a cross-sectional view showing a sixteenth layout example of the second inorganic film, Fig. 22P is a cross-sectional view showing a seventeenth layout example of the second inorganic film, Fig. 22Q is a cross-sectional view showing an eighteenth layout example of the second inorganic film, and Fig. 22R is a cross-sectional view showing a nineteenth layout example of the second inorganic film.

[0014] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0015] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0016] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0017] FIG. 1 is a plan view showing a semiconductor device 1 (electronic component). FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1. FIG. 4 is a plan view showing an example layout of a first main surface 3. The semiconductor device 1 is a semiconductor switching device including an insulated gate transistor structure Tr. The transistor structure Tr may be referred to as a MISFET structure (Metal Insulator Semiconductor Field Effect Transistor structure).

[0018] 1 to 4, in this embodiment, semiconductor device 1 includes chip 2 that includes a single crystal of a wide bandgap semiconductor and is formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In other words, semiconductor device 1 is a "wide bandgap semiconductor device." Chip 2 may also be called a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0019] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "SiC semiconductor device."

[0020] The semiconductor device 1 may be referred to as a "SiC-MISFET." Hexagonal SiC single crystal has a variety of polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, and 6H-SiC single crystal. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0021] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0022] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0023] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0024] In this embodiment, the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal, and the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal. Of course, the first direction X may be the m-axis direction of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Hereinafter, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0025] The first main surface 3 and the second main surface 4 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane. The off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle may be greater than 0° and not more than 10°. The off angle is preferably not more than 5°.

[0026] The chip 2 (first main surface 3 and second main surface 4) has an off-axis angle inclined at a predetermined angle in a predetermined off-axis direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical line toward the off-axis direction by the off-axis angle. The c-plane of the SiC single crystal is also inclined with respect to the horizontal plane by the off-axis angle.

[0027] The off-direction is preferably the a-axis direction of the SiC single crystal (i.e., the first direction X). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0028] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0029] The semiconductor device 1 includes an n-type first semiconductor region 6 formed in a surface layer portion of the second main surface 4 of the chip 2. A drain potential is applied to the first semiconductor region 6 as a first potential (high potential). The first semiconductor region 6 may also be referred to as a "semiconductor layer," a "first semiconductor layer," a "drain region," or the like. The first semiconductor region 6 is formed in a layer shape extending along the second main surface 4 and is exposed from the second main surface 4 of the chip 2 and first to fourth side surfaces 5A to 5D of the chip 2.

[0030] In this embodiment, the first semiconductor region 6 is made of an n-type semiconductor layer. Specifically, the first semiconductor region 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal), and forms the second main surface 4 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2. The first semiconductor region 6 (substrate) has the off direction and off angle described above.

[0031] The first semiconductor region 6 may have a thickness of 10 μm or more and 500 μm or less. The thickness of the first semiconductor region 6 may have a value belonging to at least one of the ranges of 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0032] The semiconductor device 1 includes an n-type second semiconductor region 7 formed in a surface layer portion of the first main surface 3 of the chip 2. The second semiconductor region 7 may also be referred to as a "semiconductor layer," a "second semiconductor layer," a "drift region," or the like. The second semiconductor region 7 has an n-type impurity concentration that is lower than the n-type impurity concentration of the first semiconductor region 6.

[0033] The second semiconductor region 7 is formed in a layer shape extending along the first main surface 3 and is electrically connected to the first semiconductor region 6. The second semiconductor region 7 is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D of the chip 2. In this embodiment, the second semiconductor region 7 is made of an n-type semiconductor layer.

[0034] In this embodiment, the second semiconductor region 7 is made of an n-type semiconductor layer. Specifically, the second semiconductor region 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal), and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D of the chip 2. The second semiconductor region 7 (epitaxial layer) has the off direction and off angle described above.

[0035] The second semiconductor region 7 preferably has a thickness less than that of the first semiconductor region 6. Of course, the thickness of the second semiconductor region 7 may be greater than the thickness of the first semiconductor region 6. The thickness of the second semiconductor region 7 may be 5 μm or more and 50 μm or less.

[0036] The thickness of the second semiconductor region 7 may have a value belonging to at least one of the ranges of 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 35 μm, 35 μm to 40 μm, 40 μm to 45 μm, and 45 μm to 50 μm.

[0037] The semiconductor device 1 includes a first surface 8, a second surface 9, and first to fourth connection surface portions 10A to 10D formed on the first main surface 3. The first surface 8, the second surface 9, and the first to fourth connection surface portions 10A to 10D define a mesa 11 on the first main surface 3. The first surface 8, the second surface 9, and the first to fourth connection surface portions 10A to 10D (i.e., mesa 11) may be considered to be components of the chip 2 (first main surface 3).

[0038] The first surface portion 8 may be referred to as the "active surface," the second surface portion 9 may be referred to as the "outer surface," the first to fourth connecting surface portions 10A to 10D may be referred to as "connecting surfaces," and the mesa 11 may be referred to as the "active mesa."

[0039] The first surface portion 8 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The first surface portion 8 has a flat surface extending horizontally and is formed by a c-plane (Si-plane). In this embodiment, the first surface portion 8 is formed in a polygonal shape (specifically, a quadrilateral shape) having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view. The planar area of ​​the first surface portion 8 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0040] The second surface 9 is located closer to the periphery of the first main surface 3 than the first surface 8, and is recessed in the thickness direction of the chip 2 (toward the second main surface 4) from the height position of the first surface 8. The second surface 9 extends in a strip shape along the first surface 8 in a plan view, and is formed in a ring shape (specifically, a quadrangular ring) surrounding the first surface 8. The second surface 9 is continuous with the first to fourth side surfaces 5A to 5D.

[0041] The second surface 9 is formed substantially parallel to the first surface 8 and has a flat surface extending horizontally. In this embodiment, the second surface 9 is formed by the c-plane (Si-plane). The second surface 9 is formed in the second semiconductor region 7 at a distance from the first semiconductor region 6. In other words, the second surface 9 is recessed to a depth less than the thickness of the second semiconductor region 7, exposing the second semiconductor region 7.

[0042] The second surface portion 9 has a depth of 0.1 μm or more and 3 μm or less. The depth of the second surface portion 9 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the second surface portion 9 is preferably 1.5 μm or more and 2.5 μm or less.

[0043] The first to fourth connection surface portions 10A to 10D extend in the vertical direction Z and are connected to the first surface portion 8 and the second surface portion 9. The first connection surface portion 10A is located on the first side surface 5A side, the second connection surface portion 10B is located on the second side surface 5B side, the third connection surface portion 10C is located on the third side surface 5C side, and the fourth connection surface portion 10D is located on the fourth side surface 5D side. The first connection surface portion 10A and the second connection surface portion 10B extend in the first direction X and face the second direction Y. The third connection surface portion 10C and the fourth connection surface portion 10D extend in the second direction Y and face the first direction X.

[0044] In this way, the mesa 11 is defined in a protruding (convex) shape on the first main surface 3. The mesa 11 is formed only in the second semiconductor region 7, and not in the first semiconductor region 6. The first to fourth connection surface portions 10A to 10D may extend substantially perpendicularly between the first surface portion 8 and the second surface portion 9, and define the mesa 11 in the shape of a quadrangular pillar.

[0045] The first to fourth connection surface portions 10A to 10D may be inclined obliquely downward from the first surface portion 8 toward the second surface portion 9, and may define a mesa 11 having a truncated quadrangular pyramid shape. The first to fourth connection surface portions 10A to 10D may be inclined with respect to the first surface portion 8 at an angle greater than 90° and equal to or less than 135°.

[0046] Referring to FIG. 3 , the semiconductor device 1 includes an active region 12, a first side end region 13, a second side end region 14, a first termination region 15, a second termination region 16, a third termination region 17, a fourth termination region 18 and a peripheral region 19 on the first main surface 3.

[0047] The active region 12 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 12 is set in the inner portion of the first surface portion 8. Specifically, the active region 12 is provided in the inner portion of the first surface portion 8 at a distance from the periphery of the first surface portion 8 (the first to fourth connection surface portions 10A to 10D). In this embodiment, the active region 12 is provided in a polygonal shape (specifically, a quadrilateral shape) having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0048] The proportion of the active region 12 in the first surface portion 8 is preferably 50% or more and 95% or less. The proportion of the active region 12 may be in any one of the ranges of 50% or more and 60% or more, 60% or more and 70% or less, 70% or more and 80% or less, 80% or more and 90% or less, and 90% or more and 95% or less. The proportion of the active region 12 is preferably 70% or more.

[0049] The first side end region 13 is provided on one side of the active region 12 in the first direction X (the third connection surface portion 10C side) on the first surface portion 8, and faces the active region 12 in the first direction X. In this embodiment, the first side end region 13 extends in a strip shape in the second direction Y in a plan view.

[0050] The second side end region 14 is provided on the first surface 8 on the other side in the first direction X (the fourth connection surface 10D side) of the active region 12, and faces the first side end region 13 across the active region 12 in the first direction X. In this embodiment, the second side end region 14 extends in a strip shape in the second direction Y in a plan view.

[0051] The first termination region 15 is provided on one side (the first connection surface portion 10A side) of the active region 12 in the second direction Y, and faces the active region 12 in the second direction Y. In this embodiment, the first termination region 15 extends in the first direction X in a plan view, and faces the first side end region 13 and the second side end region 14 in the second direction Y.

[0052] The second termination region 16 is provided on the other side in the second direction Y (the second connection surface portion 10B side) of the active region 12, and faces the first termination region 15 across the active region 12 in the second direction Y. In this embodiment, the second termination region 16 extends in the first direction X in plan view, and faces the first side end region 13 and the second side end region 14 across the active region 12 in the second direction Y.

[0053] The third termination region 17 is provided on one side in the second direction Y (the side of the first connection surface portion 10A) of the first termination region 15, and faces the active region 12 in the second direction Y, with the first termination region 15 sandwiched between them. The third termination region 17 is provided in a region between the periphery of the first surface portion 8 and the first termination region 15. In this embodiment, the third termination region 17 extends in a strip shape in the first direction X in a plan view, and faces the first side end region 13 and the second side end region 14, with the first termination region 15 sandwiched between them.

[0054] The fourth termination region 18 is provided on the other side in the second direction Y (the second connection surface portion 10B side) of the second termination region 16, and faces the active region 12 across the second termination region 16 in the second direction Y. The fourth termination region 18 is provided in a region between the periphery of the first surface portion 8 and the third termination region 17. In this embodiment, the fourth termination region 18 extends in a strip shape in the first direction X in a plan view, and faces the first side end region 13 and the second side end region 14 across the second termination region 16.

[0055] The peripheral region 19 is provided as an inactive region on the second surface portion 9. In this embodiment, the peripheral region 19 is provided in a ring shape (specifically, a rectangular ring shape) surrounding the first surface portion 8 (mesa 11) in a plan view. That is, the peripheral region 19 surrounds the active region 12, the first side end region 13, the second side end region 14, the first termination region 15, the second termination region 16, the third termination region 17, and the fourth termination region 18 in a plan view.

[0056] The configuration of the active region 12 will be described below. Fig. 5 is an enlarged plan view showing a main part of the active region 12. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 5. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 5.

[0057] 5 to 7, the semiconductor device 1 includes a p-type body region 20 formed in a surface layer portion of the first surface portion 8 (first main surface 3) in the active region 12. The body region 20 may also be referred to as a "channel region," a "base region," or the like. A source potential is applied to the body region 20 as a second potential (low potential) different from a first potential (high potential). The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be ground potential or a potential other than ground potential.

[0058] The body region 20 is formed at a distance from the bottom of the second semiconductor region 7 toward the first surface portion 8, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. The body region 20 is formed at a distance from the depth position of the second surface portion 9 toward the first surface portion 8.

[0059] The body region 20 is formed in a layer shape extending along the first surface portion 8. In this embodiment, the body region 20 is formed over the entire first surface portion 8 and is exposed from the first to fourth connecting surface portions 10A to 10D. Of course, the body region 20 may also be formed at a distance inward from the periphery of the first surface portion 8.

[0060] The semiconductor device 1 includes an n-type source region 21 (impurity region) formed in a surface layer portion of the first surface portion 8 (first main surface 3) in the active region 12. A source potential is applied to the source region 21. The source region 21 has an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7.

[0061] The source region 21 is formed in a surface layer portion of the body region 20. Specifically, the source region 21 is formed at a distance from the bottom of the body region 20 toward the first surface portion 8. In other words, the source region 21 is formed in a region on the first surface portion 8 side of the body region 20. The source region 21 forms a channel of a transistor together with the second semiconductor region 7 in the body region 20.

[0062] In this embodiment, the source region 21 is formed at a distance inward from the periphery of the first surface portion 8. Therefore, the source region 21 is not exposed from the first to fourth connection surface portions 10A to 10D. In this embodiment, the source region 21 is formed only in the active region 12, and not in any region other than the active region 12.

[0063] Of course, to the extent that it does not affect the electrical characteristics, source region 21 may be formed in at least one of first side end region 13, second side end region 14, first termination region 15, second termination region 16, third termination region 17, and fourth termination region 18. Of course, source region 21 may be formed on the entire surface of first surface 8 and exposed from first to fourth connection surface portions 10A to 10D.

[0064] The semiconductor device 1 includes a plurality of trench-type (trench electrode-type) gate structures 25 formed in the first surface portion 8 (first main surface 3) in the active region 12. The gate structures 25 may also be referred to as "trench structures" or "trench gate structures." A gate potential is applied to the plurality of gate structures 25 as a control potential. The plurality of gate structures 25 control inversion and non-inversion of the channel in the body region 20 in response to the gate potential.

[0065] The plurality of gate structures 25 are arranged on the first surface 8 at intervals inward from the periphery of the first surface 8 (first to fourth connection surface portions 10A to 10D), and define the active region 12 in the inner part of the first surface 8. In other words, the plurality of gate structures 25 are formed only in the active region 12, and are not formed in the first side end region 13, the second side end region 14, the first termination region 15, the second termination region 16, the third termination region 17, or the fourth termination region 18.

[0066] The plurality of gate structures 25 extend in a strip shape in the first direction X in a plan view, and are arranged at intervals in the second direction Y. In other words, the plurality of gate structures 25 are arranged in a stripe shape extending in the first direction X in a plan view.

[0067] The plurality of gate structures 25 penetrate the body region 20 and the source region 21 to reach the second semiconductor region 7. That is, the body region 20 and the source region 21 are located on both sides of the plurality of gate structures 25, respectively.

[0068] The plurality of gate structures 25 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a part of the second semiconductor region 7. In this embodiment, the plurality of gate structures 25 are formed substantially perpendicular to the first surface portion 8. Of course, the plurality of gate structures 25 may also be formed in a tapered shape toward the bottom of the second semiconductor region 7.

[0069] The sidewalls of the plurality of gate structures 25 are each formed by the m-plane ((1-100) plane) of the SiC single crystal. Of course, the sidewalls of the plurality of gate structures 25 may each be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the gate structures 25. The sidewalls of the plurality of gate structures 25 are formed approximately perpendicular to the first main surface 3.

[0070] The bottom walls of the gate structures 25 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the gate structures 25 preferably extend substantially flat in the horizontal direction. Of course, the bottom walls of the gate structures 25 may be curved in an arc shape toward the second main surface 4.

[0071] The inclination angle (absolute value) of the sidewall of the gate structure 25 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0072] The gate structure 25 may have a width of 0.1 μm to 3 μm. The width of the gate structure 25 may have a value belonging to at least one of the ranges of 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm. The width of the gate structure 25 is preferably 0.5 μm to 2 μm.

[0073] The gate structure 25 preferably has a depth less than the depth of the second surface portion 9. Of course, the depth of the gate structure 25 may be approximately equal to the depth of the second surface portion 9, or may be greater than the depth of the second surface portion 9.

[0074] The depth of the gate structure 25 may be 0.1 μm or more and 3 μm or less. The depth of the gate structure 25 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the gate structure 25 is preferably 0.5 μm or more and 1.5 μm or less.

[0075] The following describes the configuration of one gate structure 25. The gate structure 25 includes a first trench 26, a first insulating film 27, and a first buried electrode 28. The first trench 26 is formed in the first surface portion 8 and defines the wall surfaces (sidewalls and bottom wall) of the gate structure 25.

[0076] The first insulating film 27 covers the wall surface of the first trench 26. The first insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first insulating film 27 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first insulating film 27 include a silicon oxide film made of an oxide of the chip 2.

[0077] The first insulating film 27 includes a first film portion and a second film portion. The first film portion coats the sidewall of the first trench 26 in a film-like manner. The second film portion coats the bottom wall of the first trench 26 in a film-like manner and is continuous with the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion.

[0078] The first insulating film 27 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0079] The first buried electrode 28 is buried in the first trench 26 with a first insulating film 27 sandwiched therebetween. The first buried electrode 28 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both. The first buried electrode 28 faces the channel with the first insulating film 27 sandwiched therebetween. In other words, the first buried electrode 28 faces the second semiconductor region 7, the body region 20, and the source region 21 with the first insulating film 27 sandwiched therebetween.

[0080] The first buried electrode 28 has an electrode surface exposed from the first trench 26. The electrode surface of the first buried electrode 28 is located closer to the bottom wall of the first trench 26 with respect to the height position of the first surface portion 8. The electrode surface of the first buried electrode 28 is located closer to the first main surface 3 with respect to the depth position of the bottom of the body region 20. The electrode surface of the first buried electrode 28 has a recess in an inner portion that tapers toward the bottom wall of the first trench 26.

[0081] The semiconductor device 1 includes a plurality of trench-type (trench electrode-type) first source structures 30 formed on the first main surface 3 (first surface portion 8) in the active region 12. The first source structures 30 may be referred to as "trench structures," "trench source structures," "first trench source structures," or the like. A source potential is applied to the plurality of first source structures 30.

[0082] The multiple first source structures 30 are formed in the first surface portion 8 so as to be adjacent to the multiple gate structures 25 in the second direction Y in the active region 12. Specifically, the multiple first source structures 30 are respectively arranged in regions between the multiple gate structures 25 and face the multiple gate structures 25 in the second direction Y. In other words, the multiple first source structures 30 are arranged alternately with the multiple gate structures 25 in the second direction Y.

[0083] The multiple first source structures 30 each extend in a strip shape in the first direction X in a plan view. In this embodiment, the multiple first source structures 30 are drawn out from the active region 12 to either or both of the first side end region 13 and the second side end region 14 (in this embodiment, both). The multiple first source structures 30 face the gate structure 25 in the second direction Y in the active region 12, but do not face the gate structure 25 in the second direction Y in the first side end region 13 (second side end region 14).

[0084] The plurality of first source structures 30 are exposed from at least one of the third connection surface portion 10C and the fourth connection surface portion 10D. In this embodiment, the plurality of first source structures 30 penetrate both the third connection surface portion 10C and the fourth connection surface portion 10D and are exposed from both the third connection surface portion 10C and the fourth connection surface portion 10D.

[0085] The plurality of first source structures 30 penetrate the body region 20 and the source region 21 to reach the second semiconductor region 7. That is, the body region 20 and the source region 21 are located on both sides of the plurality of first source structures 30, respectively.

[0086] The plurality of first source structures 30 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a part of the second semiconductor region 7. In this embodiment, the plurality of first source structures 30 are formed substantially perpendicular to the first surface portion 8. Of course, the plurality of first source structures 30 may be formed in a tapered shape toward the bottom of the second semiconductor region 7.

[0087] The sidewalls of the plurality of first source structures 30 are each formed by an m-plane of the SiC single crystal. Of course, the sidewalls of the plurality of first source structures 30 may each be formed by an a-plane of the SiC single crystal depending on the extension direction of the first source structures 30. The sidewalls of the plurality of first source structures 30 are formed approximately perpendicular to the first main surface 3.

[0088] The bottom walls of the first source structures 30 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the first source structures 30 preferably extend substantially flat in the horizontal direction. Of course, the bottom walls of the first source structures 30 may be curved in an arc shape toward the second main surface 4.

[0089] The inclination angle (absolute value) of the sidewall of the first source structure 30 relative to the vertical line may be 85° to 95°. The inclination angle may have a value belonging to at least one of the ranges of 85° to 87.5°, 87.5° to 90°, 90° to 92.5°, and 92.5° to 95°. The inclination angle is preferably 87° to 93°.

[0090] The first source structure 30 preferably has a width greater than the width of the gate structure 25. Of course, the width of the first source structure 30 may be approximately equal to the width of the gate structure 25 or may be less than the width of the gate structure 25.

[0091] The width of the first source structure 30 may be 0.1 μm or more and 3 μm or less. The width of the first source structure 30 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The width of the first source structure 30 is preferably 0.5 μm or more and 2 μm or less.

[0092] The first source structure 30 preferably has a depth greater than the depth of the gate structure 25. Of course, the depth of the first source structure 30 may be approximately equal to the depth of the gate structure 25 or may be less than the depth of the gate structure 25. The depth of the first source structure 30 is preferably approximately equal to the depth of the second surface portion 9. Of course, the depth of the first source structure 30 may be less than the depth of the second surface portion 9 or may be greater than the depth of the second surface portion 9.

[0093] The ratio (depth ratio) of the depth of the first source structure 30 to the depth of the gate structure 25 is preferably 1 to 3. The depth ratio may have a value belonging to at least one of the following ranges: 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 2.5. The depth ratio is preferably 1.5 to 2.5.

[0094] The depth of the first source structure 30 may be 0.1 μm or more and 3 μm or less. The depth of the first source structure 30 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the first source structure 30 is preferably 1.5 μm or more and 2.5 μm or less.

[0095] The configuration of one first source structure 30 will be described below. The first source structure 30 includes a second trench 31, a second insulating film 32, and a second buried electrode 33. The second trench 31 is formed in the first surface portion 8 and defines the wall surfaces (sidewalls and bottom wall) of the first source structure 30. The sidewalls of the second trench 31 are connected to either or both (in this embodiment, both) of the third connection surface portion 10C and the fourth connection surface portion 10D. The bottom wall of the second trench 31 is connected to the second surface portion 9.

[0096] The second insulating film 32 covers the wall surface of the second trench 31. The second insulating film 32 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second insulating film 32 preferably includes the same type of insulating material as the insulating material of the first insulating film 27. In this embodiment, the second insulating film 32 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second insulating film 32 includes a silicon oxide film made of an oxide of the chip 2.

[0097] The second insulating film 32 includes a first film portion and a second film portion. The first film portion coats the sidewall of the second trench 31 in a film-like manner. The second film portion coats the bottom wall of the second trench 31 in a film-like manner and is continuous with the first film portion.

[0098] The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion. The thickness of the first film portion of the second insulating film 32 may be approximately equal to the thickness of the first film portion of the first insulating film 27. The thickness of the second film portion of the second insulating film 32 may be approximately equal to the thickness of the second film portion of the first insulating film 27.

[0099] The second insulating film 32 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0100] The second buried electrode 33 is buried in the second trench 31 with the second insulating film 32 sandwiched therebetween. The second buried electrode 33 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. The second buried electrode 33 preferably contains the same type of conductive material as the conductive material of the first buried electrode 28. The second buried electrode 33 faces the second semiconductor region 7, the body region 20, and the source region 21 with the second insulating film 32 sandwiched therebetween.

[0101] The second buried electrode 33 has an electrode surface exposed from the second trench 31. The electrode surface of the second buried electrode 33 is located closer to the bottom wall of the second trench 31 with respect to the height position of the first surface portion 8. The electrode surface of the second buried electrode 33 is located closer to the second main surface 4 with respect to the depth position of the bottom of the body region 20. The electrode surface of the second buried electrode 33 has a recess in an inner portion that tapers toward the bottom wall of the second trench 31.

[0102] The semiconductor device 1 includes a plurality of p-type first well regions 35 formed in regions along the plurality of gate structures 25 in a surface layer portion of the first surface portion 8 (first main surface 3) of the active region 12. The first well regions 35 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20. Of course, the p-type impurity concentration of the first well regions 35 may be lower than the p-type impurity concentration of the body region 20.

[0103] The plurality of first well regions 35 are formed in one-to-one correspondence with the plurality of gate structures 25. The plurality of first well regions 35 are formed in regions along the corresponding gate structures 25 at intervals from the plurality of first source structures 30.

[0104] The plurality of first well regions 35 are formed along the sidewalls and bottom walls of the corresponding gate structures 25, and are each electrically connected to the body region 20 in a surface layer portion of the first surface portion 8. The plurality of first well regions 35 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 with a part of the second semiconductor region 7 in between. The plurality of first well regions 35 form pn junctions with the second semiconductor region 7.

[0105] The semiconductor device 1 includes a plurality of p-type second well regions 36 formed in regions along the plurality of first source structures 30 in a surface layer portion of the first surface portion 8 (first main surface 3) of the active region 12. The second well regions 36 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20. Of course, the p-type impurity concentration of the second well regions 36 may be lower than the p-type impurity concentration of the body region 20. It is preferable that the p-type impurity concentration of the second well regions 36 be approximately equal to the p-type impurity concentration of the first well region 35.

[0106] The second well regions 36 are formed in one-to-one correspondence with the first source structures 30. The second well regions 36 are formed in regions along the corresponding first source structures 30, spaced apart from the gate structures 25.

[0107] The second well regions 36 are formed along the sidewalls and bottom walls of the corresponding first source structures 30, and are electrically connected to the body regions 20 in the surface layer portion of the first surface portion 8. The second well regions 36 extend along the wall surfaces of the corresponding first source structures 30 in the active region 12, the first side end region 13, and the second side end region 14, and are exposed from the third connection surface portion 10C and the fourth connection surface portion 10D.

[0108] The second well regions 36 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a part of the second semiconductor region 7. The bottoms of the second well regions 36 are located closer to the bottom of the second semiconductor region 7 than the depth positions of the bottoms of the first well regions 35. The second well regions 36 form pn junctions with the second semiconductor region 7.

[0109] The semiconductor device 1 includes a plurality of p-type contact regions 37 formed in regions along the plurality of first well regions 35 in a surface layer portion of the first surface portion 8 (first main surface 3) of the active region 12. The contact regions 37 may also be referred to as "back gate regions." The contact regions 37 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20. The p-type impurity concentration of the contact regions 37 is higher than the p-type impurity concentration of the first well region 35 (second well region 36).

[0110] The plurality of contact regions 37 are formed in the plurality of second well regions 36. The plurality of contact regions 37 extend along the wall surfaces of the corresponding first source structures 30 in the corresponding second well regions 36. The plurality of contact regions 37 are formed in a one-to-many correspondence with the corresponding first source structures 30.

[0111] The plurality of contact regions 37 are formed at intervals in the first direction X along the corresponding first source structures 30. The plurality of contact regions 37 are drawn out to the surface layer portion of the body region 20 along the wall surfaces of the corresponding first source structures 30 in the corresponding second well regions 36, and are exposed from the first surface portion 8.

[0112] In this embodiment, the multiple contact regions 37 each extend in a strip shape in the first direction X in a plan view. The length of the multiple contact regions 37 in the first direction X is preferably equal to or greater than the width of the first source structure 30 in the second direction Y. The length of the multiple contact regions 37 is preferably greater than the distance between two adjacent contact regions 37 in the first direction X.

[0113] The plurality of contact regions 37 along one first source structure 30 face the plurality of contact regions 37 along other first source structures 30 in the second direction Y. That is, in this embodiment, the plurality of contact regions 37 are arranged in a matrix form at intervals in the first direction X and the second direction Y as a whole in a plan view.

[0114] The plurality of contact regions 37 along one first source structure 30 may be arranged offset in the first direction X so as to face the regions between the plurality of contact regions 37 along other first source structures 30 in the second direction Y. In other words, the plurality of contact regions 37 may be arranged in a staggered pattern as a whole in a plan view with intervals in the first direction X and the second direction Y.

[0115] The configuration of the first side end region 13 will be described below. Fig. 8 is an enlarged plan view showing a main portion of the first side end region 13. Fig. 9 is a cross-sectional view taken along line IX-IX in Fig. 8. Fig. 10 is a cross-sectional view taken along line XX in Fig. 8. Fig. 11 is a cross-sectional view taken along line XI-XI in Fig. 8. Fig. 12 is a cross-sectional view taken along line XII-XII in Fig. 8.

[0116] The layout of the second side edge region 14 is similar to that of the first side edge region 13, and therefore a description of the layout of the second side edge region 14 will be omitted. The layout of the second side edge region 14 can be obtained by replacing "first side edge region 13" with "second side edge region 14" and "third connecting surface portion 10C" with "fourth connecting surface portion 10D" in the description of the first side edge region 13.

[0117] 8 to 12, semiconductor device 1 includes a plurality of trench-type (trench electrode-type) second source structures 40 formed in first surface portion 8 (first main surface 3) in first side end region 13. A source potential is applied to the plurality of second source structures 40. Second source structures 40 may also be referred to as "trench structures," "source-side end structures," "trench source structures," "second trench source structures," or the like.

[0118] The second source structures 40 are respectively arranged in regions on the periphery of the first surface portion 8 (third connection surface portion 10C) and between the gate structures 25. The second source structures 40 are respectively arranged in regions between the first source structures 30 and face the first source structures 30 in the second direction Y. In other words, the second source structures 40 and the first source structures 30 are alternately arranged in the second direction Y.

[0119] The second source structures 40 face the gate structures 25 in a one-to-one correspondence in the first direction X, and together with the gate structures 25, define a plurality of side mesa portions. The side mesa portions are arranged in a line in the second direction Y. Of course, the side mesa portions may be arranged offset from one another in one and the other of the first direction X so as not to be adjacent to and face other side mesa portions in the second direction Y.

[0120] The multiple second source structures 40 each extend in a strip shape in the first direction X in a plan view. In this embodiment, the multiple second source structures 40 penetrate the third connection surface portion 10C and are exposed from the third connection surface portion 10C. The multiple second source structures 40 penetrate the body region 20 to reach the second semiconductor region 7. The multiple second source structures 40 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 with a part of the second semiconductor region 7 in between.

[0121] In this embodiment, the plurality of second source structures 40 are formed substantially perpendicular to the first surface portion 8. Of course, the plurality of second source structures 40 may be formed in a tapered shape toward the bottom of the second semiconductor region 7.

[0122] The sidewalls of the second source structures 40 are each formed by an m-plane of the SiC single crystal. Of course, the sidewalls of the second source structures 40 may each be formed by an a-plane of the SiC single crystal depending on the extension direction of the second source structures 40. The sidewalls of the second source structures 40 are formed approximately perpendicular to the first main surface 3.

[0123] The bottom walls of the second source structures 40 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the second source structures 40 preferably extend substantially flat in the horizontal direction. Of course, the bottom walls of the second source structures 40 may be curved in an arc shape toward the second main surface 4.

[0124] The inclination angle (absolute value) of the sidewall of the second source structure 40 relative to the vertical line may be 85° to 95°. The inclination angle may have a value belonging to at least one of the ranges of 85° to 87.5°, 87.5° to 90°, 90° to 92.5°, and 92.5° to 95°. The inclination angle is preferably 87° to 93°.

[0125] The second source structure 40 preferably has a width greater than the width of the gate structure 25. Of course, the width of the second source structure 40 may be approximately equal to the width of the gate structure 25 or may be less than the width of the gate structure 25. The width of the second source structure 40 is preferably approximately equal to the width of the first source structure 30.

[0126] The width of the second source structure 40 may be 0.1 μm or more and 3 μm or less. The width of the second source structure 40 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The width of the second source structure 40 is preferably 0.5 μm or more and 2 μm or less.

[0127] The second source structure 40 preferably has a depth greater than the depth of the gate structure 25. Of course, the depth of the second source structure 40 may be approximately equal to the depth of the gate structure 25 or may be less than the depth of the gate structure 25.

[0128] The depth of the second source structure 40 is preferably approximately equal to the depth of the second surface portion 9. Of course, the depth of the second source structure 40 may be less than the depth of the second surface portion 9 or may be greater than the depth of the second surface portion 9. The depth of the plurality of second source structures 40 is preferably approximately equal to the depth of the plurality of first source structures 30.

[0129] The ratio (depth ratio) of the depth of the second source structure 40 to the depth of the gate structure 25 is preferably 1 to 3. The depth ratio may have a value belonging to at least one of the following ranges: 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 2.5. The depth ratio is preferably 1.5 to 2.5.

[0130] The depth of the second source structure 40 may be 0.1 μm or more and 3 μm or less. The depth of the second source structure 40 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the second source structure 40 is preferably 1.5 μm or more and 2.5 μm or less.

[0131] The second source structures 40 are arranged at first intervals from the gate structures 25 in the first direction X. The first intervals are preferably 0.5 to 2 times the width of the second source structures 40.

[0132] The plurality of second source structures 40 are arranged at a second spacing in the second direction Y from the plurality of source structures. The second spacing may be approximately equal to the first spacing. The second spacing may be greater than or less than the first spacing. The second spacing is preferably greater than or equal to 0.5 times and less than or equal to 2 times the width of the second source structures 40.

[0133] The first interval (second interval) may be 0.1 μm or more and 3 μm or less. The first interval (second interval) may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The first interval (second interval) is preferably 0.5 μm or more and 2 μm or less.

[0134] The configuration of one second source structure 40 will be described below. The second source structure 40 includes a third trench 41, a third insulating film 42, and a third buried electrode 43. The third trench 41 is formed in the first surface portion 8 and defines the wall surfaces (sidewalls and bottom wall) of the second source structure 40. The sidewalls of the third trench 41 are connected to the third connection surface portion 10C. The bottom wall of the third trench 41 is connected to the second surface portion 9.

[0135] The third insulating film 42 covers the wall surface of the third trench 41. The third insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The third insulating film 42 preferably includes the same insulating material as the insulating material of the first insulating film 27 (second insulating film 32). In this embodiment, the third insulating film 42 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the third insulating film 42 include a silicon oxide film made of an oxide of the chip 2.

[0136] The third insulating film 42 includes a first film portion and a second film portion. The first film portion coats the sidewall of the third trench 41 in a film-like manner. The second film portion coats the bottom wall of the third trench 41 in a film-like manner and is continuous with the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion. The thickness of the first film portion of the third insulating film 42 may be approximately equal to the thickness of the first film portion of the first insulating film 27. The thickness of the second film portion of the third insulating film 42 may be approximately equal to the thickness of the second film portion of the first insulating film 27.

[0137] The third insulating film 42 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0138] The third buried electrode 43 is buried in the third trench 41 with the third insulating film 42 sandwiched therebetween. The third buried electrode 43 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both. The third buried electrode 43 preferably includes the same type of conductive material as the conductive material of the first buried electrode 28 (second buried electrode 33). The third buried electrode 43 faces the second semiconductor region 7 and the body region 20 with the third insulating film 42 sandwiched therebetween.

[0139] The third buried electrode 43 has an electrode surface exposed from the third trench 41. The electrode surface of the third buried electrode 43 is located closer to the bottom wall of the third trench 41 with respect to the height position of the first surface portion 8. The electrode surface of the third buried electrode 43 is located closer to the second main surface 4 with respect to the depth position of the bottom of the body region 20. The electrode surface of the third buried electrode 43 has a recess in an inner portion that tapers toward the bottom wall of the third trench 41.

[0140] The semiconductor device 1 includes a plurality of p-type third well regions 44 formed in a region along the plurality of second source structures 40 in a surface layer portion of the first surface portion 8 (first main surface 3) of the first side end region 13. The third well regions 44 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20. Of course, the p-type impurity concentration of the third well regions 44 may be lower than the p-type impurity concentration of the body region 20. It is preferable that the p-type impurity concentration of the third well regions 44 be approximately equal to the p-type impurity concentration of the first well region 35 (second well region 36).

[0141] The plurality of third well regions 44 are formed in a one-to-one correspondence with the plurality of second source structures 40. The plurality of third well regions 44 are formed in regions along the corresponding second source structures 40, spaced apart from the plurality of first well regions 35 and the plurality of second well regions 36. Of course, the plurality of third well regions 44 may be formed integrally with the plurality of first well regions 35. The plurality of third well regions 44 may be formed integrally with the plurality of second well regions 36.

[0142] The plurality of third well regions 44 are formed along the sidewalls and bottom wall of the corresponding second source structures 40, and are electrically connected to the body region 20 in the surface layer portion of the first surface portion 8. The plurality of third well regions 44 are exposed from the third connection surface portion 10C.

[0143] The plurality of third well regions 44 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a part of the second semiconductor region 7. The bottoms of the plurality of third well regions 44 are located closer to the bottom of the second semiconductor region 7 than the depth positions of the bottoms of the plurality of first well regions 35. The bottoms of the plurality of third well regions 44 are formed at depth positions approximately equal to the bottoms of the plurality of second well regions 36. The plurality of third well regions 44 form pn junctions with the second semiconductor region 7.

[0144] The following describes the configuration of first termination region 15. Figure 13 is an enlarged plan view showing a main part of first termination region 15. Figure 14 is a cross-sectional view taken along line XIV-XIV shown in Figure 13.

[0145] The layout of the second termination region 16 is similar to that of the first termination region 15, and therefore a description of the layout of the second termination region 16 will be omitted. The layout of the second termination region 16 can be obtained by replacing "first termination region 15" with "second termination region 16" and "first connection surface portion 10A" with "second connection surface portion 10B" in the description of the first termination region 15.

[0146] The semiconductor device 1 includes a plurality of trench-type (trench electrode-type) dummy gate structures 50 formed in the first surface portion 8 (first main surface 3) in the first termination region 15. The dummy gate structures 50 may also be referred to as "trench structures," "trench termination structures," "gate termination structures," "dummy trench structures," or "dummy trench gate structures." A source potential is applied to the plurality of dummy gate structures 50. In other words, the plurality of dummy gate structures 50 do not contribute to inversion or non-inversion of the channel.

[0147] The multiple dummy gate structures 50 are formed in a region on the first connection surface portion 10A side of the active region 12. The multiple dummy gate structures 50 each extend in a strip shape in the first direction X in a plan view, and are arranged at intervals in the second direction Y. That is, the multiple dummy gate structures 50 are arranged in a stripe shape extending in the first direction X in a plan view. The multiple dummy gate structures 50 face the multiple gate structures 25 and the multiple first source structures 30 in the second direction Y.

[0148] In this embodiment, the multiple dummy gate structures 50 are extended in the second direction Y to a region facing either one or both (in this embodiment, both) of the first side end region 13 and the second side end region 14, and face the multiple second source structures 40 in the second direction Y.

[0149] The plurality of dummy gate structures 50 are exposed from at least one of the third connection surface portion 10C and the fourth connection surface portion 10D. In this embodiment, the plurality of dummy gate structures 50 penetrate both the third connection surface portion 10C and the fourth connection surface portion 10D and are exposed from both the third connection surface portion 10C and the fourth connection surface portion 10D.

[0150] The plurality of dummy gate structures 50 penetrate the body region 20 to reach the second semiconductor region 7. The plurality of dummy gate structures 50 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 with a part of the second semiconductor region 7 in between. In this embodiment, the plurality of dummy gate structures 50 are formed substantially perpendicular to the first surface portion 8. Of course, the plurality of dummy gate structures 50 may be formed in a tapered shape toward the bottom of the second semiconductor region 7.

[0151] The sidewalls of the plurality of dummy gate structures 50 are each formed by an m-plane of the SiC single crystal. Of course, the sidewalls of the plurality of dummy gate structures 50 may each be formed by an a-plane of the SiC single crystal depending on the extension direction of the dummy gate structures 50. The sidewalls of the plurality of dummy gate structures 50 are formed approximately perpendicular to the first main surface 3.

[0152] The bottom walls of the plurality of dummy gate structures 50 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the plurality of dummy gate structures 50 preferably extend substantially flat in the horizontal direction. Of course, the bottom walls of the plurality of dummy gate structures 50 may be curved in an arc shape toward the second main surface 4.

[0153] The inclination angle (absolute value) of the sidewall of the dummy gate structure 50 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0154] The dummy gate structure 50 preferably has a width approximately equal to that of the gate structure 25. Of course, the width of the dummy gate structure 50 may be greater than or less than that of the gate structure 25. The width of the dummy gate structure 50 is preferably less than the width of the first source structure 30 (second source structure 40). Of course, the dummy gate structure 50 may be approximately equal to or greater than the width of the first source structure 30 (second source structure 40).

[0155] The width of the dummy gate structure 50 may be 0.1 μm or more and 3 μm or less. The width of the dummy gate structure 50 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The width of the dummy gate structure 50 is preferably 0.5 μm or more and 2 μm or less.

[0156] The depth of the dummy gate structure 50 is preferably less than the depth of the second surface portion 9. Of course, the depth of the dummy gate structure 50 may be approximately equal to the depth of the second surface portion 9, or may be greater than the depth of the second surface portion 9. The dummy gate structure 50 preferably has a depth approximately equal to the depth of the gate structure 25. Of course, the depth of the dummy gate structure 50 may be greater than the depth of the gate structure 25, or may be less than the depth of the gate structure 25.

[0157] The depth of the dummy gate structure 50 is preferably less than the depth of the first source structure 30 (second source structure 40). Of course, the depth of the dummy gate structure 50 may be approximately equal to the depth of the first source structure 30 (second source structure 40), or may be greater than the depth of the first source structure 30 (second source structure 40).

[0158] The depth of the dummy gate structure 50 may be 0.1 μm or more and 3 μm or less. The depth of the dummy gate structure 50 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the dummy gate structure 50 is preferably 1.5 μm or more and 2.5 μm or less.

[0159] The following describes the configuration of one dummy gate structure 50. The dummy gate structure 50 includes a fourth trench 51, a fourth insulating film 52, and a fourth buried electrode 53. The fourth trench 51 is formed in the first surface portion 8, and defines the wall surfaces (sidewalls and bottom wall) of the dummy gate structure 50.

[0160] The fourth insulating film 52 covers the wall surface of the fourth trench 51. The fourth insulating film 52 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The fourth insulating film 52 preferably includes the same insulating material as the insulating material of the first insulating film 27 (second insulating film 32). In this embodiment, the fourth insulating film 52 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the fourth insulating film 52 includes a silicon oxide film made of an oxide of the chip 2.

[0161] The fourth insulating film 52 includes a first film portion and a second film portion. The first film portion coats the sidewall of the fourth trench 51 in a film-like manner. The second film portion coats the bottom wall of the fourth trench 51 in a film-like manner and is continuous with the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion. The thickness of the first film portion of the fourth insulating film 52 may be approximately equal to the thickness of the first film portion of the first insulating film 27. The thickness of the second film portion of the fourth insulating film 52 may be approximately equal to the thickness of the second film portion of the first insulating film 27.

[0162] The fourth insulating film 52 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, or 125 nm to 150 nm.

[0163] The fourth buried electrode 53 is buried in the fourth trench 51 with the fourth insulating film 52 sandwiched therebetween. The fourth buried electrode 53 may contain either p-type conductive polysilicon or n-type conductive polysilicon, or both. The fourth buried electrode 53 preferably contains the same type of conductive material as the conductive material of the first buried electrode 28 (second buried electrode 33). The fourth buried electrode 53 faces the second semiconductor region 7 and the body region 20 with the fourth insulating film 52 sandwiched therebetween.

[0164] The fourth buried electrode 53 has an electrode surface exposed from the fourth trench 51. The electrode surface of the fourth buried electrode 53 is located closer to the bottom wall of the fourth trench 51 with respect to the height position of the first surface portion 8. The electrode surface of the fourth buried electrode 53 is located closer to the first main surface 3 with respect to the depth position of the bottom of the body region 20. The electrode surface of the fourth buried electrode 53 has a recess in an inner portion that tapers toward the bottom wall of the fourth trench 51.

[0165] The semiconductor device 1 includes a plurality of trench-type (trench electrode-type) third source structures 55 formed in the first surface portion 8 (first main surface 3) in the first termination region 15. A source potential is applied to the plurality of third source structures 55. The third source structures 55 may also be referred to as "trench structures," "source termination structures," "trench source structures," "third trench source structures," or the like.

[0166] The plurality of third source structures 55 are formed in a region on the first connection surface portion 10A side of the active region 12. The plurality of third source structures 55 are formed in the first surface portion 8 so as to be adjacent to the plurality of dummy gate structures 50 in the second direction Y in the first termination region 15. Specifically, the plurality of third source structures 55 are respectively arranged in regions between the plurality of dummy gate structures 50 and face the plurality of dummy gate structures 50 in the second direction Y.

[0167] That is, the multiple third source structures 55 are arranged alternately with the multiple dummy gate structures 50 in the second direction Y. The multiple third source structures 55 each extend in a strip shape in the first direction X in a plan view. The multiple third source structures 55 face the multiple gate structures 25 and the multiple first source structures 30 in the second direction Y.

[0168] In this embodiment, the plurality of third source structures 55 are drawn out to a region facing either one or both (in this embodiment, both) of the first side end region 13 and the second side end region 14 in the second direction Y, and face the plurality of second source structures 40 in the second direction Y. In this embodiment, the plurality of third source structures 55 face the plurality of second source structures 40 in the second direction Y, with the plurality of dummy gate structures 50 sandwiched therebetween.

[0169] The plurality of third source structures 55 are exposed from at least one of the third connection surface portion 10C and the fourth connection surface portion 10D. In this embodiment, the plurality of third source structures 55 penetrate both the third connection surface portion 10C and the fourth connection surface portion 10D and are exposed from both the third connection surface portion 10C and the fourth connection surface portion 10D.

[0170] The plurality of third source structures 55 penetrate the body region 20 to reach the second semiconductor region 7. The plurality of third source structures 55 are formed at intervals from the bottom of the second semiconductor region 7 toward the first face portion 8, and face the first semiconductor region 6 with a part of the second semiconductor region 7 in between. In this embodiment, the plurality of third source structures 55 are formed substantially perpendicular to the first face portion 8. Of course, the plurality of third source structures 55 may be formed in a tapered shape toward the bottom of the second semiconductor region 7.

[0171] The sidewalls of the plurality of third source structures 55 are each formed by an m-plane of the SiC single crystal. Of course, the sidewalls of the plurality of third source structures 55 may each be formed by an a-plane of the SiC single crystal depending on the extension direction of the third source structures 55. The sidewalls of the plurality of third source structures 55 are formed approximately perpendicular to the first main surface 3.

[0172] The bottom walls of the third source structures 55 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the third source structures 55 preferably extend substantially flat in the horizontal direction. Of course, the bottom walls of the third source structures 55 may be curved in an arc shape toward the second main surface 4.

[0173] The inclination angle (absolute value) of the sidewall of the third source structure 55 relative to the vertical line may be 85° to 95°. The inclination angle may have a value belonging to at least one of the ranges of 85° to 87.5°, 87.5° to 90°, 90° to 92.5°, and 92.5° to 95°. The inclination angle is preferably 87° to 93°.

[0174] The third source structure 55 preferably has a width greater than that of the dummy gate structure 50. Of course, the width of the third source structure 55 may be approximately equal to or less than that of the dummy gate structure 50. The width of the third source structure 55 is preferably approximately equal to the width of the first source structure 30 (second source structure 40). Of course, the width of the third source structure 55 may be greater than or less than that of the first source structure 30 (second source structure 40).

[0175] The width of the third source structure 55 may be 0.1 μm or more and 3 μm or less. The width of the third source structure 55 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The width of the third source structure 55 is preferably 0.5 μm or more and 2 μm or less.

[0176] The third source structure 55 preferably has a depth greater than the depth of the dummy gate structure 50 (gate structure 25). Of course, the depth of the third source structure 55 may be approximately equal to the depth of the dummy gate structure 50 (gate structure 25), or may be less than the depth of the dummy gate structure 50 (gate structure 25).

[0177] The depth of the third source structure 55 is preferably approximately equal to the depth of the first source structure 30 (second source structure 40). Of course, the depth of the third source structure 55 may be less than the depth of the first source structure 30 (second source structure 40) or may be greater than the depth of the first source structure 30 (second source structure 40). The depth of the third source structure 55 is preferably approximately equal to the depth of the second surface portion 9. Of course, the depth of the third source structure 55 may be less than the depth of the second surface portion 9 or may be greater than the depth of the second surface portion 9.

[0178] The ratio of the depth of the third source structure 55 to the depth of the gate structure 25 (dummy gate structure 50) is preferably 1 to 3. The depth ratio may have a value belonging to at least one of the ranges of 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 2.5. The depth ratio is preferably 1.5 to 2.5.

[0179] The depth of the third source structure 55 may be 0.1 μm or more and 3 μm or less. The depth of the third source structure 55 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the third source structure 55 is preferably 1.5 μm or more and 2.5 μm or less.

[0180] The configuration of one third source structure 55 will be described below. The third source structure 55 includes a fifth trench 56, a fifth insulating film 57, and a fifth buried electrode 58. The fifth trench 56 is formed in the first surface portion 8 and defines the wall surfaces (sidewalls and bottom wall) of the third source structure 55. The sidewalls of the fifth trench 56 are connected to either or both (in this embodiment, both) of the third connection surface portion 10C and the fourth connection surface portion 10D. The bottom wall of the fifth trench 56 is connected to the second surface portion 9.

[0181] The fifth insulating film 57 covers the wall surface of the fifth trench 56. The fifth insulating film 57 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The fifth insulating film 57 preferably includes the same insulating material as the insulating material of the first insulating film 27 (second insulating film 32). In this embodiment, the fifth insulating film 57 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the fifth insulating film 57 includes a silicon oxide film made of an oxide of the chip 2.

[0182] The fifth insulating film 57 includes a first film portion and a second film portion. The first film portion coats the sidewall of the fifth trench 56 in a film-like manner. The second film portion coats the bottom wall of the fifth trench 56 in a film-like manner and is continuous with the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion. The thickness of the first film portion of the fifth insulating film 57 may be approximately equal to the thickness of the first film portion of the first insulating film 27. The thickness of the second film portion of the fifth insulating film 57 may be approximately equal to the thickness of the second film portion of the first insulating film 27.

[0183] The fifth insulating film 57 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0184] The fifth buried electrode 58 is buried in the fifth trench 56 with a fifth insulating film 57 sandwiched therebetween. The fifth buried electrode 58 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both. The fifth buried electrode 58 preferably includes the same type of conductive material as the conductive material of the first buried electrode 28 (second buried electrode 33). The fifth buried electrode 58 faces the second semiconductor region 7 and the body region 20 with the fifth insulating film 57 sandwiched therebetween.

[0185] The fifth buried electrode 58 has an electrode surface exposed from the fifth trench 56. The electrode surface of the fifth buried electrode 58 is located on the bottom wall side of the fifth trench 56 with respect to the height position of the first surface portion 8. The electrode surface of the fifth buried electrode 58 is located on the second main surface 4 with respect to the depth position of the bottom of the body region 20. The electrode surface of the fifth buried electrode 58 has a recess in an inner portion that tapers toward the bottom wall side of the fifth trench 56.

[0186] The semiconductor device 1 includes a plurality of p-type fourth well regions 59 formed in regions along the plurality of dummy gate structures 50 in a surface layer portion of the first surface portion 8 (first main surface 3) of the first termination region 15. The fourth well regions 59 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20. Of course, the p-type impurity concentration of the fourth well regions 59 may be lower than the p-type impurity concentration of the body region 20. It is preferable that the p-type impurity concentration of the fourth well regions 59 be approximately equal to the p-type impurity concentration of the first well region 35 (second well region 36).

[0187] The plurality of fourth well regions 59 are formed in a one-to-one correspondence with the plurality of dummy gate structures 50. The plurality of fourth well regions 59 are formed in regions along the corresponding dummy gate structures 50 at intervals from the plurality of third source structures 55. The plurality of fourth well regions 59 are formed along the sidewalls and bottom walls of the corresponding dummy gate structures 50, and are each electrically connected to the body region 20 in the surface layer portion of the first surface portion 8.

[0188] The plurality of fourth well regions 59 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a portion of the second semiconductor region 7. The bottoms of the plurality of fourth well regions 59 are located on the first surface portion 8 side relative to the depth positions of the bottoms of the plurality of second well regions 36. In this embodiment, the plurality of fourth well regions 59 are exposed from either or both (in this embodiment, both) of the third connecting surface portion 10C and the fourth connecting surface portion 10D. The plurality of fourth well regions 59 form pn junctions with the second semiconductor region 7.

[0189] The semiconductor device 1 includes a plurality of p-type fifth well regions 60 formed in a region along the plurality of third source structures 55 in a surface layer portion of the first surface portion 8 (first main surface 3) of the first termination region 15. The fifth well regions 60 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20. Of course, the p-type impurity concentration of the fifth well regions 60 may be lower than the p-type impurity concentration of the body region 20. It is preferable that the p-type impurity concentration of the fifth well regions 60 is approximately equal to the p-type impurity concentration of the first well region 35 (second well region 36).

[0190] The plurality of fifth well regions 60 are formed in one-to-one correspondence with the plurality of third source structures 55. The plurality of fifth well regions 60 are formed in regions along the corresponding third source structures 55 at intervals from the plurality of dummy gate structures 50. The plurality of fifth well regions 60 are formed along the sidewalls and bottom walls of the corresponding third source structures 55, and are each electrically connected to the body region 20 in the surface layer portion of the first surface portion 8.

[0191] The plurality of fifth well regions 60 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a part of the second semiconductor region 7. The bottoms of the plurality of fifth well regions 60 are located closer to the bottom of the second semiconductor region 7 than the depth positions of the bottoms of the plurality of fourth well regions 59.

[0192] The bottoms of the plurality of fifth well regions 60 are formed at a depth substantially equal to that of the bottoms of the plurality of second well regions 36. In this embodiment, the plurality of fifth well regions 60 are exposed from either or both (in this embodiment, both) of the third connecting surface portion 10C and the fourth connecting surface portion 10D. The plurality of fifth well regions 60 form pn junctions with the second semiconductor region 7.

[0193] The following describes the configuration of third termination region 17. Figure 15 is an enlarged plan view showing a main part of third termination region 17. Figure 16 is a cross-sectional view taken along line XVI-XVI shown in Figure 15.

[0194] The layout of fourth termination region 18 is similar to that of third termination region 17, and therefore a description of the layout of fourth termination region 18 will be omitted. The layout of fourth termination region 18 can be obtained by replacing "third termination region 17" with "fourth termination region 18", "first termination region 15" with "second termination region 16", and "first connection surface portion 10A" with "second connection surface portion 10B" in the description of third termination region 17.

[0195] The semiconductor device 1 includes a plurality of trench-type (trench electrode-type) fourth source structures 65 formed in the first surface portion 8 (first main surface 3) in the third termination region 17. A source potential is applied to the plurality of fourth source structures 65. The fourth source structures 65 may also be referred to as "trench structures," "source termination structures," "trench source structures," "fourth trench source structures," or the like.

[0196] The multiple fourth source structures 65 are formed in a region on the first connection surface portion 10A side with respect to the active region 12 (first termination region 15). The multiple fourth source structures 65 each extend in a strip shape in the first direction X in a plan view, and are arranged at intervals in the second direction Y. In other words, the multiple fourth source structures 65 are arranged in a stripe shape extending in the first direction X in a plan view. The multiple fourth source structures 65 are adjacent to each other without any trench structure in between.

[0197] The multiple fourth source structures 65 face the active region 12 (the multiple gate structures 25 and the multiple first source structures 30) across the first termination region 15 (the multiple dummy gate structures 50 and the multiple third source structures 55) in the second direction Y.

[0198] In this embodiment, the plurality of fourth source structures 65 are drawn out to a region facing either one or both (in this embodiment, both) of the first side end region 13 and the second side end region 14 in the second direction Y, and face the plurality of second source structures 40 in the second direction Y. In this embodiment, the plurality of fourth source structures 65 face the plurality of second source structures 40 with the first termination region 15 (the plurality of dummy gate structures 50 and the plurality of third source structures 55) interposed therebetween.

[0199] The plurality of fourth source structures 65 are exposed from at least one of the third connection surface portion 10C and the fourth connection surface portion 10D. In this embodiment, the plurality of fourth source structures 65 penetrate both the third connection surface portion 10C and the fourth connection surface portion 10D and are exposed from both the third connection surface portion 10C and the fourth connection surface portion 10D.

[0200] The plurality of fourth source structures 65 penetrate the body region 20 to reach the second semiconductor region 7. The plurality of fourth source structures 65 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 with a part of the second semiconductor region 7 in between. In this embodiment, the plurality of fourth source structures 65 are formed substantially perpendicular to the first surface portion 8. Of course, the plurality of fourth source structures 65 may be formed in a tapered shape toward the bottom of the second semiconductor region 7.

[0201] The sidewalls of the plurality of fourth source structures 65 are each formed by an m-plane of the SiC single crystal. Of course, the sidewalls of the plurality of fourth source structures 65 may each be formed by an a-plane of the SiC single crystal depending on the extension direction of the fourth source structures 65. The sidewalls of the plurality of fourth source structures 65 are formed approximately perpendicular to the first main surface 3.

[0202] The bottom walls of the fourth source structures 65 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the fourth source structures 65 preferably extend substantially flat in the horizontal direction. Of course, the bottom walls of the fourth source structures 65 may be curved in an arc shape toward the second main surface 4.

[0203] The inclination angle (absolute value) of the sidewall of the fourth source structure 65 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0204] The fourth source structure 65 preferably has a width greater than that of the gate structure 25. Of course, the width of the fourth source structure 65 may be approximately equal to or less than that of the gate structure 25. The width of the fourth source structure 65 is preferably approximately equal to the width of the first source structure 30 (second source structure 40). Of course, the width of the fourth source structure 65 may be greater than or less than that of the first source structure 30 (second source structure 40).

[0205] The width of the fourth source structure 65 may be 0.1 μm or more and 3 μm or less. The width of the fourth source structure 65 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The width of the fourth source structure 65 is preferably 0.5 μm or more and 2 μm or less.

[0206] The fourth source structure 65 preferably has a depth greater than the depth of the gate structure 25. Of course, the depth of the fourth source structure 65 may be approximately equal to the depth of the gate structure 25 or may be less than the depth of the gate structure 25.

[0207] The depth of the fourth source structure 65 is preferably approximately equal to the depth of the first source structure 30 (second source structure 40). Of course, the depth of the fourth source structure 65 may be less than the depth of the first source structure 30 (second source structure 40) or may be greater than the depth of the first source structure 30 (second source structure 40). The depth of the fourth source structure 65 is preferably approximately equal to the depth of the second surface portion 9. Of course, the depth of the fourth source structure 65 may be less than the depth of the second surface portion 9 or may be greater than the depth of the second surface portion 9.

[0208] The ratio (depth ratio) of the depth of the fourth source structure 65 to the depth of the gate structure 25 (dummy gate structure 50) is preferably 1 or more and 3 or less. The depth ratio may have a value belonging to at least one of the ranges of 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, 2.25 or more and 2.5 or less, 2.5 or more and 2.75 or less, and 2.75 or more and 2.5 or less. The depth ratio is preferably 1.5 or more and 2.5 or less.

[0209] The depth of the fourth source structure 65 may be 0.1 μm or more and 3 μm or less. The depth of the fourth source structure 65 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the fourth source structure 65 is preferably 1.5 μm or more and 2.5 μm or less.

[0210] The ratio (spacing ratio) of the spacing between the plurality of fourth source structures 65 to the spacing between the gate structure 25 and the first source structure 30 is preferably 0.5 or more and 2 or less. The spacing ratio may have a value belonging to at least one of the ranges of 0.5 or more and 0.75 or less, 0.75 or more and 1 or less, 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, and 1.75 or more and 2 or less. The spacing ratio is preferably 0.75 or more and 1.25 or less.

[0211] The configuration of one fourth source structure 65 will be described below. The fourth source structure 65 includes a sixth trench 66, a sixth insulating film 67, and a sixth buried electrode 68. The sixth trench 66 is formed in the first surface portion 8 and defines the wall surfaces (sidewalls and bottom wall) of the fourth source structure 65. The sidewalls of the sixth trench 66 are connected to either or both (both in this embodiment) of the third connection surface portion 10C and the fourth connection surface portion 10D. The bottom wall of the sixth trench 66 is connected to the second surface portion 9.

[0212] The sixth insulating film 67 covers the wall surface of the sixth trench 66. The sixth insulating film 67 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The sixth insulating film 67 preferably includes the same type of insulating material as the insulating material of the first insulating film 27 (second insulating film 32). In this embodiment, the sixth insulating film 67 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the sixth insulating film 67 includes a silicon oxide film made of an oxide of the chip 2.

[0213] The sixth insulating film 67 includes a first film portion and a second film portion. The first film portion coats the sidewall of the sixth trench 66 in a film-like manner. The second film portion coats the bottom wall of the sixth trench 66 in a film-like manner and is continuous with the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion. The thickness of the first film portion of the sixth insulating film 67 may be approximately equal to the thickness of the first film portion of the first insulating film 27. The thickness of the second film portion of the sixth insulating film 67 may be approximately equal to the thickness of the second film portion of the first insulating film 27.

[0214] The sixth insulating film 67 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0215] The sixth buried electrode 68 is buried in the sixth trench 66 with a sixth insulating film 67 sandwiched therebetween. The sixth buried electrode 68 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both. The sixth buried electrode 68 preferably includes the same type of conductive material as the conductive material of the first buried electrode 28 (second buried electrode 33). The sixth buried electrode 68 faces the second semiconductor region 7 and the body region 20 with the sixth insulating film 67 sandwiched therebetween.

[0216] The sixth buried electrode 68 has an electrode surface exposed from the sixth trench 66. The electrode surface of the sixth buried electrode 68 is located closer to the bottom wall of the sixth trench 66 with respect to the height position of the first surface portion 8. The electrode surface of the sixth buried electrode 68 is located closer to the second main surface 4 with respect to the depth position of the bottom of the body region 20. The electrode surface of the sixth buried electrode 68 has a recess in an inner portion that tapers toward the bottom wall of the sixth trench 66.

[0217] The semiconductor device 1 includes a plurality of p-type sixth well regions 69 formed in regions along the plurality of fourth source structures 65 in a surface layer portion of the first surface portion 8 (first main surface 3) of the third termination region 17. The sixth well regions 69 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20. Of course, the p-type impurity concentration of the sixth well regions 69 may be lower than the p-type impurity concentration of the body region 20. It is preferable that the p-type impurity concentration of the sixth well regions 69 be approximately equal to the p-type impurity concentration of the first well region 35 (second well region 36).

[0218] The plurality of sixth well regions 69 are formed in one-to-one correspondence with the plurality of fourth source structures 65. The plurality of sixth well regions 69 are formed at intervals from one another in regions along the corresponding fourth source structures 65. The plurality of sixth well regions 69 are formed along the sidewalls and bottom walls of the corresponding fourth source structures 65, and are each electrically connected to the body region 20 in the surface layer portion of the first surface portion 8.

[0219] The plurality of sixth well regions 69 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a portion of the second semiconductor region 7. The bottoms of the plurality of sixth well regions 69 are located closer to the bottom of the second semiconductor region 7 than the depth positions of the bottoms of the plurality of first well regions 35. In this embodiment, the plurality of sixth well regions 69 are exposed from either or both (in this embodiment, both) of the third connecting surface portion 10C and the fourth connecting surface portion 10D. The plurality of sixth well regions 69 form pn junctions with the second semiconductor region 7.

[0220] The configuration on the peripheral region 19 side will be described below. Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in Fig. 1. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII shown in Fig. 1. With reference to Figs. 17 and 18, the semiconductor device 1 includes a p-type outer well region 70 formed in a surface layer portion of the second surface portion 9 in the peripheral region 19. A source potential is applied to the outer well region 70.

[0221] The outer well region 70 has a p-type impurity concentration lower than the p-type impurity concentration of the contact region 37. The p-type impurity concentration of the outer well region 70 is higher than the p-type impurity concentration of the body region 20. Of course, the p-type impurity concentration of the outer well region 70 may be lower than the p-type impurity concentration of the body region 20. It is preferable that the outer well region 70 has a p-type impurity concentration approximately equal to that of the first well region 35 (second well region 36).

[0222] The outer well region 70 is formed at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the second surface portion 9 toward the first surface portion 8 in plan view. The outer well region 70 extends in a band shape along the first surface portion 8 in plan view.

[0223] In this embodiment, the outer well region 70 is formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the first surface portion 8. The outer well region 70 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0224] The outer well region 70 extends from a surface layer portion of the second surface portion 9 toward surface layer portions of the first to fourth connection surface portions 10A to 10D, and has a portion extending in the vertical direction Z along the first to fourth connection surface portions 10A to 10D. The outer well region 70 is electrically connected to the body region 20 in a surface layer portion of the first surface portion 8. The outer well region 70 is connected to the second well region 36, the third well region 44, the fourth well region 59, the fifth well region 60, and the sixth well region 69 at the third connection surface portion 10C (fourth connection surface portion 10D).

[0225] The outer well region 70 is formed at a distance from the bottom of the second semiconductor region 7 toward the second surface portion 9, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. The bottom of the outer well region 70 is located on the bottom side of the second semiconductor region 7 with respect to the depth position of the bottom wall of the gate structure 25. The bottom of the outer well region 70 is located on the bottom side of the second semiconductor region 7 with respect to the depth position of the bottom wall of the first source structure 30 (second source structure 40).

[0226] The bottom of the outer well region 70 is located closer to the bottom of the second semiconductor region 7 than the depth position of the contact region 37. The bottom of the outer well region 70 is preferably formed at a depth position substantially equal to the bottom of the second well region 36 (third well region 44).

[0227] The outer well region 70 forms a pn junction with the second semiconductor region 7. The outer well region 70 spreads a depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer in the outer well region 70 spreads in the horizontal and thickness directions and integrates with the depletion layer spreading from the active region 12. The outer well region 70 expands the depletion layer spreading from the active region 12 toward the periphery of the second surface 9, thereby mitigating the electric field intensity (electric field concentration) at the periphery of the first surface 8 (first to fourth connecting surface portions 10A to 10D).

[0228] The semiconductor device 1 includes a p-type outer contact region 71 formed in the surface layer portion of the second surface portion 9 in the peripheral region 19. The outer contact region 71 has a p-type impurity concentration higher than the p-type impurity concentration of the body region 20. The p-type impurity concentration of the outer contact region 71 is higher than the p-type impurity concentration of the outer well region 70. It is preferable that the p-type impurity concentration of the outer contact region 71 be approximately equal to the p-type impurity concentration of the contact region 37.

[0229] The outer contact region 71 is formed in a surface layer portion of the second surface portion 9 at a distance from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D) and the periphery of the second surface portion 9 (first to fourth side surfaces 5A to 5D) in a plan view. Specifically, the outer contact region 71 is formed in a surface layer portion of the outer well region 70. The outer contact region 71 is formed at a distance from the bottom of the outer well region 70 towards the second surface portion 9, and faces the second semiconductor region 7 across a part of the outer well region 70.

[0230] The outer contact region 71 extends in a band shape along the first surface 8 in a plan view. In this embodiment, the outer contact region 71 is formed in a polygonal ring shape (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the first surface 8. The outer contact region 71 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape).

[0231] The bottom of the outer well region 70 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the gate structure 25. The bottom of the outer well region 70 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the first source structure 30 (second source structure 40). The bottom of the outer contact region 71 is preferably formed at a depth position substantially equal to the bottom of the contact region 37.

[0232] The semiconductor device 1 includes at least one p-type field region 72 formed in the surface layer of the second surface 9 in the peripheral region 19. The multiple field regions 72 may be formed in an electrically floating state or may be fixed to the source potential. The multiple field regions 72 relieve the electric field within the chip 2 in the peripheral region 19.

[0233] The number of field regions 72 is arbitrary. The number of field regions 72 may be 1 or more and 20 or less. The number of field regions 72 may be a value belonging to at least one of the ranges of 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 15 or less, and 15 or more and 20 or less. The number of field regions 72 is typically 1 or more and 8 or less. In this embodiment, the semiconductor device 1 includes four field regions 72.

[0234] The plurality of field regions 72 are formed in the surface layer portion of the second surface portion 9 at intervals from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D) and the periphery of the second surface portion 9 (first to fourth side surfaces 5A to 5D) in a plan view. Specifically, the plurality of field regions 72 are formed in the region between the periphery of the second surface portion 9 and the outer well region 70, at intervals from the outer well region 70 toward the periphery of the second surface portion 9.

[0235] The plurality of field regions 72 are formed at intervals from the bottom of the second semiconductor region 7 toward the second surface portion 9, and face the first semiconductor region 6 across a part of the second semiconductor region 7. The plurality of field regions 72 each extend in a strip shape along the first surface portion 8 in a plan view.

[0236] In this embodiment, the plurality of field regions 72 are each formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surround the first surface portion 8. The plurality of field regions 72 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0237] The plurality of field regions 72 each form a pn junction with the second semiconductor region 7. The plurality of field regions 72 expands a depletion layer toward the second semiconductor region 7 when a reverse bias voltage is applied.

[0238] The depletion layers in the plurality of field regions 72 expand in the horizontal and thickness directions and become integrated with the depletion layer in the outer well region 70. The plurality of field regions 72 expand the depletion layer expanding from the active region 12 toward the periphery of the second surface 9, thereby mitigating the electric field intensity (electric field concentration) at the periphery of the first surface 8 (first to fourth connection surface portions 10A to 10D).

[0239] The width, depth, spacing, p-type impurity concentration, etc. of the multiple field regions 72 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The width of the multiple field regions 72 may be approximately constant or may be non-uniform. The width of the multiple field regions 72 may gradually increase toward the periphery of the second surface 9. The width of the multiple field regions 72 may gradually decrease toward the periphery of the second surface 9.

[0240] The depth of the plurality of field regions 72 may be substantially uniform or may be non-uniform. The depth of the plurality of field regions 72 may gradually increase toward the periphery of the second surface 9. The depth of the plurality of field regions 72 may gradually decrease toward the periphery of the second surface 9.

[0241] The spacing between the multiple field regions 72 may be approximately constant or may be non-uniform. The spacing between the multiple field regions 72 may gradually increase toward the periphery of the second surface 9. The spacing between the multiple field regions 72 may gradually decrease toward the periphery of the second surface 9.

[0242] The p-type impurity concentrations of the plurality of field regions 72 may be substantially constant or may be non-uniform. The p-type impurity concentrations of the plurality of field regions 72 may gradually increase toward the periphery of the second surface 9. The p-type impurity concentrations of the plurality of field regions 72 may gradually decrease toward the periphery of the second surface 9.

[0243] The p-type impurity concentrations of the multiple field regions 72 may be approximately equal to the p-type impurity concentration of the body region 20. The p-type impurity concentrations of the multiple field regions 72 may be higher than the p-type impurity concentration of the body region 20, or may be lower than the p-type impurity concentration of the body region 20.

[0244] The p-type impurity concentrations of the multiple field regions 72 may be approximately equal to the p-type impurity concentration of the first well region 35 (second well region 36). The p-type impurity concentrations of the multiple field regions 72 may be higher than the p-type impurity concentration of the first well region 35 (second well region 36), or may be lower than the p-type impurity concentration of the first well region 35 (second well region 36).

[0245] The p-type impurity concentration of the multiple field regions 72 may be approximately equal to the p-type impurity concentration of the outer well region 70. The p-type impurity concentration of the multiple field regions 72 may be higher than the p-type impurity concentration of the outer well region 70, or may be lower than the p-type impurity concentration of the outer well region 70.

[0246] The p-type impurity concentrations of the multiple field regions 72 may be approximately equal to the p-type impurity concentration of the contact region 37 (outer contact region 71). The p-type impurity concentrations of the multiple field regions 72 may be higher than the p-type impurity concentration of the contact region 37 (outer contact region 71) or lower than the p-type impurity concentration of the contact region 37 (outer contact region 71).

[0247] The semiconductor device 1 includes an insulating first inorganic film 75 that selectively covers the first main surface 3. The first inorganic film 75 is an example of a "subject to be covered." The first inorganic film 75 may be referred to as an "inorganic insulating film (first inorganic insulating film)" or the like.

[0248] The first inorganic film 75 selectively covers the first surface portion 8, the second surface portion 9, and the first to fourth connecting surface portions 10A to 10D. In this embodiment, the first inorganic film 75 is continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second surface portion 9. In other words, the first inorganic film 75 is formed flush with the periphery (first to fourth side surfaces 5A to 5D) of the second surface portion 9.

[0249] The first inorganic film 75 has a layered structure including a lower inorganic film 76 and an upper inorganic film 77. The lower inorganic film 76 may be referred to as a "base insulating film," a "main surface insulating film," etc. The upper inorganic film 77 may be referred to as an "upper insulating film," an "interlayer insulating film," an "intermediate insulating film," etc.

[0250] The lower inorganic film 76 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The lower inorganic film 76 preferably includes the same type of insulating material as the insulating material of the first insulating film 27, etc. In this embodiment, the lower inorganic film 76 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the lower inorganic film 76 includes a silicon oxide film made of an oxide of the chip 2.

[0251] The lower inorganic film 76 selectively covers the first surface portion 8, the second surface portion 9, and the first to fourth connecting surface portions 10A to 10D. The lower inorganic film 76 is connected to the first insulating film 27, the second insulating film 32, the third insulating film 42, the fourth insulating film 52, the fifth insulating film 57, and the sixth insulating film 67 on the first surface portion 8, and exposes the first buried electrode 28, the second buried electrode 33, the third buried electrode 43, the fourth buried electrode 53, the fifth buried electrode 58, and the sixth buried electrode 68.

[0252] The lower inorganic film 76 covers the outer well region 70, the outer contact region 71, and the plurality of field regions 72 in the second surface portion 9. The lower inorganic film 76 is connected to the second insulating film 32, the third insulating film 42, the fourth insulating film 52, the fifth insulating film 57, and the sixth insulating film 67 in the first to fourth connecting surface portions 10A to 10D, and exposes the second buried electrode 33, the third buried electrode 43, the fourth buried electrode 53, the fifth buried electrode 58, and the sixth buried electrode 68.

[0253] The lower inorganic film 76 covers the body region 20, the second well region 36, the third well region 44, the fourth well region 59, the fifth well region 60, the sixth well region 69 and the outer well region 70 in the first to fourth connection surface portions 10A to 10D.

[0254] The upper inorganic film 77 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The upper inorganic film 77 preferably includes a silicon oxide film. The upper inorganic film 77 preferably includes an insulating material having properties different from those of the insulating material of the lower inorganic film 76.

[0255] For example, the upper inorganic film 77 preferably has a single layer structure or a laminated structure including at least one of a silicon oxide film containing phosphorus (PSG film), a silicon oxide film containing phosphorus and boron (BPSG film), a silicon oxide film without added impurities (NSG film), and a tetraethyl orthosilicate film (TEOS film). For example, the upper inorganic film 77 may have a laminated structure including an NSG film laminated on the lower inorganic film 76 and a PSG film (or BPSG film) laminated on the NSG film.

[0256] The upper inorganic film 77 is stacked on the lower inorganic film 76 and selectively covers the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D with the lower inorganic film 76 sandwiched therebetween. The upper inorganic film 77 covers, on the first surface portion 8, the plurality of gate structures 25 (first buried electrodes 28), the plurality of first source structures 30 (second buried electrodes 33), the plurality of second source structures 40 (third buried electrodes 43), the plurality of dummy gate structures 50 (fourth buried electrodes 53), the plurality of third source structures 55 (fifth buried electrodes 58), and the plurality of fourth source structures 65 (sixth buried electrodes 68).

[0257] The upper inorganic film 77 covers the outer well region 70, the outer contact region 71, and the plurality of field regions 72 with the lower inorganic film 76 sandwiched between them in the second surface portion 9. The upper inorganic film 77 covers the plurality of first source structures 30 (second buried electrodes 33), the plurality of second source structures 40 (third buried electrodes 43), the plurality of dummy gate structures 50 (fourth buried electrodes 53), the plurality of third source structures 55 (fifth buried electrodes 58), and the plurality of fourth source structures 65 (sixth buried electrodes 68) in the first to fourth connection surface portions 10A to 10D.

[0258] 8 to 12 etc., the semiconductor device 1 includes a plurality of gate connection electrodes 78 that selectively cover a plurality of gate structures 25 in the active region 12. The gate connection electrodes 78 may also be referred to as "connection electrodes," "connection electrode films," "gate connection electrode films," etc.

[0259] The gate connection electrode 78 may be considered to be one component of the gate structure 25. The gate connection electrodes 78 include either p-type conductive polysilicon or n-type conductive polysilicon, or both. The gate connection electrodes 78 preferably include the same type of conductive material as the conductive material of the first buried electrode 28.

[0260] The plurality of gate connection electrodes 78 are respectively interposed between the plurality of gate structures 25 and the upper inorganic film 77. In other words, the plurality of gate connection electrodes 78 are respectively disposed on the plurality of gate structures 25 and are covered with the upper inorganic film 77.

[0261] In this embodiment, the plurality of gate connection electrodes 78 are formed in a one-to-many correspondence with the plurality of gate structures 25. In this embodiment, the plurality of gate connection electrodes 78 cover both ends of the corresponding gate structures 25 in a film-like manner, and extend in a strip-like manner in the first direction X.

[0262] The plurality of gate connection electrodes 78 are formed at intervals in the second direction Y from the plurality of first source structures 30 in a plan view, and are formed at intervals in the first direction X from the plurality of second source structures 40 .

[0263] The plurality of gate connection electrodes 78 expose the plurality of first source structures 30 and the plurality of second source structures 40, and are electrically isolated from the plurality of first source structures 30 and the plurality of second source structures 40. The plurality of gate connection electrodes 78 are arranged alternately with the plurality of first source structures 30 in the second direction Y in a plan view, and do not face the plurality of second source structures 40 in the second direction Y.

[0264] The plurality of gate connection electrodes 78 are connected to the first buried electrodes 28 in portions covering the corresponding gate structures 25, and each has a portion extending from above the first buried electrodes 28 to above the lower inorganic film 76. In other words, the plurality of gate connection electrodes 78 have a portion facing the gate structures 25 corresponding to the vertical direction Z, and a portion facing the body region 20 in the vertical direction Z.

[0265] In this embodiment, the plurality of gate connection electrodes 78 are formed integrally with the first buried electrodes 28 of the corresponding gate structures 25. That is, the plurality of gate connection electrodes 78 are each formed from an extended portion of the corresponding first buried electrode 28. Of course, the gate connection electrodes 78 may be formed separately from the first buried electrodes 28.

[0266] Each of the gate connection electrodes 78 has an electrode surface extending along the first surface portion 8. In this embodiment, the gate connection electrodes 78 are formed in a tapered shape (a truncated quadrangular pyramid shape) toward the electrode surface in a cross-sectional view. The electrode surface is preferably formed to be wider than the gate structure 25 in the second direction Y.

[0267] The thickness of the gate connection electrode 78 may be less than the depth of the first source structure 30 or may be greater than the depth of the first source structure 30. The thickness of the gate connection electrode 78 may be less than the depth of the second surface portion 9 or may be greater than the depth of the second surface portion 9. The thickness of the gate connection electrode 78 may be less than the depth of the gate structure 25 or may be greater than the depth of the gate structure 25.

[0268] The thickness of the gate connection electrode 78 may be 0.05 μm or more and 3 μm or less. The thickness of the gate connection electrode 78 may have a value belonging to at least one of the ranges of 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The thickness of the gate connection electrode 78 is preferably 1.5 μm or more and 2.5 μm or less.

[0269] 8 to 16 , etc., the semiconductor device 1 includes a sidewall wiring 79 that covers at least one of the first to fourth connecting surface portions 10A to 10D on the second surface portion 9. Specifically, the sidewall wiring 79 is interposed between the lower inorganic film 76 and the upper inorganic film 77. In other words, the sidewall wiring 79 is disposed on the lower inorganic film 76 and is covered by the upper inorganic film 77. The sidewall wiring 79 also functions as a "sidewall structure" that reduces the step between the first surface portion 8 and the second surface portion 9.

[0270] The sidewall wiring 79 preferably extends in a strip shape along at least one of the third connecting surface portion 10C and the fourth connecting surface portion 10D. In this embodiment, the sidewall wiring 79 is formed in a polygonal ring shape (specifically, a quadrangular ring shape) extending along the first to fourth connecting surface portions 10A to 10D in a plan view, and surrounds the first surface portion 8. The sidewall wiring 79 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0271] The sidewall wiring 79 includes a portion extending in a film-like manner along the second surface 9 and portions extending in a film-like manner along the first to fourth connecting surface portions 10A to 10D. The portion of the sidewall wiring 79 located above the second surface 9 may cover the second surface 9 in a film-like manner in an area closer to the second surface 9 than the height position of the first surface 8. In other words, the portion of the sidewall wiring 79 located above the second surface 9 may have a thickness less than the depth of the second surface 9.

[0272] The sidewall wiring 79 is formed at intervals from the plurality of field regions 72 toward the first surface portion 8, and faces the outer well region 70 across the lower inorganic film 76. The sidewall wiring 79 is formed at intervals from the outer edge of the outer well region 70 toward the first surface portion 8.

[0273] In this embodiment, the sidewall wiring 79 is formed at a distance from the outer edge of the outer contact region 71 toward the first surface 8, and has a portion facing the outer contact region 71 across the lower inorganic film 76. The sidewall wiring 79 may also be formed at a distance from the inner edge of the outer contact region 71 toward the first surface 8.

[0274] The sidewall wiring 79 covers the first to fourth connection surface portions 10A to 10D with the lower inorganic film 76 interposed therebetween. The sidewall wiring 79 covers the body region 20, the second well region 36, the third well region 44, the fourth well region 59, the fifth well region 60, the sixth well region 69, and the outer well region 70 with the lower inorganic film 76 interposed therebetween in the first to fourth connection surface portions 10A to 10D.

[0275] The sidewall wiring 79 is electrically connected to the plurality of first source structures 30 (second buried electrodes 33), the plurality of second source structures 40 (third buried electrodes 43), the plurality of dummy gate structures 50 (fourth buried electrodes 53), the plurality of third source structures 55 (fifth buried electrodes 58) and the plurality of fourth source structures 65 (sixth buried electrodes 68) in the first to fourth connection surface portions 10A to 10D.

[0276] The sidewall wiring 79 has an overlapping portion 79a that extends from at least one of the first to fourth connecting surface portions 10A to 10D onto the edge of the first surface portion 8. In this embodiment, the overlapping portion 79a extends from all of the first to fourth connecting surface portions 10A to 10D onto the first surface portion 8 and is formed in a ring shape (specifically, a quadrangular ring) that surrounds the inner portion of the first surface portion 8. The overlapping portion 79a covers the first surface portion 8 in a film-like manner in a plan view and extends in a band shape along the edge of the first surface portion 8.

[0277] The overlapping portion 79a covers the peripheral portion of the first surface portion 8 at a distance from the plurality of gate structures 25. The overlapping portion 79a is electrically connected to the plurality of first source structures 30 (second buried electrodes 33), the plurality of second source structures 40 (third buried electrodes 43), the plurality of dummy gate structures 50 (fourth buried electrodes 53), the plurality of third source structures 55 (fifth buried electrodes 58), and the plurality of fourth source structures 65 (sixth buried electrodes 68) at the peripheral portion of the first surface portion 8.

[0278] The sidewall wiring 79 includes either p-type conductive polysilicon or n-type conductive polysilicon, or both. The sidewall wiring 79 preferably includes the same type of conductive material as the conductive material of the first buried electrode 28, etc.

[0279] In this embodiment, the sidewall wiring 79 is formed integrally with the second buried electrode 33, the third buried electrode 43, the fourth buried electrode 53, the fifth buried electrode 58, and the sixth buried electrode 68. Of course, the sidewall wiring 79 may be formed separately from the second buried electrode 33, the third buried electrode 43, the fourth buried electrode 53, the fifth buried electrode 58, and the sixth buried electrode 68.

[0280] 5 to 7 , the semiconductor device 1 includes a plurality of source openings 80 formed in the first inorganic film 75 in the active region 12. The plurality of source openings 80 penetrate the first inorganic film 75 and selectively expose the plurality of first source structures 30. Specifically, the plurality of source openings 80 are formed in a one-to-one correspondence with the plurality of source structures, respectively, and extend in a strip shape along the corresponding first source structures 30.

[0281] Of course, the multiple source openings 80 may be formed in a one-to-many correspondence with the corresponding first source structures 30. In this case, the multiple source openings 80 may be formed at intervals in the second direction Y along the corresponding first source structures 30. Each of the multiple source openings 80 exposes a corresponding one first source structure 30, a source region 21, and multiple contact regions 37.

[0282] 8 to 16 again, the semiconductor device 1 includes at least one outer opening 81 (one in this embodiment) formed in the first inorganic film 75 in the peripheral region 19. The outer opening 81 penetrates the first inorganic film 75 and exposes both the outer contact region 71 and the sidewall wiring 79.

[0283] Specifically, the outer opening 81 penetrates the upper inorganic film 77 to expose the sidewall wiring 79. The outer opening 81 also penetrates both the lower inorganic film 76 and the upper inorganic film 77 to expose the outer contact region 71. The outer opening 81 extends in a strip shape along the outer contact region 71 and the sidewall wiring 79 in a plan view.

[0284] In this embodiment, the outer opening 81 is formed in a polygonal ring shape (specifically, a square ring shape) in a plan view that surrounds the first surface portion 8. Of course, the semiconductor device 1 may have a plurality of outer openings 81. In this case, the plurality of outer openings 81 may be formed at intervals along the outer contact region 71 so as to surround the first surface portion 8.

[0285] 8 to 12, the semiconductor device 1 includes a plurality of gate openings 82 formed in the first inorganic film 75 in the active region 12. The plurality of gate openings 82 penetrate the first inorganic film 75 and selectively expose the plurality of gate structures 25.

[0286] Specifically, the plurality of gate openings 82 are formed in portions of the first inorganic film 75 that cover the plurality of gate connection electrodes 78, respectively, and expose the plurality of gate connection electrodes 78. The plurality of gate openings 82 are formed in a one-to-one correspondence with the plurality of gate connection electrodes 78, and each extends in a strip shape in the first direction X in plan view.

[0287] 17 and 18 , semiconductor device 1 includes at least one anchor opening 83 (one in this embodiment) formed in first inorganic film 75 in peripheral region 19. Anchor opening 83 is selectively formed in a portion of first inorganic film 75 that covers the peripheral edge portion of second surface portion 9.

[0288] That is, the anchor opening 83 is formed in the region between the first surface portion 8 and the second surface portion 9. Specifically, the anchor opening 83 is formed in the region between the periphery of the second surface portion 9 and the outer well region 70. Even more specifically, the anchor opening 83 is formed in the region between the periphery of the second surface portion 9 and the plurality of field regions 72 (the outermost field region 72).

[0289] The anchor opening 83 penetrates the first inorganic film 75 and exposes the second surface portion 9. Specifically, the anchor opening 83 exposes the second semiconductor region 7. The anchor opening 83 may be dug down toward the bottom of the second semiconductor region 7 with respect to the height position of the second surface portion 9. In other words, the bottom wall of the anchor opening 83 may be located on the bottom side of the second semiconductor region 7 with respect to the height position of the second surface portion 9.

[0290] The anchor opening 83 extends in a band shape along the first surface portion 8 in a plan view. In this embodiment, the anchor opening 83 is formed in a polygonal ring shape (specifically, a square ring shape) surrounding the first surface portion 8 in a plan view. Of course, the semiconductor device 1 may have a plurality of anchor openings 83. In this case, the plurality of anchor openings 83 may be formed at intervals along the first surface portion 8 so as to surround the first surface portion 8.

[0291] The plurality of anchor openings 83 may be formed in a matrix or staggered pattern at intervals in the first direction X and the second direction Y so as to surround the first surface portion 8. Of course, the plurality of anchor openings 83 may be formed in a stripe or lattice pattern so as to surround the first surface portion 8. Furthermore, the plurality of annular anchor openings 83 may be formed in a concentric pattern so as to surround the first surface portion 8.

[0292] The configuration on the first main surface 3 will be described below. Fig. 19 is a plan view showing an example layout of main electrodes (source electrode 85, source wiring 90, gate electrode 95, and gate wiring 100) arranged on the first main surface 3. Fig. 20 is a plan view showing a first example layout of the second inorganic film 110. Fig. 21 is an enlarged plan view showing a main part of the second inorganic film 110.

[0293] 19 to 21 , the semiconductor device 1 includes a source electrode 85 disposed on the first inorganic film 75. The source electrode 85 is a terminal electrode to which a source potential is applied from the outside. The source electrode 85 may also be referred to as an "electrode," a "first electrode," a "first pad electrode," a "first main surface electrode," a "first terminal electrode," a "source pad electrode," or the like.

[0294] The source electrode 85 has a thickness greater than the depth of the gate structure 25. The thickness of the source electrode 85 is preferably greater than the depth of the first source structure 30. The thickness of the source electrode 85 is preferably greater than the depth of the second surface portion 9. The thickness of the source electrode 85 is preferably greater than the thickness (total thickness) of the first inorganic film 75.

[0295] The thickness of the source electrode 85 may be 0.5 μm or more and 5 μm or less. The thickness of the source electrode 85 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0296] The source electrode 85 is disposed on a portion of the first inorganic film 75 that covers the first surface portion 8. The source electrode 85 covers at least the active region 12 in a plan view. The source electrode 85 covers the active region 12 at a distance from the first side end region 13 and the second side end region 14. In other words, the source electrode 85 covers the first surface portion 8 at a distance from both ends of the multiple gate structures 25. Specifically, the source electrode 85 is formed at a distance inward from the multiple gate connection electrodes 78.

[0297] The source electrode 85 may cover either or both of the first termination region 15 and the third termination region 17. That is, the source electrode 85 may face a plurality of dummy gate structures 50 and a plurality of third source structures 55 on the first termination region 15 side, with the first inorganic film 75 sandwiched therebetween. The source electrode 85 may face a plurality of fourth source structures 65 on the third termination region 17 side. Of course, the source electrode 85 may cover the active region 12 at a distance from either or both of the first termination region 15 and the third termination region 17.

[0298] In this embodiment, the source electrode 85 has a first pad portion 85a, a second pad portion 85b, and a third pad portion 85c. The first pad portion 85a has a relatively large planar area and forms the main body of the source electrode 85. In this embodiment, the first pad portion 85a is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the second side surface 5B (second connection surface portion 10B) than the first side surface 5A (first connection surface portion 10A).

[0299] The second pad portion 85b has a planar area smaller than that of the first pad portion 85a, and is drawn out in a strip (rectangular) shape from one end of the first pad portion 85a in the first direction X (the end on the third connecting surface portion 10C side) toward the first connecting surface portion 10A. The third pad portion 85c has a planar area smaller than that of the first pad portion 85a, and is drawn out in a strip (rectangular) shape from the other end of the first pad portion 85a in the first direction X (the end on the fourth connecting surface portion 10D side) toward the first connecting surface portion 10A, and faces the second pad portion 85b in the second direction Y.

[0300] The plane area of ​​the third pad portion 85c may be approximately equal to the plane area of ​​the second pad portion 85b. Of course, the plane area of ​​the third pad portion 85c may be larger than the plane area of ​​the second pad portion 85b, or may be smaller than the plane area of ​​the second pad portion 85b. Either or both of the second pad portion 85b and the third pad portion 85c may be used as a terminal portion for monitoring current.

[0301] The proportion of the source electrode 85 in the first surface portion 8 is preferably 50% or more and less than 100%. The proportion of the source electrode 85 may have a value belonging to any one of the ranges of 50% or more and 60% or more, 60% or more and 70% or more, 70% or more and 80% or more, 80% or more and 90% or more, and 90% or more and less than 100%.

[0302] The source electrode 85 does not necessarily have to have both the second pad portion 85b and the third pad portion 85c at the same time. The source electrode 85 may have only one of the second pad portion 85b and the third pad portion 85c. Of course, the source electrode 85 may be composed of only the first pad portion 85a and may not have both the second pad portion 85b and the third pad portion 85c.

[0303] The source electrode 85 extends from above the first inorganic film 75 into the plurality of source openings 80 and is electrically connected to the plurality of first source structures 30 , the source regions 21 and the plurality of contact regions 37 within the plurality of source openings 80 .

[0304] The source electrode 85 includes a first electrode surface 86 and a first electrode sidewall 87. The first electrode surface 86 extends along the first inorganic film 75. The first electrode surface 86 may have a plurality of recesses recessed toward the first surface portion 8 in portions covering the plurality of source openings 80. The first electrode sidewall 87 is located on the first inorganic film 75. The first electrode sidewall 87 slopes obliquely downward from the first electrode surface 86 toward the first inorganic film 75. In this embodiment, the first electrode sidewall 87 slopes obliquely downward in a curved manner from the first electrode surface 86 toward the first inorganic film 75.

[0305] In this embodiment, the source electrode 85 has a laminated structure including a first lower electrode film 88 and a first upper electrode film 89 laminated in this order from the first inorganic film 75 side. The first lower electrode film 88 is laminated in a film form on the first inorganic film 75 as a base film (barrier film) of the source electrode 85, and forms a lower layer portion of a first electrode side wall 87 of the source electrode 85.

[0306] In this embodiment, the first lower electrode film 88 has a layered structure including a Ti film and a TiN film stacked in this order from the first inorganic film 75 side. The first lower electrode film 88 may have a single-layer structure made of a Ti film or a TiN film. The first lower electrode film 88 has a thickness (total thickness) that is less than the thickness (total thickness) of the first inorganic film 75.

[0307] The thickness (total thickness) of the first lower electrode film 88 may be 0.01 μm or more and 1 μm or less, or 0.75 μm or less, 0.5 μm or less, 0.25 μm or less, or 0.1 μm or less.

[0308] The first lower electrode film 88 collectively covers the region of the first inorganic film 75 where the multiple source openings 80 are formed, and extends into the multiple source openings 80 from above the first inorganic film 75. The first lower electrode film 88 has a portion that covers the insulating main surface of the first inorganic film 75 in a film-like manner, a portion that covers the wall surfaces of the multiple source openings 80 in a film-like manner, and a portion that covers the first surface portions 8 within the multiple source openings 80 in a film-like manner.

[0309] Specifically, the first lower electrode film 88 directly covers the insulating principal surface of the first inorganic film 75 and faces the plurality of gate structures 25 across the first inorganic film 75. The first lower electrode film 88 extends into the plurality of source openings 80 from above the insulating principal surface of the first inorganic film 75 and coats the wall surfaces of the plurality of source openings 80 in a film-like manner.

[0310] The first lower electrode film 88 covers the first surface portion 8 in the form of a film within the plurality of source openings 80. The first lower electrode film 88 is mechanically and electrically connected to the plurality of first source structures 30, the source regions 21, and the plurality of contact regions 37 within the plurality of source openings 80.

[0311] The first upper electrode film 89 is laminated in the form of a film on the first lower electrode film 88 as the main body of the source electrode 85, and forms the upper layer portions of the first electrode surface 86 and the first electrode sidewall 87 of the source electrode 85. The first upper electrode film 89 contains a conductive material different from that of the first lower electrode film 88. The first upper electrode film 89 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.

[0312] The first upper electrode film 89 has a thickness greater than the thickness (total thickness) of the first lower electrode film 88. The thickness of the first upper electrode film 89 is preferably greater than the thickness of the first inorganic film 75. The thickness of the first upper electrode film 89 is preferably greater than the depth of the gate structure 25. The thickness of the first upper electrode film 89 is preferably greater than the depth of the first source structure 30. The thickness of the first upper electrode film 89 is preferably greater than the depth of the second surface portion 9.

[0313] The thickness of the first upper electrode film 89 may be 0.5 μm or more and 5 μm or less. The thickness of the first upper electrode film 89 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0314] The first upper electrode film 89 collectively covers the region of the first inorganic film 75 where the plurality of source openings 80 are formed, and backfills the plurality of source openings 80. The first upper electrode film 89 has a portion that covers the insulating principal surface of the first inorganic film 75 with the first lower electrode film 88 in between, a portion that covers the wall surfaces of the plurality of source openings 80 with the first lower electrode film 88 in between, and a portion that covers the first surface portion 8 with the first lower electrode film 88 in between.

[0315] Specifically, the first upper electrode film 89 covers the insulating main surface of the first inorganic film 75 with the first lower electrode film 88 interposed therebetween, and faces the plurality of gate structures 25 with the first inorganic film 75 and the first lower electrode film 88 interposed therebetween. The first upper electrode film 89 extends into the plurality of source openings 80 from above the first inorganic film 75, and coats the wall surfaces of the plurality of source openings 80 in a film-like manner with the first lower electrode film 88 interposed therebetween.

[0316] The first upper electrode film 89 covers the first surface portion 8 in a film state within the plurality of source openings 80, sandwiching the first lower electrode film 88. The first upper electrode film 89 is electrically connected to the plurality of first source structures 30, the source regions 21, and the plurality of contact regions 37 via the first lower electrode film 88 within the plurality of source openings 80.

[0317] The semiconductor device 1 includes a source wiring 90 arranged around the source electrode 85 on the first inorganic film 75. The same potential (source potential) as the potential (source potential) applied to the source electrode 85 is applied to the source wiring 90. The source wiring 90 may also be referred to as a "wiring," a "first wiring," a "finger electrode," a "source finger," or the like.

[0318] The source wiring 90 has a thickness greater than the depth of the gate structure 25. The thickness of the source wiring 90 is preferably greater than the depth of the first source structure 30. The thickness of the source wiring 90 is preferably greater than the depth of the second surface portion 9. The thickness of the source wiring 90 is preferably approximately equal to the thickness of the source electrode 85.

[0319] Of course, the thickness of the source wiring 90 may be greater than or less than the thickness of the source electrode 85. The thickness of the source electrode 85 is preferably greater than the thickness (total thickness) of the first inorganic film 75.

[0320] The thickness of the source wiring 90 may be 0.5 μm or more and 5 μm or less. The thickness of the source wiring 90 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0321] The source wiring 90 has a wiring width smaller than the electrode width of the source electrode 85, and is selectively routed over the first inorganic film 75. The source wiring 90 extends in a strip shape along the first electrode sidewall 87 of the source electrode 85 at a distance from the first electrode sidewall 87.

[0322] The source wiring 90 preferably extends in a strip shape along at least one of the third connection surface portion 10C and the fourth connection surface portion 10D. In this embodiment, the source wiring 90 is formed in a polygonal ring shape (specifically, a square ring shape) extending along the first to fourth connection surface portions 10A to 10D in a plan view, and surrounds the source electrode 85.

[0323] In this embodiment, source wiring 90 is disposed on first side end region 13, second side end region 14, first termination region 15, second termination region 16, third termination region 17, and fourth termination region 18 in plan view, and surrounds active region 12. Source wiring 90 may have an edge portion that connects the portion extending in first direction X and the portion extending in second direction Y in an arc shape (preferably a quadrant arc shape).

[0324] The source wiring 90 is electrically connected to the source electrode 85 on the first surface 8. Specifically, the source wiring 90 has a portion extending along the second connection surface 10B that extends in a strip shape in the second direction Y toward the source electrode 85 (first pad portion 85a), and is connected to an end of the source electrode 85 (first pad portion 85a). In other words, the source wiring 90 is formed as an extraction wiring that is extracted from the source electrode 85.

[0325] Source wiring 90 covers second termination region 16 and fourth termination region 18 at the connection portion with source electrode 85. Source wiring 90 faces second termination region 16 (plurality of dummy gate structures 50 and plurality of third source structures 55) at the connection portion with source electrode 85, with first inorganic film 75 sandwiched therebetween.

[0326] The source wiring 90 faces the fourth termination region 18 (plurality of fourth source structures 65) at the connection portion with the source electrode 85, with the first inorganic film 75 sandwiched therebetween. The connection portion between the source electrode 85 and the source wiring 90 may be considered as part of the source electrode 85.

[0327] The source wiring 90 is drawn out from the first surface 8 across at least one (all in this embodiment) of the first to fourth connection surface portions 10A to 10D onto the second surface 9. In this embodiment, the source wiring 90 is formed as the outermost wiring on the second surface 9. That is, the source wiring 90 does not face other electrodes in the horizontal direction along the insulating main surface of the first inorganic film 75 in the peripheral region 19. In other words, other electrodes are not interposed between the periphery of the second surface 9 and the region between the source wiring 90.

[0328] The source wiring 90 covers the sidewall wiring 79 on the first to fourth connection surface portions 10A to 10D with the first inorganic film 75 (upper inorganic film 77) interposed therebetween. The film formability of the source wiring 90 is improved by the sidewall wiring 79. The source wiring 90 enters the outer opening 81 from above the first inorganic film 75, and is connected to both the outer contact region 71 and the sidewall wiring 79 within the outer opening 81.

[0329] As a result, the source wiring 90 is electrically connected to the outer contact region 71 and the sidewall wiring 79. The source wiring 90 transmits the source potential applied to the source electrode 85 to the outer contact region 71 and the sidewall wiring 79. In other words, the source wiring 90 transmits the source potential to the first source structure 30, the second source structure 40, the dummy gate structure 50, the third source structure 55, and the fourth source structure 65 via the sidewall wiring 79.

[0330] The source wiring 90 is arranged at a distance from the plurality of field regions 72 toward the first surface portion 8, and faces the outer well region 70 across the first inorganic film 75. In this embodiment, the source wiring 90 is arranged at a distance from the outer edge of the outer well region 70 toward the first surface portion 8, and covers the entire outer contact region 71.

[0331] The source wiring 90 may cross the outer edge of the outer well region 70. In other words, the source wiring 90 may cover the entire outer well region 70. In this case, it is preferable that the source wiring 90 is formed at a distance from the plurality of field regions 72 toward the first surface portion 8. Of course, the source wiring 90 may cover at least one of the plurality of field regions 72.

[0332] The source wiring 90 includes a first wiring surface 91, a first inner side wall 92 on the inner side (the source electrode 85 side), and a first outer side wall 93 on the outer side (the peripheral edge side of the chip 2). The first inner side wall 92 may be referred to as a "first wiring sidewall," and the second inner side wall 102 may be referred to as a "second wiring sidewall."

[0333] The first wiring surface 91 has a portion located on the first surface 8 and a portion located on the second surface 9. The portion of the first wiring surface 91 located on the first surface 8 is located at a height position approximately equal to that of the first electrode surface 86 of the source wiring 90.

[0334] The portion of the first wiring surface 91 located on the second surface 9 is recessed toward the second surface 9 relative to the portion of the first wiring surface 91 located on the first surface 8. It is preferable that the portion of the first wiring surface 91 located on the second surface 9 be located higher than the height position of the first surface 8 (on the side of the portion of the first wiring surface 91 located on the first surface 8). Of course, the portion of the first wiring surface 91 located on the second surface 9 may also be located lower than the height position of the first surface 8 (on the side of the second surface 9).

[0335] The first inner side wall 92 is located on a portion of the first inorganic film 75 that covers the first surface portion 8, with a gap between them and the first electrode side wall 87 of the source electrode 85. The first inner side wall 92 slopes obliquely downward from the first wiring surface 91 toward the first inorganic film 75. In this embodiment, the first inner side wall 92 slopes obliquely downward in a curved manner from the first wiring surface 91 toward the first inorganic film 75.

[0336] The first outer wall 93 is located on a portion of the first inorganic film 75 that covers the second surface 9. The first inner wall 92 slopes obliquely downward from the first wiring surface 91 toward the first inorganic film 75. In this embodiment, the first inner wall 92 slopes obliquely downward in a curved manner from the first wiring surface 91 toward the first inorganic film 75.

[0337] In this embodiment, the first outer wall 93 faces the outer well region 70 with the first inorganic film 75 interposed therebetween. The first outer wall 93 may face the outer contact region 71 with the first inorganic film 75 interposed therebetween. The first outer wall 93 may face the second semiconductor region 7 with the first inorganic film 75 interposed therebetween. The first outer wall 93 may face at least one of the plurality of field regions 72 with the first inorganic film 75 interposed therebetween.

[0338] Like the source electrode 85, the source wiring 90 has a laminated structure including a first lower electrode film 88 and a first upper electrode film 89. The first lower electrode film 88 is laminated in the form of a film on the first inorganic film 75 as a base film (barrier film) of the source wiring 90, and forms lower layers of a first inner wall 92 and a first outer wall 93 of the source wiring 90.

[0339] The first lower electrode film 88 covers the entire region of the first inorganic film 75 where the outer opening 81 is formed, and extends into the outer opening 81 from above the first inorganic film 75. The first lower electrode film 88 is mechanically and electrically connected to the outer contact region 71 and the sidewall wiring 79 within the outer opening 81.

[0340] The first upper electrode film 89 is laminated in film form on the first lower electrode film 88 as the main body of the source wiring 90, and forms the first wiring surface 91 of the source wiring 90, the upper layer portion of the first inner wall 92, and the upper layer portion of the first outer wall 93. The first upper electrode film 89 collectively covers the region of the first inorganic film 75 where the outer opening 81 is formed, and backfills the outer opening 81. The first upper electrode film 89 is electrically connected to the outer contact region 71 and the sidewall wiring 79 via the first lower electrode film 88 within the outer opening 81.

[0341] Inside the chip 2, different electric field distributions are formed on the first surface 8 side (active region 12 side) and the second surface 9 side (peripheral region 19 side). For example, on the first surface 8 side, a substantially uniform electric field distribution is formed along the first main surface 3. On the other hand, on the second surface 9 side, an end portion of the electric field distribution formed on the first surface 8 side is formed, and the electric field is more likely to concentrate there than on the first surface 8.

[0342] That is, the source electrode 85 is disposed on the active region 12 (first region) having a relatively low first electric field, while the source wiring 90 is disposed on the peripheral region 19 (second region) having a second electric field higher than the first electric field.

[0343] That is, since the source wiring 90 is disposed in a location where the electric field is likely to concentrate, the second electric field for the source wiring 90 may be locally higher than the first electric field for the source electrode 85. For example, the electric field within the chip 2 leaks from the inside to the outside of the chip 2 outside the source wiring 90. Therefore, the second electric field on the outer periphery region 19 side may be locally higher in the vicinity of the first outer wall 93 of the source wiring 90.

[0344] The semiconductor device 1 includes a gate electrode 95 disposed on the first inorganic film 75. The gate electrode 95 is a terminal electrode to which a gate potential is applied from the outside. The gate electrode 95 may also be referred to as an "electrode," a "second electrode," a "second pad electrode," a "second main surface electrode," a "second terminal electrode," a "gate pad electrode," or the like.

[0345] The gate electrode 95 has a thickness greater than the depth of the gate structure 25. The thickness of the gate electrode 95 is preferably greater than the depth of the first source structure 30. The thickness of the gate electrode 95 is preferably greater than the depth of the second surface portion 9. The thickness of the gate electrode 95 is preferably approximately equal to the thickness of the source electrode 85. The thickness of the gate electrode 95 is preferably greater than the thickness (total thickness) of the first inorganic film 75.

[0346] The thickness of the gate electrode 95 may be 0.5 μm or more and 5 μm or less. The thickness of the gate electrode 95 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0347] The gate electrode 95 is disposed on the first inorganic film 75 at a distance from the source electrode 85. Specifically, the gate electrode 95 is disposed on a portion of the first inorganic film 75 that covers the first surface portion 8.

[0348] The gate electrode 95 is disposed in a region on the first connection surface portion 10A side of the first pad portion 85a, and is interposed in a region between the second pad portion 85b and the third pad portion 85c. The gate electrode 95 faces the first pad portion 85a in the second direction Y, and faces both the second pad portion 85b and the third pad portion 85c in the first direction X.

[0349] The gate electrode 95 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate electrode 95 has a planar area less than that of the source electrode 85. The gate electrode 95 has a planar area less than that of the first pad portion 85a. The gate electrode 95 may also have a planar area less than that of the second pad portion 85b (third pad portion 85c).

[0350] The proportion of the gate electrode 95 in the first surface portion 8 is preferably 1% or more and 25% or less. The proportion of the gate electrode 95 may be in any one of the ranges of 1% or more and 5% or more, 5% or more and 10% or less, 10% or more and 15% or less, 15% or more and 20% or less, and 20% or more and 25% or less. The proportion of the gate electrode 95 is preferably 10% or less.

[0351] The gate electrode 95 covers at least the active region 12 in a plan view. That is, the gate electrode 95 partially faces the plurality of gate structures 25 and the plurality of first source structures 30, with the first inorganic film 75 sandwiched therebetween. The gate electrode 95 also faces the body region 20, the source region 21, the plurality of first well regions 35, the plurality of second well regions 36, and the plurality of contact regions 37, with the first inorganic film 75 sandwiched therebetween.

[0352] The gate electrode 95 preferably covers the active region 12 at a distance from the first side end region 13 and the second side end region 14. In other words, the gate electrode 95 preferably covers the first surface portion 8 at a distance from both ends of the plurality of gate structures 25. Specifically, the gate electrode 95 is preferably formed at a distance inward from the plurality of gate connection electrodes 78.

[0353] In this embodiment, the gate electrode 95 does not have direct electrical connection to the plurality of gate structures 25. Of course, the gate electrode 95 may be electrically connected to the plurality of gate structures 25 via the plurality of gate openings 82. Of course, the portions of the plurality of gate structures 25 located directly below the gate electrode 95 may be removed.

[0354] The gate electrode 95 may cover either or both of the first termination region 15 and the third termination region 17. That is, the gate electrode 95 may face the plurality of dummy gate structures 50 and the plurality of third source structures 55 on the first termination region 15 side, with the first inorganic film 75 sandwiched therebetween. The gate electrode 95 may also face the plurality of fourth source structures 65 on the third termination region 17 side. Of course, the gate electrode 95 may cover the active region 12 at a distance from both the first termination region 15 and the third termination region 17.

[0355] The gate electrode 95 includes a second electrode surface 96 and a second electrode sidewall 97. The second electrode surface 96 extends along the first inorganic film 75. The second electrode surface 96 is located at a height position substantially equal to that of the first electrode surface 86 of the source electrode 85. Of course, the second electrode surface 96 may be located lower than the first electrode surface 86, or may be located higher than the first electrode surface 86.

[0356] The second electrode side wall 97 is located on the first inorganic film 75. The second electrode side wall 97 slopes obliquely downward from the second electrode surface 96 toward the first inorganic film 75. In this embodiment, the second electrode side wall 97 slopes obliquely downward in a curved shape from the second electrode surface 96 toward the first inorganic film 75.

[0357] In this embodiment, the gate electrode 95 has a laminated structure including a second lower electrode film 98 and a second upper electrode film 99 laminated in this order from the first inorganic film 75 side. The second lower electrode film 98 is laminated in a film form on the first inorganic film 75 as a base film (barrier film) of the gate electrode 95, and forms a lower layer portion of a second electrode sidewall 97 of the gate electrode 95.

[0358] In this embodiment, the second lower electrode film 98 has a layered structure including a Ti film and a TiN film stacked in this order from the first inorganic film 75 side, similar to the first lower electrode film 88 of the source electrode 85. The second lower electrode film 98 may have a single layer structure made of a Ti film or a TiN film. The second lower electrode film 98 has a thickness less than the thickness (total thickness) of the first inorganic film 75. It is preferable that the thickness of the second lower electrode film 98 is approximately equal to the thickness of the first lower electrode film 88.

[0359] The thickness (total thickness) of the second lower electrode film 98 may be 0.01 μm or more and 1 μm or less, or 0.75 μm or less, 0.5 μm or less, 0.25 μm or less, or 0.1 μm or less.

[0360] The second upper electrode film 99 is laminated in the form of a film on the second lower electrode film 98 as the main body of the gate electrode 95, and forms the upper layer portions of the second electrode surface 96 and second electrode sidewall 97 of the gate electrode 95. The second upper electrode film 99 contains a conductive material different from that of the second lower electrode film 98. The second upper electrode film 99 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.

[0361] The second upper electrode film 99 has a thickness greater than the thickness (total thickness) of the second lower electrode film 98. The thickness of the second upper electrode film 99 is preferably greater than the thickness of the first inorganic film 75. The thickness of the second upper electrode film 99 is preferably greater than the depth of the gate structure 25. The thickness of the second upper electrode film 99 is preferably greater than the depth of the first source structure 30. The thickness of the second upper electrode film 99 is preferably greater than the depth of the second surface portion 9. The thickness of the second upper electrode film 99 is preferably approximately equal to the thickness of the first upper electrode film 89.

[0362] The thickness of the second upper electrode film 99 may be 0.5 μm or more and 5 μm or less. The thickness of the second upper electrode film 99 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0363] The semiconductor device 1 includes a gate wiring 100 arranged on the first inorganic film 75 around the source electrode 85. The gate wiring 100 is applied with the same potential (gate potential) as the potential (gate potential) applied to the gate electrode 95. The gate wiring 100 may also be referred to as a "wiring," a "second wiring," a "finger electrode," a "gate finger," or the like.

[0364] The gate wiring 100 has a thickness greater than the depth of the gate structure 25. The thickness of the gate wiring 100 is preferably greater than the depth of the first source structure 30. The thickness of the gate wiring 100 is preferably greater than the depth of the second surface portion 9. The thickness of the gate wiring 100 is preferably approximately equal to the thickness of the source electrode 85 (gate electrode 95).

[0365] Of course, the thickness of the gate wiring 100 may be greater than or less than the thickness of the source electrode 85 (gate electrode 95). The thickness of the gate electrode 95 is preferably greater than the thickness (total thickness) of the first inorganic film 75.

[0366] The thickness of the gate wiring 100 may be 0.5 μm or more and 5 μm or less. The thickness of the gate wiring 100 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0367] The gate wiring 100 has a wiring width smaller than the electrode width of the gate electrode 95, and is selectively routed over the first inorganic film 75. The gate wiring 100 is disposed inward from the periphery of the first surface portion 8 at a distance. Therefore, the gate wiring 100 is not positioned over the second surface portion 9.

[0368] The gate wiring 100 is electrically connected to the gate electrode 95 on the first surface 8. Specifically, the gate wiring 100 is connected to the end of the gate electrode 95 on the first connection surface 10A side. In other words, the gate wiring 100 is formed as an extraction wiring that is extracted from the gate electrode 95. The connection portion between the gate electrode 95 and the gate wiring 100 may be considered to be part of the gate electrode 95.

[0369] The gate wiring 100 is routed over the first inorganic film 75 in a region between the source electrode 85 and the source wiring 90 at a distance from the source electrode 85 and the source wiring 90. The gate wiring 100 extends in a strip shape along the first electrode sidewall 87 of the source electrode 85 at a distance from the first electrode sidewall 87.

[0370] The gate wiring 100 preferably extends in a strip shape along at least one of the third connection surface portion 10C and the fourth connection surface portion 10D. In this embodiment, the gate wiring 100 is formed in a loop shape with ends (specifically, a square loop with ends) that extends along the first to fourth connection surface portions 10A to 10D so as to surround the gate electrode 95.

[0371] Specifically, the gate wiring 100 has, in a plan view, a portion extending in the first direction X along the first connection surface portion 10A, a portion extending in the second direction Y along the second connection surface portion 10B, a portion extending in the second direction Y along the third connection surface portion 10C, and a portion extending in the second direction Y along the fourth connection surface portion 10D.

[0372] The gate wiring 100 has a pair of open ends along the second connection surface portion 10B through which the source wiring 90 passes. The gate wiring 100 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape).

[0373] The gate wiring 100 intersects (specifically, is perpendicular to) both ends of the gate structures 25 at a portion along the third connection surface portion 10C and a portion along the fourth connection surface portion 10D. The gate wiring 100 enters the gate openings 82 from above the first inorganic film 75 and is electrically connected to the ends (both ends) of the gate structures 25 within the gate openings 82.

[0374] Specifically, the gate wiring 100 is mechanically and electrically connected to the plurality of gate connection electrodes 78 in the plurality of gate openings 82, and is electrically connected to the plurality of gate structures 25 via the plurality of gate connection electrodes 78. As a result, the gate potential applied to the gate electrode 95 is applied to the plurality of gate structures 25 via the gate wiring 100.

[0375] The gate wiring 100 may cover the active region 12 at a distance from the first side end region 13 and the second side end region 14. In other words, the gate wiring 100 may be formed at a distance from the plurality of second source structures 40. Of course, the gate wiring 100 may have portions that face the plurality of second source structures 40 with the first inorganic film 75 interposed therebetween.

[0376] The gate wiring 100 may cover at least one of the first termination region 15, the second termination region 16, the third termination region 17, and the fourth termination region 18. The gate electrode 95 may face the plurality of dummy gate structures 50 and the plurality of third source structures 55 on the first termination region 15 (second termination region 16) side, with the first inorganic film 75 interposed therebetween.

[0377] Gate electrode 95 may face the plurality of fourth source structures 65 on the third termination region 17 (fourth termination region 18) side, with first inorganic film 75 sandwiched therebetween. Of course, gate electrode 95 may cover active region 12 at intervals from first termination region 15, second termination region 16, third termination region 17, and fourth termination region 18.

[0378] The gate wiring 100 includes a second wiring surface 101, a second inner side wall 102 on the inner side (the source electrode 85 side), and a second outer side wall 103 on the outer side (the peripheral edge side of the chip 2). The second inner side wall 102 may be referred to as a "first wiring sidewall," and the second inner side wall 102 may be referred to as a "second wiring sidewall."

[0379] The second wiring surface 101 is positioned at a height position approximately equal to that of the first electrode surface 86 of the source electrode 85. The second wiring surface 101 is positioned at a height position approximately equal to that of the portion of the first wiring surface 91 of the source wiring 90 that is positioned on the first surface portion 8.

[0380] The second inner side wall 102 is located on a portion of the first inorganic film 75 that covers the first surface portion 8, with a gap between them and the first electrode side wall 87 of the source electrode 85. The second inner side wall 102 slopes obliquely downward from the second wiring surface 101 toward the first inorganic film 75. In this embodiment, the second inner side wall 102 slopes obliquely downward in a curved manner from the second wiring surface 101 toward the first inorganic film 75.

[0381] The second outer wall 103 is located on a portion of the first inorganic film 75 that covers the first surface 8, spaced apart from the first inner wall 92 of the source wiring 90. The second outer wall 103 slopes obliquely downward from the second wiring surface 101 toward the first inorganic film 75. In this embodiment, the second outer wall 103 slopes obliquely downward in a curved manner from the second wiring surface 101 toward the first inorganic film 75.

[0382] Like the gate electrode 95, the gate wiring 100 has a laminated structure including a second lower electrode film 98 and a second upper electrode film 99. The second lower electrode film 98 is laminated in the form of a film on the first inorganic film 75 as an undercoat film (barrier film) of the gate wiring 100, and forms lower layers of a second inner wall 102 and a second outer wall 103 of the gate wiring 100.

[0383] The second lower electrode film 98 collectively covers the region of the first inorganic film 75 where the multiple gate openings 82 are formed, and extends into the multiple gate openings 82 from above the first inorganic film 75. The second lower electrode film 98 is mechanically and electrically connected to the multiple gate structures 25 (the multiple gate connection electrodes 78) within the multiple gate openings 82.

[0384] The second upper electrode film 99 is laminated in film form on the second lower electrode film 98 as the main body of the gate wiring 100, and forms the second wiring surface 101 of the gate wiring 100, the upper layer of the second inner wall 102, and the upper layer of the second outer wall 103.

[0385] The second upper electrode film 99 collectively covers the region of the first inorganic film 75 where the plurality of gate openings 82 are formed, and backfills the plurality of gate openings 82. The second upper electrode film 99 is electrically connected to the plurality of gate structures 25 (the plurality of gate connection electrodes 78) via the second lower electrode film 98 within the plurality of gate openings 82.

[0386] The semiconductor device 1 includes an insulating second inorganic film 110 that selectively covers the first inorganic film 75. The second inorganic film 110 may be referred to as an "inorganic insulating film (second inorganic insulating film)," an "upper insulating film," a "passivation film," or the like. The second inorganic film 110 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0387] The second inorganic film 110 preferably contains an insulating material different from the insulating material of the first inorganic film 75. Specifically, the second inorganic film 110 preferably contains an insulating material different from the insulating material of the upper inorganic film 77. In this embodiment, the second inorganic film 110 has a single-layer structure made of a silicon nitride film.

[0388] The second inorganic film 110 preferably has a thickness less than the thickness of the source electrode 85 (gate electrode 95). The thickness of the second inorganic film 110 is preferably greater than the thickness of the lower inorganic film 76. The thickness of the second inorganic film 110 is preferably greater than the thickness of the upper inorganic film 77. The thickness of the second inorganic film 110 is preferably greater than the thickness (total thickness) of the first inorganic film 75.

[0389] Of course, the thickness of the second inorganic film 110 may be less than the thickness (total thickness) of the first inorganic film 75. The thickness of the second inorganic film 110 may be less than the thickness of the upper inorganic film 77. The thickness of the second inorganic film 110 may be less than the thickness of the lower inorganic film 76.

[0390] The thickness of the second inorganic film 110 may be greater than the depth of the second surface portion 9 or may be less than the depth of the second surface portion 9. The thickness of the second inorganic film 110 may be greater than the depth of the gate structure 25 or may be less than the depth of the gate structure 25. The thickness of the second inorganic film 110 may be greater than the depth of the first source structure 30 or may be less than the depth of the first source structure 30.

[0391] The thickness of the second inorganic film 110 may be 0.01 μm or more and 5 μm or less. The thickness of the second inorganic film 110 may have a value belonging to at least one of the ranges of 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The thickness of the second inorganic film 110 is preferably 0.1 μm or more and 2 μm or less.

[0392] The second inorganic film 110 selectively covers the source electrode 85, the source wiring 90, the gate electrode 95, and the gate wiring 100 on the first inorganic film 75. Specifically, the second inorganic film 110 has a first inner coating portion 111, a second inner coating portion 112, an outer coating portion 113, and a removed portion 114.

[0393] The first inner covering portion 111 selectively covers the source electrode 85. Specifically, the first inner covering portion 111 covers the first electrode surface 86 of the source electrode 85 in a film-like manner so as to expose at least a portion of the first electrode sidewall 87 of the source electrode 85. In this embodiment, the first inner covering portion 111 exposes the entire first electrode sidewall 87. Specifically, the first inner covering portion 111 covers the first electrode surface 86 at a distance from the first electrode sidewall 87, exposing not only the first electrode sidewall 87 but also the peripheral edge of the first electrode surface 86.

[0394] The first inner covering portion 111 extends flatly over the first electrode surface 86. The first inner covering portion 111 covers the peripheral edge of the first electrode surface 86 (source electrode 85) and exposes the inside of the first electrode surface 86 (source electrode 85). The first inner covering portion 111 extends in a strip shape along the first electrode sidewall 87 at the peripheral edge of the first electrode surface 86. The first inner covering portion 111 has a portion extending along the first pad portion 85a, a portion extending along the second pad portion 85b, and a portion extending along the third pad portion 85c.

[0395] In this embodiment, first inner covering portion 111 has an extension 115 that extends from above source electrode 85 to above the connection portion between source electrode 85 and source wiring 90. In this embodiment, extension 115 is formed to be wider than the other portions. Of course, extension 115 may have approximately the same width as the other portions.

[0396] The extension portion 115 covers the connection portion of the source electrode 85 and the source wiring 90 at a distance from the first electrode sidewall 87 of the source electrode 85 and the first outer sidewall 93 of the source wiring 90. The extension portion 115 preferably covers the connection portion of the source electrode 85 and the source wiring 90 at a distance from the second surface portion 9 toward the first surface portion 8. Of course, the extension portion 115 may have a portion that crosses the second connection surface portion 10B and covers the source wiring 90.

[0397] In this embodiment, the first inner covering portion 111 is formed in a ring shape that surrounds the inner portion of the first electrode surface 86 in a plan view. The first inner covering portion 111 is formed in a polygonal ring shape having four sides that are parallel to the periphery of the chip 2 in a plan view. Specifically, the first inner covering portion 111 is formed in a polygonal ring shape (U-ring) that matches the planar shape of the first electrode surface 86 in a plan view.

[0398] The first inner covering portion 111 defines a first pad opening 116 that exposes the inner portion of the first electrode surface 86. The first pad opening 116 is defined in a polygonal shape having four sides parallel to the periphery of the chip 2 in a plan view. In this embodiment, the first pad opening 116 is defined in a polygonal shape (U-shape) that matches the planar shape of the first electrode surface 86 in a plan view.

[0399] The first inner coating portion 111 may face the active region 12 with the first inorganic film 75 and the source electrode 85 interposed therebetween. In other words, the first inner coating portion 111 may face one or more gate structures 25 and / or one or more first source structures 30 with the first inorganic film 75 and the source electrode 85 interposed therebetween.

[0400] First inner coating portion 111 may face either or both of first termination region 15 and second termination region 16, with first inorganic film 75 and source electrode 85 sandwiched between them. In other words, first inner coating portion 111 may face one or more dummy gate structures 50 and / or one or more third source structures 55, with first inorganic film 75 and source electrode 85 sandwiched between them.

[0401] First inner coating portion 111 may face either or both of third termination region 17 and fourth termination region 18, with first inorganic film 75 and source electrode 85 sandwiched between them. In other words, first inner coating portion 111 may face one or more fourth source structures 65, with first inorganic film 75 and source electrode 85 sandwiched between them.

[0402] The first inner coating portion 111 preferably has a width greater than the thickness of the source electrode 85. Of course, the width of the first inner coating portion 111 may be less than the thickness of the source electrode 85. The width of the first inner coating portion 111 may be not less than 1 μm and not more than 100 μm.

[0403] The width of the first inner covering portion 111 may have a value belonging to at least one of the ranges of 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or more and 100 μm or less.

[0404] The first inner covering portion 111 is preferably formed at a distance from the first electrode sidewall 87 that is greater than the thickness of the source electrode 85. Of course, the distance between the first inner covering portions 111 may be less than the thickness of the source electrode 85. The distance between the first inner covering portions 111 may be 0.1 μm or more and 100 μm or less.

[0405] The spacing of the first inner covering portion 111 may have a value belonging to at least one of the ranges of 0.1 μm to 1 μm, 1 μm to 5 μm, 5 μm to 10 μm, 10 μm to 20 μm, 20 μm to 30 μm, 30 μm to 40 μm, 40 μm to 50 μm, 50 μm to 60 μm, 60 μm to 70 μm, 70 μm to 80 μm, 80 μm to 90 μm, and 90 μm to 100 μm.

[0406] The second inner covering portion 112 selectively covers the gate electrode 95. Specifically, the second inner covering portion 112 covers the second electrode surface 96 of the gate electrode 95 in a film-like manner so as to expose at least a portion of the second electrode sidewall 97 of the gate electrode 95. In this embodiment, the second inner covering portion 112 exposes the entire second electrode sidewall 97. Specifically, the second inner covering portion 112 covers the second electrode surface 96 at a distance from the second electrode sidewall 97, exposing not only the second electrode sidewall 97 but also the peripheral edge of the second electrode surface 96.

[0407] The second inner covering portion 112 extends flatly over the second electrode surface 96. The second inner covering portion 112 covers the peripheral edge of the second electrode surface 96 (gate electrode 95), leaving the inside of the second electrode surface 96 (gate electrode 95) exposed. The second inner covering portion 112 extends in a strip shape along the second electrode sidewall 97 at the peripheral edge of the second electrode surface 96.

[0408] In this embodiment, the second internal covering portion 112 is formed in a ring shape that surrounds the inner portion of the second electrode surface 96 in a plan view. The second internal covering portion 112 is formed in a polygonal ring shape (a square ring shape in this embodiment) that has four sides parallel to the periphery of the chip 2 in a plan view. Specifically, the second internal covering portion 112 is formed in a polygonal ring shape (specifically, a square ring shape) that matches the planar shape of the second electrode surface 96 in a plan view.

[0409] The second inner covering portion 112 defines a second pad opening 117 that exposes the inner portion of the second electrode surface 96. The second pad opening 117 is defined in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in plan view.

[0410] The second inner coating portion 112 may face the active region 12 with the first inorganic film 75 and the gate electrode 95 interposed therebetween. In other words, the second inner coating portion 112 may face one or more gate structures 25 and / or one or more first source structures 30 with the first inorganic film 75 and the gate electrode 95 interposed therebetween.

[0411] The second inner coating portion 112 may face the first termination region 15, with the first inorganic film 75 and the gate electrode 95 interposed therebetween. In other words, the second inner coating portion 112 may face one or more dummy gate structures 50 and / or one or more third source structures 55, with the first inorganic film 75 and the gate electrode 95 interposed therebetween.

[0412] The second inner coating portion 112 may face the third termination region 17, with the first inorganic film 75 and the gate electrode 95 interposed therebetween. In other words, the second inner coating portion 112 may face one or more fourth source structures 65, with the first inorganic film 75 and the gate electrode 95 interposed therebetween.

[0413] The second inner coating portion 112 preferably has a width greater than the thickness of the gate electrode 95. Of course, the width of the second inner coating portion 112 may be less than the thickness of the gate electrode 95. The width of the second inner coating portion 112 may be approximately equal to the width of the first inner coating portion 111. Of course, the width of the second inner coating portion 112 may be less than the width of the first inner coating portion 111 or greater than the width of the first inner coating portion 111. The width of the second inner coating portion 112 may be not less than 1 μm and not more than 100 μm.

[0414] The width of the second inner covering portion 112 may have a value belonging to at least one of the ranges of 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, and 90 μm or more and 100 μm or less.

[0415] The second inner coating portions 112 are preferably formed at a distance from the second electrode sidewall 97 that is greater than the thickness of the gate electrode 95. Of course, the distance between the second inner coating portions 112 may be less than the thickness of the gate electrode 95. The distance between the second inner coating portions 112 may be approximately equal to the distance between the first inner coating portions 111. The distance between the second inner coating portions 112 may be less than the distance between the first inner coating portions 111, or may be greater than the distance between the first inner coating portions 111. The distance between the second inner coating portions 112 may be 0.1 μm or more and 100 μm or less.

[0416] The spacing of the second inner covering portion 112 may have a value belonging to at least one of the ranges of 0.1 μm to 1 μm, 1 μm to 5 μm, 5 μm to 10 μm, 10 μm to 20 μm, 20 μm to 30 μm, 30 μm to 40 μm, 40 μm to 50 μm, 50 μm to 60 μm, 60 μm to 70 μm, 70 μm to 80 μm, 80 μm to 90 μm, and 90 μm to 100 μm.

[0417] The outer covering portion 113 selectively covers the first inorganic film 75 at a distance from the first inner covering portion 111 and the second inner covering portion 112. Specifically, the outer covering portion 113 is formed on a covering portion of the first inorganic film 75 that corresponds to the second surface portion 9. The outer covering portion 113 extends in a band shape along the first surface portion 8 in a plan view. The outer covering portion 113 is formed in a ring shape (a square ring shape in this embodiment) that surrounds the first surface portion 8 in a plan view.

[0418] The outer covering portion 113 covers the outer well region 70 and the plurality of field regions 72 on the second surface portion 9 side, sandwiching the first inorganic film 75. The outer covering portion 113 enters the anchor opening 83 on the second surface portion 9 side from above the first inorganic film 75, and is mechanically connected to the second surface portion 9 (second semiconductor region 7) within the anchor opening 83.

[0419] The outer covering portion 113 extends in a film-like shape along the second surface portion 9 within the anchor opening 83. The outer covering portion 113 defines an anchor recess 118 that is recessed toward the anchor opening 83 in the covering portion relative to the anchor opening 83.

[0420] When multiple anchor openings 83 are formed in the first inorganic film 75, the outer covering portion 113 defines multiple anchor recesses 118. The anchor recesses 118 have a planar shape that is approximately similar to the planar shape of the anchor openings 83. The anchor recesses 118 extend in a band shape (annular in this form) along the anchor openings 83 in a planar view.

[0421] In this embodiment, the outer covering portion 113 is drawn out from the anchor opening 83 toward the periphery (first to fourth side faces 5A to 5D) of the second surface portion 9. The outer covering portion 113 is formed at a distance inward from the periphery of the second surface portion 9, and exposes the first inorganic film 75 from the periphery of the second surface portion 9.

[0422] The outer covering portion 113 covers at least a portion of the source wiring 90 on the second surface portion 9 side. The outer covering portion 113 preferably covers at least a portion of the first outer wall 93 of the source wiring 90. In this embodiment, the outer covering portion 113 covers the entire area of ​​the source wiring 90 in a cross-sectional view.

[0423] The outer covering portion 113 covers the first wiring surface 91 of the source wiring 90 in a film-like manner, and extends flatly over the first wiring surface 91, following the slope of the first wiring surface 91. The outer covering portion 113 covers the first inner sidewall 92 of the source wiring 90 in a film-like manner, and has an inclined surface that extends following the slope of the first inner sidewall 92. The outer covering portion 113 covers the first outer sidewall 93 of the source wiring 90 in a film-like manner, and has an inclined surface that extends following the slope of the first outer sidewall 93.

[0424] In this embodiment, the outer covering portion 113 covers the entire area of ​​the source wiring 90 in plan view, excluding the connection portion between the source electrode 85 and the source wiring 90. The outer covering portion 113 exposes the first outer wall 93 of the source wiring 90 at the connection portion between the source electrode 85 and the source wiring 90. This prevents stress generated in the source electrode 85 from being applied to the second inorganic film 110 via the source wiring 90.

[0425] The outer coating portion 113 is drawn from the second surface portion 9 side to the first surface portion 8 side via the source wiring 90. That is, the outer coating portion 113 has a portion facing the outer opening 81 with the source wiring 90 interposed therebetween. The outer coating portion 113 also has a portion facing the sidewall wiring 79 with the first inorganic film 75 (upper inorganic film 77) and the source wiring 90 interposed therebetween.

[0426] The outer covering portion 113 covers at least a portion of the gate wiring 100 on the first surface portion 8 side. The outer covering portion 113 preferably covers at least a portion of the second outer wall 103 of the gate wiring 100. In this embodiment, the outer covering portion 113 covers the entire area of ​​the gate wiring 100 in a cross-sectional view.

[0427] The outer covering portion 113 covers the second wiring surface 101 of the gate wiring 100 in a film-like manner, and extends flatly over the second wiring surface 101, following the slope of the second wiring surface 101. The outer covering portion 113 covers the second inner sidewall 102 of the gate wiring 100 in a film-like manner, and has an inclined surface that extends following the slope of the second inner sidewall 102. The outer covering portion 113 covers the second outer sidewall 103 of the gate wiring 100 in a film-like manner, and has an inclined surface that extends following the slope of the second outer sidewall 103.

[0428] In this embodiment, the outer covering portion 113 covers the entire gate wiring 100 in plan view, except for the connection portion between the gate electrode 95 and the gate wiring 100. The outer covering portion 113 exposes the second outer wall 103 of the gate wiring 100 at the connection portion between the gate electrode 95 and the gate wiring 100. This prevents stress generated in the gate electrode 95 from being applied to the second inorganic film 110 via the gate wiring 100.

[0429] The outer covering portion 113 covers the first inorganic film 75 at a distance from the first inner covering portion 111 and the second inner covering portion 112 on the first surface portion 8 side. The outer covering portion 113 covers the first inorganic film 75 so as to expose at least a portion of the first electrode sidewall 87 of the source electrode 85.

[0430] In this embodiment, the outer covering portion 113 covers the first inorganic film 75 at a distance from the first electrode sidewall 87, exposing the entire area of ​​the first electrode sidewall 87. In this embodiment, the outer covering portion 113 has an inner edge portion positioned between the first electrode sidewall 87 of the source electrode 85 and the second inner sidewall 102 of the gate wiring 100. The inner edge portion of the outer covering portion 113 extends along the first electrode sidewall 87 at a distance from the first electrode sidewall 87.

[0431] The outer coating portion 113 covers the first inorganic film 75 so as to expose at least a portion of the second electrode sidewall 97 of the gate electrode 95. In this embodiment, the outer coating portion 113 covers the first inorganic film 75 at a distance from the second electrode sidewall 97, exposing the entire area of ​​the second electrode sidewall 97.

[0432] That is, in plan view, the outer covering portion 113 collectively surrounds both the source electrode 85 and the gate electrode 95 at a distance from the source electrode 85 and the gate electrode 95. The inner edge of the outer covering portion 113 is positioned between the first inner sidewall 92 of the source wiring 90 and the second electrode sidewall 97 of the gate electrode 95. The inner edge of the outer covering portion 113 extends along the second electrode sidewall 97 at a distance from the second electrode sidewall 97.

[0433] The outer coating portion 113 may face the active region 12 with the first inorganic film 75 interposed therebetween. In other words, the outer coating portion 113 may face one or more gate structures 25 and / or one or more first source structures 30 with the first inorganic film 75 interposed therebetween.

[0434] The outer covering portion 113 may face either one or both of the first side end region 13 and the second side end region 14, with the first inorganic film 75 interposed therebetween. In other words, the outer covering portion 113 may face one or more first source structures 30 and / or one or more second source structures 40, with the first inorganic film 75 interposed therebetween.

[0435] The outer covering portion 113 may face either one or both of the first termination region 15 and the second termination region 16, with the first inorganic film 75 sandwiched between them. In other words, the outer covering portion 113 may face one or more dummy gate structures 50 and / or one or more third source structures 55, with the first inorganic film 75 sandwiched between them.

[0436] The outer coating portion 113 may face either one or both of the third termination region 17 and the fourth termination region 18, with the first inorganic film 75 interposed therebetween. In other words, the outer coating portion 113 may face one or more fourth source structures 65, with the first inorganic film 75 interposed therebetween.

[0437] The removed portion 114 includes a first removed portion 114a, a second removed portion 114b, and a third removed portion 114c. The first removed portion 114a is defined in the region between the first inner covering portion 111 and the outer covering portion 113, and exposes the first electrode sidewall 87 of the source electrode 85. In this embodiment, the first removed portion 114a extends in a strip shape along the first electrode sidewall 87, and exposes the peripheral portion of the first electrode surface 86, the first electrode sidewall 87, and the first inorganic film 75 between the source electrode 85 and the gate wiring 100.

[0438] The second removed portion 114b is defined in the region between the second inner covering portion 112 and the outer covering portion 113 and is connected to the first removed portion 114a. The second removed portion 114b exposes the second electrode sidewall 97 of the gate electrode 95. In this embodiment, the second removed portion 114b extends in a strip shape along the second electrode sidewall 97, exposing the peripheral edge of the second electrode surface 96, the second electrode sidewall 97, and the first inorganic film 75 between the source wiring 90 and the gate electrode 95.

[0439] The third removed portion 114c is defined in the region between the first inner coating portion 111 and the second inner coating portion 112, and is connected to the first removed portion 114a and the second removed portion 114b. The third removed portion 114c exposes the first electrode sidewall 87 of the source electrode 85 and the second electrode sidewall 97 of the gate electrode 95.

[0440] In this embodiment, the third removed portion 114c extends in a strip shape along the first electrode side wall 87 and the second electrode side wall 97, exposing the peripheral portion of the first electrode surface 86, the first electrode side wall 87, the peripheral portion of the second electrode surface 96, the second electrode side wall 97, and the first inorganic film 75 between the gate electrode 95 and the source electrode 85.

[0441] The semiconductor device 1 includes an insulating organic film 120 that selectively covers the second inorganic film 110. The organic film 120 may be referred to as an "organic insulating film," a "resin film," or the like. The organic film 120 preferably includes a transparent resin or a translucent resin.

[0442] The organic film 120 preferably includes a photosensitive resin. The photosensitive resin may be a negative type or a positive type. The organic film 120 may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0443] The organic film 120 may have a thickness greater than the depth of the gate structure 25. The thickness of the organic film 120 may be greater than the depth of the first source structure 30. The thickness of the organic film 120 may be greater than the thickness (total thickness) of the first inorganic film 75. The thickness of the organic film 120 may be greater than the thickness of the source electrode 85 (gate electrode 95).

[0444] The thickness of the organic film 120 may be greater than the thickness of the second inorganic film 110. The thickness of the organic film 120 is preferably less than the thickness of the chip 2. The thickness of the organic film 120 may be greater than the thickness of the second semiconductor region 7 or may be less than the thickness of the second semiconductor region 7.

[0445] The thickness of the organic film 120 may be 1 μm or more and 25 μm or less. The thickness of the organic film 120 may have a value belonging to at least one of the ranges of 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or more and 25 μm or less.

[0446] The organic film 120 covers the second surface portion 9 from above the first surface portion 8 across the first to fourth connection surface portions 10A to 10D. The organic film 120 fills the removed portion 114 of the second inorganic film 110 on the first surface portion 8 side, and directly covers the first inner covering portion 111, the second inner covering portion 112, and the outer covering portion 113 of the second inorganic film 110.

[0447] The organic film 120 spans the first inner coating portion 111 and the outer coating portion 113, and has a portion that fills the region between the first inner coating portion 111 and the outer coating portion 113 (i.e., the first removed portion 114a). The organic film 120 directly covers the first electrode sidewall 87 of the source electrode 85 in the first removed portion 114a.

[0448] In this embodiment, the organic film 120 directly covers the peripheral edge of the first electrode surface 86 and the first electrode sidewall 87 in the first removed portion 114 a. The organic film 120 directly covers the portion of the first inorganic film 75 that is exposed between the first electrode sidewall 87 of the source electrode 85 and the outer covering portion 113 (gate wiring 100) in the first removed portion 114 a.

[0449] The organic film 120 spans the second inner coating portion 112 and the outer coating portion 113, and has a portion that fills the region between the second inner coating portion 112 and the outer coating portion 113 (i.e., the second removed portion 114b). The organic film 120 directly covers the second electrode sidewall 97 of the gate electrode 95 in the second removed portion 114b.

[0450] In this embodiment, the organic film 120 directly covers the peripheral edge of the second electrode surface 96 and the second electrode sidewall 97 in the second removed portion 114 b. The organic film 120 directly covers the portion of the first inorganic film 75 that is exposed between the second electrode sidewall 97 of the gate electrode 95 and the outer covering portion 113 (source wiring 90) in the second removed portion 114 b.

[0451] The organic film 120 spans the first inner coating portion 111 and the second inner coating portion 112, and has a portion that fills the region between the first inner coating portion 111 and the second inner coating portion 112 (i.e., the third removed portion 114c). The organic film 120 directly covers both the first electrode sidewall 87 of the source electrode 85 and the second electrode sidewall 97 of the gate electrode 95 in the third removed portion 114c.

[0452] In this embodiment, the organic film 120 directly covers the peripheral edge of the first electrode surface 86, the first electrode sidewall 87, the peripheral edge of the second electrode surface 96, and the second electrode sidewall 97 in the third removed portion 114 c. The organic film 120 directly covers the portion of the first inorganic film 75 that is exposed between the first electrode sidewall 87 of the source electrode 85 and the second electrode sidewall 97 of the gate electrode 95 in the third removed portion 114 c.

[0453] The organic film 120 covers the entire periphery of the first internal covering portion 111 and defines a first upper pad opening 121 that exposes the inner portion of the first electrode surface 86 (see FIGS. 1 to 3). Specifically, the organic film 120 covers the first internal covering portion 111 with a gap between the inner edge (inner wall) of the first internal covering portion 111 and the outer edge (outer wall) of the first internal covering portion 111, exposing the inner edge of the first internal covering portion 111. In other words, the wall surface of the first upper pad opening 121 is positioned closer to the first electrode sidewall 87 than the wall surface of the first pad opening 116, and faces the first electrode surface 86 across the first internal covering portion 111.

[0454] The organic film 120 covers the entire periphery of the second internal covering portion 112 and defines a second upper pad opening 122 that exposes the inner portion of the second electrode surface 96 (see FIGS. 1 to 3). Specifically, the organic film 120 covers the second internal covering portion 112 with a gap between the inner edge (inner wall) of the second internal covering portion 112 and the outer edge (outer wall) of the second internal covering portion 112, exposing the inner edge of the second internal covering portion 112. In other words, the wall surface of the second upper pad opening 122 is positioned closer to the second electrode sidewall 97 than the wall surface of the second pad opening 117, and faces the second electrode surface 96 across the second internal covering portion 112.

[0455] The organic film 120 is extended from above the source electrode 85 and the gate electrode 95 toward the gate wiring 100, and covers at least a portion of the gate wiring 100 with the outer coating portion 113 in between. The organic film 120 preferably covers the second outer wall 103 of the gate wiring 100 with the outer coating portion 113 in between.

[0456] In this embodiment, the organic film 120 covers the entire area of ​​the gate wiring 100 in a cross-sectional view, sandwiching the outer coating portion 113. That is, the organic film 120 has, in a cross-sectional view, a portion that covers the second wiring surface 101 with the outer coating portion 113 in between, a portion that covers the second inner wall 102 with the outer coating portion 113 in between, and a portion that covers the second outer wall 103 with the outer coating portion 113 in between.

[0457] In this embodiment, the organic film 120 has a portion that directly covers the portion of the second outer wall 103 of the gate wiring 100 that is exposed from the second inner coating portion 112 and the outer coating portion 113 at the connection portion between the gate electrode 95 and the gate wiring 100. The organic film 120 also covers the second wiring surface 101 of the gate wiring 100 at the connection portion between the gate electrode 95 and the gate wiring 100.

[0458] The organic film 120 is extended from above the gate wiring 100 toward the source wiring 90, and covers at least a portion of the source wiring 90 with the outer covering portion 113 sandwiched therebetween. The organic film 120 has a portion that directly covers the outer covering portion 113 in the region between the source wiring 90 and the gate wiring 100.

[0459] The organic film 120 preferably covers the first outer wall 93 of the source wiring 90, sandwiching the outer coating portion 113. In this embodiment, the organic film 120 covers the entire area of ​​the source wiring 90, sandwiching the outer coating portion 113 in a cross-sectional view. That is, the organic film 120 has, in a cross-sectional view, a portion that covers the first wiring surface 91, sandwiching the outer coating portion 113, a portion that covers the first inner wall 92, sandwiching the outer coating portion 113, and a portion that covers the first outer wall 93, sandwiching the outer coating portion 113.

[0460] In this embodiment, the organic film 120 has a portion that directly covers the portion of the first outer wall 93 of the source wiring 90 that is exposed from the first inner covering portion 111 and the outer covering portion 113 at the connection portion of the source electrode 85 and the source wiring 90. In this embodiment, the organic film 120 also covers the first wiring surface 91 of the source wiring 90 at the connection portion of the source electrode 85 and the source wiring 90.

[0461] The organic film 120 is drawn from the first surface portion 8 side to the second surface portion 9 side via the source wiring 90. That is, the organic film 120 has a portion facing the outer opening 81 with the source wiring 90 in between. The organic film 120 also has a portion facing the sidewall wiring 79 with the source wiring 90 in between.

[0462] The organic film 120 covers the outer well region 70 and the plurality of field regions 72 on the second surface 9 side, sandwiching the first inorganic film 75 and the second inorganic film 110. The organic film 120 covers the anchor openings 83 on the periphery of the second surface 9, sandwiching the second inorganic film 110. The organic film 120 engages with the anchor recesses 118 of the second inorganic film 110 (the anchor openings 83 of the first inorganic film 75).

[0463] In this embodiment, the organic film 120 is drawn out from the anchor opening 83 toward the periphery of the second surface portion 9 (first to fourth side surfaces 5A to 5D). The organic film 120 is formed at a distance inward from the periphery of the second surface portion 9, exposing the first inorganic film 75 from the periphery of the second surface portion 9. In this embodiment, the organic film 120 covers the outer covering portion 113 at a distance inward from the outer edge (outer wall) of the outer covering portion 113, exposing the outer edge of the outer covering portion 113.

[0464] The semiconductor device 1 includes a drain electrode 125 covering the second main surface 4. The drain electrode 125 is a terminal electrode to which a drain potential is applied from the outside. The drain electrode 125 may also be referred to as an "electrode," a "third electrode," a "third pad electrode," a "third main surface electrode," a "third terminal electrode," a "drain pad electrode," or the like.

[0465] The drain electrode 125 is electrically connected to the first semiconductor region 6. The drain electrode 125 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain electrode 125 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0466] The breakdown voltage that can be applied between the source electrode 85 and the drain electrode 125 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0467] As described above, the semiconductor device 1 (electronic component) includes the insulating first inorganic film 75 (object to be covered), the source electrode 85 (electrode), the source wiring 90 (wiring), the insulating second inorganic film 110 (inorganic film), and the insulating organic film 120. The source electrode 85 is disposed on the first inorganic film 75, and has a first electrode sidewall 87 on the first inorganic film 75. The source wiring 90 is disposed around the source electrode 85 on the first inorganic film 75.

[0468] The second inorganic film 110 has a first inner covering portion 111 that covers the source electrode 85 so as to expose the first electrode sidewall 87, and an outer covering portion 113 that covers the source wiring 90 at a distance from the first inner covering portion 111. The organic film 120 spans the first inner covering portion 111 and the outer covering portion 113, and covers the source electrode 85 between the first inner covering portion 111 and the outer covering portion 113.

[0469] This configuration provides a semiconductor device 1 having a novel layout. Since the semiconductor device 1 is used in various environments depending on the application, the semiconductor device 1 is required to have durability suitable for various usage environmental conditions.

[0470] For example, when the semiconductor device 1 is installed in a vehicle such as a hybrid vehicle, an electric vehicle, or a fuel cell vehicle that uses a motor as a drive source, excellent durability is required to be compatible with these operating environmental conditions. The durability of the semiconductor device 1 is evaluated, for example, by a high-temperature, high-humidity bias test. In the high-temperature, high-humidity bias test, the electrical operation of the semiconductor device 1 is evaluated while the semiconductor device 1 is exposed to a high-temperature, high-humidity environment.

[0471] In a high-temperature environment, stress caused by thermal expansion of the source electrode 85 concentrates near the first electrode sidewall 87 of the source electrode 85. When the second inorganic film 110 covers the first electrode sidewall 87, the second inorganic film 110 may peel off from the first electrode sidewall 87 due to the stress of the source electrode 85. If peeling of the second inorganic film 110 occurs, moisture (water) may penetrate from the peeled portion of the second inorganic film 110 in a high-humidity environment.

[0472] In this regard, in the semiconductor device 1, the first inner covering portion 111 of the second inorganic film 110 exposes the first electrode sidewall 87, and the outer covering portion 113 of the second inorganic film 110 is formed at a distance from the first inner covering portion 111. This reduces the number of peeling starting points of the second inorganic film 110 caused by stress of the source electrode 85, and suppresses peeling of the second inorganic film 110.

[0473] On the other hand, the organic film 120 covers the exposed portion of the source electrode 85 in the region between the first inner covering portion 111 and the outer covering portion 113. The organic film 120 has a hardness lower than that of the second inorganic film 110. Therefore, even if stress due to thermal expansion occurs in the source electrode 85, the organic film 120 elastically absorbs the stress. This prevents the organic film 120 from peeling off from the first electrode sidewall 87, and protects the source electrode 85 by the organic film 120.

[0474] Due to the layout in which the source wiring 90 is disposed around the source electrode 85, an electric field higher than the electric field on the source electrode 85 side may be concentrated near the source wiring 90. If moisture (water) reaches the source wiring 90 from the peeled portion in a high-temperature environment, the oxidation reaction of the moisture (water) and the source wiring 90 may be accelerated due to the high electric field near the source wiring 90.

[0475] In this regard, in the semiconductor device 1, the source wiring 90 is protected by the outer coating 113, and therefore the outer coating 113 prevents moisture (water) from contacting the source wiring 90. This prevents oxidation of the source wiring 90. As a result, a decrease in the adhesion of the organic film 120 and a decrease in the wiring resistance of the source wiring 90 caused by the oxidized portion are prevented.

[0476] The source wiring 90 has a first outer wall 93 (wiring sidewall) on the opposite side from the source electrode 85 in a cross-sectional view. In this case, it is preferable that the outer coating portion 113 of the second inorganic film 110 covers the first outer wall 93 of the source wiring 90 in a cross-sectional view. It is preferable that the organic film 120 covers the first outer wall 93 of the source wiring 90 with the outer coating portion 113 sandwiched therebetween in a cross-sectional view. With this configuration, oxidation of the source wiring 90 starting from the first outer wall 93 is appropriately suppressed. Such a configuration is particularly effective when an electric field is concentrated on the first outer wall 93 side.

[0477] The outer coating portion 113 may cover the entire area of ​​the source wiring 90 in a cross-sectional view. In this case, the organic film 120 may cover the entire area of ​​the source wiring 90, sandwiching the outer coating portion 113 in a cross-sectional view. With this configuration, oxidation of the source wiring 90 is appropriately suppressed over the entire area of ​​the source wiring 90.

[0478] It is preferable that the first inner covering portion 111 covers the source electrode 85 at a distance from the first electrode sidewall 87. With this configuration, peeling of the first inner covering portion 111 due to thermal expansion of the source electrode 85 is appropriately suppressed.

[0479] The outer covering portion 113 preferably exposes the first electrode sidewall 87. This configuration appropriately prevents the outer covering portion 113 from peeling off due to thermal expansion of the source electrode 85. The outer covering portion 113 preferably covers the first inorganic film 75 at a distance from the first electrode sidewall 87.

[0480] It is preferable that the organic film 120 has a portion that directly covers the first electrode side wall 87. With this configuration, the first electrode side wall 87 is appropriately protected by the organic film 120. It is preferable that the first inner covering portion 111 exposes the peripheral edge of the source electrode 85. In this case, it is preferable that the organic film 120 has a portion that directly covers the first electrode side wall 87 of the source electrode 85 and the peripheral edge of the source electrode 85.

[0481] In the region between the source electrode 85 and the source wiring 90, the organic film 120 preferably has a portion that directly covers the exposed portion of the first inorganic film 75 between the source electrode 85 and the outer covering 113. The organic film 120 preferably has a portion that directly covers the exposed portion of the first inorganic film 75 between the source electrode 85 and the outer covering 113. These configurations suppress peeling of the organic film 120, and at the same time, the increased creepage distance suppresses the intrusion of moisture (water).

[0482] The first inner covering portion 111 preferably exposes the inner portion of the source electrode 85. With this configuration, the inner portion of the source electrode 85 is used as an end to which a potential is applied. The organic film 120 may expose the edge of the first inner covering portion 111 on the inner portion side of the source electrode 85. The source wiring 90 may be electrically connected to the source electrode 85. The source wiring 90 may be drawn out from the source electrode 85. The source wiring 90 may be the outermost wiring.

[0483] The semiconductor device 1 may include a gate wiring 100 (second wiring) disposed on the first inorganic film 75 in a region between the source electrode 85 and the source wiring 90. The gate wiring 100 is electrically isolated from the source wiring 90. The organic film 120 may cover the gate wiring 100. With this configuration, the organic film 120 protects the gate wiring 100.

[0484] The outer coating portion 113 may cover the gate wiring 100. In this case, the organic film 120 may cover the gate wiring 100 with the outer coating portion 113 sandwiched therebetween. According to this configuration, the outer coating portion 113 prevents moisture (water) from contacting the gate wiring 100. This prevents oxidation of the gate wiring 100.

[0485] The outer coating portion 113 may cover the entire area of ​​the gate wiring 100 in a cross-sectional view. In this case, the organic film 120 may cover the entire area of ​​the gate wiring 100, sandwiching the outer coating portion 113 in a cross-sectional view. According to this configuration, oxidation of the gate wiring 100 is appropriately suppressed over the entire area of ​​the gate wiring 100.

[0486] The first inorganic film 75 may have an anchor opening 83. In this case, the second inorganic film 110 may have a portion positioned within the anchor opening 83. According to this configuration, the adhesion of the second inorganic film 110 to the first inorganic film 75 is increased by the anchor opening 83. This prevents the second inorganic film 110 from peeling off from the first inorganic film 75. Furthermore, since the creeping distance is increased by the anchor opening 83, the intrusion of moisture (water) is prevented.

[0487] The organic film 120 may cover a portion of the second inorganic film 110 that covers the anchor opening 83. According to this configuration, the adhesion of the organic film 120 to the second inorganic film 110 is increased by the unevenness of the second inorganic film 110 caused by the anchor opening 83. This suppresses peeling of the organic film 120 from the second inorganic film 110.

[0488] The semiconductor device 1 may include a chip 2. The first inorganic film 75 may be formed on the chip 2. The semiconductor device 1 may include an active region 12 provided in the inner part of the chip 2 and an outer periphery region 19 provided on the periphery of the chip 2. In this case, the first inorganic film 75 may cover both the active region 12 and the outer periphery region 19. The source electrode 85 may be arranged on the active region 12. The source wiring 90 may be arranged on the outer periphery region 19.

[0489] The electric field on the peripheral region 19 side is likely to be higher than the electric field on the active region 12 side. Therefore, a higher electric field may be concentrated on the source wiring 90 on the peripheral region 19 side than on the source electrode 85 side. Therefore, if moisture (water) enters from the peripheral region 19 side, the risk of oxidation is higher for the source wiring 90 than for the source electrode 85. Therefore, a configuration in which the source wiring 90 is protected by the outer coating 113 is particularly effective in a configuration in which the source wiring 90 is disposed in the peripheral region 19.

[0490] The chip 2 preferably contains SiC. With this configuration, the semiconductor device 1 is provided as a SiC semiconductor device. The SiC semiconductor device exhibits excellent electrical characteristics and durability even in harsh usage environments.

[0491] From another perspective, the semiconductor device 1 (electronic component) includes a source electrode 85 (terminal electrode), a source wiring 90 (wiring), an insulating second inorganic film 110 (inorganic film), and an insulating organic film 120. The source wiring 90 is disposed around the source electrode 85. The second inorganic film 110 covers the source wiring 90 with a gap between it and the source electrode 85. The organic film 120 has a portion that directly covers the source electrode 85 and a portion that covers the source wiring 90 with the second inorganic film 110 sandwiched therebetween.

[0492] This configuration provides a semiconductor device 1 having a novel layout. For example, in the semiconductor device 1, peeling of the second inorganic film 110 caused by stress of the source electrode 85 is suppressed, and oxidation of the source wiring 90 is suppressed by the second inorganic film 110. In addition, both the source electrode 85 and the source wiring 90 are protected by the organic film 120.

[0493] From another perspective, the semiconductor device 1 (electronic component) includes a first region (12), a second region (19), a source electrode 85 (terminal electrode), a source wiring 90 (wiring), an insulating second inorganic film 110 (inorganic film), and an insulating organic film 120. The first region (12) has a first electric field. The second region (19) has a second electric field around the first region (12) that is higher than the first electric field. In this embodiment, the active region 12 is exemplified as one aspect of the first region (12), and the peripheral region 19 is exemplified as one aspect of the second region (19).

[0494] The source electrode 85 is disposed in the first region (12). The source wiring 90 is disposed in the second region (19) around the source wiring 90. The second inorganic film 110 exposes the source electrode 85 and covers the source wiring 90. The organic film 120 has a portion that directly covers the source electrode 85 and a portion that covers the source wiring 90 with the second inorganic film 110 sandwiched therebetween.

[0495] This configuration provides a semiconductor device 1 having a novel layout. For example, the semiconductor device 1 suppresses peeling of the second inorganic film 110 due to stress of the source electrode 85, and the second inorganic film 110 suppresses oxidation of the source wiring 90. In particular, the semiconductor device 1 suppresses moisture (moisture) and oxidation reactions of the source wiring 90 due to the second electric field near the source wiring 90. Furthermore, both the source electrode 85 and the source wiring 90 are protected by the organic film 120.

[0496] From another perspective, the semiconductor device 1 includes a chip 2, an active region 12, a peripheral region 19, a transistor structure Tr (device structure), an outer well region 70 (impurity region), a source electrode 85 (electrode), a source wiring 90 (wiring), an insulating second inorganic film 110, and an insulating organic film 120.

[0497] The chip 2 has a first main surface 3. An active region 12 is provided in an inner portion of the first main surface 3. An outer peripheral region 19 is provided in a peripheral portion of the first main surface 3. A transistor structure Tr is formed on the first main surface 3 in the active region 12. An outer well region 70 is formed in a surface layer portion of the first main surface 3 in the outer peripheral region 19.

[0498] The source electrode 85 is disposed on the first main surface 3 in the active region 12 and is electrically connected to the transistor structure Tr. The source wiring 90 is disposed on the first main surface 3 in the peripheral region 19 and is electrically connected to the outer well region 70. The second inorganic film 110 exposes the source electrode 85 and covers the source wiring 90. The organic film 120 has a portion that directly covers the source electrode 85 and a portion that covers the source wiring 90 with the second inorganic film 110 sandwiched therebetween.

[0499] This configuration provides a semiconductor device 1 having a novel layout. For example, the semiconductor device 1 suppresses peeling of the second inorganic film 110 due to stress of the source electrode 85, and the second inorganic film 110 suppresses oxidation of the source wiring 90. In particular, the semiconductor device 1 suppresses moisture (moisture) and oxidation reactions of the source wiring 90 due to an electric field near the source wiring 90. Furthermore, both the source electrode 85 and the source wiring 90 are protected by the organic film 120.

[0500] Here, the relationship between the source electrode 85 and the source wiring 90 has been described, but the source electrode 85 may be replaced with the gate electrode 95 , and the source wiring 90 may be replaced with the gate wiring 100 .

[0501] That is, from another perspective, the semiconductor device 1 (electronic component) includes an insulating first inorganic film 75 (object to be covered), a gate electrode 95 (electrode), a gate wiring 100 (wiring), an insulating second inorganic film 110 (inorganic film), and an insulating organic film 120. The gate electrode 95 is disposed on the first inorganic film 75, and has a second electrode sidewall 97 on the first inorganic film 75. The gate wiring 100 is disposed around the gate electrode 95 on the first inorganic film 75.

[0502] The second inorganic film 110 has a second inner coating portion 112 that covers the gate electrode 95 so as to expose the second electrode sidewall 97, and an outer coating portion 113 that covers the gate wiring 100 at a distance from the second inner coating portion 112. The organic film 120 spans the second inner coating portion 112 and the outer coating portion 113, and covers the gate electrode 95 between the second inner coating portion 112 and the outer coating portion 113.

[0503] This configuration provides a semiconductor device 1 having a novel layout. For example, the semiconductor device 1 suppresses peeling of the second inorganic film 110 due to stress of the gate electrode 95, and the second inorganic film 110 suppresses oxidation of the gate wiring 100. Furthermore, both the gate electrode 95 and the gate wiring 100 are protected by the organic film 120.

[0504] From another perspective, the semiconductor device 1 (electronic component) includes an insulating first inorganic film 75 (object to be covered), a source electrode 85 (electrode), a gate wiring 100 (wiring), an insulating second inorganic film 110 (inorganic film), and an insulating organic film 120. The source electrode 85 is disposed on the first inorganic film 75 and has a first electrode sidewall 87 on the first inorganic film 75. The gate wiring 100 is disposed on the first inorganic film 75 around the source electrode 85.

[0505] The second inorganic film 110 has a first inner coating portion 111 that covers the source electrode 85 so as to expose the first electrode sidewall 87, and an outer coating portion 113 that covers the gate wiring 100 at a distance from the first inner coating portion 111. The organic film 120 spans the first inner coating portion 111 and the outer coating portion 113, and covers the source electrode 85 between the first inner coating portion 111 and the outer coating portion 113.

[0506] This configuration provides a semiconductor device 1 having a novel layout. For example, the semiconductor device 1 suppresses peeling of the second inorganic film 110 due to stress of the source electrode 85, and the second inorganic film 110 suppresses oxidation of the gate wiring 100. Furthermore, both the source electrode 85 and the gate wiring 100 are protected by the organic film 120.

[0507] From another perspective, the semiconductor device 1 (electronic component) includes an insulating first inorganic film 75 (object to be covered), a gate electrode 95 (electrode), a source wiring 90 (wiring), an insulating second inorganic film 110 (inorganic film), and an insulating organic film 120. The gate electrode 95 is disposed on the first inorganic film 75, and has a second electrode sidewall 97 on the first inorganic film 75. The source wiring 90 is disposed around the gate electrode 95 on the first inorganic film 75.

[0508] The second inorganic film 110 has a second inner coating portion 112 that covers the gate electrode 95 so as to expose the second electrode sidewall 97, and an outer coating portion 113 that covers the source wiring 90 at a distance from the second inner coating portion 112. The organic film 120 spans the second inner coating portion 112 and the outer coating portion 113, and covers the gate electrode 95 between the second inner coating portion 112 and the outer coating portion 113.

[0509] This configuration provides a semiconductor device 1 having a novel layout. For example, in the semiconductor device 1, peeling of the second inorganic film 110 due to stress of the gate electrode 95 is suppressed, and oxidation of the source wiring 90 is suppressed by the second inorganic film 110. In addition, both the gate electrode 95 and the source wiring 90 are protected by the organic film 120.

[0510] 22A to 22R, second to nineteenth layout examples of the second inorganic film 110 are shown below. FIGS. 22A to 22G are cross-sectional views showing second to sixth layout examples of the second inorganic film 110. FIGS. 22F to 22H are enlarged plan views showing seventh to ninth layout examples of the second inorganic film 110. FIGS. 22I to 22R are cross-sectional views showing tenth to nineteenth layout examples of the second inorganic film 110.

[0511] The semiconductor device 1 can include the features of any one of the second inorganic films 110 according to the first to nineteenth layout examples. Of course, the features of the second inorganic films 110 according to the first to nineteenth layout examples can be combined as appropriate. Therefore, the semiconductor device 1 can simultaneously include at least two of the features of the second inorganic films 110 according to the first to nineteenth layout examples in the same or different regions.

[0512] 22A (second layout example), the second inorganic film 110 may have an outer covering portion 113 that exposes the second inner sidewall 102 of the gate wiring 100 and covers the second wiring surface 101 of the gate wiring 100 and the second outer sidewall 103 of the gate wiring 100. The outer covering portion 113 may have an inner edge portion located on the second wiring surface 101 of the gate wiring 100.

[0513] In this embodiment, the organic film 120 has a portion that directly covers the first inorganic film 75 in the region (first removed portion 114a) between the source electrode 85 and the gate wiring 100. The organic film 120 directly covers the second inner sidewall 102 of the gate wiring 100, and covers the second outer sidewall 103 of the gate wiring 100 with the outer coating portion 113 in between. In this embodiment, the organic film 120 has a portion that directly covers the second wiring surface 101 of the gate wiring 100, and a portion that covers the second wiring surface 101 of the gate wiring 100 with the outer coating portion 113 in between.

[0514] 22B (third layout example), the second inorganic film 110 may have an outer covering portion 113 that exposes the entire area of ​​the gate wiring 100. The outer covering portion 113 may have an inner edge portion located in a region between the source wiring 90 and the gate wiring 100. The inner edge portion of the outer covering portion 113 may cover the first inorganic film 75 at a distance from the second outer wall 103 of the gate wiring 100 toward the source wiring 90.

[0515] In this embodiment, the organic film 120 has a portion in the first removed portion 114a that directly covers the second wiring surface 101, the second inner wall 102, and the second outer wall 103 of the gate wiring 100. In this embodiment, the organic film 120 has a portion that directly covers the first inorganic film 75 in the region between the source wiring 90 and the gate wiring 100, and a portion that covers the first inorganic film 75 with the second inorganic film 110 sandwiched therebetween.

[0516] 22C (fourth layout example), the second inorganic film 110 may have an outer covering portion 113 that exposes the first inner sidewall 92 of the source wiring 90 and covers the first wiring surface 91 of the source wiring 90 and the first outer sidewall 93 of the source wiring 90. The outer covering portion 113 may have an inner edge portion located on the first wiring surface 91 of the source wiring 90. The inner edge portion of the outer covering portion 113 may face the first surface portion 8 with the source wiring 90 interposed therebetween.

[0517] In this embodiment, the organic film 120 directly covers the second wiring surface 101, the second inner wall 102, and the second outer wall 103 of the gate wiring 100 in the first removed portion 114a. The organic film 120 directly covers the first inorganic film 75 in the region between the source wiring 90 and the gate wiring 100.

[0518] The organic film 120 directly covers the first inner sidewall 92 of the source wiring 90, and covers the first outer sidewall 93 of the source wiring 90 with the outer coating portion 113 in between. In this embodiment, the organic film 120 has a portion that directly covers the first wiring surface 91 of the source wiring 90, and a portion that covers the first wiring surface 91 of the gate wiring 100 with the outer coating portion 113 in between.

[0519] Referring to Figure 22D (fifth layout example), the second inorganic film 110 may have an outer coating portion 113 that exposes the first inner wall 92 of the source wiring 90 and covers the first wiring surface 91 of the source wiring 90 and the first outer wall 93 of the source wiring 90.

[0520] The outer covering portion 113 may have an inner edge portion located on the first wiring surface 91 of the source wiring 90. The inner edge portion of the outer covering portion 113 may face the second surface portion 9 across the source wiring 90. The inner edge portion of the outer covering portion 113 may be located closer to the first outer wall 93 than the outer opening 81, or may be located closer to the first inner wall 92 than the outer opening 81.

[0521] In this embodiment, the organic film 120 directly covers the second wiring surface 101, the second inner wall 102, and the second outer wall 103 of the gate wiring 100 in the first removed portion 114a. The organic film 120 directly covers the first inorganic film 75 in the region between the source wiring 90 and the gate wiring 100.

[0522] The organic film 120 directly covers the first inner sidewall 92 of the source wiring 90, and covers the first outer sidewall 93 of the source wiring 90 with the outer coating portion 113 in between. In this embodiment, the organic film 120 has a portion that directly covers the first wiring surface 91 of the source wiring 90, and a portion that covers the first wiring surface 91 of the gate wiring 100 with the outer coating portion 113 in between.

[0523] Referring to Figure 22E (sixth layout example), the second inorganic film 110 may have an outer covering portion 113 that is spaced apart from the first inner covering portion 111 and covers the first electrode side wall 87 of the source electrode 85.

[0524] In this case, the outer covering portion 113 may have an inner edge portion located on the peripheral edge portion of the first electrode surface 86 of the source electrode 85. The outer covering portion 113 may expose the peripheral edge portion of the first electrode surface 86 of the source electrode 85 together with the first inner covering portion 111. The first removed portion 114a may expose only the peripheral edge portion of the first electrode surface 86 of the source electrode 85.

[0525] In this embodiment, the organic film 120 covers the first electrode sidewall 87 of the source electrode 85, sandwiching the outer covering portion 113. The organic film 120 has a portion that covers the peripheral portion of the first electrode surface 86 of the source electrode 85, sandwiching the outer covering portion 113. The organic film 120 has a portion that directly covers the portion of the peripheral portion of the first electrode surface 86 that is exposed from the first inner covering portion 111 and the outer covering portion 113. The organic film 120 may directly cover only the peripheral portion of the first electrode surface 86 in the first removed portion 114a.

[0526] 22F (seventh layout example), the second inorganic film 110 may have one or more first openings 131 formed in the first inner covering portion 111 so as to expose the first electrode surface 86 of the source electrode 85. The multiple first openings 131 may be formed at intervals along the extension direction of the first inner covering portion 111. The multiple first openings 131 may be defined in a strip-like, quadrangular, rectangular, polygonal, circular, or other shape in plan view.

[0527] Similarly, the second inorganic film 110 may have one or more second openings 132 formed in the second inner covering portion 112 so as to expose the second electrode surface 96 of the gate electrode 95. The multiple second openings 132 may be formed at intervals along the extension direction of the second inner covering portion 112. The multiple second openings 132 may be defined in a strip-like, quadrangular, rectangular, polygonal, circular, or other shape in plan view.

[0528] In this embodiment, the organic film 120 penetrates the plurality of first openings 131 from above the first inner covering portion 111 and is connected to the first electrode surface 86 of the source electrode 85 within the plurality of first openings 131. The adhesion of the organic film 120 to the first inner covering portion 111 (second inorganic film 110) is increased by the plurality of first openings 131.

[0529] Similarly, organic film 120 penetrates into the multiple second openings 132 from above second inner covering portion 112 and is connected to second electrode surface 96 of gate electrode 95 within the multiple second openings 132. The adhesion of organic film 120 to second inner covering portion 112 (second inorganic film 110) is increased by the multiple second openings 132.

[0530] Referring to Figure 22G (eighth layout example), the second inorganic film 110 may have a plurality of first inner covering portions 111 arranged at intervals from the first electrode side wall 87 side of the source electrode 85 to the inner side of the source electrode 85.

[0531] The first inner covering portion 111 disposed on the inner side of the source electrode 85 defines the first pad opening 116. The multiple first inner covering portions 111 may each be formed in the shape of a strip with edges or a strip without edges extending along the first electrode sidewall 87 of the source electrode 85. The multiple first inner covering portions 111 may each be formed in the shape of a ring surrounding the inner portion of the source electrode 85.

[0532] Similarly, the second inorganic film 110 may have a plurality of second inner covering portions 112 arranged at intervals from the second electrode sidewall 97 side of the gate electrode 95 toward the inward side of the gate electrode 95. The second inner covering portion 112 arranged on the inward side of the source electrode 85 defines a second pad opening 117. The plurality of second inner covering portions 112 may each be formed in the shape of a strip with edges or a strip without edges extending along the second electrode sidewall 97 of the gate electrode 95. The plurality of second inner covering portions 112 may each be formed in the shape of a ring surrounding the inner portion of the gate electrode 95.

[0533] In this embodiment, the organic film 120 extends from above the multiple first inner coating portions 111 into the regions (openings) between the multiple first inner coating portions 111, and is connected to the first electrode surface 86 of the source electrode 85 in the regions between the multiple first inner coating portions 111. The adhesion of the organic film 120 to the first inner coating portion 111 (second inorganic film 110) is increased by the multiple first inner coating portions 111.

[0534] Similarly, in this embodiment, the organic film 120 extends from above the multiple second inner coating portions 112 into the regions (openings) between the multiple second inner coating portions 112, and is connected to the second electrode surface 96 of the gate electrode 95 in the regions between the multiple second inner coating portions 112. The adhesion of the organic film 120 to the second inner coating portion 112 (second inorganic film 110) is increased by the multiple second inner coating portions 112.

[0535] 22H (ninth layout example), second inorganic film 110 may have a plurality of first inner covering portions 111 arranged at intervals along first electrode sidewall 87 of source electrode 85. The plurality of first inner covering portions 111 may be formed in a strip-like, quadrangular, rectangular, polygonal, circular, or other shape in plan view.

[0536] Similarly, the second inorganic film 110 may have a plurality of second inner covering portions 112 arranged at intervals along the second electrode sidewall 97 of the gate electrode 95. The plurality of second inner covering portions 112 may be formed in a strip-like, quadrangular, rectangular, polygonal, circular, or other shape in plan view.

[0537] In this embodiment, the organic film 120 extends from above the multiple first inner coating portions 111 into the regions (openings) between the multiple first inner coating portions 111, and is connected to the first electrode surface 86 of the source electrode 85 in the regions between the multiple first inner coating portions 111. The adhesion of the organic film 120 to the first inner coating portion 111 (second inorganic film 110) is increased by the multiple first inner coating portions 111.

[0538] Similarly, in this embodiment, the organic film 120 extends from above the multiple second inner coating portions 112 into the regions (openings) between the multiple second inner coating portions 112, and is connected to the second electrode surface 96 of the gate electrode 95 in the regions between the multiple second inner coating portions 112. The adhesion of the organic film 120 to the second inner coating portion 112 (second inorganic film 110) is increased by the multiple second inner coating portions 112.

[0539] 22I (tenth layout example), second inorganic film 110 may have outer covering portion 113 exposed from at least one (for example, all) of first to fourth side surfaces 5A to 5D. Outer covering portion 113 may be formed flush with at least one (for example, all) of first to fourth side surfaces 5A to 5D.

[0540] 22J (eleventh layout example), the second inorganic film 110 may have an outer covering portion 113 positioned inward from the outer edge of the organic film 120. In other words, the organic film 120 may protrude outward from the outer edge of the outer covering portion 113.

[0541] 22K (twelfth layout example), the second inorganic film 110 may have an outer covering portion 113 located inside the organic film 120. In other words, the organic film 120 may cover the outer edge of the outer covering portion 113.

[0542] 22L (thirteenth layout example), the first inorganic film 75 may have a cutout portion 133 formed at a distance inward from at least one (for example, all) of the first to fourth side surfaces 5A to 5D, and exposing the peripheral edge portion (second semiconductor region 7) of the second surface portion 9. In this case, the second inorganic film 110 may have an outer covering portion 113 having an outer edge portion disposed on the first inorganic film 75 at a distance inward from the cutout portion 133.

[0543] 22M (fourteenth layout example), the first inorganic film 75 may have a cutout portion 133, as in the case of the thirteenth layout example. In this case, the second inorganic film 110 may have an outer covering portion 113 that extends from above the first inorganic film 75 into the cutout portion 133 and has a portion that directly covers the peripheral edge portion of the second surface portion 9 within the cutout portion 133. The outer covering portion 113 may be formed at a distance inward from at least one (for example, all) of the first to fourth side surfaces 5A to 5D.

[0544] 22N (15th layout example), the second inorganic film 110 may have an outer covering portion 113 positioned within the cutout portion 133, as in the case of the 14th layout example. The outer covering portion 113 may be exposed from at least one (for example, all) of the first to fourth side surfaces 5A to 5D. The outer covering portion 113 may be formed flush with at least one (for example, all) of the first to fourth side surfaces 5A to 5D.

[0545] 22O (sixteenth layout example), second inorganic film 110 may have first inner covering portion 111 positioned inward from the inner edge of organic film 120. In other words, organic film 120 may extend inward from the inner edge of first inner covering portion 111 toward the source electrode 85 (first electrode surface 86).

[0546] The wall surface of the first upper pad opening 121 may be located closer to the inside of the first electrode surface 86 than the wall surface of the first pad opening 116. The wall surface of the first upper pad opening 121 may be formed at a distance from the first electrode surface 86 in the stacking direction.

[0547] Similarly, the second inorganic film 110 may have a second inner covering portion 112 positioned inward from the inner edge of the organic film 120. In other words, the organic film 120 may protrude inward from the gate electrode 95 (second electrode surface 96) beyond the inner edge of the second inner covering portion 112.

[0548] The wall surface of the second upper pad opening 122 may be located closer to the inner side of the second electrode surface 96 than the wall surface of the second pad opening 117. The wall surface of the second upper pad opening 122 may be formed at a distance from the second electrode surface 96 in the stacking direction.

[0549] 22P (17th layout example), the second inorganic film 110 may have a first inner covering portion 111 located inside the organic film 120. In other words, the organic film 120 may cover the inner edge portion of the first inner covering portion 111. In this case, the organic film 120 may cover the entire area of ​​the first inner covering portion 111.

[0550] The organic film 120 may directly cover the source electrode 85 (first electrode surface 86) in a region that is more inward than the inner edge of the first inner covering portion 111. The wall surface of the first upper pad opening 121 may be positioned more inward of the first electrode surface 86 than the wall surface of the first pad opening 116. The wall surface of the first upper pad opening 121 may directly cover the first electrode surface 86 in a region that is more inward than the inner edge of the first inner covering portion 111.

[0551] Similarly, the second inorganic film 110 may have a second inner coating portion 112 located inside the organic film 120. That is, the organic film 120 may cover the inner edge portion of the second inner coating portion 112. In this case, the organic film 120 may cover the entire area of ​​the second inner coating portion 112.

[0552] The organic film 120 may directly cover the gate electrode 95 (second electrode surface 96) in a region that is more inward than the inner edge of the second inner covering portion 112. The wall surface of the second upper pad opening 122 may be positioned more inward of the second electrode surface 96 than the wall surface of the second pad opening 117. The wall surface of the second upper pad opening 122 may directly cover the second electrode surface 96 in a region that is more inward than the inner edge of the second inner covering portion 112.

[0553] 22Q (18th layout example), second inorganic film 110 does not necessarily have to have first inner covering portion 111, and the entire area of ​​source electrode 85 may be exposed. In this case, second inorganic film 110 is required to have at least outer covering portion 113. Second inorganic film 110 may or may not have second inner covering portion 112.

[0554] In this embodiment, the organic film 120 directly covers the peripheral edge of the first electrode surface 86 and the first electrode sidewall 87 at the peripheral edge of the source electrode 85 without going through the first inner covering portion 111. In other words, the wall surface of the first upper pad opening 121 may directly cover the peripheral edge of the first electrode surface 86.

[0555] 22R (19th layout example), the second inorganic film 110 does not necessarily have to have the second inner covering portion 112, and the entire area of ​​the gate electrode 95 may be exposed. In this case, it is sufficient that the second inorganic film 110 has at least the outer covering portion 113. The second inorganic film 110 may have the first inner covering portion 111, or may not have the first inner covering portion 111.

[0556] In this embodiment, the organic film 120 directly covers the peripheral edge of the second electrode surface 96 and the second electrode sidewall 97 at the peripheral edge of the source electrode 85 without the second inner covering portion 112. In other words, the wall surface of the second upper pad opening 122 may directly cover the peripheral edge of the second electrode surface 96.

[0557] The above-described embodiment (including variations) can be implemented in other embodiments. For example, in the above-described embodiment, the mesa 11 (the first surface 8, the second surface 9, and the first to fourth connecting surface portions 10A to 10D) is defined on the first main surface 3. However, the first main surface 3 does not necessarily have to have the mesa 11, and may be formed flat.

[0558] In this case, the outer well region 70 defines the active region 12 and the peripheral region 19. Also, in this case, the first side end region 13, the second side end region 14, the first termination region 15, the second termination region 16, the third termination region 17, and the fourth termination region 18 may be removed.

[0559] In the above embodiment, an example has been shown in which the anchor openings 83 are formed in the first inorganic film 75. However, a first inorganic film 75 that does not have the anchor openings 83 may also be employed.

[0560] In the above-described embodiment, an example has been shown in which the source wiring 90 is connected to the source electrode 85. However, the source wiring 90 may be electrically separated from the source electrode 85. In this case, the source wiring 90 may be formed in an electrically floating state as a floating wiring or a field wiring (a so-called field preplate).

[0561] In the above-described embodiments, a structure may be adopted in which the conductivity type of the “n-type” semiconductor region is inverted to “p-type” and the conductivity type of the “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0562] In the above-described embodiment, the chip 2 includes a SiC single crystal. However, the chip 2 may include a silicon single crystal. Similarly, the first semiconductor region 6 may include a silicon single crystal. Similarly, the second semiconductor region 7 may include a silicon single crystal.

[0563] In the above-described embodiment, a p-type collector region may be formed in a surface layer portion of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of the MISFET structure. A specific configuration in this case can be obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure in the above description. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0564] In the above-described embodiment, the first semiconductor region 6 (second semiconductor region 7) may be formed as part or all of the cathode region of a semiconductor rectifier (diode), and the body region 20 may be formed as part or all of the anode region of the semiconductor rectifier (diode). In this case, the source electrode 85 is formed as an anode electrode, and the drain electrode 125 is formed as a cathode electrode. Of course, instead of the body region 20 (anode region) and the source electrode 85, a Schottky electrode (anode electrode) that forms a Schottky junction with the second semiconductor region 7 may be employed.

[0565] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components of the aforementioned embodiments, but are not intended to limit the scope of each clause to the aforementioned embodiments. The "electronic component" in the following clauses may be replaced with "semiconductor device," "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," "semiconductor rectifier device," etc., as necessary.

[0566] [A1] A coating object (75), electrodes (85, 95) arranged on the coating object (75) and having electrode side walls (87, 97) on the coating object (75), wiring (90, 100) arranged around the electrodes (85, 95) on the coating object (75), inner coating parts (111, 112) that cover the electrodes (85, 95) so as to expose the electrode side walls (87, 97), and The electronic component (1) includes: an insulating inorganic film (110) having an outer coating portion (113) that covers the wiring (90, 100) at a distance from the inner coating portion (111, 112); and an insulating organic film (120) that spans the inner coating portion (111, 112) and the outer coating portion (113) and covers the electrodes (85, 95) between the inner coating portion (111, 112) and the outer coating portion (113).

[0567] [A2] The electronic component (1) according to A1, wherein the wiring (90, 100) has a wiring sidewall (93, 103) opposite the electrode (85, 95) in a cross-sectional view, the outer coating portion (113) covers the wiring sidewall (93, 103) of the wiring (90, 100) in a cross-sectional view, and the organic film (120) covers the wiring sidewall (93, 103) across the outer coating portion (113) in a cross-sectional view.

[0568] [A3] The electronic component (1) according to A2, wherein the outer coating portion (113) covers the entire area of ​​the wiring (90, 100) in a cross-sectional view, and the organic film (120) covers the entire area of ​​the wiring (90, 100) across the outer coating portion (113) in a cross-sectional view.

[0569] [A4] The electronic component (1) according to any one of A1 to A3, wherein the outer covering portion (113) exposes the electrode side walls (87, 97) in a cross-sectional view, and the organic film (120) has a portion that directly covers the electrode side walls (87, 97) in a cross-sectional view.

[0570] [A5] The electronic component (1) described in A4, wherein the inner covering portion (111, 112) covers the electrode (85, 95) at a distance from the electrode side wall (87, 97), and the outer covering portion (113) covers the object to be covered (75) at a distance from the electrode side wall (87, 97).

[0571] [A6] The electronic component (1) according to A5, wherein the inner covering portion (111, 112) exposes the peripheral portion of the electrode (85, 95), and the organic film (120) has a portion that directly covers the peripheral portion of the electrode (85, 95).

[0572] [A7] The electronic component (1) according to A5 or A6, wherein the organic film (120) has a portion that directly covers an exposed portion of the object to be covered (75) between the electrodes (85, 95) and the outer covering portion (113).

[0573] [A8] The electronic component (1) according to any one of A1 to A7, wherein the inner covering portion (111, 112) exposes the inner portion of the electrode (85, 95).

[0574] [A9] The electronic component (1) according to any one of A1 to A8, wherein the organic film (120) exposes the edge of the inner covering portion (111, 112) on the inner side of the electrode (85, 95).

[0575] [A10] The electronic component (1) according to any one of A1 to A9, wherein the wiring (90, 100) is electrically connected to the electrodes (85, 95).

[0576] [A11] The electronic component (1) according to any one of A1 to A10, wherein the wiring (90, 100) is drawn out from the electrodes (85, 95).

[0577] [A12] The electronic component (1) according to any one of A1 to A11, wherein the wiring (90, 100) is the outermost wiring (90).

[0578] [A13] The electronic component (1) according to any one of A1 to A12, wherein the electrode (85, 95) is a source electrode (85), and the wiring (90, 100) is a source wiring (90).

[0579] [A14] An electronic component (1) according to any one of A1 to A13, further comprising a chip (2), wherein the object to be coated (75) is formed on the chip (2).

[0580] [A15] An electronic component (1) according to A14, further comprising an active region (12) provided in the inner part of the chip (2) and an outer peripheral region (19) provided on the periphery of the chip (2), wherein the object to be covered (75) covers both the active region (12) and the outer peripheral region (19), the electrodes (85, 95) are arranged on the active region (12), and the wiring (90) is arranged on the outer peripheral region (19).

[0581] [A16] The electronic component (1) according to A14 or A15, wherein the chip (2) contains SiC.

[0582] [A17] The electronic component (1) according to any one of A1 to A16, further comprising a second wiring (100) disposed in a region between the electrode (85) and the wiring (90) on the object to be covered (75), and the organic film (120) covering the second wiring (100).

[0583] [A18] The electronic component (1) according to A17, wherein the outer coating portion (113) covers the second wiring (100), and the organic film (120) covers the second wiring (100) with the outer coating portion (113) sandwiched therebetween.

[0584] [B1] An electronic component (1) comprising: electrodes (85, 95) arranged in a first region (12) having a first electric field; wiring (90) arranged in a second region (19) having a second electric field higher than the first electric field around the electrodes (85, 95); an insulating inorganic film (110) exposing the electrodes (85, 95) and covering the wiring (90); and an insulating organic film (120) having a portion directly covering the electrodes (85, 95) and a portion covering the wiring (90) with the inorganic film (110) sandwiched therebetween.

[0585] [B2] The electronic component (1) according to B1, wherein the electrodes (85, 95) are terminal electrodes (85, 95).

[0586] [B3] The electronic component (1) according to B1 or B2, wherein the wiring (90) has a width smaller than the width of the electrodes (85, 95).

[0587] [B4] The electronic component (1) according to any one of B1 to B3, wherein the inorganic film (110) exposes the electrode side walls (87, 97) of the electrodes (85, 95).

[0588] [B5] The electronic component (1) according to B4, wherein the inorganic film (110) has inner covering portions (111, 112) that cover the electrodes (85, 95) at a distance from the electrode side walls (87, 97), and an outer covering portion (113) that covers the wiring (90) at a distance from the inner covering portions (111, 112), and the organic film (120) spans the inner covering portions (111, 112) and the outer covering portion (113) and covers the electrode side walls (87, 97) of the electrodes (85, 95) between the inner covering portions (111, 112) and the outer covering portion (113).

[0589] [B6] The electronic component (1) according to any one of B1 to B5, wherein the wiring (90) is at the same potential as the electrode (85).

[0590] [B7] The electronic component (1) according to any one of B1 to B6, wherein the wiring (90) is connected to the electrode (85).

[0591] [B8] An electronic component (1) according to any one of B1 to B7, further including a chip (2), wherein the first region (12) is formed in the chip (2), the second region (19) is formed around the first region (12) in the chip (2), the electrodes (85, 95) are arranged on the first region (12), and the wiring (90) is arranged on the second region (19).

[0592] [B9] An electronic component (1) according to B8, wherein the first region (12) is an active region (12), the second region (19) is a peripheral region (19) surrounding the active region (12), the electrodes (85, 95) are arranged on the active region (12), and the wiring (90) is arranged on the peripheral region (19).

[0593] [B10] The electronic component (1) according to B8 or B9, wherein the chip (2) contains SiC.

[0594] [C1] A chip (2) having a main surface (3), an active region (12) provided in the inner part of the main surface (3), an outer peripheral region (19) provided on the periphery of the main surface (3), a device structure (Tr) formed on the main surface (3) in the active region (12), an impurity region (70) formed in the surface layer of the main surface (3) in the outer peripheral region (19), and a device structure (Tr) disposed on the main surface (3) in the active region (12). an electrode (85) electrically connected to the impurity region (70); wiring (90) disposed on the main surface (3) in the peripheral region (19) and electrically connected to the impurity region (70); an insulating inorganic film (110) exposing the electrode (85) and covering the wiring (90); and an insulating organic film (120) having a portion directly covering the electrode (85) and a portion covering the wiring (90) with the inorganic film (110) sandwiched therebetween.

[0595] [C2] The electronic component (1) according to C2, wherein the conductivity type of the impurity region (70) is p-type.

[0596] [C3] The electronic component (1) according to C1 or C2, wherein the device structure (Tr) includes a MISFET structure.

[0597] [C4] The electronic component (1) according to C1 or C2, wherein the device structure (Tr) includes an IGBT structure.

[0598] [D1] An electronic component (1) comprising: a terminal electrode; wiring arranged around the terminal electrode; an insulating inorganic film covering the wiring at a distance from the terminal electrode; and an insulating organic film having a portion that directly covers the terminal electrode and a portion that covers the wiring with the inorganic film sandwiched therebetween.

[0599] [E1] An electronic component (1) comprising: an object to be covered (75); a gate electrode (95) disposed on the object to be covered (75) and having an electrode sidewall (97) on the object to be covered (75); a gate wiring (100) disposed around the gate electrode (95) on the object to be covered (75); an insulating inorganic film (110) having an inner coating portion (112) that covers the gate electrode (95) so as to expose the electrode sidewall (97), and an outer coating portion (113) that covers the gate wiring (100) at a distance from the inner coating portion (112); and an insulating organic film (120) that spans the inner coating portion (112) and the outer coating portion (113) and covers the gate electrode (95) between the inner coating portion (112) and the outer coating portion (113).

[0600] [F1] An electronic component (1) comprising: an object to be coated (75); a source electrode (85) disposed on the object to be coated (75) and having an electrode sidewall (87) on the object to be coated (75); a gate wiring (100) disposed around the source electrode (85) on the object to be coated (75); an insulating inorganic film (110) having an inner coating portion (112) that covers the source electrode (85) so as to expose the electrode sidewall (87) and an outer coating portion (113) that covers the gate wiring (100) at a distance from the inner coating portion (112); and an insulating organic film (120) that spans the inner coating portion (112) and the outer coating portion (113) and covers the source electrode (85) between the inner coating portion (112) and the outer coating portion (113).

[0601] [G1] An electronic component (1) comprising: an object to be covered (75); a gate electrode (95) arranged on the object to be covered (75) and having an electrode sidewall (97) on the object to be covered (75); a source wiring (90) arranged around the gate electrode (95) on the object to be covered (75); an insulating inorganic film (110) having an inner coating portion (111) that covers the gate electrode (95) so as to expose the electrode sidewall (97), and an outer coating portion (113) that covers the source wiring (90) at a distance from the inner coating portion (111); and an insulating organic film (120) that spans the inner coating portion (111) and the outer coating portion (113) and covers the gate electrode (95) between the inner coating portion (111) and the outer coating portion (113).

[0602] Although specific embodiments have been described in detail above, these are merely examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification or the order of the embodiment examples.

[0603] REFERENCE SIGNS LIST 1 semiconductor device (electronic component) 2 chip 3 first main surface 12 active region (first region) 19 peripheral region (second region) 70 outer well region (impurity region) 75 first inorganic film (covering target) 85 source electrode (electrode) 87 first electrode sidewall 90 source wiring (wiring) 93 first outer wall (wiring sidewall) 95 gate electrode (electrode) 97 second electrode sidewall 100 gate wiring (second wiring) 110 second inorganic film 111 first inner covering portion 112 second inner covering portion 113 outer covering portion 120 organic film Tr transistor structure (device structure)

Claims

1. a coating object; an electrode disposed on the object to be coated and having an electrode sidewall on the object to be coated; Wiring arranged around the electrode on the object to be covered; an insulating inorganic film having an inner covering portion that covers the electrode so as to expose the electrode sidewall, and an outer covering portion that covers the wiring at a distance from the inner covering portion; an insulating organic film that spans the inner coating portion and the outer coating portion and covers the electrode between the inner coating portion and the outer coating portion.

2. the wiring has a wiring sidewall on the opposite side to the electrode in a cross-sectional view, the outer covering portion covers the wiring sidewall of the wiring in a cross-sectional view, The electronic component according to claim 1 , wherein the organic film covers the wiring sidewalls with the outer coating portion sandwiched therebetween in a cross-sectional view.

3. the outer covering portion covers the entire wiring in a cross-sectional view, The electronic component according to claim 2 , wherein the organic film covers the entire wiring across the outer coating portion in a cross-sectional view.

4. the outer covering portion exposes the electrode side wall in a cross-sectional view, The electronic component according to claim 1 , wherein the organic film has a portion that directly covers the electrode side wall in a cross-sectional view.

5. the inner covering portion covers the electrode at a distance from the electrode side wall; The electronic component according to claim 4 , wherein the outer coating portion covers the object to be coated with a space therebetween from the electrode sidewall.

6. the inner covering portion exposes a peripheral edge portion of the electrode; 6. The electronic component according to claim 5, wherein the organic film has a portion that directly covers a peripheral edge of the electrode.

7. 6. The electronic component according to claim 5, wherein the organic film has a portion that directly covers an exposed portion of the object to be covered between the electrode and the outer coating portion.

8. The electronic component according to claim 1 , wherein the inner covering portion exposes an inner portion of the electrode.

9. 2. The electronic component according to claim 1, wherein the organic film exposes an edge of the inner covering portion on the inner side of the electrode.

10. The electronic component according to claim 1 , wherein the wiring is electrically connected to the electrode.

11. The electronic component according to claim 1 , wherein the wiring is drawn out from the electrode.

12. The electronic component according to claim 1 , wherein the wiring is an outermost wiring.

13. the electrode is a source electrode, The electronic component according to claim 1 , wherein the wiring is a source wiring.

14. Further comprising a chip, The electronic component according to any one of claims 1 to 13, wherein the object to be coated is formed on the chip.

15. an active region provided in an inner portion of the chip; an outer peripheral region provided on a peripheral edge of the chip, the coating target covers both the active region and the peripheral region; the electrode is disposed over the active region; The electronic component according to claim 14 , wherein the wiring is disposed on the outer periphery region.

16. The electronic component of claim 14 , wherein the chip comprises SiC.

17. a second wiring disposed on the object to be covered in a region between the electrode and the wiring; The electronic component according to any one of claims 1 to 13, wherein the organic film covers the second wiring.

18. the outer covering portion covers the second wiring, The electronic component according to claim 17 , wherein the organic film covers the second wiring with the outer coating portion sandwiched therebetween.

19. a terminal electrode; Wiring arranged around the terminal electrode; an insulating inorganic film covering the wiring at a distance from the terminal electrode; an insulating organic film having a portion that directly covers the terminal electrode and a portion that covers the wiring with the inorganic film sandwiched therebetween;

20. an electrode disposed in a first region having a first electric field; a wiring disposed in a second region around the electrode, the second region having a second electric field higher than the first electric field; an insulating inorganic film that exposes the electrodes and covers the wiring; an insulating organic film having a portion that directly covers the electrode and a portion that covers the wiring with the inorganic film sandwiched therebetween;