Semiconductor device

Abstract

A semiconductor device 1 comprises: a substrate 10 having an insulating surface 10a; a lower-portion electrode 21 provided on the insulating surface 10a; a dielectric film 22 provided on the lower-portion electrode 21; and an upper-portion electrode 30 provided on the dielectric film 22. In a cross-sectional view, the upper-portion electrode 30 has a protruding shape.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Patent Document 1 describes forming an MIM (Metal Insulator Metal) structure capacitor by sequentially forming an insulating film, a lower electrode, a dielectric film, an upper electrode, a protective film, and a terminal electrode on a substrate.

[0003] International Publication No. 2018 / 003445

[0004] In a capacitor with this structure, the thicker the upper electrode, the smaller the ESR (equivalent series resistance). However, a thick upper electrode increases processing variations, which in turn increases variations in the area of ​​the upper electrode, resulting in greater variations in capacitance. Therefore, there is a trade-off between ESR and capacitance variations. Semiconductor devices that can function as capacitors also face similar challenges.

[0005] The present invention has been made to solve the above problems, and has an object to provide a semiconductor device that can reduce both ESR and capacitance variations.

[0006] The semiconductor device of the present invention comprises a substrate having an insulating surface, a lower electrode provided on the insulating surface, a dielectric film provided on the lower electrode, and an upper electrode provided on the dielectric film, and in cross-sectional view, the upper electrode has a convex shape.

[0007] According to the present invention, it is possible to provide a semiconductor device that can reduce both ESR and capacitance variations.

[0008] FIG. 1 is a plan view schematically illustrating an example of a capacitor according to a first embodiment of the present invention. FIG. 2 is an example of a cross-sectional view of the capacitor shown in FIG. 1 taken along line A-A. FIG. 3A is a cross-sectional view schematically illustrating an example of a step of forming an insulating layer in the first embodiment. FIG. 3B is a cross-sectional view schematically illustrating an example of a step of forming a lower electrode in the first embodiment. FIG. 3C is a cross-sectional view schematically illustrating an example of a step of forming a dielectric film in the first embodiment. FIG. 3D is a cross-sectional view schematically illustrating an example of a step of forming a metal film for an upper electrode in the first embodiment. FIG. 3E is a cross-sectional view schematically illustrating an example of a first step of processing a metal film for an upper electrode in the first embodiment. FIG. 3F is a cross-sectional view schematically illustrating an example of a second step of processing a metal film for an upper electrode in the first embodiment. FIG. 3G is a cross-sectional view schematically illustrating an example of a step of forming a via in a dielectric film in the first embodiment. FIG. 3H is a cross-sectional view schematically illustrating an example of a step of forming a protective layer in the first embodiment. FIG. 3I is a cross-sectional view schematically illustrating an example of a step of forming an external electrode in the first embodiment. FIG. 4 is a cross-sectional view schematically showing an example of a capacitor according to embodiment 2 of the present invention. FIG. 5A is a cross-sectional view schematically showing an example of a step of forming an insulating layer according to embodiment 2. FIG. 5B is a cross-sectional view schematically showing an example of a step of forming a lower electrode according to embodiment 2. FIG. 5C is a cross-sectional view schematically showing an example of a step of forming a dielectric film according to embodiment 2. FIG. 5D is a cross-sectional view schematically showing an example of a step of forming a lower layer of an upper electrode according to embodiment 2. FIG. 5E is a cross-sectional view schematically showing an example of a step of forming an upper layer of an upper electrode according to embodiment 2. FIG. 5F is a cross-sectional view schematically showing an example of a step of forming a via in a dielectric film according to embodiment 2. FIG. 5G is a cross-sectional view schematically showing an example of a step of forming a protective layer according to embodiment 2. FIG. 5H is a cross-sectional view schematically showing an example of a step of forming an external electrode according to embodiment 2. FIG. 6 is a cross-sectional view schematically showing an example of a capacitor according to embodiment 3 of the present invention. FIG. 7A is a cross-sectional view schematically showing an example of a step of forming an insulating layer according to embodiment 3. FIG. 7B is a cross-sectional view schematically showing an example of a step of forming a lower electrode according to embodiment 3.FIG. 7C is a cross-sectional view schematically showing an example of a step of forming a dielectric film in embodiment 3. FIG. 7D is a cross-sectional view schematically showing an example of a step of forming a lower layer of an upper electrode in embodiment 3. FIG. 7E is a cross-sectional view schematically showing an example of a step of forming an upper layer of an upper electrode in embodiment 3. FIG. 7F is a cross-sectional view schematically showing an example of a step of forming a via in a dielectric film in embodiment 3. FIG. 7G is a cross-sectional view schematically showing an example of a step of forming a protective layer in embodiment 3. FIG. 7H is a cross-sectional view schematically showing an example of a step of forming an external electrode in embodiment 3. FIG. 8 is a cross-sectional view schematically showing an example of a capacitor according to embodiment 4 of the present invention. FIG. 9A is a cross-sectional view schematically showing an example of a step of forming an insulating layer in embodiment 4. FIG. 9B is a cross-sectional view schematically showing an example of a step of forming a lower electrode in embodiment 4. FIG. 9C is a cross-sectional view schematically showing an example of a step of forming a dielectric film in embodiment 4. FIG. 9D is a cross-sectional view schematically showing an example of a step of forming a metal film for an upper electrode in embodiment 4. 9E is a cross-sectional view schematically showing an example of a first step of processing a metal film for an upper electrode in embodiment 4. FIG. 9F is a cross-sectional view schematically showing an example of a second step of processing a metal film for an upper electrode in embodiment 4. FIG. 9G is a cross-sectional view schematically showing an example of a third step of processing a metal film for an upper electrode in embodiment 4. FIG. 9H is a cross-sectional view schematically showing an example of a step of forming a via in a dielectric film in embodiment 4. FIG. 9I is a cross-sectional view schematically showing an example of a step of forming a protective layer in embodiment 4. FIG. 9J is a cross-sectional view schematically showing an example of a step of forming an external electrode in embodiment 4. FIG. 10 is a cross-sectional view schematically showing an example of a capacitor according to embodiment 5 of the present invention.

[0009] The semiconductor device of the present invention will be described below. However, the present invention is not limited to the following configuration, and can be appropriately modified and applied within the scope of the present invention. Note that a combination of two or more of the individual desirable configurations described below also constitutes the present invention.

[0010] The following embodiments are merely examples, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. From embodiment 2 onwards, descriptions of matters common to embodiment 1 will be omitted, and differences will be mainly described. In particular, similar effects resulting from similar configurations will not be mentioned one after the other for each embodiment.

[0011] In the following description, unless otherwise specified, each embodiment will be referred to simply as the "semiconductor device of the present invention." The shape and arrangement of the semiconductor device and each component of the present invention are not limited to the examples shown in the drawings.

[0012] In the following, a capacitor will be described as an example of one embodiment of the semiconductor device of the present invention. The semiconductor device of the present invention may be a capacitor itself or a device including a capacitor.

[0013] (Embodiment 1) A capacitor according to embodiment 1 of the present invention will be described. Fig. 1 is a plan view schematically showing an example of a capacitor according to embodiment 1 of the present invention. Fig. 2 is an example of a cross-sectional view taken along line AA of the capacitor shown in Fig. 1.

[0014] The capacitor 1 shown in FIGS. 1 and 2 comprises a substrate 10 having an insulating surface (main surface) 10 a, a lower electrode 21 provided on the insulating surface 10 a, a dielectric film 22 provided on the lower electrode 21, and an upper electrode 30 provided on the dielectric film 22.

[0015] Here, the substrate 10 has a semiconductor substrate 11 and an insulating layer 12 provided on the semiconductor substrate 11, but if the substrate 10 is an insulating substrate such as glass or alumina, the insulating layer 12 can be omitted.

[0016] The capacitor 1 further includes a protective layer 23 provided on the dielectric film 22 and the upper electrode 30, and external electrodes 24 that penetrate the protective layer 23. The external electrodes 24 include a first external electrode 24A connected to the lower electrode 21 and a second external electrode 24B connected to the upper electrode 30. The first external electrode 24A penetrates the protective layer 23 and the dielectric film 22, and the second external electrode 24B penetrates the protective layer 23.

[0017] The capacitor 1 may further include a moisture-resistant film (not shown) provided on the dielectric film 22 and the upper electrode 30 .

[0018] In the capacitor 1, a lower electrode 21, a dielectric film 22, and an upper electrode 30 are stacked in this order to form an MIM capacitor structure. By applying a voltage between the lower electrode 21 and the upper electrode 30, electric charges can be stored in the dielectric film 22.

[0019] 2, the upper electrode 30 has a convex shape in cross section. Therefore, a capacitor with small capacitance variation and small ESR can be realized. More specifically, the capacitance is determined by processing a thin film that becomes the lower portion 30A of the upper electrode 30, so its variation is small. Furthermore, the ESR can be reduced because the upper portion 30B of the upper electrode 30 exists and the upper electrode 30 can be made thicker.

[0020] In this specification, the term "convex shape" refers to a shape having a lower portion and an upper portion disposed on the lower portion, with the entire upper portion existing inside the lower portion in a plan view. Therefore, the end surface of the upper portion is not particularly limited to a flat surface such as a vertical surface (see FIG. 2), but may be an uneven surface. For example, the end of the upper portion may have an overhanging shape (see FIG. 10, which will be described later).

[0021] In this specification, the side closer to the substrate is referred to as "bottom" and the side farther from the substrate is referred to as "top."

[0022] 1, the substrate 10, the lower electrode 21, and the upper electrode 30 are all rectangular in plan view. In plan view, the lower electrode 21 is formed within the region of the substrate 10, and the upper electrode 30 is formed within the formation region of the lower electrode 21.

[0023] 1, the lower portion 30A and the upper portion 30B of the upper electrode 30 are both rectangular. In plan view, the upper portion 30B is formed within the formation region of the lower portion 30A. That is, in plan view, the lower portion 30A protrudes from the upper portion 30B in a frame-like manner around the entire periphery of the upper portion 30B. Thus, the lower portion 30A is composed of a fringe portion (brim-shaped portion) that protrudes from the upper portion 30B around the entire periphery and a central portion that is located at the same height as the fringe portion, and the upper portion 30B corresponds to the portion of the upper electrode 30 excluding the lower portion 30A.

[0024] The dimensions (in-plane dimensions) of the lower portion 30A and the upper portion 30B of the upper electrode 30 are not particularly limited. For example, the dimensions of the lower portion 30A can be set according to the desired capacitance value of the capacitor 1. The length of each side of the upper portion 30B may be, for example, 50% to 99% of the length of the corresponding side (adjacent side) of the lower portion 30A, but is preferably 90% to 99% of the length of the corresponding side (adjacent side) of the lower portion 30A.

[0025] 2, the upper electrode 30 is made of a single layer. That is, the upper portion 30B of the upper electrode 30 and the lower portion 30A of the upper electrode 30 are made of the same material, and there is no boundary between them. This prevents the capacitor 1 from being adversely affected by such a boundary.

[0026] The thickness of the lower portion 30A of the upper electrode 30 is preferably smaller than the thickness of the upper portion 30B of the upper electrode 30. This makes it possible to effectively reduce variations in ESR and capacitance.

[0027] The thickness of the lower portion 30A is preferably less than 1 μm. This allows for further reduction in capacitance variation. The thickness of the lower portion 30A is more preferably 0.05 μm or more and 0.5 μm or less, and even more preferably 0.05 μm or more and 0.1 μm or less. Here, the thickness of the lower portion 30A may be the thickness of a fringe portion of the lower portion 30A.

[0028] The thickness of the upper portion 30B is preferably 1 μm or more. This allows for a further reduction in ESR. The thickness of the upper portion 30B is more preferably 1 μm or more and 5 μm or less, and even more preferably 3 μm or more and 5 μm or less. Here, the thickness of the upper portion 30B may be the thickness of a portion located above the fringe portion of the lower portion 30A.

[0029] Next, a method for manufacturing the capacitor according to this embodiment will be described.

[0030] FIG. 3A is a cross-sectional view schematically showing an example of a step of forming an insulating layer in embodiment 1. FIG. 3B is a cross-sectional view schematically showing an example of a step of forming a lower electrode in embodiment 1. FIG. 3C is a cross-sectional view schematically showing an example of a step of forming a dielectric film in embodiment 1. FIG. 3D is a cross-sectional view schematically showing an example of a step of forming a metal film for an upper electrode in embodiment 1. FIG. 3E is a cross-sectional view schematically showing an example of a first step of processing a metal film for an upper electrode in embodiment 1. FIG. 3F is a cross-sectional view schematically showing an example of a second step of processing a metal film for an upper electrode in embodiment 1. FIG. 3G is a cross-sectional view schematically showing an example of a step of forming a via in a dielectric film in embodiment 1. FIG. 3H is a cross-sectional view schematically showing an example of a step of forming a protective layer in embodiment 1. FIG. 3I is a cross-sectional view schematically showing an example of a step of forming an external electrode in embodiment 1.

[0031] 3A to 3I focus on one capacitor, but multiple capacitors may be formed simultaneously on a substrate. That is, an aggregate substrate having multiple capacitors may be manufactured and then separated into individual capacitors. The same applies to the second and subsequent embodiments.

[0032] First, as shown in FIG. 3A, a semiconductor substrate 11 such as a silicon substrate or a gallium arsenide substrate is coated with SiO 2 by a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, or the like. ２ , SiN, Al ２ O ３In this way, the substrate 10 having an insulating surface 10a is prepared. If the substrate 10 is an insulating substrate such as glass or alumina, the insulating layer 12 can be omitted.

[0033] 3B, a lower electrode 21 is formed on the insulating surface 10a (insulating layer 12) by a lift-off method, a plating method, an etching method, etc. The material of the lower electrode 21 is preferably Cu, Ag, Au, Al, Pt, or an alloy containing at least one of these metals.

[0034] 3C, a dielectric film 22 is formed on the entire surface of the substrate 10 by a CVD method, a PVD method, or the like. ２ , SiN, Al ２ O ３ , HfO ２ , Ta ２ O ５ The oxides or nitrides thereof are preferred.

[0035] 3D , a metal film 30a that will become the upper electrode 30 is formed on the dielectric film 22 by a CVD method, a PVD method, or the like. The material of the upper electrode 30 (metal film 30a) is preferably Cu, Ag, Au, Al, Pt, or an alloy containing at least one of these metals.

[0036] 3E, a resist pattern for the upper portion 30B of the upper electrode 30 is formed by photolithography, and the metal film 30a is processed by etching, adjusting the etching time and other factors so that a thin film remains.

[0037] 3F, a resist pattern for the lower portion 30A of the upper electrode 30 is formed by photolithography, and the lower portion 30A is formed by etching. At this time, it is preferable to use a method such as dry etching, which has high processing accuracy.

[0038] Next, as shown in FIG. 3G, vias (openings) 25 for electrical connection of the lower electrodes 21 are formed in the dielectric film 22 by etching or the like.

[0039] Next, as shown in FIG. 3H, the protective layer 23 is formed. The material of the protective layer 23 is preferably a resin material such as polyimide. The protective layer 23 is provided with a via (opening) 26A above the via 25 and a via (opening) 26B above the upper electrode 30. The protective layer 23 can be formed by, for example, a spin coating method. Alternatively, the pattern of the protective layer 23 can be formed by a photolithography method, an etching method, or the like.

[0040] A moisture-resistant film such as SiN may be formed under the protective layer 23 by a CVD method, a PVD method, or the like.

[0041] Next, as shown in Fig. 3I, the external electrode 24 is formed by a lift-off method, a plating method, an etching method, or the like. More specifically, a first external electrode 24A is formed so as to fill the vias 25 and 26A, and a second external electrode 24B is formed so as to fill the via 26B. The material of the external electrode 24 is preferably Cu, Ni, Ag, Au, or Al, and the outermost surface is preferably Au. The external electrode 24 may have a single-layer structure or a multi-layer structure.

[0042] When manufacturing an aggregate substrate having a plurality of capacitors, the aggregate substrate is thinned to a desired element thickness by back grinding, and then diced into individual pieces by blade dicing, stealth dicing, plasma dicing, etc. In other words, the aggregate substrate is cut into pieces the size of individual capacitors.

[0043] In this manner, the capacitor 1 according to this embodiment is manufactured.

[0044] Second Embodiment This embodiment differs from the first embodiment in that the upper electrode is formed of a plurality of layers, two layers in this case.

[0045] 4 is a cross-sectional view schematically illustrating an example of a capacitor according to embodiment 2 of the present invention, which corresponds to the cross-sectional view of the capacitor taken along line AA in FIG.

[0046] 4, the upper electrode 30 has a lower layer 31 and an upper layer 32 provided on the lower layer 31. This allows the convex structure of the upper electrode 30 to be formed using different materials, and by combining a material that is easy to process with a material that has low resistance, the ESR can be further reduced and capacitance variation can be minimized. Furthermore, compared to embodiment 1, it is easier to control the film thickness of the lower portion 30A (lower layer 31) of the upper electrode 30.

[0047] Thus, in this embodiment, the lower layer 31 corresponds to the lower portion 30A of the upper electrode 30 , and the upper layer 32 corresponds to the upper portion 30B of the upper electrode 30 .

[0048] The upper layer 32 is provided only on the upper surface of the lower layer 31. That is, the entire upper layer 32 is present inside the lower layer 31 in a plan view.

[0049] As described above, the upper layer 32 and the lower layer 31 may contain different materials. That is, the material constituting the upper layer 32 may be different from the material constituting the lower layer 31. This allows the use of materials suitable for each of the upper layer 32 and the lower layer 31. In this case, it is preferable that the resistivity of the material constituting the upper layer 32 is lower than the resistivity of the material constituting the lower layer 31. It is also preferable that the lower layer 31 is formed from a material that is easy to process, and the upper layer 32 is formed from a material that has low resistance.

[0050] On the other hand, the upper layer 32 and the lower layer 31 may contain the same material, and the material constituting the upper layer 32 may be the same as the material constituting the lower layer 31. This can prevent a boundary from occurring between the upper layer 32 and the lower layer 31. Therefore, it is possible to prevent the capacitor 2 from being adversely affected by such a boundary.

[0051] In this specification, the term "same" includes cases where something is substantially the same.

[0052] Next, a method for manufacturing the capacitor according to this embodiment will be described.

[0053] FIG. 5A is a cross-sectional view schematically showing an example of a step of forming an insulating layer in embodiment 2. FIG. 5B is a cross-sectional view schematically showing an example of a step of forming a lower electrode in embodiment 2. FIG. 5C is a cross-sectional view schematically showing an example of a step of forming a dielectric film in embodiment 2. FIG. 5D is a cross-sectional view schematically showing an example of a step of forming a lower layer of an upper electrode in embodiment 2. FIG. 5E is a cross-sectional view schematically showing an example of a step of forming an upper layer of an upper electrode in embodiment 2. FIG. 5F is a cross-sectional view schematically showing an example of a step of forming a via in a dielectric film in embodiment 2. FIG. 5G is a cross-sectional view schematically showing an example of a step of forming a protective layer in embodiment 2. FIG. 5H is a cross-sectional view schematically showing an example of a step of forming an external electrode in embodiment 2.

[0054] First, as shown in FIGS. 5A to 5C, an insulating layer 12, a lower electrode 21, and a dielectric film 22 are formed in this order on a semiconductor substrate 11, similarly to the first embodiment.

[0055] 5D, a lower layer 31 of the upper electrode 30 is formed on the dielectric film 22. The material of the lower layer 31 is preferably Cu, Ag, Au, Al, Pt, or an alloy containing at least one of these metals. At this time, it is preferable to use a method such as dry etching, which has high processing accuracy.

[0056] 5E, the upper layer 32 of the upper electrode 30 is selectively formed only on the upper surface of the lower layer 31 of the upper electrode 30 by a method that does not depend on the base, such as a lift-off method or a plating method. Note that the lift-off method and the plating method have lower processing accuracy than dry etching, but this is not a particular problem because the upper layer 32 does not affect the capacitance. The material of the upper layer 32 is preferably Cu, Ag, Au, Al, Pt, or an alloy containing at least one of these metals.

[0057] Thereafter, as in the first embodiment, as shown in FIGS. 5F to 5H, vias 25, a protective layer 23, and external electrodes 24 are formed in this order, and the device is thinned to a desired element thickness and then singulated.

[0058] In this manner, the capacitor 2 according to this embodiment is manufactured.

[0059] Third Embodiment This embodiment differs from the second embodiment in that a thick lower layer of the upper electrode is formed, and a thin upper layer is formed thereon to cover it.

[0060] 6 is a cross-sectional view schematically illustrating an example of a capacitor according to embodiment 3 of the present invention, which corresponds to the cross-sectional view of the capacitor taken along line AA in FIG.

[0061] 6, the upper layer 32 of the upper electrode 30 is provided so as to cover the upper and side surfaces of the lower layer 31 of the upper electrode 30. This provides the effect of being able to apply a process technology for improving dimensional accuracy in addition to the effect of the second embodiment. More specifically, in the second embodiment, when the lower layer 31 and the upper layer 32 of the upper electrode 30 are formed of the same material, only methods with low processing accuracy, such as lift-off and plating, could be used to form the upper layer 32. However, in this embodiment, methods with high processing accuracy, such as dry etching, can be used to form the upper layer 32.

[0062] In this embodiment, the end of the upper layer 32 (the fringe portion in contact with the dielectric film 22) and the lower portion of the lower layer 31 (the portion located at the same height as the end of the upper layer 32) correspond to the lower portion 30A of the upper electrode 30, and the upper portion of the lower layer 31 (the portion excluding the lower portion of the lower layer 31) and the portion of the upper layer 32 excluding the end correspond to the upper portion 30B of the upper electrode 30.

[0063] The upper layer 32 is provided so as to cover the entire upper surface and the entire side surface of the lower layer 31.

[0064] As in the second embodiment, the material constituting the upper layer 32 may be different from the material constituting the lower layer 31, but in this embodiment, it is preferable that the resistivity of the material constituting the lower layer 31 is lower than the resistivity of the material constituting the upper layer 32. It is also preferable that the upper layer 32 is formed from a material that is easy to process, and the lower layer 31 is formed from a material that has low resistance.

[0065] As in the second embodiment, the upper layer 32 and the lower layer 31 may contain the same material, and the material constituting the upper layer 32 may be the same as the material constituting the lower layer 31 .

[0066] Next, a method for manufacturing the capacitor according to this embodiment will be described.

[0067] 7A is a cross-sectional view schematically showing an example of a step of forming an insulating layer in embodiment 3. FIG. 7B is a cross-sectional view schematically showing an example of a step of forming a lower electrode in embodiment 3. FIG. 7C is a cross-sectional view schematically showing an example of a step of forming a dielectric film in embodiment 3. FIG. 7D is a cross-sectional view schematically showing an example of a step of forming a lower layer of an upper electrode in embodiment 3. FIG. 7E is a cross-sectional view schematically showing an example of a step of forming an upper layer of an upper electrode in embodiment 3. FIG. 7F is a cross-sectional view schematically showing an example of a step of forming a via in a dielectric film in embodiment 3. FIG. 7G is a cross-sectional view schematically showing an example of a step of forming a protective layer in embodiment 3. FIG. 7H is a cross-sectional view schematically showing an example of a step of forming an external electrode in embodiment 3.

[0068] First, as shown in FIGS. 7A to 7C, an insulating layer 12, a lower electrode 21, and a dielectric film 22 are formed in this order on a semiconductor substrate 11, similarly to the first embodiment.

[0069] 7D , a lower layer 31 of the upper electrode 30 is formed on the dielectric film 22. The material of the lower layer 31 is preferably Cu, Ag, Au, Al, Pt, or an alloy containing at least one of these metals. The method for forming the lower layer 31 is not particularly limited, and may be a method with low processing accuracy, such as a lift-off method or a plating method, or a method with high processing accuracy, such as dry etching. In other words, this embodiment offers more options for the process of forming the lower layer 31 than the second embodiment.

[0070] 7E, the upper layer 32 of the upper electrode 30 is formed so as to cover the upper and side surfaces of the lower layer 31 of the upper electrode 30. The material of the upper layer 32 is preferably Cu, Ag, Au, Al, Pt, or an alloy containing at least one of these metals. At this time, it is preferable to use a method such as dry etching, which has high processing accuracy.

[0071] Thereafter, as in the first embodiment, as shown in FIGS. 7F to 7H, vias 25, a protective layer 23, and external electrodes 24 are formed in this order, and the device is thinned to a desired element thickness and then singulated.

[0072] In this manner, the capacitor 3 according to this embodiment is manufactured.

[0073] (Embodiment 4) This embodiment differs from embodiment 2 in that another metal layer is inserted between the first layer (lower layer) and the second layer (upper layer) of the upper electrode.

[0074] 8 is a cross-sectional view schematically illustrating an example of a capacitor according to embodiment 4 of the present invention, which corresponds to the cross-sectional view of the capacitor taken along line AA in FIG.

[0075] 8, the upper electrode 30 has a metal layer 33 provided between the upper layer 32 and the lower layer 31. This provides the same effect as in the third embodiment, because the metal layer 33 between the upper layer 32 and the lower layer 31 functions as a stopper film during etching.

[0076] In this embodiment, the lower layer 31 corresponds to a lower portion 30A of the upper electrode 30 , and the upper layer 32 and the metal layer 33 correspond to an upper portion 30B of the upper electrode 30 .

[0077] Moreover, the upper layer 32 and the metal layer 33 are provided only on the upper surface of the lower layer 31. That is, in a plan view, the entire upper layer 32 and the entire metal layer 33 are present inside the lower layer 31. Furthermore, the upper layer 32 is provided on the entire upper surface of the metal layer 33. That is, in a plan view, the formation area of ​​the upper layer 32 coincides with the formation area of ​​the metal layer 33. Here, "coinciding" includes the case where they substantially coincide.

[0078] Next, a method for manufacturing the capacitor according to this embodiment will be described.

[0079] FIG. 9A is a cross-sectional view schematically showing an example of a step of forming an insulating layer in embodiment 4. FIG. 9B is a cross-sectional view schematically showing an example of a step of forming a lower electrode in embodiment 4. FIG. 9C is a cross-sectional view schematically showing an example of a step of forming a dielectric film in embodiment 4. FIG. 9D is a cross-sectional view schematically showing an example of a step of forming a metal film for an upper electrode in embodiment 4. FIG. 9E is a cross-sectional view schematically showing an example of a first step of processing a metal film for an upper electrode in embodiment 4. FIG. 9F is a cross-sectional view schematically showing an example of a second step of processing a metal film for an upper electrode in embodiment 4. FIG. 9G is a cross-sectional view schematically showing an example of a third step of processing a metal film for an upper electrode in embodiment 4. FIG. 9H is a cross-sectional view schematically showing an example of a step of forming a via in a dielectric film in embodiment 4. FIG. 9I is a cross-sectional view schematically showing an example of a step of forming a protective layer in embodiment 4. FIG. 9J is a cross-sectional view schematically showing an example of a step of forming an external electrode in embodiment 4.

[0080] First, as shown in FIGS. 9A to 9C, an insulating layer 12, a lower electrode 21, and a dielectric film 22 are formed in this order on a semiconductor substrate 11, similarly to the first embodiment.

[0081] 9D , metal films 31a, 33a, and 32a, which will become the lower layer 31, metal layer 33, and upper layer 32 of the upper electrode 30, respectively, are formed on the dielectric film 22. The material for the lower layer 31 (metal film 31a) is preferably Cu, Ag, Au, Al, Pt, or an alloy containing at least one of these metals. The material for the metal layer 33 (metal film 33a) is preferably Ti, Cr, Ta, or an alloy containing at least one of these metals. The material for the upper layer 32 (metal film 32a) is preferably Cu, Ag, Au, Al, Pt, or an alloy containing at least one of these metals.

[0082] 9E, a resist pattern for the upper layer 32 of the upper electrode 30 is formed by photolithography, and the metal film 32a is processed by etching to form the upper layer 32. In this process, the metal film 32a functions as an etching stopper film. Therefore, a method such as dry etching, which has high processing accuracy, can be used.

[0083] 9F, the metal film 33a is processed to form the metal layer 33. In detail, the metal film 33a is dry-etched using the upper layer 32 as a mask, and the metal layer 33 is formed.

[0084] 9G, a resist pattern for the lower layer 31 of the upper electrode 30 is formed by photolithography, and the lower layer 31 is formed by etching. At this time, it is preferable to use a method such as dry etching, which has high processing accuracy.

[0085] In this manner, in this embodiment as well, as in the third embodiment, the upper electrode 30 can be formed without using a method with low processing accuracy such as a lift-off method or a plating method.

[0086] Here, in order to improve the processing accuracy of the lower layer 31, the metal films 33a and 31a are patterned, respectively, and the metal layer 33 and the lower layer 31 are formed sequentially. However, depending on the materials of the metal films 33a and 31a, the metal films 33a and 31a may be patterned at the same time, and the metal layer 33 and the lower layer 31 may be formed simultaneously.

[0087] Thereafter, as in the first embodiment, as shown in FIGS. 9H to 9J, vias 25, a protective layer 23, and external electrodes 24 are formed in this order, and the device is thinned to a desired element thickness and then singulated.

[0088] In this manner, the capacitor 4 according to this embodiment is manufactured.

[0089] Fifth Embodiment This embodiment differs from the second embodiment in that an insulating film is formed between the end of the first layer (lower layer) and the end of the second layer (upper layer) of the upper electrode.

[0090] 10 is a cross-sectional view schematically illustrating an example of a capacitor according to embodiment 5 of the present invention, which corresponds to the cross-sectional view of the capacitor taken along line AA in FIG.

[0091] 10 further includes an insulating film 27 provided between an end of the upper layer 32 of the upper electrode 30 and an end of the lower layer 31 of the upper electrode 30. This not only achieves the effect of the second embodiment, but also alleviates stress concentration at the end of the upper layer 32, improving reliability.

[0092] In this embodiment, the lower layer 31 corresponds to the lower portion 30A of the upper electrode 30, and the upper layer 32 corresponds to the upper portion 30B of the upper electrode 30. The end of the upper layer 32 is formed in an overhanging shape.

[0093] The insulating film 27 may overlap the end of the lower layer 31 of the upper electrode 30 in a portion of the periphery of the lower layer 31, but it is preferable that the insulating film 27 overlaps the end of the lower layer 31 so as to surround the entire periphery of the lower layer 31 of the upper electrode 30. In other words, it is preferable that the entire periphery of the lower layer 31 is covered with the insulating film 27. Examples of materials for the insulating film 27 include SiO ２ , SiN, Al ２ O ３ etc. can be used.

[0094] As shown in FIG. 10, the width w of the insulating film 27 overlapping with the upper layer 32 is not particularly limited, but is preferably 1% or more and 50% or less of the width W of the upper layer 32, and more preferably 1% or more and 10% or less.

[0095] The percentage of the width w relative to the width W is calculated based on the widths w and W measured at the same cross section.

[0096] The thickness of the insulating film 27 is not particularly limited, but is preferably 0.05 μm or more and 0.5 μm or less, and more preferably 0.05 μm or more and 0.1 μm or less.

[0097] The capacitor 5 according to this embodiment can be manufactured by the same process as the capacitor 2 according to embodiment 2. However, in this embodiment, after the lower layer 31 of the upper electrode 30 is formed (see FIG. 5D ), an insulating film is formed by a CVD method, a PVD method, or the like, and the insulating film is patterned by an etching method or the like to form an insulating film 27. Thereafter, as in embodiment 2, the upper layer 32 of the upper electrode 30, the via 25, the protective layer 23, and the external electrode 24 are formed in this order, and the resulting device is thinned to a desired element thickness and then singulated.

[0098] (Other Embodiments) The semiconductor device of the present invention is not limited to the above-described embodiments, and various applications and modifications can be made within the scope of the present invention with respect to the configuration and manufacturing conditions of the semiconductor device such as a capacitor.

[0099] For example, the semiconductor device of the present invention may further include a second upper electrode provided on the dielectric film at a distance from the upper electrode, and the first external electrode may be connected to the second upper electrode. This allows two capacitors to be formed for one lower electrode. In this case, it is preferable that the second upper electrode also has a convex shape in cross section.

[0100] The present specification discloses the following:

[0101] <1> A semiconductor device comprising: a substrate having an insulating surface; a lower electrode provided on the insulating surface; a dielectric film provided on the lower electrode; and an upper electrode provided on the dielectric film, wherein the upper electrode has a convex shape in a cross-sectional view.

[0102] <2> The semiconductor device according to <1>, wherein the upper electrode has a lower layer and an upper layer provided on the lower layer.

[0103] <3> The semiconductor device according to <2>, wherein the upper layer is provided only on an upper surface of the lower layer.

[0104] <4> The semiconductor device according to <2>, wherein the upper layer is provided so as to cover an upper surface and a side surface of the lower layer.

[0105] <5> The semiconductor device according to <3>, wherein the upper electrode has a metal layer provided between the upper layer and the lower layer.

[0106] <6> The semiconductor device according to <3>, further comprising an insulating film provided between an end of the upper layer and an end of the lower layer.

[0107] <7> The semiconductor device according to any one of <2> to <6>, wherein the upper layer and the lower layer contain the same material.

[0108] <8> The semiconductor device according to any one of <2> to <6>, wherein the upper layer and the lower layer contain different materials.

[0109] <9> The semiconductor device according to any one of <1> to <8>, wherein the thickness of the lower portion of the upper electrode is smaller than the thickness of the upper portion of the upper electrode.

[0110] <10> The semiconductor device according to <9>, wherein the thickness of the lower portion is less than 1 μm.

[0111] <11> The semiconductor device according to <9> or <10>, wherein the thickness of the upper portion is 1 μm or more.

[0112] 1, 2, 3, 4, 5 Capacitor (semiconductor device) 10 Substrate 10a Insulating surface 11 Semiconductor substrate 12 Insulating layer 21 Lower electrode 22 Dielectric film 23 Protective layer 24 External electrode 24A First external electrode 24B Second external electrode 25, 26A, 26B Via (opening) 27 Insulating film 30 Upper electrode 30A Lower part of upper electrode 30B Upper part of upper electrode 30a, 31a, 32a, 33a Metal film 31 Lower layer of upper electrode 32 Upper layer of upper electrode 33 Metal layer of upper electrode

Claims

1. a substrate having an insulating surface; a lower electrode provided on the insulating surface; a dielectric film provided on the lower electrode; an upper electrode provided on the dielectric film; a protective layer provided on the dielectric film and the upper electrode; an external electrode penetrating the protective layer; Equipped with In a plan view, the upper electrode is provided within a region where the lower electrode is formed, The semiconductor device, wherein the upper electrode has a convex shape in a cross-sectional view.

2. 2. The semiconductor device according to claim 1, wherein said upper electrode has a lower layer and an upper layer provided on said lower layer.

3. 3. The semiconductor device according to claim 2, wherein said upper layer is provided only on an upper surface of said lower layer.

4. 3. The semiconductor device according to claim 2, wherein said upper layer is provided so as to cover an upper surface and side surfaces of said lower layer.

5. 4. The semiconductor device according to claim 3, wherein said upper electrode has a metal layer provided between said upper layer and said lower layer.

6. 4. The semiconductor device according to claim 3, further comprising an insulating film provided between an end of said upper layer and an end of said lower layer.

7. 7. The semiconductor device according to claim 2, wherein the upper layer and the lower layer comprise the same material.

8. 7. The semiconductor device according to claim 2, wherein the upper layer and the lower layer contain different materials.

9. 7. The semiconductor device according to claim 1, wherein a thickness of the lower portion of said upper electrode is smaller than a thickness of the upper portion of said upper electrode.

10. 10. The semiconductor device of claim 9, wherein the thickness of the lower portion is less than 1 [mu]m.

11. 10. The semiconductor device according to claim 9, wherein the upper portion has a thickness of 1 [mu]m or more.