Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of reducing stress concentration due to an electrostrictive effect when a voltage is applied. This multilayer ceramic capacitor includes a first lead-out portion 31B, a first opposing portion 31A, a second lead-out portion 32B, and a second opposing portion 32A. The first lead-out portion 31B includes a first external electrode-side region 31BB, a first opposing portion-side region 31BC, and a first intermediate region 31BA, and the second lead-out portion 32B includes a second external electrode-side region 32BB, a second opposing portion-side region 32BC, and a second intermediate region 32BA. The coverage of the first intermediate region 31BA and the second intermediate region 32BA is less than the coverage of the first external electrode-side region 31BB and the second external electrode-side region 32BB, and the coverage of the first intermediate region 31BA and the second intermediate region 32BA is less than the coverage of the first opposing portion 31A and the second opposing portion 32A.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors have been known for some time. Generally, multilayer ceramic capacitors include a laminate in which multiple dielectric layers and internal electrode layers are alternately stacked (see Patent Document 1). There is a demand for such multilayer ceramic capacitors to be further miniaturized, have higher capacitance, and are more reliable. To this end, ferroelectric materials with high dielectric constants are sometimes used as the material for the dielectric layers. Furthermore, attempts have been made to reduce the thickness of the dielectric layers, reduce the thickness of the internal electrode layers, and increase the number of stacked layers.

[0003] Japanese Patent Application Publication No. 8-306580

[0004] Such dielectric layers have piezoelectricity and electrostriction, and therefore, when a voltage is applied to a multilayer ceramic capacitor having such dielectric layers, strain corresponding to the magnitude of the applied voltage is generated in the laminate due to the electrostrictive effect, generating stress inside the multilayer ceramic capacitor.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor that can ensure capacitance density, maintain connectivity between internal electrode layers and external electrodes, and reduce stress concentration due to the electrostrictive effect when a voltage is applied.

[0006] A multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor comprising: a laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, the laminate including a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction; a first external electrode arranged on the first end surface side; and a second external electrode arranged on the second end surface side, wherein the plurality of internal electrode layers include a first internal electrode layer and a second internal electrode layer, and the first internal electrode layer has a first lead portion, one end of which is extended to the first end surface and connected to the first external electrode, and a first opposing portion, which is connected to the first lead portion and faces the second internal electrode layer arranged adjacent to the first internal electrode layer in the lamination direction, and the second internal electrode layer has one end of which is extended to the second end surface and connected to the second external electrode. a second lead portion and a second opposing portion connected to the second lead portion and opposing the first internal electrode layer arranged adjacent to the second lead portion in the stacking direction, the first lead portion having a first external electrode side region near the connection portion with the first external electrode, a first opposing portion side region near the connection portion with the first opposing portion, and a first intermediate region between the first external electrode side region and the first opposing portion side region, and the second lead portion having a first external electrode side region near the connection portion with the second external electrode, The first intermediate region has a second external electrode side region, a second opposing portion side region near the connection with the second opposing portion, and a second intermediate region between the second external electrode side region and the second opposing portion side region, and the coverage of the first intermediate region and the second intermediate region is lower than the coverage of the first external electrode side region and the second external electrode side region, and the coverage of the first intermediate region and the second intermediate region is lower than the coverage of the first opposing portion and the second opposing portion.

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can ensure capacitance density, maintain connectivity between internal electrode layers and external electrodes, and reduce stress concentration due to the electrostrictive effect when a voltage is applied.

[0008] 1 is an external perspective view of the multilayer ceramic capacitor according to the first embodiment. FIG. 2 is a cross-sectional view taken along II-II in FIG. 1. FIG. 3 is a cross-sectional view taken along III-III in FIG. 2. FIG. 4 is a cross-sectional view taken along IVA-IVA in FIG. 2. FIG. 5 is a cross-sectional view taken along IVB-IVB in FIG. 2. FIG. 5 is an enlarged cross-sectional view schematically showing a portion indicated by R1 in FIG. 2. FIG. 6 is an enlarged cross-sectional view schematically showing a portion indicated by R2 in FIG. 2 of the multilayer ceramic capacitor according to the second embodiment. FIG. 7 is an enlarged cross-sectional view schematically showing a portion indicated by R2 in FIG. 2 of the multilayer ceramic capacitor according to the second embodiment.

[0009] First Embodiment Hereinafter, a multilayer ceramic capacitor 1 according to a first embodiment of the present disclosure will be described with reference to the drawings. FIG. 1 is an external perspective view of the multilayer ceramic capacitor 1 according to the embodiment. FIG. 2 is a cross-sectional view taken along II-II in FIG. 1. FIG. 3 is a cross-sectional view taken along III-III in FIG. 2. FIG. 4A is a cross-sectional view taken along IVA-IVA in FIG. 2. FIG. 4B is a cross-sectional view taken along IVB-IVB in FIG. 2.

[0010] 1, the multilayer ceramic capacitor 1 according to the embodiment has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 10 having a substantially rectangular parallelepiped shape and a pair of external electrodes 40 disposed at both ends of the laminate 10 while being spaced apart from each other.

[0011] In Fig. 1, arrow T indicates the stacking direction of the multilayer ceramic capacitor 1 and the laminate 10. This stacking direction T also corresponds to the thickness direction and height direction of the multilayer ceramic capacitor 1 and the laminate 10. In Fig. 1, arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T. In Fig. 1, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T and the length direction L. A pair of external electrodes 40 are respectively disposed at one end and the other end of the length direction L of the laminate 10.

[0012] 1 to 4B show an XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in FIG. 2 is also referred to as an LT cross section. The cross section shown in FIG. 3 is also referred to as a WT cross section. The cross sections shown in FIGS. 4A and 4B are also referred to as LW cross sections.

[0013] As shown in Figures 1 to 4B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that face each other in the stacking direction T, a first end surface LS1 and a second end surface LS2 that face each other in a length direction L that is perpendicular to the stacking direction T, and a first side surface WS1 and a second side surface WS2 that face each other in a width direction W that is perpendicular to the stacking direction T and the length direction L.

[0014] As shown in FIG. 1 , the laminate 10 has a substantially rectangular parallelepiped shape. The dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. The corners and ridges of the laminate 10 are preferably rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. Incidentally, unevenness may be formed on part or all of the surfaces constituting the laminate 10.

[0015] The dimensions of the laminate 10 are not particularly limited, but if the dimension of the laminate 10 in the length direction L is defined as the L dimension, the L dimension is preferably 0.2 mm or more and 6 mm or less. If the dimension of the laminate 10 in the stacking direction T is defined as the T dimension, the T dimension is preferably 0.05 mm or more and 5 mm or less. If the dimension of the laminate 10 in the width direction W is defined as the W dimension, the W dimension is preferably 0.1 mm or more and 5 mm or less.

[0016] As shown in Figures 2 and 3, the laminate 10 has an inner layer portion 11, and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged to sandwich the inner layer portion 11 in the stacking direction T.

[0017] The inner layer portion 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 alternately stacked in the stacking direction T. The inner layer portion 11 includes, in the stacking direction T, the internal electrode layer 30 located closest to the first main surface TS1 to the internal electrode layer 30 located closest to the second main surface TS2. In the inner layer portion 11, the plurality of internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0018] The dielectric layers 20 are made of a dielectric material, such as BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ The dielectric material may be a dielectric ceramic containing components such as BaTiO as the main component. The dielectric material may also be a material containing these main components to which subcomponents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds are added. The dielectric material may be a material containing BaTiO as the main component. ３ It is particularly preferred that the material contains:

[0019] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 10 μm or less. The number of laminated dielectric layers 20 is preferably 15 or more and 1200 or less. Note that this number of dielectric layers 20 is the total number of the dielectric layers 20 in the inner layer portion 11 and the number of the dielectric layers 20 in each of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0020] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The first internal electrode layers 31 and the second internal electrode layers 32 are alternately arranged in the stacking direction T with the dielectric layer 20 sandwiched therebetween. The first internal electrode layers 31 are extended to the first end face LS1. The second internal electrode layers 32 are extended to the second end face LS2. In the following, when it is not necessary to distinguish between the first internal electrode layers 31 and the second internal electrode layers 32, the first internal electrode layers 31 and the second internal electrode layers 32 may be collectively referred to as the internal electrode layers 30.

[0021] 4A , the first internal electrode layer 31 has a first opposing portion 31A and a first lead portion 31B. The first opposing portion 31A is a region facing the second internal electrode layer 32 with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The first lead portion 31B is a portion that extends from the first opposing portion 31A to the first end face LS1 and is exposed at the first end face LS1.

[0022] 4B , the second internal electrode layer 32 has a second opposing portion 32A and a second lead portion 32B. The second opposing portion 32A is a region facing the first internal electrode layer 31 with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The second lead portion 32B is a portion that extends from the second opposing portion 32A to the second end face LS2 and is exposed at the second end face LS2.

[0023] In this embodiment, the first opposing portion 31A and the second opposing portion 32A face each other with the dielectric layer 20 interposed therebetween, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0024] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle. The shapes of the first draw-out portion 31B and the second draw-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle.

[0025] The width direction W of the first opposing portion 31A and the width direction W of the first lead portion 31B may be the same, or one of the dimensions may be smaller. The width direction W of the second opposing portion 32A and the width direction W of the second lead portion 32B may be the same, or one of the dimensions may be smaller.

[0026] The first internal electrode layer 31 and the second internal electrode layer 32 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0027] The thickness of each of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. 4 The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 15 or more and 1000 or less.

[0028] 2 and 3 , the first main surface side outer layer portion 12 is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. On the other hand, the second main surface side outer layer portion 13 is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 may both be the same as the dielectric layers 20 used in the internal layer portion 11.

[0029] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is a portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as a part of the inner layer portion 11. Figures 4A and 4B show the range of the counter electrode portion 11E in the width direction W and length direction L. The counter electrode portion 11E is also referred to as the effective portion of the capacitor.

[0030] The laminate 10 has a side surface outer layer portion. The side surface outer layer portion includes a first side surface outer layer portion WG1 and a second side surface outer layer portion WG2. The first side surface outer layer portion WG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first side surface WS1. The second side surface outer layer portion WG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second side surface WS2. Figures 3, 4A, and 4B show the ranges in the width direction W of the first side surface outer layer portion WG1 and the second side surface outer layer portion WG2. The side surface outer layer portion is also referred to as a W gap or a side gap.

[0031] The laminate 10 has an end surface side outer layer portion. The end surface side outer layer portion includes a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2. The first end surface side outer layer portion LG1 is a portion located between the counter electrode portion 11E and the first end face LS1 and including the dielectric layer 20 and the first lead portion 31B. That is, the first end surface side outer layer portion LG1 is an assembly of the portions of the plurality of dielectric layers 20 on the first end face LS1 side and the plurality of first lead portions 31B. The second end surface side outer layer portion LG2 is a portion located between the counter electrode portion 11E and the second end face LS2 and including the dielectric layer 20 and the second lead portion 32B. That is, the second end surface side outer layer portion LG2 is an assembly of the portions of the plurality of dielectric layers 20 on the second end face LS2 side and the plurality of second lead portions 32B. 2, 4A, and 4B show the range of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 in the length direction L. The end surface side outer layer portions are also called L gaps or end gaps.

[0032] As shown in Figures 1 and 2, the external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end face LS2 side of the laminate 10.

[0033] The first external electrode 40A and the second external electrode 40B have the same basic configuration. The first external electrode 40A and the second external electrode 40B have shapes that are approximately plane-symmetric with respect to a WT cross section at the center in the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, in the following, when it is not necessary to distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrodes 40.

[0034] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is in contact with the first lead portions 31B of each of the first internal electrode layers 31 exposed at the first end face LS1. This electrically connects the first external electrode 40A to the first internal electrode layers 31. The first external electrode 40A may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0035] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is in contact with the second lead portions 32B of each of the second internal electrode layers 32 exposed at the second end face LS2. This electrically connects the second external electrode 40B to the second internal electrode layers 32. The second external electrode 40B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0036] As described above, in the laminate 10, capacitance is formed by the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 facing each other via the dielectric layer 20. Therefore, the characteristics of a capacitor are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0037] 2, 4A, and 4B, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. The second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0038] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first lead portions 31B of each of the first internal electrode layers 31 exposed at the first end face LS1. In this embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0039] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is in contact with the second lead portions 32B of each of the second internal electrode layers 32 exposed at the second end face LS2. In this embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0040] The first base electrode layer 50A and the second base electrode layer 50B of this embodiment are baked layers. The baked layers preferably contain a metal component and either a glass component or a ceramic component, or both. The metal component includes at least one selected from, for example, Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, Li, etc. The ceramic component may be the same type of ceramic material as that of the dielectric layer 20, or a different type of ceramic material. The ceramic component may be, for example, BaTiO ３ , CaTiO ３ , (Ba,Ca)TiO ３ , SrTiO ３ , CaZrO ３ It includes at least one selected from the following:

[0041] The baked layer is formed by, for example, applying and baking a conductive paste containing glass and metal to the laminate 10. The baked layer can be formed by co-firing a pre-fired laminate chip, which is the material for the laminate 10 having multiple internal electrodes and dielectric layers, with a conductive paste applied to the laminate chip. Alternatively, the baked layer can be formed by firing the laminate chip to obtain the laminate 10, and then applying and baking a conductive paste to the laminate 10. In the case of the co-fired structure, it is preferable to form the baked layer by adding a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may be multiple layers.

[0042] The thickness of the first base electrode layer 50A located on the first end surface LS1 in the longitudinal direction L is preferably, for example, approximately 3 μm or more and 200 μm or less at the center of the first base electrode layer 50A in the stacking direction T and width direction W.

[0043] The thickness corresponding to the length direction L of the second base electrode layer 50B located on the second end surface LS2 is preferably, for example, approximately 3 μm or more and 200 μm or less at the center of the second base electrode layer 50B in the stacking direction T and width direction W.

[0044] When the first base electrode layer 50A is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the first base electrode layer 50A provided in this portion, corresponding to the stacking direction T, is, for example, approximately 3 μm or more and 40 μm or less at the center of the length direction L and width direction W of the first base electrode layer 50A provided in this portion.

[0045] When the first base electrode layer 50A is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness corresponding to the width direction W of the first base electrode layer 50A provided on this portion be, for example, approximately 3 μm or more and 40 μm or less at the center of the length direction L and stacking direction T of the first base electrode layer 50A provided on this portion.

[0046] When the second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the second base electrode layer 50B provided on this portion, corresponding to the stacking direction T, is, for example, approximately 3 μm or more and 40 μm or less at the center of the length direction L and width direction W of the second base electrode layer 50B provided on this portion.

[0047] When the second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness corresponding to the width direction W of the second base electrode layer 50B provided on this portion be, for example, approximately 3 μm or more and 40 μm or less at the center of the length direction L and stacking direction T of the second base electrode layer 50B provided on this portion.

[0048] The first and second underlying electrode layers 50A and 50B are not limited to baked layers. The first and second underlying electrode layers 50A and 50B include at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like. For example, the first and second underlying electrode layers 50A and 50B may be thin film layers. The thin film layers are formed by a thin film formation method such as sputtering or vapor deposition. The thin film layers are layers of metal particles deposited to a thickness of 10 μm or less.

[0049] The first plating layer 60A is disposed so as to cover the first base electrode layer 50A.

[0050] The second plating layer 60B is disposed so as to cover the second base electrode layer 50B.

[0051] The first plating layer 60A and the second plating layer 60B may contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed of multiple layers. The first plating layer 60A and the second plating layer 60B preferably have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0052] The first plating layer 60A is disposed so as to cover the first base electrode layer 50A. In this embodiment, the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0053] The second plating layer 60B is disposed so as to cover the second base electrode layer 50B. In this embodiment, the second plating layer 60B has a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0054] The Ni plating layer prevents the first and second base electrode layers 50A and 50B from being eroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1, thereby facilitating mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably 2 μm or more and 10 μm or less.

[0055] The external electrode 40 of this embodiment may have, for example, a conductive resin layer containing conductive particles and a thermosetting resin. The conductive resin layer may be disposed so as to cover the baked layer. When the conductive resin layer is disposed so as to cover the baked layer, the conductive resin layer is disposed between the baked layer and the plating layer (first plating layer 60A, second plating layer 60B). The conductive resin layer may completely cover the baked layer or may cover only a portion of the baked layer.

[0056] The conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even when the multilayer ceramic capacitor 1 is subjected to a physical shock or a shock due to a thermal cycle, the conductive resin layer functions as a buffer layer. Therefore, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0057] The metal constituting the conductive particles may be Ag, Cu, Ni, Sn, Bi, or an alloy containing any of these. The conductive particles preferably contain Ag. The conductive particles are, for example, Ag metal powder. Ag has the lowest resistivity among metals and is therefore suitable as an electrode material. Furthermore, Ag is a noble metal, so it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as conductive particles.

[0058] The conductive particles may also be metal powder whose surface is coated with Ag. When using metal powder whose surface is coated with Ag, the metal powder is preferably Cu, Ni, Sn, Bi, or an alloy powder thereof. In order to maintain the properties of Ag while making the base metal inexpensive, it is preferable to use Ag-coated metal powder.

[0059] Furthermore, the conductive particles may be Cu or Ni that has been subjected to an anti-oxidation treatment. Furthermore, the conductive particles may be metal powder in which the surface of metal powder is coated with Sn, Ni, or Cu. When using metal powder in which the surface of Sn, Ni, or Cu is coated, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof.

[0060] The shape of the conductive particles is not particularly limited. The conductive particles may be spherical, flat, or other shapes, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0061] The conductive particles contained in the conductive resin layer mainly play a role in ensuring the electrical conductivity of the conductive resin layer. Specifically, the conductive particles come into contact with each other to form electrical paths within the conductive resin layer.

[0062] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins, such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, the resin of the conductive resin layer preferably includes a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent for the epoxy resin may be any of various known compounds, such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0063] The conductive resin layer may be formed of a plurality of layers. The thickness of the thickest part of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0064] Note that a configuration may be adopted in which a first plating layer 60A and a second plating layer 60B, which will be described later, are disposed directly on the laminate 10 without providing the first base electrode layer 50A and the second base electrode layer 50B. That is, the multilayer ceramic capacitor 1 may be configured to include plating layers that are directly and electrically connected to the first internal electrode layer 31 and the second internal electrode layer 32. In such a case, a catalyst may be disposed on the surface of the laminate 10 as a pretreatment, and then the plating layers may be formed.

[0065] Even in this case, the plating layer preferably comprises multiple layers. The lower plating layer and the upper plating layer each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing these metals. The lower plating layer is more preferably formed using Ni, which has solder barrier properties. The upper plating layer is more preferably formed using Sn or Au, which have good solder wettability. For example, when the first internal electrode layer 31 and the second internal electrode layer 32 are formed using Ni, the lower plating layer is preferably formed using Cu, which has good bonding properties with Ni. The upper plating layer may be formed as needed, and the external electrode 40 may be composed of only the lower plating layer. Furthermore, the upper plating layer may be the outermost layer, or another plating layer may be formed on the surface of the upper plating layer.

[0066] The thickness of each plating layer disposed without a base electrode layer is preferably 2 μm or more and 10 μm or less. The plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0067] Note that, when the plating layer is formed directly on the laminate 10, the thickness of the base electrode layer can be reduced. Therefore, the dimension of the multilayer ceramic capacitor 1 in the height direction T can be reduced by the amount of the reduced thickness of the base electrode layer, thereby making it possible to reduce the height of the multilayer ceramic capacitor 1. Alternatively, the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 can be increased by the amount of the reduced thickness of the base electrode layer, thereby improving the thickness of the element body. In this way, by forming the plating layer directly on the laminate 10, the design freedom of the multilayer ceramic capacitor can be improved.

[0068] The above is the basic configuration of the multilayer ceramic capacitor 1 according to the embodiment. If the lengthwise dimension of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 40 is defined as L, the L dimension is preferably 0.2 mm or more and 6 mm or less. If the lengthwise dimension of the multilayer ceramic capacitor 1 is defined as T, the T dimension is preferably 0.05 mm or more and 5 mm or less. If the widthwise dimension of the multilayer ceramic capacitor 1 is defined as W, the W dimension is preferably 0.1 mm or more and 5 mm or less.

[0069] Here, the present inventors, through extensive studies, experiments, and simulations, have found that it is desirable to achieve an appropriate coverage of the internal electrode layers in order to improve the overall quality of a multilayer ceramic capacitor. This point is explained below. In multilayer ceramic capacitors, efforts are underway to establish technologies for increasing the coverage of the internal electrode layers in order to improve capacitance density. Coverage is also referred to as the coverage rate of the internal electrode layers relative to the dielectric layers. Through these studies and other efforts, the present inventors have found that improving coverage also contributes to improving the connectivity between the internal electrode layers and the external electrodes. On the other hand, they have also found that if the coverage of the internal electrode layers is not appropriately set, problems such as increased residual stress during the firing process during manufacturing and increased stress due to the electrostrictive effect when voltage is applied can occur. These increased stresses can potentially make the structure of the multilayer ceramic capacitor more susceptible to destruction.

[0070] Fig. 5A is an enlarged cross-sectional view schematically showing a portion indicated by R1 in Fig. 2. Fig. 5B is an enlarged cross-sectional view schematically showing a portion indicated by R2 in Fig. 2. Figs. 5A and 5B are portions of an LT cross section. Figs. 5A and 5B show the dielectric layers 20, first internal electrode layers 31, second internal electrode layers 32, first external electrodes 40A, and second external electrodes 40B in the laminate 10.

[0071] The first internal electrode layer 31 has a first extension portion 31B, one end of which is extended to the first end face LS1 and connected to the first external electrode 40A, and a first opposing portion 31A, which is connected to the first extension portion 31B and faces the second internal electrode layer 32 arranged adjacent to it in the stacking direction T.

[0072] The second internal electrode layer 32 has a second extension portion 32B, one end of which is extended to the second end face LS2 and connected to the second external electrode 40B, and a second opposing portion 32A, which is connected to the second extension portion 32B and faces the first internal electrode layer 31 arranged adjacent to it in the stacking direction T.

[0073] The first extension portion 31B has a first external electrode side region 31BB near the connection portion with the first external electrode 40A, a first opposing portion side region 31BC near the connection portion with the first opposing portion 31A, and a first intermediate region 31BA between the first external electrode side region 31BB and the first opposing portion side region 31BC.

[0074] The second extension portion 32B has a second external electrode side region 32BB near the connection portion with the second external electrode 40B, a second opposing portion side region 32BC near the connection portion with the second opposing portion 32A, and a second intermediate region 32BA between the second external electrode side region 32BB and the second opposing portion side region 32BC.

[0075] The first intermediate region 31BA is located at the longitudinal center of the first lead portion 31B, and preferably has a length of 60% to 80% of the length of the first lead portion 31B in the longitudinal direction L. The second intermediate region 32BA is located at the longitudinal center of the first lead portion, and preferably has a length of 60% to 80% of the length of the first lead portion in the longitudinal direction L.

[0076] The coverage of the first intermediate region 31BA and the second intermediate region 32BA is lower than the coverage of the first external electrode side region 31BB and the second external electrode side region 32BB, and the coverage of the first intermediate region 31BA and the second intermediate region 32BA is lower than the coverage of the first opposing portion 31A and the second opposing portion 32A. This ensures capacitance density, maintains connectivity between the internal electrode layers and the external electrodes, and reduces stress concentration due to the electrostrictive effect when a voltage is applied.

[0077] Furthermore, the coverage of the first opposing portion side region 31BC and the second opposing portion side region 32BC is higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA, which makes it possible to reduce stress concentration during firing caused by the difference in linear expansion coefficient between the dielectric layer and the internal electrode layer near the connection portion between the opposing portion of the internal electrode layer and the lead portion.

[0078] The coverage of the first intermediate region 31BA and the second intermediate region 32BA is preferably 55% or more. With such a configuration, difficulties in processing are less likely to arise when manufacturing the multilayer ceramic capacitor 1 of this embodiment.

[0079] The coverage of the first intermediate region 31BA and the second intermediate region 32BA is preferably 80% or less, which can further reduce stress concentration due to the electrostrictive effect when a voltage is applied.

[0080] The coverage of the first external electrode side region 31BB and the second external electrode side region 32BB is higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA, and is preferably 68% or more, thereby more reliably maintaining connectivity with the external electrodes.

[0081] The coverage of the first external electrode side region 31BB and the second external electrode side region 32BB may be higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA, and may be 88% or less.

[0082] The coverage of the first opposing portion side region 31BC and the second opposing portion side region 32BC is preferably higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA, and is preferably 68% or more, thereby further reducing stress concentration due to the electrostrictive effect when a voltage is applied and further reducing stress concentration during firing caused by the difference in linear expansion coefficient between the dielectric layer and the internal electrode layer.

[0083] The coverage of the first facing portion side region 31BC and the second facing portion side region 32BC may be higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA, and may be 88% or less.

[0084] The coverage of the first facing portion 31A and the second facing portion 32A is preferably higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA, and is preferably 75% or more, thereby ensuring the capacitance density and achieving the effects of this embodiment.

[0085] The coverage of the first facing portion 31A and the second facing portion 32A may be higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA, and may be 88% or less.

[0086] The coverage of the first intermediate region 31BA and the second intermediate region 32BA is preferably approximately 60% to 90% of the coverage of the first external electrode side region 31BB and the second external electrode side region 32BB, and more preferably approximately 60% to 83%.

[0087] The coverage of the first intermediate region 31BA and the second intermediate region 32BA is preferably approximately 60% to 90% of the coverage of the first opposing portion side region 31BC and the second opposing portion side region 32BC, and more preferably approximately 60% to 83%.

[0088] The coverage of the first intermediate region 31BA and the second intermediate region 32BA is preferably approximately 60% to 90% of the coverage of the first opposing portion 31A and the second opposing portion 32A, and more preferably approximately 60% to 83%.

[0089] If the coverage of the first intermediate region 31BA and the second intermediate region 32BA is reduced more than necessary, the effect of reducing stress concentration due to the electrostrictive effect when a voltage is applied will be limited. Furthermore, if the coverage of the first intermediate region 31BA and the second intermediate region 32BA is reduced too much, the balance may be lost and residual stress may occur. If the coverage is within the above range, the effects of this embodiment can be appropriately obtained.

[0090] It is preferable that the coverage of the first external electrode side region 31BB, the coverage of the first opposing portion side region 31BC, and the coverage of the first opposing portion 31A are substantially the same. It is also preferable that the coverage of the second external electrode side region 32BB, the coverage of the second opposing portion side region 32BC, and the coverage of the second opposing portion 32A are substantially the same. This makes it less likely that the overall balance will be lost and residual stress will be generated.

[0091] According to the multilayer ceramic capacitor 1 of this embodiment, it is possible to ensure capacitance density and maintain connectivity between the internal electrode layers and the external electrodes while reducing stress concentration due to the electrostrictive effect when a voltage is applied, and further to reduce stress concentration during firing caused by the difference in linear expansion coefficient between the dielectric layers and the internal electrode layers.

[0092] Second Embodiment A multilayer ceramic capacitor 1 according to a second embodiment will now be described. In the following description, the same components as those in the first embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted. FIG. 6A is an enlarged cross-sectional view schematically showing a portion indicated by R1 in FIG. 2 in the multilayer ceramic capacitor 1 according to the second embodiment. FIG. 6B is an enlarged cross-sectional view schematically showing a portion indicated by R2 in FIG. 2 in the multilayer ceramic capacitor 1 according to the second embodiment. FIGS. 6A and 6B show a portion of an LT cross section. FIGS. 6A and 6B show the dielectric layers 20, first internal electrode layers 31, second internal electrode layers 32, first external electrodes 40A, and second external electrodes 40B in the laminate 10.

[0093] In this embodiment, the coverage of the first facing portion-side region 31BC is substantially the same as the coverage of the first intermediate region 31BA, and the coverage of the second facing portion-side region 32BC is substantially the same as the coverage of the second intermediate region 32BA. Although this configuration may generate a slightly larger amount of stress than in the first embodiment, it is possible to ensure capacitance density, maintain connectivity between the internal electrode layers and the external electrodes, reduce stress concentration due to the electrostrictive effect when a voltage is applied, and reduce stress concentration during firing due to the difference in linear expansion coefficient between the dielectric layer and the internal electrode layer.

[0094] Next, a method for measuring the coverage as the coverage rate of the internal electrode layer 30 to the dielectric layer 20 in each embodiment will be described.

[0095] First, the internal electrode layer 30 and the dielectric layer 20 located in the center of the laminate 10 in the stacking direction T are peeled off by electrolytic peeling to expose the internal electrode layer 30. Next, each region of the internal electrode layer 30 (regions 31A, 31BA, 31BB, 31BC, 32A, 32BA, 32BB, and 32BC) is set as the measurement range, and laser microscope observation is performed. Here, the measurement range is set to, for example, a range of 25 μm × 25 μm. Note that, when the first internal electrode layer 31 is exposed, first, each region of the first internal electrode layer 31 (regions 31A, 31BA, 31BB, and 31BC) is set as the measurement range, and laser microscope observation is performed. Thereafter, the second internal electrode layer 32 is exposed by FIB (focused ion beam) processing. Then, each region (regions 32A, 32BA, 32BB, 32BC) of the second internal electrode layer 32 is set as the above-mentioned measurement range, and laser microscope observation is performed. Note that after the laser microscope observation, the first internal electrode layer 31 may be observed with the laser microscope.

[0096] Then, the area of ​​the internal electrode layer 30 in the measurement range is identified by analyzing the laser microscope image. Then, based on the area of ​​the analysis range and the area of ​​the area of ​​the internal electrode layer 30, the coverage rate of the internal electrode layer 30 with respect to the dielectric layer 20 is calculated as coverage by the following formula (1): Coverage (%) = (area of ​​internal electrode layer / area of ​​analysis range) × 100 (1)

[0097] The coverage of the intermediate region is calculated by averaging the values ​​of the first intermediate region 31BA and the second intermediate region 32BA. The coverages of the first intermediate region 31BA and the second intermediate region 32BA are measured at the center positions in the width direction W and length direction L of the pull-out portion.

[0098] The coverage of the external electrode side region is calculated as the average of the values ​​of the first external electrode side region 31BB and the second external electrode side region 32BB. The coverage of the first external electrode side region 31BB and the second external electrode side region 32BB is measured at a position 7% of the length of the lead-out portion in the length direction L from the end face position of the laminate toward the center of the laminate, and at the center position in the width direction W.

[0099] The coverage of the facing portion side region is calculated as the average of the values ​​of the first facing portion side region 31BC and the second facing portion side region 32BC. The coverage of the first facing portion side region and the second facing portion side region is measured at a position 7% of the length of the lead-out portion in the longitudinal direction L from the boundary between the facing portion and the lead-out portion toward the end face of the laminate, and at the center position in the width direction W.

[0100] The coverage of the opposing portions is calculated as the average value of the value of the first opposing portion 31A of the first internal electrode layer and the value of the second opposing portion 32A of the second internal electrode layer. The coverage of the first opposing portion 31A and the second opposing portion 32A is measured at the center position in the width direction W and length direction L of the opposing portions.

[0101] Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. The method for manufacturing the multilayer ceramic capacitor 1 of this embodiment is not limited as long as it satisfies the above-mentioned requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.

[0102] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. Both the dielectric sheet for the dielectric layer 20 and the conductive paste for the internal electrode layer 30 contain a binder and a solvent. The binder and solvent may be known. The paste made of a conductive material is, for example, a metal powder to which an organic binder and an organic solvent have been added.

[0103] On the dielectric sheet, the conductive paste for the internal electrode layer 30 is printed by, for example, screen printing or gravure printing using a printing plate patterned to have the shape of the internal electrode layer 30 of this embodiment. As a result, a dielectric sheet on which the pattern of the first internal electrode layer 31 is formed and a dielectric sheet on which the pattern of the second internal electrode layer 32 is formed are prepared. At this time, the thickness of the conductive paste applied to the location where the coverage is desired to be adjusted is adjusted to adjust the coverage of each region of the internal electrode layer to a desired value.

[0104] A predetermined number of dielectric sheets on which the pattern of the internal electrode layer 30 is not printed are stacked to form a portion that will become the first main surface side outer layer portion 12 on the first main surface TS1 side. Dielectric sheets on which the pattern of the first internal electrode layer 31 is printed and dielectric sheets on which the pattern of the second internal electrode layer 32 is printed are stacked alternately in sequence on top of that to form a portion that will become the internal layer portion 11. A predetermined number of dielectric sheets on which the pattern of the internal electrode layer 30 is not printed are stacked on top of this portion that will become the second main surface side outer layer portion 13 on the second main surface TS2 side. In this way, a laminated sheet is obtained.

[0105] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0106] The laminated block is then cut into individual pieces of a predetermined size to obtain a plurality of laminated chips, which may then be polished by barrel polishing or the like to round off corners and ridges.

[0107] Next, the laminated chip is fired to obtain the laminate 10. The firing temperature at this time depends on the materials of the dielectric layers 20 and the internal electrode layers 30, but is preferably, for example, 900° C. or higher and 1400° C. or lower.

[0108] A conductive paste that will become the base electrode layer 50 is applied to both end surfaces of the laminate 10. In this embodiment, the base electrode layer 50 is a baked layer. The baked layer can be formed by applying a conductive paste containing a glass component and a metal to the laminate 10 by a method such as dipping, and then performing a baking process. The temperature for the baking process at this time is preferably 700°C or higher and 900°C or lower.

[0109] The laminated chip before firing and the conductive paste applied to the laminated chip may be fired simultaneously. In this case, it is preferable to form the baked layer by adding a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are baked simultaneously to form the laminate 10 with the baked layer formed.

[0110] Thereafter, a plating layer is formed on the surface of the base electrode layer 50, which is made of a baked layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Furthermore, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layers. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0111] When the base electrode layer is formed as a thin film layer, the thin film layer is formed as the base electrode layer in the area where the external electrode is to be formed by masking or the like. The thin film layer is formed by a thin film formation method such as sputtering or vapor deposition. The thin film layer is a layer of metal particles deposited to a thickness of 10 μm or less.

[0112] When a conductive resin layer is provided, the conductive resin layer may be disposed so as to cover the baked layer. When providing the conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied onto the baked layer, and then heat-treated at a temperature of 250 to 550°C or higher. This causes the thermosetting resin to thermally harden, forming a conductive resin layer. The atmosphere during this heat treatment is N ２ In order to prevent the resin from scattering and the various metal components from being oxidized, the oxygen concentration is preferably 100 ppm or less.

[0113] Alternatively, the plating layer may be disposed directly on the exposed portions of the internal electrode layers 30 of the laminate 10 without providing a base electrode layer. In this case, the first end face LS1 and the second end face LS2 of the laminate 10 are plated, and a plating layer is formed on the exposed portions of the internal electrode layers 30. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred. Barrel plating is preferred as the plating method. If necessary, an upper plating layer formed on the surface of the lower plating layer may be formed using the same method as the lower plating layer.

[0114] Through the above manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0115] The multilayer ceramic capacitor 1 according to the embodiment described above provides the following advantages.

[0116] (1) The multilayer ceramic capacitor 1 according to the first embodiment includes a laminate 10 including a plurality of laminated dielectric layers 20 and a plurality of laminated internal electrode layers 30, a first main surface TS1 and a second main surface TS2 facing in a stacking direction T, a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 facing in a length direction L perpendicular to the stacking direction T and the width direction W, a first external electrode 40A arranged on the first end surface LS1 side, and a second external electrode 40B arranged on the second end surface LS2 side. The multilayer ceramic capacitor 1 includes a plurality of internal electrode layers 30, each of which includes a first internal electrode layer 31 and a second internal electrode layer 32. The first internal electrode layer 31 has a first lead portion 31B, one end of which is drawn to a first end face LS1 and connected to the first external electrode 40A, and a first opposing portion 31A, which is connected to the first lead portion 31B and faces the second internal electrode layer 32 arranged adjacent to the first internal electrode layer 32 in the stacking direction. The second internal electrode layer 32 has one end of which is drawn to a second end face LS2 and connected to the second external electrode 40B. and a second opposing portion 32A connected to the second lead portion 32B and opposing the first internal electrode layer 31 arranged adjacently in the stacking direction, the first lead portion 31B having a first external electrode side region 31BB near the connection portion with the first external electrode 40A, a first opposing portion side region 31BC near the connection portion with the first opposing portion 31A, and a first intermediate region 31BA between the first external electrode side region 31BB and the first opposing portion side region 31BC, and the second lead portion 32B has a second external electrode side region 31BB near the connection portion with the second external electrode 40B, The first intermediate region 31BA has an external electrode side region 32BB, a second opposing portion side region 32BC near the connection with the second opposing portion 32A, and a second intermediate region 32BA located between the second external electrode side region 32BB and the second opposing portion side region 32BC, and the coverage of the first intermediate region 31BA and the second intermediate region 32BA is lower than the coverage of the first external electrode side region 31BB and the second external electrode side region 32BB, and the coverage of the first intermediate region 31BA and the second intermediate region 32BA is lower than the coverage of the first opposing portion 31A and the second opposing portion 32A.

[0117] This ensures a high capacitance and maintains connectivity between the internal electrode layers and the external electrodes, while reducing stress concentration due to the electrostrictive effect when a voltage is applied.

[0118] (2) In the multilayer ceramic capacitor 1 described in (1), the coverage of the first opposing portion side region 31BC and the second opposing portion side region 32BC is higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA.

[0119] This makes it possible to reduce stress concentration during firing caused by the difference in linear expansion coefficient between the dielectric layer and the internal electrode layer near the connection between the opposing portion of the internal electrode layer and the lead portion.

[0120] (3) In the multilayer ceramic capacitor 1 described in (1) or (2), the coverage of the first intermediate region 31BA and the coverage of the second intermediate region 32BA are 55% or more.

[0121] With this configuration, difficulties in processing are unlikely to arise when manufacturing the multilayer ceramic capacitor 1 of this embodiment.

[0122] (4) In the multilayer ceramic capacitor 1 described in (1) to (3), the coverage of the first intermediate region 31BA and the second intermediate region 32BA is 80% or less.

[0123] This makes it possible to further reduce stress concentration due to the electrostrictive effect when a voltage is applied.

[0124] (5) In the multilayer ceramic capacitor 1 described in (1) to (4), the coverage of the first external electrode side region 31BB and the second external electrode side region 32BB is higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA, and is 68% or more.

[0125] This ensures that the connection to the external electrodes is maintained more reliably.

[0126] (6) In the multilayer ceramic capacitor 1 described in (1) to (5), the coverage of the first opposing portion side region 31BC and the second opposing portion side region 32BC is higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA, and is 68% or more.

[0127] This makes it possible to further reduce stress concentration due to the electrostrictive effect when a voltage is applied, and further to further reduce stress concentration during firing caused by the difference in linear expansion coefficient between the dielectric layers and the internal electrode layers.

[0128] (7) In the multilayer ceramic capacitor 1 described in (1) to (6), the coverage of the first opposing portion 31A and the second opposing portion 32A is higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA, and is 75% or more.

[0129] This ensures the capacitance density while achieving the effect of this embodiment. Experimental Example

[0130] <Sample Preparation> According to the manufacturing method described in the embodiment, a plurality of lots of multilayer ceramic capacitors were prepared by adjusting the coverage of each region of the internal electrode layer, and each lot was prepared as a sample. Then, using the prepared samples, the breakdown voltage due to electrostriction, the occurrence of cracks, and the connectivity between the internal electrodes and the external electrodes were evaluated.

[0131] First, according to the manufacturing method described in this embodiment, a multilayer ceramic capacitor having the following specifications was fabricated as an example sample.

[0132] ・Dimensions of multilayer ceramic capacitor: L×W×T = 3.2 mm×2.5 mm×2.5 mm ・Capacitance: 2.2 μF ・Rated voltage: 100 V ・Dielectric layer: BaTiO3 ・Thickness of dielectric layer: 1 μm ・Internal electrode layer: Ni ・Base electrode layer: Electrode containing conductive metal (Cu) and glass component ・Plating layer: Two-layer structure of Ni plating layer 2 μm and Sn plating layer 2 μm ・Length in the L direction of the internal electrode lead-out portion (end face side outer layer portion (L gap)): 220 μm

[0133] Here, each lot was manufactured under different manufacturing conditions, and the coverage of each region of the internal electrode layer was adjusted accordingly. In this experimental example, the thickness of the internal electrode layer was adjusted to a range of 0.5 μm to 1 μm, and the coverage of each region was adjusted. For each example and comparative example, the required number of samples for use in each evaluation was prepared. In addition, five samples for coverage measurement were prepared for each example and comparative example, and the average of the coverage measurements of the five samples was calculated as the coverage value of the example and comparative example. However, for the region where the conductive paste for the internal electrode layer was applied at the standard application thickness in this experimental example, the coverage was described as 88% based on the accumulated evaluation results.

[0134] <Evaluation of Breakdown Voltage Due to Electrostriction> The breakdown voltage of a multilayer ceramic capacitor varies depending on the degree of electrostriction. Therefore, electrostriction was evaluated using a BVD device that measures dielectric breakdown voltage (BVD). First, the external electrodes of each sample of the multilayer ceramic capacitor were placed on the electrodes of a BDV measurement device. Next, voltage application was initiated at room temperature under the following conditions: initial voltage: 0 V, voltage increase rate: 100 V / sec, and detection current (current value set to determine a defect): 10 mA. The voltage immediately before exceeding the detection current was recorded, and this value was defined as the electrostrictive breakdown voltage. For each example and comparative example, 20 samples were evaluated, and the average value was defined as the electrostrictive breakdown voltage for the example and comparative example.

[0135] <Evaluation of Crack Occurrence> To evaluate the occurrence of cracks due to the influence of residual stress during firing of multilayer ceramic capacitors, 100 multilayer ceramic capacitors were fabricated for each lot. The presence or absence of cracks was confirmed by polishing to expose the WT cross section passing through the center of the laminate and observing the exposed cross section with an optical microscope. Samples in which cracks were confirmed were counted as cracked samples (failures).

[0136] <Evaluation of Connectivity Between Internal and External Electrodes> For the evaluation of connectivity between the internal and external electrodes, 100 multilayer ceramic capacitors were fabricated from each lot. A rapid discharge test was performed on 100 samples, in which a rated voltage of 100 V was applied and then immediately short-circuited. The capacitance was then measured, and the rate of decrease from the capacitance value before the rapid discharge test was calculated. Samples with a decrease rate of 5% or more were counted as samples with poor connection (failures), as this indicated that some degree of disconnection had occurred at the connection between the internal and external electrodes due to the rapid discharge test. Experimental Example 1

[0137] As Experimental Example 1, an experiment was conducted to evaluate samples with varying coverage in the intermediate region of the lead-out portion of the internal electrode layer. As shown in Table 1, in the samples of Examples 1 to 5, the coverage of the first intermediate region 31BA and the second intermediate region 32BA was lower than the coverage of the first external electrode side region 31BB and the second external electrode side region 32BB, and the coverage of the first intermediate region 31BA and the second intermediate region 31BAB was lower than the coverage of the first opposing portion 31A and the second opposing portion 32A. The coverage of the intermediate region of the samples of Examples 1 to 5 was 80%, 73%, 62%, 55%, and 41%, while the coverage of the other regions was 88%. It was difficult to fabricate samples in which only the coverage of the intermediate region was less than 41%. As samples of Comparative Examples 1 and 2 for comparison, samples with uniform coverage of the facing portion and the lead-out portion were prepared.

[0138]

[0139] As shown in Table 1, in the evaluation of the electrostrictive breakdown voltage, the electrostrictive breakdown voltage of Examples 1 to 5, in which the coverage of the intermediate region was lower than the coverage of the external electrode side region and the coverage of the opposing portion, was higher than the electrostrictive breakdown voltage of Comparative Example 2, in which the coverage of the opposing portion and the lead-out portion was uniform.

[0140] In the evaluation of the connectivity between the internal electrodes and the external electrodes, no connection defects occurred in Examples 1 to 5. On the other hand, in Comparative Example 1, connection defects occurred.

[0141] In the evaluation of crack occurrence, no cracks occurred in Examples 1 to 4. The rate of crack occurrence was also extremely low in Example 5. On the other hand, the rate of crack occurrence in Comparative Example 2 was higher than in the Examples.

[0142] It is considered that in Comparative Example 1, which has lower coverage of the opposing portion than in Examples 1 to 5, the capacitance density is lower than in Examples 1 to 5.

[0143] From the above results, it was confirmed that the multilayer ceramic capacitors of Examples 1 to 5, in which the coverage of the intermediate region is lower than the coverage of the external electrode side region and the coverage of the opposing portion, can ensure capacitance density, maintain connectivity between the internal electrode layers and the external electrodes, and reduce stress concentration due to the electrostrictive effect when voltage is applied. The coverage of the intermediate region is preferably 41% or more, and more preferably 55% or more. The coverage of the intermediate region may be 41% or more and 88% or less, or may be 55% or more and 88% or less. Note that Comparative Example 2 showed a tendency for the electrostrictive breakdown voltage to be lower when the coverage, including the intermediate region, was high. Note that if the coverage of the intermediate region was too low, residual stress tended to occur during firing. Experimental Example 2

[0144] As Experimental Example 2, an experiment was conducted to evaluate samples in which the coverage of the external electrode side region of the lead-out portion of the internal electrode layer was varied. As shown in Table 2, the samples of Examples 1 to 3 are samples in which the coverage of the first intermediate region 31BA and the second intermediate region 32BA is lower than the coverage of the first external electrode side region 31BB and the second external electrode side region 32BB, and the coverage of the first intermediate region 31BA and the second intermediate region 31BAB is lower than the coverage of the first opposing portion 31A and the second opposing portion 32A. The coverage of the intermediate region of the samples of Examples 1 to 3 was 62%, and the coverage of the external electrode side region was 88%, 74%, and 68%, respectively. The sample of Comparative Example 1 has a coverage of the external electrode side region of 60%, and the coverage of the first external electrode side region 31BB and the second external electrode side region 32BB is lower than the coverage of the first intermediate region 31BA and the second intermediate region 32BA.

[0145]

[0146] As shown in Table 2, in the evaluation of the breakdown voltage due to electrostriction and the evaluation of crack occurrence, Examples 1 to 3 and Comparative Example 1 all showed good results.

[0147] However, in the evaluation of the connectivity between the internal electrodes and the external electrodes, while Examples 1 to 3 gave good results, Comparative Example 1 suffered from poor connection.

[0148] From the above results, it was confirmed that the multilayer ceramic capacitors of Examples 1 to 3, in which the coverage of the intermediate region is lower than the coverage of the external electrode side region and the coverage of the opposing portion, can ensure capacitance density, maintain connectivity between the internal electrode layers and the external electrodes, and reduce stress concentration due to the electrostrictive effect when voltage is applied. The coverage of the external electrode side region is preferably higher than the coverage of the intermediate region and is 68% or more. Experimental Example 3

[0149] As Experimental Example 3, an experiment was conducted to evaluate samples in which the coverage of the opposing portion side region of the lead portion of the internal electrode layer was varied. As shown in Table 3, the samples of Examples 1 to 4 are samples in which the coverage of the first intermediate region 31BA and the second intermediate region 32BA is lower than the coverage of the first external electrode side region 31BB and the second external electrode side region 32BB, and the coverage of the first intermediate region 31BA and the second intermediate region 31BAB is lower than the coverage of the first opposing portion 31A and the second opposing portion 32A. The coverage of the intermediate region of the samples of Examples 1 to 4 was 62%, and the coverage of the opposing portion side region was 88%, 75%, 68%, and 64%, respectively.

[0150]

[0151] As shown in Table 3, in the evaluation of the breakdown voltage due to electrostriction and the evaluation of the connectivity between the internal electrodes and the external electrodes, Examples 1 to 4 all showed good results.

[0152] In the evaluation of crack occurrence, no cracks occurred in Examples 1 to 3. In Example 4 as well, the rate of crack occurrence was extremely low.

[0153] From the above results, it was confirmed that the multilayer ceramic capacitors of Examples 1 to 4, in which the coverage of the intermediate region is lower than the coverage of the external electrode side region and the coverage of the opposing region, can ensure capacitance density, maintain connectivity between the internal electrode layers and the external electrodes, and reduce stress concentration due to the electrostrictive effect when voltage is applied. The coverage of the opposing region is higher than the coverage of the intermediate region, and is preferably 64% or more, more preferably 68% or more. Note that when the coverage of the opposing region is lower, a tendency for residual stress to occur during firing was observed. Experimental Example 4

[0154] As Experimental Example 4, an experiment was conducted to evaluate samples in which the coverage of the opposing portions of the internal electrode layers was varied. As shown in Table 4, the samples of Examples 1 to 3 are samples in which the coverage of the first intermediate region 31BA and the second intermediate region 32BA is lower than the coverage of the first external electrode side region 31BB and the second external electrode side region 32BB, and the coverage of the first intermediate region 31BAA and the second intermediate region 31BAB is lower than the coverage of the first opposing portion 31A and the second opposing portion 32A. The coverage of the intermediate region of the samples of Examples 1 to 3 was 62%, and the coverage of the opposing portion was 88%, 75%, and 71%, respectively.

[0155]

[0156] As shown in Table 4, Examples 1 to 3 showed good results in the evaluation of the breakdown voltage due to electrostriction and the evaluation of the connectivity between the internal and external electrodes.

[0157] In the evaluation of crack occurrence, no cracks occurred in Examples 1 and 2. In Example 3, the rate of crack occurrence was also extremely low.

[0158] From the above results, it was confirmed that the multilayer ceramic capacitors of Examples 1 to 3, in which the coverage of the intermediate region is lower than the coverage of the external electrode side region and the coverage of the opposing portion, can ensure capacitance density, maintain connectivity between the internal electrode layers and the external electrodes, and reduce stress concentration due to the electrostrictive effect when voltage is applied. The coverage of the opposing portion is higher than the coverage of the intermediate region, and is preferably 71% or more, more preferably 75% or more. Note that when the coverage of the opposing portion is lower, a tendency for residual stress to occur during firing was observed.

[0159] Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments and can be embodied in various forms without departing from the spirit of the present invention. The present invention includes the following combinations.

[0160] <1> A multilayer ceramic capacitor comprising: a laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, the laminate including a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction; a first external electrode arranged on the first end surface side; and a second external electrode arranged on the second end surface side, wherein the plurality of internal electrode layers include a first internal electrode layer and a second internal electrode layer, the first internal electrode layer having a first lead portion, one end of which is extended to the first end surface and connected to the first external electrode, and a first opposing portion, which is connected to the first lead portion and faces the second internal electrode layer arranged adjacent to the second internal electrode layer in the lamination direction; a second opposing portion connected to a lead portion and opposing the first internal electrode layer arranged adjacent to the lead portion in the stacking direction, the first lead portion having a first external electrode side region near a connection portion with the first external electrode, a first opposing portion side region near a connection portion with the first opposing portion, and a first intermediate region between the first external electrode side region and the first opposing portion side region, the second lead portion having a second external electrode side region near a connection portion with the second external electrode, a second opposing portion side region near a connection portion with the second opposing portion, and a second intermediate region between the second external electrode side region and the second opposing portion side region, wherein coverage of the first intermediate region and the second intermediate region is lower than coverage of the first external electrode side region and the second external electrode side region, and coverage of the first intermediate region and the second intermediate region is lower than coverage of the first opposing portion and the second opposing portion.

[0161] <2> The multilayer ceramic capacitor according to <1>, wherein the coverage of the first opposing portion side region and the second opposing portion side region is higher than the coverage of the first intermediate region and the second intermediate region.

[0162] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the coverage of the first intermediate region and the coverage of the second intermediate region are 55% or more.

[0163] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the coverage of the first intermediate region and the second intermediate region is 80% or less.

[0164] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the coverage of the first external electrode side region and the second external electrode side region is higher than the coverage of the first intermediate region and the second intermediate region and is 68% or more.

[0165] <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the coverage of the first opposing portion side region and the second opposing portion side region is higher than the coverage of the first intermediate region and the second intermediate region and is 68% or more.

[0166] <7> The multilayer ceramic capacitor according to any one of <1> to <6>, wherein the coverage of the first opposing portion and the second opposing portion is higher than the coverage of the first intermediate region and the second intermediate region and is 75% or more.

[0167] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 31A First opposing portion 31B First lead portion 31BA First intermediate region 31BB First external electrode side region 31BC First opposing portion side region 32 Second internal electrode layer 32A Second opposing portion 32B Second lead portion 32BA Second intermediate region 32BB Second external electrode side region 32BC Second opposing portion side region 40 External electrode 40A First external electrode 40B Second external electrode 50 Base electrode layer 50A First base electrode layer 50B Second base electrode layer L Length direction T Stacking direction W Width direction LS1 First end face LS2 Second end face TS1 First main surface TS2 Second main surface WS1 First side WS2 Second side

Claims

1. a laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, the laminate including a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction; a first external electrode disposed on the first end face side; a second external electrode disposed on the second end face side; A multilayer ceramic capacitor comprising: the plurality of internal electrode layers include a first internal electrode layer and a second internal electrode layer, the first internal electrode layer has a first lead portion, one end of which is led out to the first end face and connected to the first external electrode, and a first opposing portion, which is connected to the first lead portion and opposed to the second internal electrode layer disposed adjacent to the first internal electrode layer in the stacking direction, the second internal electrode layer has a second lead portion, one end of which is led out to the second end face and connected to the second external electrode, and a second opposing portion, which is connected to the second lead portion and opposed to the first internal electrode layer disposed adjacent to the first internal electrode layer in the stacking direction, the first lead portion has a first external electrode side region in the vicinity of a connection portion with the first external electrode, a first opposing portion side region in the vicinity of a connection portion with the first opposing portion, and a first intermediate region between the first external electrode side region and the first opposing portion side region, the second lead portion has a second external electrode side region in the vicinity of a connection portion with the second external electrode, a second opposing portion side region in the vicinity of a connection portion with the second opposing portion, and a second intermediate region between the second external electrode side region and the second opposing portion side region, coverage of the first intermediate region and the second intermediate region is lower than coverage of the first external electrode side region and the second external electrode side region; The multilayer ceramic capacitor, wherein the coverage of the first intermediate region and the second intermediate region is lower than the coverage of the first opposing portion and the second opposing portion.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein the coverage of the first opposing portion side region and the second opposing portion side region is higher than the coverage of the first intermediate region and the second intermediate region.

3. 3. The multilayer ceramic capacitor according to claim 1, wherein the coverage of the first intermediate region and the coverage of the second intermediate region are 55% or more.

4. 3. The multilayer ceramic capacitor according to claim 1, wherein the coverage of the first intermediate region and the second intermediate region is 80% or less.

5. 3. The multilayer ceramic capacitor according to claim 1, wherein the coverage of the first external electrode side region and the second external electrode side region is higher than the coverage of the first intermediate region and the second intermediate region, and is 68% or more.

6. 3. The multilayer ceramic capacitor according to claim 1, wherein the coverage of the first opposing portion side region and the second opposing portion side region is higher than the coverage of the first intermediate region and the second intermediate region and is 68% or more.

7. 3. The multilayer ceramic capacitor according to claim 1, wherein the coverage of the first opposing portion and the second opposing portion is higher than the coverage of the first intermediate region and the second intermediate region, and is 75% or more.