Driver circuit and voltage generation circuit

Abstract

Provided is a driver circuit (1) that outputs, to an amplifier that outputs an output PWM signal indicating an output voltage, a first drive signal and a second drive signal for driving the amplifier, the driver circuit outputting, on the basis of an input PWM signal input to the driver circuit, the first drive signal, which is a PWM signal having the same phase as the input PWM signal, and the second drive signal, which is a PWM signal having an opposite phase to the input PWM signal. On the basis of the first drive signal and the second drive signal output from the driver circuit, the amplifier outputs an output PWM signal having an opposite phase to the first drive signal and the same phase as the second drive signal. If the duty ratio of the input PWM signal input to the driver circuit is less than a prescribed duty ratio, the driver circuit increases the pulse width of the first drive signal to be output inversely with the pulse width of the input PWM signal.

Description

Driver circuit and voltage generation circuit

[0001] The present disclosure relates to a driver circuit and a voltage generation circuit.

[0002] An envelope tracking amplifier is a well-known example of a conventional high-efficiency amplifier. An envelope tracking amplifier dynamically changes the drain voltage of a transistor in the amplifier in accordance with the envelope of an input signal, thereby maintaining a state close to saturation and improving power efficiency. Here, a GaN circuit, for example, is used to dynamically change the drain voltage in accordance with the envelope of the input signal (see, for example, Non-Patent Document 1).

[0003] An example configuration of a drain voltage generation circuit used in an envelope tracking amplifier is shown in Fig. 10. As shown in Fig. 10, the drain voltage generation circuit is mainly composed of a front-stage driver circuit and a rear-stage GaN circuit (amplifier). The driver circuit outputs two PWM signals (IN+: high-side signal, IN-: low-side signal) in response to a PWM signal (hereinafter also referred to as "input PWM signal") that is an input signal. In this case, the high-side signal is output in phase with the input PWM signal, and the low-side signal is output in anti-phase with the input PWM signal.

[0004] The GaN circuit is driven by two PWM signals (high-side signal and low-side signal) output from the driver circuit, and outputs a PWM signal (hereinafter also referred to as the "output PWM signal") corresponding to the input PWM signal input to the driver circuit. At this time, the output PWM signal is output in opposite phase to the high-side signal and in phase with the low-side signal. In other words, the output PWM signal is a signal with the logic of the input PWM signal inverted. The output PWM signal output from the GaN circuit is flattened (time-averaged) by an LPF, and the signal obtained thereby is output as a signal indicating the drain voltage (Vout in FIG. 10).

[0005] Saiki et al., "High-speed, high-efficiency GaN switching envelope amplifier capable of operating in an 80 MHz modulation band," Institute of Electronics, Information and Communication Engineers 2021 Society Conference

[0006] In order for the signal Vout output from the drain voltage generation circuit to accurately track the envelope of the input signal input to the amplifier, the GaN circuit needs to output, as an output PWM signal, a signal indicating an output voltage (time integral value of the output pulse) that is accurately proportional to the duty ratio of the input PWM signal input to the driver circuit. However, in a region where the duty ratio of the input PWM signal input to the driver circuit is close to 0% or 100%, the output PWM signal is affected by the rise time and fall time (trf: time rise fall) of the output PWM signal output from the GaN circuit, which causes a problem of degraded accuracy of the output voltage of the drain voltage generation circuit.

[0007] For example, when the trf of the output PWM signal output from the GaN circuit is large, if the duty ratio of the input PWM signal input to the driver circuit is less than a predetermined duty ratio, there is a problem in that the relationship between the duty ratio of the input PWM signal and the output voltage of the drain voltage generation circuit becomes non-linear. Figure 11 shows the relationship between the duty ratio of the input PWM signal input to the driver circuit and the output voltage of the drain voltage generation circuit. In this example, as described above, it is assumed that the input PWM signal input to the driver circuit and the output PWM signal output from the GaN circuit have inverted logic, and as shown in Figure 11, a signal obtained by inverting the logic of the high-side signal output from the driver circuit is output from the GaN circuit as the output PWM signal.

[0008] Assume that the duty ratio of the input PWM signal input to the driver circuit is less than the predetermined duty ratio indicated by the symbol x. In other words, a signal with a pulse width smaller than the sum of the rise time and fall time of the output PWM signal output from the GaN circuit is input to the driver circuit. In this case, if the trf of the output PWM signal output from the GaN circuit is large, the output PWM signal cannot fall sufficiently, increasing the equivalent pulse width of the output PWM signal and increasing the output voltage of the drain voltage generation circuit. As a result, in the region to the left of the symbol x in FIG. 11 , the linearity of the output voltage of the drain voltage generation circuit relative to the duty ratio of the input PWM signal may be lost. Therefore, to maintain this linearity, it is necessary to lower the output voltage of the drain voltage generation circuit (the voltage indicated by the output PWM signal output from the GaN circuit) in the region where the duty ratio of the input PWM signal is less than the predetermined duty ratio.

[0009] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a driver circuit that drives an amplifier that outputs an output PWM signal that indicates an output voltage, and that can improve the linearity of the output voltage indicated by the output PWM signal relative to the duty ratio of the input PWM signal.

[0010] A driver circuit according to the present disclosure is a driver circuit that outputs a first drive signal and a second drive signal for driving an amplifier that outputs an output PWM signal indicating an output voltage, the driver circuit outputs, based on an input PWM signal that is a PWM signal input to the driver circuit, the first drive signal being a PWM signal in phase with the input PWM signal and the second drive signal being a PWM signal in opposite phase to the input PWM signal, the amplifier outputs, based on the first drive signal and the second drive signal output from the driver circuit, an output PWM signal being a signal in opposite phase to the first drive signal and in phase with the second drive signal, and the driver circuit is characterized in that, when the duty ratio of the input PWM signal input to the driver circuit is less than a predetermined duty ratio, the driver circuit increases the pulse width of the first drive signal that it outputs in inverse proportion to the pulse width of the input PWM signal.

[0011] According to the present disclosure, it is possible to obtain a driver circuit that drives an amplifier that outputs an output PWM signal that indicates an output voltage, and that can improve the linearity of the output voltage indicated by the output PWM signal relative to the duty ratio of the input PWM signal.

[0012] 1 is a diagram showing a configuration example of a driver circuit according to a first embodiment. FIG. 2 is a diagram showing a configuration example of a SW signal generation circuit according to the first embodiment. FIG. 3 is a diagram showing configuration examples of a first control signal generation circuit and a second control signal generation circuit according to the first embodiment. FIG. 4 is a diagram showing a configuration example of a first logical operation circuit according to the first embodiment. FIG. 5 is a diagram showing a configuration example of a second logical operation circuit according to the first embodiment. FIG. 6 is a timing chart showing an operation example of the driver circuit 1 according to the first embodiment, and is a timing chart of each signal when pulse width correction is performed. FIG. 7 is a timing chart of each signal processed by the first logical operation circuit when pulse width correction is not performed in the first embodiment. FIG. 8 is a timing chart of each signal processed by the second logical operation circuit when pulse width correction is not performed in the first embodiment. FIG. 9 is a timing chart of each signal processed by the first logical operation circuit when pulse width correction is performed in the first embodiment. 1 is a truth table of each signal processed by the first logical operation circuit when the discharge voltage from the capacitor exceeds a threshold voltage in embodiment 1. FIG. 2 is a truth table of each signal processed by the second logical operation circuit when the discharge voltage from the capacitor is equal to or lower than the threshold voltage in embodiment 1. FIG. 3 is a truth table of each signal processed by the second logical operation circuit when the discharge voltage from the capacitor exceeds a threshold voltage in embodiment 1. FIG. 4 is a diagram showing an example of the configuration of a conventional drain voltage generation circuit. FIG. 5 is a diagram showing the relationship between the duty ratio of an input PWM signal input to a driver circuit and the output voltage of the drain voltage generation circuit in a conventional drain voltage generation circuit.

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

[0014] FIG. 1 is a diagram showing an example configuration of a driver circuit 1 according to a first embodiment. The driver circuit 1 shown in FIG. 1 drives a GaN circuit constituting a drain voltage generation circuit used in an envelope tracking amplifier. The driver circuit 1 receives an input PWM signal and generates two PWM signals (Hout, Lout) for driving the GaN circuit. Of these, Hout corresponds to the high-side signal described above, and Lout corresponds to the low-side signal described above. In the following description, the signal Hout will also be referred to as a "first drive signal," and the signal Lout will also be referred to as a "second drive signal." The driver circuit 1 includes, for example, a signal control circuit 31 and an adder circuit 32, as shown in FIG. 1 .

[0015] <Signal Control Circuit 31> The signal control circuit 31 is a circuit that generates signals Vt1 and Vt2 that perform pulse width correction of two PWM signals (Hout, Lout) for driving the GaN circuit, using a high-side input signal Hin and a low-side input signal Lin obtained from the input PWM signal input to the driver circuit 1. In the following description, the signals Vt1 and Vt2 are also referred to as "correction pulses." As shown in FIG. 1 , the signal control circuit 31 is configured to include a SW signal generation circuit 33, a control signal generation circuit (first control signal generation circuit) 34, and a control signal generation circuit (second control signal generation circuit) 35.

[0016] The SW signal generation circuit 33 generates signals VSW1 and VSW2 using the high-side input signal Hin and the low-side input signal Lin, and outputs the generated signals VSW1 and VSW2 to the control signal generation circuit 34 and the control signal generation circuit 35. The SW signal generation circuit 33 also generates signals Hin1 and / Hin1 using the high-side input signal Hin and the low-side input signal Lin, and outputs the generated signals Hin1 and / Hin1 to the adder circuit 32. The signal / Hin1 is an inverted signal of the signal Hin1, and " / " indicates an overbar.

[0017] The control signal generating circuit 34 uses the signals VSW1 and VSW2 output from the SW signal generating circuit 33 to generate a signal Vt1 that performs pulse width correction on the two PWM signals (Hout, Lout), and outputs the generated signal Vt1 to the adding circuit 32.

[0018] The control signal generating circuit 35 uses the signals VSW1 and VSW2 output from the SW signal generating circuit 33 to generate a signal Vt2 that performs pulse width correction on the two PWM signals (Hout, Lout), and outputs the generated signal Vt2 to the adding circuit 32.

[0019] <Adder Circuit 32> The adder circuit 32 is a circuit that performs pulse width correction on the signals Hout and Lout using the signals Vt1 and Vt2 generated by the signal control circuit 31 (control signal generation circuits 34, 35). The adder circuit 32 includes a logical operation circuit (first logical operation circuit) 36, a logical operation circuit (second logical operation circuit) 37, a logical sum circuit 38, and a logical product circuit 39, as shown in FIG.

[0020] The logical operation circuit 36 ​​is a circuit that adds the signals Vt1 and Vt2 generated by the signal control circuit 31 (control signal generation circuits 34, 35) to the high-side input signal Hin of the driver circuit 1. The logical operation circuit 36 ​​calculates signals Hout1 and Hout2 by addition, and outputs the calculated signals Hout1 and Hout2 to the logical sum circuit 38.

[0021] The logical operation circuit 37 is a circuit that adds the signals Vt1 and Vt2 generated by the signal control circuit 31 (control signal generation circuits 34, 35) to the low-side input signal Lin of the driver circuit 1. The logical operation circuit 37 calculates the signals Lout1 and Lout2 by addition, and outputs the calculated signals Lout1 and Lout2 to the logical product circuit 39.

[0022] The logical sum circuit 38 calculates the logical sum of the signals Hout1 and Hout2 output from the logical operation circuit 36, and outputs the resulting signal Hout. The logical product circuit 39 calculates the logical product of the signals Lout1 and Lout2 output from the logical operation circuit 37, and outputs the resulting signal Lout.

[0023] The signal Hout output from the logical sum circuit 38 and the signal Lout output from the logical product circuit 39 become input signals to, for example, a GaN circuit connected in a subsequent stage to the driver circuit 1. The GaN circuit is driven by the input signals Hout and Lout, and outputs a signal indicating an output voltage according to the duty ratio of the input PWM signal input to the driver circuit 1.

[0024] Next, an example of the configuration of each of the above circuits will be described. <SW signal generation circuit 33> Fig. 2 is a diagram showing an example of the configuration of the SW signal generation circuit 33. As shown in Fig. 2, the SW signal generation circuit 33 is configured to include rising edge triggered T flip-flop circuits 41 and 42, inverter circuits 43 and 44, and logical product circuits 45 and 46.

[0025] The rising-edge triggered T flip-flop circuit 41 is a circuit that can obtain a desired voltage waveform by system reset, and receives the high-side input signal Hin and generates a signal Hin1. The rising-edge triggered T flip-flop circuit 41 outputs the generated signal Hin1 to the logical operation circuit 36, the inverter circuit 43, and the logical product circuit 46.

[0026] The rising edge triggered T flip-flop circuit 42 is a circuit that can obtain a desired voltage waveform by system reset, and receives the low side input signal Lin and generates a signal Lin1. The rising edge triggered T flip-flop circuit 42 outputs the generated signal Lin1 to the inverter circuit 44 and the logical product circuit 45.

[0027] The inverter circuit 43 inverts the signal Hin1 to generate a signal / Hin1, and outputs the generated signal / Hin1 to the logical operation circuit 36 ​​and the logical product circuit 45.

[0028] The inverter circuit 44 inverts the signal Lin1 to generate a signal / Lin1, and outputs the generated signal / Lin1 to the AND circuit 46.

[0029] The logical product circuit 45 calculates the logical product of the signal / Hin1 and the signal Lin1, and outputs the resulting signal VSW1 to the control signal generation circuits 34 and 35.

[0030] The AND circuit 46 calculates the logical product of the signal Hin1 and the signal / Lin1, and outputs the resulting signal VSW2 to the control signal generation circuits 34 and 35. The signals VSW1 and VSW2 define the charging time of a capacitor 516 included in the control signal generation circuits 34 and 35, which will be described later.

[0031] <Control Signal Generation Circuits 34 and 35> Figure 3 is a diagram showing an example configuration of the control signal generation circuits 34 and 35. As shown in Figure 3, the control signal generation circuits 34 and 35 are configured to include switches 511 and 512, resistors 513 to 515, a capacitor 516, and a switch 517. Note that the basic configuration examples of the control signal generation circuits 34 and 35 are the same, and only the signals input to each element are different, so here, configuration examples of both circuits will be explained together in one diagram.

[0032] In the control signal generating circuits 34 and 35, a switch 511, a resistor 513, a switch 512, and a resistor 515 are connected in series between the power supply voltage Vdd and ground. In the control signal generating circuits 34 and 35, a capacitor 516 and a resistor 514 are connected in parallel between the signal line connecting the resistor 513 and the switch 512 and ground.

[0033] In the control signal generating circuits 34 and 35, a switch 517 having a threshold voltage Vth is connected between the signal line connecting the resistor 513 and the switch 512 and the output terminal that outputs the signal Vt1 or Vt2.

[0034] The signal VSW1 or VSW2 is input to the switches 511 and 512. Specifically, in the control signal generation circuit 34, the signal VSW1 is input to the switch 511, and the signal VSW2 is input to the switch 512. In the control signal generation circuit 35, the signal VSW2 is input to the switch 511, and the signal VSW1 is input to the switch 512. The switches 511 and 512 are controlled to be turned on or off by the signal VSW1 or VSW2.

[0035] Furthermore, the on / off state of the switch 517 is controlled in accordance with the magnitude relationship between the discharge voltage VM1 or VM2 from the capacitor 516 and the threshold voltage Vth of the switch 517. Specifically, in the control signal generation circuit 34, the on / off state of the switch 517 is controlled in accordance with the magnitude relationship between the discharge voltage VM1 from the capacitor 516 and the threshold voltage Vth. In the control signal generation circuit 34, when the discharge voltage VM1 from the capacitor 516 exceeds the threshold voltage Vth, the switch 517 is turned on, and when the switch 517 is turned on, a signal Vt1 for performing the pulse width correction is output (the level of the signal Vt1 becomes High).

[0036] In the control signal generating circuit 35, the switch 517 is controlled to be turned on or off depending on the magnitude relationship between the discharge voltage VM2 from the capacitor 516 and the threshold voltage Vth. In the control signal generating circuit 35, when the discharge voltage VM2 from the capacitor 516 exceeds the threshold voltage Vth, the switch 517 is turned on, and when the switch 517 is turned on, a signal Vt2 for performing the pulse width correction is output (the level of the signal Vt2 becomes High).

[0037] <Logical Operation Circuit 36> Fig. 4 is a diagram showing an example of the configuration of the logical operation circuit 36. The logical operation circuit 36 ​​includes inverter circuits 61 and 62, logical product circuits 63 to 66, and logical sum circuits 67 and 68, as shown in Fig. 4, for example.

[0038] The inverter circuit 61 generates a signal / Vt1 by inverting the signal Vt1 output from the control signal generation circuit 34. The inverter circuit 61 outputs the generated signal / Vt1 to the AND circuit 64.

[0039] The inverter circuit 62 generates a signal / Vt2 by inverting the signal Vt2 output from the control signal generation circuit 35. The inverter circuit 62 outputs the generated signal / Vt2 to the AND circuit 66.

[0040] The logical product circuit 63 calculates the logical product of the signal Hin 1 output from the SW signal generating circuit 33 and the signal Vt 1 , and outputs the resulting signal to the logical sum circuit 67 .

[0041] The logical product circuit 64 calculates the logical product of the high-side input signal Hin of the driver circuit 1, the signal Hin1 output from the SW signal generation circuit 33, and the signal / Vt1 output from the inverter circuit 61, and outputs the resulting signal to the logical sum circuit 67.

[0042] The logical product circuit 65 calculates the logical product of the signal / Hin1 output from the SW signal generating circuit 33 and the signal Vt2, and outputs the resulting signal to the logical sum circuit 68.

[0043] The logical product circuit 66 calculates the logical product of the high-side input signal Hin of the driver circuit 1, the signal / Hin1 output from the SW signal generation circuit 33, and the signal / Vt2 output from the inverter circuit 62, and outputs the resulting signal to the logical sum circuit 68.

[0044] The OR circuit 67 calculates the logical sum of the signals output from the AND circuits 63 and 64, and outputs the resulting signal Hout1 to the OR circuit 38.

[0045] The OR circuit 68 calculates the logical sum of the signals output from the AND circuits 65 and 66, and outputs the resulting signal Hout2 to the OR circuit 38.

[0046] <Logical Operation Circuit 37> Fig. 5 is a diagram showing an example of the configuration of the logical operation circuit 37. For example, as shown in Fig. 5, the logical operation circuit 37 includes a falling edge triggered T flip-flop circuit 71, inverter circuits 72 to 74, logical product circuits 75 to 80, and logical sum circuits 81 and 82.

[0047] The falling-edge triggered T flip-flop circuit 71 is a circuit that can obtain a desired voltage waveform by system reset, and receives the low-side input signal Lin and generates a signal Lin2. The falling-edge triggered T flip-flop circuit 71 outputs the generated signal Lin2 to the inverter circuit 72 and the AND circuits 76 and 78.

[0048] The inverter circuit 72 inverts the signal Lin2 to generate a signal / Lin2, and outputs the generated signal / Lin2 to the AND circuits 75, 79, and 80.

[0049] The inverter circuit 73 generates a signal / Vt1 by inverting the signal Vt1 output from the control signal generation circuit 34. The inverter circuit 73 outputs the generated signal / Vt1 to AND circuits 75 and 77.

[0050] The inverter circuit 74 generates a signal / Vt2 by inverting the signal Vt2 output from the control signal generating circuit 35. The inverter circuit 74 outputs the generated signal / Vt2 to AND circuits 78 and 80.

[0051] The logical product circuit 75 calculates the logical product of the low-side input signal Lin, the signal / Lin2 output from the inverter circuit 72, and the signal / Vt1 output from the inverter circuit 73, and outputs the resulting signal to the logical sum circuit 81.

[0052] The logical product circuit 76 calculates the logical product of the low-side input signal Lin, the signal Lin2 output from the falling edge triggered T flip-flop circuit 71, and the signal Vt1 output from the control signal generation circuit 34, and outputs the resulting signal to the logical sum circuit 81.

[0053] The logical product circuit 77 calculates the logical product of the signal Vt 1 output from the control signal generating circuit 34 and the signal / Vt 1 output from the inverter circuit 73 , and outputs the resulting signal to the logical sum circuit 81 .

[0054] The logical product circuit 78 calculates the logical product of the low-side input signal Lin, the signal Lin2 output from the falling edge triggered T flip-flop circuit 71, and the signal / Vt2 output from the inverter circuit 74, and outputs the resulting signal to the logical sum circuit 82.

[0055] The logical product circuit 79 calculates the logical product of the low-side input signal Lin, the signal / Lin2 output from the inverter circuit 72, and the signal Vt2 output from the control signal generation circuit 35, and outputs the resulting signal to the logical sum circuit 82.

[0056] The logical product circuit 80 calculates the logical product of the signal / Lin2 output from the inverter circuit 72 and the signal / Vt2 output from the inverter circuit 74, and outputs the resulting signal to the logical sum circuit 82.

[0057] The logical sum circuit 81 calculates the logical sum of the signals output from the logical product circuits 75 to 77 and outputs the resulting signal Lout 1 to the logical product circuit 39 .

[0058] The logical sum circuit 82 calculates the logical sum of the signals output from the logical product circuits 78 to 80 and outputs the resulting signal Lout 2 to the logical product circuit 39 .

[0059] Next, an example of the operation of the driver circuit 1 according to the first embodiment will be described with reference to the timing charts shown in FIG. 6 and FIGS. 7A to 7D.

[0060] In the timing charts shown in Figures 6 and 7A to 7D, the horizontal axis represents time. Also, Hin, Lin, Hin1, Lin1, / Hin1, / Lin1, Lin2, / Lin2, VSW1, VSW2, VM1, Vt1, VM2, Vt2, Hout1, Hout2, Lout1, Lout2, Hout, and Lout, shown on the vertical axis, represent input signals to and output signals from each node shown in Figures 1 to 5. In these charts, the voltage waveforms of each input signal and each output signal are represented by two values: High or Low.

[0061] Fig. 6 shows a timing chart of each signal when pulse width correction is performed. Fig. 7A shows a timing chart of each signal processed by the logical operation circuit 36 ​​when pulse width correction is not performed, and Fig. 7B shows a timing chart of each signal processed by the logical operation circuit 37 when pulse width correction is not performed. Fig. 7C shows a timing chart of each signal processed by the logical operation circuit 36 ​​when pulse width correction is performed, and Fig. 7D shows a timing chart of each signal processed by the logical operation circuit 37 when pulse width correction is performed.

[0062] First, the SW signal generation circuit 33 generates a signal Hin1 from the high-side input signal Hin of the driver circuit 1 via a rising-edge triggered T flip-flop circuit 41. The SW signal generation circuit 33 also generates a signal Lin1 from the low-side input signal Lin of the driver circuit 1 via a rising-edge triggered T flip-flop circuit 42.

[0063] The SW signal generating circuit 33 also generates, via an inverter circuit 43 and a logical product circuit 45, a signal VSW1 indicating the logical product of a signal / Hin1, which is the inverted version of the high-side input signal Hin, and the signal Lin1.

[0064] The SW signal generating circuit 33 also generates a signal VSW2 indicating the logical product of the signal / Lin1, which is the inverted version of the signal Lin1, and the signal Hin1, via an inverter circuit 44 and a logical product circuit 46.

[0065] The signals VSW1 and VSW2 generated by the SW signal generating circuit 33 control the switches 511 and 512 of the control signal generating circuits 34 and 35.

[0066] Specifically, the on / off of switch 511 of control signal generation circuit 34 is controlled by signal VSW1, and the on / off of switch 512 of control signal generation circuit 34 is controlled by signal VSW2. By the operation of these switches, charging and discharging of capacitor 516 in control signal generation circuit 34 is controlled.

[0067] For example, in the control signal generating circuit 34, when the signal VSW1 is high, the switch 511 is turned on, thereby charging the capacitor 516. Then, when the signal VSW2 becomes high after the signal VSW1 becomes low, the switch 511 is turned off and the switch 512 is turned on, causing the capacitor 516 to discharge.

[0068] At this time, if the discharge voltage VM1 from the capacitor 516 exceeds the threshold voltage Vth of the switch 517, the switch 517 is connected to the power supply voltage Vdd (turned on). As a result, the signal Vt1 output from the control signal generation circuit 34 becomes high. On the other hand, if the discharge voltage VM1 from the capacitor 516 is equal to or lower than the threshold voltage Vth of the switch 517, the switch 517 is connected to the ground (turned off). As a result, the signal Vt1 output from the control signal generation circuit 34 becomes low.

[0069] As a result, the signal Vt1 is output from the control signal generating circuit 34 in a form such as that shown in FIG. 6. At this time, the signal Vt1 has a pulse width that is inversely proportional to the length of time that the high-side input signal Hin is high. Furthermore, the time at which the signal Vt1 starts to fall is delayed compared to the time at which the high-side input signal Hin starts to fall by the pulse width correction amount shown in FIG.

[0070] Similarly, in the control signal generating circuit 35, the on / off of the switch 511 is controlled by the signal VSW2, and the on / off of the switch 512 is controlled by the signal VSW1. By the operation of these switches, the control signal generating circuit 35 controls the charging and discharging of the capacitor 516.

[0071] For example, in the control signal generating circuit 35, when the signal VSW2 is high, the switch 511 is turned on, thereby charging the capacitor 516. Then, when the signal VSW2 goes low and then the signal VSW1 goes high, the switch 511 is turned off and the switch 512 is turned on, causing the capacitor 516 to discharge.

[0072] At this time, if the discharge voltage VM2 from the capacitor 516 exceeds the threshold voltage Vth of the switch 517, the switch 517 is connected to the power supply voltage Vdd (turned on). As a result, the signal Vt2 output from the control signal generation circuit 35 becomes high. On the other hand, if the discharge voltage VM2 from the capacitor 516 is equal to or lower than the threshold voltage Vth of the switch 517, the switch 517 is connected to the ground (turned off). As a result, the signal Vt2 output from the control signal generation circuit 35 becomes low.

[0073] As a result, the signal Vt2 is output from the control signal generating circuit 35 in a form such as that shown in FIG. 6. At this time, the signal Vt2 has a pulse width that is inversely proportional to the length of time that the high-side input signal Hin is high. Furthermore, the start time of the falling edge of the signal Vt2 is delayed by the pulse width correction amount shown in FIG. 6 compared to the start time of the rising edge of the low-side input signal Lin.

[0074] The logical operation circuit 36 ​​adds the signals Vt1 and Vt2 to the high-side input signal Hin of the driver circuit 1, and outputs signals Hout1 and Hout2.

[0075] 8A and 8B show truth tables for the signals in the logical operation circuit 36. Fig. 8A shows a truth table for the case where the discharge voltages VM1 and VM2 from the capacitor 516 are equal to or lower than the threshold voltage Vth of the switch 517. In Fig. 8A, the discharge voltages VM1 and VM2 from the capacitor 516 are equal to or lower than the threshold voltage Vth of the switch 517, so the signals Vt1 and Vt2 are always 0.

[0076] In this case, the logical operation circuit 36 ​​does not perform pulse width correction on the high side input signal Hin. That is, the logical operation circuit 36 ​​generates signals Hout1 and Hout2 as shown in the truth table in FIG. 8A and outputs the generated signals Hout1 and Hout2 to the logical sum circuit 38 (see also FIG. 7A). The logical sum circuit 38 then outputs a signal Hout indicating the logical sum of the signals Hout1 and Hout2 output from the logical operation circuit 36. This signal Hout has a waveform similar to that of the high side input signal Hin (a waveform of the high side input signal Hin without pulse width correction).

[0077] 8B shows a truth table for the case where the discharge voltages VM1 and VM2 from the capacitor 516 exceed the threshold voltage Vth of the switch 517. In FIG. 8B, since the discharge voltages VM1 and VM2 from the capacitor 516 exceed the threshold voltage Vth of the switch 517, the signals Vt1 and Vt2 may become 1.

[0078] In this case, the logical operation circuit 36 ​​performs pulse width correction on the high-side input signal Hin corresponding to the pulse width correction amount generated by the signals Vt1 and Vt2. That is, the logical operation circuit 36 ​​generates signals Hout1 and Hout2 as shown in the truth table in FIG. 8B and outputs the generated signals Hout1 and Hout2 to the logical sum circuit 38 (see also FIG. 7C ). The logical sum circuit 38 outputs a signal Hout indicating the logical sum of the signals Hout1 and Hout2 output from the logical operation circuit 36. As shown in FIG. 6 , this signal Hout is a signal exhibiting a waveform in which the pulse width (High width) is increased and the Low width is decreased by the amount of pulse width correction, compared to the high-side input signal Hin.

[0079] On the other hand, the logical operation circuit 37 adds the signals Vt1 and Vt2 to the low-side input signal Lin of the driver circuit 1, and outputs signals Lout1 and Lout2.

[0080] 9A and 9B show truth tables for each signal in the logical operation circuit 37. Fig. 9A shows a truth table for the case where the discharge voltages VM1 and VM2 from the capacitor 516 are equal to or lower than the threshold voltage Vth of the switch 517. In Fig. 9A, the discharge voltages VM1 and VM2 from the capacitor 516 are equal to or lower than the threshold voltage Vth of the switch 517, so the signals Vt1 and Vt2 are always 0.

[0081] In this case, the logical operation circuit 37 does not perform pulse width correction on the low-side input signal Lin. That is, the logical operation circuit 37 generates signals Lout1 and Lout2 as shown in the truth table in FIG. 9A and outputs the generated signals Lout1 and Lout2 to the logical product circuit 39 (see also FIG. 7B). The logical product circuit 39 outputs a signal Lout indicating the logical product of signals Lout1 and Lout2. This signal Lout has the same waveform as the low-side input signal Lin (a waveform in which pulse width correction has not been performed on the low-side input signal Lin).

[0082] 9B shows a truth table for the case where the discharge voltages VM1 and VM2 from the capacitor 516 exceed the threshold voltage Vth of the switch 517. In FIG. 9B, since the discharge voltages VM1 and VM2 from the capacitor 516 exceed the threshold voltage Vth of the switch 517, the signals Vt1 and Vt2 may become 1.

[0083] In this case, the logical operation circuit 37 performs pulse width correction on the low-side input signal Lin according to the pulse width correction amount generated by the signals Vt1 and Vt2. That is, the logical operation circuit 37 generates signals Lout1 and Lout2 as shown in the truth table in FIG. 9B and outputs the generated signals Lout1 and Lout2 to the logical product circuit 39 (see also FIG. 7D). The logical product circuit 39 outputs a signal Lout indicating the logical product of signals Lout1 and Lout2. As shown in FIG. 6, this signal Lout is a signal exhibiting a waveform in which the pulse width (High width) is reduced and the Low width is increased by the amount of pulse width correction compared to the low-side input signal Lin.

[0084] As described above, the signal Hout output from the OR circuit 38 and the signal Lout output from the AND circuit 39 become input signals to, for example, a GaN circuit arranged in the subsequent stage of the driver circuit 1. The GaN circuit outputs a voltage according to the duty ratio of the input signals Hout and Lout.

[0085] Here, as shown in FIG. 10 , for example, the GaN circuit includes two transistors M1 and M2 and is used in two states: one in which transistor M1 is on and transistor M2 is off, and the other in which transistor M1 is off and transistor M2 is on. Therefore, in the GaN circuit, for example, if the pulse width of signal Hout increases and the number of states in which transistor M1 is on increases, the pulse width of signal Lout must be decreased to increase the number of states in which transistor M2 is off. Furthermore, as described above, the output PWM signal output from the GaN circuit is a signal that is opposite in phase to the high-side signal (i.e., signal Hout) and in phase with the low-side signal (i.e., signal Lout). Therefore, the driver circuit 1 performs the pulse width correction, increasing the pulse width of signal Hout and decreasing the pulse width of signal Lout, thereby decreasing the pulse width of the output PWM signal output from the GaN circuit. As a result, the output voltage of the GaN circuit can be reduced.

[0086] When the duty ratio of the input PWM signal input to the driver circuit 1 increases from the region where the relationship between the duty ratio and the output voltage is nonlinear, that is, when the duty ratio of the input PWM signal input to the driver circuit 1 shifts to the right from a point slightly smaller than the symbol x in Fig. 11, the time during which the signals VSW1 and VSW2 generated from the high-side input signal Hin and the low-side input signal Lin are high decreases. As a result, in the driver circuit 1, the charging time of the capacitors 516 in the control signal generation circuits 34 and 35 decreases.

[0087] Therefore, in the driver circuit 1, a voltage equal to or greater than the voltage across the terminals of the capacitor 516 when the duty ratio of the input PWM signal is large enough to eliminate the need to lower the output voltage of the GaN circuit, that is, when the duty ratio of the input PWM signal is a predetermined duty ratio indicated by the symbol x in Fig. 11, is set as the threshold voltage Vth of the switch 517. Note that the voltage across the terminals of the capacitor 516 when the duty ratio of the input PWM signal is equal to the symbol x in Fig. 11 can be determined in advance by, for example, simulation.

[0088] When the threshold voltage Vth of the switch 517 is set in this manner, the driver circuit 1 operates as follows. For example, in the driver circuit 1, when the relationship between the duty ratio of the input PWM signal and the output voltage of the GaN circuit relative to the duty ratio is linear, that is, when a signal having a pulse width equal to or greater than the sum of the rise time and fall time of the output PWM signal output from the GaN circuit is input to the driver circuit 1, the charging time of the capacitor 516 in the control signal generation circuits 34 and 35 decreases, and the signals Vt1 and Vt2 are always low. In this case, the driver circuit 1 does not perform the pulse width correction, and as a result, the signals Hout and Lout input to the GaN circuit have waveforms similar to those of the high-side input signal Hin and the low-side input signal Lin.

[0089] On the other hand, in the driver circuit 1, when the relationship between the duty ratio of the input PWM signal and the output voltage relative to the duty ratio is nonlinear, i.e., when a signal with a pulse width smaller than the sum of the rise time and fall time of the output PWM signal output from the GaN circuit is input to the driver circuit 1, the charging time of the capacitor 516 in the control signal generation circuits 34 and 35 increases, causing signals Vt1 and Vt2 to go high. In this case, the driver circuit 1 performs the pulse width correction, and the signals Hout and Lout input to the GaN circuit exhibit waveforms obtained by pulse width correction for the high-side input signal Hin and the low-side input signal Lin. In this case, the output voltage of the GaN circuit decreases. In this way, the driver circuit 1 can reduce the output voltage of the GaN circuit only in the duty ratio region of the input PWM signal that requires pulse width correction (the region to the left of the symbol x in FIG. 11 ).

[0090] In the driver circuit 1, the signal Hout output to the GaN circuit is not generated by logically inverting the signal Lout, but is generated from the high-side input signal Hin. In the driver circuit 1, the signal Lout output to the GaN circuit is not generated by logically inverting the signal Hout, but is generated from the low-side input signal Lin.

[0091] As a result, in the first embodiment, the signals Hout and Lout output by the driver circuit 1 can have an overlap equivalent to the overlap (a state in which two pulses simultaneously become High in logic level) of the high-side input signal Hin and the low-side input signal Lin. In addition, by having the signals Hout and Lout overlap, in the first embodiment, it is possible to suppress the current that flows when the GaN circuit is switched, and to improve the power efficiency of the GaN circuit.

[0092] As described above, according to the first embodiment, the driver circuit 1 outputs a first drive signal and a second drive signal for driving an amplifier that outputs an output PWM signal indicating an output voltage, and based on an input PWM signal that is a PWM signal input to the driver circuit 1, outputs the first drive signal, which is a PWM signal in phase with the input PWM signal, and the second drive signal, which is a PWM signal in phase with the input PWM signal, and based on the first drive signal and second drive signal output from the driver circuit 1, the amplifier outputs an output PWM signal, which is a signal in phase with the first drive signal and in phase with the second drive signal, and when the duty ratio of the input PWM signal input to the driver circuit 1 is less than a predetermined duty ratio, the driver circuit 1 increases the pulse width of the first drive signal that it outputs in inverse proportion to the pulse width of the input PWM signal. As a result, the driver circuit 1 according to the first embodiment can improve the linearity of the output voltage indicated by the output PWM signal relative to the duty ratio of the input PWM signal.

[0093] The driver circuit 1 also includes a signal control circuit 31 that generates a correction pulse having a pulse width inversely proportional to the length of time that the input PWM signal is High when the duty ratio of the input PWM signal is less than a predetermined duty ratio, and an adder circuit 32 that generates a first drive signal with an increased pulse width by logically operating the correction pulse generated by the signal control circuit 31 and the input PWM signal. This allows the driver circuit 1 according to the first embodiment to generate a first drive signal with an increased pulse width in accordance with the duty ratio of the input PWM signal.

[0094] The signal control circuit 31 also includes a capacitor 516 that can be charged or discharged depending on whether the input PWM signal is High or Low, and a switch 517 that switches the correction pulse between High and Low depending on the magnitude relationship between the voltage value of the voltage charged or discharged by the capacitor 516 and a preset threshold voltage. This allows the driver circuit 1 according to the first embodiment to generate correction pulses with high precision.

[0095] Furthermore, the threshold voltage can be set arbitrarily depending on the pulse width of the input PWM signal, which allows the driver circuit 1 according to the first embodiment to flexibly set whether or not to generate a correction pulse depending on the pulse width of the input PWM signal.

[0096] The threshold voltage is set to be equal to or greater than the voltage across the capacitor 516 when the duty ratio of the input PWM signal corresponds to a predetermined duty ratio, thereby enabling the driver circuit 1 according to the first embodiment to switch whether or not to generate a correction pulse, based on the predetermined duty ratio.

[0097] The predetermined duty ratio is a duty ratio at which the relationship between the duty ratio of the input PWM signal and the output voltage indicated by the output PWM signal output from the amplifier switches between a linear region and a nonlinear region. As a result, the driver circuit 1 according to the first embodiment can switch whether to generate a correction pulse, using the duty ratio at which the relationship between the duty ratio of the input PWM signal and the output voltage indicated by the output PWM signal output from the amplifier switches between a linear region and a nonlinear region.

[0098] The predetermined duty ratio is the duty ratio of the input PWM signal when the pulse width of the input PWM signal is smaller than the sum of the rise time and fall time of the output PWM signal output from the amplifier. As a result, the driver circuit 1 according to the first embodiment can switch whether or not to generate a correction pulse based on the duty ratio of the input PWM signal when the pulse width of the input PWM signal is smaller than the sum of the rise time and fall time of the output PWM signal output from the amplifier.

[0099] The voltage generating circuit according to the first embodiment includes a driver circuit 1 and an amplifier that outputs an output PWM signal, which is a signal indicating an output voltage and is a signal of opposite phase to the first drive signal, based on the first drive signal and the second drive signal output from the driver circuit 1. This makes it possible for the voltage generating circuit according to the first embodiment to improve the linearity of the output voltage indicated by the output PWM signal relative to the duty ratio of the PWM signal input to the driver circuit 1.

[0100] In addition, in the present disclosure, any component of the embodiments may be modified or any component of the embodiments may be omitted.

[0101] The present disclosure provides a driver circuit that drives an amplifier that outputs an output PWM signal that indicates an output voltage, and that can improve the linearity of the output voltage indicated by the output PWM signal relative to the duty ratio of the input PWM signal, making it suitable for use in a driver circuit.

[0102] 1 Driver circuit, 31 Signal control circuit, 32 Adder circuit, 33 SW signal generation circuit, 34 Control signal generation circuit, 35 Control signal generation circuit, 36 Logical operation circuit, 37 Logical operation circuit, 38 Logical OR circuit, 39 Logical AND circuit, 41 Rising edge triggered T flip-flop circuit, 42 Rising edge triggered T flip-flop circuit, 43 Inverter circuit, 44 Inverter circuit, 45 Logical AND circuit, 46 Logical AND circuit, 61 Inverter circuit, 62 Inverter circuit, 63 Logical AND circuit, 64 Logical AND circuit, 65 Logical AND circuit, 66 Logical AND circuit, 67 Logical OR circuit, 68 Logical OR circuit, 71 Falling edge triggered T flip-flop circuit, 72 Inverter circuit, 73 Inverter circuit, 74 Inverter circuit, 75 Logical AND circuit, 76 Logical AND circuit, 77 Logical AND circuit, 78 Logical AND circuit, 79 AND circuit, 80 AND circuit, 81 OR circuit, 82 OR circuit, 511 switch, 512 switch, 513 resistor, 514 resistor, 515 resistor, 516 capacitor (capacitance), 517 switch, M1 transistor, M2 transistor.

Claims

1. A driver circuit that outputs a first drive signal and a second drive signal for driving an amplifier that outputs an output PWM signal indicating an output voltage, The driver circuit includes: Based on an input PWM signal that is a PWM signal input to the driver circuit, a first drive signal that is a PWM signal in phase with the input PWM signal and a second drive signal that is a PWM signal in phase opposite to the input PWM signal are output; The amplifier comprises: outputting the output PWM signal, which is a signal having a phase opposite to that of the first drive signal and a phase identical to that of the second drive signal, based on the first drive signal and the second drive signal output from the driver circuit; The driver circuit includes: When the duty ratio of the input PWM signal input to the driver circuit is less than a predetermined duty ratio, the driver circuit increases the pulse width of the output first drive signal in inverse proportion to the pulse width of the input PWM signal.

2. a signal control circuit that generates a correction pulse having a pulse width inversely proportional to a time period during which the input PWM signal is at a high level when the duty ratio of the input PWM signal is less than the predetermined duty ratio; an adder circuit that generates the first drive signal having an increased pulse width by performing a logical operation on the correction pulse generated by the signal control circuit and the input PWM signal; 2. The driver circuit according to claim 1, further comprising:

3. The signal control circuit includes: a capacitance that can be charged or discharged depending on whether the input PWM signal is high or low; a switch for switching the correction pulse between High and Low in accordance with a magnitude relationship between a voltage value of a voltage charged and discharged by the capacitance and a preset threshold voltage; 3. The driver circuit according to claim 2, further comprising:

4. 4. The driver circuit according to claim 3, wherein the threshold voltage can be arbitrarily set in accordance with the pulse width of the input PWM signal.

5. The threshold voltage is set to be equal to or higher than the voltage across the capacitor when the duty ratio of the input PWM signal corresponds to the predetermined duty ratio.

4. The driver circuit according to claim 3.

6. The predetermined duty ratio is This is the duty ratio when the relationship between the duty ratio of the input PWM signal and the output voltage indicated by the output PWM signal output from the amplifier switches between a linear region and a nonlinear region. A driver circuit as claimed in any one of claims 1 to 5.

7. The predetermined duty ratio is is the duty ratio of the input PWM signal when the pulse width of the input PWM signal is smaller than the sum of the rise time and fall time of the output PWM signal output from the amplifier. A driver circuit as claimed in any one of claims 1 to 5.

8. A driver circuit according to any one of claims 1 to 5; an amplifier that outputs an output PWM signal, which is a signal indicating an output voltage based on a first drive signal and a second drive signal output from the driver circuit and is a signal of opposite phase to the first drive signal; A voltage generating circuit comprising: