Solar battery element and solar battery element manufacturing method

Abstract

A solar battery element (1) is provided with a substrate (2), an oxide film (3), and a polysilicon layer (4). The substrate (2) has a first region (21) which is a semiconductor region of a first conductivity type. The oxide film (3) is in contact with the first region (21). The polysilicon layer (4) is in contact with a surface of the oxide film (3) on the side opposite to the first region (21). The polysilicon layer (4) contains a dopant. The polysilicon layer (4) includes a second region (41). The second region (41) is an oxide film-side region of the polysilicon layer (4) in contact with the oxide film (3). In a region from the second region (41) to the first region (21) through the oxide film (3), the distribution of the dopant concentration in the polysilicon layer (4) in a direction from a surface on the side opposite to the substrate (2) toward the substrate (2) has a maximum first peak (Pk1) and a maximum second peak (Pk2). In the distribution of the dopant concentration, the second peak (Pk2) is located at a distance of 3 nm or more from a position indicating the first peak (Pk1) in a direction from the first region (21) to the second region (41) through the oxide film (3). The dopant is of the first conductivity type or a second conductivity type different from the first conductivity type.

Description

Solar cell element and method for manufacturing the solar cell element CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority from Japanese Application No. 2023-100567 (filed June 20, 2023), the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to a solar cell element and a method for manufacturing a solar cell element.

[0003] There is a solar cell element having a structure called POLO (polysilicon on oxide) (also called a POLO structure), in which an extremely thin oxide film and a layer of polycrystalline silicon doped with an impurity element are stacked in a region on the surface of a crystalline silicon substrate (also called simply a substrate) or in a region located inside the substrate and extending from a portion along the surface of the substrate to the surface of the substrate (see, for example, the description in Non-Patent Document 1).

[0004] In recent years, there has been an increasing demand for reducing defects in solar cell elements.

[0005] Christian N. Kruse, et al., “Simulation-based roadmap for the integration of poly-silicon on oxide contacts into screen-printed crystalline silicon solar cells”, Scientific reports 11:996 (2021)

[0006] A solar cell device and a method for manufacturing the solar cell device are disclosed.

[0007] One aspect of a solar cell element includes a substrate, an oxide film, and a polysilicon layer. The substrate has a first region that is a region of a first conductivity type semiconductor. The oxide film is in contact with the first region. The polysilicon layer is in contact with a surface of the oxide film opposite the first region. The polysilicon layer contains a dopant. The polysilicon layer includes a second region. The second region is a region of the polysilicon layer on the oxide film side that is in contact with the oxide film. In a region extending from the second region through the oxide film to the first region, the distribution of the dopant concentration in a direction from the surface of the polysilicon layer opposite the substrate toward the substrate has a maximum first peak and a second peak. In the dopant concentration distribution, the second peak is located at a position 3 nm or more away from the position showing the first peak in a direction from the first region through the oxide film toward the second region. The dopant is a dopant of the first conductivity type or a second conductivity type different from the first conductivity type.

[0008] One aspect of a solar cell element includes a substrate and a polysilicon layer. The substrate has a first region that is a region of a first conductivity type semiconductor. The substrate includes an oxide film. The oxide film is located between the first region and the polysilicon layer and is in contact with both the first region and the polysilicon layer. The polysilicon layer is in contact with the substrate. The polysilicon layer contains a dopant. The polysilicon layer includes a second region. The second region is a region of the polysilicon layer on the oxide film side that is in contact with the oxide film. In a region extending from the second region through the oxide film to the first region, a distribution of the dopant concentration in a direction from the surface of the polysilicon layer opposite the substrate toward the substrate has a maximum first peak and a second peak. In the dopant concentration distribution, the second peak is located at a position 3 nm or more away from the position showing the first peak in a direction from the first region through the oxide film toward the second region. The dopant is a dopant of the first conductivity type or a dopant of a second conductivity type different from the first conductivity type.

[0009] One aspect of a method for manufacturing a solar cell element includes a first step, a second step, a third step, and a fourth step. In the first step, an oxide film is formed inside a crystalline silicon substrate including a first region, which is a region of a first conductivity type semiconductor, along the surface of the substrate or on the surface of the substrate, and in contact with the first region. In the second step, a first layer of intrinsic crystalline silicon is formed on the oxide film. In the third step, a second layer of amorphous silicon, which has a thickness greater than that of the first layer and contains a dopant, is formed on the first layer. In the fourth step, a heat treatment is performed to promote crystallization of the amorphous silicon of the second layer while diffusing the dopant contained in the second layer toward the first layer and the oxide film, thereby generating a polysilicon layer located on the oxide film and containing the dopant from the first layer and the second layer. The dopant is a dopant of the first conductivity type or a second conductivity type different from the first conductivity type.

[0010] One aspect of a solar cell element includes a substrate, an oxide film, and a polysilicon layer. The substrate has a first region that is a region of a first conductivity type semiconductor. The oxide film is in contact with the first region. The polysilicon layer is in contact with a surface of the oxide film opposite the first region. The polysilicon layer contains a dopant. The polysilicon layer is formed from a first layer of intrinsic crystalline silicon located on the oxide film and a second layer of amorphous silicon located on the first layer, having a thickness greater than that of the first layer, and containing the dopant, by performing a heat treatment on the first layer and the second layer. The heat treatment is a process that diffuses the dopant contained in the second layer toward the first layer and the oxide film, thereby promoting crystallization of the amorphous silicon of the second layer. The dopant is a dopant of the first conductivity type or a second conductivity type different from the first conductivity type.

[0011] One aspect of a solar cell element includes a substrate and a polysilicon layer. The substrate has a first region, which is a region of a semiconductor of a first conductivity type. The substrate includes an oxide film. The oxide film is located between the first region and the polysilicon layer and is in contact with both the first region and the polysilicon layer. The polysilicon layer is in contact with the substrate. The polysilicon layer contains a dopant. The polysilicon layer is formed from a first layer of intrinsic crystalline silicon located on the oxide film and a second layer of amorphous silicon located on the first layer, having a thickness greater than that of the first layer, and containing the dopant, by performing a heat treatment on the first layer and the second layer. The heat treatment is a process that diffuses the dopant contained in the second layer toward the first layer and the oxide film, thereby promoting crystallization of the amorphous silicon of the second layer. The dopant is a dopant of the first conductivity type or a second conductivity type different from the first conductivity type.

[0012] FIG. 1 is a cross-sectional view schematically showing an example of the configuration of a solar cell element according to the first embodiment. FIG. 2 is an enlarged cross-sectional view schematically showing part II of FIG. 1 in the configuration of the solar cell element according to the first embodiment. FIG. 3 is a flowchart showing an example of a method for manufacturing a solar cell element according to the first embodiment. FIG. 4 is a cross-sectional view schematically showing an example of the configuration of a solar cell element according to the first embodiment during the course of its manufacture. FIG. 5 is a cross-sectional view schematically showing an example of the configuration of a solar cell element according to the first embodiment during the course of its manufacture. FIG. 6 is a cross-sectional view schematically showing an example of the configuration of a solar cell element according to the first embodiment during the course of its manufacture. FIG. 7 is a cross-sectional view schematically showing an example of the configuration of a solar cell element according to the first embodiment during the course of its manufacture. FIG. 8 is a cross-sectional view schematically showing an example of the configuration of a solar cell element according to the first embodiment during the course of its manufacture. FIG. 9 is a cross-sectional view schematically showing an example of the configuration of a solar cell element according to the first embodiment during the course of its manufacture. FIG. 10 is a cross-sectional view schematically showing an example of the configuration of a solar cell element according to the first embodiment during the course of its manufacture. FIG. 11 is a cross-sectional view schematically showing an example of the configuration of a solar cell element according to the first embodiment during the course of its manufacture. FIG. 12 is a cross-sectional view schematically showing an example of the configuration of a solar cell element according to the first embodiment during the course of its manufacture. FIG. 13 is a cross-sectional view schematically illustrating an example of a configuration during manufacturing of a solar cell element according to the first embodiment. FIG. 14 is a flowchart illustrating a method for fabricating samples of various specific examples relating to the TOPCon structure. FIG. 15 is a flowchart illustrating a method for fabricating samples of various reference examples relating to the TOPCon structure. FIG. 16 is a diagram illustrating an example of an image capturing the surface of an n-type polysilicon layer in a sample of Reference Example 6. FIG. 17 is a diagram illustrating an example of an image capturing the surface of an n-type polysilicon layer in a sample of Reference Example 6. FIG. 18 is a diagram illustrating an example of an image capturing the surface of an n-type polysilicon layer in a sample of Reference Example 13. FIG. 19 is a diagram illustrating an example of an image capturing the surface of an n-type polysilicon layer in a sample of Reference Example 13. FIG. 20 is a graph illustrating an example of measurement results of the distribution of phosphorus concentration in a portion of a first direction obtained by secondary ion mass spectrometry for each of the samples of Specific Example 4 and Reference Example 4.FIG. 21 is a graph illustrating the characteristics of the phosphorus concentration distribution in a portion of the first direction obtained by using secondary ion mass spectrometry on the sample of Specific Example 4. FIG. 22 is a graph illustrating the characteristics of the phosphorus concentration distribution in a portion of the first direction obtained by using secondary ion mass spectrometry on the sample of Specific Example 4. FIG. 23 is a graph illustrating the characteristics of the phosphorus concentration distribution in a portion of the first direction obtained by using secondary ion mass spectrometry on the sample of Reference Example 4. FIG. 24 is a graph showing an example of measurement results of the phosphorus concentration distribution in a portion of the first direction obtained by using secondary ion mass spectrometry on the samples of Specific Example 6 and Reference Example 6. FIG. 25 is a graph illustrating the characteristics of the phosphorus concentration distribution in a portion of the first direction obtained by using secondary ion mass spectrometry on the sample of Specific Example 6. FIG. 26 is a graph illustrating the characteristics of the phosphorus concentration distribution in a portion of the first direction obtained by using secondary ion mass spectrometry on the sample of Specific Example 6. 27 is a graph illustrating the characteristics of the phosphorus concentration distribution in a portion of the first direction obtained by using secondary ion mass spectrometry on the sample of Reference Example 6. FIG. 28 is a graph illustrating an example of measurement results of the phosphorus concentration distribution in a portion of the first direction obtained by using secondary ion mass spectrometry on the samples of Specific Example 2 and Reference Example 2. FIG. 29 is a graph illustrating the characteristics of the phosphorus concentration distribution in a portion of the first direction obtained by using secondary ion mass spectrometry on the sample of Specific Example 2. FIG. 30 is a graph illustrating the characteristics of the phosphorus concentration distribution in a portion of the first direction obtained by using secondary ion mass spectrometry on the sample of Specific Example 2. FIG. 31 is a graph illustrating the characteristics of the phosphorus concentration distribution in a portion of the first direction obtained by using secondary ion mass spectrometry on the sample of Reference Example 2. FIG. 32 is a graph illustrating an example of measurement results of the phosphorus concentration distribution in a portion of the first direction obtained by using secondary ion mass spectrometry on the sample of Specific Example 3.FIG. 33 is a graph illustrating the characteristics of the phosphorus concentration distribution in a portion of the first direction obtained by secondary ion mass spectrometry on the sample of Specific Example 3. FIG. 34 is a graph illustrating an example of measurement results of the phosphorus concentration distribution in a portion of the first direction obtained by secondary ion mass spectrometry on the sample of Specific Example 5. FIG. 35 is a graph illustrating the characteristics of the phosphorus concentration distribution in a portion of the first direction obtained by secondary ion mass spectrometry on the sample of Specific Example 5. FIG. 36 is a cross-sectional view schematically illustrating an example of the configuration of a solar cell element according to a second embodiment. FIG. 37 is a cross-sectional view schematically illustrating an example of the configuration of a solar cell element according to a third embodiment. FIG. 38 is an enlarged cross-sectional view schematically illustrating a portion XXXVIII of FIG. 36 in the configuration of the solar cell element according to the second embodiment and a portion XXXVIII of FIG. 37 in the configuration of the solar cell element according to the third embodiment. FIG. 39 is a flowchart illustrating an example of a method for manufacturing a solar cell element according to the third embodiment. FIG. 40 is a cross-sectional view schematically illustrating an example of the configuration of a solar cell element according to a fourth embodiment. FIG. 41 is a cross-sectional view schematically illustrating an example of the configuration of a solar cell element according to a fifth embodiment. Fig. 42 is a flow chart showing an example of a method for manufacturing a solar cell element according to the fifth embodiment. Fig. 43 is a cross-sectional view showing an example of the configuration of a back-contact solar cell element. Fig. 44 is a cross-sectional view showing an example of the configuration of another back-contact solar cell element.

[0013] Solar cell elements have a structure called POLO (polysilicon on oxide) in a region on the surface of a crystalline silicon substrate (also called a crystalline silicon substrate) or in a region located inside the crystalline silicon substrate and extending from a portion along the surface of the crystalline silicon substrate to the crystalline silicon substrate. This POLO structure includes a stacked structure of an ultrathin oxide film (also called an ultrathin oxide film) and a layer of polycrystalline silicon doped with an impurity element (also called a doped polysilicon layer). One example of a solar cell element having a POLO structure is a tunnel oxide passivated contact (TOPCon) solar cell element.

[0014] An example of a TOPCon type solar cell element is a solar cell element having a structure in which an ultrathin oxide film and a doped polysilicon layer of the first conductivity type (e.g., n-type) are stacked on a crystalline silicon substrate having a first conductivity type (e.g., n-type).

[0015] The TOPCon structure can provide solar cell elements with features such as high passivation performance and the ability to selectively transmit carriers (also known as carrier selectivity). In other words, the TOPCon structure can improve the conversion efficiency of solar cell elements, which indicates the proportion of incident light energy that is converted into electrical energy.

[0016] Incidentally, a doped polysilicon layer in a POLO structure such as a TOPCon structure can be formed by chemical vapor deposition (CVD), including low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD).

[0017] When the doped polysilicon layer is formed using the LPCVD method, the desired doped polysilicon layer can be formed, for example, by sequentially forming an intrinsic polycrystalline silicon layer (also referred to as an i-type polysilicon layer) using the LPCVD method, doping the i-type polysilicon layer with an impurity element, and annealing the doped polycrystalline silicon layer (also referred to as a polysilicon layer). Alternatively, the desired doped polysilicon layer can be formed by forming a polysilicon layer while doping it with an impurity element using the LPCVD method, and then annealing the doped polysilicon layer.

[0018] However, when a polysilicon layer is formed using the LPCVD method, the polysilicon layer is deposited on both sides of the crystalline silicon substrate. This requires complex processes, such as removing one of the unnecessary polysilicon layers deposited on both sides of the crystalline silicon substrate, or depositing a polysilicon layer on the second side of the crystalline silicon substrate with a mask provided on the first side of the crystalline silicon substrate and then removing the mask. Furthermore, when a polysilicon layer is formed using the LPCVD method, it takes a long time to deposit a polysilicon layer of the desired thickness. In other words, the deposition speed (also referred to as the deposition rate) when a polysilicon layer is formed using the LPCVD method is slow.

[0019] Therefore, it is considered that the time required to form a POLO structure such as a TOPCon structure can be shortened by forming a doped polysilicon layer using the PECVD method, which has a higher film formation rate than the LPCVD method and is capable of forming a silicon layer (also referred to as a silicon layer) on one desired side of a crystalline silicon substrate. In other words, it is considered that the productivity of solar cell elements including a POLO structure such as a TOPCon structure can be improved by forming a doped polysilicon layer using the PECVD method.

[0020] When a silicon layer doped with an impurity element is formed on a desired surface of a crystalline silicon substrate using the PECVD method, the silicon layer becomes an amorphous silicon layer doped with the impurity element (also called a doped amorphous silicon layer). Therefore, it is considered that a doped polysilicon layer is formed by subjecting the doped amorphous silicon layer formed on the desired surface of the crystalline silicon substrate using the PECVD method to a high-temperature heat treatment, which promotes crystallization of the doped amorphous silicon layer. When a doped amorphous silicon layer is formed on an ultrathin oxide film using the PECVD method, a doped polysilicon layer is formed by using, for example, monosilane (SiH ４ ) gas, phosphine (PH ３ ) gas and hydrogen (H ２A gaseous source material (also referred to as a source gas) containing hydrogen, such as a hydrogen-containing gas, can be used. In this case, a process (also referred to as hydrogenation) for bonding hydrogen to dangling bonds of silicon elements in the doped amorphous silicon layer can be performed, thereby stabilizing the silicon elements in the doped amorphous silicon layer.

[0021] However, when a doped amorphous silicon layer is formed on an ultrathin oxide film using the PECVD method, and when a high-temperature heat treatment is performed on the doped amorphous silicon layer formed on the ultrathin oxide film using the PECVD method for crystallization, defects called blisters can occur. Blisters are voids that occur between the ultrathin oxide film and the doped amorphous silicon layer.

[0022] For example, when a doped amorphous silicon layer is formed on an ultrathin oxide film by PECVD using a source gas containing hydrogen, the hydrogen in the source gas may turn into hydrogen gas and reach areas or defects at the interface between the ultrathin oxide film and the doped amorphous silicon layer where adhesion is weak. In this case, the ultrathin oxide film may reduce the inflow of hydrogen to the crystalline silicon substrate. Therefore, the hydrogen gas may aggregate at the interface between the ultrathin oxide film and the doped amorphous silicon layer, causing blisters.

[0023] Furthermore, for example, when a doped amorphous silicon layer formed on an ultrathin oxide film by PECVD using a hydrogen-containing source gas is subjected to high-temperature heat treatment for crystallization, hydrogen may be released from the doped amorphous silicon layer. This hydrogen release may occur due to desorption of hydrogen bonded to silicon in the doped amorphous silicon layer. This hydrogen may then turn into hydrogen gas and reach areas or defects at the interface between the ultrathin oxide film and the doped amorphous silicon layer with weak adhesion. At this time, the ultrathin oxide film may reduce the inflow of hydrogen to the crystalline silicon substrate. Therefore, hydrogen gas may aggregate at the interface between the ultrathin oxide film and the doped amorphous silicon layer, causing blisters. Furthermore, when the doped amorphous silicon layer is transformed into a doped polysilicon layer by heat treatment, the silicon layer shrinks due to the progress of bonding between silicon elements, which may increase stress that may peel the silicon layer from the ultrathin oxide film. This increased stress also makes blisters more likely to occur. The internal pressure of the blister may increase due to, for example, further condensation of hydrogen gas. This may result in localized rupture of the doped amorphous silicon layer where crystallization has begun. In other words, defects where the doped amorphous silicon layer is not present may occur locally in the doped amorphous silicon layer where crystallization has begun. As a result, the doped polysilicon layer produced by crystallization of the doped amorphous silicon layer may have localized defects due to blisters. Localized defects in the doped polysilicon layer may be considered a type of defect in the doped polysilicon layer. Furthermore, unruptured blisters may exist at the interface between the ultrathin oxide film and the doped polysilicon layer. Therefore, defects in the POLO structure may include, for example, one or more of blisters existing at the interface between the ultrathin oxide film and the doped polysilicon layer and localized defects in the doped polysilicon layer.

[0024] Consider a solar cell device including a TOPCon structure, a type of POLO, in which an ultrathin oxide film and a doped polysilicon layer of the first conductivity type (e.g., n-type) are stacked on a crystalline silicon substrate having a first conductivity type (e.g., n-type). In this case, if there are one or more defects, such as blisters at the interface between the ultrathin oxide film and the doped polysilicon layer and local defects caused by blisters in the doped polysilicon layer, the high passivation performance of the TOPCon structure may be reduced. This may result in a decrease in the conversion efficiency of the solar cell device including the TOPCon structure.

[0025] Consider a solar cell element having a POLO structure in which an ultrathin oxide film and a doped polysilicon layer of a first conductivity type (e.g., n-type) are stacked on a crystalline silicon substrate of a second conductivity type (e.g., p-type). In this case, if there are one or more defects among blisters at the interface between the ultrathin oxide film and the doped polysilicon layer and local defects caused by blisters in the doped polysilicon layer, the region where the crystalline silicon substrate and the doped polysilicon layer are joined via the ultrathin oxide film (also referred to as a pn junction region) may be reduced. This may result in a decrease in the conversion efficiency of the solar cell element having the POLO structure.

[0026] Furthermore, the method for forming the doped amorphous silicon layer on the ultrathin oxide film is not limited to the PECVD method, and other methods such as evaporation may also be used.

[0027] Therefore, for solar cell elements having a POLO structure including a doped polysilicon layer formed through deposition of a doped amorphous silicon layer and heat treatment for crystallization of this doped amorphous silicon layer, there is room for improvement in terms of reducing the occurrence of blisters when the doped polysilicon layer is formed and the occurrence of local defects caused by blisters.

[0028] That is, there is room for improvement in terms of reducing defects in solar cell elements having a POLO structure formed using a doped amorphous silicon layer.

[0029] Therefore, the inventors of the present disclosure have created a technique for reducing defects in a solar cell element having a POLO structure formed using a doped amorphous silicon layer.

[0030] In this regard, various embodiments and examples will be described below with reference to the drawings. In the drawings, parts having the same or similar configurations and functions are designated by the same reference numerals. Duplicate explanations will be omitted in the following description. The drawings are schematic. A right-handed XYZ coordinate system is shown in each of FIGS. 1, 2, 4 to 13, 36 to 38, 40, 41, 43, and 44. In this XYZ coordinate system, one direction along the thickness direction of solar cell elements 1, 1A, 1B, 1C, 1D, 1E, and 1F (also referred to as the first thickness direction) is defined as the +Z direction, one direction perpendicular to the +Z direction is defined as the +X direction, and one direction perpendicular to both the +X direction and the +Z direction is defined as the +Y direction. Furthermore, the direction opposite to the first thickness direction along the thickness direction of the solar cell elements 1, 1A, 1B, 1C, 1D, 1E, and 1F (also called the second thickness direction) is defined as the -Z direction.

[0031] 1. Example of solar cell element structure Fig. 1 is a cross-sectional view schematically showing an example of the configuration of a solar cell element 1 according to the first embodiment. Fig. 2 is an enlarged cross-sectional view schematically showing part II of Fig. 1 in the configuration of the solar cell element 1 according to the first embodiment.

[0032] The solar cell element 1 has a plate-like shape with a surface 1f (also called the first element surface or front surface) facing the +Z direction and a surface 1b (also called the second element surface or back surface) facing the -Z direction.

[0033] The solar cell element 1 includes a silicon substrate 2 serving as a substrate. The silicon substrate 2 includes crystalline silicon (also referred to as crystalline silicon), such as single crystal or polycrystalline. In other words, the silicon substrate 2 may be a crystalline silicon substrate. The silicon substrate 2 has, for example, a first surface (also referred to as a first main surface) 2f, a second surface (also referred to as a second main surface) 2b opposite the first surface 2f, and an end surface connecting the first surface 2f and the second surface 2b. The first surface 2f and the second surface 2b face in opposite directions in the thickness direction of the silicon substrate 2. The thickness direction of the silicon substrate 2 may be a direction along the +Z direction as the first thickness direction, or a direction along the −Z direction as the second thickness direction. In the example of FIG. 1, the first surface 2f faces the +Z direction, and the second surface 2b faces the −Z direction. In the present disclosure, the direction along the +Z direction is also referred to as the upward direction or up, and the direction along the −Z direction is also referred to as the downward direction or down.

[0034] The silicon substrate 2 has a first semiconductor region 21 as a first region, which is a region of a semiconductor of a first conductivity type. In the first embodiment, the silicon substrate 2 also has a region (also referred to as a second semiconductor region) 22 of a semiconductor of a second conductivity type different from the first conductivity type. In other words, the silicon substrate 2 has a first semiconductor region 21 of crystalline silicon of the first conductivity type and a second semiconductor region 22 of crystalline silicon of the second conductivity type. In the silicon substrate 2, the first semiconductor region 21 is located on the second surface 2b side, and the second semiconductor region 22 is located on the first surface 2f side.

[0035] In the example of FIG. 1 , most of the silicon substrate 2 is the first semiconductor region 21, and the region located inside the silicon substrate 2 and along the first surface 2f is the second semiconductor region 22. The first conductivity type is n-type, and the second conductivity type is p-type. The n-type first semiconductor region 21 contains an n-type dopant (also referred to as an n-type dopant). The second semiconductor region 22 contains a p-type dopant (also referred to as a p-type dopant). Here, for example, a Group 15 element such as phosphorus (P) is used as the n-type dopant. For example, a Group 13 element such as boron (B) is used as the p-type dopant. The concentration of the n-type dopant in the first semiconductor region 21 is, for example, 1×10 １５atoms / cubic centimeter (atoms / cm ３ ) to 1 x 10 １７ atoms / cm ３ The concentration of the p-type dopant in the second semiconductor region 22 is set to a range of, for example, 1×10 ２０ atoms / cm ３ From 1 x 10 ２２ atoms / cm ３ is set to the range.

[0036] The thickness of the silicon substrate 2 is set to, for example, 100 micrometers (μm) to 250 μm. The shape of the silicon substrate 2 in a planar view is set to, for example, a rectangular or square shape with a side length of 20 millimeters (mm) to 210 mm. The shape of the silicon substrate 2 in a planar view is the shape of the silicon substrate 2 when the silicon substrate 2 is viewed in the −Z direction or the +Z direction. The shape of the silicon substrate 2 in a planar view is not limited to a rectangular shape, and may be another polygonal shape or other shape. The thickness of the second semiconductor region 22 is set to, for example, 0.1 μm to 2 μm.

[0037] As shown in the example of FIG. 1 , a fine uneven structure (also referred to as a textured structure) may be formed on the first surface 2f of the silicon substrate 2. The shapes of the convex and concave portions of the textured structure may be, for example, pyramidal or spherical. The height of the convex portions of the textured structure may be, for example, 0.1 μm to 10 μm. The height of the convex portions may be, for example, the distance between the bottom of the concave portion and the top of the convex portion in the +Z direction. The spacing between adjacent convex portions in the textured structure may be, for example, 0.1 μm to 20 μm. The spacing between adjacent convex portions may be, for example, the distance between the tops of adjacent convex portions in a direction perpendicular to the +Z direction. Each layer of the solar cell element 1 located above the first surface 2f of the silicon substrate 2 may also have a shape that reflects the uneven structure of its underlying layer. In other words, each layer of the solar cell element 1 located above the first surface 2f of the silicon substrate 2 may also have an uneven structure. This uneven structure can reduce the light reflectance on the front surface 1f side of the solar cell element 1. As a result, the solar cell element 1 can efficiently take in light irradiated onto the front surface 1f into the solar cell element 1.

[0038] The solar cell element 1 includes a silicon oxide film 3 as an oxide film and an n-type polysilicon layer 4 as a layer of polycrystalline silicon (also referred to as a polysilicon layer) containing a dopant of a first conductivity type on the second surface 2b side of the silicon substrate 2. The solar cell element 1 also includes a first anti-reflection film 5 and a first electrode 6 on the back surface 1b side of the n-type polysilicon layer 4.

[0039] The silicon oxide film 3 is in contact with the first semiconductor region 21 of the silicon substrate 2. The silicon oxide film 3 may be located on the surface of the silicon substrate 2 on the second surface 2b side, or may be located inside the silicon substrate 2 and along the second surface 2b. Here, for example, when the silicon oxide film 3 is located on the surface of the silicon substrate 2 on the second surface 2b side, the solar cell element 1 includes a silicon substrate 2, a silicon oxide film 3, and an n-type polysilicon layer 4. For example, when the silicon oxide film 3 is located inside the silicon substrate 2 and along the second surface 2b, the solar cell element 1 includes a silicon substrate 2 including the silicon oxide film 3, and an n-type polysilicon layer 4. From another perspective, the silicon oxide film 3 is located in a state covering the first semiconductor region 21 from the second surface 2b side. The silicon oxide film 3 is a silicon oxide film. The thickness direction of the silicon oxide film 3 may be the +Z direction as a first thickness direction, as is the direction of the thickness of the silicon substrate 2, or the −Z direction as a second thickness direction. The thickness of the silicon oxide film 3 is set to, for example, 3 nanometers (nm) or less. This may cause, for example, a tunnel effect between the first semiconductor region 21 and the n-type polysilicon layer 4, which are positioned across the silicon oxide film 3. The thickness of the silicon oxide film 3 may be, for example, 2 nm or less. The lower limit of the thickness of the silicon oxide film 3 may be a thickness at which the presence of the silicon oxide film 3 can be confirmed by analysis using, for example, secondary ion mass spectrometry (SIMS).

[0040] The n-type polysilicon layer 4 is in contact with the silicon oxide film 3. In other words, the silicon oxide film 3 is in contact with both the first semiconductor region 21 and the n-type polysilicon layer 4. From another perspective, the n-type polysilicon layer 4 is located on the silicon oxide film 3. More specifically, the n-type polysilicon layer 4 is in contact with the surface of the silicon oxide film 3 opposite to the first semiconductor region 21. From another perspective, the n-type polysilicon layer 4 is located in a state covering the surface of the silicon oxide film 3 opposite to the first semiconductor region 21. From yet another perspective, the silicon oxide film 3 is located between the first semiconductor region 21 and the n-type polysilicon layer 4. Here, for example, when the silicon oxide film 3 is located inside the silicon substrate 2 and in a portion along the second surface 2b, the n-type polysilicon layer 4 is in contact with the silicon substrate 2. More specifically, for example, when the silicon oxide film 3 is located inside the silicon substrate 2 and along the second surface 2b, the n-type polysilicon layer 4 is in contact with the second surface 2b of the silicon substrate 2. This n-type polysilicon layer 4 is a layer of polycrystalline silicon doped with an impurity element (also referred to as a doped polysilicon layer). In the first embodiment, the n-type polysilicon layer 4 contains an n-type dopant as a dopant of the first conductivity type. From another perspective, the n-type polysilicon layer 4 is a layer of n-type polycrystalline silicon. Here, for example, a Group 15 element such as phosphorus (P) is used as the n-type dopant. The concentration of the n-type dopant in the n-type polysilicon layer 4 is, for example, 1×10 ２０ atoms / cm ３ From 1 x 10 ２２ atoms / cm ３The thickness of the n-type polysilicon layer 4 is set to a range of tens to hundreds of nanometers. This allows for high passivation performance to be achieved by a TOPCon structure, a type of POLO structure, in which the first semiconductor region 21, the silicon oxide film 3, and the n-type polysilicon layer 4 are stacked in this order. The thickness direction of the n-type polysilicon layer 4 may be a first thickness direction along the +Z direction, similar to the thickness directions of the silicon substrate 2 and the silicon oxide film 3, or a second thickness direction along the −Z direction. In the example of FIG. 2 , an arrow indicates a first thickness direction D1, which is the direction from the surface of the n-type polysilicon layer 4 opposite the silicon substrate 2 toward the silicon substrate 2. The thickness of the n-type polysilicon layer 4 is set to a range of, for example, several tens to several hundreds of nanometers. For example, the thickness of the n-type polysilicon layer 4 may be set to a range of 30 to 250 nm.

[0041] The first anti-reflection film 5 is located on the back surface 1b of the solar cell element 1. The first anti-reflection film 5 is located on the n-type polysilicon layer 4. More specifically, the first anti-reflection film 5 is located in a state where it covers substantially the entire surface of the n-type polysilicon layer 4 opposite the silicon oxide film 3, except for the region where the first electrode 6 is located. The first anti-reflection film 5 is, for example, a silicon nitride film. The first anti-reflection film 5 has, for example, the role of protecting the n-type polysilicon layer 4 and the role of reducing light reflection on the back surface 1b of the solar cell element 1. The thickness direction of the first anti-reflection film 5 may be the +Z direction as a first thickness direction, or the −Z direction as a second thickness direction, which is the same as the thickness directions of the silicon substrate 2, the silicon oxide film 3, and the n-type polysilicon layer 4. The thickness of the first anti-reflection film 5 is set, for example, in the range of several nanometers to 100 nanometers.

[0042] The first electrode 6 is located on the back surface 1b of the solar cell element 1. The first electrode 6 collects carriers generated by photoelectric conversion in response to light irradiation in the solar cell element 1 on the back surface 1b of the solar cell element 1 and extracts electricity to the outside of the solar cell element 1. The first electrode 6 is located on the n-type polysilicon layer 4 and penetrates the first antireflection film 5. In other words, the first electrode 6 contacts the n-type polysilicon layer 4 inside a through-hole (also referred to as a first through-hole) in the first antireflection film 5. Here, the form in which the first electrode 6 is located on the n-type polysilicon layer 4 may include a form in which the first electrode 6 reaches a recess in the n-type polysilicon layer 4 located on the first electrode 6 side. The first through-hole may be formed, for example, by laser beam irradiation or etching using photolithography, or by firing through (also referred to as fire-through) the first antireflection film 5 when forming the first electrode 6. The shape of the first electrode 6 in a planar view may be, for example, a grid. In this case, for example, the first electrode 6 may have a configuration in which a plurality of first busbar electrodes, each having a longitudinal direction along the +Y direction, intersect with a plurality of first finger electrodes, each having a longitudinal direction along the +X direction and thinner than the first busbar electrodes. The width of the first busbar electrodes is set, for example, in the range of 0.5 mm to 3 mm. The width of the first finger electrodes is set, for example, in the range of 10 μm to 150 μm. The spacing between the plurality of first finger electrodes is set, for example, in the range of 0.5 mm to 3 mm. The thickness direction of the first electrode 6 may be the +Z direction as a first thickness direction, or the −Z direction as a second thickness direction, which is the same as the thickness directions of the silicon substrate 2, the silicon oxide film 3, the n-type polysilicon layer 4, and the first anti-reflection coating 5. The thickness of the first electrode 6 is set, for example, in the range of 5 μm to 50 μm.

[0043] In the example of FIG. 1 , two first bus bar electrodes of the first electrode 6 are depicted. By joining wiring materials to these two first bus bar electrodes with solder or the like, electricity can be extracted to the outside of the solar cell element 1 via the first electrode 6. The first electrode 6 contains, for example, a metal as a main component. Here, the term "main component" may mean a content ratio of 50% or more. The metal as a main component of the first electrode 6 may be, for example, any of silver (Ag), copper (Cu), a mixture of aluminum (Al) and silver, and a mixture of titanium (Ti), lead (Pb), and silver.

[0044] The solar cell element 1 includes a passivation film 7 , a second anti-reflection film 8 , and a second electrode 9 on the front surface 1 f side of the silicon substrate 2 .

[0045] The passivation film 7 is located on the first surface 2f of the silicon substrate 2. More specifically, the passivation film 7 is located in a state where it covers substantially the entire first surface 2f of the silicon substrate 2 except for the region where the second electrode 9 is located. In other words, the passivation film 7 is in contact with the second semiconductor region 22 of the silicon substrate 2. The passivation film 7 may be, for example, an aluminum oxide layer or a silicon oxide layer. The passivation film 7 serves to reduce the recombination of minority carriers generated by photoelectric conversion in response to light irradiation in the silicon substrate 2 by passivating the first surface 2f of the silicon substrate 2. The thickness direction of the passivation film 7 may be the +Z direction as the first thickness direction, as is the thickness direction of the silicon substrate 2, or the −Z direction as the second thickness direction. The thickness of the passivation film 7 is set to, for example, a range of several nanometers to 100 nanometers. The thickness of the passivation film 7 may be set in the range of, for example, several nm to 50 nm.

[0046] The second anti-reflection film 8 is located on the front surface 1f of the solar cell element 1. The second anti-reflection film 8 is located on the passivation film 7. More specifically, the second anti-reflection film 8 is located in a state where it covers substantially the entire surface of the passivation film 7 opposite the silicon substrate 2. The second anti-reflection film 8 is, for example, a silicon nitride film. The second anti-reflection film 8, together with the passivation film 7, serves to reduce the reflectance of light irradiated onto the front surface 1f of the solar cell element 1. The thickness direction of the second anti-reflection film 8 may be the +Z direction as a first thickness direction, or the −Z direction as a second thickness direction, similar to the thickness directions of the silicon substrate 2 and the passivation film 7. The thickness of the second anti-reflection film 8 is set to, for example, a range of several nanometers to 100 nanometers.

[0047] The second electrode 9 is an electrode located on the front surface 1f of the solar cell element 1, which collects carriers generated by photoelectric conversion in response to light irradiation in the solar cell element 1 and extracts electricity from the solar cell element 1. The second electrode 9 is located on the first surface 2f of the silicon substrate 2 and penetrates the second anti-reflection film 8 and the passivation film 7. In other words, the second electrode 9 is in contact with the first surface 2f inside a through-hole (also referred to as a second through-hole) that penetrates the second anti-reflection film 8 and the passivation film 7. The second through-hole may be formed, for example, by laser beam irradiation or etching using photolithography, or by firing through the second anti-reflection film 8 and the passivation film 7 during the formation of the second electrode 9. The second electrode 9 may have, for example, a grid-like shape in plan view. In this case, for example, the second electrode 9 may have a configuration in which a plurality of second busbar electrodes, each having a longitudinal direction along the +Y direction, intersect with a plurality of second finger electrodes, each having a longitudinal direction along the +X direction and thinner than the second busbar electrodes. The width of the second busbar electrodes is set, for example, in the range of 0.5 mm to 3 mm. The width of the second finger electrodes is set, for example, in the range of 10 μm to 150 μm. The spacing between the plurality of second finger electrodes is set, for example, in the range of 0.5 mm to 3 mm. The thickness of the second electrode 9 is set, for example, in the range of 5 μm to 50 μm.

[0048] 1 illustrates two second bus bar electrodes of the second electrode 9. By joining wiring material to the two second bus bar electrodes with solder or the like, it is possible to extract electricity to the outside of the solar cell element 1 via the second electrode 9. The second electrode 9 contains, for example, a metal as a main component. The metal as a main component of the second electrode 9 may be, for example, any of silver, copper, a metal mixture of aluminum and silver, and a metal mixture of titanium, lead, and silver.

[0049] 2. Manufacturing of Solar Cell Element An example of a manufacturing method of the solar cell element 1 according to the first embodiment will be described with reference to Fig. 3 and Figs. 4 to 13. Fig. 3 is a flow chart showing an example of a manufacturing method of the solar cell element 1 according to the first embodiment. Figs. 4 to 13 are cross-sectional views each showing an example of a configuration during manufacturing of the solar cell element 1 according to the first embodiment. Here, the solar cell element 1 can be manufactured by performing the processes of steps S1 to S8 in Fig. 3 in the order shown.

[0050] In step S1, a silicon substrate 2 is prepared. For example, as shown in FIG. 4, the silicon substrate 2 has a first surface 2f and a second surface 2b opposite to the first surface 2f. A substrate of n-type crystalline silicon having a first conductivity type is used as the silicon substrate 2. More specifically, the silicon substrate 2 contains, for example, a group 15 element such as phosphorus (P) as an n-type dopant. The concentration of the n-type dopant in the silicon substrate 2 is, for example, 1×10 １５ atoms / cm ３ From 1 x 10 １７ atoms / cm ３ The thickness of the silicon substrate 2 is set within the range of 0.01 μm. Here, the silicon substrate 2 can be obtained by slicing an n-type crystalline silicon ingot produced by, for example, the Czochralski (CZ) method or a casting method into thin slices having a thickness of 250 μm or less. Here, for example, a slight etching process may be performed on the cut surface of the silicon substrate 2 when the silicon substrate 2 is cut from the silicon ingot. For example, an alkaline aqueous solution such as sodium hydroxide or potassium hydroxide, or an acidic aqueous solution such as fluoronitric acid is used as an etching solution for the etching process. This allows mechanically damaged layers and contaminated layers on the cut surface of the silicon substrate 2 to be removed.

[0051] In step S2, a textured structure is formed on the first surface 2f of the silicon substrate 2. For example, as shown in FIG. 5 , the textured structure is formed over the entire first surface 2f of the silicon substrate 2. The textured structure may be formed, for example, by wet or dry etching of the first surface 2f of the silicon substrate 2. Wet etching may be performed using, for example, an alkaline aqueous solution such as sodium hydroxide or an acidic aqueous solution such as fluoronitric acid. Dry etching may be performed using, for example, reactive ion etching (RIE). After the textured structure is formed on the first surface 2f of the silicon substrate 2, the oxide film on the entire surface of the silicon substrate 2 may be removed by RCA cleaning or the like.

[0052] In step S3, a second semiconductor region 22 is formed in a portion located inside the silicon substrate 2 and along the first surface 2f having a textured structure. The second semiconductor region 22 is a region of p-type crystalline silicon as the second conductivity type. The second semiconductor region 22 is a region containing a p-type dopant such as boron, for example. Here, before the second semiconductor region 22 is formed in the portion located inside the silicon substrate 2 and along the first surface 2f, the surface of the silicon substrate 2 may be cleaned with an aqueous solution containing hydrofluoric acid. The second semiconductor region 22 is formed by, for example, gaseous boron tribromide (BBr ３ The diffusion source may be boron tribromide, boron trifluoride (BF), or the like. ３ ) and boron trichloride (BCl ３ The concentration of the p-type dopant in the second semiconductor region 22 may be, for example, 1×10 ２０ atoms / cm ３ From 1 x 10 ２２ atoms / cm ３The thickness of the second semiconductor region 22 is set to a range of 0.1 μm to 2 μm, for example. As a result, for example, as shown in FIG. 6 , in the silicon substrate 2, the second semiconductor region 22 is located in a portion along the first surface 2 f, and the remaining portion excluding the second semiconductor region 22 is the first semiconductor region 21, which is a region of n-type crystalline silicon as the first conductivity type. In other words, the silicon substrate 2 is a crystalline silicon substrate including the n-type first semiconductor region 21 as the first conductivity type.

[0053] Here, when the second semiconductor region 22 is formed, if a region of p-type crystalline silicon (also referred to as a p-type region) as the second conductivity type is also formed in a portion located inside the silicon substrate 2 and along the second surface 2b, this p-type region is removed by etching using an aqueous solution of fluoronitric acid or the like. Also, for example, if boron glass is attached to the first surface 2f side of the silicon substrate 2 when the second semiconductor region 22 is formed, this boron glass is removed by etching. Here, for example, a diffusion mask may be formed in advance on the second surface 2b side of the silicon substrate 2, the second semiconductor region 22 may be formed by vapor phase thermal diffusion or the like, and the diffusion mask may then be removed.

[0054] In step S4, as an example of a first process, a process of forming a silicon oxide film 3 in contact with the first semiconductor region 21 of the silicon substrate 2 is performed. Here, the silicon oxide film 3 may be formed in a portion located inside the silicon substrate 2 and along the surface of the silicon substrate 2, or the silicon oxide film 3 may be formed on the surface of the silicon substrate 2. More specifically, the silicon oxide film 3 may be formed in a portion located inside the silicon substrate 2 and along the second surface 2b, or the silicon oxide film 3 may be formed on the second surface 2b of the silicon substrate 2. For example, as shown in FIG. 7 , the silicon oxide film 3 is formed along the entire surface of the second surface 2b of the silicon substrate 2. The silicon oxide film 3 may be formed by one or a combination of two or more of a chemical reaction method, a thermal reaction method, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a plasma reaction method, a steam oxidation method, and an ozone oxidation method. The chemical reaction method may be, for example, a method in which the silicon substrate 2 is immersed in nitric acid at about 100 degrees Celsius (100°C) to oxidize the surface of the silicon substrate 2. The thermal reaction method may be a method in which the silicon substrate 2 is heated to a high temperature, such as 600°C to 1100°C, in an oxygen atmosphere to modify the surface of the silicon substrate 2 into a silicon oxide film (also referred to as a silicon oxide film). The CVD method may be, for example, an LPCVD method. When the LPCVD method is used to form the silicon oxide film 3, for example, a mask may be provided on the first surface 2f of the silicon substrate 2, or the oxide film formed on the first surface 2f of the silicon substrate 2 may be removed with hydrofluoric acid or the like. The plasma reaction method may be, for example, a plasma-enhanced atomic layer deposition (PEALD) method in which plasma is used to promote a reaction in the ALD method. The plasma reaction method may be, for example, a method in which plasma is used to promote a reaction in thermal oxidation. The thickness of the silicon oxide film 3 may be set to, for example, 3 nm or less, or 2 nm or less.The lower limit of the thickness of the silicon oxide film 3 may be a thickness that allows the presence of the silicon oxide film 3 to be confirmed by analysis using, for example, SIMS, etc. In other words, the silicon oxide film 3 may be an extremely thin oxide film (also referred to as an ultrathin oxide film).

[0055] In step S5, an n-type polysilicon layer 4 is formed on the silicon oxide film 3. In step S5, the processes of steps S51 to S53 in FIG. 3 are performed in this order, so that the n-type polysilicon layer 4 can be formed.

[0056] In step S51, as an example of the second process, an intrinsic crystalline silicon layer 4a is formed as a layer of intrinsic crystalline silicon (also referred to as the first layer) on the silicon oxide film 3. For example, as shown in FIG. 8, the intrinsic crystalline silicon layer 4a is formed on the surface of the silicon oxide film 3 opposite to the first semiconductor region 21. The intrinsic crystalline silicon is crystalline silicon that does not substantially contain dopants. Here, "crystalline silicon that does not substantially contain dopants" means that the crystalline silicon does not contain 8×10 ions that may be unavoidably mixed in during the crystalline silicon film formation process. １９ atoms / cm ３ In other words, the crystalline silicon being substantially free of dopants means that the crystalline silicon may contain dopants in a concentration of 8×10 １９ atoms / cm ３This means that the intrinsic crystalline silicon layer 4a does not contain a dopant at a concentration exceeding 1000°C. The intrinsic crystalline silicon layer 4a may be, for example, an intrinsic polycrystalline silicon layer. For example, after an amorphous silicon layer substantially free of dopants (also referred to as an intrinsic amorphous silicon layer or an i-type amorphous silicon layer) is formed, the intrinsic amorphous silicon layer is subjected to a heat treatment to promote crystallization of the amorphous silicon, thereby forming the intrinsic crystalline silicon layer 4a. The temperature of this heat treatment is set, for example, within a range of 550°C to 1000°C. In this case, the intrinsic crystalline silicon layer 4a is a polysilicon layer substantially free of dopants (also referred to as an intrinsic polysilicon layer). For example, after the intrinsic crystalline silicon layer 4a is formed, the oxide films on the surfaces of the second semiconductor region 22 of the silicon substrate 2 and the intrinsic crystalline silicon layer 4a formed up to the intrinsic crystalline silicon layer 4a may be removed with an aqueous solution containing hydrofluoric acid. The thickness of the intrinsic crystalline silicon layer 4a is set to, for example, 1 nm to 50 nm or less. The intrinsic crystalline silicon layer 4a may be formed by stacking two or more films of intrinsic polysilicon, for example.

[0057] In step S52, as an example of a third process, an n-type amorphous silicon layer 4b is formed on the intrinsic crystalline silicon layer 4a as an amorphous silicon layer (also referred to as a second layer) having a thickness greater than that of the intrinsic crystalline silicon layer 4a and containing an n-type dopant as a dopant of the first conductivity type. Here, the n-type amorphous silicon layer 4b is formed using, for example, a PECVD method. For example, as shown in FIG. 9, the n-type amorphous silicon layer 4b is formed on the surface of the intrinsic crystalline silicon layer 4a opposite to the silicon oxide film 3. For example, phosphorus (P) or the like is used as the n-type dopant contained in the n-type amorphous silicon layer 4b. The n-type amorphous silicon layer 4b is formed by, for example, using monosilane (SiH) as a gaseous raw material (also referred to as a raw material gas). ４ ) gas and phosphine (PH ３ In this case, since phosphorus is introduced as an n-type dopant, phosphine gas, phosphorus trifluoride (PF ) gas, and３ ) gas and phosphorus pentafluoride (PF ５ ) gases may be employed. The thickness of the n-type amorphous silicon layer 4b is set to, for example, 20 nm to 200 nm. For example, when the first electrode 6 is formed by firing through the first anti-reflection film 5, if the thickness of the n-type amorphous silicon layer 4b is set to a certain thickness or greater, such as 100 nm or greater, the first electrode 6 will not fire through to the n-type polysilicon layer 4 when firing through the first anti-reflection film 5. This reduces the reduction in the area on the surface of the silicon substrate 2 where the TOPCon structure, in which the first semiconductor region 21, the silicon oxide film 3, and the n-type polysilicon layer 4 are stacked in this order, is present. As a result, the degradation of the passivation performance due to the TOPCon structure in the solar cell element 1 can be reduced. If the thickness of the n-type amorphous silicon layer 4b is set to a certain thickness or less, such as 200 nm or less, the time required to form the n-type amorphous silicon layer 4b and the amount of material required can be reduced, thereby improving the productivity of the solar cell element 1. Furthermore, if the thickness of the n-type amorphous silicon layer 4b is set to a certain thickness or less, such as 200 nm or less, the amount of light absorbed by the n-type polysilicon layer 4 can be reduced by reducing the thickness of the n-type polysilicon layer 4. The concentration of the n-type dopant in the n-type amorphous silicon layer 4b is, for example, 1×10 ２０ atoms / cm ３ From 1 x 10 ２２ atoms / cm ３ This ensures the concentration of the n-type dopant in the n-type polysilicon layer 4, and thus high passivation performance can be achieved by the TOPCon structure in the solar cell element 1.

[0058] In step S53, as an example of a fourth process, a process of forming an n-type polysilicon layer 4 by heat treatment is performed. Here, for example, as shown in FIG. 10, the intrinsic crystalline silicon layer 4a and the n-type amorphous silicon layer 4b stacked on the silicon oxide film 3 shown in FIG. 9 are transformed into an n-type polysilicon layer 4. Here, a heat treatment is performed to promote crystallization of the amorphous silicon of the n-type amorphous silicon layer 4b while diffusing the n-type dopant contained in the n-type amorphous silicon layer 4b toward the intrinsic crystalline silicon layer 4a and the silicon oxide film 3. As a result, an n-type polysilicon layer 4 located on the silicon oxide film 3 and containing an n-type dopant can be generated from the intrinsic crystalline silicon layer 4a and the n-type amorphous silicon layer 4b. Here, the temperature of the heat treatment (also referred to as a heat treatment temperature) is set, for example, within a range of 550°C to 1000°C. For example, if the heat treatment temperature is set within a range of 700° C. to 1000° C., it is possible to reduce the sheet resistance by activating the dopant in the n-type polysilicon layer 4. Furthermore, if the heat treatment temperature is set within a range of 700° C. to 900° C., it is possible to achieve high passivation performance due to the TOPCon structure in the solar cell element 1.

[0059] In the above-described step S5, before the n-type amorphous silicon layer 4b is formed as the second layer of amorphous silicon containing the first conductivity type dopant, an intrinsic crystalline silicon layer 4a having a thickness smaller than that of the n-type amorphous silicon layer 4b is formed on the silicon oxide film 3. When this intrinsic crystalline silicon layer 4a is formed, even if hydrogen bonded to silicon in the intrinsic amorphous silicon layer is desorbed by a heat treatment for promoting crystallization of the intrinsic amorphous silicon layer, the hydrogen can be released from the surface of the intrinsic amorphous silicon layer opposite to the silicon oxide film 3. This reduces the aggregation of hydrogen gas at the interface between the silicon oxide film 3 and the intrinsic crystalline silicon layer 4a. Furthermore, because the thickness of the intrinsic amorphous silicon layer before being transformed into the intrinsic crystalline silicon layer 4a by the heat treatment is small, the increase in stress that may cause the silicon layer to peel off from the silicon oxide film 3 due to the contraction of the silicon layer when the intrinsic amorphous silicon layer is transformed into the intrinsic crystalline silicon layer 4a by the heat treatment can be reduced. These factors can improve the adhesion between the silicon oxide film 3 and the intrinsic crystalline silicon layer 4a. As a result, when a heat treatment is performed to promote the crystallization of amorphous silicon in the n-type amorphous silicon layer 4b formed on the intrinsic crystalline silicon layer 4a, the aggregation of hydrogen gas between the silicon oxide film 3 and the intrinsic crystalline silicon layer 4a is reduced, and hydrogen can be released from the surface of the n-type amorphous silicon layer 4b opposite to the silicon oxide film 3 and can migrate toward the silicon substrate 2. This can reduce the occurrence of blisters at the interface between the silicon oxide film 3 and the n-type polysilicon layer 4. This can also reduce the occurrence of local defects in the n-type polysilicon layer 4 due to these blisters.

[0060] In other words, in the above-described step S5, when the n-type polysilicon layer 4 is formed on the silicon oxide film 3, an intrinsic crystalline silicon layer 4a is formed on the silicon oxide film 3, and an n-type amorphous silicon layer 4b is further formed on the intrinsic crystalline silicon layer 4a, and then the n-type polysilicon layer 4 is produced from the intrinsic crystalline silicon layer 4a and the n-type amorphous silicon layer 4b by heat treatment. This can reduce the occurrence of blisters at the interface between the silicon oxide film 3 and the n-type polysilicon layer 4, and can also reduce the occurrence of local defects in the n-type polysilicon layer 4 due to these blisters.

[0061] Therefore, the occurrence of blisters and local defects due to blisters can be reduced when the n-type polysilicon layer 4 is formed as a doped polysilicon layer using a PECVD method or the like. In other words, defects can be reduced in the solar cell element 1 having an example of a TOPCon structure, which is a type of POLO structure formed using a doped amorphous silicon layer. From another perspective, defects in the solar cell element 1 can be easily reduced. Furthermore, in the solar cell element 1 according to the first embodiment, the reduction in the area on the surface of the silicon substrate 2 where the TOPCon structure, in which the first semiconductor region 21, the silicon oxide film 3, and the n-type polysilicon layer 4 are stacked in this order, is reduced. This reduces the degradation of passivation performance due to the TOPCon structure in the solar cell element 1 according to the first embodiment. As a result, the conversion efficiency of the solar cell element 1 can be easily improved.

[0062] In step S6, a passivation film 7 is formed on the first surface 2f of the silicon substrate 2. For example, as shown in FIG. 11 , the passivation film 7 is formed over the entire surface of the second semiconductor region 22 on the side opposite to the first semiconductor region 21. For example, if an aluminum oxide layer is applied to the passivation film 7, the aluminum oxide layer may be formed by the ALD method. For example, if a silicon oxide layer is applied to the passivation film 7, the silicon oxide layer may be formed by the PECVD method. Here, before the passivation film 7 is formed, the first surface 2f of the silicon substrate 2 may be cleaned with an aqueous solution containing hydrofluoric acid.

[0063] In step S7, anti-reflection films are formed on each of the first surface 2f and the second surface 2b of the silicon substrate 2. For example, as shown in FIG. 12 , a first anti-reflection film 5 is formed over the entire surface of the n-type polysilicon layer 4 opposite the silicon substrate 2, and a second anti-reflection film 8 is formed over the entire surface of the passivation film 7 opposite the silicon substrate 2. For example, when a silicon nitride layer is applied to each of the first anti-reflection film 5 and the second anti-reflection film 8, the silicon nitride layer may be formed by a PECVD method. Here, before the first anti-reflection film 5 and the second anti-reflection film 8 are formed, each of the surface of the n-type polysilicon layer 4 opposite the silicon substrate 2 and the surface of the passivation film 7 opposite the silicon substrate 2 may be cleaned with an aqueous solution containing hydrofluoric acid.

[0064] In step S8, electrodes are formed on each of the first surface 2f and the second surface 2b of the silicon substrate 2. For example, as shown in FIG. 1, a first electrode 6 is formed on the second surface 2b of the silicon substrate 2, and a second electrode 9 is formed on the first surface 2f of the silicon substrate 2. Here, for example, as shown in FIG. 13, a first metal paste 6p may be applied to the first anti-reflection film 5 by screen printing or the like, and the first metal paste 6p may be fired to form the first electrode 6. Alternatively, as shown in FIG. 13, a second metal paste 9p may be applied to the second anti-reflection film 8 by screen printing or the like, and the second metal paste 9p may be fired to form the second electrode 9. Here, each of the first metal paste 6p and the second metal paste 9p may contain a metal powder, an organic vehicle, and a glass frit. The metal powder may be, for example, any of silver powder, copper powder, a mixture of aluminum powder and silver powder, and a mixture of titanium powder, lead powder, and silver powder. The maximum temperature at which the first metal paste 6p and the second metal paste 9p are fired is set to, for example, a range of 600°C to 800°C. When the first metal paste 6p is fired, the glass frit in the first metal paste 6p melts, causing a fire-through of the first anti-reflection film 5. This allows the first electrode 6 to penetrate the first anti-reflection film 5 and connect to the n-type polysilicon layer 4. When the second metal paste 9p is fired, the glass frit in the second metal paste 9p melts, causing a fire-through of the second anti-reflection film 8 and the passivation film 7. As a result, the second electrode 9 penetrates the second anti-reflection film 8 and the passivation film 7 and is connected to the second semiconductor region 22 .

[0065] In this manner, the solar cell element 1 having the configuration shown in FIG. 1 can be manufactured.

[0066] 3. Various specific examples and reference examples related to TOPCon structure Various specific examples that were produced to evaluate the TOPCon structure that can be manufactured by the manufacturing method of the solar cell element 1 according to the first embodiment described above will be described.

[0067] 14 is a flowchart showing a method for fabricating samples of various specific examples of the TOPCon structure. The processes of steps Sa1 to Sa5 in FIG. 14 were performed in this order to fabricate samples of various specific examples of the TOPCon structure. The conditions under which the samples of the various specific examples described below were fabricated are examples of conditions adopted to confirm the feasibility and effects of the present disclosure, and the present disclosure is not limited to these examples of conditions.

[0068] 15 is a flowchart showing a method for fabricating various reference example samples relating to the TOPCon structure. The processes of steps Sb1 to Sb4 in FIG. 15 were performed in the order shown, thereby fabricating various reference example samples relating to the TOPCon structure. The process flow of steps Sb1 to Sb4 in FIG. 15 corresponds to the process flow of steps Sa1 to Sa5 in FIG. 14 with step Sa3 deleted.

[0069] Each of the various specific examples of the TOPCon structure was fabricated by forming a silicon oxide film (silicon oxide film) corresponding to the silicon oxide film 3 on a crystalline silicon substrate (also called a crystalline silicon substrate) corresponding to the silicon substrate 2, and then forming an n-type polysilicon layer (also called an n-type polysilicon layer) corresponding to the n-type polysilicon layer 4 on this silicon oxide film, in the order described above.

[0070] Here, for the crystalline silicon substrate, the concentration of n-type dopant is 1×10 １６ atoms / cm ３ A substrate of n-type crystalline silicon with a dopant concentration of about 1×10 １６ atoms / cm ３ The n-type polysilicon layer had an n-type dopant concentration of about 1×10 ２０ atoms / cm ３ From 1 x 10 ２２ atoms / cm ３It was assumed that, regardless of whether an n-type crystalline silicon substrate or a p-type crystalline silicon substrate is used as the crystalline silicon substrate, the defect occurrence state, characteristics, and dopant concentration distribution in the silicon oxide film and n-type polysilicon layer formed on the crystalline silicon substrate will be approximately the same, provided other film formation conditions are the same. Various specific examples and reference example samples were therefore prepared on the assumption that. For example, when a p-type crystalline silicon substrate is used as the crystalline silicon substrate, a depletion layer is generated in the vicinity of the oxide film in the crystalline silicon substrate. For this reason, a p-type crystalline silicon substrate was used as the crystalline silicon substrate in order to more accurately measure the sheet resistance of the n-type polysilicon layer, which will be described later. Furthermore, for example, when the passivation performance of the TOPCon structure was measured using the Quasi-Steady-State Photo Conductance (QSSPC) method, the time it takes for carriers generated by excitation such as light irradiation to recombine (also referred to as carrier lifetime or simply lifetime) and the implied Voc (iVoc) were measured, an n-type crystalline silicon substrate was used as the crystalline silicon substrate. iVoc is an index for evaluating the open-circuit voltage of a solar cell element without contact and without electrodes.

[0071] <3-1. Fabrication of Samples of Various Specific Examples and Reference Examples> <3-1-1. Fabrication of Samples of Specific Examples 1 to 8> First, a crystalline silicon substrate was prepared (step Sa1 in FIG. 14 ). Here, a p-type crystalline silicon substrate (also simply referred to as a substrate) was prepared as the crystalline silicon substrate. As the p-type crystalline silicon substrate, a single-crystal silicon substrate doped with boron as a p-type dopant (also referred to as a p-type single-crystal silicon substrate) was used. As the p-type single-crystal silicon substrate, a wafer was used whose one main surface corresponding to the second surface 2b was in a mirror-finished state. The mirror-finished surface was achieved by mechanical polishing using an abrasive for mirror finishing. The unevenness on the mirror-finished surface was estimated to be several nanometers or less.

[0072] Next, a silicon oxide film (silicon oxide film) was formed on the substrate (step Sa2 in FIG. 14). Here, the surface of the substrate was cleaned using hydrofluoric acid to remove native oxide on the surface of the substrate. The substrate was then immersed in nitric acid heated to 90°C to 100°C for 10 minutes, forming a silicon oxide film with a thickness of 2 nm or less on the surface of the substrate.

[0073] Next, an intrinsic crystalline silicon layer was formed on the silicon oxide film (step Sa3 in FIG. 14 ). Here, an intrinsic amorphous silicon layer was formed by PECVD on the silicon oxide film formed on the mirror-finished main surface of the substrate. The substrate temperature was set to 275°C, and monosilane gas was used as the source gas. An intrinsic amorphous silicon layer having a thickness (also referred to as the first thickness) ti1 of 10 nm was formed. Then, crystallization of the amorphous silicon in the amorphous silicon layer was promoted by heat treatment. As a result, the intrinsic amorphous silicon layer was transformed into an intrinsic polysilicon layer. This heat treatment was performed in a nitrogen gas atmosphere in a heating furnace. In this heat treatment, the substrate was loaded into the heating furnace with the temperature inside the heating furnace at room temperature, the temperature inside the heating furnace was increased from room temperature to 400°C at a rate of 100°C per hour, then held at 400°C for 30 minutes, and then further decreased from 400°C to room temperature at a rate of 100°C per hour, and then the substrate was removed from the heating furnace. Then, the substrate was loaded into the heating furnace again with the temperature inside the heating furnace at 550°C, the temperature inside the heating furnace was increased from 550°C to 850°C at a rate of 100°C per hour, then held at 850°C for 30 minutes, and then further decreased from 850°C to 550°C at a rate of 100°C per hour, and then the substrate was removed from the heating furnace. Here, the oxide film formed on the surface of the intrinsic crystalline silicon layer was removed by cleaning using hydrofluoric acid. In this case, a region of the intrinsic crystalline silicon layer having a thickness of about 1 nm to 2 nm from the surface was removed by cleaning with hydrofluoric acid.

[0074] Next, an n-type amorphous silicon layer (also referred to as an n-type amorphous silicon layer) was formed on the intrinsic crystalline silicon layer using the PECVD method (step Sa4 in FIG. 14 ). Here, an amorphous silicon layer doped with phosphorus (P) as an n-type dopant (also referred to as a P-doped amorphous silicon layer) was formed. The substrate temperature was set to 275° C., and monosilane gas and phosphine gas diluted with hydrogen were used as source gases to form a P-doped amorphous silicon layer having a thickness (also referred to as a second thickness) tn2 of 50 nm. Regarding the flow rates of the source gases introduced into the reaction chamber, the ratio of the flow rate of monosilane gas to the flow rate of phosphine gas was set to 40 [sccm]:20 [sccm]. Here, the unit of gas flow rate, [sccm], is the volumetric flow rate (standard cubic centimeter per minute) at 1 atmosphere and 0° C., i.e., cubic centimeters per minute (cm ) at standard conditions. ３ / min).

[0075] Next, an n-type polysilicon layer was formed by heat treatment (step Sa5 in FIG. 14 ). Here, the heat treatment promoted the crystallization of the amorphous silicon in the P-doped amorphous silicon layer, and also diffused P (phosphorus) as an n-type dopant contained in the P-doped amorphous silicon layer into the intrinsic crystalline silicon layer. This transformed the intrinsic crystalline silicon layer and the P-doped amorphous silicon layer into a phosphorus (P)-doped polysilicon layer serving as an n-type polysilicon layer. This heat treatment was performed in a nitrogen gas atmosphere in a heating furnace. In this heat treatment, the substrate was loaded into the heating furnace with the temperature in the heating furnace at room temperature. The temperature in the heating furnace was then increased from room temperature to 400°C at a rate of 100°C per hour, then held at 400°C for 30 minutes, and then further decreased from 400°C to room temperature at a rate of 100°C per hour, after which the substrate was removed from the heating furnace. Thereafter, with the temperature inside the heating furnace set to 550°C, the substrate was again loaded into the heating furnace, and the temperature inside the heating furnace was raised from 550°C to a maximum temperature (heat treatment temperature) T1 [°C] at a rate of 100°C per hour, then held at the maximum temperature (heat treatment temperature) T1 [°C] for 30 minutes, and then further lowered from the maximum temperature (heat treatment temperature) T1 [°C] to 550°C at a rate of 100°C per hour, after which the substrate was removed from the heating furnace.

[0076] Here, a sample of Specific Example 1 according to the TOPCon structure was obtained by setting the heat treatment temperature T1 [°C] to 550°C. A sample of Specific Example 2 according to the TOPCon structure was obtained by setting the heat treatment temperature T1 [°C] to 650°C. A sample of Specific Example 3 according to the TOPCon structure was obtained by setting the heat treatment temperature T1 [°C] to 700°C. A sample of Specific Example 4 according to the TOPCon structure was obtained by setting the heat treatment temperature T1 [°C] to 750°C. A sample of Specific Example 5 according to the TOPCon structure was obtained by setting the heat treatment temperature T1 [°C] to 800°C. A sample of Specific Example 6 according to the TOPCon structure was obtained by setting the heat treatment temperature T1 [°C] to 850°C. A sample of Specific Example 7 according to the TOPCon structure was obtained by setting the heat treatment temperature T1 [°C] to 900°C. A sample of Specific Example 8 according to the TOPCon structure was obtained by setting the heat treatment temperature T1 [°C] to 1000°C.

[0077] 3-1-2. Fabrication of Samples of Reference Example 1, Reference Example 2, Reference Example 4, and Reference Example 6 For comparison with the samples of Specific Example 1, Specific Example 2, Specific Example 4, and Specific Example 6, the samples of Reference Example 1, Specific Example 2, Specific Example 4, and Specific Example 6 were fabricated. The fabrication flow of the sample of Reference Example 1 was based on the fabrication flow of the sample of Specific Example 1, but excluding the process of step Sa3 in FIG. 14 , in which an intrinsic crystalline silicon layer is formed on a silicon oxide film. The fabrication flow of the sample of Reference Example 2 was based on the fabrication flow of the sample of Specific Example 2, but excluding the process of step Sa3 in FIG. 14 , in which an intrinsic crystalline silicon layer is formed on a silicon oxide film. The fabrication flow of the sample of Reference Example 4 was based on the fabrication flow of the sample of Specific Example 4, but excluding the process of step Sa3 in FIG. 14 , in which an intrinsic crystalline silicon layer is formed on a silicon oxide film. 14 , in which an intrinsic crystalline silicon layer is formed on a silicon oxide film, was removed, and the flow of the fabrication method for the sample of Reference Example 6 was used as the flow of the fabrication method for the sample of Reference Example 6. In other words, in the fabrication of each of the samples of Reference Examples 1, 2, 4, and 6, the first thickness ti1 was set to 0 nm.

[0078] More specifically, a crystalline silicon substrate was first prepared (step Sb1 in FIG. 15 ). Here, a p-type crystalline silicon substrate (also simply referred to as a substrate) was prepared under the same conditions as in step Sa1 in FIG. 14 in the fabrication of the samples of Specific Examples 1, 2, 4, and 6.

[0079] Next, a silicon oxide film was formed on the substrate (step Sb2 in FIG. 15 ) under the same conditions as in step Sa2 in FIG. 14 for fabricating the samples of Specific Examples 1, 2, 4, and 6. The silicon oxide film was formed to a thickness of 2 nm or less on the surface of the substrate.

[0080] Next, an n-type amorphous silicon layer was formed on the silicon oxide film using the PECVD method (step Sb3 in FIG. 15 ). Here, an amorphous silicon layer doped with phosphorus (P) as an n-type dopant (P-doped amorphous silicon layer) was formed on the silicon oxide film formed on the mirror-finished main surface side of the substrate. The conditions for forming the P-doped amorphous silicon layer were the same as those used in step Sa4 in FIG. 14 for fabricating the samples of Specific Examples 1, 2, 4, and 6. As a result, a P-doped amorphous silicon layer having a thickness (second thickness) tn2 of 50 nm was formed.

[0081] Next, an n-type polysilicon layer was formed by heat treatment (step Sb4 in FIG. 15 ). Here, the heat treatment promoted crystallization of the amorphous silicon in the P-doped amorphous silicon layer. As a result, the P-doped amorphous silicon layer was transformed into a polysilicon layer doped with phosphorus (P) as an n-type polysilicon layer. The conditions for this heat treatment were the same as those for step Sa5 in FIG. 14 in the fabrication of the samples of Specific Examples 1, 2, 4, and 6.

[0082] Here, the heat treatment temperature T1 [°C] was set to 550°C, the same as in the preparation of the sample of Specific Example 1, to obtain the sample of Reference Example 1 having a TOPCon structure. The heat treatment temperature T1 [°C] was set to 650°C, the same as in the preparation of the sample of Specific Example 2, to obtain the sample of Reference Example 2 having a TOPCon structure. The heat treatment temperature T1 [°C] was set to 750°C, the same as in the preparation of the sample of Specific Example 4, to obtain the sample of Reference Example 4 having a TOPCon structure. The heat treatment temperature T1 [°C] was set to 850°C, the same as in the preparation of the sample of Specific Example 6, to obtain the sample of Reference Example 6 having a TOPCon structure.

[0083] <3-1-3. Fabrication of Samples of Specific Examples 11 to 15> First, a crystalline silicon substrate was prepared (step Sa1 in FIG. 14 ). Here, an n-type crystalline silicon substrate (also simply referred to as a substrate) was prepared as the crystalline silicon substrate. A single-crystal silicon substrate doped with phosphorus (P) as an n-type dopant (also referred to as an n-type single-crystal silicon substrate) was used as the n-type crystalline silicon substrate. More specifically, a wafer serving as an n-type single-crystal silicon substrate was obtained by cutting the n-type single-crystal silicon substrate from an n-type single-crystal silicon ingot produced by the CZ method. Then, the surface of the n-type single-crystal silicon substrate was etched using potassium hydroxide to remove mechanically damaged and contaminated layers on the cut surface of the wafer that had been created when the wafer was cut from the ingot. The etching process was performed on the surface of the n-type single-crystal silicon substrate to form a textured structure. The surface of the n-type single crystal silicon substrate was then subjected to an etching treatment using a mixture of hydrofluoric acid, nitric acid, and acetic acid, thereby obtaining an n-type single crystal silicon substrate having a surface with a slightly flattened textured structure. Measurements of the surface irregularities of the n-type single crystal silicon substrate using a laser microscope focused on a 100 μm long region of the slightly flattened textured surface revealed irregularities with heights of approximately 1.6 μm to 2.9 μm. The height of the irregularities was defined as the difference in height between the top and bottom of the irregularities. The n-type single crystal silicon substrates prepared in this manner were used to fabricate the samples of Examples 11 to 15.

[0084] Next, a silicon oxide film was formed on the substrate (step Sa2 in FIG. 14). Here, the surface of the substrate was cleaned using hydrofluoric acid to remove native oxides and contaminants from the surface of the substrate. The substrate was then immersed in nitric acid heated to 90°C to 100°C for 10 minutes, forming a silicon oxide film with a thickness of 2 nm or less on the surface of the substrate.

[0085] Next, an intrinsic crystalline silicon layer was formed on the silicon oxide film (step Sa3 in FIG. 14 ). Here, a PECVD method was used to sequentially form an intrinsic amorphous silicon layer on each of the silicon oxide films formed on both sides of the substrate. The substrate temperature was set to 275°C, and monosilane gas was used as the source gas to form an intrinsic amorphous silicon layer having a thickness (first thickness) ti1 of 10 nm. Then, a heat treatment was performed to promote crystallization of the amorphous silicon in the amorphous silicon layer. This transformed the intrinsic amorphous silicon layer into an intrinsic polysilicon layer. This heat treatment was performed in a nitrogen gas atmosphere in a heating furnace. In this heat treatment, the substrate was loaded into the heating furnace with the temperature inside the heating furnace at room temperature, the temperature inside the heating furnace was increased from room temperature to 400°C at a rate of 100°C per hour, then held at 400°C for 30 minutes, and then further decreased from 400°C to room temperature at a rate of 100°C per hour, and then the substrate was removed from the heating furnace. Then, the substrate was loaded into the heating furnace again with the temperature inside the heating furnace at 550°C, the temperature inside the heating furnace was increased from 550°C to 850°C at a rate of 100°C per hour, then held at 850°C for 30 minutes, and then further decreased from 850°C to 550°C at a rate of 100°C per hour, and then the substrate was removed from the heating furnace. Here, the oxide film formed on the surface of the intrinsic crystalline silicon layer was removed by cleaning using hydrofluoric acid. In this case, a region of the intrinsic crystalline silicon layer having a thickness of about 1 nm to 2 nm from the surface was removed by cleaning with hydrofluoric acid.

[0086] Next, using the PECVD method, n-type amorphous silicon layers were sequentially formed on the intrinsic crystalline silicon layers on both sides of the substrate (step Sa4 in FIG. 14 ). Here, an amorphous silicon layer doped with phosphorus (P) as an n-type dopant (P-doped amorphous silicon layer) was formed. The substrate temperature was set to 275° C., and monosilane gas and phosphine gas diluted with hydrogen were used as source gases to form a P-doped amorphous silicon layer having a thickness (second thickness) tn2 of 150 nm. In this case, the ratio of the flow rates of the monosilane gas and the phosphine gas introduced into the reaction chamber was set to 40 sccm:20 sccm.

[0087] Next, an n-type polysilicon layer was formed on each of the two surfaces of the substrate by heat treatment (step Sa5 in FIG. 14 ). Here, the heat treatment promoted the crystallization of the amorphous silicon in the P-doped amorphous silicon layer, and also diffused P (phosphorus) as an n-type dopant contained in the P-doped amorphous silicon layer into the intrinsic crystalline silicon layer. This transformed the intrinsic crystalline silicon layer and the P-doped amorphous silicon layer into a phosphorus (P)-doped polysilicon layer serving as an n-type polysilicon layer. This heat treatment was performed in a nitrogen gas atmosphere in a heating furnace. During this heat treatment, the substrate was loaded into the heating furnace with the temperature in the heating furnace at room temperature. The temperature in the heating furnace was then increased from room temperature to 400°C at a rate of 100°C per hour, then held at 400°C for 30 minutes, and then further decreased from 400°C to room temperature at a rate of 100°C per hour, after which the substrate was removed from the heating furnace. Thereafter, with the temperature inside the heating furnace set to 550°C, the substrate was again loaded into the heating furnace, and the temperature inside the heating furnace was raised from 550°C to a maximum temperature (heat treatment temperature) T1 [°C] at a rate of 100°C per hour, then held at the maximum temperature (heat treatment temperature) T1 [°C] for 30 minutes, and then further lowered from the maximum temperature (heat treatment temperature) T1 [°C] to 550°C at a rate of 100°C per hour, after which the substrate was removed from the heating furnace.

[0088] Here, a sample of specific example 11 relating to the TOPCon structure was obtained by setting the heat treatment temperature T1 [°C] to 750°C. A sample of specific example 12 relating to the TOPCon structure was obtained by setting the heat treatment temperature T1 [°C] to 800°C. A sample of specific example 13 relating to the TOPCon structure was obtained by setting the heat treatment temperature T1 [°C] to 850°C. A sample of specific example 14 relating to the TOPCon structure was obtained by setting the heat treatment temperature T1 [°C] to 900°C. A sample of specific example 15 relating to the TOPCon structure was obtained by setting the heat treatment temperature T1 [°C] to 950°C.

[0089] <3-1-4. Fabrication of Sample of Reference Example 13> A sample of Reference Example 13 was fabricated for comparison with the sample of Specific Example 13. Here, the fabrication method flow for the sample of Reference Example 13 was based on the fabrication method flow for the sample of Specific Example 13, and a fabrication method flow excluding the process of step Sa3 in FIG. 14 in which an intrinsic crystalline silicon layer is formed on a silicon oxide film was used as the fabrication method flow for the sample of Reference Example 13. In other words, in fabricating the sample of Reference Example 13, the first thickness ti1 was set to 0 nm.

[0090] More specifically, a crystalline silicon substrate was first prepared (step Sb1 in FIG. 15). Here, an n-type crystalline silicon substrate (also simply referred to as a substrate) was prepared as the crystalline silicon substrate under the same conditions as those in step Sa1 in FIG. 14 for fabricating the sample of specific example 13.

[0091] Next, a silicon oxide film was formed on the substrate (step Sb2 in FIG. 15) under the same conditions as in step Sa2 in FIG. 14 for preparing the sample of specific example 13. The silicon oxide film was formed on the surface of the substrate to a thickness of 2 nm or less.

[0092] Next, an n-type amorphous silicon layer was formed on the silicon oxide film on each of both surfaces of the substrate using the PECVD method (step Sb3 in FIG. 15). Here, an amorphous silicon layer doped with phosphorus (P) as an n-type dopant (P-doped amorphous silicon layer) was formed on the silicon oxide film formed on both surfaces of the substrate. The conditions for forming the P-doped amorphous silicon layer were the same as those used in step Sa4 in FIG. 14 for fabricating the sample of Example 13. As a result, a P-doped amorphous silicon layer having a thickness (second thickness) tn2 of 150 nm was formed.

[0093] Next, an n-type polysilicon layer was formed on each of the two surfaces of the substrate by heat treatment (step Sb4 in FIG. 15). Here, the heat treatment promoted crystallization of the amorphous silicon in the P-doped amorphous silicon layer. As a result, the P-doped amorphous silicon layer was transformed into a polysilicon layer doped with phosphorus (P) as an n-type polysilicon layer. The conditions for this heat treatment were the same as those for step Sa5 in FIG. 14 in the preparation of the sample of Example 13.

[0094] Here, the heat treatment temperature T1 [° C.] was set to 850° C., the same as in the preparation of the sample of Specific Example 13, and the sample of Reference Example 13 having a TOPCon structure was obtained.

[0095] <3-1-5. Preparation of Samples of Specific Examples 21 to 25> For the purpose of more accurately measuring the sheet resistance of the n-type polysilicon layer of each of the samples of Specific Examples 11 to 15, samples of Specific Examples 21 to 25 were prepared in which the crystalline silicon substrate in each of the samples of Specific Examples 11 to 15 was changed from an n-type crystalline silicon substrate to a p-type crystalline silicon substrate.

[0096] More specifically, a sample of Example 21 was fabricated based on the sample of Example 11, except that the crystalline silicon substrate was changed from an n-type crystalline silicon substrate to a p-type crystalline silicon substrate. The fabrication method for the sample of Example 21 was based on the fabrication method for the sample of Example 11, except that the n-type crystalline silicon substrate was changed to a p-type crystalline silicon substrate. A sample of Example 22 was fabricated based on the sample of Example 12, except that the crystalline silicon substrate was changed from an n-type crystalline silicon substrate to a p-type crystalline silicon substrate. The fabrication method for the sample of Example 22 was based on the fabrication method for the sample of Example 12, except that the n-type crystalline silicon substrate was changed to a p-type crystalline silicon substrate. A sample of Example 23 was fabricated based on the sample of Example 13, except that the crystalline silicon substrate was changed from an n-type crystalline silicon substrate to a p-type crystalline silicon substrate. The sample of Example 23 was fabricated based on the method for fabricating the sample of Example 13, except that the n-type crystalline silicon substrate was replaced with a p-type crystalline silicon substrate. The sample of Example 24 was fabricated based on the sample of Example 14, except that the crystalline silicon substrate was replaced with a p-type crystalline silicon substrate. The sample of Example 24 was fabricated based on the method for fabricating the sample of Example 14, except that the n-type crystalline silicon substrate was replaced with a p-type crystalline silicon substrate. The sample of Example 25 was fabricated based on the sample of Example 15, except that the crystalline silicon substrate was replaced with a p-type crystalline silicon substrate. The sample of Example 25 was fabricated based on the method for fabricating the sample of Example 15, except that the n-type crystalline silicon substrate was replaced with a p-type crystalline silicon substrate. Here, a single-crystal silicon substrate doped with boron as a p-type dopant (p-type single-crystal silicon substrate) was used as the p-type crystalline silicon substrate.

[0097] 3-2. Occurrence of Defects in Each Sample of Specific Examples and Reference Examples The surfaces of the n-type polysilicon layers of each of the samples of Specific Example 1, Specific Example 2, Specific Example 3, Specific Example 4, Specific Example 5, Specific Example 6, Specific Example 7, Specific Example 8, Reference Example 1, Reference Example 2, Reference Example 4, Reference Example 6, Specific Example 11, Specific Example 12, Specific Example 13, Specific Example 14, Specific Example 15, and Reference Example 13 were observed using an optical microscope. More specifically, the presence of blisters at the interface between the silicon oxide film and the n-type polysilicon layer, as well as the presence of local defects in the n-type polysilicon layer, were confirmed. Here, if a circular bulge was present on the surface of the n-type polysilicon layer in a planar view in a portion of the n-type polysilicon layer where no local defects had occurred, it was deemed that blisters were present.

[0098]

[0099] As shown in Table 1, the presence of numerous localized defects in the n-type polysilicon layer was confirmed in all of the samples of Reference Example 1, Reference Example 2, Reference Example 4, and Reference Example 6. Fig. 16 is a diagram showing an example of an image capturing the surface of the n-type polysilicon layer in the sample of Reference Example 6.

[0100] In contrast, as shown in Table 1, neither local defects nor blisters were observed in the n-type polysilicon layer in any of the samples of Specific Examples 1 to 8. Fig. 17 is a diagram showing an example of an image capturing the surface of the n-type polysilicon layer in the sample of Specific Example 6.

[0101]

[0102] As shown in Table 2, the presence of numerous localized defects and blisters in the n-type polysilicon layer was confirmed in the sample of Reference Example 13. Fig. 18 is a diagram showing an example of an image capturing the surface of the n-type polysilicon layer in the sample of Reference Example 13. In Fig. 18, the circular black areas correspond to localized defects in the n-type polysilicon layer.

[0103] In contrast, as shown in Table 2, neither the presence of local defects nor the presence of blisters in the n-type polysilicon layer was confirmed in any of the samples of Specific Examples 11 to 15. Fig. 19 is a diagram showing an example of an image capturing the surface of the n-type polysilicon layer in the sample of Specific Example 13. As shown in Fig. 19, although the presence of a textured structure was confirmed in the sample of Specific Example 13, neither the presence of local defects nor the presence of blisters in the n-type polysilicon layer was confirmed.

[0104] Therefore, it was estimated that the occurrence of blisters and the occurrence of local defects in the n-type polysilicon layer due to blisters can be reduced by forming an intrinsic crystalline silicon layer on a silicon oxide film, and then forming an n-type amorphous silicon layer on the intrinsic crystalline silicon layer, and then generating an n-type polysilicon layer from the intrinsic crystalline silicon layer and the n-type amorphous silicon layer by heat treatment.

[0105] In other words, it is estimated that, according to the manufacturing method of the solar cell element 1 according to the first embodiment, by performing the following steps 1 to 4, it is possible to reduce the occurrence of blisters and local defects caused by blisters when forming the n-type polysilicon layer 4 as a doped polysilicon layer. In other words, it is estimated that defects can be reduced in the solar cell element 1 having an example of a TOPCon structure, which is a type of POLO structure, formed using the n-type amorphous silicon layer 4b as a doped amorphous silicon layer. From another perspective, it is estimated that defects in the solar cell element 1 can be easily reduced.

[0106] [Step 1] A silicon oxide film 3 is formed as an oxide film in contact with a first semiconductor region 21 located inside a silicon substrate 2 serving as a crystalline silicon substrate including an n-type first semiconductor region 21 serving as a first region, which is a region of a semiconductor of a first conductivity type, along the surface of the silicon substrate 2 or on the surface of the silicon substrate 2.

[0107] [Step 2] On the silicon oxide film 3, an intrinsic crystalline silicon layer 4a is formed as a first layer of intrinsic crystalline silicon.

[0108] [Step 3] An n-type amorphous silicon layer 4b is formed on the intrinsic crystalline silicon layer 4a as a second layer of amorphous silicon having a thickness greater than that of the intrinsic crystalline silicon layer 4a and containing phosphorus as an n-type dopant of the first conductivity type. The n-type amorphous silicon layer 4b may be formed using, for example, a PECVD method.

[0109] [Step 4] A heat treatment is carried out to promote crystallization of the amorphous silicon of the n-type amorphous silicon layer 4b while diffusing phosphorus as an n-type dopant contained in the n-type amorphous silicon layer 4b toward the intrinsic crystalline silicon layer 4a and the silicon oxide film 3. As a result, an n-type polysilicon layer 4 is produced from the intrinsic crystalline silicon layer 4a and the n-type amorphous silicon layer 4b as a polysilicon layer located on the silicon oxide film 3 and containing phosphorus as an n-type dopant.

[0110] The above step 1 is an example of the first step of the present disclosure. The above step 2 is an example of the second step of the present disclosure. The above step 3 is an example of the third step of the present disclosure. The above step 4 is an example of the fourth step of the present disclosure.

[0111] Incidentally, the solar cell element 1 manufactured by the manufacturing method of the solar cell element 1 of the first embodiment in which the above steps 1 to 4 are executed can be said to be an element having either of the following configurations 5 and 6.

[0112] [Configuration 5] The solar cell element 1 includes a silicon substrate 2, a silicon oxide film 3, and an n-type polysilicon layer 4. The silicon substrate 2 has a first semiconductor region 21 as a first region, which is a region of an n-type semiconductor having a first conductivity type. The silicon oxide film 3 is an oxide film in contact with the first semiconductor region 21. The n-type polysilicon layer 4 is in contact with the surface of the silicon oxide film 3 opposite the first semiconductor region 21 and is an n-type polysilicon layer containing phosphorus as an n-type dopant. The n-type polysilicon layer 4 is formed by performing a heat treatment on an intrinsic crystalline silicon layer 4a as a first layer of intrinsic crystalline silicon located on the silicon oxide film 3, and an n-type amorphous silicon layer 4b as a second layer of amorphous silicon located on the intrinsic crystalline silicon layer 4a, having a thickness greater than that of the intrinsic crystalline silicon layer 4a, and containing phosphorus as an n-type dopant. This heat treatment is a process for diffusing phosphorus as an n-type dopant contained in the n-type amorphous silicon layer 4 b toward the intrinsic crystalline silicon layer 4 a and the silicon oxide film 3, thereby promoting the crystallization of the amorphous silicon in the n-type amorphous silicon layer 4 b.

[0113] [Configuration 6] The solar cell element 1 includes a silicon substrate 2 and an n-type polysilicon layer 4. The silicon substrate 2 has a first semiconductor region 21 as a first region, which is a region of an n-type semiconductor as a first conductivity type. The n-type polysilicon layer 4 is in contact with the silicon substrate 2 and is an n-type polysilicon layer containing phosphorus as an n-type dopant. The silicon substrate 2 includes a silicon oxide film 3. The silicon oxide film 3 is an oxide film located between the first semiconductor region 21 and the n-type polysilicon layer 4 and in contact with both the first semiconductor region 21 and the n-type polysilicon layer 4. The n-type polysilicon layer 4 is a layer produced from the intrinsic crystalline silicon layer 4a and the n-type amorphous silicon layer 4b by performing a heat treatment on the intrinsic crystalline silicon layer 4a, which is a first layer of intrinsic crystalline silicon located on the silicon oxide film 3, and the n-type amorphous silicon layer 4b, which is a second layer of amorphous silicon located on the intrinsic crystalline silicon layer 4a, has a thickness greater than that of the intrinsic crystalline silicon layer 4a, and contains phosphorus as an n-type dopant. This heat treatment is a process that diffuses phosphorus, which is an n-type dopant contained in the n-type amorphous silicon layer 4b, toward the intrinsic crystalline silicon layer 4a and the silicon oxide film 3, thereby promoting crystallization of the amorphous silicon of the n-type amorphous silicon layer 4b.

[0114] For this reason, it was understood that the solar cell element 1 having either of the above-mentioned configurations 5 and 6 has a configuration suitable for a method for manufacturing the solar cell element 1 that can reduce the occurrence of blisters and local defects caused by blisters when the n-type polysilicon layer 4 as the doped polysilicon layer is formed. In other words, it was understood that the solar cell element 1 having either of the above-mentioned configurations 5 and 6 has a configuration suitable for a method for manufacturing the solar cell element 1 that can reduce the occurrence of blisters and local defects caused by blisters when the n-type polysilicon layer 4 as the doped polysilicon layer is formed by performing film formation of the n-type amorphous silicon layer 4b as the doped amorphous silicon layer and heat treatment for crystallization of this n-type amorphous silicon layer 4b. In other words, it was understood that the solar cell element 1 having either of the above-mentioned configurations 5 and 6 has a configuration suitable for a method for manufacturing the solar cell element 1 that can reduce defects in the solar cell element 1 having an example of a TOPCon structure, which is a type of POLO structure, formed using a doped amorphous silicon layer. Therefore, it has been understood that defects can be reduced in the solar cell element 1 having an example of a TOPCon structure, which is a type of POLO structure formed using a doped amorphous silicon layer, by employing the solar cell element 1 having either of the above-described configurations 5 and 6. From another perspective, it has been understood that defects in the solar cell element 1 can be easily reduced.

[0115] 3-3. Distribution of Dopant Concentration in Each Sample of Specific Examples and Reference Examples The distribution of the concentration of phosphorus as an n-type dopant in a first direction was measured using SIMS for each of the samples of Specific Example 2, Specific Example 3, Specific Example 4, Specific Example 5, Specific Example 6, Reference Example 2, Reference Example 4, and Reference Example 6. Here, the first direction is a direction from the surface of the n-type polysilicon layer opposite the substrate toward the substrate. This first direction may be a direction along the thickness directions of the n-type polysilicon layer, the silicon oxide film, and the substrate. This first direction may be a direction from the n-type polysilicon layer toward the substrate via the silicon oxide film. For each of the samples of Reference Examples 2, 4, and 6, the distribution of the concentration of phosphorus in the first direction was measured using SIMS, while avoiding blisters and local defects due to blisters in the n-type polysilicon layer.

[0116] 3-3-1. Comparison Between Sample of Specific Example 4 and Sample of Reference Example 4> FIG. 20 is a graph showing an example of measurement results of the distribution of phosphorus concentration in a portion of the first direction obtained by using SIMS for each of the samples of Specific Example 4 and Reference Example 4. The graph of FIG. 20 shows the distribution of the concentration of phosphorus as an n-type dopant in the first direction for the region of the n-type polysilicon layer from the silicon oxide film side region through the silicon oxide film to the semiconductor region of the substrate for each of the samples of Specific Example 4 and Reference Example 4. From another perspective, the graph of FIG. 20 shows the distribution of the concentration of phosphorus as an n-type dopant in the first direction for the region corresponding to portion II shown in FIG. 2 for each of the samples of Specific Example 4 and Reference Example 4. In the graph of FIG. 20, the horizontal axis represents position in the first direction, and the vertical axis represents the phosphorus concentration. In the graph of FIG. 20 , for each sample of Specific Example 4 and Reference Example 4, the position in the first direction showing the maximum peak (also referred to as the first peak) in the distribution of phosphorus concentration in the first direction is set to zero (0), which is the reference position on the horizontal axis. In the present disclosure, the position in the first direction showing the maximum peak (first peak) in the distribution of phosphorus concentration in the first direction corresponds to the position where the phosphorus concentration is maximum in the distribution of phosphorus concentration in the first direction. On the horizontal axis of the graph of FIG. 20 , the direction from the n-type polysilicon layer toward the substrate is set to the positive direction, and the direction from the substrate toward the n-type polysilicon layer is set to the negative direction. In other words, the first direction, which is the direction from the surface of the n-type polysilicon layer opposite the substrate toward the substrate, is set to the positive direction. The graph of FIG. 20 is a semi-logarithmic graph with a common logarithmic scale on the vertical axis.

[0117] In the graph of FIG. 20 , the distribution of the phosphorus concentration in the first direction for the sample of Specific Example 4 is shown by a curve (strictly speaking, a broken line) Le4 drawn with a thick solid line, and the distribution of the phosphorus concentration in the first direction for the sample of Reference Example 4 is shown by a curve (strictly speaking, a broken line) Lr4 drawn with a thick dashed line.

[0118] For each sample of Specific Example 4 and Reference Example 4, the maximum peak (first peak) in the distribution of phosphorus concentration in the first direction was estimated to be located near the interface between the silicon oxide film and the n-type polysilicon layer by measuring the distribution of oxygen concentration in the first direction using SIMS. For each sample of Specific Example 4 and Reference Example 4, the maximum peak (first peak) in the distribution of phosphorus concentration in the first direction was estimated to be caused by phosphorus segregation near the interface between the silicon oxide film and the n-type polysilicon layer. More specifically, it was estimated that the maximum peak (first peak) in the distribution of phosphorus concentration in the first direction was caused by phosphorus diffusing from the P-doped amorphous silicon layer toward the substrate during the heat treatment that promotes crystallization of the P-doped amorphous silicon layer, resulting in the segregation of a large amount of phosphorus near the interface between the silicon oxide film and the n-type polysilicon layer. Here, it was considered that the vicinity of the interface between the silicon oxide film and the n-type polysilicon layer could include a range within ±1 nm in the first direction based on the interface between the silicon oxide film and the n-type polysilicon layer.

[0119] As shown in the graph of FIG. 20 , it was confirmed that there was a clear difference between the distribution of the phosphorus concentration in the first direction for the sample of Specific Example 4 and the distribution of the phosphorus concentration in the first direction for the sample of Reference Example 4 in the region of the n-type polysilicon layer on the silicon oxide film side.

[0120] As shown in the graph of FIG. 20 , in the distribution of the phosphorus concentration in the first direction for the sample of Reference Example 4, it was confirmed that the phosphorus concentration gradually decreased as it approached zero (0), which is the reference position on the horizontal axis, in the range from −25 nm to approximately −2.5 nm on the horizontal axis.

[0121] On the other hand, as shown in the graph of FIG. 20 , in the distribution of the phosphorus concentration in the first direction for the sample of Specific Example 4, it was confirmed that the phosphorus concentration was almost constant in the range from approximately −25 nm to approximately −6.5 nm on the horizontal axis, whereas the phosphorus concentration clearly increased in the range from approximately −6.5 nm to approximately −2.5 nm on the horizontal axis (also referred to as the first range).

[0122] It was presumed that the portion of the sample of Example 4 corresponding to the first range on the horizontal axis was contained in a portion of the n-type polysilicon layer of the sample of Example 4 that was formed by transformation from an intrinsic crystalline silicon layer due to heat treatment. Here, it was presumed that the increase in the phosphorus concentration in the first range occurred because, when the n-type polysilicon layer of the sample of Example 4 was formed by heat treatment, the solid solubility of phosphorus in the intrinsic crystalline silicon layer formed on the silicon oxide film was higher than the solid solubility of phosphorus in the n-type amorphous silicon layer formed on the intrinsic crystalline silicon layer. More specifically, it was presumed that the increase in the phosphorus concentration in the first range occurred because, during the heat treatment that promotes crystallization of the P-doped amorphous silicon layer, much of the phosphorus that diffused from the P-doped amorphous silicon layer toward the silicon oxide film via the intrinsic crystalline silicon layer was solid-solved in the intrinsic crystalline silicon layer.

[0123] 20, a portion where the phosphorus concentration appears to be elevated was observed between approximately −2.5 nm and −1 nm on the horizontal axis in the distribution of the phosphorus concentration in the first direction for both the samples of Specific Example 4 and Reference Example 4. It was presumed that this portion was caused by charging in the silicon oxide film during measurement using SIMS.

[0124] 3-3-2. Characteristics of the Phosphorus Concentration Distribution in the Sample of Specific Example 4> Each of FIGS. 21 and 22 is a graph illustrating the characteristics of the phosphorus concentration distribution in a portion of the first direction obtained by using SIMS on the sample of Specific Example 4. The graph of FIG. 21 is a graph obtained by deleting the thick dashed curve Lr4, which indicates the phosphorus concentration distribution in the first direction for the sample of Reference Example 4, from the graph of FIG. 20 . FIG. 22 shows a graph for recognizing the characteristics of the phosphorus concentration distribution in the first direction for the sample of Specific Example 4, taking noise components into consideration. In the graph of FIG. 22 , as in the graphs of FIGS. 20 and 21 , the horizontal axis indicates the position in the first direction, and the vertical axis indicates the phosphorus concentration. In the graph of FIG. 22 , as in the graph of FIG. 21 , the position in the first direction showing the maximum peak (first peak) of the phosphorus concentration distribution in the first direction for the sample of Specific Example 4 is set as zero (0), which is the reference position of the horizontal axis. 20 and 21, the horizontal axis of the graph in Fig. 22 is positive in the direction from the n-type polysilicon layer toward the substrate, and negative in the direction from the substrate toward the n-type polysilicon layer. In other words, the first direction, which is the direction from the surface of the n-type polysilicon layer opposite the substrate toward the substrate, is positive. The graph in Fig. 22 is a graph (also called a linear graph) with a normal scale for phosphorus concentration on the vertical axis at the left end. In Fig. 22, the distribution of phosphorus concentration in a portion of the first direction for the sample of Specific Example 4 is shown by a thick solid curve (strictly speaking, a broken line) Le4.

[0125] For various samples of the solar cell element of the present disclosure, when characteristics of the distribution of the concentration of a specific n-type dopant in a direction (first direction) from the surface of the n-type polysilicon layer opposite the substrate toward the substrate were recognized, minute increases and decreases in the distribution of the concentration of the specific n-type dopant in the first direction that occurred during SIMS measurement were treated as noise components that did not exhibit characteristics corresponding to actual changes in the concentration of the specific n-type dopant. Here, the specific n-type dopant may refer to a specific type of element among n-type dopants. For example, phosphorus is used as this specific type of element.

[0126] Here, an example of a method (also referred to as a first recognition method) for recognizing characteristics of the concentration distribution of a specific n-type dopant (e.g., phosphorus) in a first direction of a sample, taking noise components into consideration, will be described. In the first recognition method, the following four processes are performed in the listed order: [1] calculation of an index related to the noise components; [2] calculation of an approximation line; [3] calculation of a judgment line; and [4] peak recognition, thereby recognizing characteristics of the concentration distribution of a specific n-type dopant (e.g., phosphorus) in a first direction of a sample. In the present disclosure, this example of the first recognition method is adopted when recognizing characteristics of the concentration distribution of a specific n-type dopant in a first direction for various samples.

[0127] SIMS can determine the types of elements constituting the surface of a sample and the concentration of each element by analyzing the mass of secondary ions emitted from the surface of the sample when the surface is irradiated with primary ions. Furthermore, SIMS can analyze the sample in the depth direction because the surface of the sample is gradually eroded by the irradiation of primary ions. Therefore, SIMS can obtain data on the distribution of the concentration of a specific n-type dopant (e.g., phosphorus) in a sample in the first direction by measuring the concentration of the specific n-type dopant in the sample in the first direction. More specifically, SIMS can obtain data on the distribution of the concentration of the specific n-type dopant in a sample in the first direction by sequentially measuring the concentration of the specific n-type dopant at multiple discrete positions in the first direction of the sample. These discrete positions are positions (also referred to as measurement positions) arranged sequentially in the first direction of the sample, from 1 to M (M is a natural number), at which the concentration of the specific n-type dopant is measured. Therefore, the discrete positions are the first measured position, the second measured position, the third measured position, ..., the Mth measured position, which are arranged in order in the first direction on one sample. Therefore, the concentration of a specific n-type dopant measured in order at the first to Mth measured positions on one sample in the first direction using SIMS is the concentration of the specific n-type dopant measured in order from the first to Mth positions on one sample. In other words, data obtained using SIMS that indicates the distribution of the concentration of a specific n-type dopant on one sample in the first direction is made up of data on the concentration of the specific n-type dopant measured in order from the first to Mth positions on one sample in the first direction. Therefore, in the following description, regarding the distribution of the concentration of a specific n-type dopant in a first direction of one sample, of the M concentrations of specific n-type dopants measured in order from the first to the Mth in the first direction of one sample, the concentration of the specific n-type dopant measured at the nth position (n is an integer) and the concentration of the specific n-type dopant measured at the n+1th position are considered to be the concentrations of two specific n-type dopants adjacent to each other in the first direction.

[0128] <<[1] Calculation of an Index Related to a Noise Component>> First, for a distribution of the concentration of a specific n-type dopant in a first direction of a sample, a distribution of the absolute value of the difference between the concentrations of two adjacent specific n-type dopants in the first direction (also referred to as a Δn-type dopant concentration) is calculated. Here, if the specific n-type dopant is phosphorus, the Δn-type dopant concentration is the absolute value of the difference between the concentrations of two adjacent phosphorus in the first direction in the distribution of the phosphorus concentration in the first direction of the sample (also referred to as a Δphosphorus concentration). Here, for the concentration of the specific n-type dopant measured at an n-th point (n is an integer) in the distribution of the concentration of the specific n-type dopant in the first direction of the sample, ΔD1(n) is calculated using Equation (1).

[0129] ΔD1(n)=|D1(n+1)−D1(n)|...(1).

[0130] In Equation (1), D1(n) denotes the concentration of the specific n-type dopant measured at the nth measurement in the distribution of the concentration of the specific n-type dopant in the first direction of the sample. D1(n+1) denotes the concentration of the specific n-type dopant measured at the n+1th measurement in the distribution of the concentration of the specific n-type dopant in the first direction of the sample. In other words, for the distribution of the concentration of the specific n-type dopant in the first direction of the sample, the absolute value of the difference between the concentration of the specific n-type dopant measured at the n+1th measurement and the concentration of the specific n-type dopant measured at the nth measurement is calculated as the Δn-type dopant concentration related to the concentration of the specific n-type dopant measured at the nth measurement.

[0131] Here, when the specific n-type dopant is phosphorus, ΔP(n) as the Δphosphorus concentration is calculated by the formula (2).

[0132] ΔP(n)=|P(n+1)−P(n)|...(2).

[0133] In equation (2), P(n) denotes the nth phosphorus concentration measured in the phosphorus concentration distribution in the first direction of the sample. P(n+1) denotes the n+1th phosphorus concentration measured in the phosphorus concentration distribution in the first direction of the sample. In other words, the absolute value of the difference between the n+1th phosphorus concentration measured and the nth phosphorus concentration measured in the phosphorus concentration distribution in the first direction of the sample is calculated as the Δ phosphorus concentration related to the nth phosphorus concentration measured.

[0134] In the distribution of the Δn-type dopant concentration (e.g., Δphosphorus concentration) in the first direction of the sample, a portion where the Δn-type dopant concentration undulates finely near zero (0) is presumed to indicate a variation in measurement values ​​corresponding to noise components in the distribution of the concentration of a specific n-type dopant (e.g., phosphorus) in the first direction of the sample. Therefore, for the sample, a base region (also referred to as a base region) is set in a portion of the first direction from the silicon oxide film side region of the n-type polysilicon layer through the silicon oxide film to the semiconductor region of the substrate, where the Δn-type dopant concentration undulates finely near zero (0). In this case, in the direction away from the silicon substrate, which is the opposite direction to the first direction, a region from a first distance to a second distance is set as the base region, with the maximum peak (first peak) serving as a reference. The first distance may be set to, for example, 8 nm to 10 nm. The second distance may be set to, for example, 15 nm to 25 nm. The second distance may be set according to, for example, the thickness of the n-type polysilicon layer. For example, the second distance may be set to half the thickness of the n-type polysilicon layer or less. For example, if the thickness of the n-type polysilicon layer is 60 nm, the second distance may be set to 30 nm or less. For example, if the thickness of the n-type polysilicon layer is 30 nm, the second distance may be set to 15 nm or less. In the present disclosure, when characteristics of the distribution of the concentration of a specific n-type dopant in the first direction are recognized for each of various samples, as an example, the first distance is set to 10 nm and the second distance is set to 25 nm. Then, among the distribution of the Δn-type dopant concentration in the first direction of the sample, the standard deviation σ of the Δn-type dopant concentration in the base region is calculated as an index (also referred to as a first index) related to the noise component of the distribution of the concentration of a specific n-type dopant (e.g., phosphorus) in the first direction of the sample.

[0135] <<[2] Calculation of Approximation Line>> A line of a function (also referred to as an approximation function) approximating the concentration distribution of a specific n-type dopant (e.g., phosphorus) in the base region in a first direction of the sample is calculated. Here, the line of the approximation function is calculated as a line (also referred to as an approximation line) that is extended in the first direction of the sample so as to exist not only in the base region but also in regions other than the base region. Here, an example of the region other than the base region may be a region from the base region in the first direction of the sample to the position showing the first peak. An example of the region including the base region and regions other than the base region in the first direction of the sample may be, for example, a region from a region of the n-type polysilicon layer on the silicon oxide film side in the first direction, through the silicon oxide film, to a semiconductor region of the substrate. An example of the approximation function line may be a straight line of a linear function calculated by the least squares method. In this case, the approximation line is a straight line of a linear function. An example of the approximation function line may be a curved line of a quadratic function calculated by the least squares method. In this case, the approximation line is a curved line of a quadratic function.

[0136] <<[3] Calculation of the judgment line>> The approximation line that approximates the distribution of the concentration of a specific n-type dopant (e.g., phosphorus) in the base region in the first direction of the sample is used as a reference, and a value m times the standard deviation σ (m is a value between 3 and 4) is added as a first index to each concentration of the specific n-type dopant on the approximation line to calculate a line (also referred to as a judgment line) obtained by shifting the approximation line. Here, if the approximation line is a straight line of a linear function, the judgment line will also be a straight line of a linear function. For example, if the approximation line is a curved line of a quadratic function, the judgment line will also be a curved line of a quadratic function.

[0137] <<[4] Peak Recognition>> In the distribution of the concentration of a specific n-type dopant (e.g., phosphorus) in the first direction of the sample, in a region extending from the silicon oxide film side of the n-type polysilicon layer through the silicon oxide film to the semiconductor region of the substrate, a significant peak of the concentration of the specific n-type dopant is recognized in a portion where the concentration of the specific n-type dopant exceeds the judgment line in three or more consecutive data points in the first direction. Here, instead of the portion where the concentration of the specific n-type dopant exceeds the judgment line in three or more consecutive data points in the first direction, a significant peak of the concentration of the specific n-type dopant may be recognized in a portion where the concentration of the specific n-type dopant continues to exceed the judgment line over a range of at least a predetermined length in the first direction. The predetermined length may be set to, for example, 1 nm, 1.5 nm, or 2 nm.

[0138] In the graph of FIG. 22 , the distribution of the absolute value of the difference (Δ phosphorus concentration) between two adjacent phosphorus concentrations in the first direction for the phosphorus concentration distribution in the first direction for the sample of Specific Example 4 is shown by a curve (strictly speaking, a broken line) Le41 drawn with a thin solid line. In the graph of FIG. 22 , a normal scale for the Δ phosphorus concentration is marked on the vertical axis at the right end. The graph of FIG. 22 shows an example in which the region from −10 nm to −25 nm on the horizontal axis is set to the base region Ab0. In the graph of FIG. 22 , a straight line Le42 of a linear function is shown as a thin dashed line, which is an example of an approximation line that approximates the phosphorus concentration distribution in the first direction for the sample of Specific Example 4 in the base region Ab0. In the graph of FIG. 22 , a straight line Le43 of a linear function is shown as a thin dashed line, which is an example of a judgment line for the phosphorus concentration for the sample of Specific Example 4. The graph in FIG. 22 shows a straight line Le43 of a linear function as an example of a judgment line relating to the phosphorus concentration when m times is set to three times.

[0139] 21 and 22 , it was confirmed that the distribution of phosphorus concentration in the first direction in the region extending from the silicon oxide film side region of the n-type polysilicon layer through the silicon oxide film to the semiconductor region of the substrate had a maximum peak (first peak) Pk1 and a second peak Pk2. The second peak Pk2 was located at a position 3 nm or more away from the position of the first peak Pk1 in the direction extending from the semiconductor region of the substrate through the silicon oxide film toward the silicon oxide film side region of the n-type polysilicon layer. This characteristic of the distribution of phosphorus concentration in the first direction having the first peak Pk1 and the second peak Pk2 was confirmed at multiple locations in the sample of Example 4, and was also confirmed at multiple locations in another sample obtained by the same fabrication method as the sample of Example 4.

[0140] More specifically, the second peak Pk2 was located at a position about 3.5 nm away from the position of the first peak Pk1 in the direction from the semiconductor region of the substrate through the silicon oxide film toward the silicon oxide film side region of the n-type polysilicon layer. Note that in the graphs of Figures 21 and 22, in the distribution of phosphorus concentration in the first direction, the second peak Pk2 was the peak that first appeared when moving further in the negative direction from -3 nm on the horizontal axis.

[0141] Fig. 23 is a graph for explaining the characteristics of the distribution of phosphorus concentration in a part of the first direction obtained by using SIMS for the sample of Reference Example 4. The graph of Fig. 23 is a graph (linear graph) with a normal scale for phosphorus concentration on the vertical axis at the left end. In Fig. 23, a part of the distribution of phosphorus concentration in the first direction for the sample of Reference Example 4 is shown by a curve (strictly speaking, a broken line) Lr4 drawn with a thick dashed line.

[0142] In the graph of FIG. 23 , the distribution of the absolute value of the difference (Δ phosphorus concentration) between two adjacent phosphorus concentrations in the first direction for the phosphorus concentration distribution in the first direction for the sample of Reference Example 4 is shown by a curve (strictly speaking, a broken line) Lr41 drawn with a thin solid line. In the graph of FIG. 23 , the vertical axis at the right end is marked with a normal scale for the Δ phosphorus concentration. The graph of FIG. 23 shows an example in which the region from −10 nm to −25 nm on the horizontal axis is set to the base region Ab0. In the graph of FIG. 23 , a straight line Lr42 of a linear function is shown as a thin dashed line, which is an example of an approximation line approximating the phosphorus concentration distribution in the first direction for the sample of Reference Example 4 in the base region Ab0. In the graph of FIG. 23 , a straight line Lr43 of a linear function is shown as a thin dashed line, which is an example of a judgment line for the phosphorus concentration for the sample of Reference Example 4. The graph in FIG. 23 shows a straight line Lr43 of a linear function as an example of a judgment line relating to the phosphorus concentration when m times is set to three times.

[0143] 23 , it was confirmed that, for the sample of Reference Example 4, in the region from the silicon oxide film side region of the n-type polysilicon layer through the silicon oxide film to the semiconductor region of the substrate, the distribution of the phosphorus concentration in the first direction does not have a peak corresponding to the second peak Pk2 of the sample of Specific Example 4. The fact that the distribution of the phosphorus concentration in the first direction does not have a peak corresponding to the second peak Pk2 was confirmed at multiple locations in the sample of Reference Example 4, and was also confirmed at multiple locations in another sample obtained by the same fabrication method as the sample of Reference Example 4.

[0144] 3-3-3. Comparison Between Sample of Specific Example 6 and Sample of Reference Example 6> FIG. 24 is a graph showing an example of measurement results of the distribution of phosphorus concentration in a portion of the first direction obtained by using SIMS for each of the samples of Specific Example 6 and Reference Example 6. The graph of FIG. 24 shows the distribution of the concentration of phosphorus as an n-type dopant in the first direction for the region of the n-type polysilicon layer from the silicon oxide film side region through the silicon oxide film to the semiconductor region of the substrate for each of the samples of Specific Example 6 and Reference Example 6. From another perspective, the graph of FIG. 24 shows the distribution of the concentration of phosphorus as an n-type dopant in the first direction for the region corresponding to part II shown in FIG. 2 for each of the samples of Specific Example 6 and Reference Example 6. In the graph of FIG. 24, as with the graph of FIG. 20, the horizontal axis indicates position in the first direction, and the vertical axis indicates phosphorus concentration. In the graph of Figure 24, for each sample of Specific Example 6 and Reference Example 6, the position in the first direction showing the maximum peak (first peak) in the distribution of phosphorus concentration in the first direction is set to zero (0), which is the reference position of the horizontal axis. Similarly to the graph of Figure 20, the horizontal axis of the graph of Figure 24 has the positive direction from the n-type polysilicon layer toward the substrate, and the negative direction from the substrate toward the n-type polysilicon layer. In other words, the positive direction is the first direction, which is the direction from the surface of the n-type polysilicon layer opposite the substrate toward the substrate. Similarly to the graph of Figure 20, the graph of Figure 24 is a semi-logarithmic graph with a common logarithmic scale on the vertical axis.

[0145] In the graph of FIG. 24 , the distribution of the phosphorus concentration in the first direction for the sample of Specific Example 6 is shown by a curve (strictly speaking, a broken line) Le6 drawn with a thick solid line, and the distribution of the phosphorus concentration in the first direction for the sample of Reference Example 6 is shown by a curve (strictly speaking, a broken line) Lr6 drawn with a thick dashed line.

[0146] It should be noted that, for each of the samples of Specific Example 6 and Reference Example 6, the maximum peak (first peak) in the distribution of phosphorus concentration in the first direction was estimated to be located near the interface between the silicon oxide film and the n-type polysilicon layer by measuring the distribution of oxygen concentration in the first direction by SIMS. For each of the samples of Specific Example 6 and Reference Example 6, the maximum peak (first peak) in the distribution of phosphorus concentration in the first direction was estimated to be caused by phosphorus segregation near the interface between the silicon oxide film and the n-type polysilicon layer, as with each of the samples of Specific Example 4 and Reference Example 4 described above.

[0147] As shown in the graph of FIG. 24 , similar to the graph of FIG. 20 , it was confirmed that there was a clear difference between the distribution of the phosphorus concentration in the first direction for the sample of Specific Example 6 and the distribution of the phosphorus concentration in the first direction for the sample of Reference Example 6 in the region of the n-type polysilicon layer on the silicon oxide film side.

[0148] As shown in the graph of FIG. 24 , in the distribution of the phosphorus concentration in the first direction for the sample of Reference Example 6, it was confirmed that the phosphorus concentration slightly decreased as it approached zero (0), which is the reference position on the horizontal axis, in the range from −25 nm to approximately −3 nm on the horizontal axis.

[0149] On the other hand, as shown in the graph of FIG. 24 , in the distribution of the phosphorus concentration in the first direction for the sample of Specific Example 6, it was confirmed that the phosphorus concentration was almost constant in the range from approximately −25 nm to approximately −7.5 nm on the horizontal axis, whereas the phosphorus concentration increased in the range from approximately −7.5 nm to approximately −3 nm on the horizontal axis (also referred to as the second range).

[0150] It was presumed that the portion of the sample of Specific Example 6 corresponding to the second range on the horizontal axis was contained in a portion of the n-type polysilicon layer of the sample of Specific Example 6 that was formed by transformation of the intrinsic crystalline silicon layer by heat treatment. Here, it was presumed that the increase in the phosphorus concentration in the second range for the sample of Specific Example 6 occurred because, as with the sample of Specific Example 4 described above, when the n-type polysilicon layer of the sample of Specific Example 6 was formed by heat treatment, the solid solubility of phosphorus in the intrinsic crystalline silicon layer formed on the silicon oxide film was higher than the solid solubility of phosphorus in the n-type amorphous silicon layer formed on the intrinsic crystalline silicon layer.

[0151] 24, a portion where the phosphorus concentration appears to be elevated was observed between approximately −3 nm and approximately −1.5 nm on the horizontal axis in the distribution of the phosphorus concentration in the first direction for both the samples of Specific Example 6 and Reference Example 6. It was presumed that this portion was caused by charging in the silicon oxide film during measurement using SIMS.

[0152] The increase in the phosphorus concentration in the first range for the sample of Specific Example 4 was larger than the increase in the phosphorus concentration in the second range for the sample of Specific Example 6. It was presumed that this difference was caused by the fact that the heat treatment temperature T1 of 750°C in the preparation of the sample of Specific Example 4 was lower than the heat treatment temperature T1 of 850°C in the preparation of the sample of Specific Example 6. More specifically, in the sample of Specific Example 4, the region of the n-type polysilicon layer resulting from transformation from the intrinsic crystalline silicon layer had undergone more advanced crystallization than the region resulting from transformation from the n-type amorphous silicon layer, and therefore the solid solubility of phosphorus was clearly higher, resulting in a larger increase in the phosphorus concentration in the first range.

[0153] 3-3-4. Characteristics of the Phosphorus Concentration Distribution in the Sample of Specific Example 6> Each of FIGS. 25 and 26 is a graph illustrating the characteristics of the phosphorus concentration distribution in a portion of the first direction obtained by using SIMS on the sample of Specific Example 6. The graph of FIG. 25 is a graph obtained by deleting the thick dashed curve Lr6, which indicates the phosphorus concentration distribution in the first direction for the sample of Reference Example 6, from the graph of FIG. 24 . FIG. 26 shows a graph for recognizing the characteristics of the phosphorus concentration distribution in the first direction for the sample of Specific Example 6, taking noise components into consideration. In the graph of FIG. 26 , as in the graphs of FIGS. 24 and 25 , the horizontal axis indicates the position in the first direction, and the vertical axis indicates the phosphorus concentration. In the graph of FIG. 26 , as in the graph of FIG. 25 , the position in the first direction showing the maximum peak (first peak) of the phosphorus concentration distribution in the first direction for the sample of Specific Example 6 is set as zero (0), which is the reference position of the horizontal axis. 24 and 25, the horizontal axis of the graph in Fig. 26 is positive in the direction from the n-type polysilicon layer toward the substrate, and negative in the direction from the substrate toward the n-type polysilicon layer. In other words, the first direction, which is the direction from the surface of the n-type polysilicon layer opposite the substrate toward the substrate, is positive. Like the graph in Fig. 22, the graph in Fig. 26 is a linear graph with a normal scale for phosphorus concentration on the vertical axis at the left end. In Fig. 26, a portion of the distribution of phosphorus concentration in the first direction of the sample of Specific Example 6 is indicated by a thick solid curve (strictly speaking, a broken line) Le6.

[0154] In the graph of FIG. 26 , the distribution of the absolute value of the difference (Δ phosphorus concentration) between two adjacent phosphorus concentrations in the first direction for the phosphorus concentration distribution in the first direction for the sample of Specific Example 6 is shown by a curve (strictly speaking, a broken line) Le61 drawn with a thin solid line. In the graph of FIG. 26 , as in the graph of FIG. 22 , the vertical axis at the right end is marked with a normal scale for the Δ phosphorus concentration. In the graph of FIG. 26 , as in the graph of FIG. 22 , the graph of FIG. 26 shows an example in which the region from −10 nm to −25 nm on the horizontal axis is set to the base region Ab0. In the graph of FIG. 26 , a straight line Le62 of a linear function is shown as a thin dashed line, which is an example of an approximation line approximating the phosphorus concentration distribution in the first direction for the sample of Specific Example 6 in the base region Ab0. In the graph of FIG. 26 , a straight line Le63 of a linear function is shown as a thin dashed line, which is an example of a judgment line for the phosphorus concentration for the sample of Specific Example 6. In the graph of FIG. 26, a straight line Le63 of a linear function is shown as an example of a judgment line relating to the phosphorus concentration when m times is set to three times.

[0155] 25 and 26 , it was confirmed that the distribution of phosphorus concentration in the first direction in the region extending from the silicon oxide film side region of the n-type polysilicon layer through the silicon oxide film to the semiconductor region of the substrate had a maximum peak (first peak) Pk1 and a second peak Pk2. The second peak Pk2 was located at a position 3 nm or more away from the position of the first peak Pk1 in the direction extending from the semiconductor region of the substrate through the silicon oxide film toward the silicon oxide film side region of the n-type polysilicon layer. This characteristic of the distribution of phosphorus concentration in the first direction having the first peak Pk1 and the second peak Pk2 was confirmed at multiple locations in the sample of Example 6, and was also confirmed at multiple locations in another sample obtained by the same fabrication method as the sample of Example 6.

[0156] More specifically, the second peak Pk2 was located at a position about 4.5 nm away from the position of the first peak Pk1 in the direction from the semiconductor region of the substrate through the silicon oxide film toward the silicon oxide film side region of the n-type polysilicon layer. Note that in the graphs of Figures 25 and 26, in the distribution of phosphorus concentration in the first direction, the second peak Pk2 was the peak that first appeared when moving further in the negative direction from -3 nm on the horizontal axis.

[0157] Fig. 27 is a graph for explaining the characteristics of the distribution of the phosphorus concentration in a part of the first direction obtained by using SIMS for the sample of Reference Example 6. The graph of Fig. 27 is a graph (linear graph) in which the normal scale for the phosphorus concentration is assigned to the vertical axis at the left end, similar to the graph of Fig. 23. In Fig. 27, a part of the distribution of the phosphorus concentration in the first direction for the sample of Reference Example 6 is indicated by a curve (strictly speaking, a broken line) Lr6 drawn with a thick dashed line.

[0158] In the graph of FIG. 27 , the distribution of the absolute value of the difference (Δ phosphorus concentration) between two adjacent phosphorus concentrations in the first direction for the phosphorus concentration distribution in the first direction for the sample of Reference Example 6 is shown by a curve (strictly speaking, a broken line) Lr61 drawn with a thin solid line. In the graph of FIG. 27 , as in the graph of FIG. 23 , the vertical axis at the right end is marked with a normal scale for the Δ phosphorus concentration. In the graph of FIG. 27 , as in the graph of FIG. 23 , the graph of FIG. 27 shows an example in which the region from −10 nm to −25 nm on the horizontal axis is set to the base region Ab0. In the graph of FIG. 27 , a linear function line Lr62 is shown as a thin dashed line, which is an example of an approximation line approximating the phosphorus concentration distribution in the first direction for the sample of Reference Example 6 in the base region Ab0. In the graph of FIG. 27 , a linear function line Lr63 is shown as a thin dashed line, which is an example of a judgment line for the phosphorus concentration for the sample of Reference Example 6. The graph in FIG. 27 shows a straight line Lr63 of a linear function as an example of a judgment line relating to the phosphorus concentration when m times is set to three times.

[0159] 27 , it was confirmed that, for the sample of Reference Example 6, in the region from the silicon oxide film side region of the n-type polysilicon layer through this silicon oxide film to the semiconductor region of the substrate, the distribution of the phosphorus concentration in the first direction does not have a peak corresponding to the second peak Pk2 of the sample of Specific Example 6. The fact that the distribution of the phosphorus concentration in the first direction does not have a peak corresponding to the second peak Pk2 was confirmed at multiple locations in the sample of Reference Example 6, and was also confirmed at multiple locations in another sample obtained by the same fabrication method as the sample of Reference Example 6.

[0160] 3-3-5. Comparison Between Sample of Specific Example 2 and Sample of Reference Example 2 FIG. 28 is a graph showing an example of measurement results of the distribution of phosphorus concentration in a portion of the first direction obtained by using SIMS for each of the samples of Specific Example 2 and Reference Example 2. The graph of FIG. 28 shows the distribution of the concentration of phosphorus as an n-type dopant in the first direction for the region of the n-type polysilicon layer from the silicon oxide film side region through the silicon oxide film to the semiconductor region of the substrate for each of the samples of Specific Example 2 and Reference Example 2. From another perspective, the graph of FIG. 28 shows the distribution of the concentration of phosphorus as an n-type dopant in the first direction for the region corresponding to portion II shown in FIG. 2 for each of the samples of Specific Example 2 and Reference Example 2. In the graph of FIG. 28, as in the graphs of FIGS. 20 and 24, the horizontal axis indicates position in the first direction, and the vertical axis indicates the phosphorus concentration. In the graph of Figure 28, for each sample of Specific Example 6 and Reference Example 6, the position in the first direction showing the maximum peak (first peak) in the distribution of phosphorus concentration in the first direction is set to zero (0), which is the reference position of the horizontal axis. On the horizontal axis of the graph of Figure 28, as in the graphs of Figures 20 and 24, the direction from the n-type polysilicon layer toward the substrate is set to the positive direction, and the direction from the substrate toward the n-type polysilicon layer is set to the negative direction. In other words, the first direction, which is the direction from the surface of the n-type polysilicon layer opposite the substrate toward the substrate, is set to the positive direction. As in the graphs of Figures 20 and 24, the graph of Figure 28 is a semi-logarithmic graph with a common logarithmic scale on the vertical axis.

[0161] In the graph of FIG. 28 , the distribution of the phosphorus concentration in the first direction for the sample of Specific Example 2 is shown by a curve (strictly speaking, a broken line) Le2 drawn with a thick solid line, and the distribution of the phosphorus concentration in the first direction for the sample of Reference Example 2 is shown by a curve (strictly speaking, a broken line) Lr2 drawn with a thick dashed line.

[0162] It should be noted that, for each of the samples of Specific Example 2 and Reference Example 2, the maximum peak (first peak) in the distribution of phosphorus concentration in the first direction was estimated to be located near the interface between the silicon oxide film and the n-type polysilicon layer by measuring the distribution of oxygen concentration in the first direction by SIMS. For each of the samples of Specific Example 2 and Reference Example 2, the maximum peak (first peak) in the distribution of phosphorus concentration in the first direction was estimated to be caused by phosphorus segregation near the interface between the silicon oxide film and the n-type polysilicon layer, as in each of the samples of Specific Example 4, Specific Example 6, Reference Example 4, and Reference Example 6 described above.

[0163] As shown in the graph of FIG. 28 , similarly to the graphs of FIGS. 20 and 24 , it was confirmed that there was a clear difference between the distribution of the phosphorus concentration in the first direction for the sample of Specific Example 2 and the distribution of the phosphorus concentration in the first direction for the sample of Reference Example 2 in the region on the silicon oxide film side of the n-type polysilicon layer.

[0164] As shown in the graph of FIG. 28 , in the distribution of the phosphorus concentration in the first direction for the sample of Reference Example 2, it was confirmed that the phosphorus concentration gradually decreased as it approached zero (0), which is the reference position on the horizontal axis, in the range from −25 nm to around −1.5 nm on the horizontal axis.

[0165] On the other hand, as shown in the graph of FIG. 28 , in the distribution of the phosphorus concentration in the first direction for the sample of Specific Example 2, the phosphorus concentration gradually decreases as it approaches the substrate in the range from approximately −25 nm to approximately −10 nm on the horizontal axis, whereas it was confirmed that the phosphorus concentration clearly increases in the range from approximately −10 nm to approximately −2.5 nm on the horizontal axis (also referred to as the third range).

[0166] It was presumed that the portion of the sample of Example 2 corresponding to the third range on the horizontal axis was contained in a portion of the n-type polysilicon layer of the sample of Example 2 that was formed by transformation of the intrinsic crystalline silicon layer by heat treatment. Here, it was presumed that the increase in the phosphorus concentration in the third range for the sample of Example 2 was caused by the fact that, as with the samples of Examples 4 and 6 described above, when the n-type polysilicon layer of the sample of Example 2 was formed by heat treatment, the solid solubility of phosphorus in the intrinsic crystalline silicon layer formed on the silicon oxide film was higher than the solid solubility of phosphorus in the n-type amorphous silicon layer formed on the intrinsic crystalline silicon layer.

[0167] 28, in the distribution of the phosphorus concentration in the first direction for both the samples of Specific Example 2 and Reference Example 2, a portion was observed from approximately −2.5 nm to approximately −1.5 nm on the horizontal axis where the rate of decrease in the phosphorus concentration seemed to decrease with increasing distance from the substrate. This portion was presumed to have been caused by charging of the silicon oxide film during the measurement using SIMS.

[0168] 3-3-6. Characteristics of the Phosphorus Concentration Distribution in the Sample of Specific Example 2> Each of FIGS. 29 and 30 is a graph illustrating the characteristics of the phosphorus concentration distribution in a portion of the first direction obtained by using SIMS on the sample of Specific Example 2. The graph of FIG. 29 is a graph obtained by deleting the thick dashed curve Lr2, which indicates the phosphorus concentration distribution in the first direction for the sample of Reference Example 2, from the graph of FIG. 28 . FIG. 30 shows a graph for recognizing the characteristics of the phosphorus concentration distribution in the first direction for the sample of Specific Example 2, taking noise components into consideration. In the graph of FIG. 30 , as in the graphs of FIGS. 28 and 29 , the horizontal axis indicates the position in the first direction, and the vertical axis indicates the phosphorus concentration. In the graph of FIG. 30 , as in the graph of FIG. 29 , the position in the first direction showing the maximum peak (first peak) of the phosphorus concentration distribution in the first direction for the sample of Specific Example 2 is set as zero (0), which is the reference position of the horizontal axis. 28 and 29, the horizontal axis of the graph in Fig. 30 is positive in the direction from the n-type polysilicon layer toward the substrate, and negative in the direction from the substrate toward the n-type polysilicon layer. In other words, the first direction, which is the direction from the surface of the n-type polysilicon layer opposite the substrate toward the substrate, is positive. The graph in Fig. 30, like the graphs in Fig. 22 and 26, is a linear graph with a normal scale for phosphorus concentration on the vertical axis at the left end. In Fig. 30, a portion of the distribution of phosphorus concentration in the first direction of the sample of Specific Example 2 is indicated by a thick solid curve (strictly speaking, a broken line) Le2.

[0169] In the graph of FIG. 30 , the distribution of the absolute value of the difference (Δ phosphorus concentration) between two adjacent phosphorus concentrations in the first direction for the phosphorus concentration distribution in the first direction of the sample of Specific Example 2 is shown by a curve (strictly speaking, a broken line) Le21 drawn with a thin solid line. In the graph of FIG. 30 , as in the graphs of FIGS. 22 and 26 , the vertical axis at the right end is marked with a normal scale for the Δ phosphorus concentration. In the graph of FIG. 30 , as in the graphs of FIGS. 22 and 26 , the graph of FIG. 30 illustrates an example in which the region from −10 nm to −25 nm on the horizontal axis is set to the base region Ab0. In the graph of FIG. 30 , a linear function line Le22 ​​is shown as a thin dashed line, which is an example of an approximation line approximating the phosphorus concentration distribution in the first direction of the sample of Specific Example 2 in the base region Ab0. In the graph of FIG. 30 , a linear function line Le23 is shown as a thin dashed line, which is an example of a judgment line for the phosphorus concentration for the sample of Specific Example 2. The graph in FIG. 30 shows a straight line Le23 of a linear function as an example of a judgment line relating to the phosphorus concentration when m times is set to three times.

[0170] 29 and 30 , it was confirmed that the distribution of phosphorus concentration in the first direction in the region extending from the silicon oxide film side region of the n-type polysilicon layer through the silicon oxide film to the semiconductor region of the substrate had a maximum peak (first peak) Pk1 and a second peak Pk2. The second peak Pk2 was located at a position 3 nm or more away from the position of the first peak Pk1 in the direction extending from the semiconductor region of the substrate through the silicon oxide film toward the silicon oxide film side region of the n-type polysilicon layer. This characteristic of the distribution of phosphorus concentration in the first direction having the first peak Pk1 and the second peak Pk2 was confirmed at multiple locations in the sample of Example 2, and was also confirmed at multiple locations in another sample obtained by the same fabrication method as the sample of Example 2.

[0171] More specifically, the second peak Pk2 was located at a position about 3.7 nm away from the position of the first peak Pk1 in the direction from the semiconductor region of the substrate through the silicon oxide film toward the silicon oxide film side region of the n-type polysilicon layer. Note that in the graphs of Figures 29 and 30, in the distribution of phosphorus concentration in the first direction, the second peak Pk2 was the peak that first appeared when moving further in the negative direction from -3 nm on the horizontal axis.

[0172] Fig. 31 is a graph for explaining the characteristics of the distribution of phosphorus concentration in a part of the first direction obtained by using SIMS for the sample of Reference Example 2. The graph of Fig. 31 is a graph (linear graph) in which the normal scale for phosphorus concentration is assigned to the vertical axis at the left end, similar to the graphs of Fig. 23 and Fig. 27. In Fig. 31, a part of the distribution of phosphorus concentration in the first direction for the sample of Reference Example 2 is indicated by a curve (strictly speaking, a broken line) Lr2 drawn with a thick dashed line.

[0173] In the graph of Figure 31, the distribution of the absolute value of the difference (Δ phosphorus concentration) between two adjacent phosphorus concentrations in the first direction for the phosphorus concentration distribution in the first direction of the sample of Reference Example 2 is shown by a curve (strictly speaking, a broken line) Lr21 drawn with a thin solid line. In the graph of Figure 31, as in the graphs of Figures 23 and 27, the vertical axis at the right end is marked with a normal scale for the Δ phosphorus concentration. In the graph of Figure 31, as in the graphs of Figures 23 and 27, the graph of Figure 31 shows an example in which the region from -10 nm to -25 nm on the horizontal axis is set to the base region Ab0. In the graph of Figure 31, a linear function line Lr22 is shown as a thin dashed line as an example of an approximation line approximating the phosphorus concentration distribution in the first direction of the sample of Reference Example 2 in the base region Ab0. 31, a straight line Lr23 of a linear function is shown as a thin two-dot chain line as an example of a judgment line for the phosphorus concentration for the sample of Reference Example 2. In the graph of FIG. 31, a straight line Lr23 of a linear function is shown as an example of a judgment line for the phosphorus concentration when m times is set to 3 times.

[0174] 31 , it was confirmed that, for the sample of Reference Example 2, in the region from the silicon oxide film side region of the n-type polysilicon layer through this silicon oxide film to the semiconductor region of the substrate, the distribution of the phosphorus concentration in the first direction does not have a peak corresponding to the second peak Pk2 of the sample of Specific Example 2. The fact that the distribution of the phosphorus concentration in the first direction does not have a peak corresponding to the second peak Pk2 was confirmed at multiple locations in the sample of Reference Example 2, and was also confirmed at multiple locations in another sample obtained by the same fabrication method as the sample of Reference Example 2.

[0175] 3-3-7. Characteristics of phosphorus concentration distribution in the sample of specific example 3> Fig. 32 is a graph showing an example of measurement results of the phosphorus concentration distribution in a part of the first direction obtained by using SIMS on the sample of specific example 3. Fig. 33 is a graph for explaining characteristics of the phosphorus concentration distribution in a part of the first direction obtained by using SIMS on the sample of specific example 3.

[0176] The graph in Figure 32 shows the distribution of the concentration of phosphorus as an n-type dopant in the first direction in the region of the n-type polysilicon layer of the sample of Example 3, from the silicon oxide film side region through the silicon oxide film to the semiconductor region of the substrate. From another perspective, the graph in Figure 32 shows the distribution of the concentration of phosphorus as an n-type dopant in the first direction in the region of the sample of Example 3 corresponding to part II shown in Figure 2. In the graph in Figure 32, the horizontal axis represents position in the first direction, and the vertical axis represents the phosphorus concentration. In the graph in Figure 32, the position in the first direction showing the maximum peak (first peak) of the distribution of the phosphorus concentration in the first direction for the sample of Example 3 is set as zero (0), which is the reference position of the horizontal axis. As in the graphs in Figures 21, 25, and 29, the horizontal axis of the graph in Figure 32 shows the direction from the n-type polysilicon layer to the substrate as the positive direction, and the direction from the substrate to the n-type polysilicon layer as the negative direction. In other words, the first direction, which is the direction from the surface of the n-type polysilicon layer opposite to the substrate toward the substrate, is taken as the positive direction. The graph in Fig. 32 is a semi-logarithmic graph with a common logarithmic scale on the vertical axis, similar to the graphs in Figs. 21, 25, and 29.

[0177] In the graph of FIG. 32, the distribution of the phosphorus concentration in the first direction for the sample of Example 3 is indicated by a thick solid curve (strictly speaking, a broken line) Le3.

[0178] It should be noted that, for the sample of Specific Example 3, the maximum peak (first peak) in the distribution of the phosphorus concentration in the first direction was estimated to be located near the interface between the silicon oxide film and the n-type polysilicon layer by measuring the distribution of the oxygen concentration in the first direction by SIMS. For the sample of Specific Example 3, the maximum peak (first peak) in the distribution of the phosphorus concentration in the first direction was estimated to be caused by the segregation of phosphorus near the interface between the silicon oxide film and the n-type polysilicon layer, as in the samples of Specific Examples 2, 4, and 6 described above.

[0179] As shown in the graph of FIG. 32 , in the distribution of the phosphorus concentration in the first direction for the sample of Specific Example 3, it was confirmed that the phosphorus concentration gradually decreased as it approached the substrate in the range from approximately −25 nm to approximately −10 nm on the horizontal axis, whereas the phosphorus concentration increased in the range from approximately −10 nm to approximately −3 nm on the horizontal axis (also referred to as the fourth range).

[0180] It was presumed that the portion of the sample of Specific Example 3 corresponding to the fourth range on the horizontal axis was contained in a portion of the n-type polysilicon layer of the sample of Specific Example 3 that was formed by transformation of the intrinsic crystalline silicon layer by heat treatment. Here, it was presumed that the increase in the phosphorus concentration in the fourth range for the sample of Specific Example 3 occurred because, as with the samples of Specific Examples 2, 4, and 6 described above, the solid solubility of phosphorus in the intrinsic crystalline silicon layer formed on the silicon oxide film was higher than the solid solubility of phosphorus in the n-type amorphous silicon layer formed on the intrinsic crystalline silicon layer when the n-type polysilicon layer of the sample of Specific Example 3 was formed by heat treatment.

[0181] 32, a portion where the phosphorus concentration appears to be elevated was observed between approximately −3 nm and approximately −1.5 nm on the horizontal axis in the distribution of the phosphorus concentration in the first direction of the sample of Specific Example 3. It was presumed that this portion was caused by charging in the silicon oxide film during measurement using SIMS.

[0182] FIG. 33 shows a graph for recognizing the characteristics of the phosphorus concentration distribution in the first direction of the sample of Specific Example 3, taking noise components into consideration. In the graph of FIG. 33 , as in the graph of FIG. 32 , the horizontal axis represents the position in the first direction, and the vertical axis represents the phosphorus concentration. In the graph of FIG. 33 , as in the graph of FIG. 32 , the position in the first direction showing the maximum peak (first peak) of the phosphorus concentration distribution in the first direction for the sample of Specific Example 3 is set as zero (0), which is the reference position of the horizontal axis. Also, as in the horizontal axis of the graph of FIG. 32 , the direction from the n-type polysilicon layer toward the substrate is set as the positive direction on the horizontal axis of the graph of FIG. 33 , and the direction from the substrate toward the n-type polysilicon layer is set as the negative direction. In other words, the first direction, which is the direction from the surface of the n-type polysilicon layer opposite the substrate toward the substrate, is set as the positive direction. The graph in Fig. 33 is a graph (linear graph) in which the normal scale for the phosphorus concentration is assigned to the vertical axis at the left end, similar to the graphs in Fig. 22, Fig. 26, and Fig. 30. In Fig. 33, part of the distribution of the phosphorus concentration in the first direction of the sample of Specific Example 3 is indicated by a curve (strictly speaking, a broken line) Le3 drawn with a thick solid line.

[0183] In the graph of Figure 33, the distribution of the absolute value of the difference (Δ phosphorus concentration) between two adjacent phosphorus concentrations in the first direction for the phosphorus concentration distribution in the first direction of the sample of Specific Example 3 is shown by a curve (strictly speaking, a broken line) Le31 drawn with a thin solid line. In the graph of Figure 33, as in the graphs of Figures 22, 26, and 30, the vertical axis at the right end is marked with a normal scale for the Δ phosphorus concentration. In the graph of Figure 33, as in the graphs of Figures 22, 26, and 30, the graph of Figure 33 shows an example in which the region from -10 nm to -25 nm on the horizontal axis is set to the base region Ab0. In the graph of Figure 33, a linear function line Le32 is shown as a thin dashed line as an example of an approximation line approximating the phosphorus concentration distribution in the first direction of the sample of Specific Example 3 in the base region Ab0. 33, a straight line Le33 of a linear function is shown as a thin two-dot chain line as an example of a judgment line for the phosphorus concentration for the sample of Specific Example 3. In the graph of FIG. 33, a straight line Le33 of a linear function is shown as an example of a judgment line for the phosphorus concentration when m times is set to 3 times.

[0184] 32 and 33 , it was confirmed that the distribution of phosphorus concentration in the first direction in the region from the silicon oxide film side region of the n-type polysilicon layer of the sample of Example 3 through the silicon oxide film to the semiconductor region of the substrate had a maximum peak (first peak) Pk1 and a second peak Pk2. The second peak Pk2 was located at a position 3 nm or more away from the position of the first peak Pk1 in the direction from the semiconductor region of the substrate through the silicon oxide film toward the silicon oxide film side region of the n-type polysilicon layer. This characteristic of the distribution of phosphorus concentration in the first direction having the first peak Pk1 and the second peak Pk2 was confirmed at multiple locations in the sample of Example 3, and was also confirmed at multiple locations in another sample obtained by the same fabrication method as the sample of Example 3.

[0185] More specifically, the second peak Pk2 was located at a position about 6.2 nm away from the position of the first peak Pk1 in the direction from the semiconductor region of the substrate through the silicon oxide film toward the silicon oxide film side region of the n-type polysilicon layer. Note that in the graphs of Figures 32 and 33, in the distribution of phosphorus concentration in the first direction, the second peak Pk2 was the peak that first appeared when moving further in the negative direction from -3 nm on the horizontal axis.

[0186] 3-3-8. Characteristics of phosphorus concentration distribution in the sample of specific example 5> Fig. 34 is a graph showing an example of measurement results of the phosphorus concentration distribution in a part of the first direction obtained by using SIMS on the sample of specific example 5. Fig. 35 is a graph for explaining characteristics of the phosphorus concentration distribution in a part of the first direction obtained by using SIMS on the sample of specific example 5.

[0187] The graph in Figure 34 shows the distribution of the concentration of phosphorus as an n-type dopant in the first direction in the region of the n-type polysilicon layer of the sample of Example 5, from the silicon oxide film side region through the silicon oxide film to the semiconductor region of the substrate. From another perspective, the graph in Figure 34 shows the distribution of the concentration of phosphorus as an n-type dopant in the first direction in the region of the sample of Example 5 corresponding to part II shown in Figure 2. In the graph in Figure 34, the horizontal axis represents position in the first direction, and the vertical axis represents phosphorus concentration. In the graph in Figure 34, the position in the first direction showing the maximum peak (first peak) of the distribution of the phosphorus concentration in the first direction for the sample of Example 5 is set as zero (0), which is the reference position of the horizontal axis. As in the graphs in Figures 21, 25, 29, and 32, the horizontal axis of the graph in Figure 34 is set as the positive direction from the n-type polysilicon layer toward the substrate, and the negative direction from the substrate toward the n-type polysilicon layer. In other words, the first direction, which is the direction from the surface of the n-type polysilicon layer opposite to the substrate toward the substrate, is taken as the positive direction. The graph in Fig. 34 is a semi-logarithmic graph with a common logarithmic scale on the vertical axis, similar to the graphs in Figs. 21, 25, 29, and 32.

[0188] In the graph of FIG. 34, the distribution of the phosphorus concentration in the first direction for the sample of Example 5 is shown by a thick solid curve (strictly speaking, a broken line) Le5.

[0189] It should be noted that, for the sample of Specific Example 5, the maximum peak (first peak) in the distribution of the phosphorus concentration in the first direction was estimated to be located near the interface between the silicon oxide film and the n-type polysilicon layer by measuring the distribution of the oxygen concentration in the first direction by SIMS. For the sample of Specific Example 5, the maximum peak (first peak) in the distribution of the phosphorus concentration in the first direction was estimated to be caused by the segregation of phosphorus near the interface between the silicon oxide film and the n-type polysilicon layer, as in the samples of Specific Examples 2, 3, 4, and 6 described above.

[0190] As shown in the graph of FIG. 34 , in the distribution of the phosphorus concentration in the first direction for the sample of Specific Example 5, it was confirmed that the phosphorus concentration was almost constant in the range from approximately −25 nm to approximately −9 nm on the horizontal axis, whereas the phosphorus concentration increased in the range from approximately −9 nm to approximately −3 nm on the horizontal axis (also referred to as the fifth range).

[0191] It was presumed that the portion of the sample of Example 5 corresponding to the fifth range on the horizontal axis was contained in a portion of the n-type polysilicon layer of the sample of Example 5 that was formed by transformation of the intrinsic crystalline silicon layer by heat treatment. Here, it was presumed that the increase in the phosphorus concentration in the fifth range for the sample of Example 5, like the samples of Examples 2, 3, 4, and 6 described above, occurred because, when the n-type polysilicon layer of the sample of Example 5 was formed by heat treatment, the solid solubility of phosphorus in the intrinsic crystalline silicon layer formed on the silicon oxide film was higher than the solid solubility of phosphorus in the n-type amorphous silicon layer formed on the intrinsic crystalline silicon layer.

[0192] 34, a portion where the phosphorus concentration appears to be elevated was observed between approximately −3 nm and approximately −1.5 nm on the horizontal axis in the distribution of the phosphorus concentration in the first direction of the sample of Example 5. This portion was presumed to have been caused by charging in the silicon oxide film during measurement using SIMS.

[0193] FIG. 35 shows a graph for recognizing the characteristics of the phosphorus concentration distribution in the first direction of the sample of Specific Example 5, taking noise components into consideration. In the graph of FIG. 35 , as in the graph of FIG. 34 , the horizontal axis represents the position in the first direction, and the vertical axis represents the phosphorus concentration. In the graph of FIG. 35 , as in the graph of FIG. 34 , the position in the first direction showing the maximum peak (first peak) of the phosphorus concentration distribution in the first direction for the sample of Specific Example 5 is set as zero (0), which is the reference position of the horizontal axis. Also, on the horizontal axis of the graph of FIG. 35 , as in the horizontal axis of the graph of FIG. 34 , the direction from the n-type polysilicon layer toward the substrate is set as the positive direction, and the direction from the substrate toward the n-type polysilicon layer is set as the negative direction. In other words, the first direction, which is the direction from the surface of the n-type polysilicon layer opposite the substrate toward the substrate, is set as the positive direction. The graph in Fig. 35 is a graph (linear graph) in which the normal scale for the phosphorus concentration is assigned to the vertical axis at the left end, similar to the graphs in Fig. 22, Fig. 26, Fig. 30, and Fig. 33. In Fig. 35, a part of the distribution of the phosphorus concentration in the first direction of the sample of Specific Example 5 is indicated by a curve (strictly speaking, a broken line) Le5 drawn with a thick solid line.

[0194] In the graph of Figure 35, the distribution of the absolute value of the difference (Δ phosphorus concentration) between two adjacent phosphorus concentrations in the first direction for the phosphorus concentration distribution in the first direction of the sample of Specific Example 5 is shown by a curve (strictly speaking, a broken line) Le51 drawn with a thin solid line. In the graph of Figure 35, as in the graphs of Figures 22, 26, 30, and 33, the vertical axis at the right end is marked with a normal scale for the Δ phosphorus concentration. In the graph of Figure 35, as in the graphs of Figures 22, 26, 30, and 33, the graph of Figure 35 shows an example in which the region from -10 nm to -25 nm on the horizontal axis is set to the base region Ab0. In the graph of Figure 35, a linear function line Le52 is shown as a thin dashed line as an example of an approximation line approximating the phosphorus concentration distribution in the first direction for the sample of Specific Example 5 in the base region Ab0. 35, a straight line Le53 of a linear function is shown as a thin two-dot chain line as an example of a judgment line for the phosphorus concentration for the sample of Specific Example 5. In the graph of FIG. 35, a straight line Le53 of a linear function is shown as an example of a judgment line for the phosphorus concentration when m times is set to 3 times.

[0195] 34 and 35 , it was confirmed that the distribution of phosphorus concentration in the first direction in the region from the silicon oxide film side region of the n-type polysilicon layer of the sample of Example 5 through the silicon oxide film to the semiconductor region of the substrate had a maximum peak (first peak) Pk1 and a second peak Pk2. The second peak Pk2 was located at a position 3 nm or more away from the position of the first peak Pk1 in the direction from the semiconductor region of the substrate through the silicon oxide film toward the silicon oxide film side region of the n-type polysilicon layer. This characteristic of the distribution of phosphorus concentration in the first direction having the first peak Pk1 and the second peak Pk2 was confirmed at multiple locations in the sample of Example 5, and was also confirmed at multiple locations in another sample obtained by the same fabrication method as the sample of Example 5.

[0196] More specifically, the second peak Pk2 was located at a position about 6.3 nm away from the position of the first peak Pk1 in the direction from the semiconductor region of the substrate through the silicon oxide film toward the silicon oxide film side region of the n-type polysilicon layer. Note that in each of the graphs in Figures 34 and 35, in the distribution of phosphorus concentration in the first direction, the second peak Pk2 was the peak that first appeared when moving further in the negative direction from -3 nm on the horizontal axis.

[0197] 3-3-9. Configuration of solar cell element suitable for manufacturing method capable of reducing defects As shown in the graphs of FIGS. 21 , 22 , 25 , 26 , 29 , 30 , and 32 to 35 , it has been understood that the solar cell element 1 manufactured by the manufacturing method of the solar cell element 1 according to the first embodiment described above can be an element having either of the following configurations 1 and 2.

[0198] [Configuration 1] Solar cell element 1 includes a silicon substrate 2, a silicon oxide film 3, and an n-type polysilicon layer 4. Silicon substrate 2 has a first semiconductor region 21 as a first region, which is a region of n-type semiconductor as a first conductivity type. Silicon oxide film 3 is an oxide film in contact with first semiconductor region 21. N-type polysilicon layer 4 is in contact with the surface of silicon oxide film 3 opposite to first semiconductor region 21 and is an n-type polysilicon layer containing phosphorus as an n-type dopant. N-type polysilicon layer 4 includes a region 41 (also referred to as an oxide film side region) as a second region on the side of silicon oxide film 3 that is in contact with silicon oxide film 3. In this solar cell element 1, in the region extending from the oxide film-side region 41 through the silicon oxide film 3 to the first semiconductor region 21, the distribution of the concentration of phosphorus as an n-type dopant in the first thickness direction D1, which is the direction from the surface of the n-type polysilicon layer 4 on the side opposite to the silicon substrate 2 toward the silicon substrate 2, has a maximum first peak Pk1 and a second peak Pk2. The second peak Pk2 is located at a position 3 nm or more away from the position of the first peak Pk1 in the direction from the first semiconductor region 21 through the silicon oxide film 3 toward the oxide film-side region 41.

[0199] [Configuration 2] The solar cell element 1 includes a silicon substrate 2 and an n-type polysilicon layer 4. The silicon substrate 2 has a first semiconductor region 21 as a first region, which is a region of an n-type semiconductor as a first conductivity type. The n-type polysilicon layer 4 is in contact with the silicon substrate 2 and is an n-type polysilicon layer containing phosphorus as an n-type dopant. The silicon substrate 2 includes a silicon oxide film 3. The silicon oxide film 3 is an oxide film located between the first semiconductor region 21 and the n-type polysilicon layer 4 and in contact with both the first semiconductor region 21 and the n-type polysilicon layer 4. The n-type polysilicon layer 4 includes a region (oxide film side region) 41 as a second region on the side of the silicon oxide film 3 that is in contact with the silicon oxide film 3. In this solar cell element 1, in the region extending from the oxide film-side region 41 through the silicon oxide film 3 to the first semiconductor region 21, the distribution of the concentration of phosphorus as an n-type dopant in the first thickness direction D1, which is the direction from the surface of the n-type polysilicon layer 4 on the side opposite to the silicon substrate 2 toward the silicon substrate 2, has a maximum first peak Pk1 and a second peak Pk2. The second peak Pk2 is located at a position 3 nm or more away from the position of the first peak Pk1 in the direction from the first semiconductor region 21 through the silicon oxide film 3 toward the oxide film-side region 41.

[0200] In other words, it was understood that the solar cell element 1 having either of the above-mentioned configurations 1 and 2 has a configuration suitable for a method for manufacturing the solar cell element 1 that can reduce the occurrence of blisters and local defects caused by blisters when the n-type polysilicon layer 4 as the doped polysilicon layer is formed. In other words, it was understood that the solar cell element 1 having either of the above-mentioned configurations 1 and 2 has a configuration suitable for a method for manufacturing the solar cell element 1 that can reduce the occurrence of blisters and local defects caused by blisters when the n-type polysilicon layer 4 as the doped polysilicon layer is formed by performing deposition of the n-type amorphous silicon layer 4b as the doped amorphous silicon layer and heat treatment for crystallization of this n-type amorphous silicon layer 4b. In other words, it was understood that the solar cell element 1 having either of the above-mentioned configurations 1 and 2 has a configuration suitable for a method for manufacturing the solar cell element 1 that can reduce defects in the solar cell element 1 having an example of a TOPCon structure, which is a type of POLO structure, formed using a doped amorphous silicon layer. Therefore, it was understood that defects can be reduced in the solar cell element 1 having an example of a TOPCon structure, which is a type of POLO structure formed using a doped amorphous silicon layer, by employing the solar cell element 1 having either of the above-described configurations 1 and 2. From another perspective, it was understood that defects in the solar cell element 1 can be easily reduced.

[0201] In each of the above-described configurations 1 and 2, the distribution of the concentration of phosphorus as an n-type dopant in the first thickness direction D1, which is the direction from the surface of the n-type polysilicon layer 4 on the side opposite to the silicon substrate 2 toward the silicon substrate 2, in the region from the oxide film side region 41 of the n-type polysilicon layer 4 through the silicon oxide film 3 to the first semiconductor region 21 may be the result of measurement using, for example, SIMS, as described above.

[0202] In each of the above-described configurations 1 and 2, for example, when the n-type polysilicon layer 4 is equally divided into N regions (N is a natural number equal to or greater than 2) in the first thickness direction D1, the oxide film-side region 41 may be the region closest to the silicon oxide film 3 among the N regions. N may be, for example, two, three, or any number equal to or greater than four. The any number equal to or greater than four may be six. For example, the oxide film-side region 41 may be a region of the n-type polysilicon layer 4 that is 10 nm or less away from the silicon oxide film 3.

[0203] 21 , 22 , 25 , 26 , 29 , 30 , and 32 to 35 , the second peak Pk2 may be located at a position 3 to 10 nm away from the position of the first peak Pk1 in the direction from the first semiconductor region 21 toward the oxide film-side region 41 via the silicon oxide film 3. Here, the second peak Pk2 may be located at a position 3 to 8 nm away from the position of the first peak Pk1, or may be located at a position 3 to 7 nm away from the position of the first peak Pk1 in the direction from the first semiconductor region 21 toward the oxide film-side region 41 via the silicon oxide film 3.

[0204] <3-4. Characteristics of Samples of Specific Examples and Reference Examples> The samples of Specific Examples 1 to 3, Specific Example 5, Specific Example 7, Specific Example 8, Specific Example 21, Specific Example 22, Specific Example 23, Specific Example 24, and Specific Example 25 were used as the targets, and the sheet resistance of the n-type polysilicon layer was measured by the four-terminal method under the same conditions.

[0205]

[0206] As shown in Table 3, the sheet resistance of the n-type polysilicon layer of each of the samples of Example 1 and Example 2 was high, reaching several kOhms per square (Ω / □). In contrast, the sheet resistance of the n-type polysilicon layer of the sample of Example 3 was approximately 236 Ω / □. The sheet resistance of the n-type polysilicon layer of the sample of Example 5 was approximately 179 Ω / □. The sheet resistance of the n-type polysilicon layer of the sample of Example 7 was approximately 35 Ω / □. The sheet resistance of the n-type polysilicon layer of the sample of Example 8 was approximately 16 Ω / □.

[0207]

[0208] As shown in Table 4, the sheet resistance of the n-type polysilicon layer of the sample of Example 21 was about 100 Ω / □. The sheet resistance of the n-type polysilicon layer of the sample of Example 22 was about 85 Ω / □. The sheet resistance of the n-type polysilicon layer of the sample of Example 23 was about 71 Ω / □. The sheet resistance of the n-type polysilicon layer of the sample of Example 24 was about 59 Ω / □. The sheet resistance of the n-type polysilicon layer of the sample of Example 25 was about 18 Ω / □.

[0209] Therefore, it was estimated that the sheet resistance of the n-type polysilicon layer was reduced by sufficient activation of the n-type dopant in the n-type polysilicon layer when the heat treatment temperature during formation of the n-type polysilicon layer was set within the range of 700° C. to 1000° C. Therefore, it was estimated that the conversion efficiency of the solar cell element 1 can be improved by setting the heat treatment temperature during formation of the n-type polysilicon layer 4 within the range of 700° C. to 1000° C. in the manufacturing method of the solar cell element 1 according to the first embodiment described above.

[0210] The carrier lifetime and iVoc of each of the samples of Specific Examples 11 to 15 and Reference Example 13 were measured using a quasi-steady-state photoconductivity measurement device (QSSPC) manufactured by Sinton.

[0211]

[0212] As shown in Table 5, for the sample of Reference Example 13, the carrier lifetime was 71 microseconds (μs) and the iVoc was 626 millivolts (mV). For the sample of Example 11, the carrier lifetime was 1544 μs and the iVoc was 716 mV. For the sample of Example 12, the carrier lifetime was 2573 μs and the iVoc was 727 mV. For the sample of Example 13, the carrier lifetime was 4289 μs and the iVoc was 737 mV. For the sample of Example 14, the carrier lifetime was 1546 μs and the iVoc was 714 mV. For the sample of Example 15, the carrier lifetime was 39 μs and the iVoc was 624 mV.

[0213] Here, it was confirmed that the carrier lifetime and iVoc were significantly improved in the sample of Specific Example 13 compared to the sample of Reference Example 13. As shown in Table 2, the sample of Reference Example 13 was confirmed to have numerous local defects and blisters in the n-type polysilicon layer, whereas the sample of Specific Example 13 was confirmed to have no local defects or blisters in the n-type polysilicon layer. It was presumed that the passivation performance of the TOPCon structure, which is a type of POLO structure, was improved in the sample of Specific Example 13 compared to the sample of Reference Example 13 due to the reduction in the presence of local defects and blisters in the n-type polysilicon layer.

[0214] Therefore, it was understood that by adopting the manufacturing method of the solar cell element 1 according to the first embodiment, the passivation performance of the TOPCon structure, which is a type of POLO structure, can be improved, and the conversion efficiency of the solar cell element 1 can be improved.

[0215] Furthermore, in this example, the sample of Specific Example 15 had a carrier lifetime of approximately 39 μs or more and an iVoc of 624 mV, whereas the samples of Specific Examples 11 to 14 had a carrier lifetime of 1544 μs or more and an iVoc of 714 mV or more. Therefore, it was estimated that the passivation performance of the samples of Specific Examples 11 to 14, which are based on the TOPCon structure, which is a type of POLO structure, was superior to that of the sample of Specific Example 15. Therefore, it was estimated that the silicon oxide film 3 can be more stable when the heat treatment temperature during the formation of the n-type polysilicon layer is set within the range of 700° C. to 900° C. than when it is set at 950° C.

[0216] Therefore, in the manufacturing method of the solar cell element 1 according to the first embodiment, it was estimated that the conversion efficiency of the solar cell element 1 can be improved by setting the heat treatment temperature when the n-type polysilicon layer 4 is formed to 700°C to 900°C.

[0217] 4. Summary of First Embodiment The manufacturing method of solar cell element 1 according to the first embodiment includes, for example, steps 1, 2, 3, and 4. In step 1, a silicon oxide film 3 is formed on a silicon substrate 2 serving as a crystalline silicon substrate, the silicon substrate 2 including an n-type first semiconductor region 21 serving as a first region that is a semiconductor region of a first conductivity type, in a portion along the surface of the silicon substrate 2 or on the surface of the silicon substrate 2, the silicon oxide film 3 being located inside the silicon substrate 2 and in contact with the first semiconductor region 21. In step 2, an intrinsic crystalline silicon layer 4a serving as a first layer of intrinsic crystalline silicon is formed on the silicon oxide film 3. In step 3, an n-type amorphous silicon layer 4b serving as a second layer of amorphous silicon having a thickness greater than that of the intrinsic crystalline silicon layer 4a and containing phosphorus as an n-type dopant of the first conductivity type is formed on the intrinsic crystalline silicon layer 4a. In step 4, a heat treatment is carried out to promote crystallization of the amorphous silicon of n-type amorphous silicon layer 4b while diffusing phosphorus as an n-type dopant contained in n-type amorphous silicon layer 4b toward intrinsic crystalline silicon layer 4a and silicon oxide film 3. As a result, n-type polysilicon layer 4 is produced from intrinsic crystalline silicon layer 4a and n-type amorphous silicon layer 4b as a polysilicon layer located on silicon oxide film 3 and containing phosphorus as an n-type dopant.

[0218] In other words, the manufacturing method of the solar cell element 1 according to the first embodiment is characterized in that, when the n-type polysilicon layer 4 is formed on the silicon oxide film 3, an intrinsic crystalline silicon layer 4a is formed on the silicon oxide film 3, an n-type amorphous silicon layer 4b is further formed on the intrinsic crystalline silicon layer 4a, and then the n-type polysilicon layer 4 is produced from the intrinsic crystalline silicon layer 4a and the n-type amorphous silicon layer 4b by heat treatment. This reduces the occurrence of blisters and local defects caused by blisters when forming the n-type polysilicon layer 4 as a doped polysilicon layer. In other words, defects can be reduced in the solar cell element 1 having an example of a TOPCon structure, which is a type of POLO structure, formed using the n-type amorphous silicon layer 4b as a doped amorphous silicon layer. From another perspective, defects in the solar cell element 1 can be easily reduced.

[0219] The solar cell element 1 according to the first embodiment has, for example, the following configuration 1, configuration 2, configuration 5, or configuration 6 described above.

[0220] [Configuration 1] Solar cell element 1 includes a silicon substrate 2, a silicon oxide film 3, and an n-type polysilicon layer 4. Silicon substrate 2 has a first semiconductor region 21 as a first region, which is a region of n-type semiconductor as a first conductivity type. Silicon oxide film 3 is an oxide film in contact with first semiconductor region 21. N-type polysilicon layer 4 is in contact with the surface of silicon oxide film 3 opposite to first semiconductor region 21 and is an n-type polysilicon layer containing phosphorus as an n-type dopant. N-type polysilicon layer 4 includes a region (oxide film side region) 41 as a second region on the side of silicon oxide film 3 that is in contact with silicon oxide film 3. In this solar cell element 1, in the region extending from the oxide film-side region 41 through the silicon oxide film 3 to the first semiconductor region 21, the distribution of the concentration of phosphorus as an n-type dopant in the first thickness direction D1, which is the direction from the surface of the n-type polysilicon layer 4 on the side opposite to the silicon substrate 2 toward the silicon substrate 2, has a maximum first peak Pk1 and a second peak Pk2. The second peak Pk2 is located at a position 3 nm or more away from the position of the first peak Pk1 in the direction from the first semiconductor region 21 through the silicon oxide film 3 toward the oxide film-side region 41.

[0221] [Configuration 2] The solar cell element 1 includes a silicon substrate 2 and an n-type polysilicon layer 4. The silicon substrate 2 has a first semiconductor region 21 as a first region, which is a region of an n-type semiconductor as a first conductivity type. The n-type polysilicon layer 4 is in contact with the silicon substrate 2 and is an n-type polysilicon layer containing phosphorus as an n-type dopant. The silicon substrate 2 includes a silicon oxide film 3. The silicon oxide film 3 is an oxide film located between the first semiconductor region 21 and the n-type polysilicon layer 4 and in contact with both the first semiconductor region 21 and the n-type polysilicon layer 4. The n-type polysilicon layer 4 includes a region (oxide film side region) 41 as a second region on the side of the silicon oxide film 3 that is in contact with the silicon oxide film 3. In this solar cell element 1, in the region extending from the oxide film-side region 41 through the silicon oxide film 3 to the first semiconductor region 21, the distribution of the concentration of phosphorus as an n-type dopant in the first thickness direction D1, which is the direction from the surface of the n-type polysilicon layer 4 on the side opposite to the silicon substrate 2 toward the silicon substrate 2, has a maximum first peak Pk1 and a second peak Pk2. The second peak Pk2 is located at a position 3 nm or more away from the position of the first peak Pk1 in the direction from the first semiconductor region 21 through the silicon oxide film 3 toward the oxide film-side region 41.

[0222] [Configuration 5] The solar cell element 1 includes a silicon substrate 2, a silicon oxide film 3, and an n-type polysilicon layer 4. The silicon substrate 2 has a first semiconductor region 21 as a first region, which is a region of an n-type semiconductor having a first conductivity type. The silicon oxide film 3 is an oxide film in contact with the first semiconductor region 21. The n-type polysilicon layer 4 is in contact with the surface of the silicon oxide film 3 opposite the first semiconductor region 21 and is an n-type polysilicon layer containing phosphorus as an n-type dopant. The n-type polysilicon layer 4 is formed by performing a heat treatment on an intrinsic crystalline silicon layer 4a as a first layer of intrinsic crystalline silicon located on the silicon oxide film 3, and an n-type amorphous silicon layer 4b as a second layer of amorphous silicon located on the intrinsic crystalline silicon layer 4a, having a thickness greater than that of the intrinsic crystalline silicon layer 4a, and containing phosphorus as an n-type dopant. This heat treatment is a process for diffusing phosphorus as an n-type dopant contained in the n-type amorphous silicon layer 4 b toward the intrinsic crystalline silicon layer 4 a and the silicon oxide film 3, thereby promoting the crystallization of the amorphous silicon in the n-type amorphous silicon layer 4 b.

[0223] [Configuration 6] The solar cell element 1 includes a silicon substrate 2 and an n-type polysilicon layer 4. The silicon substrate 2 has a first semiconductor region 21 as a first region, which is a region of an n-type semiconductor as a first conductivity type. The n-type polysilicon layer 4 is in contact with the silicon substrate 2 and is an n-type polysilicon layer containing phosphorus as an n-type dopant. The silicon substrate 2 includes a silicon oxide film 3. The silicon oxide film 3 is an oxide film located between the first semiconductor region 21 and the n-type polysilicon layer 4 and in contact with both the first semiconductor region 21 and the n-type polysilicon layer 4. The n-type polysilicon layer 4 is a layer produced from the intrinsic crystalline silicon layer 4a and the n-type amorphous silicon layer 4b by performing a heat treatment on the intrinsic crystalline silicon layer 4a, which is a first layer of intrinsic crystalline silicon located on the silicon oxide film 3, and the n-type amorphous silicon layer 4b, which is a second layer of amorphous silicon located on the intrinsic crystalline silicon layer 4a, has a thickness greater than that of the intrinsic crystalline silicon layer 4a, and contains phosphorus as an n-type dopant. This heat treatment is a process that diffuses phosphorus, which is an n-type dopant contained in the n-type amorphous silicon layer 4b, toward the intrinsic crystalline silicon layer 4a and the silicon oxide film 3, thereby promoting crystallization of the amorphous silicon of the n-type amorphous silicon layer 4b.

[0224] The solar cell element 1 having the configuration 1, 2, 5, or 6 can be manufactured by the manufacturing method for the solar cell element 1 according to the first embodiment. When the solar cell element 1 is manufactured by the manufacturing method for the solar cell element 1 according to the first embodiment, the occurrence of blisters and local defects due to blisters during the formation of the n-type polysilicon layer 4 as a doped polysilicon layer can be reduced. In other words, when the solar cell element 1 is manufactured by the manufacturing method for the solar cell element 1 according to the first embodiment, defects can be reduced in the solar cell element 1 having an example of a TOPCon structure, which is a type of POLO structure, formed using the n-type amorphous silicon layer 4b as a doped amorphous silicon layer. Therefore, by employing the solar cell element 1 having the configuration 1, 2, 5, or 6 suitable for a manufacturing method for the solar cell element 1 that can reduce defects in the solar cell element 1 having an example of a TOPCon structure, which is a type of POLO structure, formed using a doped amorphous silicon layer, defects can be reduced in the solar cell element 1 having an example of a TOPCon structure, which is a type of POLO structure, formed using a doped amorphous silicon layer.

[0225] 5. Other Embodiments The present disclosure is not limited to the first embodiment described above, and various modifications and improvements can be made without departing from the gist of the present disclosure.

[0226] The manufacturing method of the solar cell element 1 according to the first embodiment is a manufacturing method for forming a TOPCon structure, which is a type of POLO structure, in which the first semiconductor region 21, the silicon oxide film 3, and the n-type polysilicon layer 4 are stacked in this order on the second surface 2b side of the silicon substrate 2. This manufacturing method of the solar cell element 1 is characterized in that, when the n-type polysilicon layer 4 is formed on the silicon oxide film 3, an intrinsic crystalline silicon layer 4a is formed on the silicon oxide film 3, and an n-type amorphous silicon layer 4b is further formed on the intrinsic crystalline silicon layer 4a, and then the n-type polysilicon layer 4 is produced from the intrinsic crystalline silicon layer 4a and the n-type amorphous silicon layer 4b by heat treatment. However, the manufacturing method of the solar cell element according to the present disclosure is not limited to this.

[0227] For example, the solar cell element may include various types of POLO structures different from the solar cell element 1 according to the first embodiment. In other words, the solar cell element 1 according to the first embodiment includes a TOPCon structure, in which an n-type first region, an oxide film, and an n-type polysilicon layer are stacked in this order, as an example of a POLO structure. However, the solar cell element according to the present disclosure is not limited to this structure. Furthermore, for example, the manufacturing method for the solar cell element according to the present disclosure is not limited to a method for manufacturing the solar cell element 1 including a TOPCon structure, which is a type of POLO structure in which an n-type first region, an oxide film, and an n-type polysilicon layer are stacked in this order. In other words, the manufacturing method for the solar cell element 1 according to the first embodiment may be modified as appropriate to form various types of POLO structures.

[0228] For example, as long as the solar cell function is realized, the solar cell element 1 may be modified to include a POLO structure on the front surface 1f side, or may be modified to include a POLO structure on both the front surface 1f side and the back surface 1b side. Regarding the POLO structure, for example, as long as the solar cell function is realized, the first region of the crystalline silicon substrate as the first conductivity type may be a p-type semiconductor region or an n-type semiconductor region. Here, for example, if the first region is a p-type semiconductor region of the crystalline silicon substrate as the first conductivity type, the polysilicon layer may be a layer containing a p-type dopant as the first conductivity type, or a layer containing an n-type dopant as the second conductivity type. For example, if the first region is an n-type semiconductor region of the crystalline silicon substrate as the first conductivity type, the polysilicon layer may be a layer containing an n-type dopant as the first conductivity type, or a layer containing a p-type dopant as the second conductivity type.

[0229] In other words, the solar cell element may have various forms as long as it includes a POLO structure including: a first region that is a region of a semiconductor of a first conductivity type in a crystalline silicon substrate; an oxide film located inside the substrate and along the surface of the substrate or on the surface of the substrate and in contact with the first region; and a polysilicon layer located on the oxide film and containing a dopant of the first conductivity type or the second conductivity type. For example, the solar cell element may have various forms as long as it includes a POLO structure including: a substrate having a first region that is a region of a semiconductor of a first conductivity type, an oxide film in contact with the first region of the substrate, and a polysilicon layer in contact with the surface of the oxide film opposite to the first region and containing a dopant of the first conductivity type or the second conductivity type. For example, the solar cell element may have various forms within the scope of a structure including a substrate having a first region which is a region of a semiconductor of a first conductivity type, and a polysilicon layer in contact with the substrate and containing a dopant of the first conductivity type or the second conductivity type, wherein the substrate is located between the first region and the polysilicon layer and includes an oxide film in contact with each of the first region and the polysilicon layer, a POLO structure.

[0230] As various forms of this solar cell element, for example, a solar cell element including one POLO structure or two POLO structures among the following Structures 1 to 4 can be considered.

[0231] [Structure 1] A POLO structure in which an n-type first region, an oxide film, and an n-type polysilicon layer are stacked in this order. This structure corresponds to a TOPCon structure, which is a type of POLO structure.

[0232] [Structure 2] A POLO structure in which a p-type first region, an oxide film, and an n-type polysilicon layer are stacked in this order.

[0233] [Structure 3] A POLO structure in which a p-type first region, an oxide film, and a p-type polysilicon layer are stacked in this order. This structure corresponds to a TOPCon structure, which is a type of POLO structure.

[0234] [Structure 4] A POLO structure in which an n-type first region, an oxide film, and a p-type polysilicon layer are stacked in this order.

[0235] The solar cell element 1 according to the first embodiment is an example of a solar cell element including the structure 1.

[0236] 5-1. Examples of configurations and manufacturing methods of solar cell elements including a POLO structure according to structure 2> Fig. 36 is a cross-sectional view schematically showing an example of the configuration of a solar cell element 1A according to the second embodiment. Fig. 37 is a cross-sectional view schematically showing an example of the configuration of a solar cell element 1B according to the third embodiment. Fig. 38 is an enlarged cross-sectional view schematically showing part XXXVIII of Fig. 36 in the configuration of solar cell element 1A according to the second embodiment and part XXXVIII of Fig. 37 in the configuration of solar cell element 1B according to the third embodiment.

[0237] As shown in Figure 36, the solar cell element 1A of the second embodiment includes, for example, an example of a POLO structure related to the above structure 2 on the surface (back surface) 1b side facing the -Z direction of the solar cell element 1A.

[0238] The solar cell element 1A according to the second embodiment is based on the solar cell element 1 according to the first embodiment, with the silicon substrate 2 being replaced with a silicon substrate 2A. The silicon substrate 2A has a first semiconductor region 21A and a second semiconductor region 22A. The second semiconductor region 22A occupies a portion of the silicon substrate 2A that contacts the second electrode 9. The first semiconductor region 21A occupies substantially the entire silicon substrate 2A except for the portion that contacts the second electrode 9. The first semiconductor region 21A and the second semiconductor region 22A are each a region of a p-type semiconductor as the first conductivity type. The concentration of the p-type dopant in the second semiconductor region 22A is higher than the concentration of the p-type dopant in the first semiconductor region 21A.

[0239] For this reason, the solar cell element 1A according to the second embodiment includes a silicon substrate 2A having a first semiconductor region 21A and an n-type polysilicon layer 4. Furthermore, in the second embodiment, the solar cell element 1A may include a silicon oxide film 3 in contact with the first semiconductor region 21A, separate from the silicon substrate 2A, or the silicon substrate 2A may include a silicon oxide film 3 located between the first semiconductor region 21A and the n-type polysilicon layer 4 and in contact with both the first semiconductor region 21A and the n-type polysilicon layer 4. The first semiconductor region 21A is a first region of the silicon substrate 2A as a substrate, which is a p-type semiconductor region having a first conductivity type. The silicon oxide film 3 may be an oxide film located inside the silicon substrate 2A and along the surface of the silicon substrate 2A, or located on the surface of the silicon substrate 2A and in contact with the first semiconductor region 21A. The n-type polysilicon layer 4 is a polysilicon layer that is in contact with the surface of the silicon oxide film 3 opposite to the first semiconductor region 21A and that contains an n-type dopant as the second conductivity type. When the silicon oxide film 3 is located inside the silicon substrate 2A and along the surface of the silicon substrate 2A, the n-type polysilicon layer 4 is a polysilicon layer that is in contact with the silicon substrate 2A and that contains an n-type dopant as the second conductivity type. In other words, the solar cell element 1A according to the second embodiment includes a structure, as an example of the POLO structure according to the above structure 2, in which the first semiconductor region 21A as the p-type first region, the silicon oxide film 3 as the oxide film, and the n-type polysilicon layer 4 as the n-type polysilicon layer are stacked in this order.

[0240] The solar cell element 1A according to the second embodiment can be manufactured, for example, by a manufacturing method based on the manufacturing method for the solar cell element 1 according to the first embodiment shown in the flowchart of Figure 3, but with some modifications to this manufacturing method.

[0241] 3, a p-type silicon substrate is prepared instead of an n-type silicon substrate, for example, a crystalline silicon substrate doped with boron or gallium as a p-type dopant may be prepared as the p-type silicon substrate.

[0242] In step S2 of FIG. 3, a p-type silicon substrate is used instead of an n-type silicon substrate.

[0243] 3, instead of forming the second semiconductor region 22, the second semiconductor region 22A is formed locally. As a result, the portion of the p-type silicon substrate other than the second semiconductor region 22A can become the first semiconductor region 21A. Here, for example, the second semiconductor region 22A can be formed locally by locally introducing a p-type dopant such as boron into a portion located inside the p-type crystalline silicon substrate and along the surface of this substrate. The local introduction of the p-type dopant can be performed, for example, by applying a paste-like boron oxide (B ２ O ３ This can be achieved by locally irradiating a boron glass layer formed by applying boron tribromide (BBr) to the boron glass layer. After this treatment, unnecessary boron glass layer can be removed by etching using, for example, hydrofluoric acid. Furthermore, local introduction of a p-type dopant can be achieved by, for example, arranging a mask and applying gaseous boron tribromide (BBr) to the boron glass layer. ３ ) as a diffusion source. Alternatively, the second semiconductor region 22A may be locally formed by locally introducing aluminum as a p-type dopant into a portion located inside the p-type silicon substrate and along the surface of the p-type silicon substrate. In this case, the local introduction of the p-type dopant can be achieved, for example, by locally irradiating a laser beam onto an aluminum-containing layer (also referred to as an aluminum-containing layer) formed by applying and drying an aluminum paste to the surface of the p-type silicon substrate. After this process, the unnecessary aluminum-containing layer can be removed by etching using, for example, hydrochloric acid. Here, the aluminum paste may be, for example, a paste containing aluminum powder, an organic vehicle, and glass frit.

[0244] In steps S4 and S5 of FIG. 3, processing is performed in which the silicon substrate 2 and the first semiconductor region 21 are changed to a silicon substrate 2A and a first semiconductor region 21A.

[0245] Here, an example of the POLO structure according to Structure 2 in solar cell element 1A according to the second embodiment can be formed by processing in accordance with the above-described modified steps S4 and S5. More specifically, for example, an example of the POLO structure according to Structure 2 in solar cell element 1A according to the second embodiment can be formed by a manufacturing method for solar cell element 1A including the following steps 1a, 2a, 3a, and 4a.

[0246] [Step 1a] A silicon oxide film 3 is formed as an oxide film in contact with a first semiconductor region 21A located inside a silicon substrate 2A as a crystalline silicon substrate including a first region 21A that is a region of a p-type semiconductor as a first conductivity type, along the surface of the silicon substrate 2A or on the surface of the silicon substrate 2A.

[0247] [Step 2a] On the silicon oxide film 3, an intrinsic crystalline silicon layer 4a is formed as a first layer of intrinsic crystalline silicon.

[0248] [Step 3a] An n-type amorphous silicon layer 4b is formed on the intrinsic crystalline silicon layer 4a. The n-type amorphous silicon layer 4b has a thickness greater than that of the intrinsic crystalline silicon layer 4a and serves as a second layer of amorphous silicon containing an n-type dopant (e.g., phosphorus) as a second conductivity type. The n-type amorphous silicon layer 4b may be formed using, for example, a PECVD method.

[0249] [Step 4a] A heat treatment is carried out to promote crystallization of the amorphous silicon of the n-type amorphous silicon layer 4b while diffusing the n-type dopant (e.g., phosphorus) contained in the n-type amorphous silicon layer 4b toward the intrinsic crystalline silicon layer 4a and the silicon oxide film 3. As a result, the n-type polysilicon layer 4 is produced from the intrinsic crystalline silicon layer 4a and the n-type amorphous silicon layer 4b as a polysilicon layer located on the silicon oxide film 3 and containing the n-type dopant (e.g., phosphorus).

[0250] Here, the n-type polysilicon layer 4 is formed on the silicon oxide film 3 by carrying out the above steps 2a to 4a.

[0251] The above-mentioned step 1a is an example of the first step of the present disclosure. The above-mentioned step 2a is an example of the second step of the present disclosure. The above-mentioned step 3a is an example of the third step of the present disclosure. The above-mentioned step 4a is an example of the fourth step of the present disclosure.

[0252] According to the manufacturing method of solar cell element 1A including the above steps 1a, 2a, 3a, and 4a, as explained with reference to specific examples 1 to 8 in Table 1 above, the occurrence of blisters and local defects caused by blisters when forming n-type polysilicon layer 4 as a doped polysilicon layer can be reduced. In other words, defects can be reduced in solar cell element 1A having an example of a POLO structure formed using n-type amorphous silicon layer 4b as a doped amorphous silicon layer. From another perspective, defects in solar cell element 1A can be easily reduced.

[0253] Incidentally, the solar cell element 1A manufactured by the manufacturing method of the solar cell element 1A of the second embodiment in which the above steps 1a to 4a are executed can be said to be an element having either of the following configurations 5a and 6a.

[0254] [Configuration 5a] Solar cell element 1A includes a silicon substrate 2A, a silicon oxide film 3, and an n-type polysilicon layer 4. Silicon substrate 2A has a first semiconductor region 21A as a first region, which is a region of p-type semiconductor as a first conductivity type. Silicon oxide film 3 is an oxide film in contact with first semiconductor region 21A. N-type polysilicon layer 4 is in contact with a surface of silicon oxide film 3 opposite to first semiconductor region 21A, and is an n-type polysilicon layer containing an n-type dopant (e.g., phosphorus) as a second conductivity type different from the first conductivity type. The n-type polysilicon layer 4 is a layer produced from the intrinsic crystalline silicon layer 4a and the n-type amorphous silicon layer 4b by performing a heat treatment on the intrinsic crystalline silicon layer 4a, which is a first layer of intrinsic crystalline silicon located on the silicon oxide film 3, and the n-type amorphous silicon layer 4b, which is a second layer of amorphous silicon located on the intrinsic crystalline silicon layer 4a, has a thickness greater than that of the intrinsic crystalline silicon layer 4a, and contains an n-type dopant (e.g., phosphorus). This heat treatment is a process that diffuses the n-type dopant (e.g., phosphorus) contained in the n-type amorphous silicon layer 4b toward the intrinsic crystalline silicon layer 4a and the silicon oxide film 3, while promoting crystallization of the amorphous silicon of the n-type amorphous silicon layer 4b.

[0255] [Configuration 6a] The solar cell element 1A includes a silicon substrate 2A and an n-type polysilicon layer 4. The silicon substrate 2A has a first semiconductor region 21A as a first region, which is a region of a p-type semiconductor as a first conductivity type. The n-type polysilicon layer 4 is in contact with the silicon substrate 2A and is an n-type polysilicon layer containing an n-type dopant (e.g., phosphorus) as a second conductivity type different from the first conductivity type. The silicon substrate 2A includes a silicon oxide film 3. The silicon oxide film 3 is an oxide film located between the first semiconductor region 21A and the n-type polysilicon layer 4 and in contact with both the first semiconductor region 21A and the n-type polysilicon layer 4. The n-type polysilicon layer 4 is a layer produced from the intrinsic crystalline silicon layer 4a and the n-type amorphous silicon layer 4b by performing a heat treatment on the intrinsic crystalline silicon layer 4a, which is a first layer of intrinsic crystalline silicon located on the silicon oxide film 3, and the n-type amorphous silicon layer 4b, which is a second layer of amorphous silicon located on the intrinsic crystalline silicon layer 4a, has a thickness greater than that of the intrinsic crystalline silicon layer 4a, and contains an n-type dopant (e.g., phosphorus). This heat treatment is a process that diffuses the n-type dopant (e.g., phosphorus) contained in the n-type amorphous silicon layer 4b toward the intrinsic crystalline silicon layer 4a and the silicon oxide film 3, while promoting crystallization of the amorphous silicon of the n-type amorphous silicon layer 4b.

[0256] For this reason, it can be said that a solar cell element 1A having either of the above-mentioned structures 5a and 6a has a configuration suitable for a method of manufacturing a solar cell element 1A that can reduce the occurrence of blisters and local defects caused by blisters when the n-type polysilicon layer 4 as the doped polysilicon layer is formed. In other words, it can be said that a solar cell element 1A having either of the above-mentioned structures 5a and 6a has a configuration suitable for a method of manufacturing a solar cell element 1A that can reduce the occurrence of blisters and local defects caused by blisters when the n-type polysilicon layer 4 as the doped polysilicon layer is formed by performing film formation of the n-type amorphous silicon layer 4b as the doped amorphous silicon layer and heat treatment for crystallization of this n-type amorphous silicon layer 4b. In other words, it can be said that a solar cell element 1A having either of the above-mentioned structures 5a and 6a has a configuration suitable for a method of manufacturing a solar cell element 1A that can reduce defects in a solar cell element 1A having an example of a POLO structure formed using a doped amorphous silicon layer. Therefore, by employing the solar cell element 1A having either of the above-described configurations 5a and 6a, defects in the solar cell element 1A having an example of a POLO structure formed using a doped amorphous silicon layer can be reduced. From another perspective, defects in the solar cell element 1A can be easily reduced.

[0257] Each of the samples of the above-described specific examples 2 to 6 was fabricated using a p-type crystalline silicon substrate as the crystalline silicon substrate. Therefore, as shown in the graphs of Figures 21, 22, 25, 26, 29, 30, and 32 to 35, the solar cell element 1A manufactured by the manufacturing method of the solar cell element 1A according to the second embodiment can be an element having either of the following configurations 1a and 2a.

[0258] [Configuration 1a] Solar cell element 1A includes a silicon substrate 2A, a silicon oxide film 3, and an n-type polysilicon layer 4. Silicon substrate 2A has a first semiconductor region 21A as a first region, which is a region of p-type semiconductor as a first conductivity type. Silicon oxide film 3 is an oxide film in contact with first semiconductor region 21A. N-type polysilicon layer 4 is in contact with the surface of silicon oxide film 3 opposite to first semiconductor region 21A and is an n-type polysilicon layer containing phosphorus, which is an n-type dopant as a second conductivity type different from the first conductivity type. N-type polysilicon layer 4 includes a region (oxide film side region) 41 as a second region on the side of silicon oxide film 3 that is in contact with silicon oxide film 3. In this solar cell element 1A, in the region extending from the oxide film-side region 41 through the silicon oxide film 3 to the first semiconductor region 21A, the distribution of the concentration of phosphorus as an n-type dopant in the first thickness direction D1, which is the direction from the surface of the n-type polysilicon layer 4 on the side opposite to the silicon substrate 2A toward the silicon substrate 2A, has a maximum first peak Pk1 and a second peak Pk2. The second peak Pk2 is located at a position 3 nm or more away from the position of the first peak Pk1 in the direction from the first semiconductor region 21A through the silicon oxide film 3 toward the oxide film-side region 41.

[0259] [Configuration 2a] The solar cell element 1A includes a silicon substrate 2A and an n-type polysilicon layer 4. The silicon substrate 2A has a first semiconductor region 21A as a first region, which is a region of a p-type semiconductor as a first conductivity type. The n-type polysilicon layer 4 is in contact with the silicon substrate 2A and is an n-type polysilicon layer containing phosphorus as an n-type dopant as a second conductivity type different from the first conductivity type. The silicon substrate 2A includes a silicon oxide film 3. The silicon oxide film 3 is an oxide film located between the first semiconductor region 21A and the n-type polysilicon layer 4 and in contact with both the first semiconductor region 21A and the n-type polysilicon layer 4. The n-type polysilicon layer 4 includes a region (oxide film side region) 41 as a second region on the side of the silicon oxide film 3 that is in contact with the silicon oxide film 3. In this solar cell element 1A, in the region extending from the oxide film-side region 41 through the silicon oxide film 3 to the first semiconductor region 21A, the distribution of the concentration of phosphorus as an n-type dopant in the first thickness direction D1, which is the direction from the surface of the n-type polysilicon layer 4 on the side opposite to the silicon substrate 2A toward the silicon substrate 2A, has a maximum first peak Pk1 and a second peak Pk2. The second peak Pk2 is located at a position 3 nm or more away from the position of the first peak Pk1 in the direction from the first semiconductor region 21A through the silicon oxide film 3 toward the oxide film-side region 41.

[0260] In other words, solar cell element 1A having either of the above-mentioned configurations 1a and 2a can be said to have a configuration suitable for a method of manufacturing solar cell element 1A that can reduce the occurrence of blisters and local defects caused by blisters when forming n-type polysilicon layer 4 as a doped polysilicon layer. In other words, solar cell element 1A having either of the above-mentioned configurations 1a and 2a can be said to have a configuration suitable for a method of manufacturing solar cell element 1A that can reduce the occurrence of blisters and local defects caused by blisters when forming n-type polysilicon layer 4 as a doped polysilicon layer by performing film formation of n-type amorphous silicon layer 4b as a doped amorphous silicon layer and heat treatment for crystallization of this n-type amorphous silicon layer 4b. In other words, solar cell element 1A having either of the above-mentioned configurations 1a and 2a can be said to have a configuration suitable for a method of manufacturing solar cell element 1A that can reduce defects in solar cell element 1A having an example of a POLO structure formed using a doped amorphous silicon layer. Therefore, by employing the solar cell element 1A having either of the above-described configurations 1a and 2a, defects in the solar cell element 1A having an example of a POLO structure formed using a doped amorphous silicon layer can be reduced. From another perspective, defects in the solar cell element 1A can be easily reduced.

[0261] In each of the above-described configurations 1a and 2a, as in each of the configurations 1 and 2 of the first embodiment, the distribution of the concentration of phosphorus as an n-type dopant in the first thickness direction D1, which is the direction from the surface of the n-type polysilicon layer 4 on the opposite side to the silicon substrate 2A toward the silicon substrate 2A, in the region from the oxide film side region 41 of the n-type polysilicon layer 4 through the silicon oxide film 3 to the first semiconductor region 21A may be the result of measurement using, for example, SIMS.

[0262] Furthermore, in each of the above-described configurations 1a and 2a, as in each of the configurations 1 and 2 of the first embodiment, for example, when the n-type polysilicon layer 4 is equally divided into N regions (N is a natural number equal to or greater than 2) in the first thickness direction D1, the oxide film-side region 41 may be the region closest to the silicon oxide film 3 among the N regions. N may be, for example, two, three, or any number equal to or greater than four. The any number equal to or greater than four may be six. For example, the oxide film-side region 41 may be a region of the n-type polysilicon layer 4 that is 10 nm or less away from the silicon oxide film 3.

[0263] 21 , 22 , 25 , 26 , 29 , 30 , and 32 to 35 , the second peak Pk2 may be located at a position 3 to 10 nm away from the position of the first peak Pk1 in the direction from the first semiconductor region 21A toward the oxide film-side region 41 via the silicon oxide film 3. Here, the second peak Pk2 may be located at a position 3 to 8 nm away from the position of the first peak Pk1, or may be located at a position 3 to 7 nm away from the position of the first peak Pk1 in the direction from the first semiconductor region 21A toward the oxide film-side region 41 via the silicon oxide film 3.

[0264] 37 , solar cell element 1B according to the third embodiment includes an example of a POLO structure according to structure 2 on the surface 1b (back surface) of solar cell element 1B facing the −Z direction. The example of the POLO structure according to structure 2 on the back surface 1b of solar cell element 1B according to the third embodiment has substantially the same configuration as the example of the POLO structure according to structure 2 on the back surface 1b of solar cell element 1A according to the second embodiment. Therefore, the example of the POLO structure according to structure 2 on the back surface 1b of solar cell element 1B according to the third embodiment can be formed by substantially the same method as the example of the POLO structure according to structure 2 on the back surface 1b of solar cell element 1A according to the second embodiment.

[0265] 5-2. Example of configuration and manufacturing method of solar cell element including POLO structure according to structure 3 As shown in FIG. 37 , solar cell element 1B according to the third embodiment includes an example of a TOPCon structure, which is a type of POLO structure according to structure 3, on the surface (front surface) 1f side of solar cell element 1B facing the +Z direction.

[0266] The solar cell element 1B according to the third embodiment is based on the solar cell element 1A according to the second embodiment, but has a configuration in which the silicon substrate 2A is replaced with a silicon substrate 2B, and a silicon oxide film 3B as an oxide film and a p-type polysilicon layer 10B as a polysilicon layer containing a p-type dopant as a first conductivity type are added. The silicon substrate 2B is based on, for example, the silicon substrate 2A according to the second embodiment, and has a configuration in which the entire area is a first semiconductor region 21A. The silicon substrate 2B may be, for example, a crystalline silicon substrate doped with boron or gallium as a p-type dopant. On the first surface 2f side of the silicon substrate 2B, the silicon oxide film 3B, the p-type polysilicon layer 10B, and the second electrode 9 are stacked in this order.

[0267] Here, focusing on the TOPCon structure, which is a type of POLO structure according to the above-described structure 3, on the front surface 1f side of the solar cell element 1B, the solar cell element 1B includes a silicon substrate 2B having a first semiconductor region 21A and a p-type polysilicon layer 10B. Furthermore, the solar cell element 1B may include a silicon oxide film 3B in contact with the first semiconductor region 21A, separate from the silicon substrate 2B. Alternatively, the silicon substrate 2B may include a silicon oxide film 3B located between the first semiconductor region 21A and the p-type polysilicon layer 10B and in contact with both the first semiconductor region 21A and the p-type polysilicon layer 10B. The first semiconductor region 21A is a first region, which is a region of a p-type semiconductor having a first conductivity type, of the silicon substrate 2B. The silicon oxide film 3B may be an oxide film located inside the silicon substrate 2B and along the first surface 2f, or may be an oxide film located on the first surface 2f, which is the surface of the silicon substrate 2B. The p-type polysilicon layer 10B is a p-type polysilicon layer that is in contact with the surface of the silicon oxide film 3B opposite to the first semiconductor region 21A and contains a p-type dopant (e.g., boron) as a first conductivity type. When the silicon oxide film 3B is located inside the silicon substrate 2B and along the surface of the silicon substrate 2B, the p-type polysilicon layer 10B is a polysilicon layer that is in contact with the silicon substrate 2B and contains a p-type dopant as a first conductivity type. In other words, the solar cell element 1B according to the third embodiment includes a structure that is an example of a TOPCon structure that is a type of POLO structure according to the above-described structure 3, in which the first semiconductor region 21A as a p-type first region, the silicon oxide film 3B as an oxide film, and the p-type polysilicon layer 10B as a p-type polysilicon layer are stacked in this order.

[0268] Fig. 39 is a flowchart showing an example of a method for manufacturing solar cell element 1B according to embodiment 3. Here, solar cell element 1B can be manufactured by performing the processes of steps S1B to S9B in Fig. 39 in this order.

[0269] In step S1B, a silicon substrate 2B is prepared, which may be, for example, a crystalline silicon substrate doped with boron or gallium as a p-type dopant.

[0270] In step S2B, a textured structure is formed on the first surface 2f of the silicon substrate 2B. The textured structure can be formed, for example, by wet or dry etching of the first surface 2f of the silicon substrate 2B.

[0271] In step S3B, silicon oxide films are formed on both the first surface 2f side and the second surface 2b side of the silicon substrate 2B. For example, silicon oxide films are formed along the entire surface of the first surface 2f and the entire surface of the second surface 2b of the silicon substrate 2B. More specifically, for example, a silicon oxide film 3 is formed on the second surface 2b side of the silicon substrate 2B, and a silicon oxide film including a portion of the silicon oxide film 3B is formed on the first surface 2f side of the silicon substrate 2B. Therefore, in step S3B, as a first example of the first process, a process of forming the silicon oxide film 3B in contact with the first semiconductor region 21A of the silicon substrate 2B is performed. Also, in step S3B, as a second example of the first process, a process of forming the silicon oxide film 3 in contact with the first semiconductor region 21A of the silicon substrate 2B is performed. Here, for example, on each of the first surface 2f side and the second surface 2b side of the silicon substrate 2B, a silicon oxide film may be formed in a portion located inside the silicon substrate 2B and along the surface of the silicon substrate 2B, or a silicon oxide film may be formed on the surface of the silicon substrate 2B. Here, the silicon oxide film may be formed by one or a combination of two or more of a chemical reaction method, a thermal reaction method, a CVD method, an ALD method, a plasma reaction method, a steam oxidation method, and an ozone oxidation method. The thickness of the silicon oxide film may be set to, for example, 3 nm or less, or 2 nm or less.

[0272] In step S4B, a p-type polysilicon layer 10B is formed on the silicon oxide film 3B, which is a part of the silicon oxide film, on the first surface 2f side of the silicon substrate 2B. In other words, the p-type polysilicon layer 10B is locally formed on a part of the silicon oxide film on the first surface 2f side of the silicon substrate 2B. The local formation of the p-type polysilicon layer 10B can be achieved, for example, by providing a mask. In step S4B, the processes of steps S41B to S43B are performed in this order, thereby forming the p-type polysilicon layer 10B.

[0273] In step S41B, as a first example of the second process, an intrinsic crystalline silicon layer (also referred to as the first layer) is formed on the silicon oxide film 3B. In other words, an intrinsic crystalline silicon layer is locally formed on a portion of the silicon oxide film on the first surface 2f of the silicon substrate 2B. The local formation of the intrinsic crystalline silicon layer can be achieved, for example, by providing a mask. Here, for example, after the intrinsic amorphous silicon layer is formed, the intrinsic amorphous silicon layer is subjected to a heat treatment to promote crystallization of the amorphous silicon, thereby forming the intrinsic crystalline silicon layer. The temperature of this heat treatment is set, for example, within a range of 550°C to 1000°C. The thickness of the intrinsic crystalline silicon layer is set, for example, to 1 nm to 50 nm or less. The intrinsic crystalline silicon layer may be formed by stacking two or more intrinsic polysilicon films.

[0274] In step S42B, as a first example of the third step, a p-type amorphous silicon layer is formed on the intrinsic crystalline silicon layer. The p-type amorphous silicon layer has a thickness greater than that of the intrinsic crystalline silicon layer, and corresponds to an amorphous silicon layer (also referred to as a first second layer) containing a p-type dopant as a first conductivity type. Here, the p-type amorphous silicon layer is formed using, for example, the PECVD method. For example, boron (B) is used as the p-type dopant. The p-type amorphous silicon layer is formed, for example, using monosilane (SiH) as a source gas. ４ ) gas and diborane (B２ H ６ The p-type amorphous silicon layer can be formed by a PECVD method using a p-type amorphous silicon layer having a thickness of, for example, 20 nm to 200 nm.

[0275] In step S43B, as a first example of the fourth step, a process of forming a p-type polysilicon layer 10B by heat treatment is performed. For example, on the first surface 2f side of the silicon substrate 2B, an intrinsic crystalline silicon layer and a p-type amorphous silicon layer stacked on the silicon oxide film 3B are transformed into a p-type polysilicon layer 10B. Here, a heat treatment is performed to promote crystallization of the amorphous silicon of the p-type amorphous silicon layer while diffusing the p-type dopant contained in the p-type amorphous silicon layer toward the intrinsic crystalline silicon layer and the silicon oxide film 3B. This results in a p-type polysilicon layer 10B located on the silicon oxide film 3B and containing the p-type dopant from the intrinsic crystalline silicon layer and the p-type amorphous silicon layer. Here, the heat treatment temperature may be set, for example, within a range of 550°C to 1000°C, 700°C to 1000°C, or 700°C to 900°C.

[0276] In the above-described step S4B, before the p-type amorphous silicon layer serving as the first or second layer of amorphous silicon containing a first conductivity type dopant is formed, an intrinsic crystalline silicon layer having a thickness smaller than that of the p-type amorphous silicon layer is formed on the silicon oxide film 3B. When this intrinsic crystalline silicon layer is formed, even if hydrogen bonded to silicon in the intrinsic amorphous silicon layer is desorbed by a heat treatment for promoting crystallization of the intrinsic amorphous silicon layer, the hydrogen can be released from the surface of the intrinsic amorphous silicon layer opposite the silicon oxide film 3B. This reduces the aggregation of hydrogen gas at the interface between the silicon oxide film 3B and the intrinsic crystalline silicon layer. Furthermore, because the thickness of the intrinsic amorphous silicon layer before being transformed into intrinsic crystalline silicon by the heat treatment is small, the increase in stress that could cause the silicon layer to peel off from the silicon oxide film 3B due to the shrinkage of the silicon layer when the intrinsic amorphous silicon layer is transformed into intrinsic crystalline silicon by the heat treatment can be reduced. These factors can improve adhesion between the silicon oxide film 3B and the intrinsic crystalline silicon layer. As a result, when a heat treatment is performed to promote crystallization of the amorphous silicon in the p-type amorphous silicon layer formed on the intrinsic crystalline silicon layer, the aggregation of hydrogen gas between the silicon oxide film 3B and the intrinsic crystalline silicon layer is reduced, and hydrogen can be released from the surface of the p-type amorphous silicon layer opposite the silicon oxide film 3B and can migrate toward the silicon substrate 2B. This can reduce the occurrence of blisters at the interface between the silicon oxide film 3B and the p-type polysilicon layer 10B. This can also reduce the occurrence of local defects in the p-type polysilicon layer 10B due to these blisters.

[0277] In other words, in the above-described step S4B, when the p-type polysilicon layer 10B is formed on the silicon oxide film 3B, an intrinsic crystalline silicon layer is formed on the silicon oxide film 3B, and then a p-type amorphous silicon layer is formed on the intrinsic crystalline silicon layer, and then the p-type polysilicon layer 10B is produced from the intrinsic crystalline silicon layer and the p-type amorphous silicon layer by heat treatment. This can reduce the occurrence of blisters at the interface between the silicon oxide film 3B and the p-type polysilicon layer 10B, and can also reduce the occurrence of local defects in the p-type polysilicon layer 10B due to the blisters.

[0278] This reduces the occurrence of blisters and local defects due to blisters when forming the p-type polysilicon layer 10B as a doped polysilicon layer using a PECVD method or the like. In other words, defects can be reduced in the solar cell element 1B having an example of a TOPCon structure, which is a type of POLO structure, formed using a doped amorphous silicon layer. From another perspective, defects in the solar cell element 1B can be easily reduced. Furthermore, in the solar cell element 1B according to the third embodiment, the reduction in the area where the TOPCon structure, which is a type of POLO structure according to the above-described structure 3, exists on the surface of the silicon substrate 2B can be reduced. This reduces the degradation of passivation performance due to the TOPCon structure, which is a type of POLO structure, in the solar cell element 1B according to the third embodiment. As a result, the conversion efficiency of the solar cell element 1B can be easily improved.

[0279] In step S5B, an etching process is performed on the first surface 2f side of the silicon substrate 2B, thereby removing the remaining portion of the silicon oxide film on the first surface 2f side of the silicon substrate 2B except for the silicon oxide film 3B covered with the p-type polysilicon layer 10B, thereby making the silicon oxide film 3B visible.

[0280] In step S6B, an n-type polysilicon layer 4 is formed on the silicon oxide film 3. In step S6B, for example, the process of step S5 in the first embodiment is used as a basis, but the silicon substrate 2 and the first semiconductor region 21 are changed to a silicon substrate 2B and a first semiconductor region 21A. More specifically, in step S6B, the processes of steps S51 to S53 in the first embodiment are used as a basis, but the processes of steps S61B to S63B are used as a basis, but the silicon substrate 2 and the first semiconductor region 21 are changed to a silicon substrate 2B and a first semiconductor region 21A. In step S61B, as a second example of the second step, an intrinsic crystalline silicon layer 4a is formed on the silicon oxide film 3 as an intrinsic crystalline silicon layer (also referred to as a second first layer). In step S62B, as a second example of the third step, an n-type amorphous silicon layer 4b is formed on the intrinsic crystalline silicon layer 4a as an amorphous silicon layer (also referred to as a second layer) having a thickness greater than that of the intrinsic crystalline silicon layer 4a and containing an n-type dopant as a dopant of the first conductivity type. In step S63B, as a second example of the fourth step, an n-type polysilicon layer 4 is formed by heat treatment.

[0281] In step S6B, similarly to step S5 of the first embodiment, for example, when the n-type polysilicon layer 4 is formed on the silicon oxide film 3, an intrinsic crystalline silicon layer 4a is formed on the silicon oxide film 3, an n-type amorphous silicon layer 4b is further formed on the intrinsic crystalline silicon layer 4a, and then the n-type polysilicon layer 4 is generated from the intrinsic crystalline silicon layer 4a and the n-type amorphous silicon layer 4b by heat treatment. This reduces the occurrence of blisters at the interface between the silicon oxide film 3 and the n-type polysilicon layer 4 and reduces the occurrence of local defects in the n-type polysilicon layer 4 due to the blisters. Therefore, the occurrence of blisters and local defects due to the blisters when the n-type polysilicon layer 4 is formed as a doped polysilicon layer using a PECVD method or the like can be reduced. In other words, defects can be reduced in the solar cell element 1B having an example of the POLO structure according to the above-described structure 2, which is formed using a doped amorphous silicon layer. From another perspective, defects in the solar cell element 1B can be easily reduced.

[0282] In step S7B, a passivation film 7 is formed on the first surface 2f of the silicon substrate 2B. For example, the passivation film 7 is formed over the entire surface of the first surface 2f of the silicon substrate 2B. Here, for example, an aluminum oxide layer may be formed as the passivation film 7 by the ALD method, or a silicon oxide layer may be formed as the passivation film 7 by the PECVD method.

[0283] In step S8B, anti-reflection films are formed on each of the first surface 2f and the second surface 2b of the silicon substrate 2B. For example, a first anti-reflection film 5 is formed over the entire surface of the n-type polysilicon layer 4 on the side opposite to the silicon substrate 2B, and a second anti-reflection film 8 is formed over the entire surface of the passivation film 7 on the side opposite to the silicon substrate 2B. Here, for example, a silicon nitride layer may be formed as the anti-reflection film by the PECVD method.

[0284] In step S9B, electrodes are formed on the first surface 2f and the second surface 2b of the silicon substrate 2B. For example, a first electrode 6 is formed on the second surface 2b of the silicon substrate 2B, and a second electrode 9 is formed on the first surface 2f of the silicon substrate 2B. Here, for example, a first metal paste may be applied to the first anti-reflection film 5 by screen printing or the like, and then fired to form the first electrode 6. Alternatively, a second metal paste may be applied to the second anti-reflection film 8 by screen printing or the like, and then fired to form the second electrode 9. For example, if the first metal paste contains a metal powder, an organic vehicle, and a glass frit, the glass frit in the first metal paste melts during firing of the first metal paste, causing a firing penetration of the first anti-reflection film 5. As a result, the first electrode 6 penetrates the first anti-reflection film 5 and is connected to the n-type polysilicon layer 4. For example, if the second metal paste contains metal powder, an organic vehicle, and glass frit, when the second metal paste is fired, the glass frit in the second metal paste melts, causing firing penetration of the second anti-reflection film 8 and the passivation film 7. As a result, the second electrode 9 penetrates the second anti-reflection film 8 and the passivation film 7 and is connected to the p-type polysilicon layer 10B.

[0285] In this manner, the solar cell element 1B having the configuration shown in FIG. 37 can be manufactured.

[0286] As described above, an example of the TOPCon structure, which is a type of POLO structure according to the structure 3 in the solar cell element 1B according to the third embodiment, can be formed by processing in accordance with steps S3B and S4B of the flowchart in Fig. 39. More specifically, for example, an example of the TOPCon structure, which is a type of POLO structure according to the structure 3 in the solar cell element 1B according to the third embodiment, can be formed by a manufacturing method for the solar cell element 1B including the following steps 1b, 2b, 3b, and 4b.

[0287] [Step 1b] A silicon oxide film including a silicon oxide film 3B as an oxide film in contact with a first semiconductor region 21A is formed on a portion of a silicon substrate 2B as a crystalline silicon substrate, the portion being located inside the silicon substrate 2B and along the surface of the silicon substrate 2B or on the surface of the silicon substrate 2B. The silicon oxide film 3B is an oxide film in contact with the first semiconductor region 21A, which is a region of a p-type semiconductor as a first conductivity type.

[0288] [Step 2b] An intrinsic crystalline silicon layer is formed on the silicon oxide film 3B as a first layer (first first layer) of intrinsic crystalline silicon.

[0289] [Step 3b] A p-type amorphous silicon layer is formed on the intrinsic crystalline silicon layer as a second layer (first second layer) of amorphous silicon having a thickness greater than that of the intrinsic crystalline silicon layer and containing a p-type dopant (e.g., boron) as the first conductivity type. The p-type amorphous silicon layer may be formed using, for example, a PECVD method.

[0290] [Step 4b] A heat treatment is performed to promote crystallization of the amorphous silicon of the p-type amorphous silicon layer while diffusing the p-type dopant (e.g., boron) contained in the p-type amorphous silicon layer toward the intrinsic crystalline silicon layer and silicon oxide film 3B, thereby producing a p-type polysilicon layer 10B from the intrinsic crystalline silicon layer and p-type amorphous silicon layer, which is located on silicon oxide film 3B and contains the p-type dopant (e.g., boron).

[0291] The above-mentioned step 1b is an example of the first step of the present disclosure. The above-mentioned step 2b is an example of the second step of the present disclosure. The above-mentioned step 3b is an example of the third step of the present disclosure. The above-mentioned step 4b is an example of the fourth step of the present disclosure.

[0292] According to the manufacturing method of solar cell element 1B including steps 1b, 2b, 3b, and 4b, an intrinsic crystalline silicon layer is formed on silicon oxide film 3B, thereby improving adhesion between silicon oxide film 3B and the intrinsic crystalline silicon layer. Furthermore, after a p-type amorphous silicon layer is formed on the intrinsic crystalline silicon layer, when the intrinsic crystalline silicon layer and the p-type amorphous silicon layer are transformed into p-type polysilicon layer 10B as a doped polysilicon layer by heat treatment, adhesion at the interface between silicon oxide film 3B and p-type polysilicon layer 10B can be ensured. This reduces the occurrence of blisters and local defects caused by blisters when forming p-type polysilicon layer 10B as a doped polysilicon layer. In other words, defects can be reduced in solar cell element 1B having an example of a TOPCon structure, which is a type of POLO structure formed using a doped amorphous silicon layer. From another perspective, defects in solar cell element 1B can be easily reduced.

[0293] Incidentally, the solar cell element 1B manufactured by the manufacturing method of the solar cell element 1B of the third embodiment in which the above steps 1b to 4b are executed can be said to be an element having either of the following configurations 5b and 6b.

[0294] [Configuration 5b] Solar cell element 1B includes a silicon substrate 2B, a silicon oxide film 3B, and a p-type polysilicon layer 10B. Silicon substrate 2B has a first semiconductor region 21A as a first region, which is a region of p-type semiconductor as a first conductivity type. Silicon oxide film 3B is an oxide film in contact with first semiconductor region 21A. P-type polysilicon layer 10B is in contact with a surface of silicon oxide film 3B opposite to first semiconductor region 21A and is a p-type polysilicon layer containing a p-type dopant (e.g., boron) as a first conductivity type. The p-type polysilicon layer 10B is formed by heat treatment of the intrinsic crystalline silicon layer, which is a first layer of intrinsic crystalline silicon located on the silicon oxide film 3B, and the p-type amorphous silicon layer, which is a second layer of amorphous silicon located on the intrinsic crystalline silicon layer, has a thickness greater than that of the intrinsic crystalline silicon layer, and contains a p-type dopant (e.g., boron). This heat treatment diffuses the p-type dopant (e.g., boron) contained in the p-type amorphous silicon layer toward the intrinsic crystalline silicon layer and the silicon oxide film 3B, thereby promoting crystallization of the amorphous silicon of the p-type amorphous silicon layer.

[0295] [Configuration 6b] Solar cell element 1B includes a silicon substrate 2B and a p-type polysilicon layer 10B. Silicon substrate 2B has a first semiconductor region 21A as a first region, which is a region of p-type semiconductor as a first conductivity type. P-type polysilicon layer 10B is in contact with silicon substrate 2B and is a p-type polysilicon layer containing a p-type dopant (e.g., boron). Silicon substrate 2B includes a silicon oxide film 3B. Silicon oxide film 3B is an oxide film located between first semiconductor region 21A and p-type polysilicon layer 10B and in contact with both first semiconductor region 21A and p-type polysilicon layer 10B. The p-type polysilicon layer 10B is formed by heat treatment of the intrinsic crystalline silicon layer, which is a first layer of intrinsic crystalline silicon located on the silicon oxide film 3B, and the p-type amorphous silicon layer, which is a second layer of amorphous silicon located on the intrinsic crystalline silicon layer, has a thickness greater than that of the intrinsic crystalline silicon layer, and contains a p-type dopant (e.g., boron). This heat treatment diffuses the p-type dopant (e.g., boron) contained in the p-type amorphous silicon layer toward the intrinsic crystalline silicon layer and the silicon oxide film 3B, thereby promoting crystallization of the amorphous silicon of the p-type amorphous silicon layer.

[0296] For this reason, solar cell element 1B having any of the above-described structures 5b and 6b can be said to have a configuration suitable for a method of manufacturing solar cell element 1B that can reduce the occurrence of blisters and local defects caused by blisters when p-type polysilicon layer 10B is formed as a doped polysilicon layer. In other words, solar cell element 1B having any of the above-described structures 5b and 6b can be said to have a configuration suitable for a method of manufacturing solar cell element 1B that can reduce the occurrence of blisters and local defects caused by blisters when p-type polysilicon layer 10B is formed as a doped polysilicon layer by undergoing deposition of a p-type amorphous silicon layer as a doped amorphous silicon layer and heat treatment for crystallization of this p-type amorphous silicon layer. In other words, solar cell element 1B having any of the above-described structures 5b and 6b can be said to have a configuration suitable for a method of manufacturing solar cell element 1B that can reduce defects in solar cell element 1B having an example of a TOPCon structure, which is a type of POLO structure, formed using a doped amorphous silicon layer. Therefore, by employing solar cell element 1B having either of the above-described configurations 5b and 6b, defects in solar cell element 1B having an example of a TOPCon structure, which is a type of POLO structure formed using a doped amorphous silicon layer, can be reduced. From another perspective, defects in solar cell element 1B can be easily reduced.

[0297] Incidentally, in the manufacturing method of the solar cell element 1 according to the first embodiment, when forming an example of a TOPCon structure, which is a type of POLO structure according to the above-mentioned structure 1, as described above, an intrinsic crystalline silicon layer is formed on a silicon oxide film, and then an n-type amorphous silicon layer is formed on the intrinsic crystalline silicon layer, and then an n-type polysilicon layer 4 is generated from the intrinsic crystalline silicon layer and the n-type amorphous silicon layer by heat treatment.

[0298] Furthermore, in the manufacturing method of the solar cell element 1A according to the second embodiment, when forming an example of the POLO structure according to the structure 2, as described above, an intrinsic crystalline silicon layer is formed on a silicon oxide film, and then an n-type amorphous silicon layer is formed on the intrinsic crystalline silicon layer, and then an n-type polysilicon layer 4 is generated from the intrinsic crystalline silicon layer and the n-type amorphous silicon layer by heat treatment.

[0299] In contrast, in the manufacturing method of the solar cell element 1B according to the third embodiment, when forming an example of a TOPCon structure, which is a type of POLO structure according to the above-mentioned structure 3, as described above, an intrinsic crystalline silicon layer is formed on a silicon oxide film, and then a p-type amorphous silicon layer is formed on the intrinsic crystalline silicon layer, and then a p-type polysilicon layer 10B is generated from the intrinsic crystalline silicon layer and the p-type amorphous silicon layer by heat treatment.

[0300] In other words, the method for forming an example of a TOPCon structure, which is a type of POLO structure relating to structure 1 in the first embodiment, the method for forming an example of a POLO structure relating to structure 2 in the second embodiment, and the method for forming an example of a TOPCon structure, which is a type of POLO structure relating to structure 3 in the third embodiment are methods based on substantially the same technical concept, except for the slight difference in the conductivity type of the dopant between n-type and p-type.

[0301] For this reason, the distribution of p-type dopant concentration in the TOPCon structure, which is a type of POLO structure according to Structure 3 of solar cell element 1B manufactured by the manufacturing method for solar cell element 1B according to the third embodiment including steps 1b to 4b, and the distribution of n-type dopant concentration in the TOPCon structure, which is a type of POLO structure according to Structure 1 of solar cell element 1 manufactured by the manufacturing method for solar cell element 1 according to the first embodiment including steps 1 to 4, can show the same tendency due to the same mechanism. Furthermore, the distribution of p-type dopant concentration in the TOPCon structure, which is a type of POLO structure according to Structure 3 of solar cell element 1B manufactured by the manufacturing method for solar cell element 1B according to the third embodiment including steps 1b to 4b, and the distribution of n-type dopant concentration in the POLO structure according to Structure 2 of solar cell element 1A manufactured by the manufacturing method for solar cell element 1A according to the second embodiment including steps 1a to 4a can show the same tendency due to the same mechanism.

[0302] Therefore, the solar cell element 1B manufactured by the manufacturing method of the solar cell element 1B according to the third embodiment can be an element having either of the following configurations 1b and 2b.

[0303] [Configuration 1b] Solar cell element 1B includes a silicon substrate 2B, a silicon oxide film 3B, and a p-type polysilicon layer 10B. Silicon substrate 2B has a first semiconductor region 21A as a first region, which is a region of p-type semiconductor as a first conductivity type. Silicon oxide film 3B is an oxide film in contact with first semiconductor region 21A. P-type polysilicon layer 10B is in contact with the surface of silicon oxide film 3B opposite to first semiconductor region 21A and is a p-type polysilicon layer containing a p-type dopant (e.g., boron) as a first conductivity type. The p-type polysilicon layer includes a region (oxide film side region) 10B1 as a second region on the side of silicon oxide film 3B that is in contact with silicon oxide film 3B. In this solar cell element 1B, in the region extending from oxide film-side region 10B1 through silicon oxide film 3B to first semiconductor region 21A, the distribution of the concentration of p-type dopant (e.g., boron) in the second thickness direction, which is the direction from the surface of p-type polysilicon layer 10B opposite silicon substrate 2B toward silicon substrate 2B, has a maximum first peak and a second peak. The second peak is located at a position 3 nm or more away from the position of the first peak in the direction from first semiconductor region 21A through silicon oxide film 3B toward oxide film-side region 10B1.

[0304] [Configuration 2b] Solar cell element 1B includes a silicon substrate 2B and a p-type polysilicon layer 10B. Silicon substrate 2B has a first semiconductor region 21A as a first region, which is a region of a p-type semiconductor having a first conductivity type. P-type polysilicon layer 10B is a p-type polysilicon layer that is in contact with silicon substrate 2B and contains a p-type dopant (e.g., boron). Silicon substrate 2B includes a silicon oxide film 3B. Silicon oxide film 3B is an oxide film that is located between first semiconductor region 21A and p-type polysilicon layer 10B and is in contact with both first semiconductor region 21A and p-type polysilicon layer 10B. P-type polysilicon layer 10B includes a region (oxide film side region) 10B1 as a second region on the side of silicon oxide film 3B that is in contact with silicon oxide film 3B. In this solar cell element 1B, in the region extending from oxide film-side region 10B1 through silicon oxide film 3B to first semiconductor region 21A, the distribution of the concentration of p-type dopant (e.g., boron) in the second thickness direction, which is the direction from the surface of p-type polysilicon layer 10B opposite silicon substrate 2B toward silicon substrate 2B, has a maximum first peak and a second peak. The second peak is located at a position 3 nm or more away from the position of the first peak in the direction from first semiconductor region 21A through silicon oxide film 3B toward oxide film-side region 10B1.

[0305] In other words, solar cell element 1B having either of the above-mentioned configurations 1b and 2b can be said to have a configuration suitable for a method of manufacturing solar cell element 1B that can reduce the occurrence of blisters and local defects caused by blisters when p-type polysilicon layer 10B is formed as a doped polysilicon layer. In other words, solar cell element 1B having either of the above-mentioned configurations 1b and 2b can be said to have a configuration suitable for a method of manufacturing solar cell element 1B that can reduce the occurrence of blisters and local defects caused by blisters when p-type polysilicon layer 10B is formed as a doped polysilicon layer by undergoing deposition of a p-type amorphous silicon layer as a doped amorphous silicon layer and heat treatment for crystallization of this p-type amorphous silicon layer. In other words, solar cell element 1B having either of the above-mentioned configurations 1b and 2b can be said to have a configuration suitable for a method of manufacturing solar cell element 1B that can reduce defects in solar cell element 1B having an example of a TOPCon structure, which is a type of POLO structure, formed using a doped amorphous silicon layer. Therefore, by employing solar cell element 1B having either of the above-described configurations 1b and 2b, defects in solar cell element 1B having an example of a TOPCon structure, which is a type of POLO structure formed using a doped amorphous silicon layer, can be reduced. From another perspective, defects in solar cell element 1B can be easily reduced.

[0306] In each of the above-described configurations 1b and 2b, as in the configurations 1 and 2 of the first embodiment and the configurations 1a and 2a of the second embodiment, the distribution of the concentration of a p-type dopant (e.g., boron) in the second thickness direction, which is the direction from the surface of the p-type polysilicon layer 10B on the opposite side from the silicon substrate 2B toward the silicon substrate 2B, in the region from the oxide film side region 10B1 of the p-type polysilicon layer 10B through the silicon oxide film 3B to the first semiconductor region 21A, may be the result of measurement using, for example, SIMS.

[0307] When identifying characteristics of the distribution of the concentration of a specific p-type dopant in the second direction for various samples of the solar cell element of the present disclosure, minute increases and decreases in the distribution of the concentration of the specific p-type dopant in the second direction that occur during SIMS measurement may be treated as noise components that do not exhibit characteristics corresponding to actual changes in the concentration of the specific p-type dopant. Here, the second direction is the direction from the surface of the p-type polysilicon layer opposite the substrate toward the substrate. This second direction may be a direction along the thickness directions of the p-type polysilicon layer, the silicon oxide film, and the substrate. The specific p-type dopant may refer to a specific type of element among the p-type dopants. For example, boron is used as this specific type of element.

[0308] Here, a method for recognizing the characteristics of the distribution of the concentration of a specific p-type dopant (e.g., boron) in a second direction of a sample, taking noise components into consideration, may be based on an example of the first recognition method described above, in which the specific n-type dopant is replaced with a specific p-type dopant (also referred to as a 1A recognition method). Specifically, in the 1A recognition method, the following four processes may be performed in this order: [1A] calculation of an index related to the noise component; [2A] calculation of an approximation line; [3A] calculation of a judgment line; and [4A] peak recognition, to recognize the characteristics of the distribution of the concentration of a specific p-type dopant in a second direction of a sample.

[0309] SIMS measures the concentration of a specific p-type dopant (e.g., boron) while drilling the surface of a sample in a second direction, thereby obtaining data on the distribution of the concentration of the specific p-type dopant in the second direction of the sample. More specifically, SIMS sequentially measures the concentration of the specific p-type dopant at a plurality of discrete positions in the second direction of the sample, thereby obtaining data on the distribution of the concentration of the specific p-type dopant in the second direction of the sample. These discrete positions are positions (measurement positions) arranged in order in the second direction of the sample, from first to Mth (M is a natural number), at which the concentration of the specific p-type dopant is measured. Therefore, the discrete positions are the first measurement position, second measurement position, third measurement position, ..., Mth measurement position arranged in order in the second direction of the sample. Therefore, the concentration of a specific p-type dopant measured sequentially at the first to Mth measurement positions in the second direction of a single sample using SIMS is the concentration of the specific p-type dopant measured sequentially from the first to Mth positions in the single sample. In other words, data indicating the distribution of the concentration of a specific p-type dopant in the second direction of a single sample obtained using SIMS is composed of data on the concentration of the specific p-type dopant measured sequentially from the first to Mth positions in the second direction of a single sample. Therefore, in the following description, with regard to the distribution of the concentration of a specific p-type dopant in the second direction of a single sample, of the M concentrations of specific p-type dopants measured sequentially from the first to Mth positions in the second direction of a single sample, the concentration of the specific p-type dopant measured at the nth position (n is an integer) and the concentration of the specific p-type dopant measured at the (n+1)th position are considered to be the concentrations of two specific p-type dopants adjacent to each other in the second direction.

[0310] <<[1A] Calculation of an Index Related to a Noise Component>> First, for the distribution of the concentration of a specific p-type dopant in the second direction of the sample, a distribution of the absolute value of the difference between the concentrations of two adjacent specific p-type dopants in the second direction (also referred to as the Δp-type dopant concentration) is calculated. Here, if the specific p-type dopant is boron, the Δp-type dopant concentration is the absolute value of the difference between the concentrations of two adjacent boron dopants in the second direction (also referred to as the Δboron concentration). Here, for the concentration of the specific p-type dopant measured at the nth point (n is an integer) in the distribution of the concentration of the specific p-type dopant in the second direction of the sample, ΔD2(n) is calculated using Formula (1A).

[0311] ΔD2(n)=|D2(n+1)−D2(n)|...(1A).

[0312] In Equation (1A), D2(n) denotes the concentration of the specific p-type dopant measured at the nth measurement in the distribution of the concentration of the specific p-type dopant in the second direction of the sample. D2(n+1) denotes the concentration of the p-type dopant measured at the n+1th measurement in the distribution of the concentration of the specific p-type dopant in the second direction of the sample. In other words, the absolute value of the difference between the concentration of the specific p-type dopant measured at the n+1th measurement and the concentration of the specific p-type dopant measured at the nth measurement in the distribution of the concentration of the specific p-type dopant in the second direction of the sample is calculated as the Δp-type dopant concentration related to the concentration of the specific p-type dopant measured at the nth measurement.

[0313] Here, when the specific p-type dopant is boron, ΔB(n) as the Δ boron concentration is calculated by equation (2A).

[0314] ΔB(n)=|B(n+1)−B(n)|...(2A).

[0315] In equation (2A), B(n) represents the nth measured boron concentration in the distribution of boron concentration in the second direction of the sample. B(n+1) represents the n+1th measured boron concentration in the distribution of boron concentration in the second direction of the sample. In other words, the absolute value of the difference between the n+1th measured boron concentration and the nth measured boron concentration in the distribution of boron concentration in the second direction of the sample is calculated as the Δ boron concentration related to the nth measured boron concentration.

[0316] In the distribution of the Δp-type dopant concentration (e.g., Δboron concentration) in the second direction of the sample, a portion where the Δp-type dopant concentration undulates finely around zero (0) is presumed to indicate variations in measurement values ​​corresponding to noise components in the distribution of the concentration of a specific p-type dopant (e.g., boron) in the second direction of the sample. Therefore, for the sample, a base region (base region) is set in a portion of the second direction from the silicon oxide film side region of the p-type polysilicon layer through the silicon oxide film to the semiconductor region of the substrate in the second direction, where the Δp-type dopant concentration undulates finely around zero (0). In this case, in the direction away from the silicon substrate, which is the opposite direction to the second direction, the region from the position of the first distance to the position of the second distance is set as the base region, using the maximum peak (first peak) as a reference. The first distance may be set to, for example, 8 nm to 10 nm. The second distance may be set to, for example, 15 nm to 25 nm. The second distance may be set according to, for example, the thickness of the p-type polysilicon layer. For example, the second distance may be set to half or less of the thickness of the p-type polysilicon layer. For example, if the thickness of the p-type polysilicon layer is 60 nm, the second distance may be set to 30 nm or less. For example, if the thickness of the p-type polysilicon layer is 30 nm, the second distance may be set to 15 nm or less. Then, among the distribution of the Δp-type dopant concentration in the second direction of the sample, the standard deviation σ of the Δp-type dopant concentration in the base region is calculated as an index (first A index) related to the noise component of the distribution of the concentration of a specific p-type dopant (e.g., boron) in the second direction of the sample.

[0317] <<[2A] Calculation of Approximation Line>> A line of a function (approximation function) approximating the concentration distribution of a specific p-type dopant (e.g., boron) in the base region in the second direction of the sample is calculated. Here, the line of the approximation function is calculated as a line (approximation line) extended in the second direction of the sample so as to exist not only in the base region but also in regions other than the base region. Here, an example of the region other than the base region may be the region from the base region in the second direction of the sample to the position showing the first peak. An example of the region including the base region and regions other than the base region in the second direction of the sample may be, for example, a region from the region of the p-type polysilicon layer on the silicon oxide film side in the second direction, through the silicon oxide film, to the semiconductor region of the substrate. An example of the line of the approximation function may be a straight line of a linear function calculated by the least squares method. In this case, the approximation line is a straight line of a linear function. An example of the line of the approximation function may be a curved line of a quadratic function calculated by the least squares method. In this case, the approximation line is a curved line of a quadratic function.

[0318] <<[3A] Calculation of the Judgment Line>> The approximation line that approximates the distribution of the concentration of a specific p-type dopant (e.g., boron) in the base region in the second direction of the sample is used as a reference, and a value m times the standard deviation σ (m is a value between 3 and 4) is added as the 1A index to each concentration of the specific p-type dopant on the approximation line to calculate a line (also referred to as a judgment line) obtained by shifting the approximation line. Here, if the approximation line is a straight line of a linear function, the judgment line will also be a straight line of a linear function. For example, if the approximation line is a curved line of a quadratic function, the judgment line will also be a curved line of a quadratic function.

[0319] <<[4A] Peak Recognition>> In the second direction, in a region extending from the silicon oxide film side of the p-type polysilicon layer through the silicon oxide film to the semiconductor region of the substrate, a significant peak of the specific p-type dopant concentration is recognized in a portion of the distribution of the specific p-type dopant concentration in the second direction of the sample where the specific p-type dopant concentration exceeds the judgment line in three or more consecutive data points in the second direction. Here, instead of a portion of the distribution of the specific p-type dopant concentration in the second direction of the sample where the specific p-type dopant concentration exceeds the judgment line in three or more consecutive data points in the second direction, a significant peak of the specific p-type dopant concentration may be recognized in a portion of the distribution of the specific p-type dopant concentration in the second direction where the specific p-type dopant concentration continues to exceed the judgment line over a range of at least a predetermined length in the second direction. The predetermined length may be set to, for example, 1 nm, 1.5 nm, or 2 nm.

[0320] Furthermore, in each of the above-described configurations 1b and 2b, as in the configurations 1a and 2a of the above-described second embodiment, the oxide film-side region 10B1 may be, for example, a region of the N regions closest to the silicon oxide film 3B when the p-type polysilicon layer 10B is equally divided into N regions (N is a natural number equal to or greater than 2) in the second thickness direction. N may be, for example, two, three, or any number equal to or greater than four. The number equal to or greater than four may be six. For example, the oxide film-side region 10B1 may be a region of the p-type polysilicon layer 10B that is 10 nm or less away from the silicon oxide film 3B.

[0321] Furthermore, in each of the above-described configurations 1b and 2b, as in the configurations 1 and 2 of the first embodiment and the configurations 1a and 2a of the second embodiment, the second peak may be located at a position 3 to 10 nm away from the position of the first peak in the direction from the first semiconductor region 21A through the silicon oxide film 3B toward the oxide film-side region 10B1. Here, the second peak may be located at a position 3 to 8 nm away from the position of the first peak, or at a position 3 to 7 nm away from the position of the first peak, in the direction from the first semiconductor region 21A through the silicon oxide film 3B toward the oxide film-side region 10B1.

[0322] <5-3. Examples of configuration and manufacturing method of solar cell element including POLO structure according to structure 4> Fig. 40 is a cross-sectional view schematically showing an example of the configuration of solar cell element 1C according to embodiment 4. Fig. 41 is a cross-sectional view schematically showing an example of the configuration of solar cell element 1D according to embodiment 5.

[0323] As shown in Figure 40, the solar cell element 1C of the fourth embodiment includes, for example, an example of a POLO structure related to the above structure 4 on the surface (back surface) 1b side facing the -Z direction of the solar cell element 1C.

[0324] The solar cell element 1C of the fourth embodiment is based on the solar cell element 1 of the first embodiment, and has a configuration in which the silicon substrate 2 is changed to a silicon substrate 2C, the n-type polysilicon layer 4 is changed to a p-type polysilicon layer 10C, the passivation film 7 is removed, and a passivation film 7C is added.

[0325] The silicon substrate 2C has a first semiconductor region 21 and a second semiconductor region 22C. In other words, the silicon substrate 2C is based on the silicon substrate 2 according to the first embodiment, with the second semiconductor region 22 replaced by the second semiconductor region 22C. The first semiconductor region 21 and the second semiconductor region 22C are each an n-type semiconductor region having a first conductivity type. The n-type dopant concentration in the second semiconductor region 22C is higher than the n-type dopant concentration in the first semiconductor region 21. The second anti-reflection film 8 is positioned so as to cover substantially the entire first surface 2f of the silicon substrate 2C except for the region where the second electrode 9 is located. In other words, the second anti-reflection film 8 is in contact with the second semiconductor region 22C of the silicon substrate 2C. The passivation film 7C is positioned on the p-type polysilicon layer 10C. More specifically, the passivation film 7C is located on the surface of the p-type polysilicon layer 10C opposite to the silicon substrate 2C. The passivation film 7C may be, for example, an aluminum oxide layer or a silicon oxide layer. The first anti-reflection film 5 is located on the passivation film 7C.

[0326] Therefore, the solar cell element 1C according to the fourth embodiment includes a silicon substrate 2C having a first semiconductor region 21 and a p-type polysilicon layer 10C. Furthermore, the solar cell element 1C may include a silicon oxide film 3 in contact with the first semiconductor region 21, separate from the silicon substrate 2C. Alternatively, the silicon substrate 2C may include a silicon oxide film 3 located between the first semiconductor region 21 and the p-type polysilicon layer 10C and in contact with both the first semiconductor region 21 and the p-type polysilicon layer 10C. The first semiconductor region 21 is a first region of the silicon substrate 2C as a substrate, which is an n-type semiconductor region having a first conductivity type. The silicon oxide film 3 may be an oxide film located inside the silicon substrate 2C and along the second surface 2b, or may be an oxide film located on the second surface 2b as the surface of the silicon substrate 2C. The p-type polysilicon layer 10C is a p-type polysilicon layer that is in contact with the surface of the silicon oxide film 3 opposite the first semiconductor region 21 and that contains a p-type dopant (e.g., boron) as a second conductivity type different from the first conductivity type. When the silicon oxide film 3 is located inside the silicon substrate 2C and along the surface of the silicon substrate 2C, the p-type polysilicon layer 10C is a polysilicon layer that is in contact with the silicon substrate 2C and that contains a p-type dopant as a second conductivity type. In other words, the solar cell element 1C according to the fourth embodiment includes a structure, as an example of the POLO structure according to the above-described structure 4, in which the first semiconductor region 21 as an n-type first region, the silicon oxide film 3 as an oxide film, and the p-type polysilicon layer 10C as a p-type polysilicon layer are stacked in this order.

[0327] The solar cell element 1C of the fourth embodiment can be manufactured, for example, by a manufacturing method that is based on the manufacturing method of the solar cell element 1 of the first embodiment shown in the flowchart of Figure 3, but with some modifications to this manufacturing method.

[0328] 3, for example, instead of forming the second semiconductor region 22, a second semiconductor region 22C is formed. Here, for example, an n-type dopant such as phosphorus is introduced into a portion located inside the n-type silicon substrate 2C and along the first surface 2f, thereby forming the second semiconductor region 22C. The introduction of the n-type dopant can be performed, for example, by introducing gaseous phosphorus oxychloride (POCl ３ ) as the diffusion source, or a paste of diphosphorus pentoxide (P ２ O ５ This method may be performed using a coating thermal diffusion method in which a phosphorus-containing film (e.g., a silicon nitride film) is coated on the first surface 2f of the silicon substrate 2C and the phosphorus is thermally diffused. Here, for example, if an n-type dopant is introduced into a portion located inside the silicon substrate 2C and along the second surface 2b, the portion located inside the silicon substrate 2C and along the second surface 2b is removed by etching using an aqueous solution of hydrofluoric nitric acid or the like. If phosphorus glass is formed on the first surface 2f of the silicon substrate 2C, the phosphorus glass is removed by etching using an aqueous solution containing hydrofluoric acid or the like. Here, a diffusion mask may be formed in advance, and the diffusion mask may be removed after the second semiconductor region 22C is formed.

[0329] 3, a process is performed in which the silicon substrate 2 is changed to a silicon substrate 2C. In this changed step S4, a step of forming a silicon oxide film 3 in contact with the first semiconductor region 21 of the silicon substrate 2C is performed as an example of a first process. Here, the silicon oxide film 3 may be formed in a portion located inside the silicon substrate 2C and along the surface of the silicon substrate 2C, or the silicon oxide film 3 may be formed on the surface of the silicon substrate 2C.

[0330] 3, a p-type polysilicon layer 10C is formed on the silicon oxide film 3 in place of the n-type polysilicon layer 4. Here, the processes of steps S51 to S53 of the first embodiment are slightly modified and are performed in the order described above, thereby forming the p-type polysilicon layer 10C.

[0331] More specifically, in step S51, as an example of a second process, an intrinsic crystalline silicon layer is formed on the silicon oxide film 3 as a layer (first layer) of intrinsic crystalline silicon corresponding to the intrinsic crystalline silicon layer 4a. For example, the intrinsic crystalline silicon layer is formed on the surface of the silicon oxide film 3 opposite the first semiconductor region 21. The intrinsic crystalline silicon layer may be, for example, an intrinsic polycrystalline silicon layer. Here, for example, after the intrinsic amorphous silicon layer is formed, the intrinsic amorphous silicon layer is subjected to a heat treatment to promote crystallization of the amorphous silicon, thereby forming the intrinsic crystalline silicon layer. The temperature of this heat treatment is set, for example, within a range of 550°C to 1000°C. For example, after the intrinsic crystalline silicon layer is formed, the oxide films on the surfaces of the second semiconductor region 22C of the silicon substrate 2C and the intrinsic crystalline silicon layer formed thereon may be removed using an aqueous solution containing hydrofluoric acid. The thickness of the intrinsic crystalline silicon layer is set to, for example, 1 nm to 50 nm or less. The intrinsic crystalline silicon layer may be formed by stacking two or more films of intrinsic polysilicon.

[0332] In step S52, as an example of a third process, a p-type amorphous silicon layer is formed on the intrinsic crystalline silicon layer in place of the n-type amorphous silicon layer 4b. The p-type amorphous silicon layer has a thickness greater than that of the intrinsic crystalline silicon layer and corresponds to a layer (second layer) of amorphous silicon containing a p-type dopant as the second conductivity type. The p-type dopant contained in the p-type amorphous silicon layer is, for example, boron. The p-type amorphous silicon layer is formed by, for example, forming a p-type amorphous silicon layer using monosilane (SiH) as a source gas. ４ ) gas and diborane (B ２ H ６ The p-type amorphous silicon layer can be formed by a PECVD method using a p-type amorphous silicon layer having a thickness of, for example, 20 nm to 200 nm.

[0333] In step S53, as an example of a fourth process, a p-type polysilicon layer 10C is formed by heat treatment instead of the n-type polysilicon layer 4. Here, for example, on the second surface 2b side of the silicon substrate 2C, the intrinsic crystalline silicon layer and the p-type amorphous silicon layer stacked on the silicon oxide film 3 are transformed into the p-type polysilicon layer 10C. Here, heat treatment is performed to promote crystallization of the amorphous silicon in the p-type amorphous silicon layer while diffusing the p-type dopant contained in the p-type amorphous silicon layer toward the intrinsic crystalline silicon layer and the silicon oxide film 3. As a result, a p-type polysilicon layer 10C located on the silicon oxide film 3 and containing the p-type dopant can be produced from the intrinsic crystalline silicon layer and the p-type amorphous silicon layer. Here, the heat treatment temperature may be set, for example, within a range of 550°C to 1000°C, 700°C to 1000°C, or 700°C to 900°C.

[0334] In step S5 after the above-described modification, before a p-type amorphous silicon layer is formed as a second amorphous silicon layer containing a second conductivity type dopant, an intrinsic crystalline silicon layer having a thickness smaller than that of the p-type amorphous silicon layer is formed on the silicon oxide film 3. When this intrinsic crystalline silicon layer is formed, even if hydrogen bonded to silicon in the intrinsic amorphous silicon layer is desorbed by a heat treatment for promoting crystallization of the intrinsic amorphous silicon layer, the hydrogen can be released from the surface of the intrinsic amorphous silicon layer opposite the silicon oxide film 3B. This reduces the aggregation of hydrogen gas at the interface between the silicon oxide film 3 and the intrinsic crystalline silicon layer. Furthermore, because the thickness of the intrinsic amorphous silicon layer before being transformed into intrinsic crystalline silicon by the heat treatment is small, the increase in stress that could cause the silicon layer to peel off from the silicon oxide film 3 due to the shrinkage of the silicon layer when the intrinsic amorphous silicon layer is transformed into intrinsic crystalline silicon by the heat treatment can be reduced. These factors can improve adhesion between the silicon oxide film 3 and the intrinsic crystalline silicon layer. As a result, when heat treatment is performed to promote crystallization of amorphous silicon in the p-type amorphous silicon layer formed on the intrinsic crystalline silicon layer, the aggregation of hydrogen gas between the silicon oxide film 3 and the intrinsic crystalline silicon layer is reduced, and hydrogen can be released from the surface of the p-type amorphous silicon layer opposite the silicon oxide film 3 and can migrate toward the silicon substrate 2C. This can reduce the occurrence of blisters at the interface between the silicon oxide film 3 and the p-type polysilicon layer 10C. This can also reduce the occurrence of local defects in the p-type polysilicon layer 10C due to these blisters.

[0335] In other words, in step S5 after the above-described modification, when the p-type polysilicon layer 10C is formed on the silicon oxide film 3, an intrinsic crystalline silicon layer is formed on the silicon oxide film 3, and then a p-type amorphous silicon layer is formed on the intrinsic crystalline silicon layer, and then the p-type polysilicon layer 10C is produced from the intrinsic crystalline silicon layer and the p-type amorphous silicon layer by heat treatment. This can reduce the occurrence of blisters at the interface between the silicon oxide film 3 and the p-type polysilicon layer 10C, and can also reduce the occurrence of local defects in the p-type polysilicon layer 10B due to the blisters.

[0336] 3, instead of forming the passivation film 7 on the first surface 2f side of the silicon substrate 2C, a passivation film 7C is formed on the second surface 2b side of the silicon substrate 2C. For example, the passivation film 7C is formed over the entire surface of the p-type polysilicon layer 10C formed on the second surface 2b side of the silicon substrate 2C, opposite the silicon substrate 2C. Here, for example, an aluminum oxide layer may be formed as the passivation film 7C by the ALD method, or a silicon oxide layer may be formed as the passivation film 7C by the PECVD method.

[0337] 3, anti-reflection films are formed on each of the first surface 2f side and the second surface 2b side of the silicon substrate 2C. At this time, for example, the first anti-reflection film 5 is formed not on the n-type polysilicon layer 4 but over the entire surface of the passivation film 7C on the side opposite to the silicon substrate 2C, and the second anti-reflection film 8 is formed over the entire surface of the second semiconductor region 22C. Here, for example, a silicon nitride layer may be formed as the anti-reflection film by the PECVD method.

[0338] In step S8 of FIG. 3 , a process is performed in which the silicon substrate 2 is changed to a silicon substrate 2C. For example, electrodes are formed on the first surface 2f and the second surface 2b of the silicon substrate 2C. For example, a first electrode 6 is formed on the second surface 2b of the silicon substrate 2C, and a second electrode 9 is formed on the first surface 2f of the silicon substrate 2C. Here, for example, a first metal paste is applied to the first anti-reflection film 5 by screen printing or the like, and the first metal paste is fired to form the first electrode 6. Alternatively, a second metal paste is applied to the second anti-reflection film 8 by screen printing or the like, and the second electrode 9 is fired to form the second electrode 9. For example, if the first metal paste contains a metal powder, an organic vehicle, and a glass frit, the glass frit in the first metal paste melts when the first metal paste is fired, causing firing penetration of the first anti-reflection film 5 and the passivation film 7C. As a result, the first electrode 6 penetrates the first anti-reflection film 5 and the passivation film 7C and is connected to the p-type polysilicon layer 10C. For example, if the second ...

Claims

1. A solar cell element comprising: a substrate; an oxide film; and a polysilicon layer, wherein the substrate has a first region which is a region of a first conductivity type semiconductor, the oxide film is in contact with the first region, the polysilicon layer is in contact with a surface of the oxide film opposite to the first region, the polysilicon layer contains a dopant, the polysilicon layer includes a second region, the second region being a region of the polysilicon layer on the oxide film side which is in contact with the oxide film, a distribution of concentration of the dopant in a direction from a surface of the polysilicon layer opposite to the substrate toward the substrate in a region from the second region through the oxide film to the first region has a first maximum peak and a second maximum peak, and in the distribution of the dopant concentration, the second peak is present at a position 3 nm or more away from a position showing the first peak in the direction from the first region through the oxide film toward the second region, and the dopant is a dopant of the first conductivity type or a second conductivity type different from the first conductivity type.

2. A semiconductor device comprising: a substrate; and a polysilicon layer, wherein the substrate has a first region which is a region of a semiconductor of a first conductivity type; the substrate includes an oxide film, the oxide film being located between the first region and the polysilicon layer and in contact with both the first region and the polysilicon layer; the polysilicon layer being in contact with the substrate; the polysilicon layer containing a dopant; the polysilicon layer including a second region, the second region being a region of the polysilicon layer on the oxide film side which is in contact with the oxide film; in a region from the second region through the oxide film to the first region, a distribution of the concentration of the dopant in a direction from a surface of the polysilicon layer on a side opposite to the substrate toward the substrate has a maximum first peak and a second peak; and in the distribution of the dopant concentration, the second peak is present at a position 3 nm or more away from a position showing the first peak in a direction from the first region through the oxide film toward the second region, The solar cell element, wherein the dopant is a dopant of the first conductivity type or a dopant of a second conductivity type different from the first conductivity type.

3. A solar cell element according to claim 1 or 2, wherein the distribution of the dopant concentration in the direction from the surface of the polysilicon layer opposite the substrate toward the substrate is measured using secondary ion mass spectrometry.

4. A method for manufacturing a solar cell element, comprising a first step, a second step, a third step, and a fourth step, wherein in the first step, an oxide film is formed on a portion of a crystalline silicon substrate including a first region that is a region of a first conductivity type semiconductor, the portion being located inside the substrate and along the surface of the substrate, or on the surface of the substrate, the oxide film being in contact with the first region, in the second step, a first layer of intrinsic crystalline silicon is formed on the oxide film, in the third step, a second layer of amorphous silicon having a thickness greater than that of the first layer and containing a dopant is formed on the first layer, in the fourth step, a heat treatment is performed to diffuse the dopant contained in the second layer toward the first layer and the oxide film while promoting crystallization of the amorphous silicon of the second layer, thereby generating a polysilicon layer located on the oxide film and containing the dopant from the first layer and the second layer, the dopant being a dopant of the first conductivity type or a second conductivity type different from the first conductivity type.

5. A solar cell element comprising: a substrate; an oxide film; and a polysilicon layer, wherein the substrate has a first region which is a region of a semiconductor of a first conductivity type, the oxide film is in contact with the first region, the polysilicon layer is in contact with a surface of the oxide film opposite to the first region, the polysilicon layer contains a dopant, the polysilicon layer being a layer produced from a first layer of intrinsic crystalline silicon located on the oxide film and a second layer of amorphous silicon located on the first layer, having a thickness greater than that of the first layer and containing the dopant, by performing a heat treatment on the first layer and the second layer, the heat treatment being a process for diffusing the dopant contained in the second layer toward the first layer and the oxide film, while progressing crystallization of the amorphous silicon of the second layer, and the dopant being a dopant of the first conductivity type or a second conductivity type different from the first conductivity type.

6. A solar cell element comprising: a substrate; and a polysilicon layer, wherein the substrate has a first region which is a region of a semiconductor of a first conductivity type, the substrate includes an oxide film, the oxide film is located between the first region and the polysilicon layer and is in contact with each of the first region and the polysilicon layer, the polysilicon layer is in contact with the substrate, and the polysilicon layer contains a dopant, the polysilicon layer being produced from a first layer of intrinsic crystalline silicon located on the oxide film and a second layer of amorphous silicon located on the first layer, having a thickness greater than that of the first layer and containing the dopant, by performing a heat treatment on the first layer and the second layer, the heat treatment being a process for diffusing the dopant contained in the second layer toward the first layer and the oxide film, while progressing crystallization of the amorphous silicon of the second layer, and the dopant being a dopant of the first conductivity type or a second conductivity type different from the first conductivity type.