Semiconductor device, power conversion device, and method of manufacturing the semiconductor device

Abstract

Provided is a semiconductor device in which a design of a printed wiring board connecting a plurality of semiconductor elements to each other is easier than before.　A semiconductor device (101) is provided with a printed wiring board (17), an individual package (201), and a relay board (3). The sum of the number of first areas (62) on the surface of the printed wiring board and the number of second areas (63) on the surface of the printed wiring board included in a printed wiring board surface pattern (32) is less than the sum of the number of first electrodes (22) and second electrodes (23) of the plurality of semiconductor elements (14) included in a plurality of the individual packages (201). The sum of the number of first areas (82) on the surface of the relay board and the number of second areas (83) on the surface of the relay board included in a relay board surface pattern (34) is less than the sum of the number of first areas (62) on the surface of the printed wiring board and the number of second areas (63) on the surface of the plurality of printed wiring boards.

Description

Semiconductor device, power conversion device, individual package, and method for manufacturing the individual package

[0001] The present disclosure relates to a semiconductor device, a power conversion device, an individual package, and a method for manufacturing the individual package.

[0002] In the prior art, a power module is disclosed in which an electrode portion is provided on the top of a semiconductor chip for connecting the electrode to a printed circuit board (for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2003-133514

[0004] However, in the prior art, when a circuit is formed by arranging a plurality of semiconductor elements, a plurality of electrodes are present directly above the semiconductor elements, i.e., on the side where the emitter and gate are provided, and in order to connect these plurality of electrodes together, the circuit for connecting these plurality of electrodes together on a printed wiring board becomes complicated, which poses a problem in that the design of the printed wiring board also becomes complicated.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device in which the design of a printed wiring board for connecting a plurality of semiconductor elements to one another is easier than ever before.

[0006] A semiconductor device according to the present disclosure includes a heat spreader and a plurality of semiconductor elements provided on the heat spreader, the semiconductor elements having first and second electrodes, the second electrode being located on the heat spreader side and the first electrode being located on the opposite side of the heat spreader. The semiconductor device according to the present disclosure also includes a printed wiring board having a printed wiring board backside pattern provided on the opposite side of the heat spreader from the semiconductor elements, the printed wiring board backside pattern including a first region on the backside of the printed wiring board electrically connected to the first electrode and a second region on the backside of the printed wiring board electrically connected to the second electrode via a conductive spacer provided on the heat spreader. The semiconductor device according to the present disclosure also includes a plurality of individual packages each including the heat spreader, the plurality of semiconductor elements, and printed wiring. The present disclosure also provides a semiconductor device comprising: an interconnection board, the interconnection board having a backside pattern provided on an opposite side of the printed wiring board from a semiconductor element, the backside pattern including a first region on a backside of the interconnection board and a second region on the backside of the interconnection board electrically connected to a first region on a front side of the printed wiring board and a second region on the backside of the interconnection board, respectively; and an interconnection board frontside pattern provided on the opposite side of the backside pattern, the backside pattern including the first region on a front side of the interconnection board and the second region on the backside of the interconnection board electrically connected to the first region on a front side of the interconnection board and the second region on the backside of the interconnection board, respectively; the interconnection board electrically connecting a plurality of individual packages via the backside pattern. The present disclosure also provides a semiconductor device comprising: an interconnection board, the backside pattern including a backside pattern provided on an opposite side of the printed wiring board from a semiconductor element, the backside pattern including a first region on a backside of the interconnection board and a second region on the backside of the interconnection board electrically connected to the first region on a front side of the interconnection board and the second region on the backside of the interconnection board, the interconnection board electrically connecting a plurality of individual packages via the backside pattern;

[0007] The individual package according to the present disclosure includes a heat spreader, and a plurality of semiconductor elements provided on the heat spreader, the semiconductor elements having first and second electrodes, the second electrodes being located on the heat spreader side and the first electrodes being located on the opposite side of the heat spreader. The individual package according to the present disclosure also includes a printed wiring board having a printed wiring board backside pattern provided on the opposite side of the heat spreader with respect to the semiconductor elements, the printed wiring board backside pattern including a first region on the backside of the printed wiring board electrically connected to the first electrode and a second region on the backside of the printed wiring board electrically connected to the second electrode via a spacer provided on the heat spreader, and a printed wiring board frontside pattern provided on the opposite side of the semiconductor elements with respect to the printed wiring board backside pattern, the printed wiring board frontside pattern including a first region on the front side of the printed wiring board electrically connected to the first region on the backside of the printed wiring board and the second region on the backside of the printed wiring board, respectively. In addition, the individual package according to the present disclosure is characterized in that the sum of the number of first regions on the surface of the printed wiring board and the number of second regions on the surface of the printed wiring board included in the printed wiring board surface pattern is less than the sum of the number of first electrodes and second electrodes of the multiple semiconductor elements included in the multiple individual packages.

[0008] A method for manufacturing an individual package according to the present disclosure includes providing, on a heat spreader, a plurality of semiconductor elements each having a first electrode and a second electrode, the second electrode being located on the heat spreader side and the first electrode being located on an opposite side of the heat spreader. The method for manufacturing an individual package according to the present disclosure also includes providing, on the opposite side of the heat spreader from the semiconductor elements, a printed wiring board having a printed wiring board back surface pattern including a first region on a back surface of the printed wiring board electrically connected to the first electrode and a second region on the back surface of the printed wiring board electrically connected to the second electrode via a spacer provided on the heat spreader, and a printed wiring board front surface pattern provided on the opposite side of the semiconductor elements from the back surface pattern of the printed wiring board, the first region on the front surface of the printed wiring board electrically connected to the first region on the back surface of the printed wiring board and the second region on the back surface of the printed wiring board, respectively. In addition, the manufacturing method of the individual package according to the present disclosure is characterized in that the sum of the number of first regions on the surface of the printed wiring board and the number of second regions on the surface of the printed wiring board included in the printed wiring board surface pattern is less than the sum of the number of first electrodes and second electrodes possessed by the plurality of semiconductor elements.

[0009] According to the semiconductor device according to the present disclosure, the design of a printed wiring board that connects a plurality of semiconductor elements to each other can be made easier than before.

[0010] FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present disclosure; FIG. 2 is a schematic cross-sectional view of a piece package according to the first embodiment of the present disclosure; FIG. 3 is a schematic plan view of a semiconductor element and a heat spreader included in the piece package according to the first embodiment of the present disclosure; FIG. 4 is a schematic plan view of a semiconductor element and a heat spreader included in the piece package according to the first embodiment of the present disclosure; FIG. 5 is a schematic top view of a printed wiring board included in the piece package according to the first embodiment of the present disclosure; FIG. 6 is a schematic bottom view of a plurality of semiconductor elements and a printed wiring board included in the piece package according to the first embodiment of the present disclosure; FIG. 7 is a schematic top view of a piece package according to the first embodiment of the present disclosure; FIG. 8 is a schematic side view of a piece package according to a second embodiment of the present disclosure, which is a schematic view of the top surfaces of a plurality of piece packages and the bottom surface of a relay board according to the first embodiment of the present disclosure; FIG. 9 is a schematic view of the circuit pattern of a printed wiring board included in the piece package according to the second embodiment of the present disclosure; FIG. 10 is a schematic diagram of a circuit pattern of an interposer substrate according to a second embodiment of the present disclosure. FIG. 11 is a schematic diagram of the upper surfaces of a plurality of individual packages and the lower surface of an interposer substrate according to the second embodiment of the present disclosure. FIG. 12 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present disclosure. FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 14 is a schematic cross-sectional view of an interposer substrate according to the fourth embodiment of the present disclosure. FIG. 15 is a schematic top view of a plurality of printed wiring boards according to the first to fourth embodiments of the present disclosure. FIG. 16 is a schematic top view of a plurality of individual packages according to the first to fourth embodiments of the present disclosure. FIG. 17 is a block diagram showing the configuration of a power conversion system to which a power conversion device according to a fifth embodiment of the present disclosure is applied.

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. Note that the drawings are schematic, and the relative sizes and positions shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. In the following description, similar components are denoted by the same reference numerals, and their names and functions are assumed to be the same or similar. Therefore, detailed descriptions thereof may be omitted.

[0012] First Embodiment A semiconductor device 101 according to a first embodiment will be described with reference to Figures 1 to 10. Figure 1 is a schematic cross-sectional view of the semiconductor device 101 according to the first embodiment.

[0013] 1 , a semiconductor device 101 according to the present embodiment includes a cooler 1, a base bonding material 2 provided on the top surface of the cooler 1, a plurality of individual packages 201 provided on the top surface of the base bonding material 2, an interconnect substrate 3 provided on the top surfaces of the plurality of individual packages 201, a sealing resin (second sealing resin) 4 filling the gaps between the plurality of individual packages 201 and the interconnect substrate 3, and a conductive bonding material 5 electrically connecting circuit patterns provided on the individual packages 201 and circuit patterns provided on the interconnect substrate 3. As shown in FIG. 1 , two individual packages 201 are provided on the top surface of the cooler 1, and a single interconnect substrate 3 is provided to connect each of the individual packages 201. Note that the number of individual packages 201 is not limited to two, and three or more may be provided horizontally in the drawing, or a plurality may be provided in the depth direction in the drawing.

[0014] The upper surface refers to the surface on which the base bonding material 2 and other components are provided, with the cooler 1 as the reference. The surface different from the upper surface, i.e., the opposite side of the upper surface, is referred to as the lower surface. The upper surface may also be referred to as the front surface, and the lower surface may also be referred to as the back surface. The same applies to the following explanations.

[0015] The cooler 1 is formed of a metal member such as aluminum or copper. The cooler 1 is, for example, a heat sink-shaped structure. The cooler 1 may have a water-cooled structure in which cooling is performed by flowing a liquid such as water inside the cooler 1. The liquid flowing inside the cooler 1 does not have to be water, and may be, for example, a refrigerant, oil, or the like. The cooler 1 may also have an air-cooled structure in which cooling is performed by feeding a gas such as air into the cooler 1. In the case of an air-cooled structure, the gas fed into the cooler 1 does not have to be air, and may be, for example, a refrigerant gas such as propane gas.

[0016] The base bonding material 2 connects the cooler 1 and the individual package 201. The base bonding material 2 is formed of, for example, sintered silver, silver paste, or solder.

[0017] 2 is a schematic cross-sectional view of an individual package 201 according to embodiment 1. As shown in FIG. 2 , the individual package 201 according to this embodiment includes a thermally conductive member 11, a heat spreader 12 provided on the upper surface of the thermally conductive member 11, and a plurality of die bond materials 13 provided on the upper surface of the heat spreader 12.

[0018] In addition, the individual package 201 according to this embodiment includes a plurality of semiconductor elements 14 provided on the upper surfaces of a plurality of die bond materials 13, a conductive spacer 15 provided on the upper surface of the heat spreader 12 in parallel with the die bond materials 13, and a bonding material 16 that electrically connects the heat spreader 12 and the conductive spacer 15.

[0019] In addition, the individual package 201 according to this embodiment includes a printed wiring board 17 provided on the upper surfaces of the plurality of semiconductor elements 14 and the conductive spacer 15, a plurality of bonding materials 16 that electrically connect the printed wiring board 17 to the electrodes included in the semiconductor elements 14 and the printed wiring board 17 to the conductive spacer 15, and a first sealing resin 18.

[0020] The thermally conductive member 11 includes a metal foil 19 and an insulating sheet 20 provided on the upper surface of the metal foil. The thermally conductive member 11 is an insulating layer with high heat dissipation properties. The insulating sheet 20 insulates the metal foil 19 from the heat spreader 12. The insulating sheet 20 also transfers heat generated by the semiconductor element 14 to the metal foil 19.

[0021] The metal foil 19 is made of a material with high thermal conductivity, such as a copper plate, an aluminum plate, or a copper foil. The insulating sheet 20 is made of a thermosetting resin, such as an epoxy resin. The insulating sheet 20 also contains a highly conductive filler, such as silica, alumina, or boron nitride.

[0022] The heat spreader 12 is provided on the upper surface of the thermally conductive member 11. The heat spreader 12 is formed, for example, in the shape of a rectangular parallelepiped block. The heat spreader 12 is formed, for example, from a metal member. The heat spreader 12 is electrically connected to an electrode (a second electrode 23 described later) on the back side of the semiconductor element 14 via a die bond material 13. The heat spreader 12 is also electrically connected to a conductive spacer 15 in parallel with the semiconductor element 14 via a bonding material 16.

[0023] The heat spreader 12 is made of, for example, a metal such as copper or aluminum, or a composite material with high thermal conductivity.

[0024] The die bond material 13 connects the heat spreader 12 and the semiconductor element 14 .

[0025] The die bond material 13 is formed of, for example, solder, sintered silver, or silver paste. It is desirable that the die bond material 13 has a higher melting point than the base bonding material 2. Since the melting point of the die bond material 13 is higher than the melting point of the base bonding material 2, even when the base bonding material 2 is formed after the die bond material 13 is formed, the base bonding material 2 can be formed without melting the die bond material 13.

[0026] 2, the individual package 201 includes a plurality of semiconductor elements 14. The individual package 201 includes, for example, two semiconductor elements 14.

[0027] The semiconductor element 14 may be, for example, a diode used in a converter section that converts input AC power into DC power, a bipolar transistor used in an inverter section that converts DC power into AC power, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a GTO (Gate Turn-Off Thyristor), or an SBD (Schottky Barrier Diode).

[0028] The semiconductor element 14 is provided on the upper surface of the heat spreader 12. Although not shown in FIG. 2 , the semiconductor element 14 includes a third electrode 21, a first electrode 22, and a second electrode 23. Note that the semiconductor element 14 does not necessarily include the third electrode. The first electrode and the second electrode are electrodes of the main circuit. The third electrode includes a control electrode, a current sense electrode, a temperature sense electrode, or the like. Note that the current sense electrode, the temperature sense electrode, or the like may be provided as an electrode separate from the third electrode, for example, as a sense electrode.

[0029] The third electrode 21 and the first electrode 22 are provided on the side of the semiconductor element 14 opposite the heat spreader 12. That is, the third electrode 21 and the first electrode 22 are provided on the upper surface of the semiconductor element 14, i.e., on the front surface of the semiconductor element 14. The second electrode 23 is provided on the heat spreader 12 side of the semiconductor element 14. That is, the second electrode 23 is provided on the lower surface of the semiconductor element 14, i.e., on the back surface of the semiconductor element 14.

[0030] Examples of the first electrode, second electrode, and third electrode will be described. The first electrode, second electrode, and third electrode can be selected appropriately depending on the type of semiconductor element. For example, if the semiconductor element 14 is a diode, the first electrode corresponds to an anode or a cathode. Furthermore, the second electrode corresponds to an anode or a cathode. If the first electrode is an anode, the second electrode is a cathode. If the first electrode is a cathode, the second electrode is an anode. Furthermore, the third electrode may be any electrode or may not be provided.

[0031] If the semiconductor element 14 is a bipolar transistor, the first electrode corresponds to an emitter electrode, the second electrode corresponds to a collector electrode, and the third electrode corresponds to a base electrode. A current sensor or a temperature sensor may be provided as a fourth electrode.

[0032] If the semiconductor element 14 is an IGBT, the first electrode corresponds to an emitter electrode, the second electrode corresponds to a collector electrode, and the third electrode corresponds to a gate electrode, etc. A fourth electrode may be provided for current sensing or temperature sensing, etc.

[0033] If the semiconductor element 14 is a MOSFET, the first electrode corresponds to a source electrode, the second electrode corresponds to a drain electrode, and the third electrode corresponds to a gate electrode. A current sensor or a temperature sensor may be provided as a fourth electrode.

[0034] Furthermore, if the semiconductor element 14 is a GTO, the first electrode corresponds to an anode or a cathode. Furthermore, the second electrode corresponds to an anode or a cathode. If the first electrode is an anode, the second electrode is a cathode. If the first electrode is a cathode, the second electrode is an anode. Furthermore, the third electrode corresponds to a gate electrode. Note that a current sensor, a temperature sensor, or the like may be provided as a fourth electrode.

[0035] Furthermore, when the semiconductor element 14 is an SBD, the first electrode corresponds to an anode or a cathode. Also, the second electrode corresponds to an anode or a cathode. When the first electrode is an anode, the second electrode is a cathode. When the first electrode is a cathode, the second electrode is an anode. Also, the third electrode may be any electrode or may not be provided.

[0036] The second electrode 23, which is an electrode provided on the underside of the semiconductor element 14, is electrically connected to the heat spreader 12 via the die bond material 13. In other words, the second electrode 23 has the same potential as the heat spreader 12, which is electrically connected to the second electrode 23 via the die bond material 13.

[0037] The heat spreader 12 is at the same potential as the conductive spacer 15 electrically connected to the heat spreader 12 via the bonding material 16. That is, the second electrode 23 and the conductive spacer 15 are at the same potential. The two semiconductor elements shown in FIG. 2 are connected in parallel between the heat spreader 12 and the printed wiring board 17.

[0038] It is also possible to form a portion having the same potential as the second electrode 23 using a member other than the conductive spacer 15 .

[0039] The third electrode 21 and the first electrode 22 provided on the upper surface of the semiconductor element 14 are electrically connected to the printed wiring board 17 via the bonding material 16 .

[0040] The conductive spacer 15 is provided on the upper surface of the heat spreader 12. The conductive spacer 15 is connected to the heat spreader 12 via a bonding material 16. The conductive spacer 15 is electrically connected to the heat spreader 12 via, for example, the bonding material 16. In other words, the conductive spacer 15 has the same potential as the heat spreader 12.

[0041] Furthermore, the conductive spacer 15 is connected to the printed wiring board 17 via the bonding material 16. The conductive spacer 15 is, for example, electrically connected to the printed wiring board 17 via the bonding material 16. That is, the heat spreader 12 and the printed wiring board 17 are electrically connected via the conductive spacer 15. In this embodiment, the conductive spacer 15 is provided in parallel with the plurality of semiconductor elements 14.

[0042] The conductive spacer 15 is preferably a copper pin or plate.

[0043] The bonding material 16 is a conductive member that electrically connects the third electrode 21 or the first electrode 22 provided on the upper surface of the semiconductor element 14 to the printed wiring board 17 .

[0044] The bonding material 16 also connects the heat spreader 12 and the conductive spacer 15. The bonding material 16 also connects the conductive spacer 15 and the printed wiring board 17. The heat spreader 12 and the conductive spacer 15 may not be electrically connected, and the heat spreader 12 and the printed wiring board 17 may be electrically connected by a member other than the conductive spacer 15.

[0045] The bonding material 16 is formed of a conductive material such as solder, low-temperature solder, sintered silver, or silver paste.

[0046] 2, the printed wiring board 17 is provided on the upper surface of the semiconductor element 14. The printed wiring board 17 includes a printed wiring board rear surface pattern 31, a printed wiring board front surface pattern 32, and a first insulating plate 43.

[0047] The printed wiring board rear surface pattern 31 is provided on the lower surface of the first insulating plate 43, i.e., on the rear surface of the first insulating plate 43. The printed wiring board rear surface pattern 31 is connected to a plurality of semiconductor elements 14. In this embodiment, as shown in FIG. 2 , the printed wiring board rear surface pattern 31 is connected to two semiconductor elements 14.

[0048] The printed wiring board rear surface pattern 31 is electrically connected to the third electrode 21 and the first electrode 22 of the semiconductor element 14 via the bonding material 16 .

[0049] Furthermore, the printed wiring board rear surface pattern 31 is connected to the conductive spacer 15 via the bonding material 16. The conductive spacer 15 and the printed wiring board rear surface pattern 31 may or may not be electrically connected. In this embodiment, the conductive spacer 15 and the printed wiring board rear surface pattern 31 are electrically connected.

[0050] The printed wiring board surface pattern 32 is provided on the upper surface of the first insulating plate 43 , that is, on the surface of the first insulating plate 43 .

[0051] The printed wiring board rear surface pattern 31 and the printed wiring board front surface pattern 32 are electrically connected to each other by corresponding patterns among the plurality of patterns included in each circuit pattern. The connection of the circuit patterns will be described in detail later.

[0052] It is desirable that a resist be formed on the printed wiring board 17 except for the portions where the printed wiring board rear surface pattern 31 and the printed wiring board front surface pattern 32 are formed. By forming the resist, it is possible to suppress the solder from spreading and improve the bondability between the circuit pattern and the mating member, for example, the electrode, connected to the circuit pattern.

[0053] Although FIG. 2 shows only two layers of circuit patterns, that is, the printed wiring board rear surface pattern 31 and the printed wiring board front surface pattern 32, the printed wiring board 17 may include three or more layers of circuit patterns.

[0054] As shown in FIG. 2, the first sealing resin 18 integrally seals the thermally conductive member 11, the heat spreader 12, the die bond material 13, the semiconductor element 14, the conductive spacer 15, the bonding material 16, and the printed wiring board 17.

[0055] The heat spreader 12 , the die bond material 13 , the semiconductor element 14 , the conductive spacer 15 , and the bonding material 16 are all sealed with a first sealing resin 18 .

[0056] The heat conducting member 11 and the printed wiring board 17 are partially exposed from the first sealing resin 18. The heat conducting member 11, particularly the metal foil 19, is exposed from the first sealing resin 18.

[0057] Part of the printed wiring board 17, in particular the printed wiring board surface pattern 32, is exposed from the first sealing resin 18. In addition, part or all of the side surfaces of the printed wiring board 17, which are surfaces other than the top and bottom surfaces of the printed wiring board 17, are exposed from the first sealing resin 18.

[0058] The first sealing resin 18 ensures insulation between the sealed components and also functions as a case for the individual package 201 .

[0059] The first sealing resin 18 is molded by a method such as transfer molding, injection molding, or compression molding.

[0060] The first sealing resin 18 is made of, for example, an epoxy resin or a phenolic resin containing a filler.

[0061] As shown in FIG. 2, the individual package 201 has a rectangular parallelepiped shape when viewed from the side, but it is not limited to a rectangular parallelepiped shape and may have any shape.

[0062] 1 , the base bonding material 2 is in contact with the individual package 201, particularly with the first sealing resin 18 and the metal foil 19 exposed from the first sealing resin 18. The base bonding material 2 bonds the cooler 1 and the heat conductive member 11 together.

[0063] 1, the semiconductor device 101 includes an interconnection substrate 3 provided on the upper surfaces of a plurality of individual packages 201. The interconnection substrate 3 includes an interconnection substrate back surface pattern 33, an interconnection substrate front surface pattern 34, and a second insulating plate 44.

[0064] The relay board rear surface pattern 33 is provided on the lower surface of the second insulating plate 44, i.e., on the rear surface of the second insulating plate 44. The relay board rear surface pattern 33 is connected to the plurality of individual packages 201. In this embodiment, as shown in FIG. 1 , the relay board rear surface pattern 33 is connected to the two individual packages 201 via the bonding material 5.

[0065] The relay board rear surface pattern 33 is electrically connected via the bonding material 5 to the area of ​​the printed wiring board front surface pattern 32 that is exposed from the first sealing resin 18 .

[0066] The individual package 201 and the relay substrate 3 are bonded together by a bonding material 5, and the narrow gap portion has a thickness dimension of about 50 to 100 microns. Meanwhile, the combined thickness of the surface of the individual package 201 and the thickness of the relay substrate back surface pattern 33 of the relay substrate 3 is the maximum gap.

[0067] A second sealing resin 4 is filled between the lower surface of the relay substrate 3 and the individual package 201. The second sealing resin 4 covers the relay substrate rear surface pattern 33, the bonding material 5, and the upper surface of the individual package 201.

[0068] The thickness of the relay substrate back surface pattern 33 is preferably 0.1 mm or more. If the thickness of the relay substrate back surface pattern 33 is less than 0.1 mm, a large current flows through the relay substrate back surface pattern 33 of the relay substrate 3. Because a large current flows through the relay substrate back surface pattern 33, the relay substrate back surface pattern 33 generates self-heat due to Joule heat, and a portion of the relay substrate back surface pattern 33 has a temperature higher than the maximum junction temperature of the semiconductor element 14. If a portion of the relay substrate back surface pattern 33 has a temperature higher than the maximum junction temperature of the semiconductor element 14, the reliability of the semiconductor device 101 may be significantly reduced.

[0069] The relay board surface pattern 34 is provided on the upper surface of the second insulating plate 44, i.e., on the surface of the second insulating plate 44. The relay board surface pattern 34 is electrically connected to another mating member (not shown).

[0070] The relay board rear surface pattern 33 and the relay board front surface pattern 34 are electrically connected to each other by corresponding patterns among the plurality of patterns included in each circuit pattern. The connection of the circuit patterns will be described in detail later.

[0071] The printed wiring board rear surface pattern 31, the printed wiring board front surface pattern 32, the relay board rear surface pattern 33, and the relay board front surface pattern 34 are, for example, copper patterns made of copper.

[0072] 3 is a schematic plan view of the heat spreader 12 and the semiconductor element 14 included in the individual package 201 according to embodiment 1. The front side of the paper in FIG. 3 is the top surface. As shown in FIG. 3, the semiconductor elements 14 are arranged side by side on the top surface of the heat spreader 12.

[0073] The individual package 201 includes, for example, two semiconductor elements 14. Two semiconductor elements 14 are provided on the upper surface of the heat spreader 12.

[0074] The semiconductor element 14 includes a third electrode 21, a first electrode 22, a second electrode 23 (not shown in FIG. 3 ), and a fourth electrode 24. As shown in FIG. 3 , the third electrode 21, the first electrode 22, and the fourth electrode 24 are provided on the upper surface of the semiconductor element 14. In FIG. 3 , the third electrode 21 is arranged to be sandwiched between two fourth electrodes 24, but the arrangement of the third electrode 21 and the fourth electrode 24 is not limited to the embodiment shown in FIG. 3 . The fourth electrode 24 is, for example, a sense electrode.

[0075] The third electrode 21 , the first electrode 22 , and the fourth electrode 24 are connected to a printed wiring board rear surface pattern 31 of the printed wiring board 17 via a bonding material 16 .

[0076] The second electrode 23 is provided on the lower surface of the semiconductor element 14. The second electrode 23 is electrically connected to the heat spreader 12. That is, the second electrode 23 and the heat spreader 12 have the same potential.

[0077] 3, the heat spreader 12 is connected to, for example, a conductive spacer 15 via a bonding material 16. Note that the conductive spacer 15 does not necessarily have to be electrically connected to the heat spreader 12.

[0078] The conductive spacer 15 is connected to the printed wiring board rear surface pattern 31 of the printed wiring board 17 via the bonding material 16. Note that the conductive spacer 15 does not have to be electrically connected to the printed wiring board rear surface pattern 31 of the printed wiring board 17.

[0079] Furthermore, members other than the semiconductor element 14 and the conductive spacer 15 may be provided on the upper surface of the heat spreader 12. Members other than the semiconductor element 14 and the conductive spacer 15 provided on the upper surface of the heat spreader 12 may be electrically connected to the heat spreader 12.

[0080] The semiconductor element 14 shown in FIGS. 1 and 2 is a schematic cross-sectional view taken along line AA' in FIG.

[0081] Furthermore, the semiconductor element 14 may include any number of fourth electrodes 24. The number of fourth electrodes 24 included in the semiconductor element 14 is not limited to two, and may be three. Furthermore, the semiconductor element 14 does not have to include the fourth electrode 24.

[0082] 4 is a schematic plan view of the heat spreader 12 and the semiconductor element 14 included in the individual package 201 according to embodiment 1. The semiconductor element 14 shown in FIG.

[0083] 5 is a schematic diagram of a printed wiring board rear pattern 31 and a printed wiring board front pattern 32 of the printed wiring board 17 included in the individual package 201 according to embodiment 1. The printed wiring board rear pattern 31 provided on the lower surface of the printed wiring board 17 is shown by a dashed line, and the printed wiring board front pattern 32 provided on the upper surface of the printed wiring board 17 is shown by a solid line. Even when the solid line and the dashed line overlap, they are shown shifted for convenience.

[0084] Hereinafter, in the explanations of the printed wiring board rear surface pattern 31, the printed wiring board front surface pattern 32, the relay board rear surface pattern 33, and the relay board front surface pattern 34, the first to fourth regions will be described. For example, the first to fourth regions refer to the regions electrically connected to the first to fourth electrodes, respectively.

[0085] The printed wiring board rear surface pattern 31 includes a third region 51 on the rear surface of the printed wiring board, a first region 52 on the rear surface of the printed wiring board, a second region 53 on the rear surface of the printed wiring board, and a fourth region 54 on the rear surface of the printed wiring board. The third region 51 on the rear surface of the printed wiring board, the first region 52 on the rear surface of the printed wiring board, the second region 53 on the rear surface of the printed wiring board, and the fourth region 54 on the rear surface of the printed wiring board are electrically connected to the third electrode 21, the first electrode 22, the second electrode 23, and the fourth electrode 24 of the semiconductor element 14, respectively.

[0086] The printed wiring board rear surface pattern 31 includes, for example, a third region 51 on the rear surface of two printed wiring boards, a first region 52 on the rear surface of one printed wiring board, a second region 53 on the rear surface of one printed wiring board, and a fourth region 54 on the rear surface of six printed wiring boards.

[0087] The number of the third regions 51 on the back surface of the printed wiring board, the first regions 52 on the back surface of the printed wiring board, the second regions 53 on the back surface of the printed wiring board, and the fourth regions 54 on the back surface of the printed wiring board is not limited to the numbers shown in FIG. 5 .

[0088] The printed wiring board surface pattern 32 includes a third region 61 on the surface of the printed wiring board, a first region 62 on the surface of the printed wiring board, a second region 63 on the surface of the printed wiring board, and a fourth region 64 on the surface of the printed wiring board. The third region 61 on the surface of the printed wiring board, the first region 62 on the surface of the printed wiring board, the second region 63 on the surface of the printed wiring board, and the fourth region 64 on the surface of the printed wiring board are electrically connected to the third region 51 on the back surface of the printed wiring board, the first region 52 on the back surface of the printed wiring board, the second region 53 on the back surface of the printed wiring board, and the fourth region 54 on the back surface of the printed wiring board, respectively.

[0089] The printed wiring board surface pattern 32 includes, for example, two third regions 61 on the surface of the printed wiring board, one first region 62 on the surface of the printed wiring board, one second region 63 on the surface of the printed wiring board, and six fourth regions 64 on the surface of the printed wiring board.

[0090] In the printed wiring board surface pattern 32 , the number of third regions 61 on the printed wiring board surface and the number of fourth regions 64 on the printed wiring board surface are equal to or less than the number of third electrodes 21 and fourth electrodes 24 of the semiconductor element 14 .

[0091] Furthermore, the sum of the number of first regions 62 on the surface of the printed wiring board and the number of second regions 63 on the surface of the printed wiring board may be less than the sum of the number of first electrodes 22 and second electrodes 23 possessed by the multiple semiconductor elements 14 included in the individual package 201.

[0092] Furthermore, the number of first regions 62 on the surface of the printed wiring board and the number of second regions 63 on the surface of the printed wiring board may be less than the number of first electrodes 22 and second electrodes 23, respectively.

[0093] Since the total number of third regions 61 on the surface of the printed wiring board, first regions 62 on the surface of the printed wiring board, second regions 63 on the surface of the printed wiring board, and fourth regions 64 on the surface of the printed wiring board is less than the total number of third electrodes 21, first electrodes 22, second electrodes 23, and fourth electrodes 24 of the multiple semiconductor elements 14 included in the individual package 201, the printed wiring board surface pattern 32 is simplified, making it easier to route the wiring on the printed wiring board 17, and thus facilitating the design of the printed wiring board 17.

[0094] Furthermore, since the sum of the number of the third region 61 on the surface of the printed wiring board, the first region 62 on the surface of the printed wiring board, the second region 63 on the surface of the printed wiring board, and the fourth region 64 on the surface of the printed wiring board is less than the sum of the number of the third electrodes 21, the first electrodes 22, the second electrodes 23, and the fourth electrodes 24 of the multiple semiconductor elements 14 included in the individual package 201, the relay substrate surface pattern 34 is simplified, making it easier to route the wiring of the relay substrate 3, and thus facilitating the design of the relay substrate 3.

[0095] The numbers of the third regions 61, the first regions 62, the second regions 63, and the fourth regions 64 on the surface of the printed wiring board are not limited to those shown in FIG.

[0096] FIG. 6 is a schematic top view of the printed wiring board 17 included in the individual package 201 according to the first embodiment. The printed wiring board 17 includes a printed wiring board surface pattern 32 on its top surface. The printed wiring board surface pattern 32 of the printed wiring board 17 shown in FIG. 6 includes a third region 61 on the printed wiring board surface, a first region 62 on the printed wiring board surface, a second region 63 on the printed wiring board surface, and a fourth region 64 on the printed wiring board surface. Furthermore, the printed wiring board surface pattern 32 of the printed wiring board 17 shown in FIG. 6 includes two fourth regions 64 on the printed wiring board surface. That is, the number of third regions 61 on the printed wiring board surface and fourth regions 64 on the printed wiring board surface shown in FIG. 6 may be fewer than the number of third regions 61 on the printed wiring board surface and fourth regions 64 on the printed wiring board surface shown in FIG. 5.

[0097] The printed wiring board surface pattern 32 and the first insulating plate 43 of the printed wiring board 17 shown in FIGS. 1 and 2 are diagrammatic cross-sectional views taken along line BB' in FIG.

[0098] 7 is a schematic diagram showing the correspondence between the upper surfaces of the plurality of semiconductor elements 14 and the lower surface of the printed wiring board 17 included in the individual package 201 according to the first embodiment. The upper surfaces of the plurality of semiconductor elements 14 are shown by dashed lines, and the printed wiring board rear surface pattern 31 provided on the lower surface of the printed wiring board 17 is shown by solid lines. Even when the solid lines and dashed lines overlap, they are shown shifted for convenience.

[0099] The upper surfaces of the multiple semiconductor elements 14 indicated by dashed lines correspond to those shown in Fig. 4. The printed wiring board rear surface pattern 31 indicated by solid lines corresponds to those indicated by dashed lines in Fig. 5. As shown in Fig. 7, it can be seen that the positions of the third electrode 21, the first electrode 22, and the fourth electrode 24 on the upper surface of the semiconductor element 14 overlap with the printed wiring board rear surface pattern 31. In addition, the second region 53 on the rear surface of the printed wiring board is disposed in a position that overlaps with the conductive spacer 15 in the stacking direction.

[0100] 7 , for example, the plurality of first electrodes 22 are collected in a first region 52 on the rear surface of the printed wiring board 17 by the printed wiring board 17. By collecting the plurality of first electrodes 22 in the first region 52 on the rear surface of the printed wiring board 17, the surface pattern 32 of the printed wiring board 17 is simplified, and the wiring of the printed wiring board 17 can be easily routed, thereby facilitating the design of the printed wiring board 17.

[0101] 5 , in the printed wiring board surface pattern 32, the number of third regions 61 on the printed wiring board surface and the number of fourth regions 64 on the printed wiring board surface are equal to or less than the number of third electrodes 21 and fourth electrodes 24 of the semiconductor elements 14. Therefore, the total number of the third regions 61 on the printed wiring board surface, the first regions 62 on the printed wiring board surface, the second regions 63 on the printed wiring board surface, and the fourth regions 64 on the printed wiring board surface is less than the total number of the third electrodes 21, the first electrodes 22, the second electrodes 23, and the fourth electrodes 24 of the multiple semiconductor elements 14 included in the individual package 201.

[0102] In FIG. 7, the bonding material 16 provided between the individual package 201 and the rear surface pattern 31 of the printed wiring board is omitted.

[0103] 8 is a schematic top view of the individual package 201 according to the first embodiment. The individual package 201 is sealed with a first sealing resin 18. A portion of the printed wiring board surface pattern 32 of the printed wiring board 17 shown by the solid line in FIG. 5 is exposed from the first sealing resin 18. Note that the portion of the printed wiring board surface pattern 32 exposed from the first sealing resin 18 may be all or only a portion of the printed wiring board surface pattern 32.

[0104] 9 is a schematic diagram of the relay board rear surface pattern 33 and the relay board front surface pattern 34 of the relay board 3 according to embodiment 1. The relay board rear surface pattern 33 provided on the lower surface of the relay board 3 is shown by a dashed line, and the relay board front surface pattern 34 provided on the upper surface of the relay board 3 is shown by a solid line. Even when the solid line and the dashed line overlap, they are shown shifted for convenience.

[0105] The relay board 3 is connected to a plurality of individual packages 201 on its underside, i.e., on the side of the relay board rear pattern 33. Fig. 9 shows the relay board rear pattern 33 and the relay board front pattern 34 when the relay board 3 is connected to three individual packages 201. Fig. 9 also shows the case where the individual package 201 shown in Fig. 8 is rotated 90 degrees left and connected.

[0106] The relay board rear surface pattern 33 includes a third region 71 on the rear surface of the relay board, a first region 72 on the rear surface of the relay board, a second region 73 on the rear surface of the relay board, and a fourth region 74 on the rear surface of the relay board. The third region 71 on the rear surface of the relay board, the first region 72 on the rear surface of the relay board, the second region 73 on the rear surface of the relay board, and the fourth region 74 on the rear surface of the relay board are electrically connected to the third region 61 on the front surface of the printed wiring board, the first region 62 on the front surface of the printed wiring board, the second region 63 on the front surface of the printed wiring board, and the fourth region 64 on the front surface of the printed wiring board of the printed wiring board front surface pattern 32, respectively.

[0107] The relay substrate back surface pattern 33 includes, for example, six relay substrate back surface third regions 71, one relay substrate back surface first region 72, three relay substrate back surface second regions 73, and 18 relay substrate back surface fourth regions 74.

[0108] The numbers of the third regions 71, the first regions 72, the second regions 73, and the fourth regions 74 on the back surface of the relay board are not limited to those shown in FIG.

[0109] The relay board surface pattern 34 includes a third region 81 on the relay board surface, a first region 82 on the relay board surface, a second region 83 on the relay board surface, and a fourth region 84 on the relay board surface. The third region 81 on the relay board surface, the first region 82 on the relay board surface, the second region 83 on the relay board surface, and the fourth region 84 on the relay board surface are electrically connected to another mating member (not shown).

[0110] In Figure 9, the third region 71 on the back surface of the relay board is electrically connected to the third region 81 on the front surface of the relay board, the first region 72 on the back surface of the relay board is electrically connected to the first region 82 on the front surface of the relay board, the second region 73 on the back surface of the relay board is electrically connected to the second region 83 on the front surface of the relay board, and the fourth region 74 on the back surface of the relay board is electrically connected to the fourth region 84 on the front surface of the relay board.

[0111] The relay substrate surface pattern 34 includes, for example, six third regions 81 on the relay substrate surface, one first region 82 on the relay substrate surface, one second region 83 on the relay substrate surface, and eighteen fourth regions 84 on the relay substrate surface.

[0112] The number of third regions 81 on the relay board surface and the number of fourth regions 84 on the relay board surface are equal to or less than the number of third electrodes 21 and fourth electrodes 24 of semiconductor element 14. The sum of the numbers of third regions 81 on the relay board surface, first regions 82 on the relay board surface, second regions 83 on the relay board surface, and fourth regions 84 on the relay board surface is less than the sum of the numbers of third regions 61 on the printed wiring board surface, first regions 62 on the printed wiring board surface, second regions 63 on the printed wiring board surface, and fourth regions 64 on the printed wiring board surface included in printed wiring board surface pattern 32 of multiple individual packages 201 included in semiconductor device 101.

[0113] That is, the sum of the number of the third region 81 on the surface of the relay substrate, the first region 82 on the surface of the relay substrate, the second region 83 on the surface of the relay substrate, and the fourth region 84 on the surface of the relay substrate is less than the sum of the number of the third electrodes 21, the first electrodes 22, the second electrodes 23, and the fourth electrodes 24 possessed by the multiple semiconductor elements 14 included in the semiconductor device 101.

[0114] Furthermore, the sum of the number of first regions 82 on the surface of the relay substrate and the number of second regions 83 on the surface of the relay substrate is less than the sum of the number of first regions 62 on the surface of the printed wiring board and the number of second regions 63 on the surface of the printed wiring board included in the printed wiring board surface pattern 32 of the multiple individual packages 201 included in the semiconductor device 101.

[0115] Furthermore, the number of first regions 82 on the surface of the relay board and the number of second regions 83 on the surface of the relay board may be less than the number of first regions 62 on the surface of the printed wiring board and the number of second regions 63 on the surface of the printed wiring board, respectively.

[0116] Since the sum of the number of third regions 81 on the surface of the relay board, first regions 82 on the surface of the relay board, second regions 83 on the surface of the relay board, and fourth regions 84 on the surface of the relay board is less than the sum of the number of third regions 61 on the surface of the printed wiring board, first regions 62 on the surface of the printed wiring board, second regions 63 on the surface of the printed wiring board, and fourth regions 64 on the surface of the printed wiring board included in the printed wiring board surface pattern 32 of the multiple individual packages 201 included in the semiconductor device 101, the relay board surface pattern 34 is simplified and the wiring of the relay board 3 can be easily routed, making the design of the relay board 3 easier.

[0117] Furthermore, since the sum of the number of third regions 81 on the surface of the relay board, first regions 82 on the surface of the relay board, second regions 83 on the surface of the relay board, and fourth regions 84 on the surface of the relay board is less than the sum of the number of third electrodes 21, first electrodes 22, second electrodes 23, and fourth electrodes 24 of the multiple semiconductor elements 14 included in the semiconductor device 101, the number of third regions 81 on the surface of the relay board, first regions 82 on the surface of the relay board, second regions 83 on the surface of the relay board, and fourth regions 84 on the surface of the relay board that are connected to other mating components not shown can be reduced, and the semiconductor device 101 can be made smaller while maintaining the insulation distance.

[0118] Furthermore, the number of first regions 82 on the surface of the relay substrate and the number of second regions 83 on the surface of the relay substrate may be less than the number of first electrodes 22 and second electrodes 23, respectively.

[0119] The numbers of the third regions 81, the first regions 82, the second regions 83, and the fourth regions 84 on the surface of the relay board are not limited to those shown in FIG.

[0120] 10 is a schematic diagram of the top surfaces of the plurality of individual packages 201 and the bottom surface of the relay substrate 3 according to embodiment 1. The top surfaces of the plurality of individual packages 201 are indicated by dashed lines, and the relay substrate back surface pattern 33 provided on the bottom surface of the relay substrate 3 is indicated by solid lines. Even when the solid and dashed lines overlap, they are shifted for convenience.

[0121] The top surfaces of the multiple individual packages 201 shown by dashed lines correspond to the individual packages 201 shown in Fig. 8 rotated 90 degrees to the left. The relay board back surface pattern 33 shown by solid lines corresponds to that shown by dashed lines in Fig. 9.

[0122] As shown in Figure 10, the printed wiring board surface pattern 32 provided on the top surface of the individual package 201 is provided at a position corresponding to the relay board back pattern 33 provided on the relay board, and it can be seen that the printed wiring board surface pattern 32 and the relay board back pattern 33 are electrically connected.

[0123] 10 , for example, the plurality of conductive regions 92 are concentrated in a first region 72 on the back surface of the relay board 3 by the relay board 3. By concentrating the plurality of conductive regions 92 in the first region 72 on the back surface of the relay board, the relay board surface pattern 34 is simplified, and the routing of the wiring of the relay board 3 becomes easier, which makes it easier to design the relay board 3.

[0124] Second Embodiment A semiconductor device 102 according to a second embodiment will be described with reference to Figures 11 to 15. Descriptions of configurations similar to those of the first embodiment will be omitted. In Figures 11 to 15, the same reference numerals as those in Figures 1 to 10 indicate the same or corresponding parts.

[0125] Fig. 11 is a schematic side view of an individual package 202 included in a semiconductor device 102 according to embodiment 2. In Fig. 11, the first sealing resin 18 is omitted. As shown in Fig. 11, the individual package 202 according to this embodiment differs from the individual package 201 of embodiment 1 in the way in which the multiple semiconductor elements 14 included in the individual package 202 are arranged. The following description will focus on the differences from the individual package 201 of embodiment 1.

[0126] The individual package 202 includes two heat spreaders 12. The individual package 202 also includes two semiconductor elements 14. The two heat spreaders 12 are electrically connected to the two semiconductor elements 14, respectively. In other words, the heat spreader 12 is divided among the multiple semiconductor elements 14.

[0127] The individual package 202 includes a printed wiring board 17. The printed wiring board 17 includes a printed wiring board rear surface pattern 31 and a printed wiring board front surface pattern 32. The printed wiring board rear surface pattern 31 includes a first region 52 on the rear surface of the printed wiring board, a second region 53 on the rear surface of the printed wiring board, and a conductor 91.

[0128] The individual package 202 includes a conductive spacer 15. The conductive spacer 15 is electrically connected to one of the two heat spreaders 12, which is located on the right side of the paper surface of FIG.

[0129] The conductor 91 is electrically connected to the first electrode 22 of the semiconductor element 14 provided on one heat spreader 12 located on the right side of the paper in Figure 11, and to the other heat spreader 12 located on the left side of the paper in Figure 11 and to which the conductive spacer 15 is not connected.

[0130] The printed wiring board surface pattern 32 includes a conductive region 92. The conductor 91 and the conductive region 92 are electrically connected. That is, in FIG. 11 , two semiconductor elements 14 are connected in series between a first region 52 on the back surface of the printed wiring board and a second region 53 on the back surface of the printed wiring board. The semiconductor element 14 located on the left side of the paper is electrically connected to the semiconductor element 14 located on the right side of the paper via the heat spreader 12, the bonding material 16, and the conductor 91. The semiconductor element 14 located on the right side of the paper is electrically connected to the second region 53 on the back surface of the printed wiring board via the heat spreader 12 and the conductive spacer 15.

[0131] 12 is a schematic diagram of a printed wiring board rear surface pattern 31 and a printed wiring board front surface pattern 32 of the printed wiring board 17 included in the individual package 202 according to embodiment 2. The printed wiring board rear surface pattern 31 provided on the lower surface of the printed wiring board 17 is shown by a dashed line, and the printed wiring board front surface pattern 32 provided on the upper surface of the printed wiring board 17 is shown by a solid line. Even when the solid line and the dashed line overlap, they are shown shifted for convenience.

[0132] Conductor 91 included in printed wiring board rear surface pattern 31 is electrically connected to conductive region 92 included in printed wiring board front surface pattern 32. A third region 51 on the rear surface of the printed wiring board, a first region 52 on the rear surface of the printed wiring board, a second region 53 on the rear surface of the printed wiring board, and a fourth region 54 on the rear surface of the printed wiring board, which are included in printed wiring board rear surface pattern 31 and printed wiring board front surface pattern 32, are the same as those in the first embodiment, and therefore description thereof will be omitted.

[0133] Fig. 13 is a schematic top view of an individual package 202 according to embodiment 2. The individual package 202 is sealed with a first sealing resin 18. A portion of the printed wiring board surface pattern 32 of the printed wiring board 17 shown by the solid line in Fig. 12 is exposed from the first sealing resin 18. Note that the portion of the printed wiring board surface pattern 32 exposed from the first sealing resin 18 may be all or only a portion of the printed wiring board surface pattern 32.

[0134] 14 is a schematic diagram of the relay board rear pattern 33 and the relay board front pattern 34 of the relay board 3 according to embodiment 2. The relay board rear pattern 33 provided on the lower surface of the relay board 3 is shown by a dashed line, and the relay board front pattern 34 provided on the upper surface of the relay board 3 is shown by a solid line. Even when the solid line and the dashed line overlap, they are shown shifted for convenience.

[0135] The relay substrate 3 is connected to a plurality of individual packages 202. Fig. 14 shows a case where the relay substrate 3 is connected to three individual packages 202. Fig. 14 also shows a case where the individual package 202 shown in Fig. 13 is rotated 90 degrees left and connected.

[0136] The relay board rear surface pattern 33 includes an L-shaped terminal 93. The terminal 93 is electrically connected to the conductive region 92 of the printed wiring board front surface pattern 32. The terminal 93 is connected to other members (not shown). The other configurations are the same as those in FIG. 10 of the first embodiment, and therefore description thereof will be omitted.

[0137] 15 is a schematic diagram of the top surfaces of a plurality of individual packages 202 and the bottom surface of the relay substrate 3 according to embodiment 2. The top surfaces of the plurality of individual packages 202 are indicated by dashed lines, and the relay substrate back surface pattern 33 provided on the bottom surface of the relay substrate 3 is indicated by solid lines. Even when the solid and dashed lines overlap, they are shifted for convenience.

[0138] The top surfaces of the multiple individual packages 202 indicated by dashed lines correspond to the individual package 201 shown in Fig. 13 rotated 90 degrees to the left. The relay board back surface pattern 33 indicated by solid lines corresponds to that indicated by dashed lines in Fig. 14.

[0139] Third Embodiment A semiconductor device 103 according to a third embodiment will be described with reference to Fig. 16. Description of the same configuration as in the first embodiment will be omitted. In Fig. 16, the same reference numerals as in Figs. 1 to 15 indicate the same or corresponding parts.

[0140] 16 is a schematic cross-sectional view of a semiconductor device 103 according to embodiment 3. The semiconductor device 103 according to this embodiment differs from the individual package 201 according to embodiment 1 in that the semiconductor device 103 includes a thermally conductive adhesive layer 6 instead of the base bonding material 2 and the thermally conductive member 11. The following description will focus on the differences from the individual package 201 according to embodiment 1.

[0141] The semiconductor device 103 according to this embodiment includes a cooler 1, a thermally conductive adhesive layer 6 provided on the upper surface of the cooler 1, a plurality of individual packages 203 provided on the upper surface of the thermally conductive adhesive layer 6, an interconnect substrate 3 provided on the upper surfaces of the plurality of individual packages 203, and a second sealing resin 4 filling the spaces between the plurality of individual packages 203 and the interconnect substrate 3. The individual packages 203 do not include a thermally conductive member 11.

[0142] The individual package 203 is molded by, for example, a transfer molding method. The individual package 203 molded by the transfer molding method and the relay substrate 3 are sealed with a second sealing resin 4, and then the heat conductive adhesive layer 6 and the cooler 1 are bonded together by a heat press. The individual package 203 and the cooler 1 are bonded together via the heat conductive adhesive layer 6.

[0143] The thermally conductive adhesive layer 6 is formed of a composite material using a thermosetting resin such as an epoxy resin and a filler with high thermal conductivity such as crystalline silica, alumina, aluminum nitride, boron nitride, or silicon nitride.

[0144] The heat pressing is performed at a temperature equal to or higher than the temperature at which the resin component of the thermally conductive adhesive layer 6 melts, and at a pressure that is sufficient to crush voids contained inside the thermally conductive adhesive layer 6 .

[0145] Fourth Embodiment A semiconductor device 104 according to a fourth embodiment will be described with reference to Figures 17 and 18. Descriptions of configurations similar to those of the first embodiment will be omitted. In Figures 17 and 18, the same reference numerals as those in Figures 1 to 16 indicate the same or corresponding parts.

[0146] 17 is a schematic cross-sectional view of a semiconductor device 104 according to a fourth embodiment. The semiconductor device 104 according to the present embodiment differs from the individual package 201 according to the first embodiment in that it includes a filling portion 7. The following description will focus on the differences from the individual package 201 according to the first embodiment.

[0147] The semiconductor device 103 according to this embodiment includes a relay substrate 3. The relay substrate 3 includes a relay substrate back surface pattern 33, a relay substrate front surface pattern 34, and a second insulating plate 44. As shown in Fig. 17 , a filling portion 7 is provided on the upper and lower surfaces of the second insulating plate 44 in portions where the relay substrate back surface pattern 33 and the relay substrate front surface pattern 34 are not provided.

[0148] A filler such as a resist is filled into the filling section 7. It is desirable that the filler be filled into the filling section 7 before the relay board 3 is connected to the individual package 201.

[0149] Fig. 18 is a cross-sectional view of a relay board 3 according to embodiment 4. Note that Fig. 18 does not show the relay board surface pattern 34 of the relay board 3. Also, Fig. 18 does not show the filling portion 7 provided on the top surface of the relay board 3.

[0150] 18, a filling portion 7 is provided on the lower surface of the relay board 3. The filling portion 7 is provided in a portion where the relay board rear surface pattern 33 and the relay board front surface pattern 34 are not provided.

[0151] The filling portion 7 may partially cover the relay board back surface pattern 33 and the relay board front surface pattern 34. The filling portion 7 has an opening 8. The relay board back surface pattern 33 is exposed from the filling portion 7 at the opening 8. Furthermore, the relay board back surface pattern 33 is electrically connected to the printed wiring board front surface pattern 32 at the portion exposed at the opening 8.

[0152] The thickness of the printed wiring board surface pattern 32 of the relay board 3 is, for example, 0.1 mm or more. When the thickness of the printed wiring board surface pattern 32 is 0.1 mm or more, the difference in thickness between the portion of the relay board 3 where the printed wiring board surface pattern 32 is provided and the portion where the printed wiring board surface pattern 32 is not provided is larger than when the thickness of the printed wiring board surface pattern 32 is less than 0.1 mm.

[0153] If there is a large difference in thickness between the portion where the printed wiring board surface pattern 32 is provided and the portion where the printed wiring board surface pattern 32 is not provided, voids may occur between the respective regions included in the printed wiring board surface pattern 32 when filling with the second sealing resin 4. A state in which voids occur is undesirable because it results in poor filling properties. Therefore, when sealing with the second sealing resin 4, it is necessary to reduce the difference between the distance (narrow gap) between the relay board rear surface pattern 33 and the individual package 201 and the distance (maximum gap) between the second insulating plate 44 and the individual package 201.

[0154] In this embodiment, as shown in FIG. 17, a filling portion 7 is provided, so that deterioration of the filling property of the second sealing resin 4 can be suppressed even when the thickness of the relay substrate back surface pattern 33 of the relay substrate 3 is large.

[0155] The following describes a method for manufacturing the individual package 201. The individual package 201 includes the configuration shown in FIG.

[0156] First, the semiconductor element 14 is bonded to the heat spreader 12 using a die bond material 13. Then, the conductive spacer 15 is bonded to the heat spreader 12 using a bonding material 16. After that, the semiconductor element 14 and the conductive spacer 15 are bonded to the printed wiring board 17. Note that the order of bonding may be reversed.

[0157] Next, the member in which the heat spreader 12, the semiconductor element 14, and the printed wiring board 17 are joined together and the thermally conductive member 11 are sealed by a transfer molding method using a first sealing resin 18 (transfer molding resin). During sealing, electrodes are exposed by using a release film or by polishing and laser deburring so that electrodes are exposed on the metal foil 19 on the underside of the thermally conductive member 11 and on the printed wiring board 17, i.e., on the first region 62 and the second region 63 of the printed wiring board surface included in the printed wiring board surface pattern 32.

[0158] Fig. 19 is a schematic top view of a plurality of printed wiring boards 17 according to embodiments 1 to 4. Fig. 20 is a schematic top view of a plurality of individual packages 201 to 203 according to embodiments 1 to 4. Fig. 21 is a schematic top view of the individual packages 201 to 203 according to embodiments 1 to 4.

[0159] FIG. 19 shows a repeating pattern in which multiple printed wiring boards 17 are arranged on the same plane. When molding individual packages 201 using a transfer molding method, a substrate (repeated pattern) in which two or more wiring boards are repeatedly arranged on one substrate is used to obtain multiple individual packages 201. As shown in FIG. 19 , for example, rectangular gaps are formed between adjacent substrates to divide the printed wiring boards, and multiple hanging portions 25 are formed to connect the patterns in the gaps. That is, in the cut-out pattern, multiple printed wiring boards 17 are arranged on a plane with a gap (gap) between them and are connected to each other via multiple hanging portions 25. That is, the hanging portions 25 are portions that connect the multiple printed wiring boards 17 to each other.

[0160] After that, after molding with transfer molding resin, an integrated square package is obtained in which a plurality of individual packages 201 are arranged in succession, as shown in FIG.

[0161] Thereafter, the integrated package is cut by dicing to obtain individual packages 201. During dicing, the wiring substrate and transfer molding resin are cut at positions corresponding to the plurality of gaps and the plurality of suspension portions 25.

[0162] 21 , due to the presence of the hanging portions 25, a portion of the printed wiring board 17 is cut off in the dicing process, and an exposed portion is seen on the side of the individual package 201. That is, in the individual package 201, the printed wiring board 17 is exposed from the first sealing resin 18 on at least one of the surfaces perpendicular to the printed wiring board 17.

[0163] After cutting, the plurality of individual packages 201 are bonded to the relay substrate 3 , and then the gap between the individual packages 201 and the relay substrate 3 is sealed with a second sealing resin 4 .

[0164] The second sealing resin 4 is a liquid resin containing fine fillers called an underfill material, and seals the narrow gap by capillary action.

[0165] The second sealing resin 4 is filled in a syringe and injected from one direction to flow, while removing air between the individual package 201 and the relay substrate 3, to seal the package. At this time, a difference occurs between the narrow gap and the maximum gap in the filling section 7 depending on whether or not there is a circuit pattern on the relay substrate 3. When the difference between the gaps is large, the flow of the sealing resin is delayed in the maximum gap, which may result in entrapment voids and gaps. Therefore, it is desirable that the ratio of the narrow gap to the maximum gap be 10 times or less.

[0166] The molded metal foil 19 and the cooler 1 are joined by the base joining material 2. The joining may be performed by reflow, welding, soldering, or the like. When soldering is used, if the cooler 1 is made of copper or aluminum, it is desirable to plate the surface with nickel or the like.

[0167] Fifth Embodiment In this fifth embodiment, the semiconductor device according to the first to fourth embodiments is applied to a power conversion device. The present invention is not limited to a specific power conversion device, but the following will describe a case in which the present invention is applied to a three-phase inverter as the fifth embodiment.

[0168] FIG. 22 is a block diagram showing the configuration of a power conversion system to which a power conversion device according to a fifth embodiment of the present invention is applied.

[0169] The power conversion system shown in Fig. 22 includes a power supply 1000, a power conversion device 2000, and a load 3000. The power supply 1000 is a DC power supply and supplies DC power to the power conversion device 2000. The power supply 1000 can be configured from a variety of sources, such as a DC system, a solar cell, or a storage battery, or it can be configured from a rectifier circuit connected to an AC system, an AC / DC converter, or the like. The power supply 1000 can also be configured from a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0170] The power conversion device 2000 is a three-phase inverter connected between the power supply 1000 and the load 3000, and converts DC power supplied from the power supply 1000 into AC power and supplies the AC power to the load 3000. As shown in Fig. 18 , the power conversion device 2000 includes a main conversion circuit 2001 that converts DC power input from the power supply 1000 into AC power and outputs it, and a control circuit 2003 that outputs a control signal to the main conversion circuit 2001 to control the main conversion circuit 2001.

[0171] The load 3000 is a three-phase electric motor driven by AC power supplied from the power conversion device 2000. The load 3000 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for hybrid vehicles, electric vehicles, railway vehicles, elevators, air conditioning equipment, etc., for example.

[0172] The power conversion device 2000 will be described in detail below. The main conversion circuit 2001 includes switching elements and freewheel diodes (not shown) built into a semiconductor device 2002. The switching elements convert DC power supplied from the power supply 1000 into AC power, which is supplied to the load 3000. The main conversion circuit 2001 can have a variety of specific circuit configurations. The main conversion circuit 2001 according to this embodiment is a two-level, three-phase full-bridge circuit, and can be configured with six switching elements and six freewheel diodes connected in antiparallel to each switching element. The main conversion circuit 2001 is configured by a semiconductor device 2002 corresponding to any one of the above-described first to fourth embodiments, which incorporates the respective switching elements and freewheel diodes. Two of the six switching elements are connected in series to form upper and lower arms, and each upper and lower arm constitutes one phase (U phase, V phase, and W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 2001, are connected to the load 3000.

[0173] The main conversion circuit 2001 also includes a drive circuit (not shown) that drives each switching element. The drive circuit may be built into the semiconductor device 2002, or may be provided separately from the semiconductor device 2002. The drive circuit generates drive signals that drive the switching elements of the main conversion circuit 2001 and supplies them to the control electrodes of the switching elements of the main conversion circuit 2001. Specifically, in accordance with control signals from a control circuit 2003 (described later), the drive circuit outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. To maintain a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or greater than the threshold voltage of the switching element. To maintain a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or less than the threshold voltage of the switching element.

[0174] The control circuit 2003 controls the switching elements of the main conversion circuit 2001 so that the desired power is supplied to the load 3000. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 2001 should be in the on state based on the power to be supplied to the load 3000. For example, the main conversion circuit 2001 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 2003 also outputs a control command (control signal) to a drive circuit included in the main conversion circuit 2001 so that an on signal is output to a switching element that should be in the on state at each time point, and an off signal is output to a switching element that should be in the off state at each time point. In accordance with this control signal, the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0175] In the power conversion device of the fifth embodiment configured as described above, the semiconductor device of the first to fourth embodiments is applied as the semiconductor device 2002 of the main conversion circuit 2001, thereby achieving improved reliability.

[0176] In this embodiment, an example in which the present invention is applied to a two-level three-phase inverter has been described, but the present invention is not limited to this and can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used. In addition, when power is supplied to a single-phase load, the present invention may also be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load, the present invention may also be applied to a DC / DC converter, an AC / DC converter, or the like.

[0177] Furthermore, the power conversion device to which the present invention is applied is not limited to cases in which the above-mentioned load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, a non-contact power supply system, etc., and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0178] In the above-described embodiments, the materials, materials, dimensions, shapes, relative positional relationships, and implementation conditions of each component may be described. However, these are merely examples in all respects and are not intended to limit the scope of each embodiment. Therefore, countless variations not exemplified are contemplated within the scope of each embodiment. For example, these include cases where any component is modified, added, or omitted, and even cases where at least one component in at least one embodiment is extracted and combined with a component in another embodiment.

[0179] It goes without saying that various design modifications are possible within the scope of the present invention, as long as the object of the present invention can be achieved and the gist of the present invention is not deviated from.

[0180] 3 Interconnect board, 12 Heat spreader, 14 Semiconductor element, 15 Conductive spacer, 17 Printed wiring board, 18 First sealing resin, 22 First electrode, 23 Second electrode, 31 Printed wiring board rear surface pattern, 32 Printed wiring board front surface pattern, 33 Interconnect board rear surface pattern, 34 Interconnect board front surface pattern, 52 First region on rear surface of printed wiring board, 53 Second region on rear surface of printed wiring board, 62 First region on front surface of printed wiring board, 63 Second region on front surface of printed wiring board, 72 First region on rear surface of interconnect board, 73 Second region on rear surface of interconnect board, 82 First region on front surface of interconnect board, 83 Second region on front surface of interconnect board, 101, 102, 103, 104, 2002 Semiconductor device, 201, 202, 203 Individual package, 2000 Power conversion device, 2001 Main conversion circuit, 2003 Control circuit

Claims

1. A semiconductor device comprising: a plurality of individual packages; and an interconnection substrate that electrically connects the plurality of individual packages; the individual package includes a heat spreader, a plurality of semiconductor elements, and a printed wiring board; the semiconductor element is provided on the heat spreader and has a first electrode and a second electrode, the second electrode being located on one side of the heat spreader and the first electrode being located on the other side of the heat spreader; the printed wiring board includes a printed wiring board rear surface pattern provided on an opposite side of the heat spreader with respect to the semiconductor element, and a printed wiring board front surface pattern provided on an opposite side of the printed wiring board rear surface pattern with respect to the semiconductor element, the printed wiring board rear surface pattern includes a first region on the rear surface of the printed wiring board that is electrically connected to the first electrode, and a second region on the rear surface of the printed wiring board that is electrically connected to the second electrode via a conductive spacer provided on the heat spreader, the printed wiring board front surface pattern includes a first region on the printed wiring board front surface electrically connected to a first region on the back surface of the printed wiring board, and a second region on the printed wiring board front surface electrically connected to a second region on the back surface of the printed wiring board; the relay board is provided on the opposite side of the printed wiring board from the semiconductor element, and includes a relay board back surface pattern and a relay board front surface pattern provided on the opposite side of the relay board back surface pattern from the printed wiring board, and the relay board back surface pattern electrically connects the plurality of individual packages; the relay board rear surface pattern includes a first region on the relay board rear surface that is electrically connected to a first region on the printed wiring board front surface, and a second region on the relay board rear surface that is electrically connected to a second region on the printed wiring board front surface, the relay board front surface pattern includes a first region on the relay board front surface electrically connected to a first region on the relay board back surface, and a second region on the relay board front surface electrically connected to a second region on the relay board back surface, a total number of first regions on the surface of the printed wiring board and second regions on the surface of the printed wiring board included in the printed wiring board surface pattern is smaller than a total number of the first electrodes and the second electrodes of the plurality of semiconductor elements included in the plurality of individual packages; a total number of first regions on the surface of the relay board and second regions on the surface of the relay board included in the relay board surface pattern is smaller than a total number of first regions on the surface of the printed wiring board and second regions on the surface of the printed wiring board, Semiconductor device.

2. the second electrodes of the semiconductor elements are connected to each other on the heat spreader; 2. The semiconductor device according to claim 1, wherein the first region on the rear surface of the printed wiring board connects the first electrodes of the semiconductor elements together.

3. the heat spreader is divided among the plurality of semiconductor elements, and the conductive spacer is connected to one of the divided heat spreaders; 2. The semiconductor device according to claim 1, further comprising a conductor electrically connecting a first electrode of a semiconductor element provided on one of the divided heat spreaders connected to the conductive spacer to another of the divided heat spreaders to which the conductive spacer is not connected.

4. 2. The semiconductor device according to claim 1, wherein the intermediate substrate back surface pattern provided on the intermediate substrate has a thickness of 0.1 mm or more.

5. 3. The semiconductor device according to claim 2, wherein a filler is provided on a portion of the surface of the insulating plate included in the intermediate substrate on which the intermediate substrate rear pattern is provided, on which the intermediate substrate rear pattern is not provided.

6. 2. The semiconductor device according to claim 1, wherein the individual package is sealed with a sealing resin, and the printed wiring board is exposed from the sealing resin on at least one of the surfaces perpendicular to the printed wiring board.

7. a main conversion circuit having the semiconductor device according to any one of claims 1 to 6, which converts input power and outputs the converted power; a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit; A power conversion device comprising:

8. A process of providing a plurality of semiconductor elements on a heat spreader, each of the semiconductor elements having a first electrode and a second electrode, the second electrode being located on the side of the heat spreader and the first electrode being located on the opposite side of the heat spreader; providing a printed wiring board on the opposite side of the semiconductor element from the heat spreader; encapsulating the heat spreader, the semiconductor elements, and the printed wiring board to form an individual package; and providing an interconnection substrate on the opposite side of the printed wiring board from the semiconductor element, the printed wiring board includes a printed wiring board rear surface pattern provided on an opposite side of the heat spreader with respect to the semiconductor element, and a printed wiring board front surface pattern provided on an opposite side of the printed wiring board rear surface pattern with respect to the semiconductor element, the printed wiring board rear surface pattern includes a first region on the rear surface of the printed wiring board that is electrically connected to the first electrode, and a second region on the rear surface of the printed wiring board that is electrically connected to the second electrode via a conductive spacer provided on the heat spreader, the printed wiring board surface pattern includes a first region on the printed wiring board surface that is electrically connected to a first region on the back surface of the printed wiring board, and a second region on the printed wiring board surface that is electrically connected to a second region on the back surface of the printed wiring board; the relay board includes a relay board back surface pattern provided on the opposite side of the printed wiring board from the semiconductor element, and a relay board front surface pattern provided on the opposite side of the relay board back surface pattern, and the relay board back surface pattern electrically connects the plurality of individual packages; the relay board rear surface pattern includes a first region on the relay board rear surface that is electrically connected to a first region on the printed wiring board front surface, and a second region on the relay board rear surface that is electrically connected to a second region on the printed wiring board front surface, the relay board front surface pattern includes a first region on the relay board front surface electrically connected to a first region on the relay board back surface, and a second region on the relay board front surface electrically connected to a second region on the relay board back surface, a total number of first regions on the surface of the printed wiring board and second regions on the surface of the printed wiring board included in the printed wiring board surface pattern is smaller than a total number of the first electrodes and the second electrodes of the plurality of semiconductor elements; a total number of first regions on the surface of the relay board and second regions on the surface of the relay board included in the relay board surface pattern is smaller than a total number of first regions on the surface of the printed wiring board and second regions on the surface of the printed wiring board, A method for manufacturing a semiconductor device.