Power supply device and electronic apparatus
Patent Information
- Application Number
- JP2025541219
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Filing Date
- 2023-08-22
- Publication Date
- 2025-02-27
Abstract
Description
Power supply devices and electronic devices
[0001] The present invention relates to a power supply device including, for example, a voltage control section that is a linear regulator using a reference voltage generating circuit, and at least one current control section, and to an electronic device including the power supply device.
[0002] In a power supply device according to the prior art, for example, when a linear regulator is used, heat is generated according to the difference between the input voltage and the output voltage and the output current. The allowable amount of heat is determined by the substrate and mold. In other words, there is a limit to the output current of the linear regulator, and it may not be possible to satisfy the required load current value.
[0003] If one attempts to address this issue by connecting multiple linear regulators in parallel and connecting the output terminals of each linear regulator to a common load, then multiple linear regulators will end up with different output voltage settings due to variations in the manufacturing process, etc. As a result, the output current will be supplied by the linear regulator with the highest output voltage setting, while the output voltage of the linear regulator with the lowest output voltage setting will be fixed at a voltage higher than its own output voltage setting, causing the internal circuit to stop the output current.
[0004] As the load current increases, the output voltage begins to drop, so when the load current exceeds a certain level, if the output voltage setting falls below the output voltage setting of the lower linear regulator, that regulator will begin to supply output current. However, the output current supply balance is uneven, and the linear regulator with the lower output voltage setting cannot supply output current equal to that of the other linear regulator, which may result in the required load current not being met. Furthermore, in terms of reliability, an imbalance in output current also causes an imbalance in heat generation, which accelerates the lifespan of the linear regulator with the highest output current and may even lead to destruction.
[0005] In the above power supply circuit, if two linear regulators are connected in parallel with their input and output terminals in common, the output current supply will be uneven. A known technique for keeping the output currents of the two linear regulators equal is to have each linear regulator detect its own output current, convert it into an analog voltage signal, and output the voltage signal information from one linear regulator via its respective bus terminal, then input the voltage signal information to the other linear regulator and compare the two voltage signals.
[0006] Patent No. 7170935
[0007] In the conventional method of maintaining an equal current as described above, if an offset occurs due to factors such as variations in the manufacturing process, causing the slave side, which receives the current information, to flow more current than the master side, which outputs the current information, then even though the master side attempts to control the current to stop when there is no load, the slave side will continue to flow current, causing the output voltage to rise to the input voltage.
[0008] An object of the present invention is to provide a power supply device that can solve the above problems and prevent the output voltage from rising when there is no load or a light load, and an electronic device that includes the power supply device.
[0009] A power supply device according to one aspect of the present disclosure comprises a voltage control unit and a current control unit, and is configured by connecting the voltage control unit and each of the current control units in parallel with each other, wherein the voltage control unit comprises: a reference voltage circuit that generates a predetermined reference voltage based on an input voltage; and a voltage control circuit that generates and outputs the output voltage of the voltage control unit based on the input voltage by controlling the output current of the voltage control unit so that the output voltage of the voltage control unit becomes a voltage that substantially corresponds to the reference voltage, and the current control unit comprises: a first current detection circuit that detects the output current of the current control unit and generates and outputs a first current detection signal indicating a value corresponding to the output current; a current control circuit that controls the output current of the current control unit so that the first current detection signal becomes a value that substantially corresponds to the output current of the voltage control unit; and a startup control circuit that starts the current control circuit and controls the output current of the current control unit to flow when the output current of the voltage control unit becomes equal to or greater than a predetermined first threshold.
[0010] Therefore, according to a power supply device according to one aspect of the present disclosure, when there is no load or a light load, the output voltage can be prevented from rising to the input voltage, and the output voltage can be prevented from rising.
[0011] 11 is a circuit diagram showing an example of the configuration of a power supply device according to embodiment 1. FIG. 12 is a circuit diagram showing an example of the detailed configuration of a power supply device according to a modification of embodiment 1. FIG. 13 is a timing chart of currents and voltages showing the operation of the power supply device of FIG. 2. FIG. 14 is a circuit diagram showing an example of the configuration of a power supply device according to embodiment 2. FIG. 15 is a circuit diagram showing an example of the configuration of a power supply device according to embodiment 3. FIG. 16 is a circuit diagram showing an example of the configuration of a power supply device according to embodiment 4. FIG. 17 is a circuit diagram showing an example of the configuration of a power supply device according to embodiment 5. FIG. 18 is a circuit diagram showing an example of the configuration of a power supply device according to embodiment 6. FIG. 19 is a timing chart of currents and voltages showing the operation of the power supply device of FIG. 8. FIG. 19 is a circuit diagram showing an example of the configuration of a power supply device according to embodiment 7. FIG. 19 is a timing chart of currents and voltages showing the operation of the power supply device of FIG. 10. FIG. 19 is a circuit diagram showing an example of the configuration of a power supply device according to embodiment 8. FIG. 19 is a graph showing the relationship between each voltage and offset voltage Voffset and output current Iot in the power supply device of FIG. 12. FIG. 19 is a graph showing output currents Io1 and Io2 when an intentionally applied offset voltage is present and output current Iot in the power supply device of FIG. 12. 16 is a graph showing output currents Io1 and Io2 relative to the output current Iot in the power supply device of FIG. 12 when there is no intentionally applied offset voltage. FIG. 17 is a circuit diagram showing an example of the configuration of a power supply device according to embodiment 9. FIG. 18 is a graph showing the relationship between the output current Iot and the current flowing into a current-voltage conversion circuit in the power supply device of FIG. 14. FIG. 19 is a circuit diagram showing an example of the configuration of a power supply device according to embodiment 10. FIG. 19 is a timing chart showing current and voltage in the power supply device of FIG. 16. FIG. 20 is a block diagram showing the configuration of a power supply device according to a comparative example.
[0012] Hereinafter, embodiments and modifications of the present invention will be described with reference to the drawings, in which the same or similar components are designated by the same reference numerals.
[0013] (Inventor's Findings) FIG. 18 is a block diagram showing the configuration of a power supply device 61 according to a comparative example disclosed in Patent Document 1. In FIG.
[0014] 18, a power supply device 61 is configured to include a voltage control unit 1 and a current control unit 2. Here, the input terminal T11 of the voltage control unit 1 and the input terminal T21 of the current control unit 2 are connected to each other and to a voltage source of the input voltage Vin. The output terminal T13 of the voltage control unit 1 and the output terminal T23 of the current control unit 2 are connected to each other and to a load 3. As a result, the voltage control unit 1 and the current control unit 2 are connected in parallel to each other. Furthermore, the current detection signal output terminal T12 of the voltage control unit 1 and the current detection signal input terminal T22 of the current control unit 2 are connected to each other, and the ground terminal T14 of the voltage control unit 1 and the ground terminal T24 of the current control unit 2 are connected to each other and grounded. Note that in FIG. 18 and other figures, IN indicates an input terminal for the input voltage, OUT indicates an output terminal, BSout indicates an output terminal for the current detection signal BS1, BSin indicates an input terminal for the current detection signal BS, and GND indicates a ground terminal.
[0015] In the power supply device 61 configured as described above, the input voltage Vin is input to the input terminal T11 of the voltage control unit 1 and the input terminal T21 of the current control unit 2. The voltage control unit 1 is a linear regulator with a built-in reference voltage generation circuit, and controls the input voltage Vin to be the reference voltage. A total current Iouttotal, which is the sum of the output current Iout0 from the voltage control unit 1 and the output current Iout1 from the current control unit 2, flows through the load 3.
[0016] Furthermore, voltage control unit 1 generates current detection signal BS1, which is an analog voltage signal that corresponds to output current Iout0 with a predetermined correlation, for example, proportional to it, and outputs it from current detection signal output terminal T12 to current detection signal input terminal T22 of current control unit 2. In response to this, current control unit 2 generates a current detection signal, which is an analog voltage signal that corresponds to output current Iout1 with a predetermined correlation, for example, proportional to it, and compares this current detection signal with the input current detection signal BS1 to control the difference between them so that it becomes substantially zero, that is, the impedance of an output transistor (e.g., corresponding to MOS transistor Q11 in FIG. 1 ) that controls output current Iout1 of current control unit 2 is controlled so that output currents Iout0 and Iout1 become equal to each other, for example.
[0017] The load 3 is, for example, an electronic device having a predetermined function that receives a power supply voltage and a power supply current from the voltage control unit 1 and the current control unit 2, and specifically, is an electronic device for an automobile that receives a power supply, or an image forming device such as a copier or printer that receives a power supply, a personal computer, a tablet, a smartphone, a mobile phone, etc.
[0018] In the power supply device 61 configured as described above, the voltage control system in the voltage control unit 1 and the current control system in the current control unit 2 are separated and do not affect each other. Therefore, a more stable control system can be established compared to the prior art, and a power supply device 61 can be realized that can prevent unnecessary oscillations.
[0019] However, in the power supply device 61 of the comparative example that maintains current uniformity as described above, if an offset occurs due to the influence of variations in the manufacturing process, such that the slave-side current control unit 2 that receives current information flows more current than the master-side voltage control unit 1 that outputs current information, then even though the master-side voltage control unit 1 attempts to control the current to stop when there is no load, the slave-side current control unit 2 will continue to flow current, causing the output voltage Vout to rise to the input voltage Vin.
[0020] The object of the embodiments of the present invention is to provide a power supply device that can solve the above problems and prevent the output voltage from rising when there is no load or a light load, and an electronic device that is equipped with the power supply device, and each embodiment will be described below.
[0021] First Embodiment FIG. 1 is a circuit diagram showing an example of the configuration of a power supply device 51 according to a first embodiment.
[0022] 1, power supply device 51 is configured to include voltage control unit 101 and current control unit 201. Here, input terminal P1 (IN) of voltage control unit 101 and input terminals P2 (IN) of current control unit 201 are connected to each other and to a voltage source of input voltage Vin. Furthermore, output terminal P2 (OUT) of voltage control unit 101 and output terminal P12 (OUT) of current control unit 201 are connected to each other and to a load 301. As a result, voltage control unit 101 and current control unit 201 are connected in parallel to each other. Furthermore, output terminal P4 (BSmout) that outputs a current detection signal (current I3) of voltage control unit 101 and input terminal P14 (BSmin) that inputs a current detection signal (current I3) of current control unit 102 are connected to each other. Furthermore, an output terminal P5 (BSout) that outputs the current-voltage converted signal (converted voltage V13) of the voltage control unit 101 and an input terminal P15 (BSin) that inputs the current-voltage converted signal (converted voltage V13) of the current control unit 102 are connected to each other. A ground terminal P3 of the voltage control unit 101 and a ground terminal P13 of the current control unit 201 are connected to each other and grounded.
[0023] In power supply device 51 configured as described above, input voltage Vin is input to input terminal P1 of voltage control unit 101, which constitutes a reference voltage linear regulator that determines output voltage Vout, and is also input to input terminal P11 of current control unit 201. Output current Io1 from output terminal P2 of voltage control unit 101 and output current Io2 from output terminal P12 of current control unit 201 are added together, and then added current Iot flows to load 301. An analog current detection signal (current I3) detected in voltage control unit 101 has a correlation with output current Io1, for example, a proportional relationship with it, and is input to current control unit 201 via output terminal P4 and input terminal P14 of current control unit 201. The current control section 201 generates a current-voltage conversion signal (converted voltage V23) that has a correlation with the output current Io2 of the current control section 201 and corresponds, for example, in a proportional relationship, and by comparing the current-voltage conversion signal (converted voltage V13) of the voltage control section 101 with the current-voltage conversion signal (converted voltage V23) of the current control section 201, the impedance of the output transistor Q11 of the current control section 201 is controlled so that the output currents Io1 and Io2 become equal to each other. Note that the current-voltage conversion signal is an example of a current detection signal, and the same applies in the following specification.
[0024] The voltage control unit 101 is a reference voltage linear regulator and includes a reference voltage generation circuit 11, an operational amplifier circuit 12, a current-voltage conversion circuit 13, PMOS transistors Q1 to Q3, and voltage-dividing resistors R1 and R2. The reference voltage generation circuit 11 generates a predetermined reference voltage Vref based on an input voltage Vin and outputs it to the inverting input terminal of the operational amplifier circuit 12. The operational amplifier circuit 12 subtracts the reference voltage Vref from a feedback voltage Vfb divided by the voltage-dividing resistors R1 and R2, amplifies the result, and outputs the amplified error voltage V12 to the gates of the PMOS transistors Q1 to Q3.
[0025] The PMOS transistor Q1 controls the output current I1 generated from the input voltage Vin based on the error voltage V12, generates the output current Io1, and outputs it from the output terminal P2 to the load 301. The PMOS transistor Q2 generates a detection current I2 (=a·I1 (a>0)) from the input voltage Vin, which is correlated with the output current Io1, for example, proportional to it, and outputs it to the current-voltage conversion circuit 13. The current-voltage conversion circuit 13 converts the detection current I2 into a corresponding, for example, proportional, detection voltage and outputs it as a current-voltage conversion signal (converted voltage V13) to the input terminal P15 of the current control unit 201 via the output terminal P5. The PMOS transistor Q3 generates a detection current I3 (=b·I1 (b>0)) from the input voltage Vin, which is correlated with the output current Io1, for example, proportional to it, and outputs it to the input terminal P14 of the current control unit 201 via the output terminal P4. The voltage dividing resistors R1 and R2 divide the output voltage Vout generated by the output current Io1 into a feedback voltage Vfb, which is output to the non-inverting input terminal of the operational amplifier circuit 12.
[0026] In the voltage control unit 101 configured as described above, a feedback control circuit (voltage control circuit) constituted by the operational amplifier circuit 12, the PMOS transistor Q1, and voltage dividing resistors R1 and R2 controls the output current I1 of the PMOS transistor Q1, which is an output transistor, so that the divided voltage Vfb becomes the reference voltage Vref.
[0027] The current control unit 201 includes an operational amplifier circuit 21, a current detection circuit 22, a current-voltage conversion circuit 23, and PMOS transistors Q11 and Q12. The operational amplifier circuit 21 subtracts the current-voltage conversion signal (converted voltage V13) from the current-voltage conversion signal (converted voltage V23) from the current-voltage conversion circuit 23, amplifies the resulting error voltage V21, and outputs the resulting error voltage V21 to the gates of the PMOS transistors Q11 and Q12. The PMOS transistor Q11 controls the output current I11 generated from the input voltage Vin based on the error voltage V21 to generate an output current Io2, which is output from the output terminal P12 to the load 301. The PMOS transistor Q12 generates a detection current I12 (=c·I11 (c>0)) that is correlated with the output current Io2, for example, proportionally, from the input voltage Vin, and outputs the detection current I12 to the current-voltage conversion circuit 23.
[0028] The current-voltage conversion circuit 23 converts the detected current I12 into a corresponding, for example proportional, detected voltage and outputs the converted current-voltage signal (converted voltage V23) to the non-inverting input terminal of the operational amplifier circuit 21. Based on the current I3 input to the input terminal P14, the current detection circuit 22 generates a low-level current detection signal S22 and outputs it as a non-start signal to the start-up control terminal of the operational amplifier circuit 21 when the current I3 is less than a predetermined third threshold current. On the other hand, when the current I3 is equal to or greater than the third threshold current (i.e., when the output current I1 is equal to or greater than a predetermined first threshold current), the current detection signal S22 generates a high-level current detection signal and outputs it as a start-up signal to the start-up control terminal of the operational amplifier circuit 21, thereby activating the current control circuit including the operational amplifier circuit 21 and controlling the output current of the current control unit. The operational amplifier circuit 21 activates and performs operational amplification in response to a high-level voltage detection signal, but does not activate in response to a low-level voltage detection signal.
[0029] Here, the current detection circuit 22 is an example of a start-up control circuit. The start signal and the non-start signal are collectively called a start-up control signal. The start-up control signal is a signal generated by the start-up control circuit.
[0030] In the current control unit 201 configured as described above, when the output current I1 corresponding to the current I3 is equal to or greater than a predetermined first threshold current, a feedback control circuit (current control circuit) composed of the current detection circuit 22, the PMOS transistor Q12, and the current-voltage conversion circuit 23 controls the output current I11 of the PMOS transistor Q11, which is an output transistor, so that the output currents Io1 and Io2 are equal to each other. On the other hand, when a current equal to or greater than a predetermined third threshold current does not flow into the current detection circuit 22, the operation of the operational amplifier circuit 21 is stopped, and the operation of the PMOS transistor Q11, which is an output transistor connected to the output terminal of the operational amplifier circuit 21, is controlled to stop, so that the output current Io2 of the current control unit 201 is not generated.
[0031] In power supply device 51 configured as described above, output current Io1 from voltage control unit 101 and output current Io2 from current control unit 201 are generally set to be substantially the same. However, for example, if an offset voltage Voff is added to operational amplifier circuit 21 due to manufacturing variations (hereinafter referred to as the first case), or if a systematic offset voltage is generated due to a predetermined gain of the feedback control circuit in current control unit 201 (hereinafter referred to as the second case), output currents Io1 and Io2 will no longer be substantially the same.
[0032] In the first example of the former case, it is assumed that the input resistance of the current-voltage conversion circuits 13 and 23 is Rin [Ω] and the current mirror ratio of the current I1 and the current I2 is A1:A2 (A2 / A1=a), then the output current difference ΔI between the output transistors Q1 and Q11 with respect to the offset voltage Voff generated in the operational amplifier circuit 21 is expressed by the following equation:
[0033] ΔI=Voff×A1 / (A2×Rin) (1)
[0034] Consider a situation where an offset voltage Voff is generated such that the output current I11 of the output transistor Q11 is greater than the output current I1 of the output transistor Q1, and the output terminals P2 and P12 are in an unloaded state with no load 3 connected. Even though voltage control unit 101 stops outputting output current Io1 to maintain output voltage Vout at a predetermined value, current control unit 201 flows a predetermined output current Io2, causing the output voltage Vout of output terminals P2 and P12 to rise to the input voltage Vin of input terminals P1 and P11. Even in the latter second case, if the systematic offset voltage causes current control unit 201 to flow the predetermined output current Io2, the output voltage Vout of output terminals P2 and P12 will rise to the input voltage Vin of input terminals P1 and P11. Therefore, the above problem is solved by controlling current control unit 201 not to flow a current until an output current Io1 equal to or greater than the above-mentioned current difference or the first threshold current begins to flow.
[0035] As described above, according to the first embodiment, the current control unit 201 is provided with the current detection circuit 22, and the current detection circuit 22 controls the operational amplifier circuit 21 so as not to start up when the output current I3 corresponding to the current I1 is less than the third threshold current. Therefore, even when the offset voltage Voff is added to the operational amplifier circuit 21, it is possible to prevent the output voltage Vout from increasing.
[0036] Therefore, the power supply device 51 according to the first embodiment can monitor the drive state of the master-side voltage control unit 101 and, as necessary, can control the slave-side current control unit 201 to suppress the current output, thereby preventing the output voltage Vout from rising to the input voltage Vin. In other words, when there is no load or a light load, the output of the output current Io2 from the slave-side current control unit 201 can be stopped, thereby preventing the output voltage Vout from rising.
[0037] In the first embodiment, the output current Io2 of the current control unit 2 is controlled so that the output current Io1 of the voltage control unit 1 and the output current Io2 of the current control unit 2 are substantially equal to each other. However, the output current Io2 of the current control unit 2 may be controlled by current distribution so that the ratio between the output current Io1 of the voltage control unit 1 and the output current Io2 of the current control unit 2 is a predetermined value.
[0038] (Modification of First Embodiment) Fig. 2 is a circuit diagram showing a detailed configuration example of a power supply device 51A according to a modification of the first embodiment, and Fig. 2 shows a detailed configuration example of the current detection circuit 22. Note that differences from Fig. 1 will be described below.
[0039] 2, the current detection circuit 22 includes a diode-connected NMOS transistor Q13, a comparator 221, and a reference voltage generation circuit 222. The reference voltage generation circuit 222 includes two switches SW1 and SW2, two voltage sources 223 and 224 having voltages V223=A3×Idet and V224=A3×Idet / 2, respectively, and an inverter INV1, where A3 is a current-voltage conversion coefficient.
[0040] A current I3 input to an input terminal P14 is grounded via the drain and source of an NMOS transistor Q13 and converted to a corresponding voltage V3, which is then applied to the non-inverting input terminal of a comparator 221. The comparator 221 compares the converted voltage V3 with a reference voltage Vref2 from a reference voltage generation circuit 222. When V3<Vref2, the comparator 221 generates a low-level current detection signal S22, which is output as a non-start signal to the startup control terminal of the operational amplifier circuit 21. When V3≧Vref2, the comparator 221 generates a high-level current detection signal S22, which is output as a start signal to the startup control terminal of the operational amplifier circuit 21. The current detection signal S22 from the comparator 221 is input to the control terminal of a switch SW2 and, via an inverter INV1, to the control terminal of a switch SW1. The switches SW1 and SW2 are each turned on when a high-level control signal is input to their control terminals, and turned off when a low-level control signal is input to their control terminals.
[0041] Here, the comparator 221 and the reference voltage generating circuit 222 are an example of a switching control circuit.
[0042] In the current control unit 201 configured as described above, as the current I3 of the PMOS transistor Q3, which is the monitor transistor, increases, the drain voltage V3 of the diode-connected NMOS transistor Q13 rises. In order to detect the rise in voltage V3, the comparator 221 compares this voltage V3 with the reference voltage Vref2 of the reference voltage generation circuit 222 to generate a current detection signal S22.
[0043] In the current detection circuit 22 of the current control section 201 shown in FIG. 2, the NMOS transistor Q13 may be replaced with a series circuit of a resistor and a bias current source.
[0044] Fig. 3 is a timing chart of currents and voltages showing the operation of the power supply device 51A in Fig. 2. The operation of the power supply device 51A in Fig. 2 will be described below with reference to Fig. 3.
[0045] At time t1 in FIG. 3, when current control unit 201 is activated, current control unit 201 shares half of the total output current Iot (see FIG. 3A), causing a drop in converted voltage V13 from current-voltage conversion circuit 13. At this time, currents Io1 and Io2 of output transistors Q1 and Q11 are roughly equal to each other and are shunted to about half of the total output current Iot, causing current I3 of monitor transistor Q3 to be about half its maximum value (see FIG. 3B). If the threshold current Irel for current I3, which disables current control unit 201, is not less than half the startup detection threshold current Idet of current control unit 201, current control unit 201 will be disabled again. Therefore, to prevent chattering, a hysteresis characteristic is provided so that release threshold current Irel is less than half the startup detection threshold current Idet. Furthermore, the voltage sources 223 and 224 used at this time are preferably adjusted to have voltages V223=A3×Idet and V224=A3×Idet / 2, respectively, to meet the above conditions.
[0046] As described above, according to the modification of the first embodiment, as shown in Fig. 3(c), it is possible to selectively switch between starting and stopping of the current control unit 201 with a predetermined hysteresis characteristic by selectively switching between the voltage sources 223 and 224 using the current detection signal S22 of the comparator 221. This prevents unintentional release of the current control unit 201 after it has been started, thereby preventing oscillations such as chattering caused by repeated starting and stopping.
[0047] (Embodiment 2) FIG. 4 is a circuit diagram showing an example of the configuration of a power supply device 52 according to embodiment 2. In FIG. 4, the power supply device 52 according to embodiment 2 differs from the power supply device 51 of FIG. 1 in the following respects: (1) A current control unit 201A is provided instead of the current control unit 201. (2) In the current control unit 201A, a current detection circuit 22A is provided instead of the current detection circuit 22. The current detection circuit 22A includes a diode-connected NMOS transistor Q14 serving as a monitor transistor, a comparator 221, and a reference voltage generation circuit 225. Here, the reference voltage generation circuit 225 generates a predetermined reference voltage Vref3 and outputs it to the inverting input terminal of the comparator 221. (3) The current control unit 201A further includes a PMOS transistor Q13 serving as a monitor transistor. The source of the PMOS transistor Q13 is connected to the input terminal P11, and the gate of the PMOS transistor Q13 is connected to the output terminal of the operational amplifier circuit 21. The PMOS transistor Q13 has a correlation with the output current I11 and generates a current I13 (=d·I11 (d>0)) proportional to the output current I11, for example, and causes the current I13 to flow into the drain and gate of the NMOS transistor Q14. The differences will be described below.
[0048] In the current control unit 201A of FIG. 4, the detection target of the current detection circuit 22A is the current value obtained by adding the current I13 corresponding to the output current I11 of the current control unit 201A to the current I3, and the NMOS transistor Q14 converts this current value into a voltage which is applied to the non-inverting input terminal of the comparator 221.
[0049] Here, the current detection circuit 22A is an example of a start-up control circuit.
[0050] In power supply device 52 configured as described above, when current control unit 201A is activated, current control unit 201 is responsible for generating half of the output current Io1 of voltage control unit 101, so the detection current of monitor transistor Q3 in FIG. 1 decreases, but the sum of output current Io1 of voltage control unit 101 and output current Io2 of current control unit 201 remains unchanged, so the detected current value of monitor transistor Q14 remains the same as the detected current value of monitor transistor Q3 before current control unit 201A was activated. Therefore, power supply device 52 according to the second embodiment has the same effects as power supply device 51, and can suppress oscillations triggered by fluctuations in detection information accompanying the activation of current control unit 201A.
[0051] (Embodiment 3) Fig. 5 is a circuit diagram showing an example of the configuration of a power supply device 53 according to embodiment 3. In Fig. 5, the power supply device 53 according to embodiment 3 differs from the power supply device 51A of Fig. 2 in the following respects: (1) Instead of the voltage control unit 101, a voltage control unit 101A is provided in which the PMOS transistor Q3 and the output terminal P4 are deleted. (2) Instead of the current control unit 201, a current control unit 201B is provided in which the input terminal P14 is deleted. The current control unit 201B further includes a reference voltage generation circuit 222 and a comparator 24 in place of the current detection circuit 22. The differences will be described below.
[0052] 5, converted voltage V13 input from current-voltage conversion circuit 13 to input terminal P15 is applied to the inverting input terminal of operational amplifier circuit 21 and the non-inverting input terminal of comparator 24. Reference voltage generation circuit 222 is configured similarly to that shown in FIG. 2, and comparator 24 outputs current detection signal S24 (which is a voltage detection signal because comparator 24 compares two input voltages, but is originally a current detection signal corresponding to the output current of current control unit 101A, and will therefore be referred to as a "current detection signal"; the same applies hereinafter) to the start-up control terminal of operational amplifier circuit 21. This signal is also input to the control terminal of switch SW2 in reference voltage generation circuit 222 and to the control terminal of switch SW1 via inverter INV1. Switches SW1 and SW2 are each turned on when an H-level control signal is input to their control terminals, and turned off when an L-level control signal is input to their control terminals.
[0053] Here, the comparator 24 is an example of a start-up control circuit, and the comparator 24 and the reference voltage generating circuit 222 are an example of a switching control circuit.
[0054] The power supply device 53 configured as described above is characterized in that it determines whether or not to activate the current control unit 201B based on the converted voltage V13 from the current-voltage conversion circuit 13. Specifically, this is as follows: The comparator 24 compares the converted voltage V13 with the reference voltage Vref4 from the reference voltage generation circuit 222, and when V13<Vref4, it generates an L-level current detection signal S24 and outputs it to the activation control terminal of the operational amplifier circuit 21 as a non-activation signal, whereas when V13≧Vref4, it generates an H-level current detection signal S24 and outputs it to the activation control terminal of the operational amplifier circuit 21 as a activation signal.
[0055] In the current control unit 201B configured as described above, the comparator 24 generates a current detection signal S24 by comparing the converted voltage V13 with the reference voltage Vref4 of the reference voltage generation circuit 222. As in the second embodiment, the reference voltage Vref4 is selectively switched with a hysteresis characteristic to prevent chattering, which occurs when the current control unit 201B is repeatedly enabled and disabled. At this time, the release current needs to be equal to or less than half the detection current corresponding to the detection voltage, and the voltage values V223 and V224 of the voltage sources 223 and 224 are set by referring to whether or not the converted voltage V13 has reached a predetermined reference voltage Vref4 and the converted voltage V13 when the release current corresponds to the predetermined release voltage.
[0056] As described above, the third embodiment has the same effects as the second embodiment.
[0057] (Fourth Embodiment) Fig. 6 is a circuit diagram showing an example of the configuration of a power supply device 54 according to a fourth embodiment. In Fig. 6, the power supply device 54 according to the fourth embodiment differs from the power supply device 53 of Fig. 5 in the following respects: (1) A current control unit 201C is provided instead of the current control unit 201B. (2) In the current control unit 201C, an adder circuit 25 and a reference voltage generation circuit 26 are provided instead of the reference voltage generation circuit 222. The differences will be described below.
[0058] 6, converted voltage V13 input to input terminal P15 is input to the inverting input terminal of operational amplifier circuit 21 and the first input terminal of adder circuit 25. Converted voltage V23 from current-voltage conversion circuit 23 is input to the second input terminal of adder circuit 25, and adder circuit 25 adds the voltages input to the two input terminals and outputs the resulting voltage (V13+V23) to the non-inverting input terminal of comparator 24. Reference voltage generation circuit 26 generates a predetermined reference voltage Vref5 that activates or deactivates current control unit 201C and outputs it to the inverting input terminal of comparator 24. The comparator 24 compares the sum voltage (V13+V23) with the reference voltage Vref5, and when (V13+V23)<Vref5, generates an L-level current detection signal S24 and outputs it to the start-up control terminal of the operational amplifier circuit 21 as a non-start-up signal, while when (V13+V23)≧Vref5, generates an H-level current detection signal S24 and outputs it to the start-up control terminal of the operational amplifier circuit 21 as a start-up signal.
[0059] In power supply device 54 configured as described above, the voltage to be detected used to determine whether current control unit 201C is activated is the sum (V13 + V23) of the converted voltages of current-voltage conversion circuits 13 and 23. When current control unit 201C is activated, current control unit 201C bears half of the output current Io1 of voltage control unit 101A, and therefore converted voltage V13 of current-voltage conversion circuit 13 drops. However, because the sum Iot (= Io1 + Io2) of the output currents of voltage control unit 101A and current control unit 201C remains unchanged, the sum of the current information of voltage control unit 101A and current control unit 201C output by current-voltage conversion circuits 13 and 23 remains unchanged.
[0060] As described above, according to the fourth embodiment, the current detection information does not fluctuate significantly even after the current control unit 201C is started, and the operational amplifier circuit 21 is started based on the fluctuation in the current detection information accompanying the start-up of the current control unit 201C. This prevents the current control unit 201C from being unintentionally released after it is started, thereby making it possible to prevent oscillations such as chattering caused by repeated start-up and stop.
[0061] Fifth Embodiment Fig. 7 is a circuit diagram showing an example of the configuration of a power supply device 55 according to a fifth embodiment. In Fig. 7, the power supply device 55 according to the fifth embodiment differs from the power supply device 51 of Fig. 1 in the following respects: (1) Instead of the voltage control unit 101, a voltage control unit 101B is provided, from which the PMOS transistor Q3, the output terminal P4, and the current-voltage conversion circuit 13 are omitted. (2) Instead of the current control unit 201, a current control unit 201D is provided. Here, instead of the current detection circuit 22 and the current-voltage conversion circuit 23 of the current control unit 201, a reference current generation circuit 28, a current mirror circuit CM1, an inverter INV2, and a diode-connected NMOS transistor Q17 are provided. The differences will be described below.
[0062] In the voltage control unit 101B of FIG. 7, the current I2 flowing through the PMOS transistor Q2 is input to the input terminal P15 of the current control unit 201D via the output terminal P5.
[0063] In the current control unit 201D, the current mirror circuit CM1 is configured to include NMOS transistors Q15 and Q16. Here, the input terminal P15 is grounded via the drain and source of the diode-connected NMOS transistor Q15, and the gate of the NMOS transistor Q15 is connected to the gate of the NMOS transistor Q16. The current I2 input to the input terminal P15 is converted to a voltage V13 by the NMOS transistor Q15 of the current mirror circuit CM1, and then input to the inverting input terminal of the operational amplifier circuit 21.
[0064] The reference current generating circuit 28 generates a predetermined reference current Iref based on the input voltage Vin applied to the input terminal P11 and outputs it to the drain of the NMOS transistor Q16. The output terminal of the reference current generating circuit 28 is grounded via the drain and source of the NMOS transistor Q16. The reference current Iref from the reference current generating circuit 28 flows into the NMOS transistor Q16 of the current mirror circuit CM1, while a current I16 corresponding to the current flowing through the NMOS transistor Q15 flows out of the NMOS transistor Q16. In other words, the current value flowing through the NMOS transistor Q16 is Iref-I16, and a voltage V91 corresponding to the current value (Iref-I16) is generated at the drain of the NMOS transistor Q16. The voltage V91 is input to the startup control terminal of the operational amplifier circuit 21 via the inverter INV2 as a voltage detection signal S93, which is a startup signal.
[0065] Furthermore, the drain of the PMOS transistor Q12 is grounded via the drain and source of a diode-connected NMOS transistor Q17, whose drain and gate are connected to the non-inverting input terminal of the operational amplifier circuit 21.
[0066] Here, the inverter INV2, the reference current generating circuit 28, and the current mirror circuit CM1 are an example of a startup control circuit.
[0067] In the power supply device 55 configured as described above, when the output current Io1 of the voltage control unit 101B increases and I16 corresponding to the output current Io1 increases, the voltage V91 corresponding to the current value (Iref-I16) becomes equal to the threshold voltage V of the inverter INV2. ＩＮＶ＿ＴＨ Therefore, the voltage detection signal of the inverter INV2 changes from L level to H level, and the start-up control signal of the inverter INV2 becomes an H-level start-up signal, starting up the operational amplifier circuit 21.
[0068] As described above, according to the fifth embodiment, the current mirror circuit CM1 copies information about the current I2 corresponding to the output current Io1 of the voltage control unit 101B to the current I16 of the current mirror circuit CM1 in the current control unit 201D, whereby the current I16 proportional to the output current Io1 of the voltage control unit 101B is compared with the reference current Iref, and the comparison result signal is used as a start-up control signal for the operational amplifier circuit 21.
[0069] In the fifth embodiment, a current mirror circuit CM1 including a diode-connected NMOS transistor Q15 and a diode-connected NMOS transistor Q17 are used, without using the current-voltage conversion circuits 13 and 23 using resistors according to the first to fourth embodiments. This makes it possible to generate a determination circuit for the start-up control signal of the operational amplifier circuit 21 of the current control unit 201D extremely easily, without the need to separately provide a constant voltage generation circuit, comparator, or the like.
[0070] Sixth Embodiment FIG. 8 is a circuit diagram showing an example of the configuration of a power supply device 56 according to a sixth embodiment. FIG. 9 is a timing chart of currents and voltages showing the operation of the power supply device 56 of FIG. 8. In FIG. 8, the power supply device 56 differs from the power supply device 55 of FIG. 7 in the following respects: (1) A current control unit 201E is provided instead of the current control unit 201D. (2) In the current control unit 201E, a reference current generation circuit 28A is provided instead of the reference current generation circuit 28. (3) The reference current generation circuit 28A includes constant current sources 29a and 29b having constant currents I29a and I29b (I29a + I29b > I29a), respectively, and a PMOS transistor Q29, which is a switch transistor. In FIG. 8, the current values in the reference current generation circuit 28A are set as follows:
[0071] Iref_det=I29a+129b (when PMOS transistor Q29 is on) (2)
[0072] Iref_rel=I29a (when PMOS transistor Q29 is off) (3)
[0073] Here, as shown in FIG. 9C, Iref_rel<Iref_det / 2 (4) holds.
[0074] The differences will be explained below.
[0075] 8, input terminal P11 is connected to the drain of NMOS transistor Q16 via constant current source 29a, and is also connected to the drain of NMOS transistor Q16 via constant current source 29b and the source and drain of PMOS transistor Q29. A current detection signal S93 from inverter INV2 is applied to the gate of NMOS transistor Q29. PMOS transistor Q29 is turned off in response to the current detection signal S93 at a high level, and turned on in response to the current detection signal S93 at a low level.
[0076] Here, the inverter INV2, the reference current generating circuit 28A, and the current mirror circuit CM1 are an example of a startup control circuit, and the inverter INV2 and the reference current generating circuit 28A are an example of a switching control circuit.
[0077] The current control section 201E configured as above is characterized in that the reference current Iref is selectively switched to either the current I29a or the added current (I29a+I29b) in response to the current detection signal S93.
[0078] As in the fifth embodiment shown in FIG. 7, when the current control unit 201E is activated, the current control unit 201E generates half of the total output current Iot (see FIG. 9(a)), so that the voltage V13 corresponding to the current I2 drops, and the current I16 flowing through the NMOS transistor Q16 of the current mirror circuit CM1 decreases. Normally, when the current I1 of the output transistor Q1 becomes equal to or greater than a predetermined threshold current, as shown in FIG. 9(b), the current mirror circuit CM1 detects this at time t2, and the drain voltage V91 of the NMOS transistor Q16 changes from H level to L level, and the drain voltage V91 becomes equal to or lower than the threshold V of the inverter INV2. ＩＮＶ＿ＴＨ When the transition occurs, the start control signal S93 that controls the enable of the operational amplifier circuit 21 changes from the L level to the H level.
[0079] However, if the reference current Iref of the reference current generating circuit 28A remains unchanged, the current of the NMOS transistor Q16 of the current mirror circuit CM1 corresponding to the output current Io1 of the voltage control unit 101B decreases, causing the drain voltage V91 to change from low to high, disabling the operational amplifier circuit 21 and resulting in chattering, as described above. Therefore, the reference current Iref from the reference current generating circuit 28A is switched from equation (2) to equation (3), and a hysteresis characteristic is provided in the characteristic of the voltage V91 versus the current I16 so that it does not fall below the release threshold. In other words, to prevent chattering, it is preferable to set the current value Iref of the reference current generating circuit 280 to a current value Iref_rel, which is less than half the current value Iref, as shown in FIG. 9C, when the current detection signal S93 of the operational amplifier circuit 21 changes from low to high.
[0080] As described above, the power supply device 56 according to the sixth embodiment has the same effect as that of the fifth embodiment, and furthermore, by preventing unintentional deactivation after the current control unit 201E is started, it is possible to prevent oscillation caused by repeated starting and stopping.
[0081] Seventh Embodiment Fig. 10 is a circuit diagram showing an example of the configuration of a power supply device 57 according to a seventh embodiment. Fig. 11 is a timing chart of currents and voltages showing the operation of the power supply device of Fig. 10. In Fig. 10, the power supply device 57 according to the seventh embodiment differs from the power supply device 55 of Fig. 7 in the following respects: (1) A current control unit 201F is provided instead of the current control unit 201D. (2) The current control unit 201F further includes an NMOS transistor Q18, and the NMOS transistor Q18 and the NMOS transistor Q17 form a current mirror circuit CM2. The differences will be explained below.
[0082] 10, the gates and sources of the diode-connected NMOS transistor Q17 and the NMOS transistor Q18 are connected to each other to form a current mirror circuit CM2. The current I18 of the NMOS transistor Q18 is a monitor current I12 that is proportional to the output current Io2=I11 of the current control unit 201F, and is a current proportional to the monitor current I12.
[0083] The current control unit 201F in FIG. 10 differs from the fifth embodiment in FIG. 7 in that the current to be detected in the current detection signal S93 used to determine the start-up of the current control unit 201F is the sum of the current I16 of the NMOS transistor Q16 in the current mirror circuit CM1 and the current I18 of the NMOS transistor Q18 in the current mirror circuit CM2.
[0084] Here, the inverter INV2, the reference current generating circuit 28, and the current mirror circuits CM1 and CM2 are an example of a startup control circuit.
[0085] When the current control unit 201F is started at time t3 in Figure 11, the current control unit 201F takes on half of the total output current Iot, so the current I16 decreases. However, since the sum current Iot of the output currents Io1 and Io2 of the voltage control unit 101B and current control unit 201F does not change (see Figure 11 (a)), the sum current amount of the current mirror circuits CM1 and CM2, which is correlated with the sum of the output current information of each control unit 101B and 201F, does not change.
[0086] As described above, embodiment 7 has the same effect as embodiment 6, and since the current detection information does not fluctuate significantly even after the current control unit 201F is started, it is possible to suppress the oscillation phenomenon triggered by the fluctuation in the current detection information accompanying the start-up of the current control unit 201F.
[0087] Eighth Embodiment Fig. 12 is a circuit diagram showing an example of the configuration of a power supply device 58 according to an eighth embodiment. In Fig. 12, the power supply device 58 according to the eighth embodiment differs from the power supply device 53 of Fig. 5 in the following respects: (1) A current control unit 201G is provided instead of the current control unit 201B. Compared to the current control unit 201B, the current control unit 201G is provided with an offset voltage source 30 having an offset voltage V30 instead of the reference voltage generation circuit 222 and the comparator 24. It should be noted that the current detection signal, which is a start-up control signal to the operational amplifier circuit 21, is not used. The differences will be described below.
[0088] 12, an offset voltage source 30 is provided at the non-inverting input terminal of the operational amplifier circuit 21 so that the output current Io2 of the current control unit 201 is intentionally lower than the output current Io1 of the voltage control unit 101A. That is, the sum voltage of the converted voltage V23 from the current-voltage conversion circuit 23 and the offset voltage Voffset is applied to the non-inverting input terminal of the operational amplifier circuit 21.
[0089] 1 , the phenomenon in which the output voltage Vout rises to the input voltage Vin of the input terminal T1 occurs because the current control unit 201 continues to pass the output current Io2 even though the voltage control unit 101 tries to maintain the output voltage Vout by stopping the output current Io1. When the current control unit 201 is started, an offset voltage is applied to the operational amplifier circuit 21 so that the voltage is controlled to be higher than the voltage at its non-inverting input terminal, which causes the above phenomenon to become apparent.
[0090] Fig. 13A is a graph showing the relationship between each voltage and offset voltage Voffset relative to output current Iot in power supply device 58 of Fig. 12. Fig. 13B is a graph showing output currents Io1 and Io2 relative to output current Iot in power supply device 58 of Fig. 12 when intentionally applied offset voltage Voffset is present. Fig. 13C is a graph showing output currents Io1 and Io2 relative to output current Iot in power supply device 58 of Fig. 12 when intentionally applied offset voltage Voffset is not present.
[0091] To avoid this phenomenon, an offset voltage source 30 is provided in the operational amplifier circuit 21 as shown in FIG. 12. As shown in FIG. 13A, the converted voltage V23 is controlled to be lower than the converted voltage V13, and the output current Io2 of the current control unit 201G is cut off when there is no load. Furthermore, until the transistor Q1 in the voltage control unit 101A flows an output current Iot1 equal to or greater than a certain level and the converted voltage V13 becomes greater than the offset voltage source 30, the voltage V231 at the non-inverting input terminal of the operational amplifier circuit 21 becomes higher, and the PMOS transistor Q12 and the output transistor Q11 are controlled to be turned off. As shown in FIGS. 13B and 13C, the offset voltage source 30 prevents the current control unit 201G from starting unnecessarily when there is no load, preventing the output voltage Vout from rising, even without providing a circuit to shut down the operational amplifier circuit 21. In other words, the offset voltage source 30 corresponds to a component of one of the startup control circuits in the first to seventh embodiments described above.
[0092] 14 is a circuit diagram showing an example of the configuration of a power supply device 59 according to the ninth embodiment. In FIG. 14, the power supply device 59 according to the ninth embodiment differs from the power supply device 58 according to the eighth embodiment in FIG. 12 in the following respects: (1) A current control unit 201H is provided instead of the current control unit 201G. (2) In the current control unit 201H, a bias voltage generation circuit 31 and a PMOS transistor Q19 are provided instead of the offset voltage source 30. The differences will be described below.
[0093] 14, input terminal P11 of current control unit 201H is connected to the input terminal of current-voltage conversion circuit 23 via the source and drain of PMOS transistor Q19, which is a bias transistor. Bias voltage generation circuit 31 generates a predetermined bias voltage Vbias and applies it to the gate of PMOS transistor Q19. PMOS transistor Q19 generates current I19 corresponding to bias voltage Vbias and causes it to flow into current-voltage conversion circuit 23. In other words, the current flowing into current-voltage conversion circuit 23 is the sum of current I12 and current I19, and current-voltage conversion circuit 23 generates converted voltage V23 corresponding to the sum current (I12 + I19) and applies it to the non-inverting input terminal of operational amplifier circuit 21.
[0094] FIG. 15 is a graph showing the relationship between the output current Iot and the current flowing into the current-voltage conversion circuits 13 and 23 in the power supply device 59 of FIG.
[0095] 15 and 14, in the power supply device 59 configured as above, under conditions in which Iot is smaller than IotA in FIG. 15, the current I2 detected by the current-voltage conversion circuit 13 (current detection circuit) of the voltage control unit 101A becomes smaller than the bias current I19 from the bias voltage generation circuit 31, and the converted voltage V23 becomes larger than the converted voltage V13, so that the PMOS transistor Q12 and the output transistor Q11 are controlled to be turned off.
[0096] As described above, according to the ninth embodiment, the bias voltage generation circuit 31 and the PMOS transistor Q19 are provided to add the offset voltage Voffset similar to that of the eighth embodiment. Here, the bias voltage generation circuit 31 causes the operational amplifier circuit 21 to recognize that the current control unit 201H is passing a larger current than the voltage control unit 101A, and an offset is applied so that the current control unit 201H tends to reduce the output current Io2. Therefore, the power supply device 59 according to the ninth embodiment has the same effects as the power supply device 58 according to the eighth embodiment.
[0097] Tenth Embodiment Fig. 16 is a circuit diagram showing an example of the configuration of a power supply device 60 according to a tenth embodiment. In Fig. 16, the power supply device 60 according to the tenth embodiment differs from the power supply device 59 according to the ninth embodiment shown in Fig. 14 in the following respects: (1) A current control unit 201I is provided instead of the current control unit 201H. (2) Compared to the current control unit 201H, the current control unit 201I further includes a reference voltage generating circuit 32, a comparator 33, and a PMOS transistor Q20. The differences will be described below.
[0098] 16, input terminal P11 of current control unit 201I is connected to the input terminal of current-voltage conversion circuit 23 via the source and drain of PMOS transistor Q19 and the source and drain of PMOS transistor Q20. Conversion voltage V13 input to input terminal P15 is input to the non-inverting input terminal of operational amplifier circuit 21 and the non-inverting input terminal of comparator 33. Reference voltage generation circuit 32 outputs a predetermined reference voltage Vref6 to the inverting input terminal of comparator 33. When conversion voltage V13<Vref6, comparator 33 applies a low-level current detection signal S33 to the gate of PMOS transistor Q20, turning on PMOS transistor Q20 and allowing offset current I19 to flow. On the other hand, when conversion voltage V13≧Vref6, comparator 33 applies a high-level current detection signal S33 to the gate of PMOS transistor Q20, turning off PMOS transistor Q20 and preventing offset current I19 from flowing.
[0099] Here, the NMOS transistor Q20, the comparator 33, and the reference voltage generating circuit 32 are an example of a switching control circuit.
[0100] The current control unit 201I configured as described above is characterized in that the start-up control of the operational amplifier circuit 21 by the comparator 24 of the power supply device 53 in FIG. 5 is realized by the reference voltage of the operational amplifier circuit 21 controlled by the current of the PMOS transistor Q20.
[0101] FIG. 17 is a timing chart showing the current and voltage in the power supply device 60 of FIG.
[0102] 17, when the output current Iot is equal to or less than a certain value, the voltage detection signal S33 of the comparator 33 goes low, turning on the PMOS transistor Q20, and adding an offset current I19 to reduce the output current Io2 of the current control unit 201I relative to the output current Io1 of the voltage control unit 101A. By turning off the PMOS transistor Q20 at the timing (time t4) when the output current Io2 of the current control unit 201I begins to flow to a certain extent, the offset current I19 of the current control unit 201I is not allowed to flow. This suppresses bias in the output current when the output current is equal to or greater than a predetermined threshold value.
[0103] As described above, according to the tenth embodiment, under light load conditions, the output current Io2 of the current control unit 201I is reduced so that the output voltage Vout does not rise, and when a predetermined threshold output current begins to flow, the PMOS transistor Q20 is turned off, thereby adjusting the current balance of the control units 101A and 201I, thereby making it possible to prevent current imbalance under heavy load conditions, which are greatly affected by heat generation.
[0104] (Modifications) In the power supply devices according to the above embodiments, examples have been shown in which the devices are used in voltage control circuits, but this is merely an example, and the present invention is not limited to this, and can be applied to all control circuits that use operational amplifier circuits. For example, the present invention may be applied to current control circuits.
[0105] As described above in detail, the power supply device according to the present invention is capable of monitoring the drive state of the voltage control unit on the master side and controlling the current output of the current control unit on the slave side to suppress it as necessary, thereby preventing the output voltage from rising to the input voltage.
[0106] An electronic device may be configured including the power supply devices 51 to 60 according to the embodiments and a load 301. The electronic device may be, for example, an electronic device for an automobile that receives power supply, an image forming device such as a copier or printer that receives power supply, a personal computer, a tablet, a smartphone, a mobile phone, or the like.
[0107] 1, 101, 101A to 101B Voltage control section 2, 201, 201A to 201I Current control section 3, 301 Load 11 Reference voltage generation circuit 12 Operational amplifier circuit 13 Current-voltage conversion circuit 21 Operational amplifier circuit 22, 22A Current detection circuit 23 Current-voltage conversion circuit 24 Comparator 25 Adder circuit 26 Reference voltage generation circuit 28, 28A, 29 Reference current generation circuit 29a, 29b Constant current source 30 Offset voltage source 31 Bias voltage generation circuit 32 Reference voltage generation circuit 33 Comparator 51 to 61, 51A Power supply device 221 Comparator 222 Reference voltage generation circuit 223, 224 Voltage source 225 Reference voltage generation circuit CM1, CM2 Current mirror circuit INV1, INV2 Inverter Q1 to Q29 MOS transistors R1, R2 Voltage dividing resistors SW1, SW2 Switches T11 to T24, P1 to P15 Terminals
Claims
1. A power supply device comprising a voltage control unit and a current control unit, the voltage control unit and each of the current control units being connected in parallel to each other, the voltage control unit comprising: a reference voltage circuit that generates a predetermined reference voltage based on an input voltage; and a voltage control circuit that generates and outputs the output voltage of the voltage control unit based on the input voltage by controlling the output current of the voltage control unit so that the output voltage of the voltage control unit becomes a voltage that substantially corresponds to the reference voltage, the current control unit comprising: a first current detection circuit that detects the output current of the current control unit and generates and outputs a first current detection signal indicating a value corresponding to the output current; a current control circuit that controls the output current of the current control unit so that the first current detection signal becomes a value that substantially corresponds to the output current of the voltage control unit; and a startup control circuit that starts up the current control circuit to control the output current of the current control unit to flow when the output current of the voltage control unit becomes equal to or greater than a predetermined first threshold value.
2. The power supply device of claim 1, wherein the voltage control unit or the current control unit further comprises a second current detection circuit that detects the output current of the voltage control unit and generates and outputs a second current detection signal indicating a value corresponding to the output current, and the startup control circuit controls to start up the current control circuit when the second current detection signal becomes equal to or greater than a predetermined second threshold value.
3. The power supply device according to claim 2, further comprising a first switching control circuit which selectively switches the second threshold value from a predetermined first value to a predetermined second value smaller than the first value when the value of the second current detection signal becomes equal to or greater than the second threshold value.
4. The power supply device according to claim 2, wherein the startup control circuit controls so as to start up the current control circuit when the sum of the first current detection signal and the second current detection signal becomes equal to or greater than a predetermined third threshold value.
5. The power supply device according to claim 2, wherein the startup control circuit controls so as to start up the current control circuit when the second current detection signal becomes equal to or greater than the sum of the first current detection signal and a predetermined offset value.
6. The power supply device according to claim 2, wherein the startup control circuit controls so as to start up the current control circuit when the second current detection signal becomes equal to or greater than the sum of the first current detection signal and a predetermined bias current value.
7. The power supply device according to claim 6, wherein the startup control circuit further comprises a second switching control circuit that switches the bias current value to zero when the value of the second current detection signal becomes equal to or greater than a predetermined third threshold value.
8. An electronic device comprising the power supply device according to claim 1 or 2 and a load of the electronic device.
9. An electronic device comprising the power supply device according to claim 3 and a load of the electronic device.
10. An electronic device comprising the power supply device according to any one of claims 4 to 7 and a load of the electronic device.