Capacitor and method for manufacturing same

Abstract

This capacitor (1A) comprises: an insulating substrate (10) having a main surface (10a); a capacitance forming part (20) provided on the main surface (10a); and first external connection wiring and second external connection wiring connected to the capacitance forming part (20). The capacitance forming part (20) includes a conductive uneven or porous structure (21) connected to the first external connection wiring, a dielectric film (22a) covering the surface of the structure (21), and a conductive film (23) covering a part of the dielectric film (22a) and connected to the second external connection wiring. The outermost surface of the capacitance forming part (20) has an uneven shape. The dielectric film (22a) has an exposed portion (222) that is not covered by the conductive film (23), and a non-exposed portion (221) that is covered by the conductive film (23). An outer edge of the capacitance forming part (20) in a direction parallel to the main surface (10a) is defined by the exposed portion (222).

Description

Capacitor and manufacturing method thereof

[0001] The present invention relates to a capacitor having a capacitance forming portion made up of a conductive structure, a dielectric film, and a conductive film, and to a method for manufacturing the same.

[0002] For example, Japanese Patent Laid-Open No. 2003-249417 (Patent Document 1), Japanese Patent Laid-Open No. 2008-130778 (Patent Document 2), and Japanese Patent Laid-Open No. 2009-49212 (Patent Document 3) disclose capacitors each having a capacitance-forming portion made up of a conductive structure consisting of a plurality of pillars, a dielectric film covering the surface of the structure, and a conductive film covering the dielectric film.

[0003] Furthermore, U.S. Patent Publication No. 2018 / 0277306 (Patent Document 4) discloses a capacitor in which a conductive structure is formed of a porous metal body instead of a plurality of columns. In the capacitor disclosed in Patent Document 4, the porous metal body constituting the structure is formed of a sintered body of metal particles, and both the dielectric layer and the conductive film are formed by atomic layer deposition (ALD). In this capacitor, the outermost surface of the capacitance forming portion has an uneven shape.

[0004] JP 2003-249417 A JP 2008-130778 A JP 2009-49212 A U.S. Patent Publication No. 2018 / 0277306

[0005] In a capacitor having a capacitance forming portion with an uneven outermost surface, such as the capacitor disclosed in Patent Document 4, film stresses occurring in the dielectric film and conductive film, etc., or externally applied stresses may be concentrated on the outer edge of the capacitance forming portion after mounting, causing damage such as cracks in that portion. Such damaged portions are prone to short circuits, resulting in a loss of functionality as a capacitor.

[0006] Therefore, the present invention has been made to solve the above-mentioned problems, and aims to improve the reliability after mounting in a capacitor having a capacitance forming portion consisting of a conductive structure, a dielectric film, and a conductive film, and to make it possible to manufacture such a capacitor.

[0007] A capacitor according to the present invention comprises an insulating substrate having a main surface, a capacitance-forming portion provided on the main surface, and first and second external connection wirings connected to the capacitance-forming portion. The capacitance-forming portion includes a conductive uneven or porous structure connected to the first external connection wiring, a dielectric film covering the surface of the structure, and a conductive film covering a portion of the dielectric film and connected to the second external connection wiring. The outermost surface of the capacitance-forming portion has an uneven shape. The dielectric film has an exposed portion not covered by the conductive film and a non-exposed portion covered by the conductive film. In the capacitor according to the present invention, the outer edge of the capacitance-forming portion in a direction parallel to the main surface is defined by the exposed portion.

[0008] A method for manufacturing a capacitor according to a first aspect of the present invention comprises the following steps: (a) preparing an insulating substrate having a main surface; (b) forming a first external connection wiring on the insulating substrate; (c) forming a conductive uneven or porous structure on the main surface; (d) forming a first dielectric film to cover the surface of the structure when the structure and the first external connection wiring are connected to each other; (e) forming a conductive film to cover the surface of the first dielectric film when the first dielectric film is formed, thereby forming a capacitance-forming portion consisting of the structure, the first dielectric film, and the conductive film, and having an uneven outermost surface; (f) forming a second external connection wiring connected to the conductive film when the capacitance-forming portion is formed; and (g) forming a resist film to cover a portion of the surface of the second external connection wiring other than the outer edge of the conductive film in a direction parallel to the main surface when the conductive film and the second external connection wiring are connected to each other. (h) a step of removing a portion of the second external connection wiring that is not covered by the resist film and a portion of the conductive film that is covered by the second external connection wiring, with the resist film having been formed; (i) a step of removing the resist film with the portion of the second external connection wiring and the portion of the conductive film having been removed.

[0009] A method for manufacturing a capacitor according to a second aspect of the present invention comprises the following steps: (a) preparing an insulating substrate having a main surface; (b) forming a first external connection wiring on the insulating substrate; (c) forming a conductive uneven or porous structure on the main surface; (d) forming a first dielectric film so as to cover the surface of the structure when the structure and the first external connection wiring are connected to each other; (e) forming a second dielectric film having adhesion to a conductive film so as to cover the surface of the first dielectric film when the first dielectric film has been formed; and (f) forming a third dielectric film having no adhesion to the conductive film so as to cover the surface of an outer edge of the second dielectric film in a direction parallel to the main surface when the second dielectric film has been formed. (g) forming the conductive film so as to cover the surface of the second dielectric film in a portion not covered by the third dielectric film when the third dielectric film has been formed, thereby forming a capacitance-forming portion having an uneven outermost surface and including the structure, the first dielectric film, the second dielectric film, the third dielectric film, and the conductive film; and (h) forming a second external connection wiring connected to the conductive film when the capacitance-forming portion has been formed.

[0010] A method for manufacturing a capacitor according to a third aspect of the present invention includes the following steps: (a) preparing an insulating substrate having a main surface; (b) forming a first external connection wiring on the insulating substrate; (c) forming a conductive uneven or porous structure on the main surface; (d) forming a first dielectric film so as to cover the surface of the structure when the structure and the first external connection wiring are connected to each other; (e) forming a resist film so as to cover an outer edge of the first dielectric film in a direction parallel to the main surface when the first dielectric film has been formed; (f) forming a second dielectric film having adhesion to a conductive film so as to cover the resist film and portions of the first dielectric film not covered by the resist film when the resist film has been formed; and (g) removing the resist film and portions of the second dielectric film covering the resist film when the second dielectric film has been formed. (h) forming a capacitance-forming portion having an uneven outermost surface, the capacitance-forming portion being made of the structure, the first dielectric film, the second dielectric film, and the conductive film, by forming the conductive film so as to cover the surface of the second dielectric film in the portion that has not been removed, in a state where the resist film and a portion of the second dielectric film have been removed; (i) forming a second external connection wiring connected to the conductive film in a state where the capacitance-forming portion has been formed.

[0011] According to the present invention, in a capacitor having a capacitance forming portion consisting of a conductive structure, a dielectric film, and a conductive film, it is possible to improve the reliability after mounting, and further to manufacture such a capacitor.

[0012] 4A and 4B are schematic front and plan views of a capacitor according to a first embodiment; a schematic cross-sectional view of the capacitor shown in FIG. 1; an enlarged cross-sectional view of a main portion of the capacitance forming portion shown in FIG. 2; a flow diagram showing a method for manufacturing a capacitor according to the first embodiment; a schematic cross-sectional view for illustrating step S5 of the manufacturing flow shown in FIG. 4; a schematic cross-sectional view for illustrating step S6 of the manufacturing flow shown in FIG. 4; a schematic cross-sectional view for illustrating step S7 of the manufacturing flow shown in FIG. 4; a schematic cross-sectional view for illustrating step S8 of the manufacturing flow shown in FIG. 4; a schematic cross-sectional view for illustrating step S9 of the manufacturing flow shown in FIG. 4; a schematic cross-sectional view for illustrating step S10 of the manufacturing flow shown in FIG. 4; a schematic cross-sectional view for illustrating step S11 of the manufacturing flow shown in FIG. 4; a schematic cross-sectional view for illustrating step S12 of the manufacturing flow shown in FIG. 4; a schematic cross-sectional view for illustrating step S13 of the manufacturing flow shown in FIG. 4; a schematic cross-sectional view for illustrating step S14 of the manufacturing flow shown in FIG. 4; a schematic cross-sectional view for illustrating step S15 of the manufacturing flow shown in FIG. 4; a schematic cross-sectional view for illustrating step S16 of the manufacturing flow shown in FIG. 4; a schematic cross-sectional view of a capacitor according to a first modified example; 25 is a schematic cross-sectional view of a capacitor according to a second modified example. It is a schematic cross-sectional view of a capacitor according to embodiment 2. It is an enlarged cross-sectional view of a main part of the capacitance forming portion shown in FIG. 19. It is a flow diagram showing a method for manufacturing a capacitor according to embodiment 2. It is a schematic cross-sectional view for explaining step S9B1 of the manufacturing flow shown in FIG. 21. It is a schematic cross-sectional view for explaining step S9B2 of the manufacturing flow shown in FIG. 21. It is a schematic cross-sectional view for explaining step S10 of the manufacturing flow shown in FIG. 21. It is a schematic cross-sectional view of a capacitor according to embodiment 3. It is an enlarged cross-sectional view of a main part of the capacitance forming portion shown in FIG. 25. It is a flow diagram showing a method for manufacturing a capacitor according to embodiment 3. It is a schematic cross-sectional view for explaining step S12 of the manufacturing flow shown in FIG. 27. It is a schematic cross-sectional view for explaining step S9B1 of the manufacturing flow shown in FIG. 27. It is a schematic cross-sectional view for explaining step S14 of the manufacturing flow shown in FIG. 27. It is a schematic cross-sectional view for explaining step S10 of the manufacturing flow shown in FIG. 27. It is a schematic cross-sectional view of a capacitor according to embodiment 4.32 . An enlarged sectional view of a main part of the capacitance forming portion shown in FIG. 32 . A flow diagram showing a method for manufacturing a capacitor according to embodiment 4. A schematic sectional view showing a state after completion of step S5 of the manufacturing flow shown in FIG. 34 . A schematic sectional view for explaining step S5D of the manufacturing flow shown in FIG. 34 . A schematic sectional view of a capacitor according to embodiment 5. An enlarged sectional view of a main part of the capacitance forming portion shown in FIG. 37 . A flow diagram showing a method for manufacturing a capacitor according to embodiment 5. A schematic sectional view of a capacitor according to embodiment 6. An enlarged sectional view of a main part of the capacitance forming portion shown in FIG. 40 . A flow diagram showing a method for manufacturing a capacitor according to embodiment 6. A schematic sectional view of a capacitor according to embodiment 7. A flow diagram showing a method for manufacturing a capacitor according to embodiment 7. A schematic sectional view of a capacitor according to embodiment 8. A schematic sectional view of a capacitor according to embodiment 9.

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the embodiments described below, identical or common parts are designated by the same reference numerals in the drawings, and their description will not be repeated. In addition, in the embodiments described below, the terms "anode" and "cathode" are used for the sake of convenience, but the electrical polarity of the capacitor in the embodiments described below is not uniquely determined by these terms, and the electrical polarity is determined appropriately according to the environment in which the capacitor is used.

[0014] (Embodiment 1) Fig. 1(A) is a schematic front view of a capacitor according to embodiment 1. Fig. 1(B) is a schematic plan view of the capacitor as viewed from the direction of arrow IB shown in Fig. 1(A). Fig. 2 is a schematic cross-sectional view of the capacitor taken along line II-II shown in Fig. 1(B). Figs. 3(A) and 3(B) are enlarged cross-sectional views of essential portions of regions IIIA and IIIB, respectively, of the capacitance forming portion shown in Fig. 2. First, the configuration of a capacitor 1A according to this embodiment will be described with reference to Figs. 1 to 3.

[0015] 1 and 2, capacitor 1A has a flat, approximately rectangular parallelepiped outer shape, and both its bottom and top surfaces are configured as mounting surfaces for a wiring board or the like. Capacitor 1A mainly comprises an insulating substrate 10, a capacitance forming portion 20, and a sealing portion 30. Of these, capacitance forming portion 20 is provided so as to face insulating substrate 10. Capacitance forming portion 20 is located inside capacitor 1A by being sealed by insulating substrate 10 and sealing portion 30 provided on insulating substrate 10.

[0016] The insulating substrate 10 is provided with a first via conductor 13 and a first bump 16. The first via conductor 13 and the first bump 16 constitute one of a pair of external connection wirings for electrically connecting the capacitance forming portion 20 located inside the capacitor 1A to an external circuit. More specifically, the pair of external connection wirings includes a first external connection wiring as an anode and a second external connection wiring as a cathode, and the first via conductor 13 and the first bump 16 constitute a part of the first external connection wiring. The second external connection wiring is composed of an extraction electrode 18, a second via conductor 14, and a second bump 17, which will be described later.

[0017] The insulating substrate 10 is a flat plate-shaped member having a first main surface 10a as a main surface and a second main surface 10b located on the opposite side of the first main surface 10a. As the insulating substrate 10, it is preferable to use a substrate having electrical insulation properties, and preferably a substrate containing an inorganic material as a main component. More specifically, the insulating substrate 10 can be made of, for example, Si, Al ２ O ３ , ZrO ２ , BN, Si ３ N ４ , AlN, MgO, Mg ２ SiO ４ , BaTiO ３ , SrTiO ３ and CaTiO ３ A substrate made mainly of any of the above can be used.

[0018] The thickness and size of the insulating substrate 10 are not particularly limited, but it is preferable to use an alumina substrate that is rectangular in plan view, for example, with a thickness of 5 μm or more and 75 μm or less and a side length of 500 μm or more and 2000 μm or less.

[0019] A first through hole 11 is provided in the insulating substrate 10. The first through hole 11 penetrates the insulating substrate 10 so as to reach from the first main surface 10a to the second main surface 10b. The first through hole 11 is filled with a first via conductor 13. The shape of the first via conductor 13 is, for example, approximately cylindrical.

[0020] The first via conductor 13 constitutes a part of the first external connection wiring described above. When viewed along the normal direction of the first main surface 10 a of the insulating substrate 10, the first via conductor 13 is provided within the region in which the capacitance forming portion 20 is arranged.

[0021] The first via conductors 13 can be made of various wiring materials, but are preferably made of a metal material with particularly high electrical conductivity. The material of the first via conductors 13 can be, for example, a metal material primarily made of Ni, Ag, Cu, Au, Pt, Mo, or W. The material of the first via conductors 13 can be changed as appropriate to suit the mounting environment of the capacitor 1A according to this embodiment. In this embodiment, the first via conductors 13 are made of Ni.

[0022] The axial length and size of first via conductor 13 are not particularly limited and are set appropriately depending on the thickness and size of insulating substrate 10. Here, the axial length of first via conductor 13 is preferably, for example, 5 μm or more and 75 μm or less, and the diameter is preferably, for example, 15 μm or more and 150 μm or less. In this embodiment, first via conductor 13 is made of Ni and has an axial length of 75 μm and a diameter of 150 μm.

[0023] First bumps 16 are provided on the second main surface 10b of the insulating substrate 10 so as to cover the first via conductors 13. The first bumps 16 serve as a bonding material for mounting the capacitor 1A on a wiring board or the like and for electrically connecting the capacitance forming portions 20 of the capacitor 1A to an external circuit. The first bumps 16 are provided so as to protrude from the second main surface 10b of the insulating substrate 10. The shape of the first bumps 16 is approximately hemispherical. The first bumps 16 constitute part of the above-mentioned first external connection wiring.

[0024] The first bump 16 can be made of various wiring materials, but is preferably made of a metal material with particularly high electrical conductivity. The material of the first bump 16 can be, for example, a metal material containing any of Ni, Ag, Cu, Au, and Sn as the main component. In this embodiment, the first bump 16 is made of Au.

[0025] The size of the first bump 16 is not particularly limited, and is set appropriately depending on the size of the first via conductor 13 .

[0026] A connecting conductor 15 is provided on the first main surface 10a of the insulating substrate 10 so as to cover the first via conductor 13. In this way, the connecting conductor 15 is electrically connected to the first via conductor 13.

[0027] Here, the connecting conductor 15 is formed of, for example, a conductive layer having a predetermined thickness. In this embodiment, the connecting conductor 15 is formed of a single conductive layer and is provided so as to cover the entire first main surface 10 a. The connecting conductor 15 forms part of the above-mentioned first external connecting wiring.

[0028] The connecting conductor 15 can be made of various wiring materials, but is preferably made of a metal material with particularly high electrical conductivity. The material of the connecting conductor 15 can be, for example, a metal material whose main component is any of Ni, Ag, Cu, Au, Pt, Mo, Ti, Cr, and W. The connecting conductor 15 may also be made of an alloy material whose main components are two or more selected from these metal materials.

[0029] The thickness and size of the connecting conductor 15 are not particularly limited, and the size is set appropriately depending on the size of the insulating substrate 10. In this embodiment, the connecting conductor 15 is made of Ni and has a thickness of 200 nm.

[0030] As described above, the first external connection wiring serving as the anode of the pair of external connection wirings is composed of the first via conductor 13 , the connection conductor 15 and the first bump 16 .

[0031] 2, the capacitance forming portion 20 is provided so as to face the first main surface 10a of the insulating substrate 10, and includes a conductive structure 21, a first dielectric film 22a covering the surface of the structure 21, and a conductive film 23 covering part of the surface of the first dielectric film 22a. The outermost surface of the capacitance forming portion 20 has an uneven shape.

[0032] The structure 21 has an uneven shape and is constituted by a plurality of conductive pillars 21 a standing upright from the first main surface 10 a of the insulating substrate 10 via the connecting conductors 15 .

[0033] The plurality of columns 21 a are formed by a Lithographie Galvanoformung Abformung (LIGA) process, which combines X-ray lithography and electroforming. Note that the method for forming the plurality of columns 21 a is not particularly limited to this and can be changed as appropriate.

[0034] The structure 21 is located on the connection conductor 15 and is joined to the connection conductor 15. Therefore, the first external connection wiring serving as the anode described above is connected to the capacitance forming portion 20 via the connection conductor 15.

[0035] The pillars 21a constituting the structure 21 can be made of various conductive metal materials, but are preferably made of a metal material primarily containing any of Ni, Mo, W, Al, Ti, Ta, Nb, Cu, Pt, Au, and Ag. The pillars 21a may also be made of an alloy material primarily containing two or more selected from these metal materials. In this embodiment, the pillars 21a are made of Ni.

[0036] The number and size of the pillars 21 a constituting the structure 21 are not particularly limited and are set appropriately depending on the size of the insulating substrate 10. In this embodiment, pillars 21 a are used that are approximately cylindrical with a length of 500 μm or less and a diameter of 1 μm or more. Note that, although a total of 116 pillars 21 a arranged in a staggered pattern are shown in FIG. 1B and 11 of these pillars 21 a are shown in FIG. 2, these numbers and arrangements are merely examples and can be changed in various ways.

[0037] As described above, the first dielectric film 22a covers the surface of the structure 21. The first dielectric film 22a also covers the surface of the connecting conductor 15 in the portion not joined to the columnar body 21a. In this embodiment, the first dielectric film 22a corresponds to the dielectric film.

[0038] The first dielectric film 22a can be made of various insulating materials, for example, AlO ｘ , SiO ｘ , HfO ｘ , TiO ｘ , TaO ｘ , ZrO ｘ , SiAlO ｘ , HfAlO ｘ , ZrAlO ｘ , AlTiO ｘ , SrTiO ｘ , HfSiO ｘ , ZrSiO ｘ , TiZrO ｘ , TiZrO ｘ , TiZrWO ｘ , SrTiOｘ , BaTiO ｘ , PbTiO ｘ , BaSrTiO ｘ , BaCaTiO ｘ Metal oxides such as AlN ｘ , SiN ｘ , AlScN ｘ Metal nitrides such as AlO ｘ N ｙ , SiO ｘ N ｙ , HfO ｘ N ｙ , SiC ｘ O ｙ N ｚ Among them, AlO ｘ (For example, Al ２ O ３ ), SiO ｘ (e.g., SiO ２ ), HfO ｘ , TiO ｘ , SiAlO ｘ , HfAlO ｘ , ZrAlO ｘ , HfSiO ｘ and ZrSiO ｘ It is preferable that the first dielectric film 22a is made of any one of the following. Note that the above chemical formula simply indicates the structure of the material and does not limit the composition. In other words, x, y, and z attached to O and N may be any value greater than 0, and the abundance ratio of each element including the metal element is arbitrary. The first dielectric film 22a may also be made of a laminated film consisting of multiple dielectric layers made of different materials. In this embodiment, the first dielectric film 22a is made of AlO ｘ and SiO ｘ The following is used:

[0039] The first dielectric film 22a can be preferably formed by a gas phase method such as a vacuum deposition method, a chemical vapor deposition (CVD) method, a sputtering method, an atomic layer deposition (ALD) method, a pulsed laser deposition (PLD) method, or a method using a supercritical fluid, and is particularly preferably formed by an ALD method.

[0040] The thickness of the first dielectric film 22a is not particularly limited, but is preferably 3 nm or more and 100 nm or less, and more preferably 5 nm or more and 50 nm or less.

[0041] As described above, the conductive film 23 covers a part of the surface of the first dielectric film 22 a, so that the first dielectric film 22 a has a non-exposed portion 221 covered with the conductive film 23 and an exposed portion 222 not covered with the conductive film 23.

[0042] 2 and 3A, the surface of the first dielectric film 22a other than the portion defining the outer edge of the capacitance forming portion 20 in the direction parallel to the first main surface 10a of the insulating substrate 10 (i.e., both ends in the left-right direction in FIG. 2) is covered with the conductive film 23, thereby constituting a non-exposed portion 221. On the other hand, as shown in FIG. 2 and 3B, the surface of the first dielectric film 22a defining the outer edge is not covered with the conductive film 23, thereby constituting an exposed portion 222.

[0043] This configuration makes it possible to improve the reliability of the capacitor 1A after it has been mounted, the details of which will be described later.

[0044] The conductive film 23 can be made of various conductive materials, including metal materials containing any of Ni, Cu, Ru, Al, W, Ti, Ag, Au, Zn, Ta, and Nb as the main material, alloy materials containing two or more selected from these metal materials as the main components, metal nitrides such as TiN, TiAlN, TiSiN, TaN, NbN, and WN, metal oxynitrides such as TiON and TiAlON, conductive polymers such as PEDOT (poly(3,4-ethylenedioxythiophene)), polypyrrole, and polyaniline, and RuO ２ This can be made of a conductive oxide film such as ZnO, (Zn,Al)O, NiO, etc. In this embodiment, the conductive film 23 is made of Ru.

[0045] The conductive film 23 can be preferably formed by CVD, ALD, PLD, plating, bias sputtering, sol-gel, a method using conductive polymer filling, or a method using supercritical fluid, and is particularly preferably formed by ALD. The conductive film 23 may also be formed as a laminated film consisting of multiple conductive layers made of different materials. In this case, a film can be formed by ALD and then another film can be formed by another method.

[0046] The thickness of the conductive film 23 is not particularly limited, but is preferably 3 nm or more, and more preferably 10 nm or more.

[0047] 2, most of the upper part of the capacitance forming portion 20 is covered by the extraction electrode 18 and is electrically connected to it. More specifically, the extraction electrode 18 is positioned so as to cover the surface of the conductive film 23 in the portion covering the non-exposed portion 221 that covers the tip end of the columnar body 21a. On the other hand, the extraction electrode 18 does not cover the conductive film 23 in the portion other than the above-mentioned portion and the surface of the exposed portion 222. The extraction electrode 18 constitutes part of the second external connection wiring described above.

[0048] The extraction electrode 18 can be made of various conductive materials, including a metal material primarily made of any of Ni, Cu, Al, Pt, Ti, and TiN, an alloy material primarily made of two or more selected from these metal materials, or a metal nitride such as TiN. In this embodiment, the extraction electrode 18 is made of either Cu or Ti. The extraction electrode 18 is formed by, for example, sputtering, vacuum deposition, or CVD.

[0049] 2 , the sealing portion 30 is provided on the first main surface 10a of the insulating substrate 10 and seals the capacitance forming portion 20 together with the insulating substrate 10. The sealing portion 30 defines an outer surface 30a located on the opposite side of the capacitance forming portion 20 from the insulating substrate 10. More specifically, the sealing portion 30 is located so as to cover a part of the upper part and the sides of the capacitance forming portion 20, which is provided so as to face the first main surface 10a of the insulating substrate 10, and the upper part and the sides of the extraction electrode 18.

[0050] The sealing portion 30 can be made of various insulating materials, but is preferably made of an insulating material that is particularly excellent in weather resistance. The material of the sealing portion 30 can be a resin material such as polyimide resin, polybenzoxazole resin, polyethylene terephthalate resin, benzocyclobutene resin, or epoxy resin. The resin material can also contain various additives, such as SiO2 to adjust the thermal expansion coefficient. ２ Filler and Al ２ O ３ It may contain fillers etc. In this embodiment, the sealing portion 30 is made of epoxy resin.

[0051] If it is difficult to ensure moisture resistance with only the sealing portion 30, a moisture-resistant protective film 40 (see FIG. 43, etc.) may be formed between the capacitance forming portion 20 and the sealing portion 30. The moisture-resistant protective film 40 may be formed by depositing a film of SiN, SiO ２ , Al ２ O ３ , HfO ２ , ZrO ２The moisture-resistant protective film 40 can be formed by providing an inorganic insulator such as a fluorine-based resin or a silane coupling agent resin so as to cover the capacitance-forming portion 20 by a CVD method, an ALD method, or the like, or by providing a water-repellent organic insulator such as a fluorine-based resin or a silane coupling agent resin so as to cover the capacitance-forming portion 20. Here, the moisture-resistant protective film 40 does not necessarily need to be formed inside the capacitance-forming portion 20, and it is sufficient if it is formed so as to cover only the outer surface.

[0052] The sealing portion 30 can be formed by various coating methods, such as a method using a vacuum laminator, a method using an air dispenser, a method using a jet dispenser, a screen printing method, a vacuum printing method, an electrostatic coating method, an inkjet method, a photolithography method, etc.

[0053] The thickness and size of sealing portion 30 are not particularly limited, and the size is set appropriately depending on the size of insulating substrate 10. Here, sealing portion 30 preferably has a thickness of, for example, 5 μm or more and 50 μm or less, and its size is preferably such that it covers the entire first main surface 10 a of insulating substrate 10.

[0054] A second through hole 12 is provided on the outer surface 30a of the sealing portion 30. The second through hole 12 penetrates the sealing portion 30 so as to reach the upper surface 18a of the extraction electrode 18 from the outer surface 30a. The second through hole 12 is filled with a second via conductor 14. The second via conductor 14 has a substantially cylindrical shape, for example.

[0055] The second via conductor 14 constitutes a part of the second external connection wiring described above. When viewed along the normal direction of the first main surface 10 a of the insulating substrate 10, the second via conductor 14 is provided within the region in which the capacitance forming portion 20 is arranged.

[0056] The second via conductors 14 can be made of various wiring materials, but are preferably made of a metal material with particularly high electrical conductivity. The material of the second via conductors 14 can be, for example, a metal material primarily made of Ni, Ag, Cu, Au, Pt, Mo, or W. The material of the second via conductors 14 can be changed as appropriate to suit the mounting environment of the capacitor 1A according to this embodiment. In this embodiment, the second via conductors 14 are made of Ni.

[0057] The axial length and size of second via conductor 14 are not particularly limited and are set appropriately depending on the thickness and size of sealing portion 30. Here, the axial length of second via conductor 14 is preferably, for example, 5 μm or more and 75 μm or less, and the diameter is preferably, for example, 15 μm or more and 150 μm or less. In the present embodiment, second via conductor 14 is made of Ni and has an axial length of 75 μm and a diameter of 150 μm.

[0058] Second bumps 17 are provided on the outer surface 30a of the sealing portion 30 so as to cover the second via conductors 14. The second bumps 17 serve as a bonding material for mounting the capacitor 1A on a wiring board or the like and for electrically connecting the capacitance forming portion 20 of the capacitor 1A to an external circuit. The second bumps 17 are provided so as to protrude from the outer surface 30a of the sealing portion 30. The shape of the second bumps 17 is approximately hemispherical. The second bumps 17 constitute part of the second external connection wiring described above.

[0059] The second bump 17 can be made of various wiring materials, but is preferably made of a metal material with particularly high electrical conductivity. The material of the second bump 17 can be, for example, a metal material containing any of Ni, Ag, Cu, Au, and Sn as the main component. In this embodiment, the second bump 17 is made of Au.

[0060] The size of the second bump 17 is not particularly limited, and is set appropriately depending on the size of the second via conductor 14 .

[0061] As described above, the second external connection wiring serving as the cathode of the pair of external connection wirings is composed of the extraction electrode 18, the second via conductor 14, and the second bump 17. Furthermore, the second external connection wiring configured in this manner is located inside the outer edge of the capacitance forming portion 20 in a direction parallel to the first main surface 10a of the insulating substrate 10. This makes it possible to improve the reliability of the capacitor 1A after it has been mounted, and details of this will be described later.

[0062] With the above-described configuration, in the capacitor 1A of this embodiment, the capacitance forming portion 20 consisting of the conductive structure 21, the first dielectric film 22a, and the conductive film 23 is sealed by the insulating substrate 10 and the sealing portion 30, and electrical extraction of the capacitance forming portion 20 is realized by a pair of external connection wirings.

[0063] Fig. 4 is a flow diagram showing a method for manufacturing a capacitor according to this embodiment. Figs. 5 to 16 are schematic cross-sectional views illustrating each step of the manufacturing flow shown in Fig. 4. Next, an example of a specific manufacturing method for manufacturing the capacitor 1A according to this embodiment will be described with reference to Figs. 4 to 16.

[0064] The manufacturing method of capacitor 1A described below is a method in which an assembly of in-process capacitors is produced by processing the entire manufacturing process in one go up to a mid-point, and then the assembly is divided into individual pieces, and the individual pieces are further processed to mass-produce multiple capacitors 1A simultaneously.

[0065] First, as shown in FIG. 4, a green sheet is produced in step S1. ２ O ３ The Al powder and the glass powder were weighed. ２ O ３The powder and glass powder are mixed with an organic solvent such as toluene or ethanol, and a binder such as polyvinyl butyral. This mixture is then formed into a sheet, thereby producing a green sheet that will serve as the base for an insulating substrate. After the green sheet is produced, it is cut into multiple green sheets.

[0066] Next, in step S2, first through holes are formed in some of the green sheets as shown in Fig. 4. Specifically, first through holes 11 are provided at predetermined positions in the green sheets, and the first through holes 11 will be filled later with first via conductors that are part of the anodes.

[0067] Here, the method for forming the first through holes 11 is not particularly limited, but for example, the first through holes 11 can be formed by irradiating the green sheet with laser light. Alternatively, the first through holes 11 may be formed by processing using a mechanical puncher or sandblasting.

[0068] 4, in step S3, first via conductors are formed in the green sheet with the first through holes 11 formed therein. Specifically, a conductive paste is applied to the green sheet so as to fill the first through holes 11.

[0069] Here, the method for applying the conductive paste is not particularly limited, but for example, a screen printing method can be used.

[0070] Next, as shown in Fig. 4, the green sheets are fired in step S4. Specifically, a green sheet without a first through hole is superimposed on the green sheet to which the conductive paste has been applied in step S3, and these superimposed green sheets are pressure-bonded. Then, the laminate of the pressed green sheets is degreased, and thereafter, the laminate of the degreased green sheets is fired.

[0071] Here, when stacking the green sheets, a green sheet without first through holes 11 is stacked on the other main surface opposite to the one main surface of the green sheet coated with the conductive paste. Furthermore, when pressing the green sheets, a uniaxial press can be used, for example. Furthermore, the green sheets are fired, for example, in the air at a temperature of 700°C to 1000°C.

[0072] By going through steps S1 to S4 described above, an insulating substrate is obtained as shown in Fig. 5. Here, the insulating substrate is a so-called multi-substrate in which insulating substrates that will ultimately be included in each of a plurality of capacitors are connected in a matrix, but in Fig. 5, attention is focused on only one of the insulating substrates, 10, and its surrounding area is omitted and shown with a dashed line.

[0073] Although the above description has been given using an example in which the green sheet and the conductive paste are fired simultaneously, the first via conductors 13 may be formed after firing an insulating substrate that does not have through holes or the like. In this case, the first through holes 11 may be formed in the fired insulating substrate by, for example, sandblasting, wet etching, dry etching, or the like, and then the conductive paste may be applied and fired. Alternatively, the first via conductors 13 may be formed by sputtering, vapor deposition, plating, or the like.

[0074] 4 and 5, in step S5, a connecting conductor is formed to cover one of the pair of main surfaces of the insulating substrate 10. More specifically, a conductive paste is applied to the first main surface 10a, which is the one main surface of the insulating substrate 10.

[0075] Here, the method for applying the conductive paste is not particularly limited, but for example, a screen printing method can be used.

[0076] 4 and 6, a structure-forming mold used to form the structure is formed in step S6. Specifically, a structure-forming mold 101 is formed on one of the pair of main surfaces of the connecting conductor 15, the main surface located on the opposite side from the insulating substrate 10 when viewed from the connecting conductor 15.

[0077] The structure-forming mold 101 is formed through the following procedure. First, X-rays are irradiated onto a photosensitive resin through an X-ray mask. Next, the photosensitive resin irradiated with X-rays is developed. As a result, only the photosensitive resin in the areas exposed to X-rays remains selectively, thereby forming a microstructure. Note that the photosensitive resin used here is not limited to the so-called negative photosensitive resin in which the areas exposed to X-rays remain selectively as described above, but may also be a so-called positive photosensitive resin in which the areas exposed to X-rays selectively dissolve.

[0078] The microstructure formed in the above manner has an approximately rectangular parallelepiped shape as a whole. The microstructure has a plurality of pores 102 that penetrate the microstructure so as to reach from one of the pair of main surfaces to the other. The pores 102 have uniform diameters on the order of microns. This microstructure constitutes a structure-forming mold 101.

[0079] Next, in step S7, a plurality of conductive pillars that constitute the structure are formed, as shown in Figures 4 and 7. More specifically, pillars 21a are formed so as to fill a plurality of pores 102 provided in the structure-forming template 101. The formed pillars 21a are joined at their lower parts to the connecting conductors 15. The pillars 21a can be formed, for example, by electrolytic plating.

[0080] 4 and 8, the structure-forming mold is peeled off in step S8. In this manner, electroplating is performed on the mold, and the mold is peeled off from the electrodeposit formed thereby, so-called electroforming is performed, whereby structure 21, which is composed of a plurality of columns 21a and has an uneven shape as a whole, is exposed on first main surface 10a of insulating substrate 10.

[0081] 4 and 9, a first dielectric film is formed in step S9. Specifically, a first dielectric film 22a is formed so as to cover the surfaces of the connecting conductor 15 and the structure 21.

[0082] The method for forming the first dielectric film 22a is not particularly limited, but preferably, the ALD method is used. The ALD method allows the raw materials for the first dielectric film 22a to be supplied as gas, making it possible to select the material and adjust the film thickness at the atomic layer level.

[0083] When the first dielectric film 22a is formed by the ALD method, it is preferable to use a source gas that has a high vapor pressure, is easy to gasify, has high thermal stability, and is highly reactive. ｘ When forming a film, it is preferable to use TMA (trimethylaluminum) as a raw material, and SiO ｘ When forming the film, it is preferable to use TDMAS (trisdimethylaminosilane) as a raw material. In this embodiment, the first dielectric film 22a is formed by ALD.

[0084] The first dielectric film 22a is formed at a temperature of, for example, 150° C. to 400° C., although this varies depending on the film formation method and film formation material.

[0085] 4 and 10, a conductive film is formed in step S10. More specifically, a conductive film 23 is formed so as to cover the first dielectric film 22a formed in step S9.

[0086] The method for forming the conductive film 23 is not particularly limited, but preferably, the ALD method is used. The ALD method allows the raw materials for the conductive film 23 to be supplied as gas, making it possible to select the material and adjust the film thickness at the atomic layer level. The conductive film 23 is formed at a temperature condition of, for example, 150° C. or higher and 600° C. or lower, although this differs depending on the film formation method and film formation material.

[0087] By going through steps S7 to S10 described above, a capacitance forming portion 20 consisting of a conductive structure 21, a first dielectric film 22a, and a conductive film 23 and having an uneven outermost surface is formed on the first main surface 10a of the insulating substrate 10, as shown in FIG. 10.

[0088] 4 and 11, an extraction electrode 18 is formed in step S11. More specifically, the extraction electrode 18 is formed so as to cover the surface of the conductive film 23 formed in step S10 except for the portion that defines the bottom side of the recessed portion of the capacitance forming portion 20.

[0089] Although there are no particular limitations on the method for forming the extraction electrode 18, sputtering is preferably used, as the use of sputtering can shorten the time required to form the extraction electrode 18 compared to other formation methods.

[0090] 4 and 12, a resist film is formed in step S12. More specifically, a resist film 24 is formed so as to cover the lead-out electrode 18 in a portion that covers the conductive film 23 other than the portion that defines the outer edge of the capacitance forming portion 20 in a direction parallel to the first main surface 10a of the insulating substrate 10 (i.e., both ends in the left-right direction in FIG. 12).

[0091] Here, the method for forming the resist film 24 is not particularly limited to this. In this embodiment, a photosensitive liquid resist is uniformly applied to a predetermined surface of the extraction electrode 18 by spin coating, and then this is locally exposed to light using a photomask. Next, unnecessary photosensitive liquid resist is removed by immersion in a developer, and the remaining photosensitive liquid resist is dried in an oven or the like, thereby forming the resist film 24.

[0092] 4 and 13, in step S13, a part of the conductive film and a part of the extraction electrode are removed. More specifically, the part of the extraction electrode 18 that is not covered with the resist film 24 formed in step S12 and the corresponding part of the conductive film 23 are removed. Examples of the removal method include wet etching, dry etching, and atomic layer etching (ALE).

[0093] By this removal, the first dielectric film 22 a has a non-exposed portion 221 covered with the conductive film 23 and an exposed portion 222 not covered with the conductive film 23 .

[0094] 4 and 14, the resist film is removed by being stripped in step S14. More specifically, the resist film 24 is stripped using a stripping solution or the like.

[0095] 4 and 15, a sealing portion is formed in step S15. More specifically, a sealing portion 30 is provided on the first main surface 10a of the insulating substrate 10 on which the capacitance forming portion 20 is provided, so as to cover the capacitance forming portion 20 and the extraction electrode 18.

[0096] The sealing portion 30 is formed, for example, by so-called compression molding. More specifically, a resin sheet is placed on the first main surface 10a of the insulating substrate 10, and in this state, a vacuum is drawn using a vacuum laminator, thereby adhering the resin sheet to the first main surface 10a of the insulating substrate 10. Then, in this state, the resin sheet is heated to 50°C to 100°C to laminate the capacitance forming portion 20, and then further heated to 100°C to 200°C to perform full curing, thereby forming the sealing portion 30. Note that the method of forming the sealing portion 30 is not limited to the above-mentioned compression molding, and so-called transfer molding may also be used.

[0097] As a result, the capacitance forming portion 20 and the extraction electrodes 18 are sealed by the insulating substrate 10 and the sealing portion 30, preventing moisture from entering the capacitance forming portion 20 and the extraction electrodes 18 from the outside and ensuring moisture resistance. Furthermore, the capacitance forming portion 20 is covered by the sealing portion 30, and the capacitance forming portion 20 is also physically protected by the sealing portion 30. Note that the curing conditions shown above are merely examples and can be changed in various ways.

[0098] Next, as shown in FIGS. 4 and 16, in step S16, second via conductors are formed in the sealed portion.

[0099] More specifically, first, a second through hole 12 is formed in the sealing portion 30 so as to extend from the outer surface 30a to the upper surface 18a of the extraction electrode 18. Next, a second via conductor 14 is formed so as to fill the second through hole 12.

[0100] The second via conductors 14 can be formed by, for example, electrolytic plating. In this case, the portions other than the second through holes 12 are covered with an ultraviolet-curable resin film serving as a mask (not shown), and electrolytic plating is performed in this state, thereby making it possible to cover only the insides of the second through holes 12 with a plating film. After the electrolytic plating is completed, the ultraviolet-curable resin film serving as a mask is removed.

[0101] The second via conductor 14 thus formed is joined to the extraction electrode 18 at its end face on the capacitance forming portion 20 side. As a result, the second via conductor 14 is connected to the capacitance forming portion 20 via the extraction electrode 18.

[0102] Next, as shown in FIG. 4, in step S17, the insulating substrate is subjected to a grinding process and then divided into individual pieces.

[0103] More specifically, a flat cutting is performed on the second main surface 10b side of the insulating substrate 10, which is located opposite the side on which the sealing portion 30 is provided, and then the insulating substrate 10 is cut into individual pieces of multiple capacitors 1A that are connected to each other.

[0104] Here, when performing the grinding process, a grinding tape (not shown) is attached to the sealing portion 30 side, and the insulating substrate 10 in the portion that blocks the first via conductor 13 is removed by flat cutting, thereby exposing the end of the first via conductor 13 on the second main surface 10b side.

[0105] Furthermore, when singulating, grooves are formed in insulating substrate 10, and force is applied to insulating substrate 10 so as to bend it starting from the grooves, thereby breaking insulating substrate 10. Methods for forming the grooves include diamond scribing, laser scribing, dicing, etc. Alternatively, singulation may be performed by directly cutting insulating substrate 10 and sealing portion 30 by scribing or dicing.

[0106] Next, in step S18, a first bump is formed on the insulating substrate, and a second bump is formed on the sealing portion, as shown in Fig. 4. More specifically, as shown in Fig. 2, a first bump 16 is formed on the second main surface 10b of the insulating substrate 10 so as to cover the first via conductor 13 provided in the insulating substrate 10. In addition, a second bump 17 is formed on the outer surface 30a of the sealing portion 30 so as to cover the second via conductor 14 provided in the sealing portion 30.

[0107] The first bump 16 can be formed by, for example, electrolytic plating. In this case, the area other than the vicinity of the exposed portion of the first via conductor 13 is covered with an ultraviolet-curable resin film (not shown) as a mask, and electrolytic plating is performed in this state, thereby forming the first bump 16 so as to protrude from the second main surface 10b. After the electrolytic plating is completed, the ultraviolet-curable resin film (mask) is removed. The same applies to the formation of the second bump 17.

[0108] The method for forming the second via conductors 14, first bumps 16, and second bumps 17 described above is not limited to the method using electrolytic plating described above; other methods that can be used include a combination of a screen printing method, an inkjet method, a dispenser method, or the like using a conductive paste and firing. In this case, the conductive paste preferably contains a metal or sintering aid that can be fired at a low temperature so that firing can be performed under temperature conditions that do not affect the resin that constitutes the sealing portion 30.

[0109] By going through the steps S1 to S18 described above, the capacitor 1A according to the first embodiment is manufactured.

[0110] In a capacitor having capacitance forming portion 20 with an uneven outermost surface, such as capacitor 1A according to the present embodiment, damage such as cracks may occur at the outer edge of capacitance forming portion 20 in a direction parallel to first main surface 10a of insulating substrate 10. Therefore, if capacitance forming portion 20 is designed to be electrically connected from this outer edge, a short circuit may occur at the damaged portion, resulting in a loss of functionality of capacitor 1A.

[0111] In this regard, in capacitor 1A according to the present embodiment, as described above, the portion of first dielectric film 22a serving as a dielectric film other than the portion defining the outer edge portion constitutes non-exposed portion 221 whose surface is covered with conductive film 23. In addition, the portion of first dielectric film 22a defining the outer edge portion constitutes exposed portion 222 whose surface is not covered with conductive film 23.

[0112] As a result, the surface of the capacitance forming portion 20 other than the outer edge portion has a so-called MIM (Metal Insulator Metal) structure, and the outer edge portion of the surface of the capacitance forming portion 20 has a so-called MI (Metal Insulator) structure.

[0113] This configuration makes it possible to suppress electrical extraction of capacitance forming portion 20 from the outer edge portion, which is prone to damage as described above, while allowing electrical extraction from other portions, resulting in capacitor 1A that is less susceptible to damage and has improved reliability after mounting.

[0114] Therefore, by using the capacitor 1A according to this embodiment, the reliability after mounting is improved in a capacitor having a capacitance forming portion consisting of a conductive structure, a dielectric film, and a conductive film.

[0115] Furthermore, in capacitor 1A according to this embodiment, as described above, second external connection wiring formed of extraction electrode 18 and the like is located inside the outer edge of capacitance forming portion 20 in the direction parallel to first main surface 10a of insulating substrate 10. Therefore, extraction electrode 18 covers a part of the surface of conductive film 23 that covers non-exposed portion 221, thereby being electrically connected thereto, while being located so as not to cover the surface of exposed portion 222.

[0116] This configuration can more reliably prevent electrical leakage from the capacitance forming portion 20 from the outer edge portion, which is prone to damage as described above, thereby improving the reliability of the capacitor 1A after mounting.

[0117] Furthermore, in the capacitor 1A of this embodiment, as described above, when viewed along the normal direction of the first main surface 10a of the insulating substrate 10, the first via conductor 13 and the second via conductor 14 are both arranged within the area in which the capacitance forming portion 20 is arranged.

[0118] In this configuration, neither the first external connection wiring nor the second external connection wiring is disposed to the side of the capacitance forming portion 20, and therefore it is possible to minimize the sealing portion 30 in the portion located to the side of the capacitance forming portion 20. As a result, not only can the capacitor 1A be made smaller than conventional capacitors, but the volume occupied by the portions of the capacitor 1A other than the capacitance forming portion 20 is reduced, thereby achieving a higher capacitance.

[0119] In the capacitor 1A according to the present embodiment described above, the case has been described in which the lead electrode 18 is formed so as to cover the surface of the conductive film 23 in a portion other than the portion that defines the bottom side of the recessed portion of the capacitance forming portion 20, in other words, the case in which the lead electrode 18 does not cover the surface of the conductive film 23 in the portion that defines the bottom side of the recessed portion of the capacitance forming portion 20, but the lead electrode 18 may also be formed so as to cover the surface of the conductive film 23 in the portion that defines the bottom side of the recessed portion of the capacitance forming portion 20. In this case, the lead electrode 18 can be formed by, for example, a CVD method or an ALD method.

[0120] 17 is a schematic cross-sectional view of a capacitor according to a first modification. A capacitor 1A1 according to the first modification based on the first embodiment will be described below with reference to FIG.

[0121] As shown in FIG. 17, the capacitor 1A1 according to the first modification is different from the capacitor 1A according to the first embodiment in the configuration of the first external connection wiring.

[0122] More specifically, in the capacitor 1A1 according to this modified example, the capacitance forming portion 20 is electrically led out by the first external connection wiring from the outer surface 30a side of the sealing portion 30, similar to the second external connection wiring.

[0123] That is, in this modified example, the first through hole 11 is formed in the sealing portion 30 so as to reach from the outer surface 30a of the sealing portion 30 to the upper surface of the connecting conductor 15. The first via conductor 13 is formed so as to fill the first through hole 11. Furthermore, the first bump 16 is formed on the outer surface 30a of the sealing portion 30 so as to cover the first via conductor 13 provided in the sealing portion 30.

[0124] Even when configured in this manner, the same effects as those described in the first embodiment can be obtained, and the reliability after mounting can be improved in a capacitor having a capacitance forming portion consisting of a conductive structure, a dielectric film, and a conductive film.

[0125] Furthermore, in this configuration, the first via conductor 13 and the second via conductor 14 are positioned so as to penetrate the sealing portion 30 in its thickness direction, and therefore these via conductors with opposite polarities are arranged close to each other with their current paths facing in opposite directions. As a result, the magnetic fields generated in these via conductors by the flow of current act to cancel each other out, thereby reducing the so-called ESL (equivalent series inductance).

[0126] Furthermore, in the capacitor 1A1 of the first modified example, if the first through hole 11 is formed simultaneously with the second through hole 12 and the first via conductor 13 is formed simultaneously with the second via conductor 14, the remaining steps can be basically manufactured in accordance with the manufacturing method of the capacitor 1A of the above-mentioned embodiment 1.

[0127] Furthermore, in the cross section of capacitor 1A1 shown in Figure 17, two first external connection wirings are shown positioned so as to sandwich capacitance forming portion 20, but the arrangement of the first external connection wirings when capacitor 1A1 is viewed in a plane is not particularly limited to this and can be changed as appropriate.

[0128] 18 is a schematic cross-sectional view of a capacitor according to a second modification, which is a capacitor 1A2 according to the first embodiment.

[0129] As shown in FIG. 18, a capacitor 1A2 according to the second modification is different from the capacitor 1A according to the first embodiment in the configuration of the second external connection wiring.

[0130] More specifically, in the capacitor 1A2 according to this modified example, the capacitance forming portion 20 is electrically led out by the second external connection wiring from the second main surface 10b side of the insulating substrate 10, similar to the first external connection wiring.

[0131] That is, in this modification, second through holes 12 are formed in insulating substrate 10, connecting conductor 15, and capacitance forming portion 20 so as to extend from second main surface 10b of insulating substrate 10 to the underside of extraction electrode 18. Second via conductors 14 are also formed so as to fill second through holes 12. As a result, second via conductors 14 are connected to capacitance forming portion 20 via extraction electrode 18. Furthermore, second bumps 17 are formed on second main surface 10b of insulating substrate 10 so as to cover second via conductors 14 provided on insulating substrate 10.

[0132] Furthermore, in this modification, first dielectric film 22a and conductive film 23 cover not only the surface of structure 21 but also the surfaces of insulating substrate 10 and connecting conductor 15 in the portions that define second through hole 12. More specifically, at the boundary between second via conductor 14 and the base material of insulating substrate 10, the base material of insulating substrate 10 is covered with first dielectric film 22a, and first dielectric film 22a is covered with conductive film 23, which is further covered by second via conductor 14. Similarly, at the boundary between extraction electrode 18 and connecting conductor 15, connecting conductor 15 is covered with first dielectric film 22a, and first dielectric film 22a is covered with conductive film 23, which is further covered by extraction electrode 18.

[0133] Even when configured in this manner, the same effects as those described in the first embodiment can be obtained, and the reliability after mounting can be improved in a capacitor having a capacitance forming portion consisting of a conductive structure, a dielectric film, and a conductive film.

[0134] Furthermore, in this configuration, the first via conductor 13 and the second via conductor 14 are positioned so as to penetrate the insulating substrate 10 in its thickness direction, and therefore these via conductors with opposite polarities are arranged close to each other with their current paths facing in opposite directions. As a result, the magnetic fields generated in these via conductors by the current flow act to cancel each other out, thereby reducing the ESL.

[0135] In addition, the capacitor 1A2 of the second modified example can be manufactured by, for example, forming the above-mentioned second through hole 12 between the formation of the structure forming mold 101 and the formation of the first dielectric film 22a (i.e., between steps S8 and S9), and forming the above-mentioned second via conductor 14 between the grinding of the insulating substrate 10 and the formation of the second bump 17 (i.e., between steps S17 and S18), with the remaining steps basically following the manufacturing method of the capacitor 1A of the above-mentioned embodiment 1.

[0136] (Embodiment 2) Fig. 19 is a schematic cross-sectional view of a capacitor according to embodiment 2. Figs. 20(A) and 20(B) are enlarged cross-sectional views of essential parts of regions XXA and XXB, respectively, of the capacitance forming portion shown in Fig. 19. A capacitor 1B according to this embodiment will now be described with reference to Figs. 19 and 20.

[0137] As shown in FIG. 19, capacitor 1B according to this embodiment differs from capacitor 1A according to the first embodiment described above in the configuration of capacitance forming portion 20B.

[0138] The capacitance forming portion 20B has a conductive structure 21, a dielectric film including a first dielectric film 22a, a second dielectric film 22b and a third dielectric film 22c, and a conductive film 23B.

[0139] As described above, the first dielectric film 22a covers the surface of the structure 21. The second dielectric film 22b covers the entire surface of the first dielectric film 22a. The third dielectric film 22c and the conductive film 23B each cover a portion of the surface of the second dielectric film 22b.

[0140] The second dielectric film 22b is a so-called adhesive film that has adhesiveness to the conductive film 23B. The second dielectric film 22b may be made of an ionic material, for example, HfO ｘ , TiO ｘ , Y.O. ｘ Metal oxides such as TiN ｘ Among them, HfO ２ , Y ２ O３ , TiO ２ It is preferable that the second dielectric film 22b is made of either TiO or TiN. Note that the above chemical formula simply indicates the composition of the material and does not limit the composition. That is, the x attached to O and N may be any value greater than 0, and the abundance ratio of each element including the metal element is arbitrary. The second dielectric film 22b may also be made of a laminated film consisting of multiple dielectric layers made of different materials. In this embodiment, the second dielectric film 22b is made of TiO ２ The one consisting of the following is used.

[0141] The second dielectric film 22b can be preferably formed by a gas phase method such as vacuum deposition, CVD, sputtering, ALD, PLD, or a method using a supercritical fluid, and is particularly preferably formed by the ALD method.

[0142] The thickness of the second dielectric film 22b is not particularly limited, but is preferably 3 nm or more and 100 nm or less, and more preferably 5 nm or more and 50 nm or less.

[0143] As described above, the third dielectric film 22c covers a portion of the surface of the second dielectric film 22b. More specifically, the third dielectric film 22c covers the surface of a portion of the second dielectric film 22b that defines the outer edge in a direction parallel to the first main surface 10a of the insulating substrate 10 (i.e., both ends in the left-right direction in FIG. 19 ) and the surface of a portion that corresponds to the tip end of the columnar body 21a. The third dielectric film 22c is a so-called inhibiting film that does not adhere to the conductive film 23B.

[0144] The third dielectric film 22c may be made of, for example, AlO ｘ , SiO ｘIt can be made of metal oxides such as SiO, SiC, etc. Note that the above chemical formula simply indicates the composition of the material and does not limit the composition. That is, x attached to O may be any value greater than 0, and the abundance ratio of each element including the metal element is arbitrary. Also, the third dielectric film 22c may be made of a laminated film consisting of multiple dielectric layers made of different materials. In this embodiment, the third dielectric film 22c is made of SiO ２ The one consisting of the following is used.

[0145] The third dielectric film 22c can be preferably formed by a gas phase method such as a vacuum deposition method, a CVD method, a sputtering method, an ALD method, a PLD method, or a method using a supercritical fluid, and is particularly preferably formed by an ALD method.

[0146] The thickness of the third dielectric film 22c is not particularly limited, but is preferably 3 nm or more and 100 nm or less, and more preferably 5 nm or more and 50 nm or less.

[0147] As described above, the conductive film 23B covers a portion of the surface of the second dielectric film 22b. Specifically, the conductive film 23B covers the surface of the portion of the second dielectric film 22b that is not covered by the third dielectric film 22c. The conductive film 23B selectively covers only the surface of the second dielectric film 22b. In other words, the conductive film 23B has underlayer dependency on the second dielectric film 22b. In this embodiment, the conductive film 23B is made of Ru.

[0148] When a Ru film is formed on an ionic material such as the second dielectric film 22b, the cycle until film formation (so-called incubation cycle) is shorter than when the Ru film is formed on a non-ionic material. By utilizing the difference in the incubation cycle resulting from the difference in the base, the Ru conductive film 23B is made to have base dependence with respect to the second dielectric film 22b made of an ionic material.

[0149] As a result, the dielectric film has a non-exposed portion 221B covered with the conductive film 23B and an exposed portion 222B not covered with the conductive film 23B.

[0150] 19 and 20A, the surface of the portion of the second dielectric film 22b that is not covered by the third dielectric film 22c (i.e., the portion of the second dielectric film 22b excluding the portion that defines the outer edge in the direction parallel to the first main surface 10a of the insulating substrate 10 and the portion that corresponds to the tip of the columnar body 21a) is covered with the conductive film 23B. As a result, the first dielectric film 22a and the second dielectric film 22b form a non-exposed portion 221B.

[0151] 19 and 20B, the surfaces of the portions of the second dielectric film 22b that are covered by the third dielectric film 22c (i.e., the portions of the second dielectric film 22b that define the outer edge in the direction parallel to the first main surface 10a of the insulating substrate 10 and the portions that correspond to the tips of the columns 21a) are not covered by the conductive film 23B. As a result, the first dielectric film 22a, the second dielectric film 22b, and the third dielectric film 22c form exposed portions 222B.

[0152] In other words, at least the outer edge of the capacitance forming portion 20B in the direction parallel to the first main surface 10a is defined by the exposed portion 222B formed by the first dielectric film 22a, the second dielectric film 22b, and the third dielectric film 22c. Therefore, the outer edge of the surface of the capacitance forming portion 20B has an MI structure.

[0153] Fig. 21 is a flow diagram showing a method for manufacturing a capacitor according to this embodiment, and Fig. 22 to Fig. 24 are schematic cross-sectional views for explaining each step of the manufacturing flow shown in Fig. 21. Next, an example of a specific manufacturing method for manufacturing the capacitor 1B according to this embodiment described above will be described with reference to Fig. 21 to Fig. 24.

[0154] 21, the manufacturing method of capacitor 1B is largely similar to the manufacturing method of capacitor 1A. Therefore, in the following, a description of the steps in the manufacturing method of capacitor 1B that are common to the manufacturing method of capacitor 1A will be omitted, and only the steps that are different from the manufacturing method of capacitor 1A will be described.

[0155] 21 and 22, after the first dielectric film is formed in step S9, a second dielectric film is formed in step S9B1. More specifically, second dielectric film 22b is formed so as to cover the entire surface of first dielectric film 22a.

[0156] 21 and 23, a third dielectric film is formed in step S9B2. More specifically, third dielectric film 22c is formed so as to cover the surface of portions of second dielectric film 22b that define the outer edge portions in the direction parallel to first main surface 10a of insulating substrate 10 (i.e., both ends in the left-right direction in FIG. 23) and the surface of portions that correspond to the tips of columnar bodies 21a.

[0157] The method for forming the third dielectric film 22c and the second dielectric film 22b described above is not particularly limited, but preferably, the ALD method is used. The ALD method allows the raw materials for the second dielectric film 22b and the third dielectric film 22c to be supplied as gases, making it possible to select the material and adjust the film thickness at the atomic layer level.

[0158] When forming the second dielectric film 22b using this ALD method, it is preferable to use a raw material gas that has a high vapor pressure and is easy to gasify, as well as high thermal stability and high reactivity.

[0159] The second dielectric film 22b and the third dielectric film 22c are formed at a temperature of, for example, 150° C. to 400° C., although this varies depending on the film formation method and film formation material.

[0160] 21 and 24, a conductive film is formed in step S10. More specifically, conductive film 23B is formed so as to cover the surface of the portion of second dielectric film 22b formed in step S9B1 that is not covered by third dielectric film 22c. This is because second dielectric film 22b has adhesion to conductive film 23B, while third dielectric film 22c does not have adhesion to conductive film 23B, and conductive film 23B has underlayer dependency on second dielectric film 22b.

[0161] By going through the aforementioned steps S7 to S9 and steps S9B1, S9B2, and S10, a capacitance forming portion 20B consisting of a conductive structure 21, a first dielectric film 22a, a second dielectric film 22b, a third dielectric film 22c, and a conductive film 23B and having an uneven outermost surface is formed on the first main surface 10a of the insulating substrate 10, as shown in FIG. 19.

[0162] The capacitor 1B according to the second embodiment described above is manufactured through all steps S1 to S11, steps S15 to S18, and steps S9B1 and S9B2, including the steps individually described above.

[0163] The capacitor 1B of this embodiment configured in this manner also achieves the same effects as those described in the first embodiment above, and improves reliability after mounting in a capacitor having a capacitance forming portion consisting of a conductive structure, a dielectric film, and a conductive film.

[0164] Third Embodiment Fig. 25 is a schematic cross-sectional view of a capacitor according to a third embodiment. Figs. 26A and 26B are enlarged cross-sectional views of essential parts of regions XXVIA and XXVIB, respectively, of the capacitance forming portion shown in Fig. 25. A capacitor 1C according to this embodiment will now be described with reference to Figs. 25 and 26.

[0165] As shown in FIG. 25, a capacitor 1C according to this embodiment differs from the capacitor 1A according to the first embodiment described above in the configuration of a capacitance forming portion 20C.

[0166] The capacitance forming portion 20C has a conductive structure 21, a dielectric film including a first dielectric film 22a and a second dielectric film 22b, and a conductive film 23C. The conductive film 23C has underlayer dependency on the second dielectric film 22b, similar to the conductive film 23B in the second embodiment described above.

[0167] The first dielectric film 22a covers the surface of the structure 21. The second dielectric film 22b covers a portion of the surface of the first dielectric film 22a. More specifically, the second dielectric film 22b covers the surface of the first dielectric film 22a except for the portions that define the outer edge portions in the direction parallel to the first main surface 10a of the insulating substrate 10 (i.e., both ends in the left-right direction in FIG. 25 ). The conductive film 23C covers the entire surface of the second dielectric film 22b.

[0168] As a result, the dielectric film has a non-exposed portion 221C covered with the conductive film 23C and an exposed portion 222C not covered with the conductive film 23C.

[0169] 25 and 26A, the entire surface of the second dielectric film 22b is covered with the conductive film 23C, so that the first dielectric film 22a and the second dielectric film 22b form a non-exposed portion 221C.

[0170] 25 and 26B, the surface of the portion of the first dielectric film 22a that is covered with the second dielectric film 22b (i.e., the portion of the first dielectric film 22a that defines the outer edge in the direction parallel to the first main surface 10a of the insulating substrate 10) is not covered with the conductive film 23B, thereby forming an exposed portion 222C of the first dielectric film 22a.

[0171] In other words, the outer edge of the capacitance forming portion 20C in the direction parallel to the first main surface 10a is defined by the exposed portion 222C formed by the first dielectric film 22a. Therefore, the outer edge of the surface of the capacitance forming portion 20C has an MI structure.

[0172] Fig. 27 is a flow diagram showing a method for manufacturing a capacitor according to this embodiment, and Fig. 28 to Fig. 31 are schematic cross-sectional views for explaining each step of the manufacturing flow shown in Fig. 27. Next, an example of a specific manufacturing method for manufacturing the capacitor 1C according to this embodiment described above will be described with reference to Fig. 27 to Fig. 31.

[0173] 27, the manufacturing method of capacitor 1C is largely similar to the manufacturing method of capacitor 1A. Therefore, in the following, a description of the steps in the manufacturing method of capacitor 1C that are common to the manufacturing method of capacitor 1A will be omitted, and only the steps that are different from the manufacturing method of capacitor 1A will be described.

[0174] 27 and 28 , after the first dielectric film is formed in step S9, a resist film is formed in step S12. More specifically, resist film 24 is formed so as to cover the surface of a portion of first dielectric film 22a that defines the outer edge in a direction parallel to first main surface 10a of insulating substrate 10 (i.e., both ends in the left-right direction in FIG. 28 ).

[0175] 27 and 29, a second dielectric film is formed in step S9B1. More specifically, second dielectric film 22b is formed so as to cover the surface of resist film 24 and the surface of the portion of first dielectric film 22a that is not covered with resist film 24C.

[0176] 27 and 30, the resist film is stripped in step S14. More specifically, the resist film 24 is stripped and removed together with the second dielectric film 22b covering the surface thereof.

[0177] 27 and 31, a conductive film is formed in step S10. More specifically, conductive film 23C is formed so as to cover the surface of second dielectric film 22b remaining on the surface of first dielectric film 22a after resist film 24 is peeled off in step S14. This is because second dielectric film 22b has adhesion to conductive film 23C and conductive film 23C has underlayer dependency on second dielectric film 22b.

[0178] By going through the aforementioned steps S7 to S9 and the steps S12, S9B1, S14, and S10, a capacitance forming portion 20C consisting of a conductive structure 21, a first dielectric film 22a, a second dielectric film 22b, and a conductive film 23C and having an uneven outermost surface is formed on the first main surface 10a of the insulating substrate 10, as shown in FIG. 25.

[0179] The capacitor 1C according to the third embodiment described above is manufactured through all steps S1 to S12, steps S14 to S18, and step S9B1, including the steps individually described above.

[0180] The capacitor 1C of this embodiment configured in this manner also achieves the same effects as those described in the first embodiment above, and improves reliability after mounting in a capacitor having a capacitance forming portion consisting of a conductive structure, a dielectric film, and a conductive film.

[0181] (Fourth Embodiment) Fig. 32 is a schematic cross-sectional view of a capacitor according to a fourth embodiment. Figs. 33(A) and 33(B) are enlarged cross-sectional views of essential parts of regions XXXIIIA and XXXIIIB, respectively, of the capacitance forming portion shown in Fig. 32. A capacitor 1D according to this embodiment will now be described with reference to Figs. 32 and 33.

[0182] As shown in FIG. 32, a capacitor 1D according to this embodiment differs from the capacitor 1A according to the first embodiment described above in the configuration of a capacitance forming portion 20D.

[0183] The capacitance forming portion 20D has a conductive structure 21D, a first dielectric film 22aD as a dielectric film, and a conductive film 23D.

[0184] The structure 21D is provided on the first main surface 10a of the insulating substrate 10 via the connecting conductor 15, and is porous and made of a conductive metal porous body 21b having a plurality of fine pores therein.

[0185] The porous metal body 21b has a plurality of micropores, at least some of which are not closed by the porous metal body itself, and preferably a majority or all of which are not closed by the porous metal body itself. Such a porous metal body is formed, for example, from a sintered body of metal particles.

[0186] The porous metal body 21b is located on a portion of the first main surface 10a of the insulating substrate 10 excluding the edge portion. As a result, the porous metal body 21b is also located on the connecting conductor 15 provided on the first main surface 10a and is joined to the connecting conductor 15. Therefore, the first external connecting wiring serving as the anode described above is connected to the capacitance forming portion 20D via the connecting conductor 15.

[0187] The porous metal body 21b can be made of various conductive metal materials, but is preferably made of a metal material whose main component is one of Ni, Mo, W, Al, Ti, Ta, Nb, Cu, Pt, Au, and Ag. Alternatively, the porous metal body 21b may be made of an alloy material whose main components are two or more selected from these metal materials.

[0188] The thickness and size of the porous metal body 21b are not particularly limited, and the size is set appropriately depending on the size of the insulating substrate 10. In this embodiment, the porous metal body 21b is made of Ni and has a thickness of 0.2 mm.

[0189] The porous metal body 21b is preferably made of a sintered body of metal particles. In this case, the metal particles may have various shapes, such as spherical, oval, flat, plate-like, or needle-like. The particle size of the metal particles is not particularly limited, but the average particle size is preferably 600 nm or less, and more preferably 20 nm to 500 nm.

[0190] The first dielectric film 22aD not only covers the surface of the metal porous body 21b in the part located on the outermost side of the capacitance forming portion 20D, but also covers the surface of the metal porous body 21b in the part located inside the capacitance forming portion 20D that is defined by the above-mentioned fine pores that are not closed by the metal porous body itself.

[0191] The conductive film 23D covers the surface of the first dielectric film 22aD except for the portions that define the outer edge portions (i.e., both ends in the left-right direction in FIG. 32 ) of the capacitance forming portion 20D in the direction parallel to the first main surface 10a of the insulating substrate 10. As a result, the first dielectric film 22aD has a non-exposed portion 221D that is covered with the conductive film 23D and an exposed portion 222D that is not covered with the conductive film 23D.

[0192] 32 and 33A, the surface of the first dielectric film 22aD other than the portion defining the outer edge of the capacitance forming portion 20D in the direction parallel to the first main surface 10a of the insulating substrate 10 is covered with the conductive film 23D, thereby constituting a non-exposed portion 221D. On the other hand, as shown in FIG. 32 and 33B, the surface of the first dielectric film 22aD defining the outer edge is not covered with the conductive film 23D, thereby constituting an exposed portion 222D.

[0193] In other words, the outer edge of the capacitance forming portion 20D in the direction parallel to the first main surface 10a is defined by the exposed portion 222D formed by the first dielectric film 22aD. Therefore, the outer edge of the surface of the capacitance forming portion 20D has an MI structure.

[0194] Fig. 34 is a flow diagram showing a method for manufacturing a capacitor according to this embodiment, and Fig. 35 and Fig. 36 are schematic cross-sectional views for explaining each step of the manufacturing flow shown in Fig. 34. Next, an example of a specific manufacturing method for manufacturing the capacitor 1D according to this embodiment described above will be described with reference to Fig. 34 to Fig. 36.

[0195] 34, the manufacturing method of capacitor 1D is largely similar to the manufacturing method of capacitor 1A. Therefore, in the following, a description of the steps in the manufacturing method of capacitor 1D that are common to the manufacturing method of capacitor 1A will be omitted, and only the steps that are different from the manufacturing method of capacitor 1A will be described.

[0196] As shown in FIG. 34, the method for manufacturing the capacitor 1D differs from the method for manufacturing the capacitor 1A (see FIG. 4, etc.) in that step S5D is performed instead of steps S6 to S8.

[0197] Specifically, after the insulating substrate as shown in FIG. 35 is obtained through the above-described steps S1 to S5, a porous metal body is formed in step S5D as shown in FIGS.

[0198] More specifically, conductive metal particles, an organic solvent such as terpineol, and an ethyl cellulose varnish are weighed and mixed, and a conductive paste is prepared from the mixture using a rolling mill. The conductive paste thus prepared is applied to the first main surface 10a of the insulating substrate 10 and dried.

[0199] At this time, the conductive paste is applied in multiple layers to have a predetermined thickness and a rectangular pattern shape as a whole when viewed from above, and is applied to the insulating substrate 10. Each layer of conductive paste applied to the insulating substrate 10 becomes the above-mentioned porous metal body 21b.

[0200] Next, insulating substrate 10 after the conductive paste is applied is degreased, and then the conductive paste is fired at temperatures of 400°C to 900°C in a reducing atmosphere, for example, a mixture of nitrogen and hydrogen. As a result, adjacent metal particles contained in the conductive paste form necks, and metal bonds are formed between connecting conductor 15 and the metal particles in contact therewith. As a result, metal porous body 21b is formed, and metal porous body 21b is bonded to connecting conductor 15.

[0201] The atmosphere during firing is preferably a reducing atmosphere as described above, but it may be set to an atmosphere below the equilibrium oxygen partial pressure of the metal selected as the main component of the metal porous body 21b.

[0202] The steps after the porous metal body 21b is formed in this manner are basically the same as steps S9 to S18 in the method for manufacturing the capacitor 1A. Through these steps, the capacitor 1D according to the fourth embodiment described above is manufactured.

[0203] Even when configured in this manner, the same effects as those described in the first embodiment can be obtained, and the reliability after mounting can be improved in a capacitor having a capacitance forming portion consisting of a conductive structure, a dielectric film, and a conductive film.

[0204] Furthermore, in the capacitor 1D according to this embodiment, as described above, the porous metal body 21b is composed of a sintered body of metal particles. In this configuration, the metal particles are metallically bonded to each other, improving the mechanical strength of the capacitance forming portion 20D and increasing the bonding area between the metal particles. This allows for a low ESR (equivalent series resistance). Furthermore, this configuration also provides the advantage of being able to relatively easily form a porous metal body with open pores.

[0205] It is of course possible to combine capacitor 1D according to the present embodiment with a characteristic configuration shown in capacitor 1A1 according to the first modified embodiment based on the above-described embodiment 1, in which the capacitance forming portion is electrically led out by the first external connection wiring from the outer surface side of the sealing portion, similar to the second external connection wiring.It is also of course possible to combine capacitor 1D with a characteristic configuration shown in capacitor 1A2 according to the second modified embodiment based on the above-described embodiment 1, in which the capacitance forming portion is electrically led out by the second external connection wiring from the second main surface side of the insulating substrate, similar to the first external connection wiring.

[0206] Here, when the structure 21D is composed of a metal porous body 21b, as in the capacitor 1D of this embodiment, the thickness of the sealing portion 30 is measured, for example, by observing a cross section perpendicular to the extension direction of the first main surface 10a of the insulating substrate 10 using an optical microscope.

[0207] Specifically, when capacitor 1D is viewed from above, the longitudinal direction of capacitor 1D is Lx, the lateral direction is Ly, and the thickness direction of capacitor 1D (i.e., the normal direction to first main surface 10a) is Lz. First, capacitor 1D is polished so that the Lx-Lz cross section of capacitor 1D at the center in the Ly direction is exposed. This polishing is performed so that the exposed cross section is located within an error range of ±100 μm in the Ly direction with respect to the center position.

[0208] Next, a portion of the exposed cross section near the outer surface 30a is observed using an optical microscope at a magnification of 1000. The observation range of the cross section in the Lx direction is within a range of ±50 μm from the center position of the cross section in the Lx direction.

[0209] Next, within the observation range of the cross section, the thickness of the sealing portion 30 in the Lz direction is measured at 10 locations equally spaced in the Lx direction, and the average value is calculated. The average value calculated in this manner is the thickness of the sealing portion 30. Here, in Figure 33(A), three of the thicknesses of the sealing portion 30 in the Lz direction measured at these 10 locations are illustrated as line segment lengths e1, e2, and e3.

[0210] Fifth Embodiment Fig. 37 is a schematic cross-sectional view of a capacitor according to a fifth embodiment. Figs. 38A and 38B are enlarged cross-sectional views of essential parts of regions XXXVIIIA and XXXVIIIB, respectively, of the capacitance forming portion shown in Fig. 37. A capacitor 1D according to this embodiment will now be described with reference to Figs. 37 and 38.

[0211] As shown in FIG. 37, a capacitor 1E according to this embodiment differs from the capacitor 1B according to the second embodiment described above in the configuration of a capacitance forming portion 20E.

[0212] The capacitance forming portion 20E has a conductive structure 21E, dielectric films including a first dielectric film 22aE, a second dielectric film 22bE and a third dielectric film 22cE, and a conductive film 23E.

[0213] The structure 21E and the first dielectric film 22aE have the same configurations as the structure 21D and the first dielectric film 22aD in the fourth embodiment described above, respectively.

[0214] The second dielectric film 22bE covers the entire surface of the first dielectric film 22aE. The third dielectric film 22cE covers a portion of the surface of the second dielectric film 22bE. More specifically, the third dielectric film 22cE covers the surface of a portion of the second dielectric film 22bE that defines the outer edge in a direction parallel to the first main surface 10a of the insulating substrate 10 (i.e., both ends in the left-right direction in FIG. 37 ) and the surface of the end on the outer surface 30a side of the sealing portion 30 in the normal direction to the first main surface 10a (i.e., the end in the upward direction in FIG. 37 ).

[0215] The conductive film 23E covers the surface of the portion of the second dielectric film 22bE that is not covered by the third dielectric film 22cE, so that the dielectric film has a non-exposed portion 221E that is covered by the conductive film 23E and an exposed portion 222E that is not covered by the conductive film 23E.

[0216] 37 and 38A, the surface of the portion of the second dielectric film 22bE that is not covered by the third dielectric film 22cE is covered with the conductive film 23E, so that the first dielectric film 22aE and the second dielectric film 22bE form a non-exposed portion 221E.

[0217] 37 and 38B, the surface of the portion of the second dielectric film 22bE that is covered with the third dielectric film 22cE is not covered with the conductive film 23E, so that the first dielectric film 22aE, the second dielectric film 22bE, and the third dielectric film 22cE form an exposed portion 222E.

[0218] In other words, at least the outer edge of the capacitance forming portion 20E in the direction parallel to the first main surface 10a is defined by the exposed portion 222E constituted by the first dielectric film 22aE, the second dielectric film 22bE, and the third dielectric film 22cE. Therefore, the outer edge of the surface of the capacitance forming portion 20E has an MI structure.

[0219] Fig. 39 is a flow diagram showing a method for manufacturing a capacitor according to this embodiment. As shown in Fig. 39, the method for manufacturing capacitor 1E differs from the method for manufacturing capacitor 1B (see Fig. 21) in that step S5D is performed instead of steps S6 to S8. Step S5D was described in detail in the description of the method for manufacturing capacitor 1D, so a detailed description of each step of the method for manufacturing capacitor 1E will be omitted here.

[0220] Even with this configuration, the same effects as those described in the second and fourth embodiments can be obtained, and the reliability after mounting can be improved in a capacitor having a capacitance forming portion consisting of a conductive structure, a dielectric film, and a conductive film.

[0221] It is of course possible to combine capacitor 1E according to the present embodiment with a characteristic configuration shown in capacitor 1A1 according to the first modified embodiment based on the above-described embodiment 1, in which the capacitance forming portion is electrically led out by the first external connection wiring from the outer surface side of the sealing portion, similar to the second external connection wiring.It is also of course possible to combine capacitor 1E with a characteristic configuration shown in capacitor 1A2 according to the second modified embodiment based on the above-described embodiment 1, in which the capacitance forming portion is electrically led out by the second external connection wiring from the second main surface side of the insulating substrate, similar to the first external connection wiring.

[0222] Sixth Embodiment Fig. 40 is a schematic cross-sectional view of a capacitor according to a sixth embodiment. Fig. 41(A) and Fig. 41(B) are enlarged cross-sectional views of essential parts of region XLIA and region XLIB, respectively, of the capacitance forming portion shown in Fig. 40. A capacitor 1F according to this embodiment will now be described with reference to Fig. 40 and Fig. 41 .

[0223] As shown in FIG. 40, a capacitor 1F according to this embodiment differs from the capacitor 1C according to the third embodiment described above in the configuration of a capacitance forming portion 20F.

[0224] The capacitance forming portion 20F has a conductive structure 21F, a dielectric film including a first dielectric film 22aF and a second dielectric film 22bF, and a conductive film 23F.

[0225] The structure 21F and the first dielectric film 22aF have the same configurations as the structure 21D and the first dielectric film 22aD in the fourth embodiment described above, respectively.

[0226] The second dielectric film 22bF covers a portion of the surface of the first dielectric film 22aF. More specifically, the second dielectric film 22bF covers the surface of the first dielectric film 22aF except for the portions that define the outer edge portions in the direction parallel to the first main surface 10a of the insulating substrate 10 (i.e., both ends in the left-right direction in FIG. 40 ). The conductive film 23F covers the entire surface of the second dielectric film 22bF.

[0227] As a result, the dielectric film has a non-exposed portion 221F covered with the conductive film 23F and an exposed portion 222F not covered with the conductive film 23F.

[0228] 40 and 41A, the entire surface of the second dielectric film 22bF is covered with the conductive film 23F, whereby the first dielectric film 22aF and the second dielectric film 22bF form a non-exposed portion 221F.

[0229] 40 and 41B, the surface of the portion of the first dielectric film 22aF that is covered by the second dielectric film 22bF (i.e., the portion of the first dielectric film 22aF that defines the outer edge in the direction parallel to the first main surface 10a of the insulating substrate 10) is not covered by the conductive film 23F, thereby forming an exposed portion 222F of the first dielectric film 22aF.

[0230] In other words, the outer edge of the capacitance forming portion 20F in the direction parallel to the first main surface 10a is defined by the exposed portion 222F formed by the first dielectric film 22aF. Therefore, the outer edge of the surface of the capacitance forming portion 20F has an MI structure.

[0231] Fig. 42 is a flow diagram showing a method for manufacturing a capacitor according to this embodiment. As shown in Fig. 42, the method for manufacturing capacitor 1F differs from the method for manufacturing capacitor 1C (see Fig. 27) in that step S5D is performed instead of steps S6 to S8. Step S5D was described in detail in the description of the method for manufacturing capacitor 1D, so a detailed description of each step of the method for manufacturing capacitor 1F will be omitted here.

[0232] Even with this configuration, the same effects as those described in the third and fourth embodiments can be obtained, and the reliability after mounting can be improved in a capacitor having a capacitance forming portion consisting of a conductive structure, a dielectric film, and a conductive film.

[0233] It is of course possible to combine capacitor 1F according to the present embodiment with the characteristic configuration shown in capacitor 1A1 according to the first modified embodiment based on the above-mentioned embodiment 1, in which the capacitance forming portion is electrically led out by the first external connection wiring from the outer surface side of the sealing portion, similar to the second external connection wiring.It is also of course possible to combine capacitor 1F with the characteristic configuration shown in capacitor 1A2 according to the second modified embodiment based on the above-mentioned embodiment 1, in which the capacitance forming portion is electrically led out by the second external connection wiring from the second main surface side of the insulating substrate, similar to the first external connection wiring.

[0234] Seventh Embodiment Fig. 43 is a schematic cross-sectional view of a capacitor according to a seventh embodiment. A capacitor 1G according to this embodiment will be described below with reference to Fig. 43 .

[0235] 43 , capacitor 1G according to this embodiment differs from capacitor 1D according to the fourth embodiment in that the moisture-resistant protective film 40 is used instead of sealing portion 30. Capacitor forming portion 20D is sealed by insulating substrate 10 and moisture-resistant protective film 40. This improves the moisture resistance of capacitor 1G.

[0236] As described above, the connecting conductor 15 is provided so as to cover the entire first main surface 10a. The connecting conductor 15 interposed between the insulating substrate 10 and the structure 21D in this manner includes an outer portion 15a that is located outside the structure 21D in the direction parallel to the first main surface 10a and extends to reach the edge of the insulating substrate 10.

[0237] The first dielectric film 22aD also covers the surface of the connecting conductor 15 in the portion not joined to the structure 21D. Specifically, the surface of the outer portion 15a located on the opposite side to the side facing the insulating substrate 10 is covered by the exposed portion 222D of the first dielectric film 22aD. Therefore, the outer end of the exposed portion 222D reaches the edge of the insulating substrate 10.

[0238] Here, the following three routes are considered as routes through which moisture can penetrate from the outside of the capacitor into the MIM structure.

[0239] The first path is a path from the outer surface 40a of the moisture-resistant protective film 40 in the thickness direction of the capacitor 1D (i.e., the normal direction of the first main surface 10a), through the first interface formed by the second via conductor 14 and the moisture-resistant protective film 40, and through the second interface formed by the moisture-resistant protective film 40 and the extraction electrode 18, to the conductive film 23D (see path RT1 in Figure 43).

[0240] The second path is a path from the outer end of the exposed portion 222D in a direction parallel to the first main surface 10a, through the third interface formed by the moisture-resistant protective film 40 and the exposed portion 222D, to the conductive film 23D (see path RT2 in Figure 43).

[0241] The third path is a path from the outer edge of the outer portion 15a in a direction parallel to the first main surface 10a, through the fourth interface formed by the exposed portion 222D and the connecting conductor 15, to the structure 21D (see path RT3 in Figure 43).

[0242] If the distance of the shortest path of path RT1 is R1, the distance of the shortest path of path RT2 is R2, and the distance of the shortest path of path RT3 is R3, the second via conductor 14 is arranged so as to satisfy R1>R2 and R1>R3.

[0243] By configuring in this manner, the risk of moisture penetrating through path RT1 and damaging the capacitor is reduced compared to capacitors configured to satisfy R1 < R2 or R1 < R3, and in this respect the moisture resistance of capacitor 1G is improved.

[0244] Furthermore, the shortest distance D (see FIG. 43 ) in the direction parallel to the first main surface 10 a between the outermost portion of the outer edge of the capacitance forming portion 20D in that direction and the edge of the insulating substrate 10 in that direction is preferably 5 μm or more and 200 μm or less, thereby ensuring sufficient lengths of the distances R2 and R3, and also in this respect improving the moisture resistance of the capacitor 1G.

[0245] Fig. 44 is a flow diagram showing a method for manufacturing a capacitor according to this embodiment. As shown in Fig. 44, the method for manufacturing capacitor 1G differs from the method for manufacturing capacitor 1D (see Fig. 34) in that step S15G is performed instead of step S15.

[0246] In step S15G, a moisture-resistant protective film 40 is provided on the first main surface 10a of the insulating substrate 10 on which the capacitance forming portion 20D is provided, so as to cover the capacitance forming portion 20D and the extraction electrode 18. The moisture-resistant protective film 40 is formed by, for example, a CVD method, an ALD method, or the like.

[0247] Even with this configuration, the same effects as those described in the fourth embodiment can be obtained, and the reliability after mounting can be improved in a capacitor having a capacitance forming portion consisting of a conductive structure, a dielectric film, and a conductive film.

[0248] It should be noted that the above-described characteristic configuration of capacitor 1G according to this embodiment can naturally be combined with a configuration in which the structure is made up of multiple pillars, as shown in capacitors 1A to 1C according to embodiments 1 to 3.

[0249] In addition, in the above-described embodiment, the case where the moisture-resistant protective film 40 is used has been exemplified, but instead of the moisture-resistant protective film 40, a combination of the sealing portion 30 and the moisture-resistant protective film 40 may be used.

[0250] Eighth Embodiment Fig. 45 is a schematic cross-sectional view of a capacitor according to an eighth embodiment. A capacitor 1H according to this embodiment will be described below with reference to Fig. 45 .

[0251] 45 , when compared with the capacitor 1D according to the fourth embodiment, the capacitor 1H according to the present embodiment differs mainly in that the moisture-resistant protective film 40 described above is used instead of the sealing portion 30, and in the configuration of the insulating substrate 10H. The capacitance forming portion 20D is sealed by the insulating substrate 10H and the moisture-resistant protective film 40.

[0252] Specifically, the insulating substrate 10H has a flat base portion 10s including a first main surface 10a and a second main surface 10b, and a peripheral wall portion 10t extending from the peripheral edge of the base portion 10s.

[0253] The capacitance forming portion 20D is disposed inside a recess defined by the base portion 10s and the peripheral wall portion 10t. A moisture-resistant protective film 40 having a predetermined thickness is interposed between the capacitance forming portion 20D and the peripheral wall portion 10t along a direction parallel to the first main surface 10a.

[0254] The connecting conductor 15 includes an extending portion 15b that is provided continuously on the first main surface 10a in a portion located outside the structure 21D in a direction parallel to the first main surface 10a, on the inner side surface 10t1 of the peripheral wall portion 10t, and on the top surface 10t2 of the peripheral wall portion 10t. The extending portion 15b reaches the outer end of the top surface 10t2 of the peripheral wall portion 10t in a direction parallel to the first main surface 10a.

[0255] The first dielectric film 22aD also covers the surface of the connecting conductor 15 in the portion not joined to the structure 21D. Specifically, the surface of the extending portion 15b located on the opposite side to the side facing the insulating substrate 10 is covered by the exposed portion 222D of the first dielectric film 22aD. Therefore, the outer end of the exposed portion 222D reaches the edge of the insulating substrate 10.

[0256] The capacitor 1H according to this embodiment can be manufactured basically in accordance with the manufacturing method of the capacitor 1G according to the seventh embodiment described above.

[0257] Even with this configuration, the same effects as those described in the fourth embodiment can be obtained, and the reliability after mounting can be improved in a capacitor having a capacitance forming portion consisting of a conductive structure, a dielectric film, and a conductive film.

[0258] Furthermore, by configuring insulating substrate 10H to have a generally concave shape, the distances of the shortest paths, namely, the path RT2 described above and the path from the outer edge of extension portion 15b in the direction parallel to first main surface 10a to structure 21D via the fifth interface formed by exposed portion 222D and connecting conductor 15 (see path RT4 in FIG. 45 ), are longer than when insulating substrate 10H is flat, thereby improving the moisture resistance of capacitor 1H.

[0259] Furthermore, in this embodiment, the position of the top surface 10t2 of the peripheral wall portion 10t in the thickness direction of the capacitor 1H is disposed outside the position of the capacitance forming portion 20D in the thickness direction of the capacitor 1H, thereby ensuring a sufficient distance between the shortest paths of the paths RT2 and RT4, and as a result, the moisture resistance of the capacitor 1H is further improved.

[0260] It should be noted that the above-described characteristic configuration of capacitor 1H according to this embodiment can naturally be combined with a configuration in which the structure is made up of multiple pillars, as shown in capacitors 1A to 1C according to embodiments 1 to 3.

[0261] In addition, in the above-described embodiment, the case where the moisture-resistant protective film 40 is used has been exemplified, but instead of the moisture-resistant protective film 40, a combination of the sealing portion 30 and the moisture-resistant protective film 40 may be used.

[0262] Ninth Embodiment Fig. 46 is a schematic cross-sectional view of a capacitor according to a ninth embodiment. A capacitor 1J according to the present embodiment will be described below with reference to Fig. 46 .

[0263] 46 , when compared with the capacitor 1D according to the fourth embodiment, the capacitor 1J according to the present embodiment differs mainly in that the moisture-resistant protective film 40 described above is used instead of the sealing portion 30, and in the configuration of the insulating substrate 10J. The capacitance forming portion 20D is sealed by the insulating substrate 10J and the moisture-resistant protective film 40.

[0264] Specifically, the insulating substrate 10J has a flat base 10s including a first main surface 10a and a second main surface 10b, and a peripheral wall 10t extending from the periphery of the base 10s. A top surface 10t2 of the peripheral wall 10t is positioned outward relative to the capacitance generating portion 20D in the thickness direction of the capacitor 1J. The capacitance generating portion 20D is positioned within a recess defined by the base 10s and the peripheral wall 10t.

[0265] The connecting conductor 15 includes an outer portion 15a that is provided continuously on the inner surface 10t1 of the peripheral wall portion 10t and on the top surface 10t2 of the peripheral wall portion 10t. The outer portion 15a is located outward of the structure 21D in a direction parallel to the first main surface 10a. The outer portion 15a reaches the outer end of the top surface 10t2 of the peripheral wall portion 10t in a direction parallel to the first main surface 10a.

[0266] The first dielectric film 22aD also covers the surface of the connecting conductor 15 in the portion not joined to the structure 21D. Specifically, the surface of the outer portion 15a located on the opposite side to the side facing the insulating substrate 10 is covered by the exposed portion 222D of the first dielectric film 22aD. Therefore, the outer end of the exposed portion 222D reaches the edge of the insulating substrate 10.

[0267] The outer edge of the capacitance forming portion 20D in a direction parallel to the first main surface 10a contacts the exposed portion 222D located on the inner surface 10t1 of the peripheral wall portion 10t. The shortest distance D (see FIG. 46 ) between the outermost portion of the capacitance forming portion 20D in the direction parallel to the first main surface 10a and the edge of the insulating substrate 10 in that direction is preferably 5 μm or more and 200 μm or less. This ensures sufficient lengths for the distances R2 and R3, thereby improving the moisture resistance of the capacitor 1J.

[0268] The capacitor 1J according to this preferred embodiment can be manufactured basically in accordance with the manufacturing method of the capacitor 1G according to the seventh preferred embodiment described above.

[0269] Even with this configuration, the same effects as those described in the fourth embodiment can be obtained, and the reliability after mounting can be improved in a capacitor having a capacitance forming portion consisting of a conductive structure, a dielectric film, and a conductive film.

[0270] It should be noted that the above-described characteristic configuration of capacitor 1J according to this embodiment can naturally be combined with a configuration in which the structure is made up of multiple pillars, as shown in capacitors 1A to 1C according to embodiments 1 to 3.

[0271] In addition, in the above-described embodiment, the case where the moisture-resistant protective film 40 is used has been exemplified, but instead of the moisture-resistant protective film 40, a combination of the sealing portion 30 and the moisture-resistant protective film 40 may be used.

[0272] (Additional Note) The characteristic configurations of the capacitor and the manufacturing method thereof disclosed in the above-described embodiment and its modifications can be summarized as follows.

[0273] [Supplementary Note 1] A capacitor comprising: an insulating substrate having a main surface; a capacitance forming portion provided on the main surface; and first and second external connection wirings connected to the capacitance forming portion, wherein the capacitance forming portion includes a conductive uneven or porous structure connected to the first external connection wiring, a dielectric film covering a surface of the structure, and a conductive film covering a portion of the dielectric film and connected to the second external connection wiring, wherein the outermost surface of the capacitance forming portion has an uneven shape, the dielectric film has an exposed portion not covered by the conductive film and a non-exposed portion covered by the conductive film, and an outer edge of the capacitance forming portion in a direction parallel to the main surface is defined by the exposed portion.

[0274] [Supplementary Note 2] The capacitor according to Supplementary Note 1, wherein the dielectric film includes a first dielectric film covering the surface of the structure, a second dielectric film covering the surface of the first dielectric film and having adhesion to the conductive film, and a third dielectric film covering a portion of the surface of the second dielectric film and not having adhesion to the conductive film, the non-exposed portion being constituted by the first dielectric film and the second dielectric film, and the exposed portion being constituted by the first dielectric film, the second dielectric film, and the third dielectric film.

[0275] [Appendix 3] The capacitor according to Appendix 1, wherein the dielectric film includes a first dielectric film covering the surface of the structure and a second dielectric film covering the surface of the first dielectric film and having adhesion to the conductive film, the non-exposed portion is formed by the first dielectric film and the second dielectric film, and the exposed portion is formed only by the first dielectric film.

[0276] [Supplementary Note 4] The capacitor according to any one of Supplementary Notes 1 to 3, wherein the second external connection wiring is located inside the outer edge of the capacitance forming portion in a direction parallel to the main surface.

[0277] [Supplementary Note 5] The capacitor according to any one of Supplementary Notes 1 to 4, wherein the structure is constituted by a plurality of pillars standing upright from the main surface.

[0278] [Appendix 6] The capacitor according to any one of Appendices 1 to 4, wherein the structure is made of a porous metal body.

[0279] [Supplementary Note 7] The capacitor according to any one of Supplementary Notes 1 to 6, wherein the structure is made of at least one conductive material selected from the group consisting of nickel, aluminum, and tantalum.

[0280] [Supplementary Note 8] A process comprising the steps of: preparing an insulating substrate having a main surface; forming a first external connection wiring on the insulating substrate; forming a conductive uneven or porous structure on the main surface; forming a first dielectric film so as to cover the surface of the structure when the structure and the first external connection wiring are connected to each other; forming a conductive film so as to cover the surface of the first dielectric film when the first dielectric film is formed, thereby forming a capacitance-forming portion made of the structure, the first dielectric film, and the conductive film, and having an uneven outermost surface; forming a second external connection wiring connected to the conductive film when the capacitance-forming portion is formed; forming a resist film so as to cover a portion of the surface of the second external connection wiring other than an outer edge portion of the conductive film in a direction parallel to the main surface when the conductive film and the second external connection wiring are connected to each other; a step of removing, with the resist film formed, a portion of the second external connection wiring not covered by the resist film and a portion of the conductive film covered by the second external connection wiring; and a step of removing the resist film with the portion of the second external connection wiring and the portion of the conductive film removed.

[0281] a step of forming a first dielectric film so as to cover the surface of the structure when the structure and the first external connection wiring are connected to each other; a step of forming a second dielectric film having adhesion to a conductive film so as to cover the surface of the first dielectric film when the first dielectric film is formed; a step of forming a third dielectric film having no adhesion to the conductive film so as to cover the surface of an outer edge portion of the second dielectric film in a direction parallel to the main surface when the second dielectric film is formed; a step of forming a third dielectric film having no adhesion to the conductive film so as to cover the surface of an outer edge portion of the second dielectric film in a direction parallel to the main surface when the third dielectric film is formed; a step of forming a capacitance forming portion consisting of the structure, the first dielectric film, the second dielectric film, the third dielectric film and the conductive film and having an uneven outermost surface when the third dielectric film is formed; and forming a second external connection wiring connected to the conductive film in a state where the capacitance forming portion has been formed.

[0282] [Supplementary Note 10] A process of preparing an insulating substrate having a main surface; a process of forming a first external connection wiring on the insulating substrate; a process of forming a conductive uneven or porous structure on the main surface; a process of forming a first dielectric film so as to cover the surface of the structure when the structure and the first external connection wiring are connected to each other; a process of forming a resist film so as to cover an outer edge portion of the first dielectric film in a direction parallel to the main surface when the first dielectric film is formed; a process of forming a second dielectric film having adhesion to a conductive film so as to cover the resist film and a portion of the first dielectric film not covered by the resist film when the resist film is formed; a process of removing the resist film and a portion of the second dielectric film covering the resist film when the second dielectric film is formed; a step of forming a capacitance forming portion having an uneven outermost surface, the capacitance forming portion being made of the structure, the first dielectric film, the second dielectric film, and the conductive film, by forming the conductive film so as to cover the surface of the second dielectric film in the portion that has not been removed, in a state where the resist film and a portion of the second dielectric film have been removed; and a step of forming a second external connection wiring connected to the conductive film in a state where the capacitance forming portion has been formed.

[0283] [Appendix 11] The method for manufacturing a capacitor according to any one of Appendices 8 to 10, wherein the structure is constituted by a plurality of pillars standing upright from the main surface.

[0284] [Appendix 12] The method for producing a capacitor according to any one of Appendices 8 to 10, wherein the structure is constituted by a porous metal body.

[0285] [Appendix 13] The method for manufacturing a capacitor according to any one of Appendices 8 to 12, wherein the structure is made of at least one conductive material selected from the group consisting of nickel, aluminum, and tantalum.

[0286] (Other Embodiments, etc.) The shape, configuration, size, number, material, etc. of each part shown in the above-described embodiment of the present invention can be changed in various ways without departing from the spirit of the present invention.

[0287] Furthermore, the characteristic configurations shown in the above-described embodiments of the present invention can naturally be combined with each other within the scope permitted in light of the spirit of the present invention.

[0288] As such, the above-described embodiments disclosed herein are illustrative in all respects and are not restrictive. The technical scope of the present invention is defined by the claims, and includes all modifications within the meaning and scope of the claims.

[0289] 1A to 1F, 1A1, 1A2 capacitor, 10, 10H, 10J insulating substrate, 10a first main surface, 10b second main surface, 10s base portion, 10t peripheral wall portion, 10t1 inner surface, 10t2 top surface, 11 first through hole, 12 second through hole, 13 first via conductor, 14 second via conductor, 15 connecting conductor, 15a outer portion, 15b extension portion, 16 first bump, 17 second bump, 18 extraction electrode, 18a upper surface, 20, 20B to 20F capacitance forming portion, 21, 21D to 21F structure, 21a columnar body, 21b metal porous body, 22a, 22aD to 22aF first dielectric film, 22b, 22bE, 22bF second dielectric film, 22c, 22cE Third dielectric film, 23, 23B to 23F conductive films, 24, 24C resist film, 30 sealing portion, 30a outer surface, 40 moisture-resistant protective film, 40a outer surface, 101 structure forming mold, 102 pores, 221, 221B to 221F non-exposed portions, 222, 222B to 222F exposed portions.

Claims

1. An insulating substrate having a main surface, A volume forming section provided on the main surface, The device comprises a first external connection wiring and a second external connection wiring connected to the capacity forming section, The capacitance forming section includes a conductive, uneven or porous structure connected to the first external connection wiring, a dielectric film covering the surface of the structure, and a conductive film covering a portion of the dielectric film and connected to the second external connection wiring. The outermost surface of the volume-forming portion has an uneven shape, The dielectric film has an exposed portion that is not covered by the conductive film and a non-exposed portion that is covered by the conductive film. The outer edge of the volume-forming portion in a direction parallel to the main surface is defined by the exposed portion. The second external connection wiring has a lead electrode provided on a surface located on the opposite side of the main surface of the capacitance forming portion, so as to cover the conductive film of the portion covering the non-exposed portion. A capacitor wherein a cavity is provided between the lead electrode and the conductive film in the portion located inside the capacitance forming portion and not covered by the lead electrode.

2. The dielectric film includes a first dielectric film covering the surface of the structure, a second dielectric film covering the surface of the first dielectric film and having adhesion to the conductive film, and a third dielectric film covering a part of the surface of the second dielectric film and not having adhesion to the conductive film. The non-exposed portion is composed of the first dielectric film and the second dielectric film. The capacitor according to claim 1, wherein the exposed portion is composed of the first dielectric film, the second dielectric film, and the third dielectric film.

3. The dielectric film includes a first dielectric film covering the surface of the structure and a second dielectric film covering the surface of the first dielectric film and having adhesion to the conductive film. The non-exposed portion is composed of the first dielectric film and the second dielectric film. The capacitor according to claim 1, wherein the exposed portion is composed solely of the first dielectric film.

4. The insulating substrate further comprises a moisture-resistant protective film, The capacitance forming portion is sealed by the insulating substrate and the moisture-resistant protective film. The first external connection wiring comprises a first via conductor that penetrates the insulating substrate in the direction normal to the main surface, and a connecting conductor interposed between the insulating substrate and the structure. The connecting conductor is connected to the first via conductor and the structure. The second external connection wiring has a second via conductor that penetrates the moisture-resistant protective film in the normal direction, The extraction electrode is connected to the second via conductor and the conductive film. The connecting conductor includes an outer portion that is located outside the structure in a direction parallel to the main surface and extends to the edge of the insulating substrate, The surface of the outer portion opposite to the side facing the insulating substrate is covered by the exposed portion. The capacitor according to claim 1, wherein the distance of the shortest path from the outer surface of the moisture-resistant protective film in the normal direction to the conductive film, via the first interface formed by the second via conductor and the moisture-resistant protective film and the second interface formed by the moisture-resistant protective film and the lead electrode, is R1; the distance of the shortest path from the outer end of the exposed portion in a direction parallel to the main surface to the conductive film, via the third interface formed by the moisture-resistant protective film and the exposed portion, is R2; and the distance of the shortest path from the outer edge of the outer portion in a direction parallel to the main surface to the structure, via the fourth interface formed by the exposed portion and the connecting conductor, is R3, the second via conductor is arranged such that R1 > R2 and R1 > R3.

5. The insulating substrate further comprises a moisture-resistant protective film, The capacitance forming portion is sealed by the insulating substrate and the moisture-resistant protective film. The first external connection wiring is interposed between the insulating substrate and the structure and has a connecting conductor connected to the structure. The insulating substrate has a base portion including the main surface and a peripheral wall portion erected from the peripheral edge of the base portion. The volume-forming portion is disposed inside the recess defined by the base portion and the peripheral wall portion. The connecting conductor includes an extension portion that is continuously provided on the main surface of the portion located outside the structure in a direction parallel to the main surface, on the inner surface of the peripheral wall, and on the top surface of the peripheral wall, so as to reach the outer end of the top surface of the peripheral wall in a direction parallel to the main surface of the peripheral wall, The surface of the extension portion opposite to the side facing the insulating substrate is covered by the exposed portion. The capacitor according to claim 1, wherein the position of the top surface of the peripheral wall portion in the direction normal to the main surface is located outside the position of the capacitance forming portion in the direction normal to the main surface.

6. The insulating substrate further comprises a moisture-resistant protective film, The capacitance forming portion is sealed by the insulating substrate and the moisture-resistant protective film. The first external connection wiring is interposed between the insulating substrate and the structure and has a connecting conductor connected to the structure. The connecting conductor includes an outer portion that is located outside the structure in a direction parallel to the main surface and extends to the edge of the insulating substrate, The surface of the outer portion opposite to the side facing the insulating substrate is covered by the exposed portion. The capacitor according to claim 1, wherein the shortest distance in the direction parallel to the main surface between the outermost portion of the outer edge in the direction parallel to the main surface and the edge of the insulating substrate is 5 μm or more.

7. The capacitor according to any one of claims 1 to 6, wherein, in a direction parallel to the main surface, the second external connection wiring is located inward from the outer edge of the capacitance forming portion.

8. The capacitor according to any one of claims 1 to 6, wherein the structure is composed of a plurality of columnar bodies erected from the main surface.

9. The capacitor according to any one of claims 1 to 6, wherein the structure is made of a porous metal.

10. The capacitor according to any one of claims 1 to 6, wherein the structure is made of at least one conductive material selected from nickel, aluminum, and tantalum.

11. A step in which an insulating substrate having a main surface is prepared, The first external connection wiring is formed on the insulating substrate, A step of forming a conductive, uneven or porous structure on the main surface, The process involves forming a first dielectric film so as to cover the surface of the structure while the structure and the first external connection wiring are connected to each other, A step in which, in the state in which the first dielectric film is formed, a conductive film is formed so as to cover the surface of the first dielectric film, thereby forming a capacitance forming portion consisting of the structure, the first dielectric film, and the conductive film, and having an uneven outer surface; In the state in which the capacitance forming portion is formed, the lead electrode of the second external connection wiring connected to the conductive film is formed on the surface of the capacitance forming portion opposite to the main surface side, thereby creating a cavity between the lead electrode and the portion of the conductive film located inside the capacitance forming portion and not covered by the lead electrode. A step in which, with the conductive film and the second external connection wiring connected to each other, a resist film is formed so as to cover the portion of the surface of the second external connection wiring that corresponds to the portion of the conductive film other than the outer edge in a direction parallel to the main surface of the conductive film, In the state in which the resist film is formed, the process involves removing the second external connection wiring in the portion not covered by the resist film, and the conductive film in the portion covered by the second external connection wiring in that portion, A method for manufacturing a capacitor, comprising the step of removing the resist film in a state in which a part of the second external connection wiring and a part of the conductive film have been removed.

12. A step in which an insulating substrate having a main surface is prepared, The first external connection wiring is formed on the insulating substrate, A step of forming a conductive, uneven or porous structure on the main surface, The process involves forming a first dielectric film so as to cover the surface of the structure while the structure and the first external connection wiring are connected to each other, In the state in which the first dielectric film is formed, a second dielectric film having adhesion to the conductive film is formed so as to cover the surface of the first dielectric film, A step of forming a third dielectric film that does not adhere to the conductive film, such that it covers the surface of the outer edge portion of the second dielectric film in a direction parallel to the main surface of the second dielectric film, while the second dielectric film is formed, In the state in which the third dielectric film is formed, the conductive film is formed so as to cover the surface of the second dielectric film in the portion not covered by the third dielectric film, thereby forming a capacitance forming portion consisting of the structure, the first dielectric film, the second dielectric film, the third dielectric film, and the conductive film, and having an uneven outer surface; A method for manufacturing a capacitor, comprising the step of forming a second external connection wiring connected to the conductive film while the capacitance forming portion is formed.

13. A step in which an insulating substrate having a main surface is prepared, The first external connection wiring is formed on the insulating substrate, A step of forming a conductive, uneven or porous structure on the main surface, The process involves forming a first dielectric film so as to cover the surface of the structure while the structure and the first external connection wiring are connected to each other, A step of forming a resist film so as to cover the outer edge of the first dielectric film in a direction parallel to the main surface of the first dielectric film, in the state in which the first dielectric film is formed. In the state in which the resist film is formed, a second dielectric film having adhesion to the conductive film is formed so as to cover the resist film and the portion of the first dielectric film not covered by the resist film. In the state in which the second dielectric film is formed, the resist film and the portion of the second dielectric film covering the resist film are removed. In a state in which a portion of the resist film and the second dielectric film have been removed, the conductive film is formed so as to cover the surface of the second dielectric film in the portion that has not been removed, thereby forming a capacitance forming portion consisting of the structure, the first dielectric film, the second dielectric film, and the conductive film, and having an uneven outer surface; A method for manufacturing a capacitor, comprising the step of forming a second external connection wiring connected to the conductive film while the capacitance forming portion is formed.

14. A method for manufacturing a capacitor according to any one of claims 11 to 13, wherein the structure is composed of a plurality of columnar bodies erected from the main surface.

15. A method for manufacturing a capacitor according to any one of claims 11 to 13, wherein the structure is made of a porous metal.

16. A method for manufacturing a capacitor according to any one of claims 11 to 13, wherein the structure is made of at least one conductive material selected from nickel, aluminum, and tantalum.