Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor of which the specifications or the like can be identified on the basis of a lamination direction view.　A multilayer ceramic capacitor 10 according to the present invention is characterized by comprising: a laminate having a first main face and a second main face opposite each other in the lamination direction, a first lateral face and a second lateral face opposite each other in a first direction orthogonal to the lamination direction, and a first end face and a second end face opposite each other in a second direction orthogonal to the lamination direction and the first direction; a first external electrode disposed on the first end face and the first main face; a second external electrode disposed on the second end face and the first main face; a third external electrode disposed on the first end face and the first main face; and a fourth external electrode disposed on the second end face and the first main face, wherein provided that flatness D1 is the maximum distance among the distances in the lamination direction x (vertical) between the first main face surface and a point where the first main face intersects with the first end face or the second end face and flatness D2 is the maximum distance among the distances in the lamination direction x (vertical) between the first main face surface and a point where the second main face intersects with the first end face or the second end face at the halfway position of the width connecting the first lateral face and the second lateral face of the laminate, then flatness D1 ≥ flatness D2.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] In recent years, as electronic devices incorporating multilayer ceramic capacitors become smaller in size, there has been a demand for multilayer ceramic capacitors with a lower height.

[0003] Patent Document 1 discloses a multilayer ceramic capacitor in which, when two adjacent sides are defined as a first side and a second side, the ratio of the length of the first side to the length of the second side is 0.9 or more and 1.1 or less.

[0004] Japanese Patent Application Laid-Open No. 2021-103730

[0005] However, in the multilayer ceramic capacitor described in Patent Document 1, in order to suppress cracks, conductors are provided in a region including the intersection of the perpendicular bisectors of two adjacent sides of a substantially rectangular shape, but this can lead to misalignment when the conductors are arranged, and the thickness of the conductor portion can become large.

[0006] Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor that can suppress the occurrence of cracks in the multilayer ceramic capacitor itself.

[0007] A multilayer ceramic capacitor according to the present invention includes a laminate having first and second main surfaces opposing each other in a stacking direction, first and second side surfaces opposing each other in a first direction perpendicular to the stacking direction, and first and second end surfaces opposing each other in a second direction perpendicular to the stacking direction and the first direction; first external electrodes arranged on the first end surfaces and the first main surface; second external electrodes arranged on the second end surfaces and the first main surface; a third external electrode arranged on the first end surfaces and the first main surface; and a second end surface. and a fourth external electrode disposed on the first main surface and the second main surface, wherein, at a position half the width connecting the first side surface and the second side surface of the laminate, the maximum distance in the stacking direction x (vertical) between the surface of the first main surface and an intersection point of the first main surface and the first end face or the second end face is defined as flatness D1, and the maximum distance in the stacking direction x (vertical) between the surface of the second main surface and an intersection point of the second main surface and the first end face or the second end face is defined as flatness D2, where flatness D1 is greater than or equal to flatness D2.

[0008] In the multilayer ceramic capacitor according to the present invention, when the maximum distance in the stacking direction x (vertical) between the first main surface and the first end face or the second end face and the surface of the first main surface at a position half the width connecting the first side surface and the second side surface of the laminate is defined as flatness D1, and the maximum distance in the stacking direction x (vertical) between the second main surface and the surface of the first main surface and the intersection of the second main surface and the first end face or the second end face is defined as flatness D2, flatness D1≧flatness D2 is satisfied. Therefore, when the multilayer ceramic capacitor is mounted, stress received from a nozzle that picks up the multilayer ceramic capacitor can be dispersed over the flat surface (second main surface), and therefore a multilayer ceramic capacitor can be provided that can improve the strength of the multilayer ceramic capacitor when mounted.

[0009] According to the present invention, a multilayer ceramic capacitor is provided that can suppress the occurrence of cracks in the multilayer ceramic capacitor itself.

[0010] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0011] 1 is an external perspective view, from one side, showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 2 is an external perspective view, from the other side, showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 3 is a front view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 4 is a side view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 5 is an external perspective view showing an example of a laminate of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 6 is a cross-sectional schematic view taken along line VI-VI in FIG. 1. FIG. 7 is a cross-sectional schematic view taken along line VII-VII in FIG. 1. FIG. 8 is a cross-sectional schematic view taken along line VIII-VIII in FIG. 1. FIG. 9 is a cross-sectional schematic view taken along line IX-IX in FIG. 1. FIG. 10 is a cross-sectional schematic view taken along line X-X in FIG. 1. FIG. 11 is a cross-sectional schematic view taken along line XI-XI in FIG. 3. FIG. 4 is an exploded perspective view of the laminate shown in FIG. 1. FIG. 5 is a cross-sectional schematic view showing an example of a multilayer ceramic capacitor according to a first modified example of the first embodiment of the present invention. FIG. 6 is a cross-sectional schematic view showing an example of a multilayer ceramic capacitor according to a second modified example of the first embodiment of the present invention. FIG. 7 is an external perspective view, from one side, showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. 15 is a schematic cross-sectional view taken along line XX-XX in FIG. 15; FIG. 16 is a schematic cross-sectional view taken along line XXI-XXI in FIG. 15; FIG. 17 is a schematic cross-sectional view taken along line XXII-XXII in FIG. 15; FIG. 18 is a schematic cross-sectional view taken along line XXIII-XXIII in FIG. 15;

[0012] A. First Embodiment 1. Multilayer Ceramic Capacitor Next, an example of a multilayer ceramic capacitor 10 according to an embodiment of the present invention will be described.

[0013] FIG. 1 is an external perspective view from one side showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 2 is an external perspective view from the other side showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 3 is a front view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 4 is a side view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 5 is an external perspective view showing an example of a laminate of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 1. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 1. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 1. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 1. FIG. 10 is a cross-sectional view taken along line X-X in FIG. 1. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 3. FIG. 12 is an exploded perspective view of the laminate shown in FIG. 1.

[0014] The multilayer ceramic capacitor 10 includes a laminate 12 and a plurality of external electrodes 30 .

[0015] The laminate 12 has a first main surface 12a and a second main surface 12b facing in a stacking direction x, a first side surface 12c and a second side surface 12d facing in a first direction y perpendicular to the stacking direction x, and a first end surface 12e and a second end surface 12f facing in a second direction z perpendicular to the stacking direction x and the first direction y. The direction connecting the first main surface 12a and the second main surface 12b of the laminate 12 is the stacking direction x.

[0016] Furthermore, it is preferable that the corners and ridges of the laminate 12 are rounded. Note that a corner refers to a portion where three adjacent faces of the laminate 12 intersect, and a ridge refers to a portion where two adjacent faces of the laminate 12 intersect. Furthermore, unevenness or the like may be formed on part or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0017] The flatness D2 of the second main surface 12b is equal to or less than the flatness D1 of the first main surface 12a. This means that the flatness of the second main surface 12b and the flatness of the first main surface 12a are equal to each other, or the second main surface 12b is flatter than the first main surface 12a. In this case, it is preferable that the first main surface 12a has a convex shape near the center.

[0018] In this embodiment, the flatness D1 and D2 are measured at a position ½W in the direction (first direction y) connecting the first side surface 12c and the second side surface 12d of the multilayer ceramic capacitor 10 when viewed from the stacking direction x, and in a region parallel to the direction (second direction z) connecting the first end surface 12e and the second end surface 12f of the multilayer ceramic capacitor 10, using a laser microscope (VK-X1000 manufactured by Keyence Corporation) at a magnification of 20. The flatness is defined as the maximum distance in the stacking direction x (perpendicular) between the intersection of the main surface and the end surface and the main surface.

[0019] Specifically, the flatness D1 on the first main surface 12a side is defined as follows. That is, as shown in Fig. 9 , in a region parallel to the direction (second direction z) connecting the first end face 12e and the second end face 12f of the multilayer ceramic capacitor 10, at a position of 1 / 2W in the direction (first direction y) connecting the first side face 12c and the second side face 12d, the intersection P1 between the first main surface 12a and the first end face 12e is defined as P1, and a point on the surface of the first main surface 12a is defined as P2. The maximum distance in the stacking direction x between P1 and P2 is defined as the flatness D1 on the first main surface 12a side in the second direction z.

[0020] The flatness D2 on the second main surface 12b side is defined as follows. That is, as shown in Fig. 9 , in a region parallel to the direction (second direction z) connecting the first end face 12e and the second end face 12f of the multilayer ceramic capacitor 10, at a position of 1 / 2W in the direction (first direction y) connecting the first side face 12c and the second side face 12d, the intersection P3 between the second main surface 12b and the first end face 12e is defined as point P3, and a point on the surface of the second main surface 12b is defined as point P4. The maximum distance in the stacking direction x between P3 and P4 is defined as the flatness D2 on the second main surface 12b side in the second direction z.

[0021] Furthermore, by satisfying the condition that the flatness D1 is greater than or equal to the flatness D2, the stress applied from the nozzle that picks up the multilayer ceramic capacitor 10 during mounting can be dispersed across a flat surface, thereby improving the strength of the multilayer ceramic capacitor 10 during mounting.

[0022] Furthermore, the flatness D2 of the second main surface 12b is preferably 4.2 μm or less. If the flatness D2 of the second main surface 12b is 4.2 μm or less, sufficient flatness is provided, and the dimension of the laminate 12 in the stacking direction x can be made relatively large, thereby improving the mechanical strength.

[0023] The laminate 12 includes a plurality of dielectric layers 14 and a plurality of internal electrodes 16. The dielectric layers 14 include an inner dielectric layer 14a and an outer dielectric layer 14b. The internal electrodes 16 include a first internal electrode 16a and a second internal electrode 16b.

[0024] The laminate 12 also has an inner layer portion 18, a first outer layer portion 20a located on the first main surface 12a side, and a second outer layer portion 20b located on the second main surface 12b side.

[0025] The first outer layer portion 20a is located on the first main surface 12a side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b located between the first main surface 12a and the internal electrode 16 closest to the first main surface 12a.

[0026] The second outer layer portion 20b is located on the second main surface 12b side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b located between the second main surface 12b and the internal electrode 16 closest to the second main surface 12b.

[0027] The region sandwiched between the first outer layer portion 20a and the second outer layer portion 20b is the inner layer portion 18.

[0028] The inner layer portion 18 has a first inner electrode 16a having one end exposed to the first side surface 12c and the first end face 12e and the other end exposed to the second side surface 12d and the second end face 12f, a second inner electrode 16b having one end exposed to the first side surface 12c and the second end face 12f and the other end exposed to the second side surface 12d and the first end face 12e, and an inner layer dielectric layer 14a.

[0029] The dielectric layer 14 can be formed from, for example, a dielectric material. Examples of the dielectric material include dielectric ceramics primarily composed of BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Substituents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may also be added to these primary components. The inner dielectric layer 14a and the outer dielectric layer 14b may be made of the same dielectric material, or may be made of different dielectric materials to separate the functions of the inner layer 18 and the outer layer 20a, 20b. For example, the inner dielectric layer 14a may have a high dielectric constant, while the outer dielectric layer 14b may have a composition with good moisture resistance, weather resistance, and strength. At least one of Si, Mg, Ba, and Mn may also be added as an additive. The additive is present between the ceramic particles.

[0030] For example, if the inner dielectric layer 14a contains a large amount of CaTiO3 or CaZrO3 as a dielectric component, it can make it difficult for insulation breakdown to occur between the first inner electrode 16a and the second inner electrode 16b. Furthermore, without being limited to this, the inner dielectric layer 14a can also be mainly composed of SrTiO3 or the like. Separately, in order to increase the capacitance of the multilayer ceramic capacitor 10, it is preferable that the inner dielectric layer 14a be made of a material with a high dielectric constant, such as BaTiO3.

[0031] The dielectric layer 14 may have a plurality of crystal grains containing a perovskite-type compound having a basic structure of BaTiO3.

[0032] The thinner the inner dielectric layer 14a, the greater the capacitance of the capacitor, so the crystal grain size is preferably 1 μm or less.

[0033] The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 3 to 700, including the first outer layer portion 20a and the second outer layer portion 20b. The thickness of the inner dielectric layer 14a is preferably 0.4 μm to 2.0 μm, and the thickness of the outer dielectric layer 14b is preferably 2.0 μm to 100.0 μm.

[0034] (Internal Electrode) The internal electrode 16 includes a plurality of first internal electrodes 16a and a plurality of second internal electrodes 16b. The first internal electrodes 16a and the second internal electrodes 16b are alternately stacked with the inner dielectric layers 14a interposed therebetween.

[0035] The first internal electrode 16a is disposed on the surface of the inner dielectric layer 14a. The first internal electrode 16a faces the first principal surface 12a and the second principal surface 12b, has a first opposing electrode portion 22a facing the second internal electrode 16b, and is laminated in a direction connecting the first principal surface 12a and the second principal surface 12b.

[0036] The first internal electrode 16a is extended by a first extension electrode portion 24a to the first side surface 12c and the first end surface 12e of the laminate 12, and is extended by a second extension electrode portion 24b to the second side surface 12d and the second end surface 12f of the laminate 12. The width of the first extension electrode portion 24a extended to the first side surface 12c may be approximately equal to the width of the first extension electrode portion 24a extended to the first end surface 12e, and the width of the second extension electrode portion 24b extended to the second side surface 12d may be approximately equal to the width of the second extension electrode portion 24b extended to the second end surface 12f.

[0037] The first internal electrode 16a is continuously extended to the first side surface 12c and the first end surface 12e of the laminate 12 by the first extension electrode portion 24a, and continuously extended to the second side surface 12d and the second end surface 12f of the laminate 12 by the second extension electrode portion 24b, but this is not limitative and the first internal electrode 16a may be discontinuously extended. The first internal electrode 16a may be arranged so that only one of the first side surface 12c to the second end surface 12f is exposed.

[0038] The second internal electrode 16b is disposed on a surface of the inner dielectric layer 14a different from the surface of the inner dielectric layer 14a on which the first internal electrode 16a is disposed. The second internal electrode 16b faces the first principal surface 12a and the second principal surface 12b, has a second opposing electrode portion 22b facing the first internal electrode 16a, and is laminated in a direction connecting the first principal surface 12a and the second principal surface 12b.

[0039] The second internal electrode 16b is extended by a third extension electrode portion 24c to the first side surface 12c and the second end surface 12f of the laminate 12, and is extended by a fourth extension electrode portion 24d to the second side surface 12d and the first end surface 12e of the laminate 12. The width of the third extension electrode portion 24c extended to the first side surface 12c may be approximately equal to the width of the third extension electrode portion 24c extended to the second end surface 12f, and the width of the fourth extension electrode portion 24d extended to the second side surface 12d may be approximately equal to the width of the fourth extension electrode portion 24d extended to the first end surface 12e.

[0040] The second internal electrode 16b is continuously extended to the first side surface 12c and the second end surface 12f of the laminate 12 by the third extension electrode portion 24c, and is continuously extended to the second side surface 12d and the first end surface 12e of the laminate 12 by the fourth extension electrode portion 24d, but this is not limitative and the second internal electrode 16b may be extended discontinuously. The second internal electrode 16b may be arranged so that only one of the first side surface 12c and the second end surface 12f is exposed.

[0041] Furthermore, when the multilayer ceramic capacitor 10 is viewed from the stacking direction x, it is preferable that a straight line connecting the first extraction electrode portion 24a and the second extraction electrode portion 24b of the first internal electrode 16a intersects with a straight line connecting the third extraction electrode portion 24c and the fourth extraction electrode portion 24d of the second internal electrode 16b.

[0042] As shown in FIG. 8 , the laminate 12 also includes a side portion (W gap) 26 a of the laminate 12 located between one end in the first direction y of the second opposing electrode portion 22 b of the second internal electrode 16 b and the first side surface 12 c, and a side portion (W gap) 26 b of the laminate 12 located between the other end in the first direction y of the first opposing electrode portion 22 a of the first internal electrode 16 a and the second side surface 12 d.

[0043] Furthermore, as shown in FIG. 9 , the laminate 12 includes an end portion (L gap) 28a of the laminate 12 located between one end in the second direction z of the second opposing electrode portion 22b of the second internal electrode 16b and the first end face 12e, and a side portion (L gap) 28b of the laminate 12 located between the other end in the second direction z of the first opposing electrode portion 22a of the first internal electrode 16a and the second end face 12f.

[0044] The first internal electrode 16a and the second internal electrode 16b can be made of an appropriate conductive material, such as, for example, metals such as Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ni-Cu alloys and Ag-Pd alloys, but are not limited thereto. Furthermore, the first internal electrode 16a and the second internal electrode 16b may be made of the same conductive material or different conductive materials.

[0045] Furthermore, by including Sn in the first internal electrode 16a and the second internal electrode 16b, it is possible to alleviate the electric field concentration at the interface between the internal electrode 16 and the dielectric layer 14, leading to an improvement in high-temperature load reliability. In this case, even if Sn is included in only one of the internal electrodes 16, either the first internal electrode 16a or the second internal electrode 16b, it is possible to achieve a sufficient effect.

[0046] The total number of the first internal electrodes 16a and the second internal electrodes 16b is preferably 3 to 700. The thickness of the first internal electrodes 16a and the second internal electrodes 16b is not particularly limited, but is preferably 0.2 μm to 2.0 μm, for example.

[0047] In the case where the internal electrodes 16 have this shape, the multilayer ceramic capacitor 10 may have the following configuration.

[0048] As shown in FIG. 10 , in the multilayer ceramic capacitor 10, when viewed from the first direction y, a region (LT plane) 5 μm inward from the first side surface 12 c in the first direction y and parallel to the second direction z preferably has a recess 40 recessed in the central portion of the first main surface 12 a in the stacking direction x. Also, a region (LT plane) 5 μm inward from the second side surface 12 d in the first direction y and parallel to the second direction z preferably has a recess 40 recessed in the central portion of the first main surface 12 a in the stacking direction x. When viewed from the first main surface 12 a in the stacking direction x, the centers of the first side surface 12 c and the second side surface 12 d have recesses. The second main surface 12 b may also have a similar configuration.

[0049] Furthermore, in the multilayer ceramic capacitor 10, when viewed from the second direction z, a region 5 μm inward from the first end face 12 e in the second direction z and parallel to the first direction y (WT plane) preferably has a recess 40 recessed in the central portion of the first main surface 12 a in the stacking direction x. Furthermore, a region 5 μm inward from the second end face 12 f in the second direction z and parallel to the first direction y preferably has a recess 40 recessed in the central portion of the first main surface 12 a in the stacking direction x. When viewed from the first main surface 12 a in the stacking direction x, the centers of the first end face 12 e and the second end face 12 f have recesses. The second main surface 12 b may also have a similar configuration.

[0050] In this way, by having an area that is the recess 40 on only one surface of the laminate 12, it is possible to distinguish between the front and back of the first main surface 12a and the second main surface 12b. Furthermore, since the distance on the end surfaces and side surfaces is curved, the distance between adjacent external electrodes 30, which will be described later, can be increased, thereby reducing the risk of electrical conduction between the external electrodes 30. Furthermore, when the external electrodes 30 are L-shaped, the recess 40 on the main surface on which the external electrodes 30 are not formed (the second main surface 12b) prevents complete contact between the nozzle that sucks the multilayer ceramic capacitor 10 and the suction surface of the multilayer ceramic capacitor 10. This prevents excessive suction during nozzle suction and suppresses the occurrence of cracks and other problems that may result from this excessive suction.

[0051] When the multilayer ceramic capacitor 10 is viewed from the first direction y, two or more regions convex in the stacking direction x may be present in a region (LT plane) that is 5 μm inward from the first side face 12 c in the first direction y and parallel to the second direction z. Furthermore, two or more regions convex in the stacking direction x may be present in a region (LT plane) that is 5 μm inward from the second side face 12 d in the first direction y and parallel to the second direction z. In this case, however, the region 5 μm inward from the first end face 12 e or the second end face 12 f in the second direction z and parallel to the first direction y is preferably flatter than the region 1 / 2 in the first direction y or the second direction z and the region 5 μm inward in the first direction y.

[0052] In addition, when viewed from the stacking direction x, recesses 40 may also be formed in the centers of the first end face 12e, the second end face 12f, the first side face 12c, and the second side face 12d.

[0053] By providing the above-described configuration, the distance between adjacent external electrodes 30 on the end faces and side faces can be increased by the amount of curvature, thereby reducing the risk of electrical conduction between the external electrodes 30.

[0054] 1 to 9, external electrodes 30 are arranged on the laminate 12. The external electrodes 30 include a plurality of external electrodes 30 connected to the first internal electrodes 16a and the second internal electrodes 16b. The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0055] The first external electrode 30a is disposed on the first side surface 12c and the first end face 12e so as to cover the first lead electrode portion 24a of the first internal electrode 16a, and further so as to cover a portion of the first main surface 12a. The first external electrode 30a is electrically connected to the first lead electrode portion 24a of the first internal electrode 16a. Note that the first external electrode 30a may be disposed so as to cover a portion of either the first side surface 12c or the first end face 12e that is exposed.

[0056] The second external electrode 30b is arranged on the second side surface 12d and the second end surface 12f so as to cover the second lead electrode portion 24b of the first internal electrode 16a, and further so as to cover a portion of the first main surface 12a. The second external electrode 30b is electrically connected to the second lead electrode portion 24b of the first internal electrode 16a. Note that the second external electrode 30b may be arranged so as to cover a portion of either the second side surface 12d or the second end surface 12f that is exposed.

[0057] The third external electrode 30c is arranged on the first side surface 12c and the second end surface 12f so as to cover the third lead electrode portion 24c of the second internal electrode 16b, and further so as to cover a portion of the first main surface 12a. The third external electrode 30c is electrically connected to the third lead electrode portion 24c of the second internal electrode 16b. Note that the third external electrode 30c may be arranged so as to cover a portion of either the first side surface 12c or the second end surface 12f that is exposed.

[0058] The fourth external electrode 30d is arranged on the second side surface 12d and the first end face 12e so as to cover the fourth lead electrode portion 24d of the second internal electrode 16b, and further so as to cover a portion of the first main surface 12a. The fourth external electrode 30d is electrically connected to the fourth lead electrode portion 24d of the second internal electrode 16b. Note that the fourth external electrode 30d may be arranged so as to cover a portion of either the second side surface 12d or the first end face 12f that is exposed.

[0059] In the laminate 12, the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b face each other via the inner dielectric layer 14a, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 30a and the second external electrode 30b to which the first internal electrode 16a is connected, and the third external electrode 30c and the fourth external electrode 30d to which the second internal electrode 16b is connected, thereby realizing the characteristics of a capacitor.

[0060] Each of the first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d preferably has a thin film layer 32, an underlayer plating layer 34, and a surface plating layer 36.

[0061] In other words, the first external electrode 30a preferably has a first thin film layer 32a, a first underlayer plating layer 34a, and a first surface plating layer 36a. The second external electrode 30b preferably has a second thin film layer 32b, a second underlayer plating layer 34b, and a second surface plating layer 36b. The third external electrode 30c preferably has a third thin film layer 32c, a third underlayer plating layer 34c, and a third surface plating layer 36c. The fourth external electrode 30d preferably has a fourth thin film layer 32d, a fourth underlayer plating layer 34d, and a fourth surface plating layer 36d.

[0062] (Thin Film Layers) The thin film layers 32 include a first thin film layer 32a, a second thin film layer 32b, a third thin film layer 32c, and a fourth thin film layer 32d.

[0063] The first thin film layer 32a is arranged so as to cover a portion of the first main surface 12a of the laminate 12 on the first side surface 12c side and the first end surface 12e side, and not to cover the first side surface 12c and the first end surface 12e of the laminate 12.

[0064] The second thin film layer 32b is arranged to cover a portion of the first main surface 12a of the laminate 12 on the second side surface 12d side and the second end surface 12f side, but not to cover the second side surface 12d and the second end surface 12f.

[0065] The third thin film layer 32c is arranged so as to cover a portion of the first main surface 12a of the laminate 12 on the first side surface 12c side and the second end surface 12f side, but not to cover the first side surface 12c and the second end surface 12f.

[0066] The fourth thin film layer 32d is arranged so as to cover a portion of the first main surface 12a of the laminate 12 on the first end face 12e side and the second side face 12d side, but not to cover the first end face 12e and the second side face 12d.

[0067] Each of the first to fourth thin film layers 32 a to 32 d is preferably formed by depositing metal particles by sputtering, vapor deposition, etc. This allows the thickness of the first to fourth thin film layers 32 a to 32 d in the direction connecting the first main surface 12 a and the second main surface 12 b of the laminate 12 to be 1 μm or less, and the dimension of the multilayer ceramic capacitor 10 in the stacking direction x can be sufficiently reduced, thereby making it possible to reduce the height of the multilayer ceramic capacitor 10.

[0068] The dimensions of the first to fourth thin film layers 32 a to 32 d in the stacking direction x can be measured as follows. That is, when the thin film layers are formed by depositing metal particles, a fluorescent X-ray device can be used to convert the concentration of a predetermined element into a thickness using a calibration curve method for the corresponding metal species. Alternatively, a cross section of a component can be observed using an FIB with a scanning microscope, and the thickness can be measured from the actual observation image.

[0069] Furthermore, when the first to fourth thin film layers 32a to 32d are formed by a thin film forming method, these thin film layers are preferably made of a metal such as Cu or Ni.

[0070] The thin film layers 32 of the multilayer ceramic capacitor 10 shown in Fig. 1 are formed by depositing metal particles by sputtering. In this case, if the thickness of the thin film layers 32 is 1 µm or less, the dimension in the stacking direction x can be made sufficiently small.

[0071] The first to fourth thin film layers 32a to 32d can be configured taking into consideration their respective functions. For example, it is preferable that the main component of each layer is at least one of Ni, Cr, and Cu, taking into consideration adhesion to the laminate 12. Furthermore, the first to fourth thin film layers 32a to 32d may be multiple layers.

[0072] The thin film layer 32 may be formed by screen printing or the like and contain a dielectric material and a metal component. This allows the thin film layer 32 to adhere to the ceramic of the laminate 12, thereby improving the adhesion between the laminate 12 and the external electrode 30. In this case, the thin film layer 32 may contain a ceramic component having the same main component as the inner dielectric layer 14a in addition to the metal component. The inclusion of a ceramic component in the thin film layer 32 reduces the difference in thermal expansion coefficient between the laminate 12 and the thin film layer 32, thereby alleviating stress on the thin film layer 32. However, the metal component may be other metal components besides Cu and Ni, or a glass component may be included in addition to the ceramic component. Examples of the glass component include oxides of Ba (barium), Sr (strontium), Si (silicon), Ca (calcium), Zn, Al, or B (boron). Other metal components may include Mg, Cr, Sr, Al, Na, Fe, etc. The thin film layer 32 may also have a discontinuous shape. The term "discontinuous" means that the film is formed discontinuously when viewed in a direction perpendicular to the longitudinal direction.

[0073] For example, when the thin film layer 32 is formed using a material containing ceramic, one method is to polish the cross section, then take a cross section photograph using a digital microscope (Keyence Corporation: VHX-5000), and use the cross section photograph to calculate the thickness, etc. Another method is to measure the thickness, etc. from the actual observation image of the cross section of the part taken by FIB using a scanning microscope.

[0074] (Underlayer Plating Layer) The underlayer plating layer 34 includes a first underlayer plating layer 34a, a second underlayer plating layer 34b, a third underlayer plating layer 34c, and a fourth underlayer plating layer 34d.

[0075] The first lower-layer plating layer 34a is disposed so as to cover the first thin film layer 32a and the first side surface 12c and first end surface 12e of the laminate 12. The second lower-layer plating layer 34b is disposed so as to cover the second thin film layer 32b and the second side surface 12d and second end surface 12f of the laminate 12. The third lower-layer plating layer 34c is disposed so as to cover the third thin film layer 32c and the first side surface 12c and second end surface 12f of the laminate 12. The fourth lower-layer plating layer 34d is disposed so as to cover the fourth thin film layer 32d and the second side surface 12d and first end surface 12e of the laminate 12.

[0076] The lower plating layer 34 contains at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, etc. The lower plating layer 34 is preferably Cu plating. In this case, the lower plating layer 34 may be directly connected to the internal electrode 16. In addition to this, another Cu plating layer with a different particle size may be provided.

[0077] The thickness of the lower plating layer 34 is preferably, for example, 1 μm or more and 10 μm or less.

[0078] (Surface Plating Layer) The surface plating layer 36 includes a first surface plating layer 36a, a second surface plating layer 36b, a third surface plating layer 36c, and a fourth surface plating layer 36d.

[0079] The first surface plating layer 36a is disposed so as to cover the first underlayer plating layer 34a. The second surface plating layer 36b is disposed so as to cover the second underlayer plating layer 34b. The third surface plating layer 36c is disposed so as to cover the third underlayer plating layer 34c. The fourth surface plating layer 36d is disposed so as to cover the fourth underlayer plating layer 34d.

[0080] The surface plating layer 36 may be, for example, only Sn plating, or may have a two-layer structure of Ni plating, Sn plating, or Ni plating and Cu plating. Furthermore, the surface plating layer 36 may be Sn plating, Ni plating, or Sn plating. The Ni plating can prevent the underlying electrode layer from being eroded by solder, and the Sn plating can improve the mountability of the multilayer ceramic capacitor 10.

[0081] The thickness of the surface plating layer 36 is preferably, for example, 1 μm or more and 10 μm or less.

[0082] The plating layer may be composed of only the lower plating layer 34. In this case, the first lower plating layer 34a is disposed so as to cover the first thin film layer 32a, and the second lower plating layer 34b is disposed so as to cover the second thin film layer 32b. Similarly, the third lower plating layer 34c is disposed so as to cover the third thin film layer 32c, and the fourth lower plating layer 34d is disposed so as to cover the fourth thin film layer 32d.

[0083] The plating layer preferably contains at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such a metal. The plating layer preferably does not contain glass. When the outermost layer of the plating layer is Au-plated, wire bonding connectivity with Au wire can be improved. Furthermore, when the outermost layer of the plating layer is Cu-plated, bonding with vias formed when the multilayer ceramic capacitor 10 is embedded in a mounting substrate can be improved.

[0084] The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0085] The thickness of each plating layer is preferably 0.5 μm or more and 10.0 μm or less.

[0086] The dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the first direction y is defined as dimension L, the dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the stacking direction x is defined as dimension T, and the dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the second direction z is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 are preferably such that the L dimension in the first direction y is 0.2 mm or more and 3.2 mm or less, the T dimension in the stacking direction x is 0.04 mm or more and 0.22 mm or less, and the W dimension in the second direction z is 0.2 mm or more and 3.2 mm or less. The dimensions of the multilayer ceramic capacitor 10 preferably satisfy the relationship 7 / 10≦L / W≦10 / 7. This allows the laminate 12 to have a substantially tetragonal shape, thereby improving the flexibility of mounting.

[0087] In the multilayer ceramic capacitor 10 shown in FIG. 1 , when the maximum distance in the stacking direction x (vertical) between the intersection of the first main surface 12 a and the first end face 12 e or the second end face 12 f and the surface of the first main surface 12 a at a position half the width connecting the first side surface 12 c and the second side surface 12 d of the laminate 12 is defined as flatness D1, and the maximum distance in the stacking direction x (vertical) between the intersection of the second main surface 12 b and the first end face 12 e or the second end face 12 f and the surface of the second main surface 12 b is defined as flatness D2, the flatness D1 is greater than the flatness D2. Therefore, when the multilayer ceramic capacitor 10 is mounted, stress received from a nozzle that picks up the multilayer ceramic capacitor 10 can be dispersed over the flat surface (second main surface 12 b), thereby improving the strength of the multilayer ceramic capacitor 10 during mounting.

[0088] 2. Modifications (1) First Modification Next, a multilayer ceramic capacitor 10A according to a first modification of the first embodiment of the present invention will be described. Fig. 13 is a cross-sectional schematic diagram showing an example of a multilayer ceramic capacitor according to the first modification of the first embodiment of the present invention. However, the same reference numerals are used to designate the same or corresponding components as those in Figs. 1 to 12, and detailed descriptions thereof will be omitted.

[0089] The external electrodes 30 of the multilayer ceramic capacitor 10A according to the first modification do not include a plating layer and are composed of a plurality of thin film layers. In the multilayer ceramic capacitor 10A shown in Fig. 13, the first external electrode 30a does not include a plating layer and is composed of only four thin film layers 32a1 to 32a4, and the second external electrode 30b does not include a plating layer and is composed of only four thin film layers 32b1 to 32b4.

[0090] In the first external electrode 30a, the thin film layer 32a extends from the first principal surface 12a to cover the first side surface 12c and the first end surface 12e. Then, thin film layers 32a2, 32a3, and 32a4 are formed in this order on the surface of the thin film layer 32a1. In the second external electrode 30b, the thin film layer 32b1 extends from the first principal surface 12a to cover the second side surface 12d and the second end surface 12f. Then, thin film layers 32b2, 32b3, and 32b4 are formed in this order on the surface of the thin film layer 32b1. Although not shown, the same applies to the third thin film layer 32c of the third external electrode 30c and the fourth thin film layer 32d of the fourth external electrode 30d.

[0091] In the first external electrode 30a, the edge portions of the laminate 12 made up of the four thin film layers 32a1 to 32a4 near the center may or may not be formed to cover the corresponding edge portions of the lower layers. Similarly, in the second external electrode 30b, the edge portions of the laminate 12 made up of the four thin film layers 32b1 to 32b4 near the center may or may not be formed to cover the corresponding edge portions of the lower layers. Although not shown, the same applies to the third thin film layer 32c of the third external electrode 30c and the fourth thin film layer 32d of the fourth external electrode 30d.

[0092] 13 according to the first embodiment, the multilayer ceramic capacitor 10A has the same effects as the multilayer ceramic capacitor 10 described above, and also has the following effect: The multilayer ceramic capacitor 10A does not include a plating layer, and the first external electrode 30a is composed only of thin film layers 32a1 to 32a4, the second external electrode 30b is composed only of thin film layers 32b1 to 32b4, and the third external electrode 30c and the fourth external electrode 30d also have a similar configuration, which reduces the T dimension in the stacking direction x, the L dimension in the first direction y, and the W dimension in the second direction z, thereby making it possible to reduce the dimensions of the multilayer ceramic capacitor.

[0093] (2) Second Modification Next, an example of a multilayer ceramic capacitor 10B according to a second modification of the first embodiment of the present invention will be described. Fig. 14 is a schematic cross-sectional view showing an example of a multilayer ceramic capacitor according to the second modification of the first embodiment of the present invention. However, the same reference numerals are used to designate the same or corresponding components as those in Figs. 1 to 12, and detailed descriptions thereof will be omitted.

[0094] As shown in FIG. 14, the external electrodes 30 of the multilayer ceramic capacitor 10B according to the second modified example of the first embodiment include a direct plating layer 33.

[0095] (Direct Plated Layer) The first external electrode 30a includes a first direct plated layer 33a, the second external electrode 30b includes a second direct plated layer 33b, and although not shown, the third external electrode 30c includes a third direct plated layer, and the fourth external electrode 30d includes a fourth direct plated layer.

[0096] The first direct plating layer 33a is arranged to cover a portion of each of the first side surface 12c and the first end surface 12e of the laminate 12, as well as the ridge portion sandwiched therebetween. The first direct plating layer 33a is electrically and directly connected to the first lead electrode portion 24a of the first internal electrode 16a. The second direct plating layer 33b is arranged to cover a portion of each of the second side surface 12d and the second end surface 12f of the laminate 12, as well as the ridge portion sandwiched therebetween. The second direct plating layer 33b is electrically and directly connected to the second lead electrode portion 24b of the first internal electrode 16a. Although not shown, the same applies to the third direct plating layer of the third external electrode 30c and the fourth direct plating layer of the fourth external electrode 30d.

[0097] The upper end of the first direct plating layer 33a of the first external electrode 30a is preferably arranged so as to overlap the underside of the first thin film layer 32a on the ridge formed by the first main surface 12a, the first side surface 12c, and the first end surface 12e of the laminate 12. The upper end of the second direct plating layer 33b of the second external electrode 30b is preferably arranged so as to overlap the underside of the second thin film layer 32b on the ridge formed by the first main surface 12a, the second side surface 12d, and the second end surface 12f of the laminate 12. Although not shown, the same applies to the third direct plating layer of the third external electrode 30c and the fourth direct plating layer of the fourth external electrode 30d.

[0098] Note that a portion of the first direct plating layer 33 a may be disposed so as to wrap around to the second main surface 12 b, and a portion of the second direct plating layer 33 b may be disposed so as to wrap around to the second main surface 12 b. Also, a portion of the third direct plating layer and a portion of the fourth direct plating layer may be disposed so as to wrap around to the second main surface 12 b.

[0099] The upper ends of the first and second direct plating layers 33 a and 33 b may be spaced apart from the first and second thin film layers 32 a and 32 b, respectively. The upper ends of the third and fourth direct plating layers may be spaced apart from the third and fourth thin film layers 32 c and 32 d, respectively.

[0100] The direct plating layer 33 is not particularly limited as long as it contains, as a main metal component, at least one metal selected from, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, etc. For example, when the first internal electrode 16 a and the second internal electrode 16 b are formed using Ni, it is preferable to adopt Cu plating as the direct plating layer 33, which has good bonding properties with Ni.

[0101] The direct plating layer 33 is formed by plating growing from the internal electrode 16 .

[0102] The thickness of each direct plating layer 33 is preferably 0.5 μm or more and 10.0 μm or less.

[0103] 14 according to the first embodiment, the multilayer ceramic capacitor 10B has the same effects as the above-described multilayer ceramic capacitor 10. That is, by forming the plating layer 33 directly on each side surface of the laminate 12, the thickness in the lamination direction of the external electrodes 30 formed on the first principal surface 12a and the second principal surface 12b can be further reduced, and therefore a multilayer ceramic capacitor with an even lower profile can be provided without impairing mountability during mounting.

[0104] Although not shown, the thin film layers 32 may be formed to wrap around to each side surface of the laminate 12. Specifically, the first thin film layer 32a of the first external electrode 30a is formed to cover a portion of the first main surface 12a and wrap around from each main surface to cover the first side surface 12c and the first end surface 12e. The second thin film layer 32b of the second external electrode 30b is formed to cover a portion of the first main surface 12a and wrap around from each main surface to cover the second side surface 12d and the second end surface 12f. The same applies to the third thin film layer 32c of the third external electrode 30c and the fourth thin film layer 32d of the fourth external electrode 30d.

[0105] Therefore, the first thin film layer 32a is directly electrically connected to the first lead electrode portion 24a of the first internal electrode 16a exposed from the first side surface 12c and the first end surface 12e. The second thin film layer 32b is directly electrically connected to the second lead electrode portion 24b of the first internal electrode 16a exposed from the second side surface 12d and the second end surface 12f. The third thin film layer 32c is directly electrically connected to the third lead electrode portion 24c of the second internal electrode 16b, and the fourth thin film layer 32d is directly electrically connected to the fourth lead electrode portion 24d of the second internal electrode 16b.

[0106] The first thin film layer 32a may be formed so that the thin film layer formed on the first main surface 12a and the thin film layer formed on the first side surface 12c and first end surface 12e are continuously or discontinuously connected. The second thin film layer 32b may be formed so that the thin film layer formed on the first main surface 12a and the thin film layer formed on the second side surface 12d and second end surface 12f are continuously or discontinuously connected. The same applies to the third thin film layer 32c of the third external electrode 30c and the fourth thin film layer 32d of the fourth external electrode 30d.

[0107] 3. Method for Manufacturing the Multilayer Ceramic Capacitor A method for manufacturing the multilayer ceramic capacitor, which is an example of the multilayer ceramic capacitor according to the first embodiment, will now be described.

[0108] (a) Manufacturing Method of Multilayer Ceramic Capacitor First, a conductive paste for the dielectric sheets and the internal electrodes is prepared. The conductive paste for the dielectric sheets and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0109] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, inkjet printing, screen printing, gravure printing, etc. This prepares a dielectric sheet on which the pattern of the first internal electrode is formed and a dielectric sheet on which the pattern of the second internal electrode is formed. Thereafter, the sheet on which the first internal electrode is printed and the sheet on which the second internal electrode is printed are laminated together to form a portion that becomes the inner layer portion 18.

[0110] Next, a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked to form the portion that will become the first outer layer portion 20a on the first main surface 12a. After that, the portion that will become the inner layer portion 18 prepared above is stacked, and a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked on top of this portion that will become the inner layer portion 18 to form the portion that will become the second outer layer portion 20b on the second main surface 12b. In this way, a laminated sheet is produced.

[0111] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0112] Next, the laminated block is cut to a predetermined size to cut out laminated chips. At this time, the corners and ridges of the laminated chips are rounded by barrel polishing or the like. During this barrel polishing, the first main surface 12a is polished so that its flatness in the second direction z is greater than that of the second main surface 12b in the second direction z. In other words, the first main surface 12a in the first direction z is less flat than the second main surface 12b in the second direction z.

[0113] The recesses 40 arranged on the first main surface 12a and the second main surface 12b are formed by, for example, cutting with a laser.

[0114] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0115] Next, the obtained laminate 12 is aligned on a work table, and a thin film layer 32 is formed on the first main surface 12 a and the second main surface 12 b by a sputtering method. At this time, by aligning the main surfaces so that the less flat main surface is on top, a thin film layer can be formed on the less flat main surface.

[0116] Thereafter, an underlayer plating layer 34 is formed on the thin film layer 32 and the surface of the laminate 12, and a surface plating layer 36 is formed to cover the underlayer plating layer 34. More specifically, a Cu plating layer is formed on the thin film layer 32 as the underlayer plating layer 34. Then, a Ni plating layer and an Sn plating layer are formed on the surface of the underlayer plating layer 34 as the surface plating layer 36. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0117] When manufacturing the multilayer ceramic capacitor 10B according to the second modification, the plating layer 33 is formed directly before the thin film layer 32 is formed.

[0118] First, a first direct plating layer 33a of the direct plating layer 33 is formed on the first side surface 12c and the first end surface 12e of the laminate 12, and a second direct plating layer 33b of the direct plating layer 33 is formed on the second side surface 12d and the second end surface 12f. Specifically, the direct plating layer 33 is assumed to be Cu plating and is formed by electrolytic plating or electroless plating. At this time, the plated laminate 12 is subjected to a heat treatment to remove residual moisture remaining in the plating film and at the interface between the laminate 12 and the direct plating layer 33.

[0119] Next, the laminate 12 on which the direct plating layer 33 has been formed is aligned on a work table, and the first thin film layer 32a and the second thin film layer 32b are formed on the first main surface 12a by sputtering.

[0120] Next, a first underlayer plating layer 34a is formed to cover the first direct plating layer 33a arranged on the first side surface 12c and first end surface 12e of the laminate 12 and the first thin film layer 32a arranged on a portion of the first main surface 12a of the laminate 12, and a first surface plating layer 36a is formed to cover the first underlayer plating layer 34a. Similarly, a second underlayer plating layer 34b is formed to cover the second direct plating layer 33b arranged on the second side surface 12d and second end surface 12f of the laminate 12 and the second thin film layer 32b arranged on a portion of the first main surface 12a of the laminate 12, and a second surface plating layer 36b is formed to cover the second underlayer plating layer 34b.

[0121] In this manner, the multilayer ceramic capacitor 10 according to the embodiment shown in Fig. 1 can be manufactured. When manufacturing the multilayer ceramic capacitor 10A of the first modified example shown in Fig. 13, the shapes of the corresponding portions are appropriately changed in each process.

[0122] B. Second Embodiment 1. Multilayer Ceramic Capacitor Next, an example of a multilayer ceramic capacitor 110 according to a second embodiment of the present invention will be described.

[0123] FIG. 15 is an external perspective view, from one side, of an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. FIG. 16 is an external perspective view, from the other side, of an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 17 is a front view of an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 18 is a side view of an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 19 is an external perspective view of an example of a laminate of a multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 15. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 15. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 15. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 15. Note that components that are the same as or equivalent to those in FIGS. 1 to 12 are designated by the same reference numerals, and detailed description thereof will be omitted.

[0124] The multilayer ceramic capacitor 110 includes a laminate 120 and a plurality of external electrodes 30 .

[0125] The laminate 120 has a first main surface 120a and a second main surface 120b that face in a stacking direction x, a first side surface 120c and a second side surface 120d that face in a first direction y that is orthogonal to the stacking direction x, and a first end surface 120e and a second end surface 120f that face in a second direction z that is orthogonal to the stacking direction x and the first direction y. The direction connecting the first main surface 120a and the second main surface 120b of the laminate 120 is the stacking direction x.

[0126] Furthermore, it is preferable that the corners and ridges of the laminate 120 are rounded. Note that a corner refers to a portion where three adjacent faces of the laminate 120 intersect, and a ridge refers to a portion where two adjacent faces of the laminate 120 intersect. Furthermore, unevenness or the like may be formed on part or all of the first main surface 120a and the second main surface 120b, the first side surface 120c and the second side surface 120d, and the first end surface 120e and the second end surface 120f.

[0127] The flatness D1 of the first main surface 120a in the second direction z is equal to or less than the flatness D2 of the second main surface 120b in the second direction z. This means that the flatness of the second main surface 120b in the second direction z and the flatness of the first main surface 120a in the second direction z are equivalent, or the second main surface 120b in the second direction z is flatter than the first main surface 120a in the second direction z.

[0128] The flatness D1 and D2 are measured at a position ½W in the direction (first direction y) connecting the first side surface 120c and the second side surface 120d of the multilayer ceramic capacitor 110 when the multilayer ceramic capacitor 110 is viewed from the stacking direction x, and in a region parallel to the direction (second direction z) connecting the first end face 120e and the second end face 120f using a laser microscope (VK-X1000 manufactured by Keyence Corporation) at a magnification of 20x. The flatness is defined as the maximum distance in the stacking direction x (perpendicular) between the intersection of the main surface and the end face and the main surface.

[0129] Specifically, the flatness D1 of the first main surface 120a in the second direction z is defined as follows. That is, as shown in Fig. 23 , in a region at a position ½W in the direction connecting the first side surface 120c and the second side surface 120d of the multilayer ceramic capacitor 110 (first direction y) and parallel to the direction connecting the first end surface 120e and the second end surface 120f (second direction z), an intersection P1 between the first main surface 120a and the first end surface 120e is defined as P1, and a point on the surface of the first main surface 120a is defined as point P2. Of the distances between P1 and P2, the maximum distance in the stacking direction x is defined as the flatness D1 of the first main surface 120a in the second direction z.

[0130] 23 , in a region parallel to the direction connecting the first end face 120e and the second end face 120f (second direction z), at a position ½W in the direction connecting the first side face 120c and the second side face 120d of the multilayer ceramic capacitor 110 (first direction y), the intersection P3 of the second main face 120b and the first end face 120e is defined as point P3, and a point on the surface of the second main face 120b is defined as point P4. Among the distances between P3 and P4, the maximum distance in the stacking direction x is defined as the flatness D2 of the second main face 120b in the second direction z.

[0131] Furthermore, the flatness D2 of the second main surface 120b in the second direction z is preferably 4.2 μm or less.

[0132] Furthermore, the flatness D3 of the first main surface 120a in the first direction y is equal to or less than the flatness D4 of the second main surface 120b in the first direction y. This means that the flatness of the second main surface 120b in the first direction y and the flatness of the first main surface 120a in the first direction y are equivalent, or the second main surface 120b in the first direction y is flatter than the first main surface 120a in the first direction y.

[0133] In the laminate 120 according to the second embodiment, the flatness D3 and D4 are measured at a position 1 / 2L in the direction connecting the first end face 120e and the second end face 120f of the laminate ceramic capacitor 110 (second direction z) when the laminated ceramic capacitor 10 is viewed from the stacking direction x, and in a region parallel to the direction connecting the first side face 120c and the second side face 120d (first direction y) using a laser microscope (VK-X1000 manufactured by Keyence Corporation) at a magnification of 20x. The flatness is defined as the maximum distance in the stacking direction x (perpendicular) between the main surface and the intersection point between the main surface and the side face.

[0134] Specifically, the flatness D3 on the first main surface 120a side in the first direction y is defined as follows. That is, as shown in Fig. 22 , in a region at a position 1 / 2L in the direction connecting the first end face 120e and the second end face 120f of the multilayer ceramic capacitor 110 (second direction z) and parallel to the direction connecting the first side face 120c and the second side face 120d (first direction y), an intersection P5 between the first main surface 120a and the first side face 120c is defined as P5, and a point on the surface of the first main surface 120a is defined as P6. Of the distances between P5 and P6, the maximum distance in the stacking direction x is defined as the flatness D3 on the first main surface 120a side in the first direction y.

[0135] 22 , in a region parallel to the direction connecting the first side surface 120c and the second side surface 120d (first direction y), at a position ½L in the direction connecting the first end surface 120e and the second end surface 120f of the multilayer ceramic capacitor 110 (second direction z), the intersection point P7 between the second main surface 120b and the first side surface 120c is defined as P7, and a point on the surface of the second main surface 120b is defined as point P8. The maximum distance between P7 and P8 in the stacking direction x is defined as the flatness D4 of the second main surface 120b in the first direction y.

[0136] Furthermore, the flatness D4 of the second main surface 120b in the first direction y is preferably 4.2 μm or less.

[0137] In this case, the first main surface 120a has a convex shape near the center, which allows the dimension of the central portion of the laminate 120 in the stacking direction x to be larger than that of other portions, thereby improving the mechanical strength.

[0138] The first internal electrode 16a of the internal electrode 16 is extended to the first side surface 120c and the first end surface 120e of the laminate 120 by the first extension electrode portion 24a, and is extended to the second side surface 120d and the second end surface 120f of the laminate 120 by the second extension electrode portion 24b.

[0139] The second internal electrode 16b of the internal electrode 16 is extended to the first side surface 120c and the second end surface 120f of the laminate 120 by the third extension electrode portion 24c, and is extended to the second side surface 120d and the first end surface 120e of the laminate 120 by the fourth extension electrode portion 24d.

[0140] In the multilayer ceramic capacitor 110 according to the second embodiment, the external electrodes 30 are arranged so as to cover the first main surface 120a of the laminate 120 but not the second main surface 120b.

[0141] 15 to 23, external electrodes 30 are arranged on the laminate 120. The external electrodes 30 include a plurality of external electrodes 30 connected to the first internal electrodes 16a and the second internal electrodes 16b. The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0142] The first external electrode 30a is disposed on the first side surface 120c and the first end surface 120e so as to cover the first lead electrode portion 24a of the first internal electrode 16a, and further so as to cover a portion of the first main surface 120a. The first external electrode 30a is electrically connected to the first lead electrode portion 24a of the first internal electrode 16a.

[0143] The second external electrode 30b is disposed on the second side surface 120d and the second end surface 120f so as to cover the second lead electrode portion 24b of the first internal electrode 16a, and further so as to cover a portion of the first main surface 120a. The second external electrode 30b is electrically connected to the second lead electrode portion 24b of the first internal electrode 16a.

[0144] The third external electrode 30c is disposed on the first side surface 120c and the second end surface 120f so as to cover the third lead electrode portion 24c of the second internal electrode 16b, and further so as to cover a part of the first main surface 120a. The third external electrode 30c is electrically connected to the third lead electrode portion 24c of the second internal electrode 16b.

[0145] The fourth external electrode 30d is disposed on the second side surface 120d and the first end surface 120e so as to cover the fourth lead electrode portion 24d of the second internal electrode 16b, and further so as to cover a part of the first main surface 120a. The fourth external electrode 30d is electrically connected to the fourth lead electrode portion 24d of the second internal electrode 16b.

[0146] According to the multilayer ceramic capacitor 110 of the second embodiment, the first main surface has a convex shape, so that the dimension in the stacking direction x at the central portion can be made larger than the dimension in the stacking direction x of the remaining portion, thereby further improving the mechanical strength of the laminate 120.

[0147] 2. Method for Manufacturing a Multilayer Ceramic Capacitor A method for manufacturing a multilayer ceramic capacitor, which is an example of a multilayer ceramic capacitor according to the second embodiment, will now be described.

[0148] First, a conductive paste for the dielectric sheets and the internal electrodes is prepared. The conductive paste for the dielectric sheets and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0149] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, inkjet printing, screen printing, gravure printing, etc. This prepares a dielectric sheet on which the pattern of the first internal electrode is formed and a dielectric sheet on which the pattern of the second internal electrode is formed. Thereafter, the sheet on which the first internal electrode is printed and the sheet on which the second internal electrode is printed are laminated together to form a portion that becomes the inner layer portion 18.

[0150] Next, a predetermined number of dielectric sheets without printed internal electrode patterns are stacked to form the portion that will become the first outer layer portion 20a on the first main surface 120a. After that, the portion that will become the inner layer portion 18 prepared above is stacked, and a predetermined number of dielectric sheets without printed internal electrode patterns are stacked on top of this portion that will become the inner layer portion 18 to form the portion that will become the second outer layer portion 20b on the second main surface 120b. In this way, a laminated sheet is produced.

[0151] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0152] Next, the laminated block is cut to a predetermined size to cut out laminated chips. At this time, the corners and ridges of the laminated chips are rounded by barrel polishing or the like. During this barrel polishing, the flatness of the first main surface 120a in the first direction y is polished to be greater than the flatness of the second main surface 120b in the first direction y, and the flatness of the first main surface 120a in the second direction z is polished to be greater than the flatness of the second main surface 120b in the second direction z.

[0153] The recesses 40 arranged on the first main surface 120a and the second main surface 120b are formed by, for example, cutting with a laser.

[0154] Next, the laminated chip is fired to produce the laminate 120. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0155] Next, the resulting laminate 120 is aligned on a work table, and the thin film layer 32 is formed on the first main surface 120a by sputtering.

[0156] Next, the resulting laminate 120 is aligned on a work table, and the thin film layer 32 is formed on the first main surface 120a by sputtering.

[0157] Thereafter, an underlayer plating layer 34 is formed on the thin film layer 32 and the surface of the laminate 120, and a surface plating layer 36 is formed to cover the underlayer plating layer 34. More specifically, a Cu plating layer is formed on the thin film layer 32 as the underlayer plating layer 34. Then, a Ni plating layer and an Sn plating layer are formed on the surface of the underlayer plating layer 34 as the surface plating layer 36. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0158] In this manner, the multilayer ceramic capacitor 110 according to the second embodiment shown in FIG. 15 can be manufactured.

[0159] According to the method for manufacturing a multilayer ceramic capacitor of this embodiment, it is possible to reduce the thickness of the external electrodes 30 formed on the first principal surface 120 a and the second principal surface 120 b in the lamination direction x, which is the dimension T, and therefore it is possible to provide a multilayer ceramic capacitor with a reduced height without impairing mountability during mounting.

[0160] 3. Experimental Example Next, in order to confirm the effects of the multilayer ceramic capacitor according to the present invention described above, a multilayer ceramic capacitor sample was fabricated according to the manufacturing method described above as an experimental sample, and an experiment was conducted to confirm the presence or absence of cracks in response to changes in flatness.

[0161] (1) Specifications of Samples in Experimental Examples First, in accordance with the above-described method for manufacturing a multilayer ceramic capacitor, samples of multilayer ceramic capacitors corresponding to sample numbers 1 to 9 having the following specifications were fabricated.

[0162] (Specifications of the Multilayer Ceramic Capacitor) - Dimensions of the multilayer ceramic capacitor: L x W x T = 600 μm x 600 μm x 80 μm - Total number of stacked internal electrode layers: 30 - Thickness per internal electrode layer: 0.5 μm - Thickness in the stacking direction of the external electrode placed on the first principal surface: 10 μm - Configuration of the external electrode on the end face: A three-layer structure consisting of, from the laminate side, a Cu plating layer, a Ni plating layer, and a Sn plating layer - Configuration of the external electrode on the principal surface: A four-layer structure consisting, from the laminate side, of a sputtered electrode containing at least one of Ni, Cr, and Cu, a Cu plating layer, a Ni plating layer, and a Sn plating layer - Flatness D1 of the first principal surface: Fixed at 4.2 μm. - Flatness D2 of the second principal surface: See Table 1. The flatness D2 of the second principal surface was varied within the range of Table 1.

[0163] (2) Method for Measuring Flatness When the multilayer ceramic capacitor is viewed from the stacking direction, the flatness was measured at 1 / 2W in the direction connecting the first side surface and the second side surface of the multilayer ceramic capacitor (first direction y) and in a region parallel to the direction connecting the first end face and the second end face (second direction z) using a laser microscope (Keyence Corporation: VK-X1000) at a magnification of 20. The flatness was defined as the maximum distance in the stacking direction x (vertical) between the intersection of the main surface and the end face and the main surface.

[0164] (3) Evaluation Method for Crack Occurrence The flatness of each sample multilayer ceramic capacitor whose main surface flatness had been manipulated was measured using the method described above. Then, the presence or absence of cracks on the main surface of each sample multilayer ceramic capacitor was confirmed using an optical microscope when the sample multilayer ceramic capacitor was pressed into place using a nozzle equipped with a buffer mechanism. The center of the nozzle equipped with a buffer mechanism was set at the center point where a diagonal line was drawn on the second main surface, and the nozzle was pressed into place to a level that would allow the minimum transfer of the sample multilayer ceramic capacitor to the solder-mounted portion. The presence or absence of cracks was confirmed by observing the presence or absence of cracks when viewed from the lamination direction x and by polishing the cross section of the laminate at 1 / 2 W and 1 / 2 of the external electrodes in the direction connecting the first and second side surfaces of the laminate. The number of samples with cracks was counted out of 100 samples for each sample number.

[0165] (3) Results Table 1 shows the number of cracks that occurred for sample numbers 1 to 9.

[0166]

[0167] According to Table 1, the flatness of the second main surface of each of samples No. 1 to No. 5 was equal to or less than the flatness of the first main surface, and therefore the number of cracks that occurred was relatively low.

[0168] Furthermore, since the flatness of the second main surface of each of Sample Nos. 1 to 5 was 4.2 μm or less, the number of cracks generated in each sample was relatively kept to 5 or less, and good results were obtained.

[0169] From the above results, it was confirmed that in the present invention, since the flatness of the second main surface is equal to or less than the flatness of the first main surface, the number of cracks occurring in the laminate can be relatively suppressed. Furthermore, it was confirmed that if the flatness of the second main surface is 4.2 μm or less, the number of cracks occurring in the laminate in each sample can be further suppressed.

[0170] As described above, although the embodiment of the present invention has been disclosed in the description above, the present invention is not limited thereto. For example, even when the external electrode 30 is disposed on the first main surface 12 a and the second main surface 12 b, the occurrence of cracks can be suppressed by configuring the pickup surface of the nozzle to be the second main surface 12 b.

[0171] In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position or arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and these modifications are included in the present invention.

[0172] <1> A laminate having a first main surface and a second main surface that face each other in a stacking direction, a first side surface and a second side surface that face each other in a first direction orthogonal to the stacking direction, and a first end surface and a second end surface that face each other in a second direction orthogonal to the stacking direction and the first direction, a first external electrode arranged on the first end surface and the first main surface, a second external electrode arranged on the second end surface and the first main surface, a third external electrode arranged on the first end surface and the first main surface, and a fourth external electrode arranged on the second end surface and the first main surface, wherein, at a position that is half the width connecting the first side surface and the second side surface of the laminate, a maximum distance in the stacking direction x (vertical) between an intersection of the first main surface and the first end surface or the second end surface and the surface of the first main surface is defined as flatness D1, a multilayer ceramic capacitor, wherein when a maximum distance in a lamination direction x (vertical) between an intersection of the second main surface and the first end face or the second end face and a surface of the second main surface is defined as a flatness D2, the flatness D1 is greater than or equal to the flatness D2.

[0173] <2> The multilayer ceramic capacitor according to <1>, wherein, at a position half the length connecting the first end face and the second end face of the laminate, a maximum distance in the stacking direction x (vertical) between an intersection of the first main surface and the first side face or the second side face and the first main surface surface is defined as a flatness D3, and a maximum distance in the stacking direction x (vertical) between an intersection of the second main surface and the first side face or the second side face and the first main surface surface is defined as a flatness D4, wherein the flatness D3 is greater than or equal to the flatness D4.

[0174] <3> A laminate having a first main surface and a second main surface that face each other in a stacking direction, a first side surface and a second side surface that face each other in a first direction orthogonal to the stacking direction, and a first end surface and a second end surface that face each other in a second direction orthogonal to the stacking direction and the first direction, a first external electrode arranged on the first end surface and the first main surface, a second external electrode arranged on the second end surface and the first main surface, a third external electrode arranged on the first end surface and the first main surface, and a fourth external electrode arranged on the second end surface and the first main surface, wherein, at a position that is half the width connecting the first side surface and the second side surface of the laminate, a maximum distance in the stacking direction x (vertical) between an intersection of the first main surface and the first end surface or the second end surface and the surface of the first main surface is defined as flatness D1, a flatness D2 is 4.2 μm or less, when the maximum distance among distances in the lamination direction x (vertical) between an intersection of the second main surface and the first end face or the second end face and a surface of the second main surface is defined as a flatness D2.

[0175] <4> The multilayer ceramic capacitor according to claim 3, wherein, at a position half the length connecting the first end face and the second end face of the laminate, a maximum distance among distances in the stacking direction x (vertical) between an intersection of the first main surface and the first side face or the second side face and the first main surface surface is defined as flatness D3, and a maximum distance among distances in the stacking direction x (vertical) between an intersection of the second main surface and the first side face or the second side face and the first main surface surface is defined as flatness D4, and the maximum distance among distances in the stacking direction x (vertical) between an intersection of the second main surface and the first side face or the second side face and the first main surface surface is defined as flatness D4, and the flatness D4 is 4.2 μm or less.

[0176] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the first main surface has a convex shape.

[0177] <6> The multilayer ceramic capacitor according to <1> or <2>, wherein the flatness D2 is 4.2 μm or less.

[0178] <7> The multilayer ceramic capacitor according to <2>, wherein the flatness D4 is 4.2 μm or less.

[0179] <8> The laminate includes an inner layer portion, the inner layer portion including: a first internal electrode having one end exposed to the first end face and the first side face and another end exposed to the second end face and the second side face; a second internal electrode having one end exposed to the first end face and the second side face and another end exposed to the second end face and the first side face; and an inner-layer dielectric layer; and the second main surface has a recess recessed in the lamination direction in a region 5 μm inward from the first side face and the second side face in a direction connecting the first side face and the second side face of the laminate.

[0180] <9> The laminate includes an inner layer portion, the inner layer portion including: a first internal electrode having one end exposed to the first end face and the first side face and another end exposed to the second end face and the second side face; a second internal electrode having one end exposed to the first end face and the second side face and another end exposed to the second end face and the first side face; and an inner-layer dielectric layer; and the first main surface has a recess recessed in the stacking direction in a region 5 μm inward from the first side face and the second side face in a direction connecting the first side face and the second side face of the laminate.

[0181] <10> The laminate includes an inner layer portion, the inner layer portion including: a first internal electrode having one end exposed at the first end face and the first side face and another end exposed at the second end face and the second side face; a second internal electrode having one end exposed at the first end face and the second side face and another end exposed at the second end face and the first side face; and an inner-layer dielectric layer; and the second main surface has a recess recessed in the stacking direction in a region 5 μm inward from the first end face and the second end face in a direction connecting the first end face and the second end face of the laminate.

[0182] <11> The multilayer ceramic capacitor according to any one of <1> to <10>, wherein the laminate includes an inner layer portion, the inner layer portion including: a first internal electrode having one end exposed at the first end face and the first side face and another end exposed at the second end face and the second side face; a second internal electrode having one end exposed at the first end face and the second side face and another end exposed at the second end face and the first side face; and an inner-layer dielectric layer, wherein a central portion of the first main surface has a recess recessed in the stacking direction, in a region 5 μm inward from the first end face and the second end face in a direction connecting the first end face and the second end face of the laminate.

[0183] <12> The multilayer ceramic capacitor according to <1> or <3>, wherein, when viewed from the second main surface in the stacking direction, the first side surface and the second side surface have a central portion with a recess.

[0184] <13> The multilayer ceramic capacitor according to <1> or <3>, wherein, when viewed from the first main surface in the stacking direction, the first side surface and the second side surface have a central portion with a recess.

[0185] <14> The multilayer ceramic capacitor according to <1> or <3>, wherein, when viewed from the second main surface in the stacking direction, the first end face and the second end face have central portions each having a recess.

[0186] <15> The multilayer ceramic capacitor according to <1> or <3>, wherein, when viewed from the first main surface in the stacking direction, the first end face and the second end face have central portions each having a recess.

[0187] 10, 10A, 10B, 110 Multilayer ceramic capacitor 12, 120 Laminate 12a, 120a First main surface 12b, 120b Second main surface 12c, 120c First side surface 12d, 120d Second side surface 12e, 120e First end surface 12f, 120f Second end surface 14 Dielectric layer 14a Inner dielectric layer 14b Outer dielectric layer 16 Internal electrode 16a First internal electrode 16b Second internal electrode 18 Internal layer portion 20a First outer layer portion 20b Second outer layer portion 22a First opposing electrode portion 22b Second opposing electrode portion 24a First lead electrode portion 24b Second lead electrode portion 24c Third lead electrode portion 24d Fourth lead electrode portion 26a, 26b Sides of laminate (W gap) 28a, 28b Ends of laminate (L gap) 30 External electrode 30a First external electrode 30b Second external electrode 30c Third external electrode 30d Fourth external electrode 32 Thin film layer 32a First thin film layer 32b Second thin film layer 32c Third thin film layer 32d Fourth thin film layer 34 Underlayer plating layer 34a First underlayer plating layer 34b Second underlayer plating layer 34c Third underlayer plating layer 34d Fourth underlayer plating layer 36 Top layer plating layer 36a First surface plating layer 36b Second surface plating layer 36c Third surface plating layer 36d Fourth surface plating layer 33 Direct plating layer 33a First direct plating layer 33b Second direct plating layer 40 Recesses D1 to D4 Flatness x Stacking direction y First direction z Second direction L Dimension of multilayer ceramic capacitor in the first direction W Dimension of multilayer ceramic capacitor in the second direction T Dimension of multilayer ceramic capacitor in the stacking direction

Claims

1. A laminate having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in a first direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in a second direction perpendicular to the stacking direction and the first direction, A first external electrode disposed on the first end face and the first main surface, A second external electrode disposed on the second end face and the first main surface, A third external electrode disposed on the first end face and the first main surface, A fourth external electrode is disposed on the second end face and the first main face. Equipped with, At a position half the width of the laminate connecting the first side surface and the second side surface, The flatness D1 is defined as the maximum distance in the stacking direction x (perpendicular) between the intersection point of the first main surface and the first end surface or the second end surface and the surface of the first main surface. When the maximum distance in the stacking direction x (perpendicular) between the intersection point of the second main surface and the first end surface or the second end surface and the surface of the second main surface is defined as the flatness D2, The flatness D1 is greater than or equal to the flatness D2. Multilayer ceramic capacitor.

2. At a position half the length of the distance connecting the first end face and the second end face of the laminate, The flatness D3 is defined as the maximum distance in the stacking direction x (perpendicular) between the intersection point of the first main surface and the first side surface or the second side surface and the surface of the first main surface. When the maximum distance in the stacking direction x (perpendicular) between the intersection point of the second main surface and the first side surface or the second side surface and the surface of the first main surface is defined as the flatness D4, The multilayer ceramic capacitor according to claim 1, wherein the flatness D3 ≥ the flatness D4.

3. A laminate having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in a first direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in a second direction perpendicular to the stacking direction and the first direction, A first external electrode disposed on the first end face and the first main surface, A second external electrode disposed on the second end face and the first main surface, A third external electrode disposed on the first end face and the first main surface, A fourth external electrode is disposed on the second end face and the first main face. Equipped with, At a position half the width of the laminate connecting the first side surface and the second side surface, The flatness D1 is defined as the maximum distance in the stacking direction x (perpendicular) between the intersection point of the first main surface and the first end surface or the second end surface and the surface of the first main surface. When the maximum distance in the stacking direction x (perpendicular) between the intersection point of the second main surface and the first end surface or the second end surface and the surface of the second main surface is defined as the flatness D2, The flatness D2 is 4.2 μm or less. Multilayer ceramic capacitor.

4. At a position half the length of the distance connecting the first end face and the second end face of the laminate, The flatness D3 is defined as the maximum distance in the stacking direction x (perpendicular) between the intersection point of the first main surface and the first side surface or the second side surface and the surface of the first main surface. When the maximum distance in the stacking direction x (perpendicular) between the intersection point of the second main surface and the first side surface or the second side surface and the surface of the first main surface is defined as the flatness D4, The multilayer ceramic capacitor according to claim 3, wherein the flatness D4 is 4.2 μm or less.

5. The multilayer ceramic capacitor according to claims 1 to 4, wherein the first main surface is convex in shape.

6. The multilayer ceramic capacitor according to claim 1, wherein the flatness D2 is 4.2 μm or less.

7. The multilayer ceramic capacitor according to claim 2, wherein the flatness D4 is 4.2 μm or less.

8. The laminate comprises an inner layer, The aforementioned inner layer is A first internal electrode having one end exposed on the first end face and first side surface, and the other end exposed on the second end face and second side surface, A second internal electrode, one end of which is exposed to the first end face and the second side surface, and the other end of which is exposed to the second end face and the first side surface, Inner dielectric layer and Equipped with, At a location in the region that extends 5 μm inward from the first and second sides of the laminate in the direction connecting the first and second sides of the laminate, The multilayer ceramic capacitor according to claim 1 or claim 3, wherein the central portion of the second main surface has a recess that is recessed in the stacking direction.

9. The laminate comprises an inner layer, The aforementioned inner layer is A first internal electrode having one end exposed on the first end face and first side surface, and the other end exposed on the second end face and second side surface, A second internal electrode, one end of which is exposed to the first end face and the second side surface, and the other end of which is exposed to the second end face and the first side surface, Inner dielectric layer and Equipped with, At a location in the region that extends 5 μm inward from the first and second sides of the laminate in the direction connecting the first and second sides of the laminate, The multilayer ceramic capacitor according to claim 1 or claim 3, wherein the central portion of the first main surface has a recess that is recessed in the stacking direction.

10. The laminate comprises an inner layer, The aforementioned inner layer is A first internal electrode having one end exposed on the first end face and first side surface, and the other end exposed on the second end face and second side surface, A second internal electrode, one end of which is exposed to the first end face and the second side surface, and the other end of which is exposed to the second end face and the first side surface, Inner dielectric layer and Equipped with, At a location in the region that extends 5 μm inward from the first end face and the second end face of the laminate in the direction connecting the first end face and the second end face, The multilayer ceramic capacitor according to claim 1 or claim 3, wherein the central portion of the second main surface has a recess that is recessed in the stacking direction.

11. The laminate comprises an inner layer, The aforementioned inner layer is A first internal electrode having one end exposed on the first end face and first side surface, and the other end exposed on the second end face and second side surface, A second internal electrode, one end of which is exposed to the first end face and the second side surface, and the other end of which is exposed to the second end face and the first side surface, Inner dielectric layer and Equipped with, At a location in the region that extends 5 μm inward from the first end face and the second end face of the laminate in the direction connecting the first end face and the second end face, The multilayer ceramic capacitor according to claim 1 or claim 3, wherein the central portion of the first main surface has a recess that is recessed in the stacking direction.

12. In a view from the second main surface in the stacking direction, the central portions of the first side surface and the second side surface have recesses, as described in claim 1 or claim 3.

13. In a view from the first main surface in the stacking direction, the central portions of the first side surface and the second side surface have recesses, as described in claim 1 or claim 3.

14. In a view from the second main surface in the stacking direction, the central portions of the first end face and the second end face have recesses, as described in claim 1 or claim 3.

15. In a view from the first main surface in the stacking direction, the central portions of the first end face and the second end face have recesses, as described in claim 1 or claim 3.