Design support system and control device

Abstract

The design support system comprises a design unit that designs wafer processes and packaging processes, a wafer process unit that manages wafer processes, a packaging unit that manages packaging processes for wafers manufactured by the wafer process unit, and a control unit that acquires wafer process information measured in the wafer process from the wafer process unit, acquires packaging process information measured in the packaging process from the packaging unit, and provides design support information obtained based on the wafer process information and packaging process information to the design unit.

Description

Technology Field

[0001] The present invention relates to a design support system and a control device. Background Technology

[0002] Conventionally, general-purpose semiconductors capable of being installed in various products are being mass-produced. Examples of general-purpose semiconductors include CPUs (Central Processing Units) installed in personal computers. General-purpose semiconductors based on the conventional Von Neumann architecture are designed to have high sequential processing performance.

[0003] According to Moore's Law, it was believed that production costs could be lowered by increasing the integration density of semiconductors, and traditionally, the primary goal was to reduce production costs by increasing the production volume of general-purpose semiconductors. However, increasing the production volume of semiconductors requires massive investment in facilities. For this reason, the fabless production method, in which a business operator primarily responsible for semiconductor design entrusts semiconductor production to an external business operator, became the mainstream.

[0004] Patent Document 1 discloses a technique for pattern optimization based on lithography. Prior art literature

[0005] U.S. Patent No. 11449659 Specification The problem to be solved

[0006] With the recent advancement of Artificial Intelligence (AI) technology, semiconductors are being used for AI processing. Since AI processing involves parallel processing, using general-purpose semiconductors is not suitable. Consequently, there has been a demand for the manufacture of dedicated semiconductors optimized for each specific AI application. However, dedicated semiconductors are designed for use only in specific products and cannot operate when installed in products other than those designated. For this reason, mass-producing dedicated semiconductors is not realistic, and even if it were possible, there was a problem of incurring enormous costs.

[0007] With the advancement of semiconductor miniaturization, the time required for design is becoming prolonged due to the increasing complexity of semiconductor design rules and constraints, as well as the Turn Around Time (TAT) for semiconductor manufacturing. Consequently, when a design problem is identified during semiconductor development, modifications to the design and manufacturing (prototyping) require vast amounts of time and cost. Therefore, a method to minimize semiconductor design modifications was required.

[0008] In the current semiconductor manufacturing method, the business operator performing semiconductor design and the business operator performing semiconductor manufacturing exist separately. For this reason, optimal manufacturing conditions or causes of failure, which can only be known by the business operator performing semiconductor manufacturing manufacturing based on design information from the business operator performing semiconductor design, were not shared with the business operator performing semiconductor design. Furthermore, even if optimal manufacturing conditions and causes of failure were shared between the business operators, the business operator performing semiconductor design did not know how to perform the optimal design of the semiconductor and merely repeated trial and error, thus requiring time for design. Moreover, even if the technology disclosed in Patent Document 1 was used, the requirement for design remained unchanged.

[0009] The present invention was made in consideration of such circumstances and aims to significantly reduce the time required from semiconductor design to production. means of solving the problem

[0010] A design support system according to the present invention comprises a design unit that designs a wafer process for manufacturing a wafer and a packaging process for manufacturing a package from a wafer, a wafer process unit that manages the wafer process, a package unit that manages the packaging process for a wafer manufactured by the wafer process unit, and a general device that acquires wafer process information measured in the wafer process from the wafer process unit, acquires packaging process information measured in the packaging process from the package unit, and provides design support information obtained based on the wafer process information and the packaging process information to the design unit. Effects of the invention

[0011] According to the present invention, by providing design support information based on information obtained by manufacturing a semiconductor, the time required from the design to the production of a semiconductor can be significantly reduced.

[0012] Problems, configurations, and effects other than those mentioned above will become apparent from the description of the following embodiments. Brief explanation of the drawing

[0013] FIG. 1 is an overall configuration diagram illustrating an example of a semiconductor manufacturing process according to one embodiment of the present invention. FIG. 2 is a drawing illustrating an example of a post-process in a packaging process according to one embodiment of the present invention. FIG. 3 is a block diagram showing an overall configuration example of a design support system according to one embodiment of the present invention. FIG. 4 is a block diagram illustrating an example of the internal configuration of a control device according to one embodiment of the present invention. FIG. 5 is a flowchart illustrating an example of an AI-assisted design solution provided by a design department according to one embodiment of the present invention. FIG. 6 is a diagram illustrating the difference in data obtained from batch type and single-wafer type according to one embodiment of the present invention through experiment. FIG. 7 is a drawing illustrating the contents of data obtained from a batch type and a single-wafer type according to one embodiment of the present invention. FIG. 8 is a diagram illustrating the difference between the turnaround time in a conventional manufacturing method and the turnaround time in a manufacturing method according to the present embodiment. FIG. 9 is a drawing illustrating a method of manufacturing using a proprietary leaf device according to one embodiment of the present invention. FIG. 10 is a drawing illustrating an example of the operation of a guidance and management unit regarding an embodiment of the present invention. FIG. 11 is a drawing illustrating an example of a heterogeneous integrated (hetero) design by chiplets according to one embodiment of the present invention. FIG. 12 is a drawing illustrating examples of three processes that can shorten the turnaround time of packaging according to one embodiment of the present invention. FIG. 13 is a drawing illustrating an example of a change in turnaround time in a packaging process according to one embodiment of the present invention. Specific details for implementing the invention

[0014] Hereinafter, embodiments for carrying out the present invention will be described with reference to the accompanying drawings. In this specification and drawings, components having substantially the same function or configuration are given the same reference numerals to omit redundant descriptions.

[0015] [One implementation form]

[0016] An example of a semiconductor manufacturing process

[0017] FIG. 1 is an overall configuration diagram illustrating an example of a semiconductor manufacturing process according to one embodiment.

[0018] The semiconductor manufacturing process is broadly divided into a design process, a wafer process for manufacturing wafers, and a packaging process for manufacturing packages from wafers. In the present embodiment, the manufacturing technology for design is referred to as MFD (Manufacturing for Design) and is distinguished from DFM (Design for Manufacturing), which is a conventional design technology for manufacturing. MFD is a methodology that supports design based on data obtained from the wafer process and the packaging process.

[0019] In the design support system (10) according to the present embodiment (refer to FIG. 3 described below), by repeating MFD and DFM, Design-Manufacturing Co-Optimization (DMCO), which represents the coordination and optimization of semiconductor design and manufacturing, becomes possible. As a result, the design support system (10) according to the present embodiment aims to reduce the total cycle time from semiconductor design to packaging by half.

[0020] In the design process, semiconductors and circuit layouts are designed. In this embodiment, a new design methodology supported by an AI (Artificial Intelligence) model is provided to a customer of the applicant. For example, by having the AI ​​model learn silicon big data measured by various measuring devices in the wafer process and packaging process, each AI model illustrated in FIG. 4 described below is trained, thereby improving the performance of the PDK (Process Design Kit). Furthermore, in this embodiment, the trained AI model is used in the design process, thereby assisting the design by the customer designer, and thus the automation of semiconductor design is advanced.

[0021] The PDK contains information on technologies necessary for semiconductor design, such as which device models exist, which design rules should be used for design, and which regulatory components to extract. The designer imports this information into the PDK tool to design the semiconductor. The MFD, which an AI model learns from the silicon big data shown in Fig. 1, and the MFD that assists in design by having the AI ​​model navigate the designer, are organized in a hierarchical structure.

[0022] (General wafer processing and packaging processes)

[0023] Wafer processing and packaging processes are divided into front-end and back-end processes. The front-end process includes the Front End of Line (FEOL), where device formation takes place, the Back End of Line (BEOL), where wiring formation takes place, and wafer characteristic testing.

[0024] FEOL includes, for example, a cleaning process, a film deposition process, a photolithography process, an etching process, an ion implantation process, and a wafer inspection process, and these processes are repeated. BEOL includes, for example, a cleaning process, a film deposition process, a photolithography process, an etching process, a planarization process, and a wafer inspection process for a wafer manufactured through FEOL, and these processes are repeated.

[0025] In the wafer characteristic inspection during the wafer inspection process, the electrical characteristics of the wafer are inspected for the wafer manufactured through BEOL. When the wafer characteristic inspection is completed, the wafer is finished.

[0026] The back-end process includes assembly and inspection processes. The assembly process includes dicing, die bonding, wire bonding, and molding processes for wafers determined to be good as a result of wafer characteristic inspection. The inspection process includes a final inspection process for the semiconductor produced by the molding process. The back-end process, consisting of such assembly and inspection processes, is performed for simple packaging processes using wire bonding of a single chip or complex packaging processes involving stacking multiple chips. When the final inspection process is completed, the packaged semiconductor (also referred to as a chip) is finished.

[0027] (Wafer process and packaging process according to the present embodiment)

[0028] Generally, in wafer processing, there are batch processing methods where the processes of wafers within a lot are identical, and single-wafer processing methods where wafers within a lot are processed one by one and the processes of each wafer can be changed; typically, both are mixed. In the wafer process according to the present embodiment, all processes are processed in a single-wafer manner. By doing so, the time required to complete a lot can be reduced to less than the usual completion time. Furthermore, by starting with changing the conditions of each wafer individually, a larger amount of data is accumulated within the same time compared to a process including batch processing, and silicon big data is formed. Silicon big data contributes to improving wafer yield in the wafer process. Additionally, silicon big data is used for training an AI model in the design process (design AI model (72) of FIG. 4 described later) (MFD). Furthermore, in the wafer process, the processing time (x) for one wafer can be reduced to less than half of the conventional time by using the single-wafer method.

[0029] Currently, chiplet technology is advancing, and the packaging process involves mounting multi-chips, formed by highly multiple bonding of wafers to wafers, wafers to chips, and chips to chips, onto a substrate; the combinations are becoming very diverse and complex.

[0030] The back-end process described below is conceptually a process in which the wafer completed in the front-end process is converted into a chip, mounted onto a substrate (such as a silicon substrate) with separate rewiring, and then mounted onto a final packaging substrate. Since a substrate with separate rewiring is mounted on the packaging substrate, multiple chips with various functions are integrated and connected. Consequently, even if all functions are not integrated onto a single chip, equivalent functionality can be realized through a product on a packaging substrate that integrates multiple chips with various functions.

[0031] Figure 2 is a diagram illustrating an example of a post-process in a packaging process corresponding to multi-chip integration.

[0032] For example, a bump formation process and a dicing process are performed on the wafer manufactured in the aforementioned preceding process. Additionally, a Through-Silicon Via (TSV) process, a redistribution layer formation process, and a bump formation process are performed on the substrate for redistribution. After that, a chip mounting process is performed in which the chip reorganized by the dicing process and the redistribution substrate are combined, and after the sealing process and the bump formation process are performed, a substrate mounting process is performed on the packaging substrate. Additionally, after the sealing process is performed, a final inspection process is performed.

[0033] In the design process, heterogeneous design using chiplet technology becomes possible based on design support information received from a chiplet technology platform containing multiple IPs. In the semiconductor field, functional blocks constituting LSIs (Large Scale Integration), such as CPUs, image processing circuits, and memory, are recognized as design assets and are referred to as IP (Intellectual Property) cores or simply IPs. In this specification, IPs are described as circuit elements in semiconductor design. Various circuit elements are envisioned, such as simple standard cells, interface functional blocks, or CPU cores. Details regarding chiplets will be described from Fig. 11 onwards.

[0034] <Example of Design Support System Configuration>

[0035] FIG. 3 is a block diagram illustrating an overall configuration example of a design support system (10) according to the present embodiment. The design support system (10) comprises a general device (1), a design unit (2), a wafer processing unit (3), and a package unit (4).

[0036] The control device (1) provides a platform that is accessible from the design unit (2), the wafer process unit (3), and the package unit (4). Accordingly, the control device (1) obtains wafer process information measured in the wafer manufacturing process from the wafer process unit (3), obtains packaging process information measured in the packaging process from the package unit (4), and provides design support information obtained based on the wafer process information and packaging process information to the design unit (2).

[0037] The control device (1) uses wafer process information as silicon big data and packaging process information as packaging big data, and performs analysis by the design AI model (72) illustrated in FIG. 4, which will be described later, to create design support information. In the analysis by the design AI model (72), correlations of various types of parameters based on silicon big data and packaging big data are obtained. The design AI model (72) provides design support information, including combinations and values ​​of optimal parameters, to the design unit (2).

[0038] The design unit (2) designs the wafer process and the wafer packaging process. Since the optimal design of the semiconductor is made possible by the design support information provided from the control device (1) and the design assistance function of the AI ​​model, the design unit (2) can increase the convergence speed of the design. Additionally, the design unit (2) may introduce information in which a designer has designed the semiconductor using the design assistance function of the AI ​​model, or it may introduce information in which the AI ​​model has designed the semiconductor itself.

[0039] The wafer process unit (3) has the function of managing the wafer process and manufactures a wafer based on design information designed by the design unit (2). The wafer process unit (3) transmits data measured by various measuring devices in the wafer process to the general device (1) as wafer process information.

[0040] The package unit (4) has the function of managing a packaging process for a wafer manufactured by the wafer process unit (3). The package unit (4) performs a packaging process for a wafer manufactured by the wafer process unit (3), based on placement information designed by the design unit (2), by placing various chips on a substrate and wiring multiple chips together. In addition, the package unit (4) transmits data measured by various measuring devices during the packaging process to the control unit (1) as packaging process information.

[0041] FIG. 4 is a block diagram illustrating an example of the internal configuration of a control device (1) according to the present embodiment. The control device (1) operates as a platform that provides the functions of each part of the design unit (2). The control device (1) is equipped with a wafer process information collection unit (50), a packaging process information collection unit (60), a design process learning unit (70), and a classification unit (75). Conventionally, correlation data was acquired from data obtained from the wafer process based on the knowledge of an engineer. In contrast, the present system makes it possible for a design AI model (72) to extract new correlation data with high precision from a large amount of data that an engineer cannot process.

[0042] The wafer process information collection unit (50) accumulates wafer process information acquired for each wafer manufactured in the wafer process and outputs the wafer process information to the design process learning unit (70). The wafer process information collection unit (50) is equipped with a data acquisition unit (51), a feedback unit (52), and a wafer process DB (Data Base) (55).

[0043] The data acquisition unit (51) acquires multiple data as wafer process information for each wafer in the wafer process. The data acquired by the data acquisition unit (51) is accumulated in the wafer process DB (55).

[0044] The feedback unit (52) outputs data (wafer process information) read from the wafer process DB (55) to the design process learning unit (70).

[0045] The packaging process information collection unit (60) accumulates packaging process information acquired whenever a chip cut from a wafer manufactured in the packaging process is packaged, and outputs the packaging process information to the design process learning unit (70). The packaging process information collection unit (60) is equipped with a data acquisition unit (61), a feedback unit (62), and a packaging process DB (65).

[0046] The data acquisition unit (61) acquires multiple data measured for each package product in the packaging process as packaging process information. The data acquired by the data acquisition unit (61) is accumulated in the packaging process DB (65).

[0047] The feedback unit (62) outputs data (packaging process information) read from the packaging process DB (65) to the design process learning unit (70).

[0048] The design process learning unit (70) has a design AI model (72) that obtains first design support information to support the design of a wafer process based on wafer process information, and obtains second design support information to support the design of a packaging process based on packaging process information. The design process learning unit (70) has a design DB (71) and a design learning unit (73).

[0049] The design DB (71) accumulates wafer process information provided by the wafer process information collection unit (50) and accumulates packaging process information provided by the packaging process information collection unit (60).

[0050] Additionally, the design DB (71) stores the design AI model (72) used in the design process. The design AI model (72) has the function of supporting various designs in the design process. For this reason, the design AI model (72) provides the functions of a generation unit (21), an optimization unit (22), and a guidance and management unit (23) to the design unit (2).

[0051] As machine learning in the design AI model (72), depending on the DMCO application, any one of untrained, trained, or reinforcement learning is used. For example, in the optimization unit (22) and guidance and management unit (23) described later, reinforcement learning is likely to be used because it is a reward-type machine learning that determines which wiring or design policy is more desirable.

[0052] For example, when the optimization unit (22) obtains a correlation between manufacturing data and electrical characteristics, teacher-assisted learning is used in which the electrical characteristics are the correct answer of the output result. In processing such as when the optimization unit (22) automatically classifies defect data, teacher-assisted learning is used.

[0053] Machine learning in the design AI model (72) is not limited to these machine learnings.

[0054] The design learning unit (73) updates the design AI model (72) by performing machine learning, etc., based on wafer process information and packaging process information accumulated in the design DB (25). The updated design AI model (72) is stored in the design DB (71).

[0055] The division unit (75) sets the division range of processes for a customer designer and a person who manufactures wafers based on the design (e.g., the manufacturer who is the applicant). The division unit (75) can arbitrarily set the division range of processes for the designer and the applicant and divide them. In this embodiment, a plurality of processes included in the design process are divided, and the design unit (2) assists the design by the customer designer according to the division range. The division range is illustrated in FIG. 5, which will be described later.

[0056] The design unit (2) has a generation unit (21) (Generator), an optimization unit (22) (Optimizer), and a guidance and management unit (23) (Navigator / Manager) as functions provided by the design AI model (72).

[0057] The generation unit (21) has the function of generating code required for the design based on specifications described in natural language.

[0058] The optimization unit (22) performs a process to find the optimal solution for a combination of design parameters under various predetermined constraints. For example, the optimization unit (22) searches for the optimal solution for a combination by reducing the leakage current while maintaining the clock frequency, and when the optimal solution is obtained, outputs the information to the guidance and management unit (23).

[0059] The guidance and management unit (23) guides the designer in design and manages the design by the designer by providing at least one of the first design support information and the second design support information based on the combinatorial optimal solution. For example, the guidance and management unit (23) has a function to navigate the designer to accelerate the convergence of the current design's PPA (performance power area) based on past design experience. The PPA is described in Fig. 7, which will be described later.

[0060] Among the guidance and management unit (23), the guidance unit is a function related to the entire design flow. In order to proceed with the various processes included in the design process, it guides the designer to avoid repetitive processes based on past experience. Among the guidance and management unit (23), the management unit is a function that plans and manages the design itself. For example, when designing a chip of a certain specification, the guidance and management unit (23) plans to determine how the System on Chip (SoC) can be divided into blocks to proceed with the design without bottlenecks.

[0061] FIG. 5 is a flowchart illustrating an example of an AI-assisted design solution. The AI-assisted design solution is provided to a customer by a design AI model (72) operating in the design unit (2).

[0062] In semiconductor design, the semiconductor's requirements specification is formulated first. Subsequently, a development plan is established, and system-level design is carried out. After the system-level design is completed, front-end design (F / E Design) and back-end design (B / E Design) are performed.

[0063] Front-end design encompasses everything from algorithm design to logic verification. In front-end design, after the algorithm is designed by the designer, it is rewritten, for example, in the C language as a program. Subsequently, High-Level Synthesis is performed, which automatically generates a hardware description language using the operational description in C as input. Additionally, after the system-level is designed by the designer, Register Transfer Level (RTL) design is carried out to realize logic circuits and the like using the hardware description language. After RTL design or High-Level Synthesis, Function Verification is performed, and after Logic Synthesis, Verification is executed. After Logic Verification, the process returns to System-Level Design or proceeds to the next stage of Back-end Design.

[0064] In backend design, design planning is performed based on the results of logic verification in frontend design and the results of test circuit insertion. After designing the floor layout, the floor layout is designed. After the floor layout is designed, physical verification is performed, and lithography verification is performed.

[0065] Furthermore, after the layout wiring is performed, static timing analysis and power rail analysis are conducted. The power rail analysis includes signal integrity. Additionally, after the layout wiring is performed, power consumption analysis is conducted. Meanwhile, after the aforementioned test circuit insertion is performed, test pattern generation is carried out, and after the layout wiring is performed, gate simulation is executed. This concludes the details of each design included in the backend design.

[0066] Backend design includes physical verification including layout wiring, timing, and power analysis. After backend design, the wafer process and packaging process illustrated in Fig. 1 are performed. That is, after power supply analysis, a sample shipment produced by the wafer process and packaging process is performed, and the operation of the sample is verified. If the sample operation is satisfactory, a mass-production product produced by the wafer process and packaging process is shipped.

[0067] The AI-assisted design solution illustrated in FIG. 5 consists of three elements (generation unit (21), optimization unit (22), guidance and management unit (23)) provided to the design unit (2) by the design AI model (72) illustrated in FIG. 4.

[0068] The generation unit (21) includes, for example, system-level design, algorithm design, program description, and RTL design in front-end design, as shown in the area enclosed by the dashed line above in FIG. 5. By the generation unit (21), code, etc., by program is automatically generated.

[0069] The optimization unit (22) includes, for example, floor planning, layout wiring, physical verification, lithography verification, static timing analysis, power supply analysis, power consumption analysis, test circuit insertion, test pattern generation, and gate simulation in backend design, as shown in the area enclosed by the dashed line below FIG. 5. Optimal conditions for various processes are obtained by the optimization unit (22), and the designer is prompted to design based on the optimal conditions.

[0070] The guidance and management department (23) can optimize the hierarchical design that realizes the Turn Around Time (TAT) design for the present embodiment. TAT refers to the time taken from the start to the completion of a process. There are cases where the TAT is defined as the long period from the start of semiconductor design to the completion of manufacturing, or cases where the TAT is defined as the period from the start of design to the completion of design in the design process, as shown in the present embodiment.

[0071] As shown on the right side of FIG. 5 as (1) to (3) and as previously explained, the applicant and the customer may arbitrarily divide the scope of responsibility. The division of the scope of responsibility is determined by the customer's design capabilities and the customer's business model, and the division section (75) shown in FIG. 4 manages the divided scope of responsibility.

[0072] For example, in the classification shown in (1) of Fig. 5, a customer who intends to make the most of the applicant’s manufacturing technology takes charge of the entire design, including the development plan, front-end design, and back-end design, and the applicant manufactures and ships sample products or ships mass-produced products.

[0073] In the division shown in (2) of Fig. 5, the customer is responsible for everything from the development plan to the front-end design, and the applicant performs the back-end design and manufactures and ships the sample product or ships the mass-produced product. The customer in this case is a customer who wants to entrust the applicant with the design corresponding to the manufacturing technology, that is, the back-end design which is a heavy burden.

[0074] In the classification shown in (3) of Fig. 5, a customer who has little design experience but wants to make a product using semiconductors is responsible for the system-level design, and the applicant is responsible for all subsequent processes.

[0075] Conventionally, various vendors provide various design tools for each block shown in Fig. 5. As the complexity of design rules and constraints accompanying recent miniaturization increases, design has become more sophisticated, making it increasingly difficult for designers to skillfully handle the design tools used to execute the design. Furthermore, in front-end design, there has been a tendency to design by packing circuits capable of realizing various functions into a single semiconductor so that the designer can obtain as many functions as possible.

[0076] Meanwhile, physical design is performed during backend design. For this reason, backend designers design how to wire the cells while fitting as many as possible into a small area of ​​the wafer. As a result, the time required for backend designers to design to realize the functions designed in the frontend was frequently increasing.

[0077] Meanwhile, the system-level design, algorithm design, and rewriting in C language as illustrated in FIG. 5 may be performed as an automatic generation process in which a design AI model (72) that interprets a specification written in natural language automatically generates machine language. Additionally, the design AI model (72) may automatically perform a process that encompasses each process in backend design, considers various constraints, finds the optimal combination of parameters, and optimizes.

[0078] Additionally, the design AI model (72) can determine the quality of a design by learning various designs or patterns that have been performed in the past. Because of this, the design AI model (72) has a support function that suggests, for example, a combination of optimal design tools to the designer so that the designer can make an optimal design.

[0079] According to the AI-assisted design solution illustrated in Fig. 5, the cycle time can be reduced by half compared to conventional design methods. In addition, in the AI-assisted design solution according to the present embodiment, the capabilities of a skilled designer can be replicated by a navigator. Because of this, even an unskilled designer can design semiconductors just like a skilled designer.

[0080] In conventional design methods, the number of modifications (ECO: Engineering Change Order) at the final stage of design increases, leading to prolonged design processes. On the other hand, by using the AI-assisted design solution according to the present embodiment, the number of modifications can be significantly reduced, thereby further shortening the TAT.

[0081] Differences in data obtained from batch and single-wafer systems

[0082] Next, the difference between the conventional manufacturing process, the data obtained from the manufacturing process according to the present embodiment, and the results derived from the data will be explained with reference to FIGS. 6 and 7.

[0083] Figure 6 is a diagram illustrating the difference in data obtained from batch and single-wafer processes through experiment. The horizontal axis of Figure 6 represents the number of parameters obtainable during semiconductor production, and the vertical axis represents the experimental time. The parameters shown on the horizontal axis are values ​​obtained by varying certain process conditions (e.g., temperature, pressure, flow rate, plasma power, etc.) (e.g., if temperature, 850°C, 900°C, 950°C, etc.). The experimental time on the vertical axis is the time required to obtain a semiconductor manufactured under certain process conditions.

[0084] In the batch process, the same processing is performed on a large number of wafers in a batch. The black dots shown in FIG. 6 represent data acquired for each processing iteration. As indicated as "Batch" in FIG. 6, a linear graph is formed by connecting four black dots.

[0085] Meanwhile, in the single-wafer type (labeled "single" in Fig. 6), the data obtained from the manufacturing process for each wafer is represented as a number of white dots.

[0086] In addition, from Fig. 6, it can be seen that there is a difference between the data obtained from the single-wafer method and the data obtained from the batch method. That is, in the batch method of Fig. 6, since the processing time is long, there are only, for example, four data points (black spots) obtained in the same experimental time as in the single-wafer method, and as the data are arranged almost linearly, the graph shows a linear change. On the other hand, in the single-wafer method (single), since multiple data can be obtained in the same experimental time, the graph shows a non-linear change.

[0087] Figure 7 is a diagram illustrating the contents of data obtained from batch type and single-wafer type.

[0088] The explanatory diagram (1) at the top of FIG. 7 shows a graph of PPA. The graph of PPA represents the density distribution function of a certain characteristic parameter. The horizontal axis of the graph represents the characteristic variation. For example, the threshold voltage of a transistor has a characteristic variation due to manufacturing variation. If the characteristic variation is high, the response becomes slow, and if the characteristic variation is low, the response becomes fast.

[0089] PPA is designed using various parameters of PDK. PPA is expressed as a function with multiple types of σ as variables, as shown in the following equation (1).

[0090] PPA=f(…, σ, …) … (1)

[0091] Here, σ represents the deviation of the most important design parameter. Design parameters are parameters set by the designer during the design of the semiconductor. For example, σ is formed by values ​​directly related to physical product manufacturing, such as the positional alignment precision of the device, the gas flow rate, and the temperature of the furnace body. Ultimately, the chip's PPA becomes a function of the manufacturing parameter. Manufacturing parameters are parameters set in the manufacturing device during the manufacturing of the semiconductor. This σ is expressed as a function with multiple manufacturing parameters m as variables, as shown in the following equation (2).

[0092] σ=g(m1, m2, …) … (2)

[0093] Typically, designers perform various designs based on data called σ, which includes manufacturing parameters m1, m2, … so they do not need to worry about physical information. In addition, since the complex process of semiconductor manufacturing is expressed by σ, designers do not need to know how semiconductor manufacturing is performed.

[0094] In the lower part of Fig. 7, the graph shown in Fig. 6 is displayed. Graph (2) of Fig. 7 represents data obtained from a batch type, and graph (3) of Fig. 7 represents data obtained from a single, i.e., a single-wafer type.

[0095] As mentioned above, σ is a value determined by the correlation of manufacturing parameters. The designer desires that the deviation of the design parameters be minimized, and the sooner the deviation is reduced, the better. Although a smaller value for σ is preferable, in the data obtained from the batch formula, a small number of m, represented as black dots in Fig. 7 i A linear graph is drawn based on the correlation of the parameters. For this reason, even if the designer fits the smallest σ, it is unclear whether this σ is a local minimum. Furthermore, if the local minimum of σ fluctuates to the left or right, the amount of change in σ increases, making semiconductor manufacturing unstable.

[0096] Meanwhile, in the single-wafer type, a plurality of m, represented by white dots in Fig. 7 i A non-linear graph is drawn based on the correlation of the parameters. In this graph, the minimum value of σ becomes clear, so the optimal solution can be easily found. For this reason, the optimization unit (22) shown in FIG. 4 obtains the minimum value of a function with multiple manufacturing parameters as variables as the optimal solution for each wafer process information and packaging process information, and the guidance and management unit (23) can guide the optimal solution to the designer.

[0097] Additionally, the location indicated as an error in the graph (3) is the value determined to be a minimum of σ in the graph (2) representing the data obtained from the batch formula. In reality, it is not a minimum of σ, and the slope of the graph is large. Because of this, a small number of m i The change in σ is likely to increase due to fluctuations. Meanwhile, the location shown as the optimal solution in the graph (3) has a small slope, so if this location is a minimum value of σ, then m i Even if changes, σ becomes difficult to change.

[0098] As mentioned above, if a designer fits at the wrong location without noticing the optimal value of σ, the quality of the manufactured semiconductor will fluctuate, resulting in the production of a large number of semiconductors that fail inspection in subsequent processes. Since it is important in semiconductor design to be able to find the minimum value of σ as quickly as possible in advance, the advantage of finding the minimum value of σ by adopting a single-wafer method is much greater than that of adopting a batch method.

[0099] In addition, the designer can accelerate the verification of the PDK by combining silicon big data and a TCAD (Technology CAD) model. For example, initially, the designer uses TCAD to predict the correlation between manufacturing parameters and design parameters. Subsequently, through an MFD in which silicon big data obtained from the all-wafer process is analyzed by a design AI model (72), the designer can verify the correlation between manufacturing parameters and design parameters using silicon big data.

[0100] FIG. 8 is a diagram illustrating the difference between TAT in a conventional manufacturing method and TAT in a manufacturing method according to the present embodiment.

[0101] In the conventional manufacturing method illustrated in the upper part of Fig. 8, the backend line (BEOL) is executed after the frontend line (FEOL) is executed, and the semiconductor manufacturing is completed. In this way, the time from the start to the completion of semiconductor manufacturing is referred to as the conventional TAT.

[0102] In the manufacturing method according to the present embodiment illustrated in the lower part of FIG. 8, the front-end line and the back-end line are started simultaneously, and the semiconductor is manufactured in parallel. That is, after the front-end line and the back-end line are completed together, the wafer produced in the front-end line and the wafer produced in the back-end line are bonded together, and the manufacturing of the semiconductor is completed.

[0103] A method of bonding wafers together in this manner is called wafer bonding. As such, the manufacturing method according to the present embodiment can significantly shorten the TAT compared to conventional methods. Shortening the TAT in the manufacturing method according to the present embodiment is referred to as "shortening the TAT."

[0104] FIG. 9 is a drawing illustrating a method using a proprietary wafer device (not shown) according to the present embodiment. The proprietary wafer device is a device used in wafer processing and packaging processes.

[0105] In the lower left corner of FIG. 9, a graph is shown showing the difference in data obtained from the batch method and the single-wafer method illustrated in FIG. 6. In the single-wafer device according to the present embodiment, consistent production is performed for each wafer. In this consistent production, the amount of silicon data acquired from the single-wafer device is, for example, nearly 100 times the amount of conventional data. For this reason, the silicon data acquired from the single-wafer device is called silicon big data.

[0106] Silicon big data is data acquired by advanced measurement devices and sensors mounted on each device. After useful data is extracted from the silicon big data, it is analyzed by a design AI model (72).

[0107] In addition, packaging big data is data acquired by advanced measurement devices and sensors installed in each device of the packaging process.

[0108] The design AI model (72) evaluates high-precision correlations and characteristics by combining various types of data included in silicon big data, thereby enabling high-precision correlations and characterizations.

[0109] In this embodiment, a series of processes in which data is transferred from a manufacturing area to a design area, and trends, optimal values, etc. obtained from data acquired in the manufacturing area are utilized in the design area, is referred to as MFD.

[0110] Silicon big data includes, for example, Test Element Group (TEG) data, sample data, and Mass Production (MP) data. TEG data, sample data, and MP data each include design data, test data of electrical characteristics, and manufacturing data (measurement, film thickness, defect information, etc.).

[0111] TEG data refers to data obtained using a foundry process verification mask that includes a TEG. TEG data is data derived from device and process technologies, such as SPICE models and design rules. TEG data is used in device and process technologies within the design domain.

[0112] Sample data is data obtained using a mask for operation verification based on the customer's design. Sample data is data obtained from the design environment, such as PDK and standard cell data.

[0113] MP data is data obtained using a mask for mass-produced products. In the design process, MP data is used for high-speed design convergence.

[0114] SPICE models and design rules in device and process technology, PDKs and standard cells in the design environment, and high-level design convergence in the design process are related to each other and influence each other.

[0115] On the right side of Fig. 9, a comparison example of a PDK without MFD and a PDK with MFD is shown. The PDK without MFD is intended for designing using conventional silicon data, and a processing window as a PDK without MFD is shown.

[0116] In contrast to conventional silicon data, where the processing window size is small and data could not be interpreted with high precision, the PDK with MFD allows for the acquisition of abundant silicon data (silicon big data), thereby increasing the processing window size. Consequently, the accuracy of data interpretation is improved in the PDK according to the present embodiment.

[0117] Furthermore, regarding the deviation (margin) considered in the design, in a PDK without MFD, the deviation is small and the design is limited, so redesigns occur multiple times and design convergence slows down. On the other hand, in the PDK with MFD according to the present embodiment, the deviation is large, improving the degree of freedom in the design. Therefore, in a PDK with MFD, redesigns are eliminated, and design convergence becomes very fast.

[0118] FIG. 10 is a diagram illustrating an example of operation of the guidance and management unit (23) described in FIG. 5. Here, an example of operation of the guidance and management unit (23) in the chip design process is described. The guidance and management unit (23) detects a design block that becomes a bottleneck from a plurality of design blocks that divide the entire design. Then, the guidance and management unit (23) changes the design block that becomes a bottleneck to equalize the time required to complete a plurality of design blocks designed in parallel, and guides the designer to the changed plurality of design blocks. An example of operation of the guidance and management unit (23) is described with reference to operations (1) to (4) illustrated in FIG. 10.

[0119] In operation (1), the guidance and management unit (23) performs the division of the optimal design for high-speed design convergence. For example, the guidance and management unit (23) divides the whole design into a plurality of individual design blocks HLB1 to HLBn.

[0120] In operation (2), the guidance and management unit (23) detects a bottleneck early on for each divided design block and finds a solution to resolve the bottleneck. For example, as shown by the dotted circle in FIG. 10, the guidance and management unit (23) detects design block HLB3 as a bottleneck. In this case, the guidance and management unit (23) redesigns the design block so that the bottleneck can be resolved. At this time, changes to the shape of each design block and updates to the netlist are performed.

[0121] In operation (3), the guidance and management unit (23) applies a design change. At this time, the guidance and management unit (23) establishes a best plan for the design change. For example, the guidance and management unit (23) changes the size and shape of the design block. In addition, the guidance and management unit (23) performs an ECO modification on the design block HLB2 that does not significantly affect the manufacturing schedule.

[0122] In addition, the guidance and management unit (23) performs re-PnR (Place and Route) of the design block HLB4. As a result, the manufacturing time of block HLB3, which was detected as a bottleneck, is shortened, and the manufacturing time of each of the design blocks HLB1 to HLBn is not affected by the bottleneck, so the design time for the entire design blocks HLB1 to HLBn is shortened.

[0123] In operation (4), the guidance and management unit (23) verifies the full chip. A full chip refers to a combination of design blocks HLB1 to HLBn in which the bottleneck has been resolved in operation (3). If the verification result in operation (4) is satisfactory, the design information is tape-out and shared with the upstream and downstream processes.

[0124] FIG. 11 is a drawing illustrating an example of a heterogeneous integrated (hetero) design using chiplets. FIG. 11 illustrates a chiplet library (80) and an example of a chiplet configuration. The chiplet library (80) is built, for example, in the design DB (71) illustrated in FIG. 4. Accordingly, the design process learning unit (70) has a chiplet library (80) that accumulates information about chiplets. In the packaging process according to the present embodiment, a chiplet platform consisting of a plurality of circuit elements (IPs) is used.

[0125] On the left side of FIG. 11, an IP group including specialized IPs and AI accelerators that bring about the characteristics of a customer's product is illustrated. The IPs selected by the customer for their own design are called domain-specialized IP groups (81). Individual IPs included in the domain-specialized IP groups (81) are shown in FIG. 11 as "IP Core1", "IP Core2", etc.

[0126] IPs included in the domain-specific IP group (81) do not function as products on their own, so a CPU for a control controller, a memory interface, etc. are required. Since the CPU for a control controller, the memory interface, etc. are generally shared general-purpose IPs, they are called a platform IP group (Platform IPs) (82). The platform IP group (82) is used as the basis for chiplets.

[0127] The chiplet library (80) is a library in which existing chiplets that can be combined according to the customer's use are accumulated. Various IPs included in domain-specific IP groups (81), base IP groups (82), etc. are accumulated in the chiplet library (80). The customer can select any chiplet from the chiplet library (80).

[0128] A customer can design a unique chiplet, even if it is not stored in the chiplet library (80), and differentiate it from other companies' chiplets. By using a chiplet selected from the chiplet library (80), the customer can determine the configuration of a system-on-chip (SOC) with the customer's own specifications early on. Because of this, the customer can mount the custom chiplet they designed onto a semiconductor substrate.

[0129] For example, in the substrate (85) shown on the right side of FIG. 11, an example is shown in which a domain-specific IP (81a, 81b) obtained from the chiplet library (80) and a base IP (82a) are mounted. In addition, in the substrate (86), an example is shown in which a domain-specific IP (81b) obtained from the chiplet library (80), a domain-specific IP (81c) newly created by the customer, and a base IP (82a) are mounted. In this way, a common base IP (82a) is mounted on the substrates (85, 86), while existing chiplets are mounted in combination on the substrate (85). In addition, existing chiplets and new chiplets are mounted in combination on the substrate (86).

[0130] Information on chiplets mounted on substrates (85, 86) is stored in the chiplet library (80) and is fed back to the packaging design process (MFD) as indicated by the arrow below FIG. 11. Because of this, the design unit (2) can support the design of chiplets by providing the optimal combination of chiplets to the designer. For example, the guidance and management unit (23) guides the combination of base type circuit elements (base IP group (82)) and specialized type circuit elements (domain specialized IP group (81)) based on the combination information of chiplets accumulated in the chiplet library (80). Because of this, unlike in the past where it took time for the circuit elements to be determined by trial and error, in this embodiment, the combination of circuit elements guided by the guidance and management unit (23) is determined early.

[0131] Figure 12 is a diagram illustrating examples of three processes that can shorten the TAT of the packaging process.

[0132] In FIG. 12, the interposer is formed by performing wiring processing on an inorganic material such as silicon using semiconductor front-end process technology. Multiple chips are connected by mounting multiple chips on the interposer.

[0133] In the packaging process according to the present embodiment, technologies such as LDI (Laser Direct Imager) exposure (maskless exposure technology) illustrated in FIG. 12, chip size standardization, and parallel integration are used. As a maskless exposure technology, for example, there is a maskless direct imaging technology that directly images a circuit by irradiating a laser. In addition, as for chip size standardization and parallel integration, for example, proprietary 2D or 3D packaging technology is used.

[0134] Two-dimensional packaging technology is a technology for arranging multiple chips on a plane, and three-dimensional packaging technology is a technology for arranging multiple chips not only on a plane but also in the height direction.

[0135] In addition, various information obtained from the packaging process has useful information extracted and sent to the design process to be used for learning (MFD). The optimization unit (22) optimizes the maskless direct drawing of the interposer in the packaging process, the standardization of the chip size of the interposer, and the mounting of at least one chip on the interposer and the manufacturing of the package substrate. The guidance and management unit (23) provides design support by guiding the optimized information to the designer. Because of this, the designer can easily design a semiconductor based on the optimized information.

[0136] The explanatory diagram (1) of FIG. 12 illustrates an example of maskless exposure technology for forming a circuit pattern on a substrate. An example of conventional stepper exposure is shown on the left side of the explanatory diagram (1). In stepper exposure, a wiring pattern (92) is formed on the upper surface of an interposer (91) using a photomask (93). The wiring pattern (92) formed by the photomask (93) is identical at any location.

[0137] On the right side of the explanatory diagram (1), an example of LDI exposure according to the present embodiment is shown. LDI exposure is a maskless exposure technology in which a laser beam (95) is irradiated onto the upper surface of an interposer (91) to perform a direct drawing in which a wiring pattern is drawn. The laser beam (95) is irradiated onto the interposer (91) based on 3D CAD data designed by the design unit (2) (see FIG. 3). The laser beam (95) can change the wiring pattern (94) for each section of the interposer (91).

[0138] The explanatory diagram (2) of FIG. 12 illustrates an example of standardizing the chip size of the interposer (91). The chip size of the interposer (91) is standardized to, for example, a mm × b mm. In this embodiment, by standardizing the chip size, it is not necessary to create interposers (91) of various sizes, so the settings of the interposer (91)'s transport mechanism can be unified.

[0139] The explanatory diagram (3) of FIG. 12 illustrates an example of parallel integration of a packaging device. In the wafer manufacturing shown in the explanatory diagram (3), for example, three wafers are shown being manufactured. In the interposer manufacturing shown in the explanatory diagram (3), a defective location (96) where a defect occurred in a part of the wiring pattern formed on the interposer (91) is indicated by an × mark. In the conventional interposer manufacturing shown on the left side of the interposer manufacturing, the defective location (96) is left as is. On the other hand, in the interposer manufacturing according to the present embodiment, a plurality of chips judged to be good products in wafer manufacturing are mounted on a good location (97) that avoids the defective location (96).

[0140] In the package substrate manufacturing of the explanatory diagram (3), a package substrate (98) is manufactured. Typically, wiring processing is performed on a substrate made of organic material using semiconductor post-processing technology on the package substrate (98). At least one chip integrated in the interposer (91) is mounted on the package substrate (98) and packaged.

[0141] In the conventional package substrate manufacturing shown on the left side of the explanatory diagram (3) of FIG. 12, there is no correlation between the interposer manufactured in the interposer manufacturing and the defective parts. On the other hand, in the package substrate manufacturing according to the present embodiment, the good parts (97) in the interposer (91) manufactured in the interposer manufacturing are mounted as is on the package substrate (98).

[0142] Figure 13 is a diagram illustrating an example of a change in TAT in a packaging process.

[0143] An example of homogeneous integration is illustrated in the upper part of Fig. 13. In homogeneous integration, since all functions are integrated on a single silicon chip, the TAT is extended.

[0144] An example of heterogeneous integration is shown in the lower part of FIG. 13. In heterogeneous integration, chiplets with divided functions are manufactured in parallel, and the chiplets are integrated in an assembly step.

[0145] As illustrated in FIG. 13, for example, a CPU (x nm), memory (y nm), and I / O (z nm) are manufactured in parallel. The processing tailored to the CPU (x nm), which has the longest manufacturing time, is called the wafer MFG step. Additionally, for the interposer, manufacturing is initiated at the same timing as the manufacturing of each heterogeneous integrated component. The manufacturing process of the interposer is called the interposer MFG step. The (1) exposure processing described in FIG. 12 and (2) standardization of chip size performed in the interposer MFG step contribute to shortening the processing time of the interposer MFG step. The processing time of the interposer MFG step is shorter than the processing time of the wafer MFG step.

[0146] After the wafer MFG step, an integration step is performed. In the integration step, each chip is integrated in parallel on the interposer. As a result, in the packaging process, the parallel integration (3) described in FIG. 12 contributes to shortening the processing time of the integration step. Because of this, the TAT for heterogeneous integration is shortened compared to homogeneous integration.

[0147] In the design support system (10) according to the above-described embodiment, a general device (1) acquires wafer process information from a wafer process unit (3) and acquires packaging process information from a package unit (4). The design AI model (72) of the general device (1) analyzes the wafer process information and the packaging process information and provides information obtained from the optimal conditions of parameters in each process to the design unit (2) as design support information. The design unit (2) provides design support information suitable for designing a semiconductor to the designer and supports the design of each process in the manufacturing of the semiconductor. The designer can reduce the time spent on trial and error in the design process and shorten the time required for design.

[0148] The generation unit (21) of the design unit (2) illustrated in FIG. 4 has the function of generating code necessary for design from specifications described in natural language, so the designer can focus on describing specifications in natural language. For this reason, compared to the case where the designer interprets specifications and generates code themselves as in the conventional method, code that appropriately reflects the specifications is automatically obtained.

[0149] The optimization unit (22) of the design unit (2) optimizes each process included in the wafer process and packaging process based on design support information received from the general device (1). The design AI model (72) according to this embodiment obtains an optimal solution by calculating the correlation and trends of various manufacturing parameters based on the vast silicon big data obtained from the single-wafer process.

[0150] As the wafer process and packaging process designed by the design department (2) are optimized, unnecessary processing and redundant processing during the actual manufacturing of the semiconductor are eliminated. Because of this, the designer does not need to redesign the semiconductor and process, and can shorten the TAT until design completion.

[0151] In addition, the guidance and management unit (23) of the design unit (2) navigates the designer to accelerate the PPA convergence of the current design based on past design experience. Because of this, the designer can find an optimal solution in which the deviation of the design parameters is minimized, and can quickly design a semiconductor that becomes a good product.

[0152] In addition, in the chip design process illustrated in FIG. 10, divided design blocks that may become bottlenecks are detected at an early stage. Subsequently, the bottleneck is resolved by changing the shape of the design blocks. As a result, the manufacturing time of the divided design blocks is standardized, and the time required to manufacture a full chip is significantly reduced compared to the conventional manufacturing time.

[0153] In addition, the chiplet library (80) illustrated in FIG. 11 accumulates domain-specific IP groups (81) and base IP groups (82). A designer can select any chip from the chiplet library (80) and design by combining at least one chip on a substrate. Because of this, the design freedom of the chiplet can be increased.

[0154] In addition, as illustrated in FIGS. 12 and 13, in the packaging process, direct drawing of wiring patterns by irradiating the interposer with laser light, standardization of the chip size of the interposer, and parallel integration are performed. Therefore, in the packaging process, the TAT of heterogeneous integration according to the present embodiment can be shortened compared to the TAT of conventional homogeneous integration.

[0155] In addition, various manufacturing devices in the wafer processing unit (3) and the packaging unit (4) may be placed in a virtual space, and a simulation of the manufacturing devices in the virtual space may be performed based on the silicon big data described above. In this simulation, the general device (1) may acquire information obtained from the manufacturing devices in the virtual space that operate based on various information designed by the design AI model (72) of the general device (1), as well as information such as virtual wafers. By repeating the simulation, it becomes possible to identify locations where defects are predicted and to extract processes that become bottlenecks before actual wafer manufacturing, thereby further increasing the design precision of the design unit (2).

[0156] Furthermore, the present invention is not limited to the embodiments described above, and it is obvious that various other applications and modifications may be taken without departing from the essence of the invention as described in the claims.

[0157] For example, the above-described embodiments are detailed and specific descriptions of the system configuration to facilitate understanding of the present invention, and are not limited to having all the described configurations. Furthermore, it is possible to add, delete, or substitute other configurations for some of the configurations of the present embodiments.

[0158] Furthermore, control lines and information lines are indicated only as deemed necessary for illustrative purposes, and it cannot be said that all control or information lines are necessarily shown on the product. In reality, it can be assumed that almost all components are interconnected. Explanation of the symbols

[0159] 1: Control device 2: Design Department 3: Wafer Processing Unit 4: Package section 10: Design Support System 21: Generation section 22: Optimization Department 23: Information and Management Department 50: Wafer Process Information Collection Unit 60: Packaging Process Information Collection Department 71: Section 80: Chiplet Library 81: Domain-specific IP group 82: Base IP group 91: Interposer

Claims

Claim 1 A design support system comprising: a design unit for designing a wafer process for manufacturing a wafer and a packaging process for manufacturing a package from said wafer; a wafer process unit for managing said wafer process; a package unit for managing said packaging process for said wafer manufactured by said wafer process unit; and a general device for acquiring wafer process information measured in said wafer process from said wafer process unit, acquiring packaging process information measured in said packaging process from said package unit, and providing design support information obtained based on said wafer process information and said packaging process information to said design unit. Claim 2 In claim 1, the general device comprises a wafer process information collection unit that accumulates wafer process information acquired for each wafer manufactured in the wafer process, a packaging process information collection unit that accumulates packaging process information acquired whenever a chip cut from the wafer manufactured in the packaging process is packaged, and a design process learning unit having a design AI model that obtains first design support information to support the design of the wafer process based on the wafer process information output from the wafer process information collection unit, and obtains second design support information to support the design of the packaging process based on the packaging process information output from the packaging process information collection unit. Claim 3 In paragraph 2, the design AI model comprises a generation unit that generates code required for design based on specifications described in natural language, an optimization unit that finds an optimal solution for a combination of design parameters under predetermined constraints, and a guidance and management unit that guides the design and manages the design by providing at least one of the first design support information and the second design support information based on the optimal solution of the combination, and the design support system in which the function of the design AI model is provided to the design unit. Claim 4 In paragraph 3, the optimization unit obtains a minimum value of a function having a plurality of manufacturing parameters as variables for each of the wafer process information and the packaging process information as the optimal solution, and the guidance and management unit guides the optimal solution, a design support system. Claim 5 In paragraph 4, the guidance and management unit detects the design block that becomes a bottleneck among a plurality of design blocks that divide the entire design, changes the design block that becomes a bottleneck to equalize the time required to complete a plurality of design blocks designed in parallel, and guides the changed plurality of design blocks. Claim 6 In paragraph 4, the design process learning unit has a chiplet library that accumulates information on chiplets, and the guidance and management unit guides the combination of a basic type circuit element and a specialized type circuit element based on the combination information of the chiplets accumulated in the chiplet library, in a design support system. Claim 7 In claim 6, the optimization unit optimizes maskless direct drawing of the interposer in the packaging process, standardization of the chip size of the interposer, and the mounting of the chip on the interposer and the manufacturing of the package substrate, and the guidance and management unit guides the optimized information, a design support system. Claim 8 A general apparatus for acquiring wafer process information measured in a wafer process from a wafer process unit that manages a wafer process for manufacturing a wafer; acquiring packaging process information measured in a packaging process from a package unit that manages a packaging process for the wafer manufactured by the wafer process unit, as a packaging process for manufacturing a package from the wafer; and providing design support information obtained based on the wafer process information and the packaging process information to a design unit that designs the wafer process and the packaging process.

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