Uniform gap-filling deposition on semiconductor substrates having various geometric structures

Abstract

A gap-filling precursor may be provided to a processing chamber to fill features within a semiconductor structure. The features may have different critical dimensions. An etchant configured to etch the gap-filling material may also be provided along with the precursor. The plasma power within the chamber may have a duty cycle of a first RF power provided during a first time duration and a second RF power provided during a second time duration, wherein the second RF power is smaller than the first RF power. The RF power levels may be selected such that the gap-filling material is etched at the top of the features while being deposited within the bottom of the features during the first time, and is deposited on both the bottom and top of the features during the second time, wherein features having different CDs complete the gap-filling process almost simultaneously.

Description

Technology Field

[0001] This application claims the benefit and priority of U.S. Regular Application No. 18 / 534,061, filed on December 8, 2023, under the title "UNIFORM GAPFILL DEPOSITION ON SEMICONDUCTOR SUBSTRATES WITH VARYING GEOMETRIES," the contents of which are incorporated herein by reference in their entirety for all purposes.

[0002] The present disclosure generally describes plasma system fabrication processes. More specifically, the present disclosure describes methodologies for plasma system fabrication processes involving samples having a plurality of CDs. Background Technology

[0003] Integrated circuits are made possible by processes that create complexly patterned material layers on substrate surfaces. Creating patterned materials on a substrate requires controlled methods for forming and removing exposed materials. As device sizes continue to shrink, material formation can affect subsequent operations. For example, in gap filling operations, materials may be formed or deposited to fill trenches or other features formed on a semiconductor substrate. Some devices may include features or trenches of various dimensions, such as trenches with various widths. For such devices, it may be necessary to develop specialized methodologies or techniques to form uniformly deposited layers.

[0004] Therefore, there is a need for improved systems and methods that can be used to produce high-quality devices and structures. These and other needs are addressed by the present technology.

[0005] In some embodiments, the method may include the step of providing a precursor to a semiconductor processing chamber. The precursor may include a gapfill material for filling features within a semiconductor structure, and the features within the semiconductor structure may have different critical dimensions (CDs). The method may also include the step of providing an etchant together with the precursor to the semiconductor processing chamber, wherein the etchant may be configured to etch the gapfill material. The method may additionally include the step of applying radio-frequency (RF) power to the processing chamber to perform a deposition process. The RF power may be provided according to a duty cycle comprising a first RF power provided during a first time duration and a second RF power provided during a second time duration, wherein the second RF power is smaller than the first RF power.

[0006] In some embodiments, the method may include the step of providing a precursor to a semiconductor processing chamber. The precursor may include a gap-filling material for filling features within a semiconductor structure, and the features within the semiconductor structure may have different critical dimensions (CD). The method may also include the step of providing an etchant together with the precursor to a semiconductor processing chamber, wherein the etchant may be configured to etch the gap-filling material. The method may additionally include the step of applying radio-frequency (RF) power to the processing chamber to perform a deposition process. The RF power may be provided according to a duty cycle comprising: a first RF power provided during a first time duration in which the gap-filling material is etched from the top portion of the features while the gap-filling material is deposited from the bottom portion of the features; and a second RF power provided during a second time duration in which the gap-filling material is deposited from the top portion of the features and within the bottom portion of the features.

[0007] In some embodiments, the method may include the step of providing a precursor to a semiconductor processing chamber. The precursor may include a gap-filling material for filling features within a semiconductor structure, and the features within the semiconductor structure may have different critical dimensions (CDs). The method may also include the step of providing an etchant together with the precursor to the semiconductor processing chamber, wherein the etchant may be configured to etch the gap-filling material. The method may also include the step of applying radio-frequency (RF) power to the processing chamber to perform a deposition process. The RF power may be provided according to a duty cycle comprising a first RF power provided for a first time duration and a second RF power provided for a second time duration. The duty cycle may cause features within the semiconductor structure having different CDs to complete the gap-filling process in approximately the same time, and the overburden of the gap-filling material on the top of the semiconductor structure may be substantially uniform.

[0008] In any embodiment, any and / or all of the following features may be implemented in any combination and without limitation. The semiconductor structure may include a memory structure comprising more than 100 alternating oxide / nitride layers. The first time duration may be greater than 50% of the period of the duty cycle. The precursor may include carbon, tungsten, or amorphous silicon. The co-flow rate provided to the processing chamber during the deposition process may be provided according to a duty cycle including a first co-flow rate during the first time duration and a second co-flow rate during the second time duration, wherein the second co-flow rate may be greater than the first co-flow rate. Applying the first RF power may include etching the tops of the pillars of the semiconductor structure while depositing material on the sidewall formations of the trenches of the patterned sample. Applying a second RF power may include depositing material on the tops of the pillars of the patterned sample while depositing material on the sidewall formations of the trenches of the patterned sample. Features within the semiconductor structure may include memory holes having a CD of less than 150 nm. Features within the semiconductor structure may include slits having a CD greater than 350 nm. Features may include first features and second features, and the second features may have a CD at least twice as large as the CD of the first features. The first RF power may result in a higher deposition rate in the first features and a lower deposition rate in the second features. The second RF power may result in similar deposition rates in the first features and the second features.A first RF power can be selected from a first data set for a first feature size and a second data set for a second feature size, wherein the first data set and the second data set may represent deposition rates across an RF power range, and the first RF power may correspond to similar deposition rates in both the first data set and the second data set. A second RF power can be selected from a first data set for a first feature size and a second data set for a second feature size, wherein the first data set and the second data set may represent deposition rates across an RF power range, and the second RF power may correspond to a lower deposition rate in the first data set and a higher deposition rate in the second data set. The duty cycle may allow features in a semiconductor structure having different CDs to complete the gap filling process without voids in the top halves of the features. The duty cycle can cause features within a semiconductor structure having different CDs to complete a gap-filling process to form voids in the lower halves of the features. The duty cycle may include a square wave oscillating between a first RF power and a second RF power, and the first RF power may be 50% to 90% of each cycle. The first RF power may be about 800 W to about 2000 W, and the second RF power may be about 100 W to about 500 W. Brief explanation of the drawing

[0009] Further understanding of the attributes and advantages of the various embodiments can be realized by referring to the remainder of the specification and the drawings, wherein similar reference numbers are used throughout the drawings to refer to similar components. In some examples, a sub-label is associated with a reference number to indicate one of a number of similar components. When a reference number is referred to without specifying an existing sub-label, it is intended to refer to all such a number of similar components.

[0010] FIG. 1 illustrates a schematic cross-sectional view of an exemplary processing chamber according to some embodiments of the present technology.

[0011] FIG. 2 illustrates a schematic cross-sectional view of a patterned sample having different CD zones according to some embodiments.

[0012] FIG. 3 is a graph showing the dependence of the sidewall deposition rate for a trench on the radio-frequency power and cavity flow rate of the deposition process, according to some embodiments.

[0013] Figure 4 is a graph showing the dependence of the sidewall deposition rate for a 400 nm diameter trench, according to some embodiments, on the radio-frequency power and cavity-flow rate of the deposition process.

[0014] FIG. 5 is a graph of the duty cycle for a gap-filling deposition process according to some embodiments.

[0015] FIG. 6 is a flowchart of an example of a process for depositing a material on a patterned substrate according to some embodiments.

[0016] FIG. 7 illustrates an exemplary computer system in which various embodiments can be implemented. Specific details for implementing the invention

[0017] Specific aspects and examples of the present disclosure relate to systems and techniques for depositing layers on patterned samples having features of various dimensions. The various dimensions may be critical dimensions (CDs). A critical dimension may be the minimum size of a feature that affects the electrical properties of a device. Devices may have multiple CDs. For example, a patterned wafer may include stacks of NAND memory elements. One CD of the patterned wafer may be associated with the width of trenches separating the stacks. Another CD may be associated with patterned holes or slits for vias, or for making electrical contact with multiple NAND memory elements within a stack or multiple stacks. Patterned holes may have different dimensions and shapes compared to the trenches. A single gap-filling material may be deposited in the patterned holes and trenches. Forming a uniform layer of gap-filling material on a patterned wafer can be difficult due to variations in the sizes and shapes of the patterned holes and trenches.

[0018] As an example, a patterned sample may have trenches of different dimensions. In a first zone of the patterned sample, smaller trenches may have dimensions of 100 nm, and a second zone of the patterned sample may contain larger trenches with dimensions of 300 nm. When a single sidewall deposition rate is used, the trenches may be filled or experience sidewall pinch-off at different times. For example, at a sidewall deposition rate of 10 nm / min, smaller trenches may experience sidewall pinch-off after 5 minutes (since sidewall growth occurs at both ends of the trench). At the same sidewall deposition rate, larger trenches may experience sidewall pinch-off after 15 minutes. Preferably, to form a uniform overgrowth layer over the pillars and trenches, sidewall pinch-off should occur simultaneously for all trenches regardless of size. Accordingly, preferably, trenches of various CDs may have various deposition rates: trenches with larger diameters may have higher deposition rates than trenches with smaller diameters.

[0019] Additionally, in some examples, trenches with large diameters may experience pinch-offs at multiple locations relative to the large trench. For instance, a large trench may experience sidewall pinch-offs at depth and overgrowth pinch-offs on the trench surface, which can cause unwanted voids within the trench. Unwanted voids can affect the uniformity of continuous deposition processes on the device and have a detrimental effect on device performance.

[0020] The deposition process may include a methodology for forming a uniform overgrowth layer and avoiding void formation despite variations in the CDs of the patterned device. The methodology may involve the application of a time-dependent duty cycle during the deposition process. The time-dependent duty cycle may include parameters that can be optimized based on the geometry of the patterned device. The parameters may include the frequency of the duty cycle, multiple radio-frequency (RF) power values ​​associated with the plasma deposition process, the cavity flow rates of the etchant and precursor for the plasma deposition process, the types of etchants, the types of precursors, or the application times for the multiple RF power values. The application of the time-dependent duty cycle may promote sidewall growth for each trench or hole at deposition rates that depend on the CD associated with each trench or hole. The time-dependent duty cycle may also discourage overgrowth pinch-off by etching the overgrowth during part of the duty cycle without interrupting sidewall growth.

[0021] After describing general aspects of chambers according to some embodiments of the present technology in which the plasma processing operations discussed below can be performed, specific methodologies may be discussed. It will be understood that the described techniques are not intended to be limited to the specific films, chambers, or processes discussed, as they can be used to improve a number of film formation processes and are applicable to various processing chambers and operations.

[0022] FIG. 1 illustrates a cross-sectional view of an exemplary processing chamber (100) according to some embodiments of the present invention. The drawing may illustrate an overview of a system that may be specifically configured to incorporate one or more aspects of the present invention and / or perform one or more operations according to embodiments of the present invention. Additional details of the chamber (100) or the methods performed may be further described below. The chamber (100) may be used to form film layers, etch material layers, form other material layers, or perform a combination thereof, but it should be understood that deposition and etching methods may similarly be performed in any chamber where deposition and etching processes may occur internally. The processing chamber (100) may include a chamber body (102), a substrate support (104) disposed inside the chamber body (102), and a lid assembly (106) coupled to the chamber body (102) and enclosing the substrate support (104) within the processing volume (120). A substrate (103) may be provided to the processing volume (120) through an opening (126) that can be typically sealed for processing using a slit valve or door. The substrate (103) may be placed on the surface (105) of the substrate support during processing. In some embodiments, the substrate support (104) may be rotatable along a vertical axis where the shaft (144) of the substrate support (104) may be positioned, or it may be stationary. Alternatively, the substrate support (104) may be lifted up to rotate as needed during the deposition process.

[0023] The gas distributor (112) may define apertures (118) for distributing process precursors into a processing volume (120). The gas distributor (112) may be coupled to a first electric power source (142), such as an RF generator, an RF power source, a DC power source, a pulsed DC power source, a pulsed RF power source, or any other power source that can be coupled to the processing chamber. In some embodiments, the first electric power source (142) may be an RF power source.

[0024] The gas distributor (112) may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor (112) may also be formed of conductive and non-conductive components. For example, the body of the gas distributor (112) may be conductive, while the face plate of the gas distributor (112) may be non-conductive. The gas distributor (112) may be powered by a first electric power source (142), such as as shown in FIG. 1, or the gas distributor (112) may be coupled to ground in some embodiments.

[0025] The first electrode (122) may be coupled to the substrate support (104). The first electrode (122) may be embedded within the substrate support (104) or coupled to the surface of the substrate support (104). The first electrode (122) may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed arrangement of conductive elements. The first electrode (122) may be a tuning electrode and may be coupled to a tuning circuit (136) by a cable having, for example, a selected resistance, such as 50 ohms, which is placed in a conduit (146), for example, the shaft (144) of the substrate support (104). The tuning circuit (136) may have an electronic controller (140), which may be a variable capacitor, and an electronic sensor (138). The electronic sensor (138) may be a voltage or current sensor and may be coupled with an electronic controller (140) to provide additional control over plasma conditions within the processing volume (120).

[0026] A second electrode (124), which may be a bias electrode and / or an electrostatic chucking electrode, may be coupled to the substrate support (104). The second electrode may be coupled to a second electric power source (150) through a filter (148), which may be an impedance matching circuit. The second electric power source (150) may be DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second electric power source (150) may be RF bias power. The substrate support (104) may also include one or more heating elements configured to heat the substrate to a processing temperature that may be about 25°C to about 800°C or greater.

[0027] The cover assembly (106) and substrate support (104) of FIG. 1 may be used with any processing chamber for plasma or thermal processing. In operation, the processing chamber (100) may provide real-time control of plasma conditions within the processing volume (120) through a system controller (101) that may be included, for example, in a processor (107). A substrate (103) may be placed on the substrate support (104), and process gases may flow through the cover assembly (106) using an inlet (114) according to any desired flow plan. The gases may exit the processing chamber (100) through an outlet (152). Electric power may be coupled to a gas distributor (112) to establish plasma in the processing volume (120). In some embodiments, the substrate may be electrically biased using a second electrode (124).

[0028] When energizing the plasma within the processing volume (120), a potential difference can be established between the plasma and the first electrode (122). Subsequently, an electronic controller (140) can be used to adjust the flow properties of the ground paths represented by the tuning circuit (136). To provide independent control of plasma density uniformity and deposition rate from the center to the edge, a set point can be transmitted to the tuning circuit (136). In embodiments where both electronic controllers may be variable capacitors, the electronic sensors can independently adjust the variable capacitors to maximize the deposition rate and minimize thickness non-uniformity.

[0029] The tuning circuit (136) may have a variable impedance that can be adjusted using an electronic controller (140). If the electronic controller (140) is a variable capacitor, the capacitance range of each variable capacitor may be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, which may have a minimum value within the capacitance range of each variable capacitor. Thus, when the capacitance of the electronic controller (140) is at a minimum or maximum value, the impedance of the tuning circuit (136) may be high, which may result in a plasma shape having minimal aerial or lateral coverage across the substrate support. When the capacitance of the electronic controller (140) approaches a value that minimizes the impedance of the tuning circuit (136), the aerial coverage of the plasma grows to a maximum, effectively covering the entire working area of ​​the substrate support (104). When the capacitance of the electronic controller (140) deviates from the minimum impedance setting, the plasma shape may contract from the chamber walls, and the aerial coverage of the substrate support may be reduced.

[0030] The electronic sensor (138) can be used to tune the tuning circuit (136) in a closed loop. A set point for current or voltage can be installed on each sensor depending on the type of sensor used, and the sensor may be provided with control software that determines the adjustment to the electronic controller (140) to minimize deviation from the set point. Consequently, the plasma shape can be selected and dynamically controlled during processing. Although the foregoing discussion is based on the electronic controller (140), which may be a variable capacitor, it will be understood that any electronic component having adjustable characteristics can be used to provide the tuning circuit (136) having adjustable impedance.

[0031] The processing chamber (100) may be used in some embodiments of the present invention for processing methods that may include bottom-up deposition of materials for semiconductor structures. It should be understood that the described chamber should not be considered limiting, and that any chamber configured to perform operations as described may be used similarly.

[0032] FIG. 2 illustrates a schematic cross-sectional view of a patterned sample having regions of different CDs according to some embodiments. The patterned sample may include a first region (202) and a second region (204). The second region (204) may include features having at least one CD that is different from the CDs associated with the features included in the first region (202) of the patterned sample. The first region (202) may include pillars such as pillar (206A), pillar (206B), and pillar (206C). Although three pillars are shown in the first region (202), the first region (202) may include any number of pillars. Each of the pillars within the first region (202) may be formed from a plurality of alternating deposited layers. The alternating deposited layers may be deposited layers within a memory stack structure such as a NAND structure. For example, the alternating deposited layers may include alternating layers of silicon oxide and silicon nitride.

[0033] A plurality of alternating deposited layers within the first zone (202) may be etched to form pillars including pillar (206A), pillar (206B), and pillar (206C). Etched zones between adjacent pillars may form trenches. Each pillar may have a width w1 and a height h1. Each trench may have a width w2 and a height h1. The trenches may be deep trenches (e.g., h1 >> w2). For example, the width w2 of a trench may be about 100 nm. For example, each trench may have a width w2 of about 10 nm to about 30 nm, about 30 nm to about 50 nm, about 50 nm to about 70 nm, about 70 nm to about 90 nm, about 90 nm to about 110 nm, about 110 nm to about 130 nm, about 130 nm to about 150 nm, about 150 nm to about 170 nm, about 170 nm to about 190 nm, about 190 nm to about 210 nm, about 210 nm to about 230 nm, about 230 nm to about 250 nm, about 250 nm to about 270 nm, about 270 nm to about 290 nm, about 290 nm to about 310 nm, about 310 nm to about 330 nm, and / or about 330 nm to about 350 nm. There is. The width of each trench may also be any combination of these ranges (e.g., about 250 nm to about 300 nm). The width of each trench may also be any specific value within these ranges (e.g., about 160 nm).

[0034] Pillars within the zone (202) may have a width w1 that is the same as or different from the width w2 of the trenches within the zone (202). For example, the width w1 of the pillars within the zone (202) may be about 140 nm. For example, each pillar within the region (202) is about 10 nm to about 30 nm, about 30 nm to about 50 nm, about 50 nm to about 70 nm, about 70 nm to about 90 nm, about 90 nm to about 110 nm, about 110 nm to about 130 nm, about 130 nm to about 150 nm, about 150 nm to about 170 nm, about 170 nm to about 190 nm, about 190 nm to about 210 nm, about 210 nm to about 230 nm, about 230 nm to about 250 nm, about 250 nm to about 270 nm, about 270 nm to about 290 nm, about 290 nm to about 310 nm, about 310 nm to about 330 nm, and / or about 330 nm to about 350 nm. It may have a width. The width of each pillar within the area (202) may also be any combination of these ranges (e.g., about 100 nm to about 250 nm). The width of each pillar within the area (202) may also be any specific value within these ranges (e.g., about 140 nm).

[0035] The height h1 of the trench in the first zone (202) can be about 10 micrometers. For example, each trench may have a height of about 1 micrometer to about 3 micrometers, about 3 micrometers to about 5 micrometers, about 5 micrometers to about 7 micrometers, about 7 micrometers to about 9 micrometers, about 9 micrometers to about 11 micrometers, about 11 micrometers to about 13 micrometers, about 13 micrometers to about 15 micrometers, about 15 micrometers to about 17 micrometers, about 17 micrometers to about 19 micrometers, about 19 micrometers to about 21 micrometers, about 21 micrometers to about 23 micrometers, about 23 micrometers to about 25 micrometers, about 25 micrometers to about 27 micrometers, about 27 micrometers to about 29 micrometers, about 29 micrometers to about 31 micrometers, about 31 micrometers to about 33 micrometers, and / or about 33 micrometers to about 35 micrometers. The height of each trench may also be any combination of these ranges (e.g., about 20 micrometers to about 35 micrometers). The height of each trench may also be any specific value within these ranges (e.g., about 30 micrometers). In some examples, the height of each trench may be designed to be a multiplicative factor of the width of each trench (e.g., h1 = 50*w2, h1 = 100*w2, etc.). The height of the pillars within zone (202) may be the same as the height of the trenches within zone (202).

[0036] The second section (204) may include wide pillars such as wide pillar (208A), wide pillar (208B), wide pillar (208C), and wide pillar (208D). Although four wide pillars are shown in the second section (204), the second section (204) may include any number of wide pillars. Each of the wide pillars within the second section (204) may form vias or contacts to make electrical contact with parts of the patterned sample.

[0037] Layer(s) within the second zone (204) may be etched to form wide pillars including wide pillar (208A), wide pillar (208B), wide pillar (208C), and wide pillar (208D). The etched zone between adjacent wide pillars may form wide trenches. Each wide pillar may have a width w3 and a height h1. Each wide trench may have a width w4 and a height h1. The wide trenches may be deep trenches (e.g., h1 >> w4). The width w4 of the wide trenches in the second zone (204) may be greater than the width w2 of each trench in the first zone (202) (e.g., w4 > w2). For example, the width w3 of the wide trenches may be about 250 nm. For example, each broad trench is about 90 nm to about 110 nm, about 110 nm to about 130 nm, about 130 nm to about 150 nm, about 150 nm to about 170 nm, about 170 nm to about 190 nm, about 190 nm to about 210 nm, about 210 nm to about 230 nm, about 230 nm to about 250 nm, about 250 nm to about 270 nm, about 270 nm to about 290 nm, about 290 nm to about 310 nm, about 310 nm to about 330 nm, about 330 nm to about 350 nm, about 350 nm to about 370 nm, about 370 nm to about 390 nm, about 390 nm to about 410 nm, about 410 nm to about 430 nm, and / or may have a width of about 430 nm to about 450 nm. The width of each wide trench may also be any combination of these ranges (e.g., about 190 nm to about 400 nm). The width of each wide trench may also be any specific value within these ranges (e.g., about 300 nm).

[0038] The wide pillars within the zone (204) may have a width w3 that is the same as or different from the width w4 of the wide trenches within the zone (204). For example, the width w3 of the wide pillars within the zone (204) may be about 240 nm. For example, each broad filament is about 90 nm to about 110 nm, about 110 nm to about 130 nm, about 130 nm to about 150 nm, about 150 nm to about 170 nm, about 170 nm to about 190 nm, about 190 nm to about 210 nm, about 210 nm to about 230 nm, about 230 nm to about 250 nm, about 250 nm to about 270 nm, about 270 nm to about 290 nm, about 290 nm to about 310 nm, about 310 nm to about 330 nm, about 330 nm to about 350 nm, about 350 nm to about 370 nm, about 370 nm to about 390 nm, about 390 nm to about 410 nm, about 410 nm to about 430 nm, and / or may have a width of about 430 nm to about 450 nm. The width of each wide pillar may also be any combination of these ranges (e.g., about 200 nm to about 300 nm). The width of each wide pillar may also be any specific value within these ranges (e.g., about 250 nm). The width w3 of the wide pillars in the second zone (204) may be greater than the width w1 of the pillars in the first zone (202).

[0039] Each of the trenches, slits, holes, or other features etched into the layers of the substrate can be filled with a gap-filling material using a gap-filling process. As described above, voids such as voids (210) may be formed within each wide trench of the second zone (204) during the gap-filling process. Wider pillars and / or wider trenches may cause void formation. Trenches and / or pillars with large diameters may experience pinch-offs at multiple locations relative to the trench. For example, a large trench may experience sidewall pinch-offs at depth and overgrowth pinch-offs on the trench, thereby causing unwanted voids within the trench. Unwanted voids can affect the uniformity of successive deposition processes on the device and may have a detrimental effect on device performance.

[0040] A patterned sample having multiple zones can be incorporated into a process such as a gap-filling deposition process. For example, the patterned sample can be placed in a process chamber such as the process chamber (100) of FIG. 1, and the trenches or patterned holes of the patterned sample can be filled by a gap-filling material (215) during a plasma-enhanced chemical vapor deposition (PECVD) process. During the PECVD process, a methodology can be used to form a uniform overgrowth layer and avoid void formation despite variations in the CDs of the patterned device. The methodology may involve the application of a time-dependent duty cycle during the deposition process. The time-dependent duty cycle may include parameters that can be optimized based on the geometry of the patterned device. Parameters may include the frequency of the duty cycle, multiple radio-frequency (RF) power values ​​associated with the plasma deposition process, cavity flow rates of etchants and precursors for the plasma deposition process, types of etchants, types of precursors, and / or application times for the multiple RF power values. The application of a time-dependent duty cycle can promote sidewall growth for each trench or hole at deposition rates dependent on the CD associated with each trench or hole. The time-dependent duty cycle can also prevent overgrowth pinch-off by etching overgrowth during part of the duty cycle without stopping sidewall growth.

[0041] For example, each feature within the first zone (202) may instead be a memory hole within a memory device stack having a cylindrical shape having a critical dimension or diameter of 100 nm to 120 nm. For example, these holes may be formed in alternating oxide / nitride layers for a NAND memory structure. Features within the second zone (204) may also be contact holes available in the memory stack. The second zone (204) may also include through-hole via extensions to memory cells for landing pads, and other features of the memory device. Thus, the memory structure may include holes of many different sizes having different diameters and critical dimensions. As described above, the first zone (202) and / or the second zone (204) may also include slits or other elongated trenches within the memory devices having various widths. During the manufacturing process, each of these trenches, slits, and / or holes (collectively referred to herein as "features") may be filled with a gap-filling material. When forming the gap-filling material on each of these features, it may be beneficial to form an overgrown or overburdened layer having the same or substantially uniform height over the features in contact hole regions, trench regions, memory hole regions, etc., across the semiconductor structure. As illustrated in FIG. 2, the gap-filling operation may unintentionally create voids, seams, or gaps near the tops of the features. As described above, these voids or gaps may be formed when pinch-off occurs within the feature during the gap-filling process. However, to avoid voids, gap-filling processes in smaller and deeper holes require the use of a slower deposition rate. However, since the semiconductor structure of Fig. 2 also includes relatively large features, it will take too long to gap-fill the larger features at a slow deposition rate.The resulting voids (210) are undesirable and can have negative effects on subsequent processing stages.

[0042] The embodiments described herein address these and other technical problems regarding gap-filling operations in which features have different critical dimensions and / or different geometric structures. These techniques utilize the inherent characteristics of each feature to define the growth rate of the sidewalls during gap-filling. For example, in the case of a feature with a wider CD, the flux of material flowing into the feature will be greater, allowing the larger feature to be gap-filled within nearly the same amount of time as the relatively smaller features within the structure. To change the flux based on the feature size on the same substrate, some embodiments may combine the etchant with the deposition precursor during the gap-filling process. For example, carbon gap-filling can be etched by materials such as carbon dioxide, hydrogen, ammonia, etc. These etchant materials can be provided in a processing chamber along with the carbon precursors for the gap-filling process. By changing the RF power, these techniques can limit the deposition occurring at the top of the feature compared to the bottom of the feature, where a higher deposition rate can be maintained. For example, by etching at the top of the features, the bottom of the features can be filled until pinch-off occurs, leaving an acceptable void (221) at the bottom of the feature. At that point, "blanket" growth occurs in which the bottom of the features are uniformly filled, thereby avoiding the voids (210) that could later become a problem at the top. This pinch-off can occur at a depth of about 400 nm below the surface of the structure or the top of the feature.

[0043] To etch gap-filling material from the top portion of features and allow blanket growth to occur after pinch-off, the embodiments described herein may also adjust the power level of the RF power supplied to the deposition plasma in the processing chamber. For example, plasma conditions can significantly affect the depth at which etching occurs. Conventionally, higher levels of RF power were generally thought to increase the level of deposition relative to the amount of etching that occurs. In contrast, lower levels of RF power were generally thought to decrease the level of deposition. However, it has been found that higher levels of RF power actually result in a greater amount of etching occurring at the top of features, thereby allowing more flux to enter the features, which can result in deposition occurring throughout the depth of the features. For example, the etching process results in more disassociation of material within the features, which allows for higher deposition rates toward the bottom of the features compared to the top. Etching ions have a relatively short lifetime, and once they are within a feature, they tend to recombine. In contrast, certain carbon precursor chemistry can increase the radicals present within the features. Temperatures can be maintained that sustain approximately 95% efficiency when these radicals attach to the sidewalls of the feature for deposition.

[0044] Data based on different geometric structures of features on a substrate may be used to identify process conditions that produce a high etching rate at the top of large features along with a high deposition rate at the bottom of these features. For example, when gap-filling relatively large features (e.g., about 400 nm) and relatively small features (e.g., about 100 nm) simultaneously, a single processing condition may not be sufficient. Instead, multiple process conditions may be identified, and the process may then alternate between these processing conditions for optimal results. For example, a first process condition that produces fast etching at the top of the features may be identified, and a second process condition that produces a high deposition rate within the features may also be identified. Subsequently, the process may alternate (or "duty cycle") between these process conditions. This can result in a balanced process that maintains just enough etching at the top of the features to prevent voids without slowing down the gap-filling process across the depth of the features. For example, some embodiments may alternate between high-deposition rate conditions and low-deposition rate conditions at the top of the features. This allows time for the carbon gap-filling material to adhere, for example, while slowing down hydrogen etching activity at the depth of the features, while also maintaining etching conditions at the top.

[0045] FIG. 3 is a graph (300) showing the dependence of the sidewall deposition rate at a depth of 100 nm in a trench as a function of the RF (radio-frequency) power and cavity flow rate of the deposition process according to some embodiments. The cavity flow rate may describe the combined flow rate of the combination of etching gases and precursors used during the deposition process. In some examples, the deposition process may be a PECVD process for depositing a gap-filling material in a trench. The gap-filling material may be carbon. The etching gases may be gases that etch carbon, such as carbon dioxide, hydrogen, ammonia, nitrous oxide, oxygen, etc. The precursors may be precursors for carbon. The graph shows several regimes for high sidewall deposition rates for hydrogen etching gas. The deposition rates of carbon for these trench widths may be relatively high relative to the intermediate values ​​of both cavity flow rate and RF power. In addition, high deposition rates can be found at very high RF power and very low cavity flow rates. Low deposition rates occur at intermediate RF power values ​​and very high cavity flow rates. It should be noted that relatively low deposition rates can be found at very high RF power values ​​and low to intermediate values ​​for cavity flow rates.

[0046] FIG. 4 is a graph (400) showing the dependence of sidewall deposition at a depth of 400 nm in a trench as a function of RF power and cavity flow rate of the deposition process according to some embodiments. As described above, cavity flow rate can describe the combined flow rate of the combination of etching gases and precursors used during the deposition process. In some examples, the deposition process may be a PECVD process for depositing gap-filling material in a trench. The gap-filling material may be carbon. The etching gases may be gases that etch carbon, such as carbon dioxide, hydrogen, ammonia, nitrous oxide, oxygen, etc. The precursors may be precursors for carbon. The graph shows various regimes for high sidewall deposition rates for hydrogen etching gas. The deposition rates of carbon for these trench widths may be relatively high relative to the intermediate values ​​of both cavity flow rate and RF power. In addition, high deposition rates can be found at very high RF power and very low cavity flow rates. In contrast to the graph (300) for a 100 nm diameter trench, high deposition rates can also be found at very high RF power values ​​and low to medium values ​​for cavity flow rates.

[0047] Using data such as that found in graphs (300) and (400), it is possible to identify a regime that can provide a high deposition rate for larger features while simultaneously providing low deposition conditions for smaller features. For example, zone (333) within graphs (300) and (400) exemplifies a low deposition zone for both large and small features. In contrast, zone (335) exemplifies a low deposition zone for small features while simultaneously providing a high deposition zone for large features. Subsequently, identifying these types of zones can provide operating conditions, and between those operating conditions, the process can duty cycle to balance etching and deposition and maintain consistent gap filling across large and small features.

[0048] For example, a cavity flow rate for a deposition process may be selected as a process parameter. A first data set may be provided for a first feature size, and a second data set may be provided for a second feature size. Graph (300) may be a first data set representing deposition rates over an RF power range. Graph (400) may be a second data set representing deposition rates over the same RF power range. A second power to be used during a second time duration of the duty cycle may be selected such that the RF power corresponds to a relatively low (and possibly similar) deposition rate in the data sets of both graphs. A first power to be used during a second time duration of the duty cycle may be selected such that the deposition rate for smaller features is lower than the deposition rate for larger features.

[0049] It should be noted that graphs (300) and (400) are provided for illustrative purposes only and are not intended to be limiting. These data represent specific types of deposition precursors and / or etching bonds at specific temperatures. Different precursors or agents may be more effective at different temperatures and may reveal completely different regions where low / high deposition bonds may be most effective. Therefore, these data may be obtained experimentally or simulated for any precursor, etchant, and / or temperature bond as needed.

[0050] FIG. 5 is a graph (500) of a duty cycle for a gap-filling deposition process according to some embodiments. The gap-filling deposition process can be applied to a patterned sample having features such as trenches or holes of various dimensions. The graph (500) shows a plot (502) showing RF power as a function of time. The duty cycle is given by a first RF power magnitude P1, a second RF power magnitude P2, a period T, and a frequency ( It may include ). The first power size may be larger than the second power size (e.g., P1 > P2). The first power size P1 may be about 1500 watts. For example, the first power size may have a value of about 800 watts to about 900 watts, about 900 watts to 1000 watts, about 1000 watts to about 1100 watts, about 1100 watts to about 1200 watts, about 1200 watts to about 1300 watts, about 1300 watts to about 1400 watts, about 1400 watts to about 1500 watts, about 1500 watts to about 1600 watts, about 1600 watts to about 1700 watts, about 1700 watts to about 1800 watts, about 1800 watts to about 1900 watts, and / or about 1900 watts to about 2000 watts. The first power size may also be any combination of these ranges (e.g., about 1200 watts to about 17000 watts). The first power size may also be any specific value within these ranges (e.g., about 1500 watts). In some examples, the first power size may be designed to be a multiple factor of the second power size (e.g., P1 = 1.5*P2, P1 = 2*P2, etc.).

[0051] The second power size P2 may be about 250 watts. For example, the second power size may have values ​​of about 100 watts to about 150 watts, about 150 watts to 200 watts, about 200 watts to about 250 watts, about 250 watts to about 300 watts, about 300 watts to about 350 watts, about 350 watts to about 400 watts, about 400 watts to about 450 watts, and / or about 450 watts to about 500 watts. The second power size may also be any combination of these ranges (e.g., about 200 watts to about 300 watts). The second power size may also be any specific value within these ranges (e.g., about 275 watts).

[0052] The frequency f of the duty cycle may be about 1000 Hz. For example, the frequency of the duty cycle may have values ​​of about 50 Hz to about 500 Hz, about 500 Hz to 1 kHz, about 1 kHz to about 5 kHz, about 5 kHz to about 10 kHz, about 10 kHz to about 50 kHz, about 50 kHz to about 100 kHz, about 100 kHz to about 500 kHz, and / or about 500 kHz to about 1 MHz. The frequency of the duty cycle may also be any combination of these ranges (e.g., about 500 Hz to about 10 kHz). The frequency of the duty cycle may also be any specific value within these ranges (e.g., about 1.2 kHz).

[0053] A first power magnitude P1 may be applied for a time duration T1. The time duration T1 may be greater than 50% of the period T of the duty cycle. For example, when the frequency f of the duty cycle is 1 kHz, the period is 1 millisecond, and the first power magnitude may be applied for at least 0.5 milliseconds. A second power magnitude may be applied for a time duration T2. ​​The time duration T2 may be smaller than the time duration T1. In some examples, the time duration T2 may be a percentage of the time duration T1. The time duration T2 may be about 50% of the time duration T1. Thus, in an example where the frequency is about 1 kHz, the time duration T1 may be about 0.67 milliseconds, and the time duration T2 may be about 0.33 milliseconds. For example, the time duration T2 may have a value of about 5% to about 15% of the time duration T1, about 15% to about 25% of the time duration T1, about 25% to about 35% of the time duration T1, about 35% to about 45% of the time duration T1, about 45% to about 55% of the time duration T1, about 55% to about 65% of the time duration T1, about 65% to about 75% of the time duration T1, about 75% to about 85% of the time duration T1, and / or about 85% to about 95% of the time duration T1. The time duration T2 may also be any combination of these ranges (e.g., about 5% of the time duration T1 to about 95% of the time duration T1). The time duration T2 may also be any specific value within these ranges (e.g., about 50% of the time duration T1).

[0054] A duty cycle can be applied while the patterned sample is in a process chamber, such as the process chamber (100) described in FIG. 1. The sample can be maintained at a constant temperature while the duty cycle is applied. The temperature can enhance the generation of free radicals of the gap-filling material in the process chamber and promote the deposition of the gap-filling material. For example, the gap-filling material may be carbon, tungsten, amorphous silicon, etc. The process chamber may include gases capable of etching the gap-filling material and precursors capable of assisting in forming deposited layers of the gap-filling material. During the time duration T1 of the duty cycle, the application of a first power magnitude P1 can effectively not only etch but also deposit the gap-filling material. During the application of P1, the etchant gases can remove the gap-filling material from the tops of the pillars, while additional gap-filling material can be deposited as a sidewall material within the trenches. Removing gap-filling material from the tops of the pillars can reduce the likelihood of void formation by avoiding pinch-off occurrences accompanied by overgrowth material. Etchent gases may have a lifetime that allows them to remove gap-filling material from the tops of the pillars without removing gap-filling material from the sidewalls of the trenches. Due to this lifetime, the etchant gases may be absorbed before reaching the depth associated with sidewall growth within the trenches. During a time duration T1, sidewall deposition rates may depend on the dimensions of the trenches. For example, trenches with larger diameters may have higher sidewall deposition rates than trenches with smaller diameters.

[0055] The application of a second power magnitude P2 during the duty cycle time duration T2 can effectively deposit the gap-filling material without etching the gap-filling material. The second power magnitude may be smaller than the first power magnitude P1. During the time duration T2, the gap-filling material may grow on the sidewalls of the trenches, on the tops of the pillars, or on both. During the time duration T2, the sidewall deposition rates may depend on the dimensions of the trenches. For example, trenches with larger diameters may have higher sidewall deposition rates than trenches with smaller diameters. The duty cycle can promote the formation of a smooth or flat overgrowth layer on the pillars of the patterned sample.

[0056] The cavity flow rate may be constant during the duty cycle time durations T1 and T2. Alternatively, the first cavity flow rate may be associated with the time duration T1, and the second cavity flow rate may be associated with the time duration T2. ​​The first cavity flow rate may differ from the second cavity flow rate. For example, the second cavity flow rate may be greater or smaller than the first cavity flow rate. The values ​​of P1, P2, T1, T2, the first cavity flow rate, or the second cavity flow rate may be determined based on the geometric structure of the patterned sample or parameters of the gap-filling deposition process. The geometric structure of the patterned sample or the parameters of the gap-filling deposition process may include types of shapes of features on the patterned sample, maximum CD for features, minimum CD for features, ranges of CDs, number of different features, depths of trenches, target overgrowth layer thickness, gap-filling material, type of etchant gas used for the duty cycle, type of precursor, number of precursors, target sidewall deposition rates, target overgrowth deposition rates, target etching rates, etc.

[0057] FIG. 6 is a flowchart of an example of a process for depositing material on a patterned substrate according to some aspects of the present disclosure. The operations of the flowchart begin at block (602) and may be performed in the indicated order or any suitable order. Other examples may involve more operations, fewer operations, operations different from those shown in FIG. 6, or an order different from those shown in FIG. 6. Some or all of the steps of the process (600) may be performed by processors.

[0058] In block (602), the process (600) may provide a precursor to a semiconductor processing chamber. The precursor may include precursors for a gap-filling material for filling features within a semiconductor structure. The semiconductor structure may include a large memory structure such as a NAND structure as described above. For example, the semiconductor structure may include alternating oxide / nitride layers, such as more than about 50 layers, more than about 100 layers, more than about 200 layers, etc. These layers may be assembled into "decks" or stacks that are deposited, etched, and then filled with a gap-filling material before additional decks are formed on top of existing decks. The overburden after the gap-filling process may be flattened to expose the top of the semiconductor structure. Features may include memory holes, slits, trenches, contact holes, and / or other features that may be present in the memory structure. Features may have different feature sizes, such as different critical dimensions. For example, features may have a height of about 10 μm to about 30 μm. However, the widths of these features may vary, for example, from 100 nm to a maximum of 500 nm.

[0059] In block (604), the process (600) may include providing an etchant along with a precursor to a semiconductor processing chamber. The etchant may be configured to etch the gap-filling material. For example, the etchant may be more selective for the gap-filling material than for other surfaces exposed on the semiconductor structure. The etchant and the gap-filling precursor may be provided to the processing chamber simultaneously. These gases may be provided in a cavity flow as described above.

[0060] The process (600) may include applying RF power to a processing chamber to perform a deposition process. For example, the process (600) may involve depositing material on a patterned substrate using a process having a cyclic duty cycle. The process may be a PECVD process, and the material may be a gap-filling material such as carbon, tungsten, amorphous silicon, or any other suitable precursor for various gap-filling materials. The duty cycle may be designed to ensure that the gap-filling is deposited to have a flat overgrowth layer despite the presence of multiple CDs on the patterned substrate. The flat overgrowth layer may have a target maximum (or target minimum) surface roughness. Surface roughness may be described by variations in the height of the flat overgrowth layer. For example, the overburden of the gap-filling material on the top of the semiconductor substrate may be substantially uniform (e.g., variations in thickness of less than 5% across the surface).

[0061] RF power can be provided according to the duty cycle. In block (606), the first RF power can be provided during the first time duration of the duty cycle. In block (608), the second RF power can be provided during the second time duration of the duty cycle. The timing of the duty cycle and the selected RF power levels can cause the gap-filling material to be deposited within the lowest portion of the features during the first time duration, while simultaneously causing the gap-filling material to be etched from the highest portion of the features. For example, the material can be deposited on the lowest 50% of the feature until pinch-off occurs at the lowest portion of the feature. Subsequently, the "lower portion" of the feature can be gradually moved toward the highest portion of the feature as gap-filling proceeds using a blanket-filling pattern. Voids may form under these pinch-offs at the bottom of the feature, which is acceptable as there is no risk of void exposure when the overburden is planarized from the top of the semiconductor structure and can reduce the time required to remove the gap-filling material. However, as blanket gap filling proceeds, this process can prevent the formation of voids in the top half of the feature, which would be at risk of exposure after planarization.

[0062] The application of a first power value can not only etch but also deposit the gap-filling material. During the first time duration, the gap-filling material can be etched by an etchant gas from some surfaces of the patterned sample, such as the top surfaces of the pillars. The etchant gas can remove the gap-filling material from the surfaces of the patterned sample. For example, when the gap-filling material is carbon, the etchant gas may be carbon dioxide, hydrogen, ammonia, nitrous oxide, oxygen, or a mixture of some of the aforementioned. Removing the gap-filling material from the tops of the pillars can reduce the possibility of void formation by avoiding pinch-off occurrences accompanied by overgrowth material.

[0063] During the first time duration, gap-filling material may be deposited and accumulated on some surfaces of the patterned substrate. For example, gap-filling material may be deposited on the sidewalls of trenches of the patterned substrate. Etchent gases may have a lifetime that allows the etchant gases to remove gap-filling material from the tops of the pillars without removing the gap-filling material from the sidewall formations of the trenches. Due to this lifetime, the etchant gases may be absorbed before reaching the depth associated with sidewall growth within the trenches. During the first time duration, sidewall deposition rates may depend on the dimensions of the trenches. For example, trenches with larger diameters may have higher sidewall deposition rates than trenches with smaller diameters.

[0064] A first cavity flow rate may be applied during a first time duration. The cavity flow rate may be the combined flow rate of the precursor material and the etchant gas present during the PECVD process. Values ​​for a first power value, a first time duration, or a first cavity flow rate may be determined based on the geometry of the patterned sample or parameters of the gap-filling deposition process. The geometry of the patterned sample or parameters of the gap-filling deposition process may include types of shapes of features on the patterned sample, maximum CD for features, minimum CD for features, ranges of CDs, number of different features, depths of trenches, target overgrowth layer thickness, gap-filling material, type of etchant gas used for the duty cycle, type of precursor, number of precursors, target sidewall deposition rates, target overgrowth deposition rates, target etching rates, etc.

[0065] The time dependence of the duty cycle may be similar to plot (502) of graph (500) in FIG. 5. The duty cycle may be periodic with respect to time and may have a period and a frequency. The duty cycle may be divided into a first time duration and a second time duration such that the sum of the first time duration and the second time duration is equal to the period of the duty cycle. In some examples, the first time duration may be greater than 50% of the period, and the second time duration may be less than 50% of the period of the duty cycle.

[0066] The application of a second RF power can deposit a gap-filling material on a patterned sample without etching the gap-filling material from the patterned sample. The second power magnitude may be smaller than the first power magnitude. During the second time duration, the gap-filling material may grow on the sidewall formations of the trenches, on the tops of the pillars, or on both. During the second time duration, the sidewall deposition rates may depend on the dimensions of the trenches. For example, trenches with larger diameters may have higher sidewall deposition rates than trenches with smaller diameters.

[0067] A second cavity flow rate may be applied during a second time duration. The second cavity flow rate may differ from the first cavity flow rate. For example, the second cavity flow rate may be greater than the first cavity flow rate. Values ​​for the second power value, the second time duration, or the second cavity flow rate may be determined based on the geometric structure of the patterned sample or parameters of the gap-filling deposition process. The geometric structure of the patterned sample or parameters of the gap-filling deposition process may include types of shapes of features on the patterned sample, maximum CD for features, minimum CD for features, ranges of CDs, number of different features, depths of trenches, target overgrowth layer thickness, gap-filling material, type of etchant gas used for the duty cycle, type of precursor, number of precursors, target sidewall deposition rates, target overgrowth deposition rates, target etching rates, etc.

[0068] The method (600) may be implemented as part of a recipe or other control methodology for controlling the conditions and operations of a semiconductor processing chamber. For example, the controller of the semiconductor processing chamber may include one or more processors and one or more memory devices for storing instructions (e.g., one or more non-transient computer-readable media). The instructions may cause one or more processors to perform the operations of the methods described above.

[0069] FIG. 7 illustrates an exemplary computer system (700) in which various embodiments may be implemented. The system (700) may be used to implement a controller for any of the computer systems described above, such as a semiconductor processing system. As illustrated in the drawing, the computer system (700) includes a processing unit (704) that communicates with a number of peripheral subsystems via a bus subsystem (702). These peripheral subsystems may include a processing acceleration unit (706), an I / O subsystem (708), a storage subsystem (718), and a communication subsystem (724). The storage subsystem (718) includes tangible computer-readable storage media (722) and system memory (710).

[0070] The bus subsystem (702) provides a mechanism for various components and subsystems of the computer system (700) to communicate with each other as intended. Although the bus subsystem (702) is schematically illustrated as a single bus, alternative embodiments of the bus subsystem may utilize multiple buses. The bus subsystem (702) may be any of the various types of bus structures, including a memory bus or memory controller, a peripheral bus, and a local bus using any of the various bus architectures. For example, such architectures may include an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus, and the PCI bus may be implemented as a mezzanine bus manufactured according to the IEEE P1386.1 standard.

[0071] A processing unit (704), which may be implemented as one or more integrated circuits (e.g., a conventional microprocessor or microcontroller), controls the operation of a computer system (700). One or more processors may be included in the processing unit (704). These processors may include single-core or multi-core processors. In certain embodiments, the processing unit (704) may be implemented as one or more independent processing units (732 and / or 734) having single or multi-core processors included in each processing unit. In other embodiments, the processing unit (704) may also be implemented as a quad-core processing unit formed by integrating two dual-core processors into a single chip.

[0072] In various embodiments, the processing unit (704) may execute various programs in response to program code and may maintain a number of concurrently executed programs or processes. At any given time, part or all of the program code to be executed may reside in the processor(s) (704) and / or the storage subsystem (718). Through appropriate programming, the processor(s) (704) may provide the various functions described above. The computer system (700) may additionally include a processing acceleration unit (706), which may include a digital signal processor (DSP), a special-purpose processor, etc.

[0073] The I / O subsystem (708) may include user interface input devices and user interface output devices. User interface input devices may include keyboards, pointing devices, such as a mouse or trackball, a touchpad or touchscreen integrated into a display, a scroll wheel, a click wheel, a dial, a button, a switch, a keypad, audio input devices having voice command recognition systems, microphones, and other types of input devices.

[0074] User interface output devices may include display subsystems, indicator lights, or non-visual displays, such as audio output devices. Display subsystems may be flat-panel devices, projection devices, touch screens, etc., such as using a cathode ray tube (CRT), liquid crystal display (LCD), or plasma display. Generally, the use of the term "output device" is intended to include all possible types of devices and mechanisms for outputting information from the computer system (700) to a user or another computer. For example, user interface output devices may include, without limitation, various display devices that visually convey text, graphics, and audio / video information, such as monitors, printers, speakers, headphones, car navigation systems, plotters, voice output devices, and modems.

[0075] The computer system (700) may include a storage subsystem (718) containing software elements described as currently located within the system memory (710). The system memory (710) may store program instructions that are loadable onto the processing unit (704) and executable on the processing unit (704), as well as data generated during the execution of these programs.

[0076] Depending on the configuration and type of the computer system (700), the system memory (710) may be volatile (e.g., RAM (random access memory)) and / or non-volatile (e.g., ROM (read-only memory), flash memory, etc.). RAM typically contains data and / or program modules that are immediately accessible to the processing unit (704) and / or are currently operating and executing by the processing unit (704). In some implementations, the system memory (710) may include a number of different types of memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM). In some implementations, a basic input / output system (BIOS) containing basic routines that help transfer information between elements within the computer system (700) during startup may typically be stored in ROM. As an example not limited to, system memory (710) also exemplifies application programs (712), program data (714), and operating system (716), which may include client applications, web browsers, middle-tier applications, relational database management systems (RDBMS), etc.

[0077] The storage subsystem (718) may also provide a computer-readable storage medium of a type for storing basic programming and data configurations that provide the functions of some embodiments. Software (programs, code modules, instructions) that provide the functions described above when executed by a processor may be stored in the storage subsystem (718). These software modules or instructions may be executed by the processing unit (704). The storage subsystem (718) may also provide a repository for storing data used according to some embodiments.

[0078] The storage subsystem (718) may also include a computer-readable storage medium reader (720) that may be additionally connected to computer-readable storage media (722). Together and optionally, in combination with system memory (710), computer-readable storage media (722) may comprehensively represent storage media for temporarily and / or more permanently containing, storing, transmitting, and retrieving computer-readable information plus remote, local, fixed, and / or removable storage devices.

[0079] Computer-readable storage media (722) containing code or parts of code may also include any suitable media including storage media and communication media such as (but not limited to) volatile and non-volatile, removable and non-removable media implemented by any method or technique for storing and / or transmitting information. This may include tangible computer-readable storage media, such as RAM, ROM, EEPROM (electronically erasable programmable ROM), flash memory or other memory technology, CD-ROM, DVD (digital versatile disk) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or other types of computer-readable media. This may also include intangible computer-readable media such as data signals, data transmissions, or any other media that can be used to transmit desired information and can be accessed by the computing system (700).

[0080] For example, computer-readable storage media (722) may include a hard disk drive that reads from or writes to non-removable nonvolatile magnetic media, a magnetic disk drive that reads from or writes to a removable nonvolatile magnetic disk, and an optical disk drive that reads from or writes to a removable nonvolatile optical disk, such as a CD-ROM, DVD, and Blu-Ray® disk, or other optical media. Computer-readable storage media (722) may include flash memory cards, USB (universal serial bus) flash drives, SD (secure digital) cards, DVD disks, digital video tapes, etc. (but are not limited thereto). Computer-readable storage media (722) may also include solid-state drives (SSDs) based on non-volatile memory, such as flash-memory-based SSDs, enterprise flash drives, solid-state ROM, etc., SSDs based on volatile memory, such as solid-state RAM, dynamic RAM, static RAM, DRAM-based SSDs, MRAM (magnetoresistive RAM) SSDs, and hybrid SSDs using a combination of DRAM and flash memory-based SSDs. Disk drives and their associated computer-readable media may provide non-volatile storage of computer-readable instructions, data structures, program modules, and other data for a computer system (700).

[0081] The communication subsystem (724) provides an interface to other computer systems and networks. The communication subsystem (724) serves as an interface for receiving data from other systems and transmitting data from the computer system (700) to other systems. For example, the communication subsystem (724) can enable the computer system (700) to be connected to one or more devices via the Internet. In some embodiments, the communication subsystem (724) may include RF (radio frequency) transceiver components, GPS (global positioning system) receiver components, and / or other components for accessing wireless voice and / or data networks (e.g., using cellular telephone technology, advanced data network technology, such as 3G, 4G, or EDGE (enhanced data rates for global evolution), WiFi (IEEE 802.11 standard family, or other mobile communication technologies, or any combination thereof). In some embodiments, the communication subsystem (724) may provide a wired network connection (e.g., Ethernet) in addition to or instead of the wireless interface.

[0082] In some embodiments, the communication subsystem (724) may also receive input communications in the form of structured and / or unstructured data feeds (726), event streams (728), event updates (730), etc., on behalf of one or more users who can use the computer system (700).

[0083] Additionally, the communication subsystem (724) may also be configured to receive data in the form of continuous data streams that may include event streams (728) and / or event updates (730) of real-time events that may be continuous or boundless without explicit termination by nature. Examples of applications that generate continuous data may include, for instance, sensor data applications, financial tickers, network performance measurement tools (e.g., network monitoring and traffic management applications), clickstream analysis tools, automotive traffic monitoring, etc.

[0084] The communication subsystem (724) may also be configured to output structured and / or unstructured data feeds (726), event streams (728), event updates (730), etc., to one or more databases capable of communicating with one or more streaming data source computers coupled to the computer system (700).

[0085] The computer system (700) may be one of various types including a handheld portable device (e.g., smartphone, computing tablet, PDA), PC, workstation, mainframe, kiosk, server rack, or any other data processing system.

[0086] Due to the ever-changing nature of computers and networks, the description of the computer system (700) depicted in the drawings is intended only as a specific example. Many other configurations are possible with more or fewer components than the system depicted in the drawings. For example, customized hardware may also be used, and / or specific elements may be implemented in hardware, firmware, software (including applets), or a combination thereof. Additionally, connections to other computing devices, such as network input / output devices, may be utilized. Based on the disclosures and teachings provided herein, other ways and / or methods for implementing various embodiments will be apparent.

[0087] As used herein, the terms “about,” “approximately,” or “substantially” may be interpreted as being within the scope expected by a person skilled in the art in light of the specification.

[0088] In the foregoing description, for the purposes of explanation, many specific details have been described to provide a complete understanding of the various embodiments. However, it will be apparent that some embodiments may be practiced without some of these specific details. In other examples, well-known structures and devices are illustrated in the form of block diagrams.

[0089] The foregoing description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the foregoing description of various embodiments will provide an enabling disclosure for implementing at least one embodiment. It should be understood that various changes in the function and arrangement of elements may be made without departing from the spirit and scope of some embodiments as described in the appended claims.

[0090] Specific details are provided in the foregoing description to provide a thorough understanding of the embodiments. However, it will be understood that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be illustrated as components in the form of block diagrams to avoid obscuring the embodiments with unnecessary details. In other examples, well-known circuits, processes, algorithms, structures, and techniques may be illustrated without unnecessary details to avoid obscuring the embodiments.

[0091] Additionally, note that individual embodiments may be described as processes depicted as flowcharts, flow diagrams, data flow diagrams, structure diagrams, or block diagrams. While flowcharts may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process terminates when the operations of the process are completed, but may have additional steps not included in the drawings. A process may correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, the termination of the process may correspond to a return to the calling function or the main function.

[0092] The term "computer-readable medium" includes (but is not limited to) portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or transporting instruction(s) and / or data. Code segments or machine-executable instructions may represent any combination of procedures, functions, subprograms, programs, routines, subroutines, modules, software packages, classes, or instructions, data structures, or program statements. A code segment may be coupled to another code segment or hardware circuit by transmitting and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be transmitted, forwarded, or transmitted through any suitable means including memory sharing, message passing, token passing, network transmission, etc.

[0093] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented by software, firmware, middleware, or microcode, program code or code segments for performing necessary tasks may be stored on a machine-readable medium. Processor(s) may perform the necessary tasks.

[0094] In the foregoing specification, features are described with reference to specific embodiments thereof, but it should be recognized that not all embodiments are limited thereto. Various features and aspects of some embodiments may be used individually or together. Additionally, embodiments may be used in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of this specification. Accordingly, the specification and drawings should be regarded as illustrative rather than restrictive.

[0095] Additionally, for the purposes of illustration, the methods have been described in a specific order. It should be recognized that in alternative embodiments, the methods may be performed in a different order than described. It should also be recognized that the methods described above may be performed by hardware components or implemented as sequences of machine-executable instructions, which may be used to cause a machine, such as a general-purpose or special-purpose processor or logic circuits programmed with instructions, to perform the methods. These machine-executable instructions may be stored on one or more machine-readable media, such as CD-ROMs or other types of optical discs, floppy disks, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, flash memory, or other types of machine-readable media suitable for storing electronic instructions. Alternatively, the methods may be performed by a combination of hardware and software.

Claims

Claim 1 A method comprising the steps of: providing a precursor to a semiconductor processing chamber — said precursor comprises a gapfill material for filling features within a semiconductor structure, said features within a semiconductor structure having different critical dimensions (CDs); providing an etchant together with said precursor to the semiconductor processing chamber — said etchant is configured to etch the gapfill material —; and applying radio-frequency (RF) power to the processing chamber to perform a deposition process, wherein the RF power is provided according to a duty cycle, said duty cycle comprises: a first RF power provided during a first time duration; and a second RF power provided during a second time duration, said second RF power being smaller than the first RF power. Claim 2 A method according to claim 1, wherein the semiconductor structure comprises a memory structure comprising more than 100 alternating oxide / nitride layers. Claim 3 A method according to claim 1, wherein the first time duration is greater than 50% of the period of the duty cycle. Claim 4 A method according to claim 1, wherein the precursor comprises carbon, tungsten, or amorphous silicon. Claim 5 The method of claim 1 further comprises the step of providing a co-flow rate to the processing chamber while performing the deposition process, wherein the co-flow rate is provided according to the duty cycle, and the duty cycle comprises a first co-flow rate during the first time duration; and a second co-flow rate during the second time duration, wherein the second co-flow rate is greater than the first co-flow rate. Claim 6 A method according to claim 1, wherein applying the first RF power comprises etching the top portions of the pillars of the semiconductor structure while depositing the material on the sidewall formations of the trenches of the patterned sample. Claim 7 A method according to claim 1, wherein applying the second RF power comprises depositing the material on the top portions of the pillars of the patterned sample while depositing the material on the sidewall formations of the trenches of the patterned sample. Claim 8 A method comprising the steps of: providing a precursor to a semiconductor processing chamber — said precursor comprises a gap-filling material for filling features within a semiconductor structure, said features within a semiconductor structure having different critical dimensions (CDs); providing an etchant together with said precursor to the semiconductor processing chamber — said etchant is configured to etch said gap-filling material —; and applying radio-frequency (RF) power to the processing chamber to perform a deposition process, wherein the RF power is provided according to a duty cycle, said duty cycle comprising: a first RF power provided during a first time duration in which the gap-filling material is etched from the top portion of said features while the gap-filling material is deposited from the bottom portion of said features; and a second RF power provided during a second time duration in which the gap-filling material is deposited from the top portion of said features and from the bottom portion of said features. Claim 9 In claim 8, the method wherein the features within the semiconductor structure include memory holes having a CD of less than 150 nm. Claim 10 In claim 8, the method wherein the features within the semiconductor structure include slits having a CD greater than 350 nm. Claim 11 In claim 8, the above features include first features and second features, and the second features have a CD that is at least twice as large as the CD of the first features. Claim 12 A method according to claim 11, wherein the first RF power results in a higher deposition rate in the first features and a lower deposition rate in the second features. Claim 13 In claim 11, the method wherein the second RF power results in a similar deposition rate in the first features and the second features. Claim 14 A method according to claim 11, further comprising the step of selecting the first RF power from a first data set for a first feature size and a second data set for a second feature size, wherein the first data set and the second data set represent deposition rates over an RF power range, and the first RF power corresponds to a similar deposition rate in both the first data set and the second data set. Claim 15 A method according to claim 11, further comprising the step of selecting a second RF power from a first data set for a first feature size and a second data set for a second feature size, wherein the first data set and the second data set represent deposition rates over an RF power range, and the second RF power corresponds to a lower deposition rate in the first data set and a higher deposition rate in the second data set. Claim 16 A method comprising the steps of: providing a precursor to a semiconductor processing chamber ― said precursor comprises a gap-filling material for filling features within a semiconductor structure, said features within the semiconductor structure having different critical dimensions (CDs); providing an etchant together with said precursor to the semiconductor processing chamber ― said etchant is configured to etch the gap-filling material ― said etchant comprises the steps of: applying radio-frequency (RF) power to the processing chamber to perform a deposition process, said RF power is provided according to a duty cycle, said duty cycle comprises: a first RF power provided for a first time duration; and a second RF power provided for a second time duration, said duty cycle causes features within the semiconductor structure having different CDs to complete the gap-filling process in approximately the same time, and the overburden of the gap-filling material on the top of the semiconductor structure is substantially uniform. Claim 17 In claim 16, the duty cycle causes features within the semiconductor structure having different CDs to complete the gap filling process without voids in the upper halves of the features. Claim 18 In claim 16, the duty cycle completes the gap filling process so that features within the semiconductor structure having different CDs form voids in the lower halfs of the features. Claim 19 In claim 16, the duty cycle comprises a square wave oscillating between the first RF power and the second RF power, and the first RF power comprises 50% to 90% of each cycle. Claim 20 In claim 16, the first RF power comprises about 800 W to about 2000 W; and the second RF power comprises about 100 W to about 500 W.

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