Memory devices including vertical stack structure, methods of manufacturing the same and electronic apparatuses including memory device

Abstract

A memory device including a vertical stacking structure, a method for manufacturing the same, and an electronic device including the memory device are disclosed. A memory device including a vertical stacking structure according to one embodiment comprises an oxygen scavenger layer provided on a base substrate, a recording material layer provided on the oxygen scavenger layer and in direct contact with the oxygen scavenger layer, a channel layer provided on the recording material layer, a gate insulating layer provided on the channel layer, and a gate electrode provided on the gate insulating layer, wherein the oxygen scavenger layer includes an element that creates an oxygen vacancy in the recording material layer and does not include oxygen.

Description

Technology Field

[0001] The present disclosure relates to a memory device, and more specifically, to a memory device comprising a structure in which a plurality of memory cells are vertically stacked, a method for manufacturing the same, and an electronic device comprising the memory device. Background Technology

[0002] Semiconductor devices can be classified into memory devices and logic devices. Memory devices are devices that store data. Generally, semiconductor memory devices can be broadly classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices are memory devices in which stored data is lost when the power supply is interrupted; examples include DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). Nonvolatile memory devices are memory devices in which stored data is not lost even when the power supply is interrupted; examples include PROM (Programmable ROM), EPROM (Erasable PROM), EEPROM (Electrically EPROM), and Flash Memory Devices.

[0003] Furthermore, in line with the recent trend toward higher performance and lower power consumption in semiconductor memory devices, next-generation semiconductor memory devices such as MRAM (Magnetic RAM), PCRAM (Phase Change RAM), and ReRAM (Resistive RAM) are being developed. The materials constituting these next-generation semiconductor memory devices exhibit resistance values ​​that change depending on current, voltage, or heat, and possess the characteristic of maintaining their resistance even when the supply of current or voltage is interrupted. Research is currently underway to apply these memories in a VNAND format. In the case of NAND flash products, which currently dominate the memory market, VNAND products are the primary items due to their advantages in increasing integration density. However, as these VNAND products are gradually reaching the height limits permissible in current chip packaging, there is a need to research methods for scaling unit cells. Applying the aforementioned next-generation semiconductor memory devices in a VNAND format enables unit cell scaling along with a reduction in operating voltage, and research regarding this is currently being conducted. The problem to be solved

[0004] An exemplary embodiment provides a memory device including a vertical stacking structure capable of ensuring stable memory operation.

[0005] An exemplary embodiment provides a memory device including a vertical stacking structure capable of increasing integration density.

[0006] An exemplary embodiment provides a method for manufacturing such a memory device.

[0007] An exemplary embodiment is provided of an electronic device including such a memory element. means of solving the problem

[0008] A memory device comprising a vertical stacking structure according to an exemplary embodiment comprises a base substrate, an oxygen scavenger layer provided on the base substrate, a recording material layer provided on the oxygen scavenger layer and in direct contact with the oxygen scavenger layer, a channel layer provided on the recording material layer, a gate insulating layer provided on the channel layer, and a gate electrode provided on the gate insulating layer, wherein the oxygen scavenger layer includes an element that creates an oxygen vacancy in the recording material layer and does not include oxygen.

[0009] In one example, the base substrate and the oxygen scavenger layer are of the same material and can form a single layer.

[0010] In one example, the base substrate and the oxygen scavenger layer may be semiconductor layers. In this case, the semiconductor layer may be an undoped semiconductor layer or a semiconductor layer doped with a dopant. In the latter case, an insulating layer may be provided at both ends of the doped semiconductor layer.

[0011] In one example, the base substrate and the oxygen scavenger layer are metal layers, and insulating layers may be provided at both ends of the metal layer.

[0012] In one example, the oxygen scavenger layer is a semiconductor layer doped with a dopant, and insulating layers may be provided at both ends thereof.

[0013] In one example, the oxygen scavenger layer may include a metal layer and may be provided with insulating layers at both ends.

[0014] In one example, the element may be a semiconductor element, and the oxygen scavenger layer may further include nitrogen (N).

[0015] In one example, the oxygen scavenger layer may include a first submaterial layer formed on the base substrate and a second submaterial layer formed on the first submaterial layer and in direct contact with the recording material layer. In one example, one of the first and second submaterial layers may be a layer containing a semiconductor component, and the other may be a metal layer. In one example, one of the first and second submaterial layers may be a semiconductor layer, and the other may be a nitride layer. One of the first and second submaterial layers may be a semiconductor layer doped with a dopant, and the other may be an undoped semiconductor layer. In one example, the layer containing the semiconductor component may further include nitrogen.

[0016] In one example, the base substrate is an insulating structure containing oxygen, and the oxygen scavenger layer may be a barrier configured to block oxygen from the base substrate from moving to the recording material layer.

[0017] In one example, a plurality of gate electrodes on the gate insulating layer are aligned in a first direction, and a separating layer is disposed between them to insulate them from each other.

[0018] In one example, the base substrate is cylindrical parallel to the first direction, and the oxygen scavenger layer, the recording material layer, the channel layer, and the gate insulating layer may be sequentially stacked on the cylindrical surface of the base substrate to surround the base substrate.

[0019] In one example, the base substrate, the oxygen scavenger layer, the recording material layer, the channel layer, the gate insulating layer, the gate electrode, and the separation layer are provided on a substrate including a doping region, and a laminate comprising the base substrate, the oxygen scavenger layer, the recording material layer, the channel layer, the gate insulating layer, and the channel layer is provided perpendicular to the surface of the substrate and has one end in contact with the doping region, and the gate electrode and the separation layer may be provided parallel to the substrate while surrounding the laminate. In one example, the other end of the laminate opposite the one end of the laminate is in contact with a drain region, and a bit line may be connected to the drain region.

[0020] In one example, the recording material layer may include one of a resistance change material and a phase change material.

[0021] An electronic device according to an exemplary embodiment may include a memory element according to the exemplary embodiment described above.

[0022] A method for manufacturing a memory device according to an exemplary embodiment comprises the steps of: forming a stacked structure by alternately and repeatedly depositing a sacrificial layer and a separation layer on a substrate; forming a channel hole penetrating the stacked structure; sequentially forming a gate insulating layer, a channel layer, a recording material layer, and an oxygen scavenger layer on the inner surface of the channel hole; filling the interior of the channel hole remaining after the oxygen scavenger layer is formed with a filling material; removing the sacrificial layer to form a gate hole; and depositing an electrode material on the gate hole, wherein the oxygen scavenger layer includes an element that creates an oxygen vacancy in the recording material layer and does not include oxygen.

[0023] In one example, after forming the gate insulating layer and the channel layer on the inner surface of the channel hole, the process may further include removing the insulating material and the channel material deposited on the bottom surface of the channel hole before forming the recording material layer.

[0024] In one example, the oxygen scavenger layer and the landfill material may be formed of the same material and may become a single layer.

[0025] In one example, the process of forming the oxygen scavenger layer may include the process of forming a first submaterial layer on the inner surface of the recording material layer and the process of forming a second submaterial layer on the inner surface of the first submaterial layer.

[0026] In one example, the oxygen scavenger layer may include a semiconductor layer.

[0027] In one example, the oxygen scavenger layer may include a metal layer and form an insulating layer at both ends in a direction perpendicular to the substrate.

[0028] In one example, the semiconductor layer is a silicon layer doped with a dopant or an undoped silicon layer, and when the semiconductor layer is the doped silicon layer, an insulating layer can be formed at both ends in a direction perpendicular to the substrate.

[0029] In one example, one of the first submaterial layer and the second submaterial layer may be a semiconductor layer, and the other may be a metal layer. In one example, one of the first submaterial layer and the second submaterial layer may be a semiconductor layer, and the other may be a nitride layer. In one example, one of the first submaterial layer and the second submaterial layer may be a doped silicon layer, and the other may be an undoped silicon layer.

[0030] In one example, the oxygen scavenger layer can be formed by the PEALD method.

[0031] In one example, the channel layer and the oxygen scavenger layer can be formed from the same material under the same conditions. Effects of the invention

[0032] In a memory device according to one embodiment, an oxygen scavenger layer is provided between a recording material layer (e.g., variable resistor oxide) and an insulating structure (e.g., SiO2). The oxygen scavenger layer may be a non-oxide material and may include a semiconductor layer (e.g., Si), a nitride layer (e.g., SiN), and / or a metal layer. As the oxygen scavenger layer is provided between the recording material layer and the insulating structure, oxygen from the recording material layer may move to the oxygen scavenger layer, thereby creating oxygen vacancies (voids) in the recording material layer. Furthermore, by providing the oxygen scavenger layer, oxygen from the insulating structure is prevented from moving to the recording material layer, thereby preventing a reduction in oxygen vacancies in the recording material layer.

[0033] The resistance change characteristics of the recording material layer can be affected by oxygen vacancies; however, by providing an oxygen scavenger layer between the recording material layer and the insulating structure, the resistance change characteristics of the recording material layer can be maintained normally without weakening. In other words, the resistance change of the recording material layer can occur smoothly under given operating conditions. Accordingly, the operation of the memory device can be stabilized even in environments with high integration density, and the reliability of the recorded information can also be enhanced. Brief explanation of the drawing

[0034] FIGS. 1 to 4 are cross-sectional views showing the schematic structure of a memory device according to an exemplary embodiment. Figure 5 is a graph showing the oxygen vacancy (vacancy) formation characteristics according to the contact material of the recording material layer included in a memory device according to an exemplary embodiment. Figure 6 shows an equivalent circuit for the memory elements of Figures 1 to 4. FIGS. 7 to 9 are drawings illustrating the write, read, and erase operations in the memory element of FIG. 1. FIGS. 10 to 14 are cross-sectional views showing the schematic configuration of a memory device according to another exemplary embodiment. FIG. 15 is a perspective view showing the schematic structure of a memory string provided in the memory element of FIG. 10. FIG. 16 is an equivalent circuit diagram for the memory elements of FIG. 10 to FIG. 14. FIGS. 17 to 25b are drawings illustrating a method for manufacturing a memory device according to an exemplary embodiment. FIG. 26 is a block diagram of a memory system according to an exemplary embodiment. FIG. 27 is a block diagram showing a neuromorphic device and an external device connected thereto according to an exemplary embodiment. Specific details for implementing the invention

[0035] Hereinafter, a memory device including a vertical stacking structure according to exemplary embodiments, a method for manufacturing the same, and an electronic device including the memory device will be described in detail with reference to the attached drawings. The described embodiments are merely exemplary, and various modifications are possible from these embodiments. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience of explanation.

[0036] In the following, terms described as "upper" or "upper" may include not only those directly above in contact, but also those above without contact.

[0037] Terms such as first, second, etc., may be used to describe various components, but are used solely for the purpose of distinguishing one component from another. These terms do not limit the difference in the material or structure of the components.

[0038] A singular expression includes a plural expression unless the context clearly indicates otherwise. Furthermore, when a part is said to "include" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0039] Additionally, terms such as “...part,” “module,” etc., as described in the specification refer to a unit that processes at least one function or operation, and this may be implemented in hardware or software, or as a combination of hardware and software.

[0040] The use of the term “above” and similar descriptive terms may apply to both the singular and plural forms.

[0041] Unless there is an explicit statement that the steps constituting the method must be performed in the described order, they may be performed in a suitable order. Furthermore, the use of all exemplary terms (e.g., etc.) is merely intended to describe the technical concept in detail and, unless limited by the claims, such terms do not limit the scope of the rights.

[0042] FIG. 1 shows a first memory element (100) according to an exemplary embodiment.

[0043] Referring to FIG. 1, the first memory element (100) comprises an insulating structure (210), a first oxygen scavenger layer (220) sequentially formed on the insulating structure (210), a recording material layer (230), a channel layer (240), a gate insulating layer (250), and a gate electrode (260) formed on the gate insulating layer (250), and includes a separation layer (270) provided on the gate insulating layer (250) between two adjacent gate electrodes (260). In one example, the separation layer (270) may be provided to cover the entire gate insulating layer (250) between the gate electrodes (260). The first oxygen scavenger layer (220), the recording material layer (230), the channel layer (240), and the gate insulating layer (250) may be sequentially stacked in a first direction (D1) and may be parallel to a second direction (D2). The first direction (D1) may be a direction perpendicular to the longitudinal direction of the insulating structure (210) or substantially perpendicular. The longitudinal direction of the insulating structure (210) may be parallel to the second direction (D2). The first and second directions (D1, D2) may be perpendicular to each other. In one example, a natural oxide film (235) may exist between the recording material layer (230) and the channel layer (240). The natural oxide film (235) may be a naturally formed silicon oxide that forms on the surface of the silicon-containing channel layer (240) after the channel layer (240) is formed during the manufacturing process of the first memory device (100). The natural oxide film (235) may also be formed by an oxidizing agent used in the deposition process of the recording material layer (230) performed after the channel layer (240) is formed. The thickness of the natural oxide film (235) is very thin compared to other material layers. Therefore, the natural oxide film (235) may not be shown in the attached drawings.

[0044] The first oxygen scavenger layer (220) exists on one side of the insulating structure (210) and may cover the entire one side. The one side of the insulating structure (210) may be a surface parallel to the second direction (D2). In the view of FIG. 1, the one side of the insulating structure (210) may be represented as the top surface of the insulating structure (210). However, in another view, the one side of the insulating structure (210) may be represented as a side surface or a bottom surface, etc., rather than a top surface. The insulating structure (210) may simply be represented as an insulating layer, an insulating structure, a base layer, a base substrate, etc. In one example, the insulating structure (210) may be an insulating oxide or may include an insulating oxide. In one example, the insulating oxide may include silicon oxide. In one example, the silicon oxide may include a SiO2 layer. In one example, the first oxygen scavenger layer (220) may be a semiconductor layer or may include a semiconductor layer. In one example, the semiconductor layer may be a layer containing a semiconductor of one component. In one example, the semiconductor layer may be a layer doped with a p-type or n-type dopant or an undoped layer. In one example, the semiconductor layer may be a doped or undoped silicon (Si) layer or may include such a silicon layer. In one example, the first oxygen scavenger layer (220) may include a component (element) (e.g., Si) that does not contain oxygen but has a relatively high reactivity to oxygen and can create oxygen vacancies in the recording material layer (230). In one example, the first oxygen scavenger layer (220) may be formed as an insulating layer containing said component. For example, the first oxygen scavenger layer (220) may be a silicon nitride layer (e.g., SiN) or may include a silicon nitride layer. In one example, the first oxygen scavenger layer (220) may be a metal oxide layer or may include a metal oxide layer. For example, the metal oxide layer may include an Al2O3 layer or a La2O3 layer.In one example, when the first oxygen scavenger layer (220) is provided between the recording material layer (230) and the insulating structure (210) as shown in FIG. 1, the thickness of the first oxygen scavenger layer (220) may be approximately 2 nm to 20 nm, but is not limited thereto.

[0045] The recording material layer (230) may cover the entire surface of the first oxygen scavenger layer (220) corresponding to the surface of the insulating structure (210). The corresponding surfaces (facing surfaces) of the recording material layer (230) and the first oxygen scavenger layer (220) may come into direct contact with each other. During the operation of the first memory element (100), some of the oxygen contained in the recording material layer (230) may be transferred to the first oxygen scavenger layer (220) through this contact. This oxygen transfer may be attributed to the combination of the oxygen in the recording material layer (230) and the components (e.g., Si) contained in the first oxygen scavenger layer (220).

[0046] Consequently, by providing the recording material layer (230) and the first oxygen scavenger layer (220) in contact with each other, oxygen vacancies in the recording material layer (230) can be created more easily than when the first oxygen scavenger layer (220) is not provided. In other words, by providing the first oxygen scavenger layer (220), a conductive filament can be easily formed in a designated area of ​​the recording material layer (230) during the operation of the first memory device (100). The oxygen vacancies may also be expressed as oxygen vacancies.

[0047] The recording material layer (230) is a layer in which resistance changes according to the applied voltage environment or a layer in which resistance switching occurs. Therefore, the recording material layer (230) may be described as a resistive change layer or a resistive switching (RS) layer.

[0048] Considering the above-mentioned operation of the first oxygen scavenger layer (220), the first oxygen scavenger layer (220) may be described as an oxygen vacancy generating layer. Additionally, as a result of the first oxygen scavenger layer (220) being provided, the oxygen vacancy of the recording material layer (230) increases; therefore, the first oxygen scavenger layer (220) may be described as a layer that increases oxygen vacancy (oxygen vacancy increasing layer) or a layer that increases oxygen vacancy concentration (oxygen vacancy concentration increasing layer).

[0049] The recording material layer (230) has a resistance change characteristic in which the resistance changes in a given area depending on the external voltage environment, and can be used as a layer for recording bit data 1 or 0, and the resistance change characteristic is related to the creation of oxygen vacancies within the recording material layer (230). That is, in order for the resistance change of the recording material layer (230) to occur smoothly, oxygen vacancies must be easily created in the recording material layer (230). Since the first oxygen scavenger layer (220) is provided, oxygen vacancies are easily created in the recording material layer (230), so the resistance change of the recording material layer (230) can occur smoothly. In this regard, the first oxygen scavenger layer (220) can be viewed as a layer that performs the role of maintaining the resistance change characteristics of the recording material layer (230) normally, and since the recording material layer (230) is a layer that records bit data, the operation of the first memory device (100) can be more stable and reliability can be increased.

[0050] The recording material layer (230) may include a variable resistance material. The variable resistance material is a material in which oxygen vacancies are formed by the behavior of oxygen occurring within the variable resistance material according to the applied voltage, and as a result, a conductive filament is formed. Depending on whether the conductive filament is formed, the variable resistance material may exhibit a low resistance state or a high resistance state, and such resistance state may indicate the recording of bit data '1' or '0'.

[0051] In one example, any one of Rb2O, TiO2, BaO, ZrO2, CaO, HfO2, SrO, Sc2O3, MgO, Li2O, Al2O3, SiO2, BeO, Sc2O3, Nb2O5, NiO, Ta2O5, WO3, V2O5, La2O3, Gd2O3, CuO, MoO3, Cr2O3, MnO2 may be used as the variable resistor material. Additionally, a structure in which two or more of the variable resistor materials are formed as multiple layers may be adopted as the recording material layer (230).

[0052] In one example, the recording material layer (230) may include a phase change material. A phase change material is a material that exhibits high resistance in an amorphous state and low resistance in a crystal state. This phase change can occur through Joule heating via electrical pulses. The phase change material may represent bit data '1' or '0' depending on the phase that appears in the phase change material. In one example, GST (Ge2Sb2Te5) may be used as the phase change material, and various chalgogenite materials such as Ga2Sb2Te5, InSbTe, and GeSeTe may also be used.

[0053] In the following description, a variable resistance material is used in the recording material layer (230) as an example, but the recording material layer (230) is not limited thereto.

[0054] The thickness of the recording material layer (230) may be in the range of 0.5 nm to 30 nm. In one example, the thickness of the recording material layer (230) may be approximately 0.5 nm to 20 nm.

[0055] In one example, the channel layer (240) may be made of a semiconductor material and may include, for example, polysilicon (poly-Si). The channel layer (240) may be doped with a predetermined dopant, for example, p-type doping. However, it is not limited thereto. The channel layer (240) may include, for example, materials such as Ge, IGZO, GaAs, etc. Source electrodes (S) and drain electrodes (D) as shown in FIG. 6 may be connected to both ends of the channel layer (240).

[0056] Furthermore, a plurality of separation layers (270) and gate electrodes (260) may be alternately arranged in a second direction (D2) on the gate insulating layer (250). That is, a plurality of separation layers (270) are arranged in a second direction (D2) on the gate insulating layer (250), and gate electrodes (260) are located between the plurality of separation layers (270). In one example, the two gate electrodes (260) shown are exemplary. Since one memory cell is formed as a unit of gate electrodes (260), gate electrodes (260) may be provided for as many memory cells as desired. In one example, the gate electrodes (260) in the second direction (D2) may have a length in the range of 5 nm to 30 nm. In one example, the separation layers (270) in the second direction (D2) may have a length in the range of 5 nm to 30 nm. In one example, the height of the gate electrode (260) and the height of the separation layer (270) on the gate insulating layer (250) may be the same. The region facing the gate electrode (260) in the recording material layer (230) may be a switching region in which the resistance may change depending on the applied voltage environment.

[0057] In one example, the gate insulating layer (250) may be made of various insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. In one example, a voltage to turn the channel layer (240) on / off may be selectively applied to the gate electrode (260).

[0058] FIG. 2 shows a second memory element (200) according to an exemplary embodiment. Only the parts different from FIG. 1 are described.

[0059] Referring to FIG. 2, the second memory device (200) includes a first oxygen scavenger layer (220), a recording material layer (230), a channel layer (240), and a gate insulating layer (250) that are sequentially stacked as a stack provided below a separation layer (270) and a gate electrode (260). The second memory device (200) does not include the insulating structure (210) of the first memory device (100). In the second memory device (200), the first oxygen scavenger layer (220) serves as the insulating structure (210) of the first memory device (100). Therefore, the thickness of the first oxygen scavenger layer (220) in the second memory device (200) may be thicker than the first oxygen scavenger layer (220) of the first memory device (100). In the case of Fig. 2, the thickness of the first oxygen scavenger layer (220) may be about 50 nm, but is not limited to this value, and the thickness may be increased or decreased as needed.

[0060] FIG. 3 shows a third memory element (300) according to an exemplary embodiment. Only the parts different from FIG. 1 are described.

[0061] Referring to FIG. 3, a second oxygen scavenger layer (320) is provided between an insulating structure (210) and a recording material layer (230). That is, the third memory device (300) includes an insulating structure (210), a second oxygen scavenger layer (320), a recording material layer (230), a natural oxide film (235), a channel layer (240), and a gate insulating layer (250) that are sequentially stacked. The arrangement relationship between the second oxygen scavenger layer (320) and the remaining material layers (210, 230, 235, 240, 250) in the third memory device (300) may be the same as the arrangement relationship between the first oxygen scavenger layer (220) and the remaining material layers (210, 230, 235, 240, 250) of the first memory device (100). However, the length of the second oxygen scavenger layer (320) in the second direction (D2) of the third memory element (300) may be shorter than the length of the first oxygen scavenger layer (220) of the first memory element (100). Insulating layers (325) are provided on both sides of the second oxygen scavenger layer (320) in the second direction (D2). Therefore, as shown in the equivalent circuit of FIG. 6, the source electrode (S) and drain electrode (D) provided on both sides of the gate electrodes (G1, G2) may be prevented from coming into direct contact with the second oxygen scavenger layer (320). In one example, the second oxygen scavenger layer (320) may be a metal layer or may include a metal layer.

[0062] FIG. 4 shows a fourth memory element (400) according to an exemplary embodiment. Only the parts different from FIG. 1 are described.

[0063] Referring to FIG. 4, the fourth memory element (400) includes a third oxygen scavenger layer (420) between an insulating structure (210) and a recording material layer (230). The third oxygen scavenger layer (420) includes first and second submaterial layers (420a, 420b) sequentially stacked in a first direction (D1) on the insulating structure (210). The third oxygen scavenger layer (420) may be a non-oxide layer or may include a non-oxide layer. In one example, the third oxygen scavenger layer (420) may be a semiconductor layer or may include a semiconductor layer, said semiconductor layer may be a pure semiconductor layer or a semiconductor layer doped with a dopant. In one example, one of the first and second submaterial layers (420a, 420b) may be a layer doped with a dopant, and the other may be an undoped layer not doped with a dopant. In one example, one of the first and second submaterial layers (420a, 420b) may be an undoped silicon layer, and the other may be a silicon layer doped with a p-type or n-type dopant, but is not limited thereto. In one example, the third oxygen scavenger layer (420) may be formed as an insulating layer containing a component (e.g., Si) that does not contain oxygen but has a relatively high reactivity to oxygen. For example, the third oxygen scavenger layer (420) may be a silicon nitride layer (e.g., SiN) or may include a silicon nitride layer. In one example, one of the first and second submaterial layers (420a, 420b) may be a doped or undoped silicon layer, and the other may be a silicon nitride layer. In one example, the third oxygen scavenger layer (420) may be a metal oxide layer or may include a metal oxide layer. For example, the metal oxide layer may include an Al2O3 layer or a La2O3 layer. In one example, one of the first and second submaterial layers (420a, 420b) is a layer selected from the group consisting of a doped silicon layer, an undoped silicon layer, a silicon nitride layer, and a metal oxide layer, and the remainder may be another layer selected from the group.

[0064] The third oxygen scavenger layer (420) has been exemplified as comprising two sub-material layers (420a, 420b), but is not limited thereto.

[0065] The first to fourth memory elements (100, 200, 300, 400) may have a structure in which a plurality of memory cells are arrayed, and as shown in the equivalent circuit of FIG. 6, they may be in a form in which a transistor and a variable resistor are connected in parallel. Each variable resistor is set by the voltage applied to the gate electrodes (G1, G2) and the voltage between the source electrode (S) and the drain electrode (D), and may have a value corresponding to information of 1 or 0.

[0066] FIG. 5 shows the results of an X-ray Photoelectron Spectroscopy (XPS) experiment performed to verify whether oxygen vacancies are created in the recording material layer when an oxygen scavenger layer (220, 320, 420) is provided to be in contact with the recording material layer (230) in a memory device according to an exemplary embodiment.

[0067] In the experiment to obtain the results of Fig. 5, a silicon layer (p++ silicon substrate) doped with an oxygen scavenger layer (220) was used, and HfO2 was used as the recording material layer (230).

[0068] The above experiment was conducted on a first sample (comparison memory device) in which the oxygen scavenger layer (220) is in direct contact with the recording material layer (230), and a second sample (control memory device) in which the oxygen scavenger layer (220) and the silicon oxide are in direct contact with the silicon oxide by providing silicon oxide (SiO2) between the oxygen scavenger layer (220) and the recording material layer (230). The second sample may correspond to a conventional memory device in which the insulating structure (SiO2) (210) and the recording material layer (HfO2) (230) are in direct contact.

[0069] In Figure 5, the horizontal axis represents binding energy, and the vertical axis represents the photoelectron intensity emitted from the sample by X-ray irradiation.

[0070] In FIG. 5, the first graph (5G1) shows the results for the first sample, and the second graph (5G2) shows the results for the second sample.

[0071] Comparing the first and second graphs (5G1, 5G2) of FIG. 5, when the recording material layer (HfO2) (230) is in contact with the doped silicon layer (oxygen scavenger layer (220)) (5G1), the Hf 4f peak is shifted toward a relatively lower binding energy compared to when the recording material layer (HfO2) (230) is in contact with silicon oxide (SiO2) (5G2).

[0072] These results suggest that oxygen defects, namely oxygen vacancies, are created in the recording material layer (230) by the direct contact between the oxygen scavenger layer (220) and the recording material layer (230), and that the oxygen scavenger layer (220) in contact with the recording material layer (230) literally acts as an oxygen scavenger for the recording material layer (230).

[0073] Additionally, when compared to the first graph (5G1), the Hf 4f peak of the second graph (5G2) can be seen as shifted toward an increase in binding energy. This result suggests that as the recording material layer (230) comes into direct contact with silicon oxide (SiO2), oxygen moves from the silicon oxide (SiO2) to the recording material layer (HfO2) (230), thereby reducing the oxygen vacancies in the recording material layer (HfO2) (230). In other words, this result suggests that the oxidation number of hafnium (Hf) in the recording material layer (HfO2) (230) increases.

[0074] An example of an insulating structure (210) in the memory elements (100, 300, 400) of FIGS. 1, FIGS. 3 and FIGS. 4 includes silicon oxide (SiO2). An oxygen scavenger layer (220) disposed between the insulating structure (210) and the recording material layer (230) to prevent direct contact between the insulating structure (210) and the recording material layer (230) consequently acts as a barrier to prevent oxygen from moving from the insulating structure (210) to the recording material layer (230).

[0075] FIGS. 7 to 9 show the write, read, and erase operations of the first to fourth memory elements (100, 200, 300, 400) of FIGS. 1 to 4.

[0076] FIG. 7 shows the case where the memory cell on the left is not selected as a write cell, and the memory cell on the right is selected as a write cell. Accordingly, a gate voltage (Von) for channel ON is applied to the gate electrode (260) on the left, and a gate voltage (Voff) for channel OFF is applied to the gate electrode (260) on the right. A write voltage (V) is applied across the ends of the channel layer (240). program When ) is applied, current (240e) flows along the channel layer (240) in the memory cell (left) in the channel-on state, whereas current cannot flow along the channel layer (240) in the memory cell (right) in the channel-off state. In this case, a strong voltage is applied across the region of the channel layer (240) where current cannot flow, and due to the influence of the electric field caused by this voltage, the resistance state of the recording material layer (230) changes to a low resistive state (LRS). Thus, the write operation is completed. This change in the resistance state indicates that bit data 1 or 0 has been written to the selected memory cell. In other words, due to the voltage applied across the region of the channel layer (240) where current cannot flow, the switching region (A) of the recording material layer (230) corresponding to the gate electrode (260) on the rightsw The resistance state of ) is switched, and information is recorded.

[0077] Consequently, in the case of FIG. 7, in the selected memory cell (memory cell in a channel-off state), current does not flow through the channel layer (240) but flows through the recording material layer (230).

[0078] Referring to FIG. 8, the left cell is a non-selected cell, and a voltage (Von) for channel ON is applied to the gate electrode (260), and the right cell is a selected cell, and a voltage (Voff) for channel OFF is applied to the gate electrode (260). For a read operation, a switching region (A sw A read voltage (V) such that the resistance state of ) does not change read ) is applied to both ends of the channel layer (240). In the right cell with the channel turned off, current does not flow into the channel layer (240) but flows through the recording material layer (230), and the resistance state of the cell can be read by measuring the current. That is, the recorded bit data can be read.

[0079] Referring to FIG. 9, to erase the information recorded in the right cell, an erase voltage (V) is applied such that current flows in the opposite direction to that during recording. erase ) is applied. The left cell is a non-selected cell, and a voltage (Von) for channel ON is applied to the gate electrode (260), and the right cell is a selected cell, and a voltage (Voff) for channel OFF is applied to the gate electrode (260). In the right cell with the channel OFF, current does not flow to the channel layer (240), but flows to the recording material layer (230) in the opposite direction to when recording, and the switching region (A sw The resistance state of ) is switched. That is, upon the application of the erase voltage (Verase), the resistance state of the switching region (Asw) is restored to its original state before the information was written.

[0080] FIGS. 10 to 14 show the schematic structure of the 5th to 9th memory elements (500, 600, 700, 800, 900) according to other embodiments, and FIG. 15 shows the schematic structure of a memory string provided in the 5th to 9th memory elements (500, 600, 700, 800, 900) of FIGS. 10 to 14 in three dimensions. FIG. 16 is an equivalent circuit diagram for the memory elements (500, 600, 700, 800, 900) of FIGS. 10 to 14.

[0081] The 5th to 9th memory elements (500, 600, 700, 800, 900) illustrated in FIGS. 10 to 14 are vertical NAND (VNAND) memories in which a plurality of memory cells (MC) are arranged in a vertical direction. The 5th to 9th memory elements (500, 600, 700, 800, 900) may be Pc-VNAND using a phase change material or Re-VNAND using a variable resistor material.

[0082] The 5th to 9th memory elements (500, 600, 700, 800, 900) may differ only in the stacking configuration inside the recording material layer (530), and the rest may be identical to each other.

[0083] Specifically, as illustrated in FIG. 10, the fifth memory element (500) includes an insulating structure (510) and an oxygen scavenger layer (515) that are sequentially stacked in a direction parallel to the substrate (520) (X-axis direction) inside the recording material layer (530). As illustrated in FIG. 11, the sixth memory element (600) is filled only with an oxygen scavenger layer (515) inside the recording material layer (530). In the sixth memory element (600), the oxygen scavenger layer (515) may be an undoped semiconductor layer (e.g., a Si layer). As illustrated in FIG. 12, the seventh memory element (700) is filled with an oxygen scavenger layer (615) and an insulating layer (620) inside the recording material layer (530). The oxygen scavenger layer (615) of the seventh memory element (700) may be a semiconductor layer (e.g., a Si layer) doped with a dopant. An insulating layer (620) is provided at the bottom and top of the oxygen scavenger layer (615), which is formed parallel to the recording material layer (530) in a direction perpendicular to the substrate (520) (Z-axis direction). The insulating layer (620) is provided between the bottom of the oxygen scavenger layer (615) and the substrate (520), and between the top of the oxygen scavenger layer (615) and the drain region (680). Accordingly, direct contact between the doped oxygen scavenger layer (615) in the seventh memory element (700) and the substrate (520) and the drain region (680) can be prevented. In the case of the eighth memory element (800), as illustrated in FIG. 13, the oxygen scavenger layer (515) disposed between the recording material layer (530) and the insulating structure (510) includes first and second submaterial layers (515a, 515b) that are sequentially stacked in a direction parallel to the substrate (520) (a direction parallel to the X-axis). In one example, the role and material of the first and second submaterial layers (515a, 515b) may be the same as the first and second submaterial layers (420a, 420b) of the fourth memory element (400) of FIG. 4.As illustrated in FIG. 14, the ninth memory element (900) includes an oxygen scavenger layer (815) formed as a metal layer parallel to the recording material layer (530) in the longitudinal direction of the recording material layer (530) between the recording material layer (530) and the insulating structure (510). The length of the oxygen scavenger layer (815) may be shorter than that of the recording material layer (530). An insulating layer (820) exists between the top of the oxygen scavenger layer (815) and the drain region (680), and between the bottom of the oxygen scavenger layer (815) and the substrate (520). Thus, direct contact between the oxygen scavenger layer (815), which is a metal layer, and the substrate (520) and the drain region (680) can be prevented. In one example, the insulating layer (820) may be an oxide layer or a nitride layer. The oxide layer may be an oxide layer that does not contain metal or a metal oxide layer.

[0084] Referring to FIGS. 10 to 16 together, the common detailed configuration of the 5th to 9th memory elements (500, 600, 700, 800, 900) is as follows.

[0085] A plurality of cell strings (CS) are provided on the substrate (520).

[0086] The substrate (520) may include a silicon material doped with a first type impurity. For example, the substrate (520) may include a silicon material doped with a p-type impurity. For example, the substrate (520) may be a p-type well (e.g., a pocket p-well). Hereinafter, it is assumed that the substrate (520) is p-type silicon. However, the substrate (520) is not limited to p-type silicon.

[0087] A doping region (525), which is a source region, is provided on the substrate (520). The doping region (525) may be of an n-type different from the substrate (520). Hereinafter, the doping region (525) is assumed to be of an n-type. However, the doping region (525) is not limited to an n-type. Such a doping region (525) may be connected to a common source line (CSL).

[0088] As shown in the circuit diagram of FIG. 16, k*n cell strings (CS) may be provided and arranged in a matrix form, and each row and column position may be named CSij (1≤i≤k, 1≤j≤n). Each cell string (CSij) is connected to a bit line (BL), a string select line (SSL), a word line (WL), and a common source line (CSL).

[0089] Each cell string (CSij) includes memory cells (MC) and string select transistors (SST). The memory cells (MC) and string select transistors (SST) of each cell string (CSij) can be stacked in the height direction.

[0090] Rows of multiple cell strings (CS) are each connected to different string select lines (SSL1 to SSLk). For example, string select transistors (SSTs) of cell strings (CS11 to CS1n) are connected in common to string select line (SSL1). String select transistors (SSTs) of cell strings (CSk1 to CSkn) are connected in common to string select line (SSLk).

[0091] The columns of multiple cell strings (CS) are each connected to different bit lines (BL1 to BLn). For example, the memory cells and string select transistors (SST) of the cell strings (CS11 to CSk1) can be connected in common to the bit line (BL1), and the memory cells (MC) and string select transistors (SST) of the cell strings (CS1n to CSkn) can be connected in common to the bit line (BLn).

[0092] Rows of multiple cell strings (CS) can each be connected to different common source lines (CSL1 to CSLk). For example, string select transistors (SST) of cell strings (CS11 to CS1n) can be commonly connected to the common source line (CSL1), and string select transistors (SST) of cell strings (CSk1 to CSkn) can be commonly connected to the common source line (CSLk).

[0093] The gate electrodes of memory cells (MCs) located at the same height from the substrate (520) or string select transistors (SST) are commonly connected to one word line (WL), and the gate electrodes of memory cells (MCs) located at different heights can be connected to different word lines (WL1~WLm), respectively.

[0094] The illustrated circuit structure is exemplary. For example, the number of rows of cell strings (CS) may be increased or decreased. As the number of rows of cell strings (CS) changes, the number of string select lines connected to the rows of cell strings (CS), and the number of cell strings (CS) connected to a single bit line may also change. As the number of rows of cell strings (CS) changes, the number of common source lines connected to the rows of cell strings (CS) may also change.

[0095] The number of columns of cell strings (CS) can also be increased or decreased. As the number of columns of cell strings (CS) changes, the number of bit lines connected to the columns of cell strings (CS) and the number of cell strings (CS) connected to one string selection line can also be changed.

[0096] The height of the cell string (CS) can also be increased or decreased. For example, the number of memory cells (MC) stacked in each cell string (CS) can be increased or decreased. As the number of memory cells (MC) stacked in each cell string (CS) changes, the number of word lines (WL) can also change. For example, the string select transistors provided in each cell string (CS) can be increased. As the number of string select transistors provided in each cell string (CS) changes, the number of string select lines or common source lines can also change. If the number of string select transistors increases, the string select transistors can be stacked in the same form as the memory cells (MC).

[0097] For example, writing and reading can be performed in units of rows of cell strings (CS). Cell strings (CS) can be selected in units of one row by common source lines (CSL), and cell strings (CS) can be selected in units of one row by string selection lines (SSL). Additionally, at least two common source lines (CSL) can be voltaged as a single unit. The common source lines (CSL) can be voltaged as a whole as a single unit.

[0098] In a selected row of cell strings (CS), writing and reading can be performed in units of pages. A page may be a row of memory cells connected to a single word line (WL). In a selected row of cell strings (CSs), memory cells may be selected in units of pages by word lines (WLs).

[0099] As illustrated in FIG. 10 and FIG. 13 to 15, the cell string (CS) may have a form in which a plurality of gate electrodes (560) and a plurality of separation layers (570) alternately surround a first structure comprising an insulating structure (510), an oxygen scavenger layer (515, 815), a recording material layer (530), a native oxide film (535), a channel layer (540), and a gate insulating layer (550), or a second structure comprising an oxygen scavenger layer (515, 615), a recording material layer (530), a native oxide film (535), a channel layer (540), and a gate insulating layer (550), which is provided to also serve as an insulating structure as illustrated in FIG. 11 and 12. In FIG. 15, the cell string (CS) is illustrated in the form of a rectangular prism, but this is exemplary and not limited thereto. The cell string (CS) may also be formed in a cylindrical shape, for example. For the convenience of the city, the natural oxide film (535) is not shown in Fig. 15.

[0100] Let us examine the shape of the first structure including an insulating structure (510), an oxygen scavenger layer (515, 815), a recording material layer (530), a natural oxide film (535), a channel layer (540), and a gate insulating layer (550).

[0101] For example, referring to FIG. 10, the insulating structure (510) is in the shape of a cylinder with the longitudinal direction being the Z-axis direction, and an oxygen scavenger layer (515, 815), a recording material layer (530), a natural oxide film (535), a channel layer (540), and a gate insulating layer (550) are sequentially stacked in the radial direction on the flat surface of the cylinder.

[0102] Let us examine the shape of a second structure including an oxygen scavenger layer (615) that also serves as an insulating structure, a recording material layer (530), a natural oxide film (535), a channel layer (540), and a gate insulating layer (550).

[0103] For example, referring to FIG. 11, the oxygen scavenger layer (515), which also serves as an insulating structure, is in the shape of a cylinder with the length direction being the Z-axis direction, and a recording material layer (530), a natural oxide film (535), a channel layer (540), and a gate insulating layer (550) are sequentially stacked in the radial direction on the flat surface of the cylinder.

[0104] In the case of FIG. 11, the inside of the recording material layer (530) is filled with an oxygen scavenger layer (515), and the oxygen scavenger layer (515) may be an undoped semiconductor layer (e.g., a Si layer). In this case, the recording material layer (530) extends between the oxygen scavenger layer (515) and the substrate (520) to prevent the oxygen scavenger layer (515) from coming into contact with the substrate (520).

[0105] In one example, the recording material layer (530) includes a variable resistance material or a phase change material. As the variable resistance material, any one of Rb2O, TiO2, BaO, ZrO2, CaO, HfO2, SrO, Sc2O3, MgO, Li2O, Al2O3, SiO2, BeO, Sc2O3, Nb2O5, NiO, Ta2O5, WO3, V2O5, La2O3, Gd2O3, CuO, MoO3, Cr2O3, MnO2 may be used. As the phase change material, GST (Ge2Sb2Te5) may be used.

[0106] In one example, the channel layer (540) may include a semiconductor material doped with a first type. The channel layer (540) may include a silicon material doped with the same type as the substrate (520), and for example, if the substrate (520) includes a silicon material doped with a p-type, the channel layer (540) may also include a silicon material doped with a p-type. Alternatively, the channel layer (540) may include a material such as Ge, IGZO, GaAs, etc.

[0107] The gate insulating layer (550) surrounds the surface of the channel layer (540) with a predetermined thickness. The gate insulating layer (550) may be made of various insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0108] A plurality of gate electrodes (560) and a plurality of separation layers (570) surround the outer surface of the structure. Specifically, the plurality of gate electrodes (560) and the plurality of separation layers (570) are provided on the outer surface of the gate insulating layer (550) and are arranged to surround the outer surface of the gate insulating layer (550). The plurality of separation layers (570) are intended to separate the plurality of gate electrodes (560), and the plurality of gate electrodes (560) and the plurality of separation layers (570) can be stacked intersecting each other in a direction perpendicular to the substrate (520) (Z direction).

[0109] The gate electrode (560) may be made of a metallic material or a highly doped silicon material. Each gate electrode (560) is connected to one of the word line (WL) or string select line (SSL). The isolation layer (570) may be made of various insulating materials such as silicon oxide, silicon nitride, etc.

[0110] The manufacturing process of the cell string (CS) described above can proceed in the order from the external structure to the internal structure. That is, a structure in which a gate electrode (560) and a separation layer (570) in the shape of a cylinder shell with the same outer and inner diameters are cross-stacked is formed first, and a gate insulating layer (550), a channel layer (540), a recording material layer (530), and an oxygen scavenger layer (515, 615, 815) can be sequentially deposited on the inner surface thereof. A natural oxide film (535) can be naturally formed on the inner surface of the channel layer (540) after the channel layer (540) is formed, and the deposition process of the recording material layer (530) can also influence the formation of the natural oxide film (535). The deposition of the above material layers will be described later in the description of the manufacturing method.

[0111] One end of the channel layer (540) and the recording material layer (530) may be in contact with the doping region (525), i.e., the common source region. A drain region (680) may be provided at the other end of the channel layer (540) and the recording material layer (530). The drain region (680) may include a silicon material doped with a second type. For example, the drain region (680) may include a silicon material doped with n type. A bit line (590) may be provided on the drain region (680). The drain region (680) and the bit line (590) may be connected via contact plugs.

[0112] Each gate electrode (560) and the regions of the gate insulating layer (550), channel layer (540), recording material layer (530), and oxygen scavenger layer (515, 615, 815) facing it can form a memory cell (MC). That is, the memory cell (MC) has a circuit structure in which a transistor including the gate electrode (560), the gate insulating layer (550), and the channel layer (540) and a variable resistor formed by the recording material layer (530) and the oxygen scavenger layer (515, 615, 815) are connected in parallel. This parallel connection structure is arranged continuously in the vertical direction (Z direction) to form a cell string (CS). And, as shown in the circuit diagram of FIG. 16, a common source line (CSL) and a bit line (BL) can be connected to both ends of the cell string (CS). By applying operating voltage to the common source line (CSL) and the bit line (BL), various operations, such as program (write), read, and erase operations, can be performed on multiple memory cells (MC).

[0113] For example, when a memory cell (MC) to be recorded is selected, the gate voltage value of the selected cell is adjusted so that a channel is not formed in the selected cell, i.e., the channel is turned off, and the gate voltage values ​​of the unselected cells are adjusted so that the channels are turned on in the unselected cells. Accordingly, the current path caused by the voltage applied to the common source line (CSL) and the bit line (BL) passes through the recording material layer (530) region of the selected memory cell (MC), and at this time, the applied voltage is V set or V reset A low resistance state or a high resistance state can be created by using a value, and desired 1 or 0 information can be written to the selected memory cell (MC).

[0114] In a read operation, similarly, a read can be performed on the selected cell. That is, after the gate voltage applied to each gate electrode (560) is adjusted so that the selected memory cell (MC) is channel off and the unselected memory cells are channel on, the applied voltage (V) between the common source line (CSL) and the bit line (BL) read The cell state (1 or 0) can be checked by measuring the current flowing through the corresponding cell (MC) by ).

[0115] In this VNAND structure, there is a limit to increasing the number of gate electrodes (560) included in the cell string (CS) due to packaging limitations based on the height of the cell string (CS). In particular, there is a limit to reducing the distance between adjacent gate electrodes (560) due to interference between adjacent cells. Accordingly, the memory capacity is limited by the limit value that can reduce the sum of the vertical lengths of adjacent gate electrodes (560) and the separation layer (570) in the vertical direction (Z direction).

[0116] As described above, the 5th to 9th memory elements (500, 600, 700, 800, 900) according to the embodiment are provided with an oxygen scavenger layer (515, 615, 815) that is in direct contact with the recording material layer (530) on the inner surface of the recording material layer (530). Accordingly, during the operation of the memory element, the creation of oxygen vacancies in the recording material layer (530) can be facilitated, and the inflow of an element (e.g., oxygen) that reduces oxygen vacancies in the recording material layer (530) from the inside of the recording material layer (530) can be prevented. Accordingly, the resistance change operation of the recording material layer (530) can be performed normally and stably. These results can help improve the integration density and reliability of the memory element.

[0117] FIGS. 17 to 25b show a step-by-step method for manufacturing a memory device according to an exemplary embodiment. Some drawings are divided into a and b, where a represents a cross-sectional view and b represents a plan view.

[0118] First, referring to FIG. 17, a stacked structure is formed by alternately stacking a separation layer (570) and a sacrificial layer (580) on a substrate (520). In one example, the substrate (520) may be a silicon substrate, for example, a silicon substrate doped with a predetermined impurity. The substrate (520) may be a p-type silicon substrate, but is not limited thereto.

[0119] The separation layer (570) is made of an insulating material and may include, for example, SiO2. The sacrificial layer (580) is a layer for forming a recess structure to form a channel layer of a curved path and a recording material layer, and is made of a material with a different etching ratio from the material of the separation layer (570). The separation layer (570) is, for example, SiN xIt may include. The thickness of the separation layer (570) and the thickness of the sacrificial layer (580) may be determined according to the detailed structure of the memory device to be manufactured. The thickness of the separation layer (570) and the thickness of the sacrificial layer (580) may correspond to the spacing between gate electrodes and the length of the gate electrode of the memory device to be manufactured, respectively. In one example, the thickness of the sacrificial layer (580) may have a range of 5 nm to 30 nm. In one example, the thickness of the separation layer (570) may be formed in a range of 5 nm to 30 nm. A gate electrode is formed at the location of the sacrificial layer (580), that is, the number of sacrificial layers (580) corresponds to the number of unit cells of the memory device to be manufactured.

[0120] For the formation of the separation layer (570) and the sacrificial layer (580), deposition methods such as atomic layer deposition (ALD), metal organic atomic layer deposition (MOALD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), and physical vapor deposition (PVD) may be used. These methods include the process of placing a substrate (520) in a chamber, heating the chamber to a predetermined temperature, and supplying a source, and the process conditions of temperature and time are controlled according to the desired thickness.

[0121] Next, as illustrated in FIGS. 18a and 18b, channel holes (HO_CH) are formed in the stacked structure of FIG. 17. The channel holes (HO_CH) are holes for applying a gate insulating material, a channel material, a recording material, an oxygen scavenger material, etc. Photolithography and etching processes may be used to form the channel holes (HO_CH). Although the number of channel holes (HO_CH) is shown as two, this is exemplary. For example, channel holes (HO_CH) can be formed as many times as the number of cell strings (CS) described in FIGS. 10 to 16.

[0122] Next, as illustrated in FIG. 19, a gate insulating layer (550), a channel layer (540), a recording material layer (530), and an oxygen scavenger layer (515) are sequentially formed on the inner surface of the channel hole (HO_ch). At this time, a natural oxide film (SiO2) (535) may be formed on the inner surface of the channel layer (540). Additionally, when forming the recording material layer (530), a natural oxide film may be added to the inner surface of the channel layer (540) by an oxidizing agent (e.g., O3, H2O, etc.) used. In one example, a process to remove or reduce the natural oxide film (535) may be performed before forming the recording material layer (430). The gate insulating layer (550) may be made of various insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The channel layer (540) may be made of a semiconductor material and may include, for example, poly-Si. The channel layer (540) may be doped with a predetermined dopant and may be doped in the same p-type as the substrate (520). However, it is not limited thereto. The channel layer (540) may include materials such as, for example, Ge, IGZO, GaAs, etc. The recording material layer (530) may include a variable resistor material or a phase change material. Any one of Rb2O, TiO2, BaO, ZrO2, CaO, HfO2, SrO, Sc2O3, MgO, Li2O, Al2O3, SiO2, BeO, Sc2O3, Nb2O5, NiO, Ta2O5, WO3, V2O5, La2O3, Gd2O3, CuO, MoO3, Cr2O3, MnO2 may be used as the variable resistor material. GST (Ge2Sb2Te5) may be used as the phase change material.

[0123] The oxygen scavenger layer (515) may be a semiconductor layer or may include a semiconductor layer. In one example, when forming the semiconductor layer, a dopant may be doped or may not be doped. The dopant may be p-type or n-type. The semiconductor layer may include silicon. In one example, the oxygen scavenger layer (515) may be a metal layer comprising one component metal or two or more components metal, or may include such a metal layer. In one example, the oxygen scavenger layer (515) may be formed as a plurality of layers (515a, 515b) as shown in FIG. 13. In one example, the oxygen scavenger layer (515) may be formed as an insulating layer comprising a component (e.g., Si) that does not contain oxygen but has a relatively high reactivity to oxygen. For example, the oxygen scavenger layer (515) may be a silicon nitride layer (e.g., SiN) or may include a silicon nitride layer. In one example, the oxygen scavenger layer (515) may be a metal oxide layer or may include a metal oxide layer. In one example, the metal oxide layer may include an Al2O3 layer or a La2O3 layer.

[0124] If the oxygen scavenger layer (515) is formed as a doped semiconductor layer or metal layer, or as a conductive metal oxide layer and has conductivity, the top and bottom of the oxygen scavenger layer (515) may be insulated, or an insulating layer may be further formed on the top and bottom. In this way, direct contact between the oxygen scavenger layer (515) and the substrate (520) can be prevented, and direct contact between the oxygen scavenger layer (515) and the drain region (680) formed in a subsequent process can also be prevented.

[0125] If the oxygen scavenger layer (515) is formed from the same material (e.g., Si) as the channel layer (540), the formation conditions of the channel layer (540) can be applied to the formation of the oxygen scavenger layer (515), so the manufacturing process of the memory device may be simplified.

[0126] To form the above material layers (550, 540, 530, 515), deposition methods such as ALD, MOALD, CVD, MOCVD, PVD, and Plasma Enhanced ALD (PEALD) may be used. These methods include the process of placing a stacked structure with channel holes (HO_ch) formed therein in a chamber, heating the chamber to a predetermined temperature, and supplying a source, wherein process conditions of temperature and time are controlled according to the desired thickness for each layer.

[0127] Meanwhile, when using the PEALD method, plasma damage may occur, and such plasma damage may cause oxygen vacancies to form in the recording material layer (530). Therefore, when the oxygen scavenger layer (515) is formed using the PEALD method, it may be easier to create oxygen vacancies in the recording material layer (530) and relatively many oxygen vacancies may be created.

[0128] Before forming a gate insulating layer (550) and a channel layer (540) on the inner side of the channel hole (HO_ch) and forming a recording material layer (530), a process of removing the insulating material and channel material deposited on the bottom surface of the channel hole (HO_ch) can be performed.

[0129] Next, an insulating structure (510) is formed in the remaining space inside the channel hole (HO_ch) as shown in FIG. 20a and FIG. 20b. The remaining space inside the channel hole (HO_ch) can be completely filled with the insulating structure (510). When the remaining space inside the channel hole (HO_ch) is filled with the insulating structure (510) and an oxygen scavenger layer (515) is formed between the insulating structure (510) and the recording material layer (530) as shown in FIG. 20a, the thickness of the oxygen scavenger layer (515) may be approximately 2 nm to 20 nm.

[0130] In one example, the remaining space inside the channel hole (HO_ch) may be filled with an oxygen scavenger layer (515) instead of being filled with an insulating structure (510). In this case, the recording material layer (530) may be formed to extend between the substrate (520) and the oxygen scavenger layer (515) as shown in FIG. 22. In this way, when the remaining space inside the channel hole (HO_ch) is filled with an oxygen scavenger layer (515) instead of an insulating structure (510), direct contact between the oxygen scavenger layer (515) and the substrate (520) can be prevented. In this way, when the remaining space inside the oxygen channel hole (HO_ch) is filled with an oxygen scavenger layer (515) instead of being filled with an insulating structure (510) (see FIG. 11), the thickness in the direction parallel to the X-axis of the oxygen scavenger layer (515), that is, the diameter of the oxygen scavenger layer (515), may be about 50 nm, but is not limited to this.

[0131] Exemplary materials capable of filling the remaining space inside the channel hole (HO_ch) may be collectively referred to as landfill materials.

[0132] Next, as shown in FIG. 21, the structure shown in FIG. 20a is etched and cut.

[0133] Next, the remaining sacrificial layer (580) is removed to form a gate hole (HO_ga) as shown in FIG. 22, and an electrode material is deposited on the gate hole (HO_ga) to form a gate electrode (560) as shown in FIG. 23. In this way, two string cells (CS) are formed on the substrate (520).

[0134] Next, as illustrated in FIG. 24a and FIG. 24b, a common source region (525) is formed on the substrate (520). This is a process of creating a high-concentration region by injecting a dopant into a predetermined region on the substrate (510), and the common source region (525) is formed in contact with the channel layer (240), recording material layer (230), and oxygen scavenger layer (515) of one end of the two string cells (CS).

[0135] In the process of forming the recording material layer (230), if the recording material layer (230) is formed to cover the bottom surface of the channel hole (HO_ch), the bottom of the oxygen scavenger layer (515) formed after the recording material layer (230) is formed may not come into contact with the substrate (520). Therefore, in this case, the common source region (525) may be formed to come into contact with the channel layer (240) and the recording material layer (230) at one end of the two string cells (CS).

[0136] Next, as illustrated in FIG. 25a and FIG. 25b, a drain region (680) is formed that is connected to the other end (e.g., top) of the channel layer (240), recording material layer (230), and oxygen scavenger layer (515) opposite the other end (e.g., bottom) of the channel layer (240), recording material layer (230), and oxygen scavenger layer (515) that is in contact with the common source region (525), and a bit line (590) connecting the drain region (680) is formed.

[0137] Each memory element (100, 200...900) according to the present disclosure can be adopted as a memory system of various electronic devices. Each memory element (100, 200...900) can be implemented as a chip-type memory block and used as a neuromorphic computing platform, or can be used to construct a neural network.

[0138] FIG. 26 is a block diagram of a memory system according to an embodiment.

[0139] Referring to FIG. 26, the memory system (1600) may include a memory controller (1601) and a memory device (1602). The memory controller (1601) performs control operations on the memory device (1602), and, for example, the memory controller (1601) provides an address (ADD) to the memory device (1602) and a command (CMD) for performing programming (or writing), reading, and / or erasing operations on the memory device (1602). Additionally, data for programming operations and reading data may be transferred between the memory controller (1601) and the memory device (1602).

[0140] The memory device (1602) may include a memory cell array (1610) and a voltage generator (1620). The memory cell array (1610) may include a plurality of memory cells arranged in an area where a plurality of word lines and a plurality of bit lines intersect each other. The memory cell array (1610) includes one of the memory elements based on the embodiments of FIGS. 1 to 4 and FIGS. 10 to 14.

[0141] The memory controller (1601) may include a processing circuit, such as hardware including logic circuits; a combination of hardware / software, such as processor execution software; or a combination thereof. For example, the processing circuit may include, more specifically, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), but is not limited thereto. The memory controller (1601) may be configured to operate in response to a request from a host (not shown) and to convert the memory controller (1601) into a special purpose controller by accessing the memory device (1602) and controlling the control operations discussed above (e.g., write / read operations). The memory controller (1601) may generate an address (ADD) and a command (CMD) for performing programming / read / erase operations on the memory cell array (1610). Additionally, in response to a command from the memory controller (1601), the voltage generator (1620) (e.g., power circuit) can generate a voltage control signal to control the voltage level of a word line for data programming or data reading in the memory cell array (1610).

[0142] Additionally, the memory controller (1601) may perform a determination operation on data read from the non-volatile memory device (1602). For example, the number of on-cells and / or off-cells may be determined from the data read from the memory cells. The memory device (1602) may provide a pass / fail signal (P / F) to the memory controller (1601) based on the result of reading the data. The memory controller (1601) may control the write and read operations of the memory cell array (1610) by referring to the pass / fail signal (P / F).

[0143] FIG. 27 is a block diagram showing a neuromorphic device and an external device connected thereto according to an exemplary embodiment.

[0144] Referring to FIG. 27, the neuromorphic device (1700) may include a processing circuit (1710) and / or a memory (1720). The neuromorphic device (1700) may include one of the memory elements based on the embodiments of FIGS. 1 to 4 and FIGS. 10 to 14.

[0145] In some exemplary embodiments, the processing circuit (1710) may be configured to control the function of driving the neuromorphic device (1700). For example, the processing circuit (1710) may be configured to control the neuromorphic (1700) by executing a program stored in memory (1720) of memory (1720). In some exemplary embodiments, the processing circuit may include hardware such as a logic circuit, a hardware / software combination such as a processor that executes software, or a combination thereof. For example, the processor may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP) included in the neuromorphic device (1700), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. In some exemplary embodiments, the processing circuit (1710) may be configured to read / write various data to an external device (1730) and / or to execute a neuromorphic device (1700) using the read / write data. In some embodiments, the external device (1730) may include an external memory and / or sensor array having an image sensor (e.g., a CMOS image sensor circuit).

[0146] In some embodiments, the neuromorphic device of FIG. 27 may be applied to a machine learning system. The machine learning system may utilize various artificial neural network organization and processing models, such as a Convolutional Neural Network (CNN), a Deconvolutional Neural Network, a Recurrent Neural Network (RNN) optionally including a Long Short-Term Memory (LSTM) unit and / or a Gated Recurrent Unit (GRU), a Stacked Neural Network (SNN), a State-Space Dynamic Neural Network (SDNN), a Deep Faith Network (DBN), a Generative Adversarial Network (GAN), and / or a Restricted Boltzmann Machine (RBM).

[0147] Alternatively, such machine learning systems may include combinations thereof, including other forms of machine learning models such as linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, expert systems, and / or random forests. These machine learning models may be used to provide various services and / or applications, such as image classification services, user authentication services based on biometric information or biometric data, ADAS (Advanced Driver Assistance System) services, voice assistant services, automatic speech recognition (ASR) services, etc., which may be executed by electronic devices.

[0148] The memory device described above has been explained with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Although many details are described in detail in the above description, they should be interpreted as examples of specific embodiments rather than as limiting the scope of the invention. Accordingly, the scope of the invention should not be determined by the described embodiments but by the technical concept described in the claims. Explanation of the symbols

[0149] 100, 200 900: 1st to 9th memory elements 210, 510: Insulating structure 220, 320, 420: 1st to 3rd oxygen scavenger layers 230, 530: Recording material layer 235, 535: Native oxide film 240, 540: Channel layer 240e: Current 250, 550: Gate insulation layer 260, 560: Gate electrode 270, 570: Separation layer 325, 620, 820: Insulating layers 420a, 420b: First and second sub-material layers 515, 615, 815: Oxygen scavenger layers 515a, 515b: First and second submaterial layers 520: Board 525: Common Source Line (CSL) 580: Victim Layer 590, BL: Beatline 680: Drain area 1600: Memory system 1700: Neuromorphic device Asw: Switching area CS: Cell string D1, D2: 1st and 2nd directions G1, G2: 1st and 2nd gate electrodes HO_ch: Channel Hall HO_ga:Gatehole MC:Memory Cell WL: Wordline

Claims

Claim 1 A memory device comprising: a base substrate; an oxygen scavenger layer provided on the base substrate; a recording material layer provided on the oxygen scavenger layer and in direct contact with the oxygen scavenger layer; a channel layer provided on the recording material layer; a gate insulating layer provided on the channel layer; and a gate electrode provided on the gate insulating layer; wherein the oxygen scavenger layer comprises a semiconductor layer doped with a dopant and insulating layers provided at both ends thereof, and the oxygen scavenger layer comprises an element that creates oxygen vacancies in the recording material layer and does not contain oxygen. Claim 2 In claim 1, the base substrate and the oxygen scavenger layer are of the same material and form a single layer of a memory device. Claim 3 delete Claim 4 delete Claim 5 delete Claim 6 delete Claim 7 delete Claim 8 A memory device comprising: a base substrate; an oxygen scavenger layer provided on the base substrate; a recording material layer provided on the oxygen scavenger layer and in direct contact with the oxygen scavenger layer; a channel layer provided on the recording material layer; a gate insulating layer provided on the channel layer; and a gate electrode provided on the gate insulating layer; wherein the oxygen scavenger layer includes an element that creates an oxygen vacancy in the recording material layer and does not include oxygen, and the oxygen scavenger layer includes a metal layer and insulating layers provided at both ends thereof. Claim 9 In claim 1, the element is a semiconductor element, and the memory device. Claim 10 In claim 9, the oxygen scavenger layer further comprises nitrogen (N), forming a memory device. Claim 11 A memory device according to claim 1, wherein the oxygen scavenger layer comprises: a first submaterial layer formed on the base substrate; and a second submaterial layer formed on the first submaterial layer and in direct contact with the recording material layer. Claim 12 A memory device according to claim 11, wherein one of the first and second submaterial layers is a layer containing a semiconductor component, and the other is a metal layer. Claim 13 A memory device according to claim 11, wherein one of the first and second submaterial layers is a semiconductor layer doped with the dopant, and the other is a nitride layer. Claim 14 A memory device according to claim 11, wherein one of the first and second submaterial layers is a semiconductor layer doped with the dopant, and the other is an undoped semiconductor layer. Claim 15 In claim 12, the layer containing the semiconductor component is a memory device further containing nitrogen. Claim 16 In claim 13, the semiconductor layer doped with the dopant is a silicon layer doped with the dopant, in a memory device. Claim 17 A memory device according to claim 1, wherein the base substrate is an insulating structure containing oxygen, and the oxygen scavenger layer is a barrier configured to block oxygen of the base substrate from moving to the recording material layer. Claim 18 In claim 1, a plurality of gate electrodes on the gate insulating layer are aligned in a first direction, and a separation layer is disposed between them to insulate each other. Claim 19 In claim 18, the base substrate is cylindrical parallel to the first direction, and the oxygen scavenger layer, the recording material layer, the channel layer, and the gate insulating layer are sequentially stacked on the cylindrical surface of the base substrate to surround the base substrate. Claim 20 In claim 19, the base substrate, the oxygen scavenger layer, the recording material layer, the channel layer, the gate insulating layer, the gate electrode, and the separation layer are provided on a substrate including a doping region, and a stack comprising the base substrate, the oxygen scavenger layer, the recording material layer, the channel layer, the gate insulating layer, and the channel layer is provided such that one end thereof is in contact with the doping region while perpendicular to the surface of the substrate, and the gate electrode and the separation layer are provided parallel to the substrate while surrounding the stack. Claim 21 In claim 20, the other end of the stack opposite to the first end of the stack is in contact with a drain region, and a bit line is connected to the drain region. Claim 22 In claim 1, the recording material layer comprises one of a resistance change material and a phase change material. Claim 23 An electronic device comprising a memory element according to any one of claims 1, 2, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, and 22. Claim 24 A method for manufacturing a memory device comprising: a step of forming a stacked structure by alternately and repeatedly depositing a sacrificial layer and a separation layer on a substrate; a step of forming a channel hole penetrating the stacked structure; a step of sequentially forming a gate insulating layer, a channel layer, a recording material layer, and an oxygen scavenger layer on the inner surface of the channel hole; a step of filling the interior of the channel hole remaining after the oxygen scavenger layer is formed with a filling material; a step of forming a gate hole by removing the sacrificial layer; and a step of depositing an electrode material on the gate hole; wherein, after forming the gate insulating layer and the channel layer on the inner surface of the channel hole, the insulating material and channel material deposited on the bottom surface of the channel hole are removed before forming the recording material layer, and the oxygen scavenger layer contains an element that creates an oxygen vacancy in the recording material layer and does not contain oxygen. Claim 25 delete Claim 26 A method for manufacturing a memory device according to claim 24, wherein the oxygen scavenger layer and the landfill material are formed of the same material and form a single layer. Claim 27 A method for manufacturing a memory device according to claim 24, wherein the step of forming the oxygen scavenger layer comprises: a step of forming a first submaterial layer on the inner surface of the recording material layer; and a step of forming a second submaterial layer on the inner surface of the first submaterial layer. Claim 28 A method for manufacturing a memory device according to claim 24 or 26, wherein the oxygen scavenger layer comprises a semiconductor layer. Claim 29 A method for manufacturing a memory device according to claim 24 or 26, wherein the oxygen scavenger layer comprises a metal layer and an insulating layer is formed at both ends thereof in a direction perpendicular to the substrate. Claim 30 A method for manufacturing a memory device according to claim 28, wherein the semiconductor layer is a silicon layer doped with a dopant or an undoped silicon layer, and when the semiconductor layer is the doped silicon layer, an insulating layer is formed at both ends in a direction perpendicular to the substrate. Claim 31 A method for manufacturing a memory device according to claim 27, wherein one of the first submaterial layer and the second submaterial layer is a semiconductor layer and the other is a metal layer. Claim 32 A method for manufacturing a memory device according to claim 27, wherein one of the first submaterial layer and the second submaterial layer is a semiconductor layer and the other is a nitride layer. Claim 33 A method for manufacturing a memory device according to claim 27, wherein one of the first submaterial layer and the second submaterial layer is a doped silicon layer and the other is an undoped silicon layer. Claim 34 In claim 24, the oxygen scavenger layer is formed by a PEALD method for manufacturing a memory device. Claim 35 A method for manufacturing a memory device according to claim 24, wherein the channel layer and the oxygen scavenger layer are formed from the same material under the same conditions.

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