Integrated circuit device

Abstract

An integrated circuit device comprises a pin-shaped active region, a channel region disposed on the pin-shaped active region, a gate line surrounding the channel region on the pin-shaped active region, and a source / drain region disposed at a position adjacent to the gate line on the pin-shaped active region and having a sidewall facing the channel region, wherein the source / drain region comprises a lower source / drain region and an upper source / drain region. The lower source / drain region comprises at least one silicon isotope selected from silicon isotopes consisting of 28Si, 29Si, and 30Si, and the upper source / drain region is integrally connected to the lower source / drain region and comprises a 28Si element with a content ratio greater than the content ratio of the 28Si element in the lower source / drain region.

Description

Technology Field

[0001] The technical concept of the present invention relates to an integrated circuit device, and in particular to an integrated circuit device equipped with a field-effect transistor. Background Technology

[0002] With the recent rapid downscaling of integrated circuit devices, it is necessary to ensure not only high operating speeds but also operational accuracy. Furthermore, as the integration density of integrated circuits increases and their size decreases, there is a need to develop new structures capable of improving the performance and reliability of field-effect transistors with fin-type active regions. The problem to be solved

[0003] The technical problem that the technical concept of the present invention aims to solve is to provide an integrated circuit device having a structure capable of improving the performance of a field-effect transistor having a pin-shaped active region and improving the reliability of an integrated circuit device including said field-effect transistor. means of solving the problem

[0004] An integrated circuit device according to one embodiment of the technical concept of the present invention comprises a pin-shaped active region extending in a first horizontal direction on a substrate, a channel region disposed on the pin-shaped active region, a gate line extending in a second horizontal direction intersecting the first horizontal direction and surrounding the channel region on the pin-shaped active region, and a source / drain region disposed at a position adjacent to the gate line on the pin-shaped active region and having a sidewall facing the channel region, wherein the source / drain region has a bottom surface in contact with the pin-shaped active region. 28 Si, 29 Si, and 30A lower source / drain region comprising at least one silicon isotope selected from silicon isotopes consisting of Si, and a lower source / drain region integrally connected to the lower source / drain region on the lower source / drain region, wherein in the lower source / drain region 28 A content ratio greater than the content ratio of the Si element 28 It includes an upper source / drain region containing Si elements.

[0005] An integrated circuit device according to another embodiment of the technical concept of the present invention comprises a pin-shaped active region extending in a first horizontal direction on a substrate, a recess formed in the pin-shaped active region, a pair of channel regions disposed on the pin-shaped active region with the recess in between, a pair of gate lines extending in a second horizontal direction intersecting the first horizontal direction on the pin-shaped active region and spaced apart in the first horizontal direction with the recess in between, and a source / drain region disposed within the recess and in contact with the pair of channel regions, wherein the source / drain region has a bottom surface in contact with the pin-shaped active region. 28 Si, 29 Si, and 30 A lower source / drain region comprising at least one silicon isotope selected from silicon isotopes consisting of Si, and a lower source / drain region integrally connected to the lower source / drain region on the lower source / drain region, wherein in the lower source / drain region 28 A content ratio greater than the content ratio of the Si element 28 It includes an upper source / drain region containing Si elements.

[0006] An integrated circuit device according to another embodiment of the technical concept of the present invention comprises a plurality of pin-shaped active regions disposed on a substrate, a plurality of recesses formed on the upper portion of each of the plurality of pin-shaped active regions, a plurality of channel regions disposed on the plurality of pin-shaped active regions, a plurality of gate lines disposed on the plurality of channel regions and extending in a second horizontal direction intersecting the first horizontal direction, a plurality of source / drain regions disposed within the plurality of recesses, a plurality of source / drain contacts disposed on the plurality of source / drain regions and each having a bottom portion surrounded by one source / drain region selected among the plurality of source / drain regions, and a plurality of metal silicide films interposed between the plurality of source / drain regions and the plurality of source / drain contacts, wherein the plurality of source / drain regions each have a bottom surface in contact with one pin-shaped active region selected among the plurality of pin-shaped active regions. 28 Si, 29 Si, and 30 A lower source / drain region comprising at least one silicon isotope selected from silicon isotopes consisting of Si, and a lower source / drain region integrally connected to the lower source / drain region on the lower source / drain region, wherein in the lower source / drain region 28 A content ratio greater than the content ratio of the Si element 28 It includes an upper source / drain region containing Si elements. Effects of the invention

[0007] An integrated circuit device according to the technical concept of the present invention has an upper local region of a source / drain region in a field-effect transistor having a fin-shaped active region, which is swollen due to the injection of Si element ions and has an elevated upper surface. Accordingly, the reliability of the electrical connection between the source / drain region and the wiring structure connected to the source / drain region can be improved, and accordingly, the performance of the field-effect transistor including the source / drain region can be improved, and the reliability of the integrated circuit device including the source / drain region can be improved. Brief explanation of the drawing

[0008] FIG. 1 is a planar layout diagram of some configurations of an integrated circuit element according to embodiments of the technical concept of the present invention. FIG. 2a is a cross-sectional view along the X1-X1' line of FIG. 1, FIG. 2b is a cross-sectional view along the Y1-Y1' line of FIG. 1, FIG. 2c is a cross-sectional view along the Y2-Y2' line of FIG. 1, and FIG. 2d is an enlarged cross-sectional view of the local area labeled "EX1" in FIG. 2a. FIG. 3a is a cross-sectional view illustrating an integrated circuit element according to other embodiments of the technical concept of the present invention, and FIG. 3b is an enlarged cross-sectional view of a local region indicated as "EX1A" in FIG. 3a. FIG. 4 is a cross-sectional view illustrating an integrated circuit element according to other embodiments of the technical concept of the present invention. FIG. 5 is a cross-sectional view illustrating an integrated circuit element according to other embodiments of the technical concept of the present invention. FIG. 6 is a cross-sectional view illustrating an integrated circuit element according to other embodiments of the technical concept of the present invention. FIG. 7 is a layout diagram for explaining an integrated circuit element according to other embodiments of the technical concept of the present invention. FIG. 8a is a cross-sectional view along the X21 - X21' line of FIG. 7, FIG. 8b is a cross-sectional view along the Y21 - Y21' line of FIG. 7, and FIG. 8c is a cross-sectional view along the Y22 - Y22' line of FIG. 7. FIG. 9 is a cross-sectional view illustrating an integrated circuit element according to other embodiments of the technical concept of the present invention. FIG. 10 is a cross-sectional view illustrating an integrated circuit element according to other embodiments of the technical concept of the present invention. FIG. 11 is a planar layout diagram for explaining an integrated circuit element according to other embodiments of the technical concept of the present invention. FIG. 12 is a block diagram of an integrated circuit element according to other embodiments of the technical concept of the present invention. FIG. 13 is a cross-sectional view illustrating an exemplary configuration of an integrated circuit element exemplified in FIG. 12. FIG. 14 is a cross-sectional view illustrating an integrated circuit element according to another embodiment of the technical concept of the present invention. FIG. 15 is a cross-sectional view illustrating an integrated circuit element according to another embodiment of the technical concept of the present invention. FIGS. 16a to 16k are cross-sectional drawings illustrated in the order of process to explain a method for manufacturing an integrated circuit element according to embodiments of the technical concept of the present invention. Specific details for implementing the invention

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0010] FIG. 1 is a planar layout diagram of some configurations of an integrated circuit device (100) according to embodiments of the technical concept of the present invention. FIG. 2a is a cross-sectional view along the X1-X1' line of FIG. 1, FIG. 2b is a cross-sectional view along the Y1-Y1' line of FIG. 1, FIG. 2c is a cross-sectional view along the Y2-Y2' line of FIG. 1, and FIG. 2a to 2d. An integrated circuit device (100) comprising a field-effect transistor (TR) having a gate-all-around structure including an active region in the shape of a nanowire or nanosheet and a gate surrounding the active region will be described.

[0011] Referring to FIGS. 1 and FIGS. 2a through 2d, an integrated circuit element (100) may include a plurality of pin-shaped active regions (FA) that protrude upward in a vertical direction (Z direction) from a substrate (102) and extend in a first horizontal direction (X direction), and a plurality of nanosheet stacks (NSS) disposed on the plurality of pin-shaped active regions (FA). As used herein, the term “nanosheet” means a conductive structure having a cross-section substantially perpendicular to the direction of current flow. The nanosheet should be understood to include nanowires.

[0012] The substrate (102) may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, InGaAs, or InP. The terms "SiGe," "SiC," "GaAs," "InAs," "InGaAs," and "InP" as used herein refer to materials composed of elements included in each term, and are not chemical formulas representing stoichiometric relationships.

[0013] A device isolation film (114) (see FIG. 1, FIG. 2b, and FIG. 2c) covering both sidewalls of each of a plurality of pin-shaped active regions (FA) may be disposed on the substrate (102). The device isolation film (114) may be made of an oxide film, a nitride film, or a combination thereof.

[0014] A plurality of gate lines (160) may be disposed on a plurality of pin-shaped active regions (FA). Each of the plurality of gate lines (160) may be extended in a second horizontal direction (Y direction) that intersects a first horizontal direction (X direction). A plurality of nanosheet stacks (NSS) may be disposed on top of each of the plurality of pin-shaped active regions (FA) in the regions where the plurality of pin-shaped active regions (FA) and the plurality of gate lines (160) intersect. Each of the plurality of nanosheet stacks (NSS) may include a plurality of nanosheets, for example, a first nanosheet (N1), a second nanosheet (N2), and a third nanosheet (N3), which overlap each other in a mutually perpendicular direction (Z direction) on the pin-shaped active region (FA). The first nanosheet (N1), the second nanosheet (N2), and the third nanosheet (N3) may have different vertical distances (Z direction distances) from the upper surface of the pin-shaped active region (FA).

[0015] FIG. 1 illustrates a case where the planar shape of the nanosheet stack (NSS) is approximately rectangular, but is not limited thereto. The nanosheet stack (NSS) may have various planar shapes depending on the planar shape of the fin-shaped active region (FA) and the gate line (160), respectively. In this example, a configuration is illustrated in which a plurality of nanosheet stacks (NSS) and a plurality of gate lines (160) are arranged on one fin-shaped active region (FA), and a plurality of nanosheet stacks (NSS) are arranged in a line along the first horizontal direction (X direction) on one fin-shaped active region (FA). However, the number of each nanosheet stack (NSS) and gate line (160) arranged on one fin-shaped active region (FA) is not particularly limited.

[0016] The first nanosheet (N1), the second nanosheet (N2), and the third nanosheet (N3) included in the nanosheet stack (NSS) may each have a channel region. For example, the first nanosheet (N1), the second nanosheet (N2), and the third nanosheet (N3) may each have a thickness selected within the range of about 4 nm to about 6 nm, but are not limited thereto. Here, the thickness of each of the first nanosheet (N1), the second nanosheet (N2), and the third nanosheet (N3) refers to the size along the vertical direction (Z direction). In exemplary embodiments, the first nanosheet (N1), the second nanosheet (N2), and the third nanosheet (N3) may have substantially the same thickness along the vertical direction (Z direction). In other exemplary embodiments, at least some of the first nanosheet (N1), the second nanosheet (N2), and the third nanosheet (N3) may have different thicknesses along the vertical direction (Z direction).

[0017] In exemplary embodiments, at least some of the first nanosheet (N1), second nanosheet (N2), and third nanosheet (N3) included in one nanosheet stack (NSS) may have different sizes in the first horizontal direction (X direction). In other exemplary embodiments, at least some of the first nanosheet (N1), second nanosheet (N2), and third nanosheet (N3) may have the same size in the first horizontal direction (X direction).

[0018] A plurality of recesses (R1) may be formed on the pin-shaped active region (FA). As illustrated in FIG. 2a, the vertical level of the lowest surface of each of the plurality of recesses (R1) may be lower than the vertical level of the upper surface of the pin-shaped active region (FA). As used herein, the term “vertical level” means a distance along the vertical direction (Z direction or -Z direction) from the main surface (102M) of the substrate (102).

[0019] A plurality of source / drain regions (130) may be disposed within a plurality of recesses (R1). Each of the plurality of source / drain regions (130) may be disposed at a location adjacent to at least one gate line (160) selected from a plurality of gate lines (160). Each of the plurality of source / drain regions (130) may have a sidewall facing a first nanosheet (N1), a second nanosheet (N2), and a third nanosheet (N3) included in an adjacent nanosheet stack (NSS). Each of the plurality of source / drain regions (130) may be in contact with a first nanosheet (N1), a second nanosheet (N2), and a third nanosheet (N3) included in an adjacent nanosheet stack (NSS).

[0020] A plurality of source / drain regions (130) may each include a lower source / drain region (130L) having a bottom surface in contact with a pin-shaped active region (FA), and an upper source / drain region (130R) disposed on the lower source / drain region (130L) and integrally connected to the lower source / drain region (130L). The lower source / drain region (130L) 28 Si, 29 Si, and 30 It may include at least one silicon isotope selected from silicon isotopes consisting of Si. The upper source / drain region (130R) is in the lower source / drain region (130L). 28 A content ratio greater than the content ratio of the Si element 28 It may include the Si element. In this specification, the term " 28 "Si" refers to a silicon atom with a unified atomic mass unit (AMU) of 28, and," 29 "Si" refers to a silicon atom with an AMU of 29, and " 30 "Si" refers to silicon atoms with an AMU of 30. In this specification, the term "content ratio" refers to the atomic percentage of the element per unit volume.

[0021] In exemplary embodiments, the upper source / drain region (130R) included 28 The content ratio of Si elements in naturally occurring Si films 28 It may be a value greater than the content ratio of the Si element. For example, the upper source / drain region (130R) is at least 80 atomic percent 28 A Si film containing Si elements, at least 50 atomic percent 28 A SiC film containing Si elements, or at least 50 atomic percent 28 It may be composed of a SiGe film containing Si elements. In other exemplary embodiments, within the upper source / drain region (130R). 28 The content ratio of the Si element may be at least 10 atomic%, at least 15 atomic%, at least 20 atomic%, at least 25 atomic%, at least 30 atomic%, at least 35 atomic%, at least 40 atomic%, at least 45 atomic%, at least 50 atomic%, at least 55 atomic%, at least 60 atomic%, at least 65 atomic%, at least 70 atomic%, at least 75 atomic%, at least 80 atomic%, at least 85 atomic%, at least 90 atomic%, at least 95 atomic%, at least 97 atomic%, at least 98 atomic%, at least 99 atomic%, or about 100 atomic%. In other exemplary embodiments, within the upper source / drain region (130R). 28 The content ratio of the Si element may be approximately 30 atomic percent to approximately 95 atomic percent based on the total amount of Si isotopes present in the upper source / drain region (130R). However, within the upper source / drain region (130R) 28 The content ratio of Si elements is not limited to what is exemplified above.

[0022] In exemplary embodiments, in each of the plurality of source / drain regions (130), the lower source / drain region (130L) is formed of an epitaxially grown semiconductor layer, and the upper source / drain region (130R) is formed of an epitaxially grown semiconductor layer 28It may be composed of a semiconductor layer additionally doped with Si elements. In exemplary embodiments, in each of the plurality of source / drain regions (130), the lower source / drain region (130L) may be composed of a group IV element semiconductor, a group IV-IV compound semiconductor, or a combination thereof. In exemplary embodiments, in each of the plurality of source / drain regions (130), the lower source / drain region (130L) may be composed of a Si layer doped with an n-type dopant, a SiC layer doped with an n-type dopant, or a SiGe layer doped with a p-type dopant. The n-type dopant may be selected from P (phosphorus), As (arsenic), and Sb (antimony). The p-type dopant may be selected from B (boron) and Ga (gallium). The Si atoms contained in the lower source / drain region (130L) 28 Si, 29 Si, and 30 It can be selected from silicon isotopes consisting of Si. In each of the plurality of source / drain regions (130), the upper source / drain region (130R) is composed of a Si layer doped with an n-type dopant, a SiC layer doped with an n-type dopant, or a SiGe layer doped with a p-type dopant, similar to the lower source / drain region (130L). 28 It can be composed of a semiconductor layer additionally doped with Si elements.

[0023] In exemplary embodiments, in each of the plurality of source / drain regions (130), the lower source / drain region (130L) and the upper source / drain region (130R) are each made of single-crystal silicon doped with an n-type dopant, and the lower source / drain region (130L) has a first content ratio greater than 0 atomic%. 28 It includes Si, and the upper source / drain region (130R) has a second content ratio greater than the first content ratio. 28 It may contain Si.

[0024] In other exemplary embodiments, in each of the plurality of source / drain regions (130), the lower source / drain region (130L) and the upper source / drain region (130R) are each composed of a SiGe layer doped with a p-type dopant, and the lower source / drain region (130L) has a first content ratio greater than 0 atomic%. 28 It includes Si, and the upper source / drain region (130R) has a second content ratio greater than the first content ratio. 28 It may contain Si.

[0025] As illustrated in FIGS. 2a and 2b, a plurality of gate lines (160) may each surround a first nanosheet (N1), a second nanosheet (N2), and a third nanosheet (N3) while covering a nanosheet stack (NSS) over a fin-shaped active region (FA). Each of the plurality of gate lines (160) may include a main gate portion (160M) and a plurality of sub-gate portions (160S). The main gate portion (160M) may cover the upper surface of the nanosheet stack (NSS) and extend in a second horizontal direction (Y direction). A plurality of sub-gate portions (160S) are integrally connected to the main gate portion (160M) and may be arranged one by one between each of the first nanosheet (N1), the second nanosheet (N2), and the third nanosheet (N3), and between the first nanosheet (N1) and the fin-shaped active region (FA). In the vertical direction (Z direction), the thickness of each of the multiple sub-gate portions (160S) may be smaller than the thickness of the main gate portion (160M).

[0026] Each of the multiple gate lines (160) may be composed of a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal nitride may be selected from TiN and TaN. The metal carbide may be TiAlC. However, the materials constituting the multiple gate lines (160) are not limited to those exemplified above.

[0027] A gate dielectric film (152) may be interposed between the nanosheet stack (NSS) and the gate line (160). In exemplary embodiments, the gate dielectric film (152) may be composed of a stacked structure of an interface dielectric film and a high dielectric film. The interface dielectric film may be composed of a low dielectric material film having a dielectric constant of about 9 or less, for example, a silicon oxide film, a silicon oxynitride film, or a combination thereof. In exemplary embodiments, the interface dielectric film may be omitted. The high dielectric film may be composed of a material having a dielectric constant greater than that of the silicon oxide film. For example, the high dielectric film may have a dielectric constant of about 10 to 25. The high dielectric film may be composed of hafnium oxide, but is not limited thereto.

[0028] A plurality of field-effect transistors (TR) may be formed on the substrate (102) at the portions where a plurality of pin-shaped active regions (FA) and a plurality of gate lines (160) intersect. The plurality of field-effect transistors (TR) may form a logic circuit or a memory device.

[0029] In exemplary embodiments, the first nanosheet (N1), the second nanosheet (N2), and the third nanosheet (N3) may be made of semiconductor layers composed of the same element. In one example, the first nanosheet (N1), the second nanosheet (N2), and the third nanosheet (N3) may each be made of a Si layer. In exemplary embodiments, the first nanosheet (N1), the second nanosheet (N2), and the third nanosheet (N3) may be made of undoped Si layers. In other exemplary embodiments, the first nanosheet (N1), the second nanosheet (N2), and the third nanosheet (N3) may be made of Si layers doped with a dopant having the same conductivity type as the source / drain region (130). In other exemplary embodiments, the first nanosheet (N1), the second nanosheet (N2), and the third nanosheet (N3) may be composed of Si layers doped with a dopant having a conductivity type opposite to that of the source / drain region (130).

[0030] As illustrated in FIGS. 2a and 2d, in each of the plurality of source / drain regions (130), the lower source / drain region (130L) may be in contact with the fin-shaped active region (FA) forming the bottom surface of the recess (R1). In each of the plurality of source / drain regions (130), the upper source / drain region (130R) may have a top surface at a vertical level (LV2) higher than the vertical level (LV1) of the top surface of the nanosheet stack (NSS) containing the channel region (i.e., the top surface of the third nanosheet (N3). The boundary (130F) between the lower source / drain region (130L) and the upper source / drain region (130R) may be at a vertical level lower than the vertical level (LV1) of the top surface of the nanosheet stack (NSS) containing the channel region (i.e., the top surface of the third nanosheet (N3).

[0031] As illustrated in FIGS. 2a, 2b, and 2d, a plurality of outer insulating spacers (118) covering both sidewalls of a gate line (160) may be disposed over a pin-shaped active region (FA) and a device isolation film (114). The plurality of outer insulating spacers (118) may cover a main gate portion (160M) on the upper surface of a plurality of nanosheet stacks (NSS). Each of the plurality of outer insulating spacers (118) may be spaced apart from the gate line (160) with a gate dielectric film (152) in between. The upper surface of each of the gate dielectric film (152), the gate line (160), and the outer insulating spacers (118) may be covered with a capping insulating pattern (164). The capping insulating pattern (164) may be made of a silicon nitride film.

[0032] As illustrated in FIG. 2c, a plurality of recessed-side insulating spacers (119) covering the side walls of the lower source / drain region (130L) included in the source / drain region (130) may be disposed on the upper surface of the device isolation film (114). In exemplary embodiments, the plurality of recessed-side insulating spacers (119) may each be integrally connected with an adjacent outer insulating spacer (118). An air gap (AG) may be disposed in the space defined by the recessed-side insulating spacers (119), the adjacent source / drain region (130), and the device isolation film (114).

[0033] A plurality of outer insulating spacers (118) and a plurality of recess-side insulating spacers (119) may each be made of silicon nitride (SiN), silicon oxide (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. The terms "SiN," "SiO," "SiCN," "SiBN," "SiON," "SiOCN," "SiBCN," and "SiOC" as used herein refer to materials composed of elements included in each term, and are not chemical formulas representing stoichiometric relationships.

[0034] As illustrated in FIGS. 2a and 2d, a plurality of source / drain regions (130) may each include a portion that overlaps with the outer insulating spacer (118) in a vertical direction (Z direction). For example, the width of the first horizontal direction (X direction) of the portion that overlaps with the outer insulating spacer (118) in a vertical direction (Z direction) among the plurality of source / drain regions (130) may be selected within the range of about 0 nm to about 4 nm, but is not limited thereto.

[0035] Between each of the first nanosheet (N1), the second nanosheet (N2), and the third nanosheet (N3), and between the first nanosheet (N1) and the pin-shaped active region (FA), the two sidewalls of each of the plurality of sub-gate portions (160S) may be spaced apart from the source / drain region (130) with the gate dielectric film (152) in between. The gate dielectric film (152) may include a portion in contact with the lower source / drain region (130L) of the source / drain region (130). Each of the plurality of source / drain regions (130) may face the nanosheet stack (NSS) and the plurality of sub-gate portions (160S) in the first horizontal direction (X direction). The upper source / drain region (130R) of the source / drain region (130) may include a portion in contact with the third nanosheet (N3) and a portion in contact with the outer insulating spacer (118).

[0036] As illustrated in FIGS. 2a, 2c, and 2d, a plurality of outer insulating spacers (118) and a plurality of source / drain regions (130) may be covered by insulating liners (142). Each insulating liner (142) may be made of silicon nitride (SiN), silicon oxide (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. In exemplary embodiments, the insulating liner (142) may be omitted. A gate-to-gate insulating film (144) may be disposed over the insulating liner (142). The gate-to-gate insulating film (144) may be made of silicon nitride, silicon oxide, SiON, SiOCN, or a combination thereof. When the insulating liner (142) is omitted, the gate-to-gate insulating film (144) may be in contact with the plurality of source / drain regions (130).

[0037] In the integrated circuit element (100), a plurality of source / drain regions (130) are each in a lower source / drain region (130L). 28 A content ratio greater than the content ratio of the Si element 28 It includes an upper source / drain region (130R) containing Si elements. The upper source / drain region (130R) may have an upper surface at a vertical level (LV2) higher than the vertical level (LV1) of the uppermost surface of the nanosheet stack (NSS) containing the channel region (i.e., the uppermost surface of the third nanosheet (N3). Accordingly, the upper source / drain region (130R) may include a portion interposed in the space between a pair of adjacent gate lines (160) among a plurality of gate lines (160).

[0038] In this way, by including an upper source / drain region (130R) having an upper surface in the upper local region of the source / drain region (130), the electrical connection process between the source / drain region (130) and a wiring structure formed thereon, such as a source / drain contact, can be easily performed during the manufacturing process of the integrated circuit device (100), and accordingly, the reliability of the electrical connection between the source / drain region (130) and the wiring structure connected to the source / drain region (130) can be improved. Accordingly, the performance of the field-effect transistor (TR) including the source / drain region (130) can be improved, and the reliability of the integrated circuit device (100) including the source / drain region (130) can be improved.

[0039] FIG. 3a is a cross-sectional view illustrating an integrated circuit element (100A) according to other embodiments of the technical concept of the present invention, and FIG. 3b is an enlarged cross-sectional view of a local region indicated as "EX1A" in FIG. 3a illustrates a partial configuration of a portion corresponding to the cross-section along the line X1 - X1' of FIG. 1. In FIG. 3a and FIG. 3b, the same reference numerals as in FIG. 1 and FIG. 2a through FIG. 2d represent the same components, and redundant descriptions thereof are omitted here.

[0040] Referring to FIGS. 3a and 3b, the integrated circuit element (100A) may have a configuration generally identical to that of the integrated circuit element (100) described with reference to FIGS. 1 and FIGS. 2a to 2d. However, the integrated circuit element (100A) may further include a plurality of source / drain contacts (184) disposed on a plurality of source / drain regions (130). Each of the plurality of source / drain contacts (184) may extend vertically (in the Z direction) between a pair of adjacent gate lines (160) among a plurality of gate lines (160). A metal silicide film (182) may be interposed between the source / drain region (130) and the source / drain contact (184).

[0041] A plurality of source / drain contacts (184) can each penetrate the inter-gate insulating film (144) and insulating liner (142) in a vertical direction (Z direction) and fill the inside of a contact hole (180H) that extends into the source / drain region (130). The source / drain region (130) can be spaced apart from the source / drain contacts (184) by a metal silicide film (182). The source / drain region (130) can surround the bottom of each of the plurality of source / drain contacts (184) from the outside of the contact hole (180H).

[0042] In each of the plurality of source / drain regions (130), the upper source / drain region (130R) may include a portion interposed between the outer insulating spacer (118) and the source / drain contact (184). The upper source / drain region (130R) may include a portion in contact with the outer insulating spacer (118) and a portion in contact with the metal silicide film (182). In each of the plurality of source / drain regions (130), the lower source / drain region (130L) and the upper source / drain region (130R) may each include a portion in contact with the metal silicide film (182).

[0043] In each of the plurality of source / drain regions (130), the upper source / drain region (130R) may include a portion interposed between at least one gate line (160) selected from a pair of adjacent gate lines (160) among the plurality of gate lines (160) and a source / drain contact (184).

[0044] In exemplary embodiments, the metal silicide film (182) may be made of titanium silicide, but is not limited thereto. In exemplary embodiments, the metal silicide film (182) may be omitted. In this case, the lower source / drain region (130L) and the upper source / drain region (130R) of the source / drain region (130) may each be in contact with the source / drain contact (184).

[0045] In exemplary embodiments, a plurality of source / drain contacts (184) may each be made of a metal, a conductive metal nitride, or a combination thereof. For example, a plurality of source / drain contacts (184) may each be made of W, Cu, Al, Ti, Ta, TiN, TaN, an alloy thereof, or a combination thereof.

[0046] FIG. 4 is a cross-sectional view illustrating an integrated circuit element (100B) according to another embodiment of the technical concept of the present invention. FIG. 4 illustrates an enlarged cross-sectional configuration of a region corresponding to the local region indicated as "EX1A" in FIG. 3a. In FIG. 4, the same reference numerals as in FIG. 1, FIG. 2a to 2d, FIG. 3a, and FIG. 3b represent the same components, and redundant descriptions thereof are omitted here.

[0047] Referring to FIG. 4, the integrated circuit element (100B) may have a configuration generally identical to that of the integrated circuit element (100A) described with reference to FIG. 3a and 3b. However, the integrated circuit element (100B) includes a source / drain region (130B) instead of the source / drain region (130) exemplified in FIG. 3a and 3b.

[0048] The source / drain region (130B) may have a configuration generally identical to the source / drain region (130) described with reference to FIGS. 2a, 2c, 2d, 3a, and 3b. However, the source / drain region (130B) includes a lower source / drain region (130LB) and an upper source / drain region (130RB). The upper source / drain region (130RB) is in the lower source / drain region (130LB). 28 A content ratio greater than the content ratio of the Si element 28It may contain Si elements. The upper source / drain region (130RB) may have an upper surface at a vertical level (LV2) higher than the vertical level (LV1) of the top surface of the nanosheet stack (NSS) containing the channel region (i.e., the top surface of the third nanosheet (N3). The boundary (130FB) between the lower source / drain region (130LB) and the upper source / drain region (130RB) may be at a vertical level lower than the vertical level (LV1) of the top surface of the nanosheet stack (NSS) containing the channel region, for example, at a vertical level lower than the vertical level of the top surface of the second nanosheet (N2). The upper source / drain region (130RB) may include a portion in contact with the second nanosheet (N2), a portion in contact with the third nanosheet (N3), and a portion in contact with the outer insulating spacer (118). The upper source / drain region (130RB) may include a portion interposed in the space between a pair of adjacent gate lines (160) among a plurality of gate lines (160).

[0049] In the source / drain region (130B), the lower source / drain region (130LB) may be spaced apart from the metal silicide film (182) with the upper source / drain region (130RB) in between. The metal silicide film (182) may be in contact only with the upper source / drain region (130RB) among the lower source / drain region (130LB) and the upper source / drain region (130RB). A more detailed configuration of the lower source / drain region (130LB) and the upper source / drain region (130RB) is as described with reference to FIGS. 2a, 2c, and 2d for the lower source / drain region (130L) and the upper source / drain region (130R).

[0050] FIG. 5 is a cross-sectional view illustrating an integrated circuit element (100C) according to another embodiment of the technical concept of the present invention. FIG. 5 illustrates an enlarged cross-sectional configuration of a region corresponding to the local region indicated as "EX1" in FIG. 2a. In FIG. 5, the same reference numerals as in FIG. 1 and FIG. 2a through 2d indicate the same components, and redundant descriptions thereof are omitted here.

[0051] Referring to FIG. 5, the integrated circuit element (100C) may have a configuration generally identical to that of the integrated circuit element (100) described with reference to FIG. 1 and FIG. 2a to 2d. However, the integrated circuit element (100C) includes a source / drain region (130C) instead of the source / drain region (130) exemplified in FIG. 2a, 2c, and 2b.

[0052] The source / drain region (130C) may have a configuration generally identical to the source / drain region (130) described with reference to FIGS. 2a, 2c, and 2d. However, the source / drain region (130C) includes a lower source / drain region (130LC) and an upper source / drain region (130RC).

[0053] The lower source / drain region (130LC) may include a first main body layer (130L1), a second main body layer (130L2), and a third main body layer (130L3) stacked sequentially from a pin-shaped active region (FA) forming the bottom surface of the recess (R1). The upper source / drain region (130RC) may include an upper body layer (130R1) and an upper capping layer (130R2) stacked sequentially on the third main body layer (130L3).

[0054] The upper source / drain region (130RC) is in the lower source / drain region (130LC). 28 A content ratio greater than the content ratio of the Si element 28It may contain Si elements. The boundary (130FC) between the lower source / drain region (130LC) and the upper source / drain region (130RC) may be at a vertical level lower than the vertical level (LV1) of the top surface of the nanosheet stack (NSS).

[0055] The upper body layer (130R1) of the upper source / drain region (130RC) may include a portion in contact with the third nanosheet (N3) and a portion in contact with the outer insulating spacer (118). The upper source / drain region (130RC) may include a portion interposed in the space between a pair of adjacent gate lines (160) among a plurality of gate lines (160).

[0056] In exemplary embodiments, in the lower source / drain region (130LC) of the source / drain region (130C), the first main body layer (130L1), the second main body layer (130L2), and the third main body layer (130L3) are each Si doped with a p-type dopant. 1-x Ge x It may be composed of layers (where 0.15 ≤ x < 0.7). Here, the Ge concentration in the second main body layer (130L2) may be greater than the Ge concentration in the first main body layer (130L1), and the Ge concentration in the third main body layer (130L3) may be greater than the Ge concentration in the second main body layer (130L2). In exemplary embodiments, the Ge concentration in the first main body layer (130L1) may be selected within the range of about 0.15 atomic% or more and about 0.30 atomic% or less, the Ge concentration in each of the second main body layers (130L2) may be selected within the range of about 0.30 atomic% or more and about 0.50 atomic% or less, and the Ge concentration in the third main body layer (130L3) may be about 0.50 atomic% or more and about 0.70 atomic% or less, but is not limited to those exemplified above. In exemplary embodiments, the p-type dopant may be at least one selected from boron (B) and gallium (Ga), but is not limited thereto.

[0057] In the upper source / drain region (130RC) of the source / drain region (130C), the upper body layer (130R1) is in the constituent material of the third main body layer (130L3). 28 It may be composed of a semiconductor layer additionally doped with Si elements. In exemplary embodiments, the upper body layer (130R1) is at least 50 atomic percent of 28 It can be made of a SiGe film containing Si elements.

[0058] In the upper source / drain region (130RC) of the source / drain region (130C), the upper capping layer (130R2) may cover the upper surface of the upper body layer (130R1) at a vertical level higher in the vertical direction (Z direction) than the vertical level (LV1) of the top surface of the nanosheet stack (NSS). In exemplary embodiments, the upper capping layer (130R2) may have a thickness of about 0.1 nm to about 10 nm. In exemplary embodiments, the upper capping layer (130R2) may be composed of a Si layer, or a SiGe layer having a Ge concentration lower than the Ge concentration in the upper body layer (130R1). The Si layer constituting the upper capping layer (130R2) 28 Si, 29 Si, and 30 Among silicon isotopes composed of Si 28 It may include at least one silicon isotope containing Si. In the upper capping layer (130R2). 28 The content ratio of Si elements in naturally occurring Si films 28 The content ratio of the Si element may be greater than that of the Si element. In other exemplary embodiments, the upper capping layer (130R2) may be composed of a Si layer doped with a p-type dopant selected from boron (B) and gallium (Ga). For example, the upper capping layer (130R2) may be composed of a Si layer doped with boron (B). The Si layer doped with the p-type dopant constituting the upper capping layer (130R2) 28 Si,29 Si, and 30 Among silicon isotopes composed of Si 28 Comprising at least one silicon isotope including Si, and within a Si layer doped with said p-type dopant 28 The content ratio of Si elements in a Si film doped with a naturally occurring p-type dopant is 28 The content ratio of the Si element may be greater. The upper capping layer (130R2) may serve to protect the first main body layer (130L1), the second main body layer (130L2), the third main body layer (130L3), and the upper body layer (130R1). For example, the upper capping layer (130R2) may serve to prevent chemical substances or external shocks from being transmitted from the outside to the first main body layer (130L1), the second main body layer (130L2), the third main body layer (130L3), and the upper body layer (130R1).

[0059] FIG. 6 is a cross-sectional view illustrating an integrated circuit element (100D) according to other embodiments of the technical concept of the present invention. FIG. 6 illustrates some configurations of the parts corresponding to the cross-section along line X1 - X1' of FIG. 1.

[0060] Referring to FIG. 6, the integrated circuit element (100D) may have a configuration generally identical to that of the integrated circuit element (100) described with reference to FIG. 1 and FIG. 2a to 2d. However, the integrated circuit element (100D) further includes a plurality of inner insulating spacers (120) interposed between each of the first nanosheet (N1), the second nanosheet (N2), and the third nanosheet (N3), and between the first nanosheet (N1) and the pin-shaped active region (FA), and between a plurality of sub-gate portions (160S) and source / drain regions (130).

[0061] Each of the multiple sub-gate portions (160S) may have both side walls covered by an inner insulating spacer (120) with the gate dielectric film (152) in between. Each of the multiple sub-gate portions (160S) may be spaced apart from the source / drain region (130) with the gate dielectric film (152) and the inner insulating spacer (120) in between. Each of the multiple inner insulating spacers (120) may be in contact with the source / drain region (130). At least a portion of the multiple inner insulating spacers (120) may overlap with the outer insulating spacer (118) in a vertical direction (Z direction).

[0062] A plurality of inner insulating spacers (120) may be made of silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. In exemplary embodiments, at least some of the plurality of inner insulating spacers (120) may further include an air gap. In exemplary embodiments, the inner insulating spacers (120) may be made of the same material as the outer insulating spacers (118). In other exemplary embodiments, the outer insulating spacers (118) and the inner insulating spacers (120) may be made of different materials.

[0063] A plurality of source / drain regions (130) may each face a plurality of sub-gate portions (160S) in the first horizontal direction (X direction) with the inner insulating spacer (120) and the gate dielectric film (152) in between. A plurality of source / drain regions (130) may not include a portion in contact with the gate dielectric film (152).

[0064] FIG. 7 is a layout diagram for explaining an integrated circuit element (200) according to another embodiment of the technical concept of the present invention. FIG. 8a is a cross-sectional view along the line X21 - X21' of FIG. 7, FIG. 8b is a cross-sectional view along the line Y21 - Y21' of FIG. 7, and FIG. 8c is a cross-sectional view along the line Y22 - Y22' of FIG. 7. In FIG. 7 and FIG. 8a to 8c, the same reference numerals as in FIG. 1 and FIG. 2a to 2d indicate the same components, and a detailed description thereof is omitted here.

[0065] The integrated circuit element (200) may include a plurality of field-effect transistors (TR2) formed on a pin-type active region (FB). The plurality of field-effect transistors (TR2) may form a logic circuit or a memory element.

[0066] The integrated circuit element (200) may include a plurality of pin-shaped active regions (FB) that protrude in a vertical direction (Z direction) from the substrate (102) and extend in a first horizontal direction (X direction), and a plurality of main channel regions (MCA) that protrude upward along the vertical direction (Z direction) from each of the plurality of pin-shaped active regions (FB) and are integrally connected with the pin-shaped active regions (FB).

[0067] As illustrated in FIGS. 8b and 8c, a device isolation film (114) covering both sidewalls of each of a plurality of fin-shaped active regions (FB) may be disposed on a substrate (102). As illustrated in FIGS. 7, 8b and 8c, a plurality of gate lines (GL2) may be disposed on the fin-shaped active regions (FB). Each of the plurality of gate lines (GL2) may be extended in a second horizontal direction (Y direction). As illustrated in FIG. 8b, a plurality of main channel regions (MCA) may each be surrounded by the gate lines (GL2). The constituent material of the plurality of gate lines (GL2) is generally the same as that described for the gate line (160) with reference to FIGS. 1, 2a and 2b. A plurality of field-effect transistors (TR2) may be formed in regions where the plurality of fin-shaped active regions (FB) and the plurality of gate lines (GL2) intersect.

[0068] In exemplary embodiments, the fin-shaped active region (FB) and the main channel region (MCA) may be made of the same material. For example, the fin-shaped active region (FB) and the main channel region (MCA) may each be made of a Si layer. In exemplary embodiments, the main channel region (MCA) may each be made of an undoped Si layer, a Si layer doped with a p-type dopant, or a Si layer doped with an n-type dopant.

[0069] As illustrated in FIG. 8a, a plurality of recesses (R2) may be formed on a pin-shaped active region (FB). In the first horizontal direction (X direction), the width of the main channel region (MCA) may be limited by two adjacent recesses (R2) among the plurality of recesses (R2). A plurality of source / drain regions (230) may be disposed within the plurality of recesses (R2). The main channel region (MCA) may have surfaces in contact with a pair of source / drain regions (230) disposed adjacently on both sides thereof.

[0070] A plurality of source / drain regions (230) may each be positioned adjacent to at least one gate line (GL2) selected from a plurality of gate lines (GL2). A plurality of source / drain regions (230) may each include a lower source / drain region (230L) adjacent to a pin-type active region (FB), and an upper source / drain region (230R) disposed on the lower source / drain region (230L) and integrally connected to the lower source / drain region (230L). A more detailed configuration of the lower source / drain region (230L) and the upper source / drain region (230R) of the source / drain region (230) is as described with reference to FIGS. 2a, 2c, and 2d for the lower source / drain region (130L) and the upper source / drain region (130R) of the source / drain region (130). However, the lower source / drain area (230L) and the upper source / drain area (230R) may each include a portion that contacts the main channel area (MCA).

[0071] In each of the multiple source / drain regions (230), the lower source / drain region (230L) may be in contact with the fin-shaped active region (FB) forming the inner wall of the recess (R2). In each of the multiple source / drain regions (230), the upper source / drain region (230R) may have an upper surface at a vertical level (LV22) higher than the vertical level (LV21) of the uppermost surface of the main channel region (MCA). The boundary (230F) between the lower source / drain region (230L) and the upper source / drain region (230R) may be at a vertical level lower than the vertical level (LV21) of the uppermost surface of the main channel region (MCA). A more detailed configuration of the lower source / drain area (230L) and the upper source / drain area (230R) included in the source / drain area (230) is as described with reference to FIGS. 2a, 2c, and 2d for the lower source / drain area (130L) and the upper source / drain area (130R).

[0072] A gate dielectric film (154) may be interposed between the main channel region (MCA) and the gate line (GL2). The gate dielectric film (154) may cover the bottom surface and side wall of the gate line (GL2). The gate dielectric film (154) may have a surface in contact with the main channel region (MCA). A more detailed configuration of the gate dielectric film (154) is generally the same as that described for the gate dielectric film (152) with reference to FIGS. 2a and 2b.

[0073] Each of the multiple gate lines (GL2) may have both side walls covered by an insulating spacer (118). The insulating spacer (118) may cover both side walls of the gate lines (GL2) on the upper surface of the main channel region (MCA). Each insulating spacer (118) may be spaced apart from the gate lines (GL2) with a gate dielectric film (154) in between.

[0074] Each of the multiple source / drain regions (230) may include a portion that overlaps with the insulating spacer (118) in the vertical direction (Z direction). For example, the width of the first horizontal direction (X direction) of the portion of the multiple source / drain regions (230) that overlaps with the insulating spacer (118) in the vertical direction (Z direction) may be selected within the range of about 0 nm to about 4 nm, but is not limited thereto. Each of the multiple source / drain regions (230) and the multiple insulating spacer (118) may be covered with an insulating liner (142). An inter-gate insulating film (144) may be disposed on the insulating liner (142).

[0075] As illustrated in FIG. 8c, a plurality of recessed insulating spacers (119) covering the side walls of the lower source / drain region (230L) included in the source / drain region (230) may be disposed on the upper surface of the device isolation film (114). In exemplary embodiments, the plurality of recessed insulating spacers (119) may each be integrally connected with an adjacent outer insulating spacer (118). An air gap (AG) may be disposed in the space defined by the recessed insulating spacers (119), the adjacent source / drain region (230), and the device isolation film (114).

[0076] FIG. 9 is a cross-sectional view illustrating an integrated circuit element (200A) according to another embodiment of the technical concept of the present invention. FIG. 9 illustrates a partial configuration of a portion corresponding to the cross-section along the line X21 - X21' of FIG. 7. In FIG. 9, the same reference numerals as in FIG. 3a, FIG. 3b, FIG. 7, and FIG. 8a through FIG. 8c indicate the same components, and redundant descriptions thereof are omitted here.

[0077] Referring to FIG. 9, the integrated circuit element (200A) may have a configuration generally identical to that of the integrated circuit element (200) described with reference to FIG. 7 and FIG. 8a through FIG. 8c. However, the integrated circuit element (200A) may further include a plurality of source / drain contacts (184) disposed on a plurality of source / drain regions (230). Each of the plurality of source / drain contacts (184) may extend vertically (in the Z direction) between a pair of adjacent gate lines (GL2) among a plurality of gate lines (GL2).

[0078] A metal silicide film (182) may be interposed between the source / drain region (230) and the source / drain contact (184). Each of the source / drain contacts (184) may fill the inside of a contact hole (180H) that extends into the source / drain region (230) by penetrating the gate-to-gate insulating film (144) and the insulating liner (142) in the vertical direction (Z direction). The source / drain region (230) may be spaced apart from the source / drain contact (184) with the metal silicide film (182) in between. The source / drain region (230) may surround the bottom of each of the source / drain contacts (184) from the outside of the contact hole (180H).

[0079] In each of the plurality of source / drain regions (230), the upper source / drain region (230R) may include a portion interposed between the outer insulating spacer (118) and the source / drain contact (184). The upper source / drain region (230R) may include a portion in contact with the outer insulating spacer (118) and a portion in contact with the metal silicide film (182). In each of the plurality of source / drain regions (230), the lower source / drain region (230L) and the upper source / drain region (230R) may each include a portion in contact with the metal silicide film (182).

[0080] In each of the plurality of source / drain regions (230), the upper source / drain region (230R) may include a portion interposed between at least one gate line (GL2) selected from a pair of adjacent gate lines (GL2) among the plurality of gate lines (GL2) and the source / drain contact (184).

[0081] FIG. 10 is a cross-sectional view illustrating an integrated circuit element (200B) according to another embodiment of the technical concept of the present invention. FIG. 10 illustrates a partial configuration of a portion corresponding to the cross-section along line X21 - X21' of FIG. 7. In FIG. 10, the same reference numerals as in FIG. 3a, FIG. 3b, FIG. 7, and FIG. 8a through FIG. 8c indicate the same components, and redundant descriptions thereof are omitted here.

[0082] Referring to FIG. 10, the integrated circuit element (200B) may have a configuration generally identical to the integrated circuit element (200A) described with reference to FIG. 9. However, the integrated circuit element (200B) includes a source / drain region (230B) instead of the source / drain region (230) exemplified in FIG. 9.

[0083] The source / drain region (230B) may have a configuration generally identical to the source / drain region (230) described with reference to FIGS. 8a, 8c, and 9. However, the source / drain region (230B) includes a lower source / drain region (230LB) and an upper source / drain region (230RB).

[0084] The upper source / drain area (230RB) is in the lower source / drain area (230LB). 28 A content ratio greater than the content ratio of the Si element 28It may contain Si elements. The upper source / drain region (230RB) may have an upper surface at a vertical level (LV22) higher than the vertical level (LV21) of the uppermost surface of the main channel region (MCA). The boundary (230FB) between the lower source / drain region (230LB) and the upper source / drain region (230RB) may be at a vertical level lower than the vertical level (LV21) of the uppermost surface of the main channel region (MCA). The lower source / drain region (230LB) and the upper source / drain region (230RB) may each include a portion in contact with the main channel region (MCA). The upper source / drain region (230RB) may include a portion in contact with the outer insulating spacer (118). The upper source / drain region (230RB) may include a portion interposed in the space between a pair of adjacent gate lines (GL2) among a plurality of gate lines (GL2).

[0085] In the source / drain region (230B), the lower source / drain region (230LB) may be spaced apart from the metal silicide film (182) with the upper source / drain region (230RB) in between. The metal silicide film (182) may be in contact only with the upper source / drain region (230RB) among the lower source / drain region (230LB) and the upper source / drain region (230RB). A more detailed configuration of the constituent materials of the lower source / drain region (230LB) and the upper source / drain region (230RB), respectively, is as described with respect to the lower source / drain region (130L) and the upper source / drain region (130R) with reference to FIGS. 2a, 2c, and 2d.

[0086] FIG. 11 is a planar layout diagram for explaining an integrated circuit element (300) according to another embodiment of the technical concept of the present invention. In FIG. 11, the same reference numerals as in FIG. 1, FIG. 2a to 2d, FIG. 3a and FIG. 3b represent the same components, and redundant descriptions thereof are omitted here.

[0087] Referring to FIG. 11, the integrated circuit element (300) includes a plurality of pin-shaped active regions (FA) that protrude in a vertical direction (Z direction) from the substrate (102) and extend in a first horizontal direction (X direction), and a plurality of gate lines (160) that extend in a second horizontal direction (Y direction) on the plurality of pin-shaped active regions (FA). A plurality of nanosheet stacks (NSS) may be disposed on the pin surface of each of the plurality of pin-shaped active regions (FA) in the regions where the plurality of pin-shaped active regions (FA) and the plurality of gate lines (160) intersect. A plurality of field-effect transistors (TR) may be formed in the regions where the plurality of pin-shaped active regions (FA) and the plurality of gate lines (160) intersect on the substrate (102).

[0088] A plurality of source / drain regions (130) are disposed at a location adjacent to a gate line (160) on a plurality of pin-shaped active regions (FA), and a source / drain contact (184) configured to be connected to the source / drain region (130) may be disposed on some of the source / drain regions (130). A source / drain contact (184) may not be disposed on other of the source / drain regions (130).

[0089] In exemplary embodiments, the X31 - X31' line cross-sectional configuration of FIG. 11 may be the same or similar to any one of the cross-sectional configurations described with reference to FIG. 2a, FIG. 2d, FIG. 5, and FIG. 6. In exemplary embodiments, the X32 - X32' line cross-sectional configuration of FIG. 11 may be the same or similar to any one of the cross-sectional configurations described with reference to FIG. 3a, FIG. 3b, and FIG. 4.

[0090] FIG. 12 is a block diagram of an integrated circuit element (400) according to other embodiments of the technical concept of the present invention.

[0091] Referring to FIG. 12, the integrated circuit element (400) includes a substrate (102) having a first region (I) and a second region (II). The first region (I) and the second region (II) of the substrate (102) refer to different regions of the substrate (102) and may be regions that perform different operations on the substrate (102). The first region (I) and the second region (II) may be regions spaced apart from each other in the horizontal direction.

[0092] In exemplary embodiments, the first region (I) may be a region where devices operating in a low-power mode are formed, and the second region (II) may be a region where devices operating in a high-power mode are formed. In other exemplary embodiments, the first region (I) may be a region where a memory device or a non-memory device is formed, and the second region (II) may be a region where a peripheral circuit, such as an input / output device (I / O), is formed.

[0093] In exemplary embodiments, the first region (I) may be a region constituting a volatile memory device such as DRAM (Dynamic Random Access Memory) or SRAM (Static RAM), or a non-volatile memory device such as ROM (Read Only Memory), MROM (Mask ROM), PROM (Programmable ROM), EPROM (Erasable ROM), EEPROM (Electrically Erasable ROM), FRAM (Ferromagnetic ROM), PRAM (Phase change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), flash memory, etc. In other exemplary embodiments, the first region (I) may be a region where a non-memory device, such as a logic device, is formed. The logic device may include standard cells that perform a desired logical function, such as a counter or a buffer. The standard cell may include various types of logic cells that include a plurality of circuit elements, such as a transistor or a register. The above logic cell can be configured, for example, AND, NAND, OR, NOR, XOR (exclusive OR), XNOR (exclusive NOR), INV (inverter), ADD (adder), BUF (buffer), DLY (delay), FIL (filter), multiplexer (MXT / MXIT), OAI (OR / AND / INVERTER), AO (AND / OR), AOI (AND / OR / INVERTER), D flip-flop, reset flip-flop, master-slave flip-flop, latch, etc.

[0094] In the integrated circuit element (400), the pattern formation density in the second region (II) may be smaller than the pattern formation density in the first region. In exemplary embodiments, the first region (I) may include at least one structure selected from the structures described for the integrated circuit elements (100, 100A, 100B, 100C, 100D, 200, 200A, 200B, 300, 400) described with reference to FIGS. 1 to 11.

[0095] FIG. 13 is a cross-sectional view illustrating an exemplary configuration of the integrated circuit element (400) exemplified in FIG. 12.

[0096] Referring to FIG. 13, the first region (I) of the integrated circuit element (400) may include a structure having a configuration as described with reference to FIG. 8a. The second region (II) may include a structure having a configuration similar to that described with reference to FIG. 8a. However, a pair of gate lines (GL2) separated by a source / drain region (230) in the first region (I) may be separated by a first separation distance (W41) in the longitudinal direction of the pin-type active region (FB) (the first horizontal direction (X direction) in FIG. 13). Additionally, a source / drain region (430) may be disposed within a recess (R42) formed on the upper part of the pin-type active region (FB4) in the second region (II), and a pair of gate lines (GL42) separated by a source / drain region (430) may be disposed on the pin-type active region (FB4). In the second region (II), a pair of gate lines (GL42) may be spaced apart by a second spacing distance (W42) greater than the first spacing distance (W41) in the longitudinal direction (the first horizontal direction (X direction) in FIG. 13) of the pin-type active region (FB4). In this specification, the pin-type active region (FB) placed in the first region (I) may be referred to as the first pin-type active region, and the pin-type active region (FB4) placed in the second region (II) may be referred to as the second pin-type active region. In this specification, the gate line (GL2) placed in the first region (I) may be referred to as the first gate line, and the gate line (GL42) placed in the second region (II) may be referred to as the second gate line. Additionally, in this specification, the source / drain region (230) placed in the first region (I) may be referred to as the first source / drain region, and the source / drain region (430) placed in the second region (II) may be referred to as the second source / drain region. A more detailed configuration of the pin-type active region (FB4) and the gate line (GL42) is as described with reference to FIG. 1 and FIG. 2a through 2d for the pin-type active region (FA) and the gate line (160).

[0097] In the second region (II), the source / drain region (430) may be positioned between a pair of gate lines (GL42). The source / drain region (430) may include a lower source / drain region (430L) in contact with a pin-shaped active region (FB4) forming the inner wall of the recess (R42), and an upper source / drain region (430R) positioned on the lower source / drain region (430L) and integrally connected to the lower source / drain region (430L). The upper source / drain region (430R) in the lower source / drain region (430L). 28 A content ratio greater than the content ratio of the Si element 28 It may contain Si elements. The lower source / drain region (430L) and the upper source / drain region (430R) may each be in contact with the main channel region (MCA4).

[0098] In the source / drain region (430), the upper source / drain region (430R) may have an upper surface at a vertical level (LV42) lower than the vertical level (LV41) of the upper surface of the main channel region (MCA4). The boundary (430F) between the lower source / drain region (430L) and the upper source / drain region (430R) may be at a vertical level lower than the vertical level (LV41) of the upper surface of the main channel region (MCA4). The upper source / drain region (430R) may not include a portion interposed in the space between a pair of gate lines (GL42). A more detailed configuration of the constituent materials of the lower source / drain region (430L) and the upper source / drain region (430R) of the source / drain region (430) is as described for the lower source / drain region (130L) and the upper source / drain region (130R) with reference to FIG. 2a, FIG. 2c, and FIG. 2d.

[0099] An interface dielectric film (452) and a gate dielectric film (454) may be interposed between the main channel region (MCA4) and the gate line (GL42). In exemplary embodiments, the interface dielectric film (452) may be made of a silicon oxide film, and the gate dielectric film (454) may be made of a high dielectric film with a dielectric constant higher than that of the silicon oxide film. A more detailed configuration of the gate dielectric film (454) is generally the same as that described for the gate dielectric film (152) with reference to FIGS. 2A, 2B, and 2B. A plurality of field-effect transistors (TR4) may be formed at the intersection of the pin-shaped active region (FB4) and the gate line (GL42).

[0100] Each sidewall of a pair of gate lines (GL42) may be covered with an insulating spacer (118). The insulating spacer (118) may cover both sidewalls of the gate lines (GL42) on the upper surface of the main channel region (MCA4). The source / drain region (430) may each include a portion that overlaps the insulating spacer (118) in a vertical direction (Z direction). The source / drain region (430) and the plurality of insulating spacers (118) may each be covered with an insulating liner (142). An inter-gate insulating film (144) may be placed over the insulating liner (142).

[0101] FIG. 14 is a cross-sectional view illustrating an exemplary configuration of an integrated circuit element (400A), which is a modified example of the integrated circuit element (400) exemplified in FIG. 13.

[0102] Referring to FIG. 14, the integrated circuit element (400A) may have a configuration generally identical to that of the integrated circuit element (400) described with reference to FIG. 12 and FIG. 13. However, the first region (I) of the integrated circuit element (400A) may include a structure having a configuration as described with reference to FIG. 9. The second region (II) may include a structure having a configuration similar to that described for the structure formed in the second region (II) with reference to FIG. 13. However, the integrated circuit element (400A) may further include a source / drain contact (484) disposed on the source / drain region (430) in the second region (II). The source / drain contact (484) may extend vertically (Z direction) between a pair of adjacent gate lines (GL42).

[0103] A metal silicide film (482) may be interposed between the source / drain region (430) and the source / drain contact (484). The source / drain contact (484) may fill the inside of a contact hole (480H) that extends into the source / drain region (430) by penetrating the gate-to-gate insulating film (144) and the insulating liner (142) in the vertical direction (Z direction). The source / drain region (430) may be spaced apart from the source / drain contact (484) with the metal silicide film (482) in between. The source / drain region (430) may surround the bottom of each of the plurality of source / drain contacts (484) from the outside of the contact hole (480H). In the source / drain region (430), the lower source / drain region (430L) and the upper source / drain region (430R) may each include a portion in contact with the metal silicide film (482). A more detailed configuration of the metal silicide film (482) and the source / drain contact (484) is as described with reference to FIGS. 3a and 3b for the metal silicide film (182) and the source / drain contact (184).

[0104] FIG. 15 is a series of cross-sectional views illustrating an exemplary configuration of an integrated circuit element (400B), which is another variation of the integrated circuit element (400) exemplified in FIG. 13.

[0105] Referring to FIG. 15, the integrated circuit element (400B) may have a configuration generally identical to that of the integrated circuit element (400) described with reference to FIG. 12 and FIG. 13. However, in the integrated circuit element (400B), the first region (I) may include a structure having a configuration as described with reference to FIG. 10. The second region (II) may include a structure having a configuration similar to that described with reference to FIG. 14 regarding the structure formed in the second region (II). However, the integrated circuit element (400B) includes a source / drain region (430B) in the second region (II) instead of the source / drain region (430) exemplified in FIG. 14.

[0106] The source / drain area (430B) may have a configuration generally identical to the source / drain area (430) described with reference to FIG. 14. However, the source / drain area (430B) includes a lower source / drain area (430LB) and an upper source / drain area (430RB). The upper source / drain area (430RB) is in the lower source / drain area (430LB). 28 A content ratio greater than the content ratio of the Si element 28 It may contain Si elements.

[0107] The upper source / drain region (430RB) may have an upper surface at a vertical level (LV42) lower than the vertical level (LV41) of the uppermost surface of the main channel region (MCA4). The boundary (430FB) between the lower source / drain region (430LB) and the upper source / drain region (430RB) may be at a vertical level lower than the vertical level (LV41) of the uppermost surface of the main channel region (MCA4) and lower than the vertical level of the lowest portion of the metal silicide film (482). The lower source / drain region (430LB) and the upper source / drain region (430RB) may each include a portion in contact with the main channel region (MCA4). The upper source / drain region (430RB) may not include a portion interposed in the space between a pair of gate lines (GL42).

[0108] In the source / drain region (430B), the lower source / drain region (430LB) may be spaced apart from the metal silicide film (482) with the upper source / drain region (430RB) in between. The metal silicide film (482) may be in contact only with the upper source / drain region (430RB) among the lower source / drain region (430LB) and the upper source / drain region (430RB). A more detailed configuration of the constituent materials of the lower source / drain region (430LB) and the upper source / drain region (430RB), respectively, is as described for the lower source / drain region (130L) and the upper source / drain region (130R) with reference to FIGS. 2a, 2c, and 2d.

[0109] According to an integrated circuit device according to embodiments of the technical concept of the present invention, the upper local region of the source / drain region includes an upper source / drain region having a raised upper surface. Accordingly, in the manufacturing process of the integrated circuit device, an electrical connection process between the source / drain region and a wiring structure formed thereon, such as a source / drain contact, can be easily performed, and thereby the reliability of the electrical connection between the source / drain region and the wiring structure connected to the source / drain region thereon can be improved. Accordingly, the performance of a field-effect transistor including the source / drain region can be improved, and the reliability of the integrated circuit device including the source / drain region can be improved.

[0110] FIGS. 16a to 16k are single drawings illustrated in the order of process to explain a method for manufacturing an integrated circuit element according to embodiments of the technical concept of the present invention. An exemplary method for manufacturing an integrated circuit element (100) illustrated in FIGS. 1 and FIGS. 2a to 2d is described with reference to FIGS. 16a to 16k. In FIGS. 16a to 16k, the same reference numerals as in FIGS. 1 and FIGS. 2a to 2d indicate the same components, and a detailed description thereof is omitted here.

[0111] Referring to FIG. 16a, a plurality of sacrificial semiconductor layers (104) and a plurality of nanosheet semiconductor layers (NS) are alternately stacked one by one on a substrate (102), and then a portion of the plurality of sacrificial semiconductor layers (104), the plurality of nanosheet semiconductor layers (NS), and the substrate (102) is etched to define a plurality of fin-shaped active regions (FA) on the substrate (102). After that, a device isolation film (114) (see FIG. 1) covering the sidewalls of each of the plurality of fin-shaped active regions (FA) can be formed. The upper surface of the device isolation film (114) can be at a level approximately the same or similar to the fin surface (FT) of the fin-shaped active region (FA). A stacked structure of a plurality of sacrificial semiconductor layers (104) and a plurality of nanosheet semiconductor layers (NS) may remain on the fin surface (FT) of each of the plurality of fin-shaped active regions (FA).

[0112] A plurality of sacrificial semiconductor layers (104) and a plurality of nanosheet semiconductor layers (NS) may be made of semiconductor materials with different etching selectivity ratios. In exemplary embodiments, a plurality of nanosheet semiconductor layers (NS) may be made of Si layers, and a plurality of sacrificial semiconductor layers (104) may be made of SiGe layers. In exemplary embodiments, the Ge content within the plurality of sacrificial semiconductor layers (104) may be constant. The SiGe layers constituting the plurality of sacrificial semiconductor layers (104) may have a constant Ge content selected within the range of about 5 atomic% to about 60 atomic%, for example, about 10 atomic% to about 40 atomic%. The Ge content within the SiGe layers constituting the plurality of sacrificial semiconductor layers (104) may be selected in various ways as needed.

[0113] Referring to FIG. 16b, a plurality of dummy gate structures (DGS) can be formed on a stacked structure of a plurality of sacrificial semiconductor layers (104) and a plurality of nanosheet semiconductor layers (NS).

[0114] A plurality of dummy gate structures (DGS) may each be formed to extend long in a second horizontal direction (Y direction). Each of the plurality of dummy gate structures (DGS) may have a structure in which an oxide film (D122), a dummy gate layer (D124), and a capping layer (D126) are stacked in sequence. In exemplary embodiments, the dummy gate layer (D124) may be made of polysilicon, and the capping layer (D126) may be made of a silicon nitride film.

[0115] Referring to FIG. 16c, after forming a plurality of outer insulating spacers (118) covering both side walls of each of a plurality of dummy gate structures (DGS), the plurality of dummy gate structures (DGS) and the plurality of outer insulating spacers (118) are used as etching masks to etch a portion of each of a plurality of sacrificial semiconductor layers (104) and a plurality of nanosheet semiconductor layers (NS) and a portion of a fin-shaped active region (FA), thereby dividing the plurality of nanosheet semiconductor layers (NS) into a plurality of nanosheet stacks (NSS) and forming a plurality of recesses (R1) on the upper part of the fin-shaped active region (FA). Each of the plurality of nanosheet stacks (NSS) may include a first nanosheet (N1), a second nanosheet (N2), and a third nanosheet (N3). To form the plurality of recesses (R1), etching may be performed using dry etching, wet etching, or a combination thereof.

[0116] Referring to FIG. 16d, a plurality of preliminary source / drain regions (P130) can be formed on the pin-shaped active region (FA) on both sides of each of the plurality of nanosheet stacks (NSS).

[0117] In exemplary embodiments, a plurality of preliminary source / drain regions (P130) may consist of a Si layer doped with an n-type dopant, a SiC layer doped with an n-type dopant, or a SiGe layer doped with a p-type dopant. The plurality of preliminary source / drain regions (P130) 28 Si, 29 Si, and 30It may include at least one silicon isotope selected from silicon isotopes consisting of Si. Within a plurality of preliminary source / drain regions (P130) 28 The content ratio of Si elements in naturally occurring Si films 28 It may be a level of the content ratio of the Si element. For example, within a plurality of preliminary source / drain regions (P130). 28 The content ratio of the Si element may be less than 10 atomic%, less than 15 atomic%, less than 20 atomic%, less than 25 atomic%, less than 30 atomic%, or less than 35 atomic%, but is not limited thereto. After a plurality of preliminary source / drain regions (P130) are formed, the vertical level (LV0) of the uppermost surface of each of the plurality of preliminary source / drain regions (P130) may be equal to or higher than the vertical level (LV1) of the uppermost surface of the third nanosheet (N3).

[0118] In exemplary embodiments, to form a plurality of preliminary source / drain regions (P130), a semiconductor material can be epitaxially grown from the surface of a fin-shaped active region (FA) exposed at the bottom of a recess (R1), the sidewalls of each of the first nanosheet (N1), the second nanosheet (N2), and the third nanosheet (N3), and the sidewalls of each of the plurality of sacrificial semiconductor layers (104).

[0119] In exemplary embodiments, to form a plurality of preliminary source / drain regions (P130), a low-pressure chemical vapor deposition (LPCVD) process, a selective epitaxial growth (SEG) process, or a cyclic deposition and etching (CDE) process may be performed using raw materials containing an elemental semiconductor precursor. The elemental semiconductor precursor may include elements such as Si, Ge, etc.

[0120] In exemplary embodiments, a plurality of preliminary source / drain regions (P130) may consist of a SiGe layer doped with a p-type dopant. A Si source and a Ge source may be used to form the SiGe layer doped with the p-type dopant. As the Si source, silane (SiH4), disilane (Si2H6), trisilane (Si3H8), dichlorosilane (SiH2Cl2), etc. may be used. As the Ge source, germane (GeH4), disemane (Ge2H6), trigermaine (Ge3H8), tetragermaine (Ge4H 10 ), dichlorogermaine (Ge2H2Cl2), etc. can be used. The above p-type dopant can be selected from B (boron) and Ga (gallium).

[0121] In other exemplary embodiments, a plurality of preliminary source / drain regions (P130) may be composed of a Si layer doped with an n-type dopant. At least one of the Si sources exemplified above may be used to form the Si layer doped with the n-type dopant. The n-type dopant may be selected from P (phosphorus), As (arsenic), and Sb (antimony).

[0122] Referring to FIG. 16e, in the result of FIG. 16d in which a plurality of preliminary source / drain regions (P130) are formed, a plurality of dummy gate structures (DGS) are used as ion implantation masks, and on top of each of the plurality of preliminary source / drain regions (P130) 28 Si element ions (510) can be injected. As a result, a plurality of source / drain regions (130), each comprising a lower source / drain region (130L) and an upper source / drain region (130R), can be obtained from a plurality of preliminary source / drain regions (P130).

[0123] In each of the plurality of source / drain regions (130), the upper source / drain region (130R) is among the preliminary source / drain region (P130) illustrated in FIG. 16d 28As a region into which Si element ions (510) are injected, the region injected into the upper part of the preliminary source / drain region (P130). 28 The volume of the upper portion of the preliminary source / drain region (P130) may be the result of swelling caused by Si elemental ions (510). In each of the plurality of source / drain regions (130), the lower source / drain region (130L) is of the preliminary source / drain region (P130) illustrated in FIG. 16d 28 Si element ions (510) are not injected 28 It may be a region not affected by Si element ions (510). In each of the multiple source / drain regions (130), the upper source / drain region (130R) may have an upper surface at a vertical level (LV2) higher than the vertical level (LV1) of the uppermost surface of the third nanosheet (N3).

[0124] In exemplary embodiments, on top of each of the plurality of preliminary source / drain regions (P130) 28 SiF4, SiH4, Si2H6, etc. can be used as a Si source to inject Si element ions (510), but are not limited to these. On the upper part of each of the plurality of preliminary source / drain regions (P130). 28 The process of implanting Si element ions (510) can be performed under various temperature conditions. In exemplary embodiments, on top of each of a plurality of preliminary source / drain regions (P130) 28 The process of injecting Si element ions (510) can be performed at room temperature, for example, at a temperature of about 1°C to about 35°C, but is not limited thereto.

[0125] In each of the plurality of source / drain regions (130) obtained by performing the process as described with reference to FIG. 16e 28 At least some of the upper source / drain region (130R) obtained by injecting Si elemental ions (510) 28It may include a portion amorphous by the injection of Si element ions (510). Each of the amorphous portions of the plurality of source / drain regions (130) may be crystallized through various processes involving heat in a subsequent process.

[0126] As described with reference to FIG. 16e, by forming a plurality of source / drain regions (130), each comprising an upper source / drain region (130R) in which the vertical level of the uppermost surface is raised from a plurality of preliminary source / drain regions (P130), the main part for applying a desired stress to the channel region among the preliminary source / drain regions (P130) (see FIG. 16d) is 28 The lower source / drain region (130L) can remain unaffected by the adverse effects of Si element ions (510), and when performing an etching process to form a contact hole (e.g., a contact hole (180H) for forming a source / drain contact (184) exemplified in FIG. 3a) on the source / drain region (130) in a subsequent process, the upper source / drain region (130R) can provide a sufficient etching margin so that the contact hole can reach the interior of the source / drain region (130). Thus, the plurality of source / drain regions (130) can contribute to improving the reliability of the integrated circuit device obtained as a final product.

[0127] Referring to FIG. 16f, an insulating liner (142) is formed to cover the result of FIG. 16e in which a plurality of source / drain regions (130) are formed, and a gate-to-gate insulating film (144) is formed on the insulating liner (142). Then, the insulating liner (142) and the gate-to-gate insulating film (144) can be flattened to expose the upper surface of the capping layer (D126).

[0128] Referring to FIG. 16g, the capping layer (D126) can be removed from the result of FIG. 16f to expose the upper surface of the dummy gate layer (D124), and the insulating liner (142) and the gate insulating film (144) can be partially removed so that the upper surface of the gate insulating film (144) and the upper surface of the dummy gate layer (D124) are at approximately the same level.

[0129] Referring to FIG. 16h, a gate space (GS) can be provided by removing the dummy gate layer (D124) and the oxide film (D122) underneath it from the result of FIG. 16g, and a plurality of nanosheet stacks (NSS) can be exposed through the gate space (GS).

[0130] Referring to FIG. 16i, the multiple sacrificial semiconductor layers (104) remaining on the fin-shaped active region (FA) in the result of FIG. 16h can be removed through the gate space (GS), thereby extending the gate space (GS) to the space between each of the first nanosheet (N1), the second nanosheet (N2), and the third nanosheet (N3), and to the space between the first nanosheet (N1) and the fin surface (FT).

[0131] In exemplary embodiments, to selectively remove a plurality of sacrificial semiconductor layers (104), the difference in etching selectivity between the first nanosheet (N1), the second nanosheet (N2), and the third nanosheet (N3) and the plurality of sacrificial semiconductor layers (104) may be utilized. A liquid or gaseous etchant may be used to selectively remove a plurality of sacrificial semiconductor layers (104). In exemplary embodiments, to selectively remove a plurality of sacrificial semiconductor layers (104), a CH3COOH-based etchant, for example, an etchant composed of a mixture of CH3COOH, HNO3, and HF, or an etchant composed of a mixture of CH3COOH, H2O2, and HF may be used, but is not limited to those exemplified above.

[0132] After that, a gate dielectric film (152) can be formed covering the exposed surfaces of each of the first nanosheet (N1), the second nanosheet (N2), and the third nanosheet (N3) and the pin-shaped active region (FA). An atomic layer deposition (ALD) process can be used to form the gate dielectric film (152).

[0133] Referring to FIG. 16j, a gate-forming conductive layer (160L) can be formed on the gate dielectric film (152) of FIG. 16i, covering the upper surface of the gate-inter-gate insulating film (144) while filling the gate space (GS) (see FIG. 16h). The gate-forming conductive layer (160L) may be made of a metal, a metal nitride, a metal carbide, or a combination thereof. An ALD process or a CVD process may be used to form the gate-forming conductive layer (160L).

[0134] Referring to FIG. 16k, the gate line (160) can be formed by partially removing the gate forming conductive layer (160L) and the gate dielectric film (152) from the upper surface so that the upper surface of the gate inter-insulating film (144) in the result of FIG. 16j is exposed and a portion of the upper side of the gate space (GS) is emptied again. At this time, a portion of each of the plurality of outer insulating spacers (118) is also consumed from their respective upper sides so that the height of each of the plurality of outer insulating spacers (118) can be lowered. After that, a capping insulating pattern (164) that fills the gate space (GS) can be formed on the gate line (160).

[0135] For the above, an exemplary method of manufacturing an integrated circuit element (100) exemplified in FIGS. 1 and FIGS. 2a to 2d has been described with reference to FIGS. 16a to 16k. However, those skilled in the art will understand that, within the scope of the technical concept of the present invention, various modifications and changes can be made to manufacture the integrated circuit elements exemplified in FIGS. 3a to 15 and integrated circuit elements having various structures modified and changed from them.

[0136] Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications and changes are possible by those skilled in the art within the technical spirit and scope of the present invention. Explanation of the symbols

[0137] 102: Substrate, 130: Source / drain region, 130L: Lower source / drain region, 130R: Upper source / drain region, 130F: Boundary.

Claims

Claim 1 A source / drain region comprising a pin-shaped active region extending in a first horizontal direction on a substrate, a channel region disposed on the pin-shaped active region, a gate line extending in a second horizontal direction intersecting the first horizontal direction and surrounding the channel region on the pin-shaped active region, and a source / drain region disposed at a position adjacent to the gate line on the pin-shaped active region and having a sidewall facing the channel region, wherein the source / drain region has a bottom surface in contact with the pin-shaped active region. 28 Si, 29 Si, and 30 A lower source / drain region comprising at least one silicon isotope selected from silicon isotopes consisting of Si, and a lower source / drain region integrally connected to the lower source / drain region on the lower source / drain region, wherein in the lower source / drain region 28 A content ratio greater than the content ratio of the Si element 28 An integrated circuit device comprising an upper source / drain region containing Si elements. Claim 2 In claim 1, the upper source / drain region is an integrated circuit element having an upper surface at a vertical level higher than the vertical level of the uppermost surface of the channel region. Claim 3 In claim 1, the upper source / drain region is an integrated circuit element having an upper surface at a vertical level lower than the vertical level of the uppermost surface of the channel region. Claim 4 An integrated circuit device according to claim 1, further comprising an outer insulating spacer covering the sidewall of the gate line, a gate-to-gate insulating film covering the source / drain region and the outer insulating spacer, a source / drain contact having a bottom portion that penetrates the gate-to-gate insulating film in a vertical direction on the source / drain region and is surrounded by the source / drain region, and a metal silicide film interposed between the source / drain contact and the source / drain region, wherein the upper source / drain region includes a portion in contact with the outer insulating spacer and a portion in contact with the metal silicide film. Claim 5 An integrated circuit device according to claim 1, wherein the channel region comprises at least one nanosheet disposed on the fin-shaped active region, the gate line comprises a portion surrounding the at least one nanosheet on the fin-shaped active region, and the upper source / drain region comprises a portion in contact with the at least one nanosheet. Claim 6 An integrated circuit device according to claim 1, wherein the channel region includes a main channel region integrally connected to the pin-type active region at the top of the pin-type active region, and the upper source / drain region includes a portion in contact with the main channel region. Claim 7 A pin-shaped active region extending in a first horizontal direction on a substrate, a recess formed in the pin-shaped active region, a pair of channel regions disposed on the pin-shaped active region with the recess in between, a pair of gate lines extending in a second horizontal direction intersecting the first horizontal direction on the pin-shaped active region and spaced apart in the first horizontal direction with the recess in between, and a source / drain region disposed within the recess and in contact with the pair of channel regions, wherein the source / drain region has a bottom surface in contact with the pin-shaped active region. 28 Si, 29 Si, and 30 A lower source / drain region comprising at least one silicon isotope selected from silicon isotopes consisting of Si, and a lower source / drain region integrally connected to the lower source / drain region on the lower source / drain region, wherein in the lower source / drain region 28 A content ratio greater than the content ratio of the Si element 28 An integrated circuit device comprising an upper source / drain region containing Si elements. Claim 8 An integrated circuit device according to claim 7, further comprising a source / drain contact having a bottom portion that is vertically extended between the pair of gate lines and surrounded by the source / drain region, and a metal silicide film interposed between the source / drain contact and the source / drain region, wherein the lower source / drain region and the upper source / drain region each comprise a portion in contact with the metal silicide film. Claim 9 A plurality of pin-shaped active regions disposed on a substrate, a plurality of recesses formed on the upper portion of each of the plurality of pin-shaped active regions, a plurality of channel regions disposed on the plurality of pin-shaped active regions, a plurality of gate lines disposed on the plurality of channel regions and extending in a second horizontal direction intersecting a first horizontal direction, a plurality of source / drain regions disposed within the plurality of recesses, a plurality of source / drain contacts disposed on the plurality of source / drain regions and each having a bottom portion surrounded by one source / drain region selected among the plurality of source / drain regions, and a plurality of metal silicide films interposed between the plurality of source / drain regions and the plurality of source / drain contacts, wherein the plurality of source / drain regions each have a bottom surface in contact with one pin-shaped active region selected among the plurality of pin-shaped active regions. 28 Si, 29 Si, and 30 A lower source / drain region comprising at least one silicon isotope selected from silicon isotopes consisting of Si, and a lower source / drain region integrally connected to the lower source / drain region on the lower source / drain region, wherein in the lower source / drain region 28 A content ratio greater than the content ratio of the Si element 28 An integrated circuit device comprising an upper source / drain region containing Si elements. Claim 10 An integrated circuit element according to claim 9, wherein the pin-shaped active region comprises a first pin-shaped active region disposed in a first region of the substrate and a second pin-shaped active region disposed in a second region of the substrate, and the plurality of gate lines comprises a pair of first gate lines disposed on the first pin-shaped active region in the first region and spaced apart from each other by a first distance, and a pair of second gate lines disposed on the second pin-shaped active region in the second region and spaced apart from each other by a second distance greater than the first distance, and the plurality of source / drain regions comprises a first source / drain region disposed between the pair of first gate lines in the first region and a second source / drain region disposed between the pair of second gate lines in the second region, wherein the upper source / drain region of the first source / drain region comprises a portion interposed between the pair of first gate lines, and the upper source / drain region of the second source / drain region does not comprise a portion interposed between the pair of second gate lines.

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