A vertical structure memory device of a two-dimensional material channel layer and its manufacturing method

Abstract

The present invention relates to a vertical memory device, and more specifically, to a memory device comprising a channel layer based on a two-dimensional material.

Description

Technology Field

[0001] The present invention relates to a vertical memory device, and more specifically, to a memory device comprising a channel layer based on a two-dimensional material. Background Technology

[0003] 3D vertical structure NAND Flash memory is a non-volatile flash memory that stacks cells vertically to improve storage density. As the miniaturization and integration of 2D planar NAND Flash memory devices have reached their limits, a 3D vertical NAND Flash structure has been proposed.

[0004] Vertical structure NAND flash memory increases integration density by stacking cells vertically, enabling the storage of more data per unit area, which can lead to an increase in storage capacity.

[0005] However, technical limitations resulting from manufacturing process complexity, costs, and the increasing number of layers require continuous innovation and improvement.

[0006] The vertical NAND flash memory channel layer conducts current and significantly impacts the performance and reliability of the memory device. Two-dimensional materials that are thinner and more flexible than conventional bulk semiconductors (Si-based) are being researched; in particular, due to their thin thickness and unique electrical properties, they are suitable for 3D stacking technology and high-density integrated memory.

[0007] However, technical limitations regarding manufacturing processes, interface quality, and process compatibility exist for commercialization, and research is currently required to develop new process technologies, improve contact resistance, and enhance reliability to address these issues. Prior art literature

[0009] Republic of Korea Published Patent Application No. 10-2024-0037733 The problem to be solved

[0010] The objective of the present invention is to provide a vertical structure memory device having a channel layer (channel film) based on a two-dimensional material through a simple process. means of solving the problem

[0012] To achieve the above objective, a vertical structure memory device according to one embodiment of the present invention comprises: a substrate; a stacked structure formed on the substrate, wherein a plurality of conductive layers and insulating layers are sequentially formed in a vertical direction; and a vertical channel structure formed in a vertical direction of the stacked structure, wherein the vertical channel structure comprises: a blocking film formed on the sidewall of the stacked structure; a vertical charge storage film formed on the blocking film; a tunneling film formed on the vertical charge storage film; a vertical channel film based on a two-dimensional material formed on the tunneling film; and a filling oxide film formed on the vertical channel film.

[0013] The above-mentioned laminated structure may have an oxide-nitride-oxide (ONO) laminated structure.

[0014] A vertical structure memory irradiation according to one embodiment of the present invention comprises the steps of: forming a stacked structure on a substrate; etching the stacked structure in a vertical direction to form a vertical channel hole; sequentially forming a blocking film and a vertical charge storage film that are continuous with respect to the sidewall of the stacked structure inside the vertical channel hole and the surface of the substrate; sequentially depositing a tunneling film, a vertical channel film based on a two-dimensional material, and a filling oxide film on the vertical charge storage film to manufacture a vertical structure; and performing photothermal treatment on the vertical structure to crystallize the two-dimensional material of the vertical channel film.

[0015] The above photothermal treatment may involve depositing metal on the upper part of the vertical structure and then performing two-dimensional material crystallization.

[0016] The above-mentioned laminated structure may have an oxide-nitride-oxide (ONO) laminated structure. Effects of the invention

[0018] The present invention has the effect of providing a two-dimensional material-based channel membrane through a simple process.

[0019] In addition, by forming a two-dimensional material that can be deposited with an amorphous thickness, it is possible to achieve high mobility. Brief explanation of the drawing

[0021] FIG. 1 illustrates a structural diagram of a vertical structure memory device according to one embodiment of the present invention. FIG. 2 illustrates a cross-section of a vertical structure of a vertical structure memory device according to one embodiment of the present invention. FIGS. 3 and 4 illustrate a process flow diagram of a method for manufacturing a vertical structure memory device according to an embodiment of the present invention. Specific details for implementing the invention

[0022] Hereinafter, embodiments of the present invention are described in detail so that those skilled in the art can easily implement the invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0024] Referring to FIG. 1, a vertical structure memory device (10) according to one embodiment of the present invention includes a substrate (100); a stacked structure (200) formed on the substrate (100); and a vertical structure (300) formed in the vertical direction of the stacked structure (200). The vertical structure memory device (10) according to one embodiment of the present invention may be a vertical NAND flash memory device.

[0026] The substrate (100) may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate (100) may contain impurities, and the impurities may include p-type impurities (e.g., boron (B)) or n-type impurities (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.).

[0027] The laminated structure (200) is disposed on the substrate (100), and the surface of the substrate (100) on which the laminated structure (200) is disposed may be referred to as the front side or top surface of the substrate (100).

[0028] The stacked structure (200) may include conductive lines and insulating lines, and may form a memory cell array by alternately forming conductive lines and insulating lines.

[0029] The laminated structure (200) may have a first insulating layer (210) and a second insulating layer (220) sequentially laminated therein. The first insulating layer (210) is intended to block charge to prevent charge leakage and minimize interference between cells, and the second insulating layer (220) may serve as a charge storage layer to provide insulation while trapping electrons and storing data. The second insulating layer (220) may have a relatively higher dielectric constant than the first insulating layer (210). In this case, the first insulating layer (210) and the second insulating layer (220) may be used as insulating lines.

[0030] For example, the first insulating layer (210) may be silicon oxide (SiO2), and the second insulating layer (220) may be silicon nitride (Si3N4). More specifically, the laminated structure (200) may be an ONO (oxide-nitride-oxide) structure in which the silicon oxide (SiO2), which is the first insulating layer (210), is placed at the top and bottom respectively, and the silicon nitride (Si3N4), which is the second insulating layer (220), is placed in the middle.

[0032] Referring to FIG. 2, the vertical structure (300) includes a blocking film (310); a charge storage film (320); a tunneling film (330); a vertical channel film (340); and a filling oxide film (350).

[0033] The blocking film (310) may be disposed on the surface of a vertical sidewall of the stacked structure (200), and may be formed on the surface of one vertical sidewall of the stacked structure (200) and the surface of the other vertical sidewall of the stacked structure (200). As a result, the blocking film (310) may be disposed between the vertical sidewall of the stacked structure (200) and the charge storage film (320).

[0034] The blocking film (310) may include a high dielectric constant material. The high dielectric constant material may include, for example, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0035] The charge storage film (320) may be disposed on the surface of the blocking film (310), and more specifically, may be disposed on one vertical side wall of the blocking film (310) and the other vertical side wall of the blocking film (310).

[0036] The charge storage film (320) may be an insulator or a high dielectric material, and may be, for example, silicon nitride (Si3N4), hafnium oxide (HfO₂), aluminum oxide (Al₂O₃) or zirconium oxide (ZrO₂).

[0037] The tunneling film (330) provides a path for electrons to enter or be emitted from the storage layer through a tunneling effect by the gate voltage, thereby preventing electrons from escaping from the storage layer and maintaining data stably. It is designed so that charges are not trapped in the tunneling film itself, thereby increasing reliability in the repetitive program / erase (P / E) cycles of the memory cell.

[0038] The vertical channel membrane (340) may be disposed on the surface of the tunneling membrane (330) and the surface of the substrate (100), and more specifically, may be disposed continuously from one vertical side wall of the tunneling membrane (330) through the surface of the substrate (100) to the other vertical side wall of the tunneling membrane (330), and as an example, may have a “U” shape in cross-section.

[0039] The vertical channel film (340) may include semiconductor materials such as single-crystal silicon, polycrystalline silicon, organic semiconductors, and carbon nanostructures, but is not limited thereto.

[0040] The vertical channel membrane (340) may be a two-dimensional material, and the vertical channel membrane (340) may be a crystallized two-dimensional material. The two-dimensional material may be silicon (Si), molybdenum disulfide (MoS2), tungsten disulfide (WS2), black phosphorus (Phosphorene), graphene (Graphene), or carbon nanotubes (CNT).

[0041] The filling oxide film (350) is intended to fill empty spaces, and the filling oxide film (350) may be an insulating material, and may include silicon oxide, but is not limited thereto.

[0043] Referring to FIG. 3, a method for manufacturing a vertical structure memory device according to one embodiment of the present invention comprises the steps of: forming a stacked structure (200) on a substrate (100) (S110); etching the stacked structure (200) in a vertical direction to form a vertical channel hole (H) (S120); sequentially forming a blocking film (310) and a vertical charge storage film (320) that are continuous with respect to the sidewall of the stacked structure (200) inside the vertical channel hole (H) and the surface of the substrate (100) (S130); sequentially depositing a tunneling film (330), a vertical channel film (340) based on a two-dimensional material, and a filling oxide film (350) on the vertical charge storage film (320) to manufacture a vertical structure (300) (S140); and crystallizing the two-dimensional material of the vertical channel film (340) by photothermal treatment on the vertical structure (300) (S150).

[0045] S110 is a step of forming a stacked structure (200) on a substrate (100) of a vertical structure memory device.

[0046] In S110, the substrate (100) may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate (100) may contain impurities, said impurities may include p-type impurities (e.g., boron (B)) or n-type impurities (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.).

[0047] The laminated structure (200) is disposed on the substrate (100), and the surface of the substrate (100) on which the laminated structure (200) is disposed may be referred to as the front side or top surface of the substrate (100).

[0048] The stacked structure (200) may include conductive lines and insulating lines, and may form a memory cell array by alternately forming conductive lines and insulating lines.

[0049] The laminated structure (200) may have a first insulating layer (210) and a second insulating layer (220) sequentially laminated therein. The first insulating layer (210) is intended to block charge to prevent charge leakage and minimize interference between cells, and the second insulating layer (220) may serve as a charge storage layer to provide insulation while trapping electrons and storing data. The second insulating layer (220) may have a relatively higher dielectric constant than the first insulating layer (210). In this case, the first insulating layer (210) and the second insulating layer (220) may be used as insulating lines.

[0050] For example, the first insulating layer (210) may be silicon oxide (SiO2), and the second insulating layer (220) may be silicon nitride (Si3N4). More specifically, the laminated structure (200) may be an ONO (oxide-nitride-oxide) structure in which the silicon oxide (SiO2), which is the first insulating layer (210), is placed at the top and bottom respectively, and the silicon nitride (Si3N4), which is the second insulating layer (220), is placed in the middle.

[0052] S120 is a step of forming a vertical channel hole (H) through etching on a stacked structure (200) so that a vertical structure (300) can be provided.

[0053] S130 is a step of sequentially forming a blocking film (310) and a vertical charge storage film (320). The blocking film (310) may be disposed on the surface of a vertical sidewall of a stacked structure (200), and may be continuously formed from the upper surface of one vertical sidewall of the stacked structure (200) through the upper surface of the substrate (100) to the upper surface of the other vertical sidewall of the stacked structure (200), and may have a 'U' shape or a cup shape when observed in cross-section. Accordingly, the blocking film (310) may be disposed between the vertical sidewall of the stacked structure (200) and the charge storage film (320).

[0054] The blocking film (310) may include a high dielectric constant material. The high dielectric constant material may include, for example, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0055] The charge storage film (320) may be disposed on the surface of the blocking film (310), and more specifically, may be disposed continuously from the top of one vertical sidewall of the blocking film (310) through the lower surface of the blocking film (310) to the top of the other vertical sidewall of the blocking film (310). The charge storage film (320) may be an insulator or a high dielectric material, and may be, for example, silicon nitride (Si3N4), hafnium oxide (HfO₂), aluminum oxide (Al₂O₃), or zirconium oxide (ZrO₂).

[0056] S140 is a step of providing a vertical structure (300) in which a blocking film (310); a charge storage film (320); a tunneling film (330); a vertical channel film (340); and a filling oxide film (350) are sequentially formed in a vertical direction by stacking a tunneling film (330); a vertical channel film (340); and a filling oxide film (350) sequentially.

[0058] The tunneling film (330) provides a path for electrons to enter or be emitted from the storage layer through a tunneling effect by the gate voltage, thereby preventing electrons from escaping from the storage layer and maintaining data stably. It is designed so that charges are not trapped in the tunneling film itself, thereby increasing reliability in the repetitive program / erase (P / E) cycles of the memory cell.

[0059] The vertical channel membrane (340) may be disposed on the surface of the tunneling membrane (330) and the surface of the substrate (100), and more specifically, may be disposed continuously from one vertical side wall of the tunneling membrane (330) through the surface of the substrate (100) to the other vertical side wall of the tunneling membrane (330), and as an example, may have a “U” shape in cross-section.

[0060] More specifically, in S140, when a vertical channel film (340) is placed, etching is performed on the area stacked vertically with respect to the surface of the substrate (100) for the blocking film (310); charge storage film (320); and tunneling film (330) placed in the previous step, and after etching the blocking film (310); charge storage film (320); and tunneling film (330) until the surface of the substrate (100) is exposed, a vertical channel film (340) is deposited on the exposed surface of the substrate (100).

[0061] The vertical channel membrane (340) may be a two-dimensional material, and the vertical channel membrane (340) may be a crystallized two-dimensional material. The two-dimensional material may be silicon (Si), molybdenum disulfide (MoS2), tungsten disulfide (WS2), black phosphorus (Phosphorene), graphene (Graphene), or carbon nanotubes (CNT).

[0062] The filling oxide film (350) is intended to fill empty spaces, and the filling oxide film (350) may be an insulating material, and may include silicon oxide, but is not limited thereto.

[0064] S150 crystallizes the two-dimensional material of the vertical channel film (340) through photothermal treatment. The photothermal treatment may be performed through a photothermal lamp (L).

[0066] Referring to FIG. 4, S150 includes a step (S151) of depositing a metal (M) on top of a stacked structure (300); a step (S152) of crystallizing a two-dimensional material of a vertical channel film (340) by photothermal treatment of the metal (M); and a step (S153) of removing the metal (M).

[0067] The above metal (M) may be for efficiently transferring heat to the vertical channel membrane (340) during photothermal treatment according to the photothermal lamp (L).

[0068] The power of the above radiant lamp (L) is 5 to 60 J / cm 2 It could be.

[0070] In the present invention, the deposition of each unit component (stacked structure (200) (first insulating layer (210), second insulating layer (220)), blocking film (310), vertical charge storage film (320), tunneling film (330), vertical channel film (340), filling oxide film (350), and metal (M) in S110 to S150 may be performed by LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma-enhanced chemical vapor deposition), APCVD (Atmospheric Pressure Chemical Vapor Deposition), or MOCVD (Metal Organic Chemical Vapor Deposition).

[0072] The present invention will be described in detail below through examples. The following examples are intended only to aid in understanding the present invention and do not limit the scope of the present invention, and the same

[0074] Example 1. Method for manufacturing a vertical NAND flash memory device

[0075] A stacked structure is formed by sequentially stacking a SiO2 layer and a Si3N4 layer on a silicon substrate (Si wafer). The stacked structure forms an ONO (oxide-nitride-oxide) mold structure in which SiO2-Si3N4-SiO2 are sequentially stacked from the substrate by placing a SiO2 layer on the surface of the silicon substrate (Si wafer), placing a Si3N4 layer on the surface of the SiO2 layer, and then placing a SiO2 layer again on the Si3N4 layer.

[0076] Subsequently, after forming vertical channel holes through etching, a SiO2 layer is formed as a blocking film along the vertical sidewalls of the stacked structure formed along the vertical channel holes, and then a Si3N4 layer is formed as a vertical charge storage film on the surface of the blocking film.

[0077] Subsequently, SiO2 is sequentially deposited as a tunneling film and molybdenum disulfide (MoS2), an N-type 2D semiconductor material, as a vertical channel film to a thickness of 3 to 5 nm on the surface of the vertical charge storage film. After fabricating the vertical structure by depositing a filling oxide film (SiO2) into the empty space formed on the surface of the vertical channel film, a lamp power of a flash lamp (Xenon lamp) of 5 to 60 J / cm² is applied to the vertical structure while the substrate temperature is raised to 400 to 600 ℃. 2 A vertical NAND flash memory device is fabricated by crystallizing a two-dimensional material of a vertical channel film through photothermal treatment with lamp irradiation in a range of 10 to 50 irradiation shots.

[0078] In Example 1, the deposition of SiO2 and Si3N4 is performed at 700 to 800 ℃ via LPCVD (Low Pressure Chemical Vapor Deposition), and the deposition of molybdenum disulfide (MoS2) is performed at 500 to 600 ℃ via LPCVD.

[0080] Example 2. Method for manufacturing a vertical NAND flash memory device

[0081] The procedure was performed in the same manner as Example 1, but tungsten disulfide (WS2) was used as the vertical channel layer.

[0083] Although preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention. Explanation of the symbols

[0085] 10: Vertical structure memory device 100: Substrate 200: Laminated structure 300: Vertical structure

Claims

Claim 1 A substrate; a laminated structure formed on the substrate, wherein a plurality of conductive layers and insulating layers are sequentially formed in a vertical direction; and a vertical channel structure formed in a vertical direction of the laminated structure, wherein the vertical channel structure comprises a blocking film formed on the sidewall of the laminated structure; a vertical charge storage film formed on the blocking film; a tunneling film formed on the vertical charge storage film; a vertical channel film based on a two-dimensional material formed on the surface of the tunneling film and the substrate; and a filling oxide film formed on the vertical channel film, wherein the two-dimensional material is molybdenum disulfide (MoS2) or tungsten disulfide (WS2), and the two-dimensional material is a flash lamp with a lamp power of 5 to 60 J / cm² 2 A vertical structure memory device that is crystallized by photothermal treatment. Claim 2 A vertical structure memory device according to claim 1, wherein the stacked structure has an oxide-nitride-oxide (ONO) stacked structure. Claim 3 The method comprises the steps of: forming a stacked structure on a substrate; etching the stacked structure in a vertical direction to form a vertical channel hole; sequentially forming a blocking film and a vertical charge storage film that are continuous with respect to the sidewall of the stacked structure inside the vertical channel hole and the surface of the substrate; sequentially depositing a tunneling film, a vertical channel film based on a two-dimensional material, and a filling oxide film on the vertical charge storage film to manufacture a vertical structure; and crystallizing the two-dimensional material of the vertical channel film by photothermal treatment on the vertical structure, wherein the two-dimensional material is molybdenum disulfide (MoS2) or tungsten disulfide (WS2), and the photothermal treatment is performed using a flash lamp with a lamp power of 5 to 60 J / cm² 2 A method for manufacturing a vertical structure memory device, performed in Claim 4 A method for manufacturing a vertical structure memory device according to claim 3, wherein the photothermal treatment involves depositing a metal on the upper part of the vertical structure and then performing two-dimensional material crystallization. Claim 5 A method for manufacturing a vertical structure memory device, wherein, in claim 3 or 4, the stacked structure has an oxide-nitride-oxide (ONO) stacked structure. Claim 6 delete

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