Decoder; decoding method.

Abstract

Disclosed is a decoder. At least one computing unit of the decoder is configured to: acquire soft bit information to be decoded of a variable node n in a basic matrix; determine whether the number of decoding iterations i is less than a decoding iteration threshold; if yes, determine whether the number of decoding layers k is smaller than the number of rows a of the basic matrix; if it is determined that k is smaller than a, determine the soft bit information of the variable node n in a kth layer according to the soft bit information of the variable node n in a k-1th layer, and determine variable node information in a k+1th layer according to the soft bit information of the variable node n in the k-1th layer; determine check node information in the k+1th layer according to the variable node information in the k+1th layer; update k to k+1, re-determine whether k is smaller than a; if it is determined that k is greater than or equal to a, update i to i+1, and re-determine whether i is smaller than the decoding iteration threshold until i equals to the decoding iteration threshold. Also disclosed are a decoding method and a computer storage medium.

Description

Decoder, decoding method and computer storage medium

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 201810717244.X, filed on June 29, 2018, the entire contents of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to, but is not limited to, the technical field of decoders for quasi-cyclic low-density parity-check (QC-LDPC) codes in wireless communications. BACKGROUND

[0004] With the continuous development of multimedia broadcast, wireless communication, and very large scale integration (VLSI) technology, low-density parity-check (LDPC) codes, as the forward error correction code (FEC) closest to the Shannon limit, are selected as the data channel coding scheme for the enhanced mobile broadband (eMBB) service in the future fifth-generation (5G) mobile communication technology.

[0005] LDPC has been widely used in digital video broadcasting (DVB), wireless local area networks (WLAN), worldwide interoperability for microwave access (WiMAX), and other communication systems. In the future 5G mobile communication system, there are demands for large capacity, low latency, and high reliability services, as well as various different application scenarios. Designing a high-performance, low-cost, and flexible LDPC decoder has become a major technical challenge in this field.

[0006] In order to meet the high bit error rate performance and throughput rate performance of the LDPC decoder, the block error ratio (BLER) performance is required to be at least below 1E-3, the throughput rate is 10Gbps-20Gbps, the bit error rate performance needs reliable and complex decoding algorithm, and the improvement of the throughput rate performance needs very low decoding delay; most of the current LDPC decoders in the industry adopt the standard layered decoding method, the decoder adopting the method has the problem of memory access conflict in the iterative decoding process, which leads to the increase of the decoding delay and the low throughput rate, and it is difficult to meet the low delay requirement; it can be seen that the LDPC decoding method in the related art has the technical problem of low decoding efficiency when the standard layered decoding method is adopted.

[0007] SUMMARY

[0008] Therefore, the embodiments of the present application aim to provide a decoder, a method and a computer storage medium.

[0009] The technical scheme of the embodiments of the present application is implemented as follows:

[0010] In a first aspect, an embodiment of the present application provides a decoder, comprising at least one computing unit, wherein the computing unit is configured to: acquire soft bit information to be decoded of a variable node n in a base matrix of an LDPC code; wherein n is an integer greater than or equal to 0 and less than a column number b of the base matrix; determine whether a decoding iteration number i of the LDPC code is less than a preset decoding iteration threshold; when the decoding iteration number i is determined to be less than the decoding iteration threshold, determine whether a decoding layer number k of the LDPC code is less than a row number a of the base matrix; when the decoding layer number k is determined to be less than the row number a of the base matrix, determine soft bit information of a kth layer variable node n of the base matrix according to soft bit information of a (k-1)th layer variable node n of the base matrix, and determine variable node information of a (k+1)th layer variable node n to a check node m of the base matrix according to the soft bit information of the (k-1)th layer variable node n of the base matrix; determine check node information of the (k+1)th layer check node m to a variable node n of the base matrix according to the variable node information of the (k+1)th layer variable node n to the check node m of the base matrix; update the decoding layer number k to k+1, and re-perform the determination of whether the decoding layer number k of the LDPC code is less than the row number a of the base matrix; when the decoding layer number k is determined to be greater than or equal to the row number a of the base matrix, update the iteration number i to i+1, re-perform the determination of whether the decoding iteration number i of the LDPC code is less than the preset decoding iteration threshold, until the decoding iteration number i is equal to the decoding iteration threshold, and determine the soft bit information of the kth layer variable node n as a decoding result of the soft bit information to be decoded of the variable node n; wherein when an initial value of i is 0 and an initial value of k is 0, and when k=0 or 1, the soft bit information of the (k-1)th layer variable node n is the soft bit information to be decoded of the variable node n.

[0011] In a second aspect, the embodiments of the present application further provide a decoding method. The method is applied to at least one computing unit of a decoder, and includes: obtaining soft bit information to be decoded of a variable node n in a base matrix of an LDPC code; wherein n is an integer greater than or equal to 0 and smaller than a column number b of the base matrix; determining whether a decoding iteration number i of the LDPC code is smaller than a preset decoding iteration threshold; when it is determined that the decoding iteration number i is smaller than the decoding iteration threshold, determining whether a decoding layer number k of the LDPC code is smaller than a row number a of the base matrix; when it is determined that the decoding layer number k is smaller than the row number a of the base matrix, determining soft bit information of a kth layer variable node n of the base matrix according to soft bit information of a (k-1)th layer variable node n of the base matrix, and determining variable node information of a (k+1)th layer variable node n to a check node m of the base matrix according to the soft bit information of the (k-1)th layer variable node n; determining check node information of the (k+1)th layer check node m to a variable node n of the base matrix according to the variable node information of the (k+1)th layer variable node n to the check node m of the base matrix; updating the decoding layer number k to k+1, and re-executing the determination of whether the decoding layer number k of the LDPC code is smaller than the row number a of the base matrix; when it is determined that the decoding layer number k is greater than or equal to the row number a of the base matrix, updating the iteration number i to i+1, re-executing the determination of whether the decoding iteration number i of the LDPC code is smaller than the preset decoding iteration threshold, until the decoding iteration number i is equal to the decoding iteration threshold, and determining the soft bit information of the kth layer variable node n as a decoding result of the soft bit information to be decoded of the variable node n; wherein when an initial value of i is 0 and an initial value of k is 0, and when k=0 or 1, the soft bit information of the (k-1)th layer variable node n is the soft bit information to be decoded of the variable node n.

[0012] In a third aspect, the embodiments of the present application further provide a computer storage medium. The computer storage medium stores a computer program. When the computer program is executed by a processor, steps of a decoding method described in one or more of the above embodiments are implemented.

[0013] The decoder, the method and the computer storage medium provided in the embodiments of the present application first comprise at least one computing unit, which is configured to: acquire soft bit information of a variable node n to be decoded in a base matrix of an LDPC code, then determine whether the decoding iteration number i of the LDPC code is less than a preset decoding iteration number, if yes, determine whether the decoding layer number k of the LDPC code is less than the row number a of the base matrix, if yes, determine the soft bit information of the variable node n of the kth layer of the base matrix according to the soft bit information of the variable node n of the (k-1)th layer of the base matrix, and determine the variable node information of the variable node n to the check node m of the (k+1)th layer of the base matrix according to the soft bit information of the variable node n of the (k-1)th layer of the base matrix, and then determine the check node information of the check node m to the variable node n of the (k+1)th layer of the base matrix according to the variable node information of the variable node n to the check node m of the (k+1)th layer of the base matrix, so that the soft bit information of the variable node n of the kth layer is obtained, and the variable node information of the next layer is generated at the same time, and the check node information of the next layer is further generated, compared with the prior art, the variable node information and the check node information of the next layer are generated in advance, and the soft bit information of the variable node n of the next layer is prepared, so that the decoding speed can be accelerated, the soft bit information of the variable node n of the kth layer is obtained, k is updated to k+1, the decoding of the next layer is performed, and the iteration number i is updated to i+1, the iteration is performed, and the iteration number is equal to the preset iteration number, so that the soft bit information is obtained, that is, in the embodiments of the present application, the variable node information of the next layer is started and generated at the same time when the soft bit information of the variable node n of the kth layer of the base matrix is generated, and the check node information of the next layer is further generated, and then the soft bit information of the variable node n of the (k+1)th layer of the base matrix can be directly determined according to the soft bit information of the variable node n of the kth layer when the decoding of the (k+1)th layer is performed, compared with the related art, the calculation of the variable node information of the (k+1)th layer and the check node information of the (k+1)th layer can be started without waiting for the soft bit information of the variable node n of the kth layer to be generated, the decoding speed is accelerated, and the decoding efficiency of the LDPC decoding is further improved. BRIEF DESCRIPTION OF DRAWINGS

[0014] FIG. 1 is a schematic structural diagram of an optional decoder in the embodiments of the present application;

[0015] FIG. 2 is a schematic structural diagram of an optional computing unit in the embodiments of the present application;

[0016] FIG. 3 is a schematic arrangement diagram of an optional base matrix in the embodiments of the present application;

[0017] FIG. 4 is a schematic storage format diagram of an optional storage unit in the embodiments of the present application;

[0018] Fig. 5 is a schematic view of an optional structure of the storage unit in the embodiment of the present application;

[0019] Fig. 6 is a schematic view of an optional structure of the shift unit in the embodiment of the present application;

[0020] Fig. 7 is a schematic view of an optional structure of the routing unit in the embodiment of the present application;

[0021] Fig. 8 is a schematic view of an optional pipeline of the layered decoding in the embodiment of the present application;

[0022] Fig. 9 is a schematic view of an optional pipeline of the layer overlapping decoding in the embodiment of the present application;

[0023] Fig. 10 is a schematic view of a flow of the decoding method in the embodiment of the present application;

[0024] Fig. 11 is a schematic view of the structure of the computer storage medium in the embodiment of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application.

[0026] The related standard layered decoding method needs to complete the soft bit information update of the current layer first, and then the variable node information calculation of the next layer can be performed, which will affect the decoding speed of the LDPC decoding. The present application provides a decoder, and Fig. 1 is a schematic view of an optional structure of the decoder in the embodiment of the present application. As shown in Fig. 1, the decoder can include a format conversion unit, a storage unit, a forward shift unit, a reverse shift unit, a routing unit, a pipeline control unit and P calculation units, the numbers of the P calculation units are 0 to P-1 in turn; wherein P is the parallelism of the decoder, the number of the forward shift unit is equal to the number of the storage unit, and the number of the reverse shift unit is equal to the number of the storage unit; and the number of the storage unit is a positive integer greater than or equal to 2; wherein the calculation unit is configured to:

[0027] obtaining soft bit information to be decoded of a variable node n in a base matrix of an LDPC code; wherein n is an integer greater than or equal to 0 and less than a column number b of the base matrix; determining whether a decoding iteration number i of the LDPC code is less than a preset decoding iteration threshold; when the decoding iteration number i is determined to be less than the decoding iteration threshold, determining whether a decoding layer number k of the LDPC code is less than a row number a of the base matrix; when the decoding layer number k is determined to be less than the row number a of the base matrix, determining soft bit information of a kth layer variable node n of the base matrix according to soft bit information of a (k-1)th layer variable node n of the base matrix, and determining variable node information of a (k+1)th layer variable node n to a check node m of the base matrix according to the soft bit information of the (k-1)th layer variable node n; determining check node information of the (k+1)th layer check node m to the variable node n of the base matrix according to the variable node information of the (k+1)th layer variable node n to the check node m of the base matrix; updating the decoding layer number k to k+1, and re-executing the determination whether the decoding layer number k of the LDPC code is less than the row number a of the base matrix; when the decoding layer number k is determined to be greater than or equal to the row number a of the base matrix, updating the iteration number i to i+1, and re-executing the determination whether the decoding iteration number i of the LDPC code is less than the preset decoding iteration threshold, until the decoding iteration number i is equal to the decoding iteration threshold, and the soft bit information of the kth layer variable node n is determined as a decoding result of the soft bit information to be decoded of the variable node n; wherein when an initial value of i is 0 and an initial value of k is 0, and when k=0 or 1, the soft bit information of the (k-1)th layer variable node n is the soft bit information to be decoded of the variable node n.

[0028] Here, the QC-LDPC code is generally represented by a base matrix H(a×b) and a unit matrix of Z dimensions and a cyclic shift matrix thereof, and the base matrix H(a×b) and the unit matrix of Z dimensions and the cyclic shift matrix thereof or a zero matrix are used to represent an extended matrix H(Z*a×Z*b), which is a sparse parity check matrix of the QC-LDPC code. The matrix includes Z*a check nodes and Z*b variable nodes, Z is also called an extension factor of the base matrix, and Z is a positive integer.

[0029] For ease of description, i is defined as an iteration number index, which can represent from the 1st iteration to the maximum Max_iterth iteration; k is defined as a layer index of the base matrix H(a×b), which can represent from the 0th layer to the (a-1)th layer; m is defined as a check row index in a layer of the base matrix, which can represent from the 1st row to the Zth row; n is defined as a variable node index of the kth layer, n' is defined as a variable node index of the (k+1)th layer, n∈N(m) represents a set of all variable node indexes n connected to the check node m, and n'∈N(m) represents a set of all variable node indexes n' connected to the check node m, wherein 0≤n≤b-1 and 0≤n'≤b-1; and is defined as prior information of the kth layer variable node n; and variable node information from variable node n to check node m of the kth layer; define old check node information from check node m to variable node n of the kth layer, and define new check node information from check node m to variable node n of the kth layer.

[0030] Specifically, the computing unit can obtain the to-be-decoded soft bit information of the variable node n in the base matrix of the LDPC code from the preprocessing unit of the decoder. Before obtaining, the preprocessing unit first determines the to-be-decoded soft bit information of the variable node n. In order to generate the to-be-decoded soft bit information of the variable node n, in an optional embodiment, the decoder further comprises a preprocessing unit connected with the computing unit. Correspondingly, before the computing unit obtains the to-be-decoded soft bit information of the variable node n, the preprocessing unit determines the to-be-decoded soft bit information of the variable node n, which can include: obtaining the to-be-decoded soft bit information; preprocessing the to-be-decoded soft bit information to obtain the to-be-decoded soft bit information of the variable node n.

[0031] The preprocessing can include format conversion, storage, shifting and routing of the to-be-decoded soft bit information, so that the computing unit can obtain the to-be-decoded soft bit information of the variable node n. In order to realize the preprocessing of the to-be-decoded soft bit information, in an optional embodiment, the preprocessing unit can include a format conversion unit, a routing unit, at least one positive shifting unit and at least one storage unit; wherein the format conversion unit is connected to the at least one storage unit, the at least one storage unit is connected to the at least one positive shifting unit, the at least one positive shifting unit is connected to the routing unit, the routing unit is connected to the at least one computing unit, and the pipeline control unit is connected to the at least one positive shifting unit and the at least one computing unit respectively, and the positive shifting unit corresponds to the storage unit one by one; accordingly, the preprocessing unit preprocesses the to-be-decoded soft bit information to obtain the to-be-decoded soft bit information of the variable node n, which can include:

[0032] The format conversion unit divides the to-be-decoded soft bit information into at least one to-be-decoded soft bit information block, and sends the at least one to-be-decoded soft bit information block to the corresponding storage unit for storage; the storage unit receives the corresponding to-be-decoded soft bit information block and stores it in groups; the pipeline control unit determines that the positive shifting unit receives the to-be-decoded soft bit information, triggers the positive shifting unit, and the positive shifting unit performs positive cyclic shifting on the to-be-decoded soft bit information to obtain the shifted to-be-decoded soft bit information.

[0033] The routing unit outputs the shifted soft bit information of the to-be-decoded code word to at least one calculation unit according to a preset routing mode, so that the calculation unit obtains the to-be-decoded soft bit information of the variable node n.

[0034] Specifically, the format conversion unit is configured to divide the input soft bit information of the to-be-decoded code word with a length of Z*b into b soft bit information blocks, each of which contains Z soft bit information and corresponds to a Z-dimensional extension submatrix. Meanwhile, the format conversion unit stores each soft bit information block in a preset format according to the parallelism P and the value of Z, and inputs the soft bit information block after the format conversion to the storage unit. The format conversion process can be performed on the soft bit information block in a ping-pong manner.

[0035] The storage unit is configured to store the to-be-decoded soft bit information block. Each storage unit stores one or more soft bit information blocks and can simultaneously provide P soft bit information for parallel calculation of P check rows. The number n of the storage units is less than or equal to the number b of the basis matrix rows. v According to the orthogonal characteristic of the basis matrix row, the number b of the basis matrix rows can be less than or equal to the number n of the storage units.

[0036] The pipeline control unit is configured to determine that the positive shift unit receives the to-be-decoded soft bit information, and trigger the positive shift unit. The positive shift unit is configured to rotate and output the soft bit information output by the storage unit. The positive shift unit includes n v shift units. Each shift unit receives P soft bit information output by the corresponding storage unit, and completes positive cyclic shift output of the P soft bit information according to a preset shift value.

[0037] The routing unit is mainly configured to transmit the P soft bit information output by each shift unit to the data receiving port of the variable node calculation unit (VNU, Variable Node Unit) in the calculation unit according to a fixed routing connection mode, or configured to transmit the soft bit information output by each data port of the variable node soft bit information update unit (UPD, Updata) to each inverse shift unit according to a fixed routing connection mode. Each inverse shift unit receives P soft bit information.

[0038] In order to save the number of storage units and reduce the consumption of hardware resources, in an optional embodiment, the format conversion unit divides the to-be-decoded soft bit information into at least one to-be-decoded soft bit information block, and sends the at least one to-be-decoded soft bit information block to the corresponding storage unit for storage, which can include:

[0039] According to the column number b of the base matrix, the soft bit information to be decoded is divided into b soft bit information blocks to be decoded, wherein each soft bit information block to be decoded corresponds to the element value of the nth column of the base matrix; and the soft bit information blocks to be decoded corresponding to the columns with orthogonality in the base matrix are stored in the same storage unit.

[0040] That is, after obtaining the b soft bit information blocks to be decoded, each soft bit information block to be decoded corresponds to the element value of each column of the base matrix, and it is determined which columns in the base matrix have orthogonality, wherein the columns with orthogonality refer to that any two columns are not simultaneously non-“-1” elements, and then the soft bit information blocks to be decoded corresponding to the columns which are not simultaneously non-“-1” elements are stored in the same storage unit.

[0041] Each storage unit can group the soft bit information blocks to be decoded and then store them, and in an optional embodiment, the storage unit receives the corresponding soft bit information blocks to be decoded, groups and stores them, which can include:

[0042] The soft bit information blocks to be decoded are divided into Z soft bit information blocks to be decoded, and the Z soft bit information blocks to be decoded are grouped according to the number of each group as a preset decoding parallelism P and stored in the storage unit.

[0043] Wherein, Z is the expansion factor of the base matrix, and Z is a positive integer.

[0044] That is, the above-mentioned division of each soft bit information block to be decoded into Z soft bit information blocks to be decoded, and then the division of each soft bit information block to be decoded into Z / P groups according to each group P and the storage in the storage unit.

[0045] Wherein, the above-mentioned decoding parallelism P is the number of computing units in the decoder.

[0046] In order to realize the computing process of each computing unit, in an optional embodiment, the positive shift unit performs positive cyclic shift on the soft bit information to be decoded to obtain the shifted soft bit information to be decoded, which includes:

[0047] According to the element value of the kth row of the base matrix, the shift value of the corresponding storage unit is determined; and according to the shift value, the received soft bit information to be decoded is positively cyclically shifted to obtain the shifted soft bit information to be decoded.

[0048] The element value of the kth row determines the shift value of the corresponding storage unit, which can be implemented by a preset algorithm formula, so that the shift value of each storage unit can be flexibly set. The positive shift unit performs positive cyclic shift on the received soft bit information to be decoded of the corresponding storage unit according to the shift value of the corresponding storage unit, and then outputs the shifted soft bit information to be decoded to at least one calculation unit according to a preset routing mode, so as to replace the soft bit information output by each shift unit to the corresponding check node for calculation.

[0049] After obtaining the soft bit information to be decoded of the variable node n in the base matrix of the LDPC code, since the iterative method is used for calculation in the embodiment of the present application, the calculation unit first determines whether the decoding iteration number i of the LDPC code is less than the preset decoding iteration threshold. If it is less than, it means that the iteration is not completed. If it is equal to, it means that the iteration is completed.

[0050] If the calculation unit determines that the decoding iteration number i is less than the decoding iteration threshold, it means that the iteration is not completed. Since the decoding is performed by layers in the embodiment of the present application, it is further needed to determine whether the decoding layer number k of the LDPC code is less than the row number a of the base matrix.

[0051] When the calculation unit determines that the decoding layer number k is less than the row number a of the base matrix, the soft bit information of the variable node n of the kth layer of the base matrix is determined according to the soft bit information of the variable node n of the (k-1)th layer of the base matrix, and the variable node information of the variable node n of the (k+1)th layer of the base matrix to the check node m is determined according to the soft bit information of the variable node n of the (k-1)th layer of the base matrix. Specifically, if it is determined that the decoding layer number k is less than the row number a of the base matrix, it means that the decoding is not completed. In the specific implementation process, when the soft bit information of the variable node n of the kth layer of the base matrix is determined, the variable node information of the variable node n of the (k+1)th layer of the base matrix to the check node m can also be determined according to the already known soft bit information of the variable node n of the (k-1)th layer of the base matrix.

[0052] In an optional embodiment, when the calculation unit determines that the decoding layer number k is less than the row number a of the base matrix, the soft bit information of the variable node n of the kth layer of the base matrix is determined according to the soft bit information of the variable node n of the (k-1)th layer of the base matrix, and the variable node information of the variable node n of the (k+1)th layer of the base matrix to the check node m is determined according to the soft bit information of the variable node n of the (k-1)th layer of the base matrix. It can include: subtracting the check node information of the variable node n of the kth layer of the base matrix to the check node m in the last iteration from the soft bit information of the variable node n of the (k-1)th layer of the base matrix, adding the check node information of the variable node n of the kth layer of the base matrix to the check node m, and determining the obtained value as the soft bit information of the variable node n of the kth layer of the base matrix.

[0053] Specifically, the soft bit information of the kth layer variable node n of the base matrix can be calculated by the following formula:

[0054]

[0055] wherein, represents the soft bit information of the kth layer variable node n, represents the soft bit information of the (k-1)th layer variable node n, represents the check node information of the kth layer variable node n to the check node m in the last iteration, represents the check node information of the kth layer variable node n to the check node m, wherein n∈N(m).

[0056] The variable node information of the (k+1)th layer variable node n to the check node m of the base matrix can be calculated by the following formula:

[0057]

[0058] wherein, the variable node information of the (k+1)th layer variable node n to the check node m of the base matrix, represents the soft bit information of the (k-1)th layer variable node n, represents the check node information of the (k+1)th layer variable node n to the check node m in the last iteration.

[0059] In determining the check node information of the (k+1)th layer check node m to the variable node n of the base matrix according to the variable node information of the (k+1)th layer variable node n to the check node m, after the variable node information of the (k+1)th layer variable node n to the check node m is calculated, the check node information of the (k+1)th layer check node m to the variable node n can be calculated by the following formula:

[0060]

[0061] wherein, represents the check node information of the (k+1)th layer check node m to the variable node n, the function f can adopt one of a minimum sum (MS, Min-Sum) algorithm, a normalised minimum sum (NMS, Normalised Offset) algorithm, and an offset minimum sum (OMS, Offset Min-Sum) algorithm, and the input information of the function f is all variable node information connected to the (k+1)th layer check node m except the variable node n wherein j∈N(m), j≠n.

[0062] The calculation unit updates the decoding layer number k to k+1, re-executes the judgment of whether the decoding layer number k of the LDPC code is less than the row number a of the base matrix, and determines that the decoding layer number k is greater than or equal to the row number a of the base matrix, updates the iteration number i to i+1, and re-executes the judgment of whether the decoding iteration number i of the LDPC code is less than the preset decoding iteration threshold value.

[0063] After completing the kth layer decoding, the decoding layer number k is updated to k+1, and the judgment of whether the decoding layer number k of the LDPC code is less than the row number a of the base matrix is returned. If k is greater than or equal to the row number a of the base matrix, the iteration is completed, the iteration number i is updated to i+1, and S102 is executed until the decoding iteration number i is equal to the decoding iteration threshold value.

[0064] The calculation unit updates the decoding layer number k to k+1, re-executes the judgment of whether the decoding layer number k of the LDPC code is less than the row number a of the base matrix, and determines that the decoding layer number k is greater than or equal to the row number a of the base matrix, updates the iteration number i to i+1, and re-executes the judgment of whether the decoding iteration number i of the LDPC code is less than the preset decoding iteration threshold value.

[0065] Here, when the decoding iteration number i is equal to the decoding iteration threshold value, it means that the entire iteration process is completed, and then the iteration result is recorded as the decoding result, that is, the soft bit information of the kth layer variable node n is determined as the decoding result of the soft bit information to be decoded of the variable node n.

[0066] Wherein, the initial value of k is 0, and when k=0, 1 or 2, the variable node information of the variable node n to the check node m of the k-2 layer is the soft bit information to be decoded of the variable node n.

[0067] In addition, after the calculation unit completes the decoding and obtains the soft bit information of the variable node n, the soft bit information of the variable node n needs to be stored. In an optional embodiment, the decoder further comprises at least one inverse shift unit, and the at least one inverse shift unit corresponds to the storage unit one by one. After the decoding iteration number i is equal to the decoding iteration threshold value, the method further comprises:

[0068] The routing unit receives the decoding result from the at least one calculation unit, and outputs the decoding result to at least one inverse shift unit according to the preset routing mode; the pipeline control unit determines that the inverse shift unit receives the decoding result, triggers the inverse shift unit, and the inverse shift unit outputs the decoding result to the corresponding storage unit according to the shift value.

[0069] Wherein, the shift value of each storage unit is flexibly set, and the inverse shift unit outputs the received soft bit information of the variable node n to the corresponding storage unit according to the shift value of the corresponding storage unit.

[0070] The above one or more embodiments of the decoder will be described below by taking examples.

[0071] Figure 2 is a schematic diagram of an optional structure of a calculation unit in the embodiment of the present application. As shown in Figure 2, the calculation unit is configured to complete the calculation of variable node information of a check row, the calculation of check node information, the storage of check node information, and the update calculation of variable node soft bit information. P calculation units complete parallel calculation of P check rows in parallel. Each calculation unit includes a VNU, a check node calculation unit (CNU), an UPD, and a check node information storage unit (CRAM).

[0072] The VNU is configured to complete the calculation of variable node information. Each VNU simultaneously receives check node information of all variable nodes connected to the check node output by the CRAM and simultaneously completes the calculation of all variable node information connected to the check node, i.e., full parallel calculation of variable node information of the same check row.

[0073] The CNU is configured to complete the calculation of check node information. Each CNU simultaneously receives variable node information output by the VNU and completes the calculation of check node information of all variable nodes connected to the check node, i.e., full parallel calculation of all check node information of the same check row. The CNU outputs the calculated check node information to the CRAM for update storage and to the UPD for update calculation.

[0074] The CRAM is configured to complete the update and storage of check node information. The CRAM outputs check node information obtained in the previous iteration for the VNU to complete the calculation of variable node information. The CRAM receives check node information output by the CNU in the current iteration and updates and stores the check node information.

[0075] The UPD is configured to complete the update calculation of variable node soft bit information. The UPD receives new check node information output by the CNU and reads old check node information from the CRAM to complete the update calculation of all variable node soft bit information of the check row in full parallel.

[0076] Based on the above decoder, Fig. 3 is a schematic diagram of an optional arrangement of a base matrix in the embodiment of the present application. The base matrix H in the present example is shown in Fig. 3. The base matrix H is H(5x9), the extension factor Z = 16, i.e. the base matrix H is composed of 5x9 16x16 cyclic shift sub-matrices. The non "-1" elements in the matrix represent the shift values of the cyclic shift sub-matrices. The sub-matrix at the position of the "-1" element is a zero matrix. The base matrix includes 5 layers, i.e. layer0, layer1, layer2, layer3 and layer4. Each layer has 16 check rows. The 16 check rows in each layer are calculated in a partial parallel manner. The partial parallel degree P = 4 is used in the present example. The embodiment of the present application does not make a specific limitation on the partial parallel degree P. The 16 check nodes c0-c15 in each layer are divided into Z / P = 4 groups. The first group includes: c0, c4, c8, c12; the second group includes: c1, c5, c9, c13; the third group includes: c2, c6, c10, c14; and the fourth group includes: c3, c7, c11, c15. The four check nodes in each group are processed in parallel, and the groups are processed in series.

[0077] Fig. 4 is a schematic diagram of an optional storage format of a storage unit in the embodiment of the present application. As shown in Fig. 4, each soft bit information block is converted into a corresponding storage format according to the parallel degree P and the extension factor Z. In the present example, the 16 soft bit information LLR0-LLR15 of each soft bit information block are divided into 4 groups. Each group is stored in the address Addr0, Addr1, Addr2, Addr3 of RAM0, RAM1, RAM2, RAM3 respectively. The first group includes: LLR0, LLR4, LLR8, LLR12; the second group includes: LLR1, LLR5, LLR9, LLR13; the third group includes: LLR2, LLR6, LLR10, LLR14; and the fourth group includes: LLR3, LLR7, LLR11, LLR15.

[0078] In order to write the serial or parallel input soft bit information block into RAM0-3 at a faster speed, the soft bit information in each group can be stored in a manner similar to a "spiral". The write address of each soft bit information can be obtained by using a "look-up table" or calculation. The to-be-decoded codeword in the present example includes 9 soft bit information blocks. The soft bit information storage unit receives the soft bit information blocks output by the format conversion unit, and stores each soft bit information block in the storage unit individually or collectively according to the column orthogonality of the base matrix H.

[0079] The columns corresponding to the variable nodes VN0, VN1, VN2 and VN3 of the base matrix H in the example are not orthogonal to each other, and the soft bit information blocks corresponding to the variable nodes are stored in different storage units respectively. The columns corresponding to the variable nodes VN4, VN5, VN6, VN7 and VN8 are orthogonal to each other, and the soft bit information blocks corresponding to the variable nodes are stored in the same storage unit.

[0080] The orthogonality of the columns refers to that the same positions of any two columns are not non-1 elements.

[0081] Fig. 5 is a schematic diagram of an optional structure of a storage unit in the embodiment of the application. As shown in Fig. 5, the storage bit width of each storage unit is equal to 4 times the soft bit information bit width. Storage unit 0 stores the soft bit information block of the variable node VN0; storage unit 1 stores the soft bit information block of the variable node VN1; storage unit 2 stores the soft bit information block of the variable node VN2; storage unit 3 stores the soft bit information block of the variable node VN3; and storage unit 4 stores the soft bit information blocks of the variable nodes VN4, VN5, VN6, VN7 and VN8. The starting storage addresses of each soft bit information block are Addr0, Addr4, Addr8, Addr12 and Addr16 respectively. Since the variable node information of the orthogonal columns is stored in a common storage unit, the storage mode reduces the consumption of storage resources of the decoder.

[0082] Each storage unit outputs 4 soft bit information stored at one address each time, and 5 storage units output 20 soft bit information simultaneously and participate in the calculation of 4 check rows in parallel. The calculation of 16 checks of one layer is completed for Z / P=4 times.

[0083] The first calculation of Layer0 corresponds to the first group of check rows c0, c4, c8 and c12. The initial read address of storage unit 0 can be obtained according to the following formula:

[0084] Init_addr0=mod(H 0,0 ,P) (4)

[0085] The calculation is Init_addr=mod(4,4)=0; therefore, the soft bit information {VN0LLR0, VN0LLR4, VN0LLR8, VN0LLR12} stored at the output address Addr0 is outputted.

[0086] By analogy:

[0087] The soft bit information {VN1LLR10, VN1LLR14, VN1LLR2, VN1LLR6} stored at the output address Addr2 of storage unit 1 is outputted.

[0088] The storage unit 2 outputs the soft bit information {VN2LLR13, VN2LLR1, VN2LLR5, VN2LLR9} stored at the address Addr1;

[0089] The storage unit 3 outputs the soft bit information {VN3LLR7, VN3LLR11, VN3LLR15, VN3LLR3} stored at the address Addr3;

[0090] The storage unit 4 outputs the soft bit information {VN4LLR0, VN4LLR4, VN4LLR8, VN4LLR12} stored at the address Addr0.

[0091] The information permutation of the soft bit information of each check node to the corresponding check row is completed by the positive shift unit and the routing unit. FIG. 6 is a schematic diagram of an optional structure of a shift unit in an embodiment of the present application, as shown in FIG. 6, the shift unit includes five positive shift units (shift unit 0, shift unit 1, shift unit 2, shift unit 3, and shift unit 4), each of which corresponds to a storage unit and receives the four soft bit information output by the storage unit in each calculation in parallel, and completes the cyclic shift operation of the four soft bit information according to a preset shift value.

[0092] FIG. 7 is a schematic diagram of an optional structure of a routing unit in an embodiment of the present application, as shown in FIG. 7, the fixed connection is used to permute the soft bit information output by each positive shift unit to the corresponding check node for calculation.

[0093] Since the variable node information of the column orthogonal variable node information uses a common storage unit, the number of storage units is reduced. Since the number of positive shift units is equal to the number of storage units, the number of shift units is reduced, the hardware resource consumption of the shift unit is reduced, and the connection complexity of the shift network is greatly reduced.

[0094] Specifically, the information permutation mode of the variable node and the check node in the first calculation process of Layer0 is as follows:

[0095] The soft bit information VN0LLR4, VN1LLR6, VN2LLR5, VN3LLR11, and VN4LLR0 participates in the calculation of the check row c0;

[0096] The soft bit information VN0LLR8, VN1LLR10, VN2LLR9, VN3LLR15, and VN4LLR4 participates in the calculation of the check row c4;

[0097] The soft bit information VN0LLR12, VN1LLR14, VN2LLR13, VN3LLR3, and VN4LLR8 participates in the calculation of the check row c8;

[0098] The soft bit information VN0LLR0, VN1LLR2, VN2LLR1, VN3LLR7 and VN4LLR12 participate in the calculation of the check row c12;

[0099] Thus, the reading of the soft bit information in the decoding calculation process and the information permutation between the variable nodes and the check nodes are completed, and so on:

[0100] The second calculation of Layer0 corresponds to the second group of check rows c1, c5, c9 and c13, and the reading of the soft bit information is as follows:

[0101] The storage unit 0 outputs the soft bit information {VN1LLR13, VN1LLR1, VN1LLR5, VN1LLR9} stored in the address Addr1;

[0102] The storage unit 1 outputs the soft bit information {VN1LLR7, VN1LLR11, VN1LLR15, VN1LLR3} stored in the address Addr3;

[0103] The storage unit 2 outputs the soft bit information {VN2LLR10, VN2LLR14, VN2LLR2, VN2LLR6} stored in the address Addr2;

[0104] The storage unit 3 outputs the soft bit information {VN3LLR0, VN3LLR4, VN3LLR8, VN3LLR12} stored in the address Addr0;

[0105] The storage unit 4 outputs the soft bit information {VN4LLR13, VN4LLR1, VN4LLR5, VN4LLR9} stored in the address Addr1.

[0106] The information permutation mode of the variable nodes and the check nodes in the second calculation of Layer0 is as follows:

[0107] The soft bit information VN0LLR5, VN1LLR7, VN2LLR6, VN3LLR12 and VN4LLR1 participate in the calculation of the check row c1;

[0108] The soft bit information VN0LLR9, VN1LLR11, VN2LLR10, VN3LLR0 and VN4LLR5 participate in the calculation of the check row c5;

[0109] The soft bit information VN0LLR13, VN1LLR15, VN2LLR14, VN3LLR4 and VN4LLR9 participate in the calculation of the check row c9;

[0110] The soft bit information VN0LLR1, VN1LLR3, VN2LLR2, VN3LLR8 and VN4LLR13 participate in the calculation of check row c13;

[0111] The third calculation of Layer0 corresponds to the third group of check rows c2, c6, c10 and c14, and the soft bit information is read as follows:

[0112] The storage unit 0 outputs the soft bit information {VN1LLR10, VN1LLR14, VN1LLR2, VN1LLR6} stored at the address Addr2;

[0113] The storage unit 1 outputs the soft bit information {VN1LLR0, VN1LLR4, VN1LLR8, VN1LLR12} stored at the address Addr0;

[0114] The storage unit 2 outputs the soft bit information {VN2LLR7, VN2LLR11, VN2LLR15, VN2LLR3} stored at the address Addr3;

[0115] The storage unit 3 outputs the soft bit information {VN3LLR13, VN3LLR1, VN3LLR5, VN3LLR9} stored at the address Addr1;

[0116] The storage unit 4 outputs the soft bit information {VN4LLR10, VN4LLR14, VN4LLR2, VN4LLR6} stored at the address Addr2.

[0117] The information permutation of the variable node and the check node of the third calculation of Layer0 is as follows:

[0118] The soft bit information VN0LLR6, VN1LLR8, VN2LLR7, VN3LLR13 and VN4LLR2 participate in the calculation of check row c2;

[0119] The soft bit information VN0LLR10, VN1LLR12, VN2LLR11, VN3LLR1 and VN4LLR6 participate in the calculation of check row c6;

[0120] The soft bit information VN0LLR14, VN1LLR0, VN2LLR15, VN3LLR5 and VN4LLR10 participate in the calculation of check row c10;

[0121] The soft bit information VN0LLR2, VN1LLR4, VN2LLR3, VN3LLR9 and VN4LLR14 participate in the calculation of check row c14;

[0122] The 4th calculation of Layer0 corresponds to the 3rd group of check rows c3, c7, cl 1 and c15, and the soft bit information reading mode is as follows:

[0123] The storage unit 0 outputs the soft bit information {VN1LLR7, VN1LLR11, VN1LLR15, VN1LLR3} stored in the address Addr3;

[0124] The storage unit 1 outputs the soft bit information {VN1LLR13, VN1LLR1, VN1LLR5, VN1LLR9} stored in the address Addr1;

[0125] The storage unit 2 outputs the soft bit information {VN2LLR0, VN2LLR4, VN2LLR8, VN2LLR12} stored in the address Addr0;

[0126] The storage unit 3 outputs the soft bit information {VN3LLR10, VN3LLR14, VN3LLR2, VN3LLR6} stored in the address Addr2;

[0127] The storage unit 4 outputs the soft bit information {VN4LLR7, VN4LLR11, VN4LLR15, VN4LLR3} stored in the address Addr3.

[0128] The information permutation mode of the variable node and the check node of the 4th calculation of Layer0 is as follows:

[0129] The soft bit information VN0LLR7, VN1LLR9, VN2LLR8, VN3LLR14 and VN4LLR3 participate in the calculation of the check row c3;

[0130] The soft bit information VN0LLR11, VN1LLR13, VN2LLR12, VN3LLR2 and VN4LLR7 participate in the calculation of the check row c7;

[0131] The soft bit information VN0LLR15, VN1LLR1, VN2LLR0, VN3LLR6 and VN4LLR11 participate in the calculation of the check row cl 1;

[0132] The soft bit information VN0LLR3, VN1LLR5, VN2LLR4, VN3LLR10 and VN4LLR15 participate in the calculation of the check row c15;

[0133] One computing unit completes the calculation of one check row, and the decoder in this embodiment needs four parallel computing units to complete the calculation of four check rows in parallel each time, and the calculation of 16 check rows in one layer is completed in four times. Among them, the VNU, CNU and UPD in each computing unit complete the calculation of all check rows in one layer in a pipeline manner, and the layer-by-layer pipeline manner is adopted between layers. FIG. 8 is a schematic diagram of an optional pipeline of layered decoding in an embodiment of the present application. As shown in FIG. 8, the calculation of the kth layer is based on the calculation result of the (k-1)th layer. The first-time calculation of four check row data in each layer is first input to the corresponding computing unit for calculation. The first-time VNU calculation process is denoted as VNU0; the first-time CNU calculation process is denoted as CNU0; and the first-time UPD calculation process is denoted as UPD0. In this way, when the VNU4 process, the CNU4 process and the UPD4 process of the fourth-time calculation are all completed, the layer-by-layer pipeline calculation is ended, and the pipeline of the next layer is started.

[0134] The layered pipeline manner can ensure that the calculation of each layer is based on the latest result of the previous layer, that is, the standard layered decoding method. In the layer-by-layer pipeline calculation process, there is a long idle time of the pipeline for the VNU, CNU and UPD computing units, which leads to a low pipeline efficiency. Specifically, the time delay of one VNU pipeline calculation is T vnu , the time delay of one CNU pipeline calculation is T cnu , and the time delay of one UPD pipeline calculation is T upd . If the interval time of each calculation in one layer is 1 unit of time, then the time delay of one iteration decoding in this embodiment is:

[0135] T iter =(T vnu +T cnu +T upd +4)×5 (5)

[0136] The pipeline control unit outputs an enable signal to control the forward shift unit to read the soft bit information from the storage unit and perform the pipeline replacement, to control the VNU computing unit to perform the pipeline calculation of the variable node information, to control the CNU computing unit to perform the pipeline calculation of the check node information, to control the UPD computing unit to perform the pipeline update of the soft bit information, and to control the reverse shift unit to perform the pipeline replacement of the new soft bit information and update the storage unit.

[0137] The decoder in the present example adopts a hierarchical pipeline mode to implement the standard hierarchical decoding process of QC-LDPC code, the parallelism of the entire decoder is 4, i.e. 4 computing units are needed to simultaneously complete the parallel computation of 4 check rows, the variable node soft bit information of the orthogonal column shares a storage unit, the number of storage units is reduced from 9 to 5, and the number of forward / reverse shift units is also reduced from 9 to 5, because the number of shift units is reduced, the complexity of the routing unit between the shift unit and the computing unit is also greatly reduced, it can be seen that the storage mode of the decoder in the present application can reduce the storage resource consumption and the hardware implementation complexity of the decoder, in addition, the decoder in the present application adopts a partial parallel decoding mode with fixed parallelism P, and the soft bit information block is stored in a "spiral" manner, without increasing the complexity of the decoder, the QC-LDPC code with different expansion factors Z can be decoded, and the decoding flexibility is high.

[0138] Fig. 9 is a schematic diagram of an optional pipeline of layer overlapping decoding in the present application, the decoding method can also be applied to the above-mentioned decoder, in the present example, the same base matrix H, the same expansion factor Z and the same parallelism P are adopted as the hierarchical decoding method, therefore the present example is only different from the hierarchical decoding method in the decoding mode, the present example adopts a fast hierarchical decoding mode, for the sake of simplicity, only the different contents from the hierarchical decoding method are described in the present example.

[0139] One computing unit completes the computation of one check row, the decoder in the present example needs 4 parallel computing units to complete the computation of 4 check rows in parallel each time, and the computation of 16 check rows in one layer is completed in 4 times, the VNU, CNU and UPD in each computing unit complete the computation of all check rows in one layer in a pipeline manner, and the layer overlapping pipeline is adopted between layers, and the layer overlapping pipeline is shown in Fig. 9.

[0140] According to the fast hierarchical decoding method, there is no dependency between the computation of adjacent two layers, i.e. the VNU computation, CNU computation and UPD computation of the kth layer all depend on the computation result of the soft bit information of the k-2th layer, therefore the last UPD pipeline computation of the k-1th layer does not need to be waited for, and the VNU pipeline computation of the kth layer can be started in advance; in the present example, after the VNU3 pipeline computation of the 0th layer is started, the VNU0 pipeline computation of the 1st layer can be started; similarly, after the VNU3 pipeline computation of the 1st layer is started, the VNU0 pipeline computation of the 2nd layer can be started; in this way, after the VNU3 pipeline computation of the 3rd layer is started, the VNU0 pipeline computation of the 4th layer can be started; until the UPD3 pipeline computation of the 4th layer is completed, the present iteration computation is ended.

[0141] The layer-overlapping pipelining mode is adopted, the flow water calculation between layers is continuously carried out, the idle waiting time of the VNU, CNU and UPD calculation units in the whole iterative calculation process can be ensured, the pipelining efficiency is high, if the VNU flow water calculation time delay is T vnu , the CNU flow water calculation time delay is T cnu , the UPD flow water calculation time delay is T upd , and the interval time of each calculation in a single layer is a unit time 1, then in the embodiment, one iteration needs 5 layers of 4 flow waters, and the decoding time delay of one iteration is:

[0142] T iter =T vnu +T cnu +T upd +4×5 (6)

[0143] The pipelining control unit outputs the enabling signals to control the flow water process of the soft bit information reading and transposition of the forward shift unit, the flow water process of the VNU calculation unit for the variable node information calculation, the flow water process of the CNU calculation unit for the check node information calculation, the flow water process of the UPD calculation unit for the soft bit information updating, and the flow water process of the inverse shift unit for the new soft bit information transposition and the soft bit information storage unit updating. It can be seen that the pipelining control unit is configured to complete the pipelining control in the decoding iteration process, adopts the hierarchical pipelining in the standard hierarchical decoding mode, adopts the layer-overlapping pipelining in the fast hierarchical decoding mode, and realizes the switching function of the pipelining mode by generating the enabling signals of each stage of the pipelining.

[0144] The decoder in the example adopts the layer-overlapping pipelining mode to realize the fast hierarchical decoding process of the QC-LDPC code, the parallelism of the whole decoder is 4, that is, 4 calculation units are needed to complete the parallel calculation of 4 check rows at the same time, the variable node soft bit information storage unit number is reduced from 9 to 5, and the forward / inverse shift unit number is also reduced from 9 to 5. Since the shift unit number is reduced, the routing unit complexity between the shift unit and the calculation unit is also greatly reduced. It can be seen that the storage mode of the decoder in the embodiment can reduce the storage resource consumption and the hardware implementation complexity of the decoder. In addition, the decoder in the embodiment adopts the partial parallel decoding mode with a fixed parallelism P, and the soft bit information block is stored in a “spiral” mode. Without increasing the complexity of the decoder, the QC-LDPC code with different expansion factors Z can be decoded, and the decoding flexibility is high.

[0145] The decoder provided in the embodiments of the present application first comprises at least one calculation unit, which is configured to acquire soft bit information of a variable node n to be decoded in a base matrix of an LDPC code, then judge whether a decoding iteration number i of the LDPC code is less than a preset decoding iteration number, if so, judge whether a decoding layer number k of the LDPC code is less than a row number a of the base matrix, if so, determine soft bit information of a variable node n in a kth layer of the base matrix according to soft bit information of a variable node n in a (k-1) th layer of the base matrix, and determine variable node information of a variable node n to a check node m in a (k+1) th layer of the base matrix according to the soft bit information of the variable node n in the (k-1) th layer of the base matrix, and then determine check node information of a check node m to a variable node n in the (k+1) th layer of the base matrix according to the variable node information of the variable node n to the check node m in the (k+1) th layer of the base matrix, so that the soft bit information of the variable node n in the kth layer is obtained, and the variable node information in the next layer is generated, and then the check node information in the next layer is generated, compared with related technologies, the variable node information and the check node information in the next layer are generated in advance, which prepares for generating the soft bit information of the variable node n in the next layer, so that the decoding speed can be accelerated, the k is updated to k+1 after the soft bit information of the variable node n in the kth layer is obtained, and decoding in the next layer is performed, and the iteration number i is updated to i+1 until the iteration number is equal to the preset iteration number, so that the soft bit information is obtained, that is, in the embodiments of the present application, the variable node information in the next layer is started and generated while the soft bit information of the variable node n in the kth layer of the base matrix is generated, and then the check node information in the next layer is generated, and then the soft bit information of the variable node n in the (k+1) th layer of the base matrix can be determined according to the soft bit information of the variable node n in the kth layer while decoding in the (k+1) th layer is performed, compared with related technologies, the calculation of the variable node information in the (k+1) th layer and the check node information in the (k+1) th layer can be started without waiting for the soft bit information of the variable node n in the kth layer to be generated, so that the decoding speed is accelerated, and the decoding efficiency of the LDPC decoder is improved.

[0146] Based on the same inventive concept, the embodiments of the present application also provide a decoding method, and FIG. 10 is a flowchart of the decoding method in the embodiments of the present application, as shown in FIG. 10, the method is applied to at least one calculation unit of a decoder, wherein the decoding method can comprise:

[0147] S1001: acquiring soft bit information of a variable node n to be decoded in a base matrix of an LDPC code;

[0148] S1002: judging whether a decoding iteration number i of the LDPC code is less than a preset decoding iteration threshold;

[0149] S1003: determining whether the number of decoding iterations i is less than a decoding iteration threshold, and judging whether the number of decoding layers k of the LDPC code is less than the number of rows a of the base matrix;

[0150] S1004: determining the soft bit information of the variable node n of the kth layer of the base matrix according to the soft bit information of the variable node n of the (k-1)th layer of the base matrix, and determining the variable node information of the variable node n to the check node m of the (k+1)th layer of the base matrix according to the soft bit information of the variable node n of the (k-1)th layer of the base matrix;

[0151] S1005: determining the check node information of the check node m to the variable node n of the (k+1)th layer of the base matrix according to the variable node information of the variable node n to the check node m of the (k+1)th layer of the base matrix;

[0152] S1006: updating the number of decoding layers k to k+1, and re-executing the judgment of whether the number of decoding layers k of the LDPC code is less than the number of rows a of the base matrix;

[0153] S1007: determining whether the number of decoding layers k is greater than or equal to the number of rows a of the base matrix, updating the number of iterations i to i+1, and re-executing the judgment of whether the number of decoding iterations i of the LDPC code is less than the preset decoding iteration threshold,

[0154] S1008: when the number of decoding iterations i is equal to the decoding iteration threshold, determining the soft bit information of the variable node n of the kth layer as the decoding result of the soft bit information to be decoded of the variable node n;

[0155] wherein, when the initial value of i is 0 and the initial value of k is 0, and when k=0 or 1, the soft bit information of the variable node n of the (k-1)th layer is the soft bit information to be decoded of the variable node n; wherein n is an integer greater than or equal to 0 and less than the number of columns b of the base matrix.

[0156] In an optional embodiment, the calculation unit determines the variable node information of the variable node n to the check node m of the (k+1)th layer of the base matrix according to the soft bit information of the variable node n of the (k-1)th layer of the base matrix, comprising:

[0157] subtracting the check node information of the variable node n to the check node m of the (k+1)th layer of the base matrix in the last iteration from the soft bit information of the variable node n of the (k-1)th layer of the base matrix to obtain a difference value, and the difference value is determined as the soft bit information of the variable node n of the kth layer of the base matrix.

[0158] Based on the foregoing embodiments, this embodiment provides a computer storage medium, and FIG. 11 is a structural schematic diagram of the computer storage medium in the embodiment of the present application. As shown in FIG. 11, the computer storage medium 110 stores a computer program. The computer program is executed by a processor to implement the steps of the decoding method described in one or more of the foregoing embodiments.

[0159] It should be noted that, in this document, the terms "comprising", "including", or any other variant thereof are intended to cover a non-exclusive inclusion, such that processes, methods, articles, or apparatuses that comprise a list of elements not only include those elements, but also include other elements that are not expressly listed, or other elements that are inherent in such processes, methods, articles, or apparatuses. Without more limitations, an element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0160] The serial numbers of the embodiments of the present application are only for description, and do not represent the advantages or disadvantages of the embodiments.

[0161] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment method can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application or the part that contributes to the related art can be embodied in the form of a software product. The computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a plurality of instructions for making a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) execute the method described in each embodiment of the present application.

[0162] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above-mentioned specific embodiments. The above-mentioned specific embodiments are only illustrative, not restrictive, and those skilled in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the protection scope of the claims.