Memory device

Abstract

A memory device includes a stacked structure, a vertical channel pillar, a charge storage structure, a first conductive plug, a second conductive plug, and a metal silicide layer. The stacked structure includes a plurality of insulating layers and a plurality of conductive layers that are alternately stacked. The vertical channel pillar vertically penetrates the stacked structure, wherein the vertical channel pillar includes an insulating column and a channel layer surrounding the insulating column. The charge storage structure is disposed between the channel layer and the plurality of conductive layers. The first conductive plug and the second conductive plug are vertically arranged on both sides of the insulating column and connected with the channel layer. The metal silicide layer is formed on the entire top surface of the first conductive plug and the entire top surface of the second conductive plug.

Description

[Technical Field]

[0001] This invention relates to a semiconductor element, and more particularly to a memory device. [Previous Technology]

[0002] Non-volatile memory elements have become a widely used type of memory element in personal computers and other electronic devices because they have the advantage that stored data will not be lost after power is turned off.

[0003] To further improve the integration density of memory elements, a three-dimensional (3D) memory has been developed. However, due to the continuous miniaturization of semiconductor elements, there are still many challenges related to 3D memory. [Summary of the Invention]

[0004] The present invention provides a memory device that can reduce contact resistance and increase conduction current.

[0005] In one embodiment of the present invention, a memory device includes at least a stacked structure, a vertical channel post, a charge storage structure, a first conductor plug, a second conductor plug, and a metal silicate layer. The stacked structure includes a plurality of alternately stacked insulating layers and a plurality of conductor layers. The vertical channel post extends vertically through the stacked structure, wherein the vertical channel post includes an insulating post and a channel layer surrounding the insulating post. The charge storage structure is located between the channel layer and the conductor layer. The first conductor plug and the second conductor plug are vertically disposed on both sides of the insulating post and are in contact with the channel layer. The metal silicate layer is located on the entire top surface of the first and second conductor plugs.

[0006] Based on the above, the entire top surface of the first conductor plug and the second conductor plug in this embodiment of the invention is provided with a low-resistance metal silicate layer, so the contact resistance with the upper contact window can be reduced, thereby increasing the conduction current. Moreover, the metal silicate layer can serve as a good etching stop layer during the formation of the contact window.

Implementation Method

[0007] The concept of the present invention can be understood by referring to the following detailed description and the accompanying drawings. Furthermore, the dimensions of the various regions in the drawings are not actual dimensions, and the dimensions between the sectional view and the top view are not drawn to scale and are for illustrative purposes only.

[0008] FIG1A is a top view of a memory device according to an embodiment of the present invention. FIG1B is a cross-sectional view along line A-A' of FIG1A.

[0009] Referring to Figures 1A and 1B, the memory device 100 of this embodiment includes at least a stacked structure 102, a vertical channel pillar VC, a charge storage structure 104, a first conductor plug 106, a second conductor plug 108, and a metal silicate layer 110. The stacked structure 102 includes a plurality of alternately stacked insulating layers 112 and a plurality of conductor layers 114. That is, the stacked structure 102 is composed of layers of insulating layers 112 and conductor layers 114 between the insulating layers 112. The number of insulating layers 112 and conductor layers 114 is not limited to that shown in the figures, and may be 8 layers, 16 layers, 32 layers, 64 layers, or more. In one embodiment, the material of the insulating layer 112 includes silicon oxide. In one embodiment, the conductor layer 114 includes, for example, a metal layer, and the material of the aforementioned metal layer includes tungsten (W). In one embodiment, the conductor layers 114, originally made of polycrystalline silicon, are formed into metal layers through a gate replacement process; that is, the conductor layers 114 can be gate layers in the memory device 100. A vertical channel post VC vertically penetrates the stacked structure 102, wherein the vertical channel post VC includes an insulating post 116 and a channel layer 118 surrounding the insulating post 116. In one embodiment, the material of the channel layer 118 includes polycrystalline silicon, but is not limited thereto. A charge storage structure 104 is located between the channel layer 118 and the conductor layers 114. In one embodiment, the charge storage structure 104 is an oxide / nitride / oxide (ONO) composite layer, but is not limited thereto. A first conductor plug 106 and a second conductor plug 108 are vertically disposed on both sides of the insulating post 116 and are in contact with the channel layer 118. In the top view of Figure 1A, the edges of the first conductor plug 106 and the second conductor plug 108 extend towards the channel layer 118. Therefore, the portion of the channel layer 118 that is in contact with the first conductor plug 106 / second conductor plug 108 is thinner, while the portion that is not in contact with the first conductor plug 106 / second conductor plug 108 is thicker. In one embodiment, the first conductor plug 106 and the second conductor plug 108 may be the source and drain in the memory device 100.

[0010] Referring to FIG1B, the metal silicate layer 110 is located on the entire top surface 106t of the first conductor plug 106 and the entire top surface 108t of the second conductor plug 108. Therefore, compared with the titanium silicate previously formed only at the bottom of the contact window 122, the resistance at the contact point between the first conductor plug 106 and the metal silicate layer 110 can be significantly reduced, and the resistance at the contact point between the second conductor plug 108 and the metal silicate layer 110 can also be significantly reduced. Once the contact resistance here is reduced, the on-current (Ion current) can be increased. In one embodiment, the material of the insulating pillar 116 is, for example, silicon nitride. In one embodiment, the vertical channel pillar VC also includes a protective layer 117, as shown in FIG1A. In FIG1A, the protective layer 117 surrounds the insulating pillar 116 and fills the space between the channel layer 118 and the first conductor plug 106 and the second conductor plug 108. In one embodiment, the material of the protective layer 117 is, for example, silicon oxide, but is not limited thereto.

[0011] In one embodiment, the metal silicate layer 110 is a cobalt silicate layer or a nickel silicate layer, and the materials of the first conductor plug 106 and the second conductor plug 108 are polycrystalline silicon. The metal silicate layer 110 is formed, for example, by depositing a metal material on polycrystalline silicon and then performing heat treatment to react the metal with silicon to form a metal silicate. Therefore, the thickness t1 of the metal silicate layer 110 can be greater than 0 and less than 450 Å.

[0012] In one embodiment, the memory device 100 may include a contact window 122 formed in the dielectric layer 121, and the contact window 122 rests on the metal silicate layer 110. The contact window 122 includes a titanium layer 124 and a titanium nitride layer 126 as a barrier layer, and the titanium layer 124 is in direct contact with the metal silicate layer 110. The conductive metal layer 128 in the contact window 122 may be copper or tungsten, but is not limited to these. In previous processes, the titanium layer 124 at the bottom of the contact window 122 reacted directly with polysilicon (the first conductor plug 106 and the second conductor plug 108) to form titanium silicate, so the titanium layer 124 was not retained at the bottom of the contact window 122. However, in this embodiment, a low-resistance titanium layer 124 is still retained, so the contact resistance between the contact window 122 and the metal silicate layer 110 is also reduced. In one embodiment, the top surface 116t of the insulating pillar 116 is higher than the top surface of the metal silicate layer 110, which facilitates electrical isolation between the first conductor plug 106 and the second conductor plug 108. In this embodiment, the metal silicate layer 110 is not in contact with the charge storage structure 104.

[0013] Referring again to FIG1B, a substrate 130, a dielectric layer 132 formed on the substrate 130, and polysilicon layers P1 and P2 formed in the dielectric layer 132 are also provided below the stacked structure 102, but the present invention is not limited thereto. In one embodiment, polysilicon layers P1 and P2 may have the same material, such as doped or undoped polysilicon material. For example, polysilicon layers P1 and P2 may be undoped polysilicon layers. Polysilicon layer P1 may serve as an etch stop layer during the formation of the first conductor plug 106, and polysilicon layer P2 may serve as an etch stop layer during the formation of the second conductor plug 108 to avoid over-etching. A stop layer 134 may be provided between the polysilicon layers P1-P2 and the stacked structure 102. In one embodiment, the stop layer 134 is made of doped or undoped polycrystalline silicon. For example, the stop layer 134 may be a p-type doped (P+) polycrystalline silicon layer. In one embodiment, the stop layer 134 may serve as an etch stop layer during the formation of the vertical channel pillar (VC) to prevent over-etching. In one embodiment, the dielectric layer 132 is, for example, a silicon oxide layer.

[0014] FIG2 is a cross-sectional view of another memory device according to an embodiment of the present invention, wherein the same element symbols as in the previous embodiment are used to represent the same or similar parts and components, and the relevant content of the same or similar parts and components can also refer to the content of the previous embodiment, and will not be repeated here.

[0015] Referring to FIG2, the main difference between the memory device 200 of this embodiment and the memory device 100 of the previous embodiment is that the materials of the first conductor plug 202 and the second conductor plug 204 are also tungsten silicate, and the metal silicate layer 206 is also a tungsten silicate layer. Therefore, the first conductor plug 202 and the metal silicate layer 206 on its surface can be continuously formed using the same process, and the second conductor plug 204 and the metal silicate layer 206 on its surface can be continuously formed using the same process. Therefore, the first conductor plug 202 and the metal silicate layer 206 on its surface can be regarded as a homogeneous tungsten silicate pillar, and the second conductor plug 204 and the metal silicate layer 206 on its surface can be regarded as another homogeneous tungsten silicate pillar.

[0016] Figures 3A to 3L are cross-sectional views of the manufacturing process of a memory device according to an embodiment of the present invention, wherein the same element symbols as those in Figure 1B are used to represent the same or similar parts, structures or size definitions, and the descriptions of the same parts, structures or size definitions can be referred to the relevant descriptions in Figure 1B, and will not be repeated here.

[0017] Referring to FIG3A, before forming the stacked structure 300, a dielectric layer 132 may be formed on the substrate 130, and then polysilicon layers P1 and P2 may be formed in the dielectric layer 132. In one embodiment, the substrate 130 may be, for example, a semiconductor substrate (such as a silicon substrate), a semiconductor compound substrate, or a semiconductor over insulator (SOI). The method for forming the polysilicon layers P1 and P2 may include, but is not limited to, forming an opening in the dielectric layer 132; forming a polysilicon material in the opening; performing a planarization process on the polysilicon material; and forming a dielectric material to cover the polysilicon material. Subsequently, a stop layer 134 is formed on the dielectric layer 132.

[0018] Then, a stacked structure 300 is formed on the stop layer 134, the stacked structure 300 comprising a plurality of alternately stacked insulating layers 112 and a plurality of sacrificial layers 302. In one embodiment, the sacrificial layer 302 is, for example, polycrystalline silicon or other suitable material. In one embodiment, the insulating layer 112 and the sacrificial layer 302 may be different dielectric materials. For example, the insulating layer 112 may be a silicon oxide layer; while the sacrificial layer 302 may be a silicon nitride layer. The number of insulating layers 112 and sacrificial layers 302 is not limited to those shown in the figures, and may be 8, 16, 32, 64 or more layers. Next, a vertical channel opening VCO is formed through the stacked structure 300. One method for forming a vertical channel opening VCO is to first deposit a relatively thick dielectric layer 120 on the stacked structure 300, then pattern the dielectric layer 120 using photolithography, and use this dielectric layer 120 as a mask to etch the stacked structure 300 and the stop layer 134, stopping at the dielectric layer 132. In one embodiment, the stop layer 134 can be considered as an etch stop layer for forming the vertical channel opening VCO to avoid over-etching.

[0019] Referring to FIG3B, a channel layer 118 and a spacer wall 304 are sequentially formed on the sidewall of the vertical channel opening VCO. Specifically, a channel material may first be formed to conformally cover the surface of the vertical channel opening VCO and extend to cover the surface of the dielectric layer 120; another dielectric material may be conformally deposited on the channel material; an anisotropic etching process (e.g., reactive ion etching (RIE) process) may be performed to remove the dielectric material and channel material on the surface of the dielectric layer 120 and the bottom surface of the vertical channel opening VCO, thereby forming the channel layer 118 and the spacer wall 304 on the sidewall of the vertical channel opening VCO. In one embodiment, the material of the spacer wall 304 is, for example, a low-temperature oxide (LTO) material.

[0020] Referring to FIG3C, a protective layer 306 is filled within the vertical channel opening VCO, and the protective layer 306 may extend to cover the dielectric layer 120. In one embodiment, the protective layer 306 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric material. Then, a central opening O1 is formed in the protective layer 306, for example by patterning the protective layer 306, and may be etched into the dielectric layer 132 concurrently, with the central opening O1 located between the polysilicon layer P1 and the polysilicon layer P2.

[0021] Referring to FIG3D, an insulating pillar 116 is formed in the protective layer 306. The formation method is, for example, to first fill the central opening O1 with the material of the insulating pillar 116, and then remove the material outside the central opening O1. The insulating pillar 116 obtained after this step, together with the channel layer 118 and the protective layer 306, constitutes the structure of the subsequently formed vertical channel pillar VC.

[0022] Referring to FIG3E, a first plug via O2 and a second plug via O3 are formed, for example, by patterning a protective layer 306 to form the first plug via O2 and the second plug via O3. In one embodiment, the first plug via O2 penetrates the stacked structure 300 and exposes the polysilicon layer P1; while the second plug via O3 penetrates the stacked structure 300 and exposes the polysilicon layer P2. The polysilicon layer P1 can be considered as an etch stop layer for forming the first plug via O2, and the polysilicon layer P2 can be considered as an etch stop layer for forming the second plug via O3, to avoid over-etching. In addition, the spacer wall 304 in FIG3D can also be removed in the step of patterning the protective layer 306 to expose the channel layer 118. The positions of the first plug via O2 and the second plug via O3 are the positions of the subsequently formed first conductor plug and second conductor plug. The top of the insulating pillar 116 may be partially reduced in this step.

[0023] Referring to FIG3F, a first conductor plug 106 and a second conductor plug 108 are formed in the first plug through-hole O2 and the second plug through-hole O3. In this embodiment, the material of the first conductor plug 106 and the second conductor plug 108 is polycrystalline silicon, and the formation method is, for example, to first deposit polycrystalline silicon material to fill the first plug through-hole O2 and the second plug through-hole O3, and then use back etching to remove a portion of the polycrystalline silicon in the first plug through-hole O2 and the second plug through-hole O3, and make the top of the insulating pillar 116 protrude.

[0024] Referring to FIG3G, a metal material layer 308 is formed on the surface of the first conductor plug 106 and the second conductor plug 108 within the first plug through-hole O2 and the second plug through-hole O3, wherein the metal material layer 308 is, for example, cobalt (Co) or nickel (Ni). The method for forming the metal material layer 308 is, for example, sputtering or CVD deposition of a metal material within the first plug through-hole O2 and the second plug through-hole O3, and the metal material layer 308 may cover the protective layer 306.

[0025] Referring to FIG3H, a thermal process is performed to react the metal material layer 308 of FIG3G with the material (polycrystalline silicon) of the first conductor plug 106 / second conductor plug 108 to form a metal silicate layer 110, wherein the metal silicate layer 110 may be cobalt silicate or nickel silicate. Afterwards, the unreacted metal material layer is removed, so that the metal silicate layer 110 is formed self-aligned on the entire top surface 106t of the first conductor plug 106 and the entire top surface 108t of the second conductor plug 108.

[0026] Referring to FIG3I, a gate replacement process is performed. For example, a dielectric layer 310 is first formed on the structure of FIG3H, and then a separator trench SLT is formed from top to bottom, penetrating the dielectric layer 310, the protective layer 306, the dielectric layer 120, the stacked structure 300, the stop layer 134, and down to the dielectric layer 132. Then, the sacrificial layer 302 in the stacked structure 300 is removed until the channel layer 118 is exposed. The method for removing the sacrificial layer 302 is, for example, by wet etching to laterally remove the sacrificial layer 302 from the separator trench SLT.

[0027] Referring to FIG3J, a charge storage structure 104 is formed in the space between the insulating layers 112 and the inner surface of the separator trench SLT, and a conductor layer 114 is formed therein. Then, a portion of the conductor layer 114 is etched, causing its side surface 114s to shrink inward and expose the entire separator trench SLT. Next, an insulating layer 312 is formed in the separator trench SLT, and a polycrystalline silicon layer 314 is formed in the insulating layer 312. Then, a dielectric layer 316 is formed on the entire structure.

[0028] Referring to FIG3K, contact window openings CO1 and CO2 are formed in dielectric layers 316 and 310, exposing the metal silicate layer 110. In one embodiment, during the formation of contact window openings CO1 and CO2, the metal silicate layer 110 can serve as a good etch stop layer, and the contact window openings CO1 and CO2 are located within the metal silicate layer 110.

[0029] Referring to FIG3L, a contact window 122 is formed in contact window openings CO1 and CO2. The formation method is, for example, to first form a titanium layer 124 and a titanium nitride layer 126 as barrier layers, and then fill the contact window openings CO1 and CO2 with a conductive metal layer 128. Therefore, the titanium layer 124 in the contact window 122 is in direct contact with the metal silicate layer 110.

[0030] Figures 4A to 4E are cross-sectional views of the manufacturing process of another memory device according to an embodiment of the present invention, wherein the same element symbols as in the previous embodiment are used to represent the same or similar parts, structures or size definitions, and the description of the same parts, structures or size definitions can be referred to the relevant description in the previous embodiment, and will not be repeated here.

[0031] The manufacturing process of this embodiment can be referred to Figures 3A to 3E. Therefore, Figure 4A is actually the same as Figure 3E, forming a first plug through hole O2 and a second plug through hole O3 that penetrate the vertical channel column VC.

[0032] Referring to Figure 4B, metal silicate is deposited in the first plug through-hole O2 and the second plug through-hole O3, and then the metal silicate is etched back to simultaneously form the first conductor plug 202 and its surface metal silicate layer 206, and simultaneously form the second conductor plug 204 and its surface metal silicate layer 206. The aforementioned metal silicate may be tungsten silicate (WSi2).

[0033] Referring to Figure 4C, a dielectric layer 310 is formed on the structure of Figure 4B.

[0034] Then, the gate replacement process shown in Figures 3I to 3J can be performed to form the charge storage structure 104 and the conductor layer 114, as shown in Figure 4D.

[0035] Referring to Figure 4E, the process is the same as that in Figures 3K to 3L, contact windows 122 are formed in contact window openings CO1 and CO2, respectively. Therefore, the titanium layer 124 in contact window 122 is in direct contact with the metal silicate layer 206.

[0036] In summary, the memory device and its manufacturing method according to the embodiments of the present invention can significantly reduce the contact resistance of the first conductor plug and the second conductor plug and the contact window above them in the vertical channel post, thereby increasing the conduction current of the memory device. Moreover, there is a whole layer of metal silicate between the contact window and the first / second conductor plug, so it can serve as a good etch stop layer during the formation of the contact window. [Simplified Explanation of the Diagram]

[0037] FIG1A is a top view of a memory device according to an embodiment of the present invention. FIG1B is a cross-sectional view along line A-A' of FIG1A. FIG2 is a cross-sectional view of another memory device according to an embodiment of the present invention. FIG3A to FIG3L are cross-sectional views of the manufacturing process of a memory device according to an embodiment of the present invention. FIG4A to FIG4E are cross-sectional views of the manufacturing process of another memory device according to an embodiment of the present invention.

Claims

1. A memory device, comprising: A stacked structure comprising multiple insulating layers and multiple conductor layers stacked alternately; A vertical channel pillar, vertically penetrating the stacked structure, wherein the vertical channel pillar includes an insulating pillar and a channel layer surrounding the insulating pillar; a charge storage structure, located between the channel layer and the plurality of conductor layers; a first conductor plug and a second conductor plug, vertically disposed on both sides of the insulating pillar and in contact with the channel layer; and a metal silicate layer, located on the entire top surface of the first conductor plug and the entire top surface of the second conductor plug; and a contact window, landing on the metal silicate layer, the contact window including a titanium layer and a titanium nitride layer as barrier layers, and the titanium layer being in direct contact with the metal silicate layer.

2. The memory device as claimed in claim 1, wherein the thickness of the metal silicate layer is less than 450 Å.

3. The memory device as claimed in claim 1, wherein the metal silicate layer is a cobalt silicate layer, a nickel silicate layer, or a tungsten silicate layer.

4. The memory device as claimed in claim 1, wherein the metal silicate layer is a cobalt silicate layer or a nickel silicate layer, and the first conductor plug and the second conductor plug are made of polycrystalline silicon.

5. The memory device as claimed in claim 1, wherein the metal silicate layer is a tungsten silicate layer, and the first conductor plug and the second conductor plug are made of tungsten silicate.

6. The memory device as claimed in claim 1, wherein the vertical channel post further includes a protective layer surrounding the insulating post and filling the space between the channel layer and the first conductor plug and the second conductor plug.

7. The memory device as claimed in claim 1, wherein the top surface of the insulating pillar is higher than the top surface of the metal silicate layer.

8. The memory device as claimed in claim 1, wherein the metal silicate layer is not in contact with the charge storage structure.

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