Electronic device and method for manufacturing electronic device

Abstract

This disclosure provides an electronic device and a method for manufacturing the same. The electronic device includes a first conductive layer, a first insulating layer, a second insulating layer, a second conductive layer, a plurality of semiconductor elements, and a capping layer. The first insulating layer is disposed on the first conductive layer. In a cross-sectional view of the electronic device, the first insulating layer has two side surfaces facing each other. The second insulating layer is disposed on the first insulating layer and contacts the two side surfaces of the first insulating layer. The second conductive layer is disposed on the second insulating layer and electrically connected to the first conductive layer. The plurality of semiconductor elements are disposed on the second conductive layer and electrically connected to the second conductive layer. The capping layer is disposed on the plurality of semiconductor elements.

Description

Technical Field

[0001] This disclosure relates to an electronic device and a method for manufacturing the electronic device, particularly an electronic device having a specific insulating layer structure and a method for manufacturing the same. Prior Technology

[0002] In recent years, electronic components in electronic devices have become increasingly miniaturized and denser, leading to the development of diverse electronic component packaging technologies to integrate them. In existing technologies, electronic components can be mounted on multiple layers of insulating layers. However, the design of these multiple insulating layers within electronic devices can affect product yield. For example, when the insulating layers are thick, creating holes or cutting the insulating layers requires more time. Alternatively, the cutting process of the overall structure of the electronic device can also affect product yield. Furthermore, the edges of the cut structure are susceptible to moisture, further reducing product yield. Summary of the Invention

[0003] One of the purposes of this disclosure is to provide an electronic device and a method for manufacturing the electronic device, in order to improve the problems encountered by existing electronic devices and their manufacturing methods. By using the structure and process of the second insulating layer contacting the side surface of the first insulating layer, the product yield can be improved, thereby enhancing the reliability of the electronic device.

[0004] One embodiment of this disclosure provides an electronic device including a first conductive layer, a first insulating layer, a second insulating layer, a second conductive layer, a plurality of semiconductor elements, and a capping layer. The first insulating layer is disposed on the first conductive layer. In a cross-sectional view of the electronic device, the first insulating layer has two side surfaces facing each other. The second insulating layer is disposed on the first insulating layer and contacts the two side surfaces of the first insulating layer. The second conductive layer is disposed on the second insulating layer and electrically connected to the first conductive layer. The plurality of semiconductor elements are disposed on the second conductive layer and electrically connected to the second conductive layer. The capping layer is disposed on the plurality of semiconductor elements.

[0005] One embodiment of this disclosure provides a method for manufacturing an electronic device, comprising: providing a substrate; forming a first insulating layer on the substrate; patterning the first insulating layer to form a first via, wherein in a cross-sectional view of the electronic device, the first insulating layer has a side surface corresponding to the first via; forming a second insulating layer on the first insulating layer, wherein the second insulating layer contacts the side surface of the first insulating layer; forming a conductive layer on the second insulating layer; disposing a plurality of semiconductor elements on the conductive layer and electrically connecting the conductive layer; and disposing a capping layer on the plurality of semiconductor elements. Simple Explanation of the Diagram

[0006] Figure 1 is a cross-sectional schematic diagram of the electronic device according to the first embodiment of this disclosure. Figure 2 is a cross-sectional schematic diagram of the electronic device according to the second embodiment of this disclosure. Figure 3 is a schematic flowchart of the manufacturing method of the electronic device according to the first embodiment of this disclosure. Figures 4A to 4M are process diagrams illustrating the manufacturing method of the electronic device according to the first embodiment of this disclosure. Figure 4N is a partial process diagram of the manufacturing method of the electronic device according to the second embodiment of this disclosure. Figure 5 is a cross-sectional schematic diagram of an electronic device according to the third embodiment of this disclosure. Figures 6A to 6L are process diagrams illustrating the manufacturing method of the electronic device according to the third embodiment of this disclosure. Figure 7 is a cross-sectional schematic diagram of the electronic device according to the fourth embodiment of this disclosure. Figures 8A to 8K are process diagrams illustrating the manufacturing method of the electronic device according to the fourth embodiment of this disclosure. Figure 9 is a top view schematic diagram of some embodiments of the semiconductor elements and shielding layers of the electronic device disclosed herein. Figures 10A and 10B are schematic cross-sectional views of some embodiments of the electronic device disclosed herein. Figures 11A and 11B are schematic cross-sectional views of some other embodiments of the electronic device disclosed herein. Figure 12 is a cross-sectional schematic diagram of an embodiment of the electronic device disclosed herein docking with another device. Implementation

[0007] The following detailed description of this disclosure is provided in conjunction with specific embodiments and accompanying drawings. It should be noted that, for ease of understanding and to maintain the simplicity of the illustrations, many of the drawings in this disclosure depict only a portion of the device, and specific components in the drawings are not drawn to scale. Furthermore, the quantity and dimensions of each component in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0008] Throughout this specification and claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following specification and claims, terms such as "containing" and "including" are open-ended terms and should therefore be interpreted as "containing but not limited to...". When the terms "comprising," "including," "containing," and / or "having" are used in this specification, they specify the presence of the stated feature, region, step, operation, and / or element, but do not exclude the presence or addition of one or more other features, regions, steps, operations, elements, and / or combinations thereof.

[0009] When an element or membrane is referred to as being "on" or "connected" to another element or membrane, it can be directly on or directly connected to the other element or membrane, or there may be an inserted element or membrane between the two. Conversely, when an element is referred to as being "directly" on or "directly connected" to another element or membrane, there may be no inserted element or membrane between the two.

[0010] The directional terms used in this document, such as "up," "down," "forward," "backward," "left," and "right," are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting this disclosure.

[0011] The terms “approximately,” “equal to,” “equivalent to,” “same,” “substantially,” or “roughly” are generally interpreted as being within 20% of a given value or range, or as being within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range.

[0012] The ordinal numbers used in the specification and claims, such as "first" and "second," to modify elements do not inherently imply or represent any prior ordinal number for that element (or those elements), nor do they represent the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another with the same name. The claims and specification may not use the same terminology; therefore, a first component in the specification may be a second component in the claims.

[0013] The electronic devices disclosed herein can be applied to semiconductor packaging devices, display devices, light-emitting devices, backlight devices, antenna devices, sensing devices, or splicing devices, but are not limited thereto. The electronic devices can be bendable or flexible. The display devices can be non-self-emissive or self-emissive. The antenna devices can be liquid crystal type or non-liquid crystal type antenna devices. The sensing devices can be sensing capacitance, light, heat, or ultrasound, but are not limited thereto. The electronic devices may include electronic components, which may include semiconductor components, including passive and active components such as capacitors, resistors, inductors, diodes, transistors, and integrated circuits. Diodes may include light-emitting diodes, photodiodes, or varactor diodes. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot LEDs, but are not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. Semiconductor components may include semiconductor layers or electronic components fabricated through semiconductor processes, but are not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the foregoing, but is not limited thereto.

[0014] It should be understood that, without departing from the spirit of this disclosure, features in several different embodiments may be replaced, recombined, or mixed to complete other embodiments.

[0015] Please refer to Figure 1, which is a cross-sectional schematic diagram of an electronic device according to the first embodiment of this disclosure. The electronic device ED shown in Figure 1 can be manufactured, for example, through a redistribution layer-first (RDL-first) process. As shown in Figure 1, the electronic device ED may include a circuit layer 100, a plurality of semiconductor elements 200, and a cover layer 300. The plurality of semiconductor elements 200 may be electrically connected to the circuit layer 100, wherein the circuit layer 100 may include multiple conductive layers and multiple insulating layers stacked in the Y direction. Specifically, the circuit layer 100 may include a conductive layer 110 (which may be referred to as a first conductive layer), an insulating layer 120 (which may be referred to as a first insulating layer), an insulating layer 122 (which may be referred to as a second insulating layer), and a conductive layer 112 (which may be referred to as a second conductive layer). The conductive layer 110 may, for example, include a plurality of conductive pads 110P for electrical connection with other electronic components. An insulating layer 120 is disposed on the conductive layer 110, and in a cross-sectional view of the electronic device ED, the insulating layer 120 has two side surfaces 120S that are opposite to each other (or can be considered as being arranged in opposite directions), such as the left and right sides of the insulating layer 120 opposite to each other in direction X in FIG. 1. An insulating layer 122 is disposed on the insulating layer 120, and the insulating layer 122 contacts the two side surfaces 120S of the insulating layer 120, that is, the insulating layer 122 can contact and cover the two side surfaces 120S of the insulating layer 120. In some embodiments, the insulating layer 122 can contact and cover more than two side surfaces 120S of the insulating layer 120, that is, in addition to the cross-sectional view shown in FIG. 1, the insulating layer 122 may contact two other side surfaces of the insulating layer 120 in another cross-sectional direction different from FIG. 1, but is not limited thereto. A conductive layer 112 is disposed on the insulating layer 122 and is electrically connected to the conductive layer 110. As shown in Figure 1, direction Y can be the normal direction of the electronic device ED, that is, opposite to the top view direction of the electronic device ED, while direction X can be parallel to the horizontal direction and perpendicular to the normal direction of the electronic device ED, for example, parallel to the upper surface of the semiconductor element 200, but is not limited thereto.

[0016] As shown in Figure 1, conductive layer 110 can be the lowest conductive layer in circuit layer 100, and conductive layer 112 can be the highest conductive layer in circuit layer 100. Circuit layer 100 may also include at least one conductive layer and at least one insulating layer between conductive layer 110 and conductive layer 112 to allow for circuit redistribution. For example, the wiring process can be used to change the location of line contacts, merge lines, and / or increase the fan-out area of ​​lines, but this is not a limitation. Therefore, circuit layer 100 can be a redistribution layer (RDL), but the number of insulating and conductive layers and the line layout in circuit layer 100 are not limited to the figures provided in this disclosure.

[0017] According to the embodiment shown in FIG1, the circuit layer 100 may include a conductive layer 110, an insulating layer 120, a conductive layer 114, an insulating layer 122, a conductive layer 116, an insulating layer 124, and a conductive layer 112 stacked sequentially in the Y direction. The insulating layer 120 may be disposed on the conductive layer 110, and the conductive layer 114 may be disposed on the insulating layer 120 and electrically connected to the conductive layer 110 via a connection hole V1 in the insulating layer 120. The insulating layer 122 may be disposed on the conductive layer 114 and the insulating layer 120, and in a cross-sectional view of the electronic device ED, the insulating layer 122 has two opposing side surfaces 122S, for example, the left and right sides of the insulating layer 122 in FIG1 that are opposite each other in the X direction. The conductive layer 116 may be disposed on the insulating layer 122 and electrically connected to the conductive layer 114 via a connection hole V2 in the insulating layer 122. An insulating layer 124 may be disposed on the conductive layer 116 and the insulating layer 122, and the insulating layer 124 is in contact with two side surfaces 122S of the insulating layer 122, that is, the insulating layer 124 may contact and cover the two side surfaces 122S of the insulating layer 122. In some embodiments, the insulating layer 124 may contact and cover more than two side surfaces 122S of the insulating layer 122, that is, in addition to the cross-sectional view shown in FIG1, the insulating layer 124 may contact two other side surfaces of the insulating layer 122 in another cross-sectional direction different from FIG1, but is not limited thereto. In the cross-sectional view of the electronic device ED, the insulating layer 124 has two side surfaces 124S that are opposite to each other, for example, the left and right sides of the insulating layer 124 that are opposite to each other in the X direction in FIG1. In the X direction, a side surface 122S of the insulating layer 122 may be located between the side surface 120S of the corresponding adjacent insulating layer 120 and the side surface 124S of the insulating layer 124. The conductive layer 112 may be disposed on the insulating layer 124 and electrically connected to the conductive layer 116 via the connection hole V3 in the insulating layer 124.

[0018] The conductive layers in circuit layer 100 (such as conductive layers 110, 112, 114, and 116) may include (but are not limited to) metallic materials such as titanium, copper, aluminum, tin, nickel, gold, or silver, or other suitable conductive materials. The insulating layers in circuit layer 100 (such as insulating layers 120, 122, and 124) may include (but are not limited to) polyimide (PI), photosensitive polyimide (PSPI), photopolymer, modified polyimide (MPI), or other suitable materials. The thickness of each insulating layer may range from 2 micrometers (μm) to 6 micrometers. In some embodiments, the insulating layer may include inorganic materials, including silicon nitride, silicon oxide, silicon oxynitride, or other suitable materials, and its thickness may range from 0.05 micrometers to 1 micrometer, but is not limited thereto. The connection holes in each insulating layer (such as connection hole V1, connection hole V2 and connection hole V3) can be formed, for example, through a photolithography process, but are not limited thereto.

[0019] According to the above-mentioned structural design of circuit layer 100, compared with insulating layer 120, the upper insulating layer 122 can extend to cover the side surface 120S of the lower insulating layer 120; compared with insulating layer 122, the upper insulating layer 124 can extend to cover the side surface 122S of the lower insulating layer 122, that is, the upper insulating layer (which can be called the second insulating layer) can cover the edge of the lower insulating layer (which can be called the first insulating layer). This structural design can provide better protection, such as reducing the influence of moisture, thereby improving the reliability of electronic device ED.

[0020] In some embodiments, as shown in FIG1, the thickness H1 of the portion of conductive layer 114 located above the upper surface of insulating layer 120 may be greater than the thickness H2 of the portion of conductive layer 116 located above the upper surface of insulating layer 122, and this thickness H2 may be greater than the thickness H3 of the portion of conductive layer 112 located above the upper surface of insulating layer 124 (i.e., H1>H2>H3). In other words, the conductive layer closer to conductive layer 110 may have a larger thickness to reduce problems such as increased load or signal distortion caused by parallel circuits, thereby improving the stability of signal transmission. The term "thickness" as used in this disclosure may refer to the maximum thickness measured along direction Y from one end of the film layer or element to the other in a cross-sectional view. In some embodiments, the thickness h1 of the insulating layer 120 may be greater than the thickness h2 of the portion of the insulating layer 122 located above the upper surface of the insulating layer 120, and this thickness h2 may be greater than the thickness h3 of the portion of the insulating layer 124 located above the upper surface of the insulating layer 122 (i.e., h1>h2>h3), in order to reduce coupling problems or signal interference caused by signal amplification, thereby improving the stability of signal transmission. In some embodiments, the ratio of thickness h1 to thickness h2, the ratio of thickness h1 to thickness H2, and the ratio of thickness h3 to thickness H3 may each be in the range of 1 to 3, in order to reduce coupling problems between lines.

[0021] Multiple semiconductor elements 200 are disposed on and electrically connected to conductive layer 112, meaning that the multiple semiconductor elements 200 can be respectively disposed on the uppermost conductive layer 112 in circuit layer 100. Each semiconductor element 200 may include a first electrode 200a and a second electrode 200b. The first electrode 200a may be electrically connected to conductive layer 112. For example, the first electrode 200a may be electrically connected to conductive layer 110 through conductive layers 112, 116, and 114. The second electrode 200b may also be electrically connected to one or more of conductive layers 112, 116, 114, and 110. For example, the second electrode 200b may be electrically connected to other circuits through conductive layers 112 and 116, but this is not a limitation. The multiple semiconductor elements 200 may include at least one of light-emitting elements, integrated circuit chips, and passive components. The light-emitting element can be a die or a chip, such as a light-emitting diode die or a light-emitting diode chip, but is not limited thereto. The function of one of the plurality of semiconductor elements 200 may differ from the function of another of the plurality of semiconductor elements 200. For example, one semiconductor element 200 may provide the function of emitting light, while another semiconductor element 200 may provide the function of absorbing light, but is not limited thereto. The function of the semiconductor element 200 may include, for example, emitting light, absorbing light, control circuitry, and / or modulating electromagnetic waves, but is not limited thereto.

[0022] A capping layer 300 is disposed on a plurality of semiconductor elements 200. In a cross-sectional view of the electronic device ED, the width W1 of the capping layer 300 may be greater than the width W2 of the circuit layer 100, that is, the width W1 of the capping layer 300 may be greater than the width of the insulating layer 124. The term "width" as used in this disclosure may refer to the maximum length measured along direction X from one end of the film layer or element to the other in a cross-sectional view. Furthermore, in direction X, there may be a distance d1 between the edge of the capping layer 300 and the edge of the corresponding adjacent circuit layer 100 (or insulating layer 124). The term "distance" as used in this disclosure may refer to the minimum length measured along direction X from one end of the film layer or element to the other in a cross-sectional view. The distance d1 may range from, for example, 0.1 mm to 0.4 mm, but is not limited thereto. According to the embodiment shown in FIG1, the capping layer 300 may be, for example, a substrate. The substrate can be a rigid substrate or a flexible substrate. Rigid substrates include, for example, glass, ceramic or sapphire, while flexible substrates include, for example, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), poly(methyl methacrylate) (PMMA), but are not limited thereto.

[0023] According to the embodiment shown in FIG1, the electronic device ED may further include an adhesive layer 400 disposed between the cover layer 300 and the plurality of semiconductor elements 200. In the cross-sectional view of the electronic device ED, the adhesive layer 400 may contact two side surfaces 124S of the insulating layer 124, that is, the adhesive layer 400 covers the side surfaces 124S of the insulating layer 124, which can improve the adhesion between the cover layer 300 and the circuit layer 100, making the structure of the electronic device ED more stable. In some embodiments, the adhesive layer 400 may contact and cover more than two side surfaces 124S of the insulating layer 124, that is, in addition to the cross-sectional view shown in FIG1, the adhesive layer 400 may contact two other side surfaces 124S of the insulating layer 124 in another cross-sectional direction different from FIG1, but is not limited thereto.

[0024] According to the embodiment shown in FIG1, the electronic device ED may further include a shielding layer 500 disposed between the cover layer 300 and the insulating layer 124. The shielding layer 500 may have a plurality of vias 510, and at least one of the plurality of semiconductor elements 200 is disposed within one of the plurality of vias 510. As shown in FIG1, each semiconductor element 200 may be disposed within one via 510, but is not limited thereto. In a variation embodiment, two or more semiconductor elements 200 may also be disposed within one via 510. The shielding layer 500 may be disposed on the circuit layer 100, for example, on the insulating layer 124 and the conductive layer 112, and the vias 510 of the shielding layer 500 may expose a portion of the insulating layer 124 and a portion of the conductive layer 112. The term "via" as used in this disclosure may refer to a hole or opening that is vertically connected, that is, a portion of the film layer or element located below it is exposed, without limitation on its size. The shielding layer 500 can reduce mutual interference between semiconductor elements 200 within adjacent vias 510 during operation, for example (but not limited to) reducing light or signal interference. In some embodiments, when the semiconductor element 200 is a light-emitting element, the shielding layer 500 can serve as a light-shielding layer, and its material may include black photoresist, organic material, opaque material, white material, gray material, or other suitable materials, but is not limited thereto. In some embodiments, the shielding layer 500 can serve as a pixel definition layer (PDL) to define the pixel area, the light-emitting area of ​​the pixel, and / or the range within which the semiconductor element 200 can be disposed. As shown in FIG1, the adhesive layer 400 of the electronic device ED can be disposed between the cover layer 300 and the shielding layer 500. Furthermore, in the cross-sectional view of the electronic device ED, the shielding layer 500 may have two outer surfaces 500S, such as the two outermost surfaces (e.g., the leftmost and rightmost) of the shielding layer 500 in Figure 1, and the adhesive layer 400 may contact the two side surfaces 124S of the insulating layer 124 and the two outer surfaces 500S of the shielding layer 500, so as to improve the adhesion between different layers in the overall structure and give it better packaging reliability.

[0025] In some embodiments, as shown in FIG1, the size of each via 510 of the shielding layer 500 is larger than the size of each semiconductor element 200. Therefore, within the range of each via 510, there may be a portion of conductive layer 112 on which no semiconductor element 200 is disposed. Thus, when the originally disposed semiconductor element 200 malfunctions, the reserved space can be used to accommodate additional semiconductor elements 200. In one embodiment, the shielding layer 500 is disposed on the conductive layer 112, which may include a plurality of first conductive elements 112a and a plurality of second conductive elements 112b. Each first conductive element 112a may be a common electrode, for example, electrically connected to the conductive layer 114 through the conductive layer 116 respectively. At least one of the first conductive elements 112a may extend along the X direction and overlap with a portion of the shielding layer 500 in the Y direction, so that the first conductive element 112a is disposed within the range of two adjacent vias 510 (or two adjacent working areas) and can be shared by the semiconductor elements 200 disposed in the two adjacent vias 510, thereby reducing the space occupied by the circuit. Each second conductive element 112b can extend along direction X but does not cross the shielding layer 500 and is disposed within the range of one of the through holes 510 of the shielding layer 500. For example, each second conductive element 112b is disposed within one through hole 510 (or one working area). Taking the embodiment shown in FIG1 as an example, within the range of each through hole 510 of the shielding layer 500, there can be two first conductive elements 112a and one second conductive element 112b, wherein the first conductive element 112a can be electrically connected to the first electrode 200a of the semiconductor element 200, and the second conductive element 112b can be electrically connected to the second electrode 200b of the semiconductor element 200. Therefore, according to the above structural design, a supplementary semiconductor element 200 can be disposed on one of the first conductive elements 112a and the corresponding second conductive element 112b within the range of the through hole 510 to repair the abnormality.

[0026] In some embodiments, as shown in FIG1, the electronic device ED may optionally include an insulating layer 600 disposed on the side of the circuit layer 100 opposite to the semiconductor element 200. The insulating layer 600 may have a plurality of vias 610, and each via 610 may expose a portion of the surface of one of the conductive pads 110P of the conductive layer 110 to define the range in which a connecting element (not shown) may be disposed and electrically connected to the conductive pad 110P, wherein the connecting element is, for example, a solder ball, which can be used to electrically connect the conductive pad 110P to an external circuit or other electronic device (e.g., (but not limited to) the device DD shown in FIG12). Therefore, by providing the insulating layer 600, the subsequently formed connecting element can be effectively accommodated within the via 610, and the phenomenon of short circuits between adjacent connecting elements can be reduced. In some embodiments, the insulating layer 600 may be trapezoidal in cross-sectional view with a width that gradually increases along the positive direction Y, and its surface may be hydrophobic, so that the connecting element can be more effectively disposed within the via 610.

[0027] In some embodiments, as shown in FIG1, in direction X, there may be a distance d2 between the edge of the cover layer 300 and the edge of the corresponding adjacent shielding layer 500, and a distance d3 between the edge of the cover layer 300 and the edge of the corresponding adjacent insulating layer 600, wherein distance d2 may be greater than distance d3, and distance d3 may be greater than distance d1 (i.e., d2>d3>d1). The range of distance d2 may be, for example, 1 mm to 2 mm, and the range of distance d3 may be, for example, 0.5 mm to 1 mm, but is not limited thereto. In order to reduce component damage during the manufacturing process, the edges of the shielding layer 500 and the insulating layer 600 need to have a certain distance from the edge of the circuit layer 100, such that both distance d2 and distance d3 are greater than distance d1. Furthermore, since the upper insulating layer in circuit layer 100 extends to cover the side surface of the lower insulating layer, circuit layer 100 can generally be a trapezoid with its width gradually decreasing along the positive direction Y in cross-sectional view. The shielding layer 500 is disposed on the smaller upper surface of circuit layer 100, and the insulating layer 600 is disposed on the larger lower surface of circuit layer 100. Therefore, the distance d2 can be greater than the distance d3. In addition, through the structural design that the distance d3 is less than the distance d2, the distance between the two outermost surfaces (such as the leftmost and rightmost surfaces) of insulating layer 600 in direction X can be greater than the distance between the two outermost surfaces 500S of shielding layer 500, thereby improving structural stability and making the structure less prone to tilting. Therefore, electronic device ED can be connected to external circuits or other electronic devices more easily and stably.

[0028] Please refer to Figure 2, which is a cross-sectional schematic diagram of an electronic device according to a second embodiment of this disclosure. The electronic device ED shown in Figure 2 can be manufactured, for example, through a redistribution layer-first (RDL-first) process. According to the embodiment shown in Figure 2, the cover layer 310 can be configured to encapsulate a plurality of semiconductor elements 200, i.e., the cover layer 310 can be, for example, an encapsulation layer. The encapsulation layer includes, for example, epoxy resin, ceramic, epoxy molding compound (EMC), other suitable materials, or combinations of the above materials. The width W1 of the cover layer 310 can be greater than the width W2 of the circuit layer 100, i.e., there can be a distance d1 between the edge of the cover layer 310 and the edge of the corresponding adjacent circuit layer 100 (or insulating layer 124) in the X direction. In the cross-sectional view of the electronic device ED, the cover layer 310 can contact the two side surfaces 124S of the insulating layer 124, i.e., the cover layer 310 covers the side surfaces 124S of the insulating layer 124 to provide better protection. In some embodiments, as shown in FIG2, the cover layer 310 may also be configured to encapsulate the shielding layer 500. In the cross-sectional view of the electronic device ED, the shielding layer 500 may have two outer surfaces 500S, for example, the two outermost (e.g., the leftmost and rightmost) surfaces of the shielding layer 500 in FIG2, and the cover layer 310 may contact the two side surfaces 124S of the insulating layer 124 and the two outer surfaces 500S of the shielding layer 500 to provide better protection and improve the adhesion between layers. The relative positions and materials of other components and film layers of the electronic device ED shown in FIG2 can be referred to the relevant content of the first embodiment disclosed above, and will not be repeated here.

[0029] Please refer to Figures 3 and 4A to 4M. Figure 3 is a flowchart illustrating a method for manufacturing an electronic device according to an embodiment of this disclosure. Figures 4A to 4M are process diagrams illustrating a method for manufacturing an electronic device according to a first embodiment of this disclosure. As shown in Figure 3, a method for manufacturing an electronic device ED according to an embodiment of this disclosure may include the following steps:

[0030] Step S100: Provide a substrate;

[0031] Step S110: Form a first insulating layer on the substrate;

[0032] Step S120: Pattern the first insulating layer to form a first via, wherein in a cross-sectional view of the electronic device, the first insulating layer has one side surface corresponding to the first via;

[0033] Step S130: Form a second insulating layer on the first insulating layer, wherein the second insulating layer contacts the side surface of the first insulating layer;

[0034] Step S140: Form a conductive layer on the second insulating layer;

[0035] Step S150: Arrange multiple semiconductor elements on the conductive layer and electrically connect the conductive layer; and

[0036] Step S160: Apply a cover layer to multiple semiconductor elements.

[0037] In detail, as shown in Figure 4A, step S100 is first performed to provide a substrate SB. The substrate SB may have a patterned conductive layer 110, which may include multiple conductive pads 110P. Then, step S110 is performed to form an insulating layer 120 (which may be referred to as a first insulating layer) on the substrate SB, where the conductive layer 110 may be located between the substrate SB and the insulating layer 120. Next, as shown in Figure 4B, step S120 is performed to pattern the insulating layer 120 to form a via TH1 (which may be referred to as a first via) and multiple connection holes V1. In a cross-sectional view of the electronic device ED process, the insulating layer 120 has a side surface 120S corresponding to the via TH1, and in this structure, another via is also present on the side opposite to the side surface 120S, so that the manufactured electronic device has a symmetrical structure. The side surface 120S of the insulating layer 120 can be adjacent to or define the via TH1, that is, the sidewall of the via TH1 can correspond to the side surface 120S of the insulating layer 120. As shown in Figure 4B, the via TH1 penetrates the insulating layer 120 and exposes the substrate SB, while the connection hole V1 penetrates the insulating layer 120 located on the conductive layer 110 to expose a portion of the conductive layer 110 below the insulating layer 120, such as exposing the corresponding conductive pad 110P. The connection hole V1 and the via TH1 can be formed simultaneously in the insulating layer 120 through the photolithography process. Forming the via TH1 first in this step can effectively reduce the complexity of the internal structure of the via TH1.

[0038] As shown in Figure 4C, a patterned conductive layer 114 can then be formed on the insulating layer 120, and the conductive layer 114 can be electrically connected to the conductive layer 110 through the connection hole V1. Then, step S130 can be performed to form an insulating layer 122 (which may be referred to as a second insulating layer) on the insulating layer 120 and the conductive layer 114. Next, as shown in Figure 4D, the insulating layer 122 can be patterned to form a through hole TH2 (which may be referred to as a second through hole) and a plurality of connection holes V2, wherein the size of the formed through hole TH2 can be smaller than the size of the through hole TH1 (that is, the minimum width of the through hole TH2 is smaller than the minimum width of the through hole TH1), so that after the insulating layer 122 is patterned, the insulating layer 122 can contact the side surface 120S of the insulating layer 120. In the cross-sectional view of the process of the electronic device ED, the insulating layer 122 has a side surface 122S corresponding to the through hole TH2. The side surface 122S of the insulating layer 122 may be adjacent to or define the via TH2, that is, the sidewall of the via TH2 may correspond to the side surface 122S of the insulating layer 122. As shown in FIG4D, the via TH2 penetrates the insulating layer 122 and exposes the substrate SB, while the connecting hole V2 penetrates the insulating layer 122 located on the conductive layer 114 to expose a portion of the conductive layer 114 below the insulating layer 122.

[0039] As shown in Figure 4E, a conductive layer 116 is then formed on the insulating layer 122, and the conductive layer 116 is electrically connected to the conductive layer 114 through the connection hole V2. Next, an insulating layer 124 is formed on the insulating layer 122 and the conductive layer 116. Then, as shown in Figure 4F, the insulating layer 124 is patterned to form a via TH3 and a plurality of connection holes V3, wherein the size of the formed via TH3 can be smaller than the size of the via TH2 (that is, the minimum width of the via TH3 is smaller than the minimum width of the via TH2), so that after the insulating layer 124 is patterned, the insulating layer 124 can contact the side surface 122S of the insulating layer 122. In the cross-sectional view of the process of the electronic device ED, the insulating layer 124 has a side surface 124S corresponding to the via TH3. The side surface 124S of the insulating layer 124 can be adjacent to or define the via TH3, that is, the sidewall of the via TH3 can correspond to the side surface 124S of the insulating layer 124. As shown in Figure 4F, the through hole TH3 penetrates the insulating layer 124 and exposes the substrate SB, while the connecting hole V3 penetrates the insulating layer 124 located on the conductive layer 116 to expose a portion of the conductive layer 116 below the insulating layer 124.

[0040] As shown in Figure 4G, step S140 can then be performed, where a patterned conductive layer 112 is formed on the insulating layer 124. The conductive layer 112 can be electrically connected to the conductive layer 116 through the connection hole V3. The conductive layer 112 may include a plurality of first conductive elements 112a and a plurality of second conductive elements 112b, thus completing the fabrication of the circuit layer 100. Then, a patterned masking layer 500 can be formed on the insulating layer 124 and the conductive layer 112, wherein the masking layer 500 may have a plurality of through holes 510. Next, as shown in Figure 4H, step S150 can be performed, where a plurality of semiconductor elements 200 are disposed on the conductive layer 112 and electrically connected to the conductive layer 112. For example, each semiconductor element 200 can be transferred into one of the plurality of through holes 510 and connected to the conductive layer 112. Next, as shown in FIG4I, step S160 can be performed to deposit a cover layer 300 on a plurality of semiconductor elements 200, wherein the cover layer 300 is, for example (but not limited to), a substrate, and the substrate may be selectively deposited on the circuit layer 100 and the semiconductor elements 200 by an adhesive layer 400. According to the method for manufacturing an electronic device ED disclosed herein, during the manufacturing process, connection holes and through holes can be formed simultaneously in the insulating layer through a photolithography process. The formed through holes can correspond to the predetermined cutting positions in the subsequent cutting process, but are not limited thereto. Therefore, by forming through holes step by step layer by layer, the complexity of the internal structure of the through holes can be effectively reduced, and the subsequent cutting process can be completed more easily.

[0041] In some embodiments, as shown in FIG4I, before the cover layer 300 is disposed on the plurality of semiconductor elements 200, an adhesive layer 400 may be formed on the cover layer 300, so that the adhesive layer 400 is disposed between the cover layer 300 and the plurality of semiconductor elements 200 and can be used to adhere and fix the cover layer 300. The adhesive layer 400 is formed, for example, by coating, but is not limited thereto. Furthermore, as shown in FIG4J, after the cover layer 300 is disposed on the plurality of semiconductor elements 200, the overall structure can be flipped up and down and the substrate SB can be removed. Then, as shown in FIG4K, an insulating layer 600 may be selectively formed on the circuit layer 100, that is, a patterned insulating layer 600 is formed on the side of the circuit layer 100 opposite to the semiconductor elements 200, wherein the insulating layer 600 may have a plurality of through holes 610 to expose a portion of the surface of each conductive pad 110P. The extent of the insulating layer 600 may not exceed the edge of the circuit layer 100 to facilitate subsequent dicing processes.

[0042] Then, as shown in FIG4L, before cutting the cover layer 300, the adhesive layer 400 can be patterned to form a through-hole TH4 (which may be referred to as a third through-hole) to expose the surface of the cover layer 300. For example, the through-hole TH4 can be formed by a laser cutting process or a developing process. The position of the through-hole TH4 can correspond to the previous through-hole TH1. In some embodiments, when performing the step of patterning the adhesive layer 400, the portion of the adhesive layer 400 near the edge of the cover layer 300 can also be removed simultaneously, so that the opposite edges of the adhesive layer 400 can be more symmetrical after patterning. Next, as shown in FIG4L and FIG4M, the cover layer 300 can be cut along the cutting path CL corresponding to the through-hole TH4 to obtain a plurality of electronic devices ED as shown in FIG1. ​​For example, the cover layer 300 can be cut by a blade cutting process or a laser cutting process. By patterning the adhesive layer 400 and cutting the cover layer 300 in steps and different processes, the fabrication of the cut electronic device ED can be performed more easily. As mentioned earlier, the position of through hole TH4 (that is, the corresponding positions of through holes TH1, TH2, and TH3) corresponds to the cutting channel position.

[0043] Please refer to Figure 4N, and in conjunction with Figures 4A to 4H. Figure 4N is a partial process diagram of the manufacturing method of the electronic device according to the second embodiment of this disclosure. In some embodiments, following Figure 4H, as shown in Figure 4N, step S160 can be performed to deposit a cover layer 310 on a plurality of semiconductor elements 200, wherein the cover layer 310 is, for example (but not limited to), an encapsulation layer used to encapsulate the plurality of semiconductor elements 200. Furthermore, the cover layer 310 can contact the side surface 124S of the insulating layer 124. Next, the substrate SB can be removed, and the cover layer 310 can be cut along the cleaving path CL to obtain a plurality of electronic devices ED as shown in Figure 2. For example, the cover layer 310 can be cut using a rotary cutting process or a laser cutting process. The cleaving path CL can correspond to the positions of the aforementioned through holes TH1, TH2, and TH3.

[0044] Other embodiments of the electronic device and its manufacturing method disclosed herein will be described in detail below. For the sake of simplicity, the same reference numerals will be used to refer to the same components. The differences between the different embodiments will be described in detail below, and the same features will not be repeated.

[0045] Please refer to Figure 5, which is a cross-sectional schematic diagram of an electronic device according to a third embodiment of this disclosure. The electronic device ED shown in Figure 5 can be manufactured, for example, through a chip-first process. According to the embodiment shown in Figure 5, the electronic device ED may include a circuit layer 700, a plurality of semiconductor elements 200, and a cover layer 300. The plurality of semiconductor elements 200 may be electrically connected to the circuit layer 700, wherein the circuit layer 700 may include a conductive layer 710, an insulating layer 720, a conductive layer 712, an insulating layer 722, and a conductive layer 714 stacked sequentially in directions opposite to the Y direction. In the cross-sectional view of the electronic device ED, the insulating layer 720 has two side surfaces 720S facing each other, for example, the left and right sides of the insulating layer 720 facing each other in the X direction in Figure 5. The insulating layer 722 is in contact with the two side surfaces 720S of the insulating layer 720, that is, the insulating layer 722 can contact and cover the two side surfaces 720S of the insulating layer 720. Conductive layer 712 is electrically connected to conductive layer 710 via connection hole V12 in insulating layer 720, and conductive layer 714 is electrically connected to conductive layer 712 via connection hole V13 in insulating layer 722, wherein conductive layer 714 may include multiple conductive pads 714P. Multiple semiconductor elements 200 are disposed on and electrically connected to conductive layer 710. Cover layer 300 is disposed on multiple semiconductor elements 200, wherein cover layer 300 may be, for example, a substrate. The width W1 of cover layer 300 may be greater than the width W2 of circuit layer 700, that is, in direction X, there may be a distance d1 between the edge of cover layer 300 and the edge of the corresponding adjacent circuit layer 700 (or insulating layer 722).

[0046] According to the embodiment shown in FIG. 5, the electronic device ED may further include a packaging layer OL for packaging a plurality of semiconductor elements 200, and a conductive layer 710 may be electrically connected to the semiconductor elements 200 via a connection hole V11 in the packaging layer OL. In a cross-sectional view of the electronic device ED, the packaging layer OL has two side surfaces OLS that are opposite to each other, for example, the left and right sides of the packaging layer OL that are opposite to each other in the X direction in FIG. 5. An insulating layer 720 may contact the two side surfaces OLS of the packaging layer OL, that is, the insulating layer 720 may contact and cover the two side surfaces OLS of the packaging layer OL. In some embodiments, as shown in FIG. 5, the electronic device ED may further include an adhesive layer 400 disposed between the cover layer 300 and the plurality of semiconductor elements 200. In addition, the electronic device ED may further include a shielding layer 500 disposed between the adhesive layer 400 and the packaging layer OL. The shielding layer 500 may have a plurality of through holes 510, and at least one of the plurality of semiconductor elements 200 is disposed in one of the plurality of through holes 510.

[0047] Please refer to Figures 6A to 6L. Figures 6A to 6L are process diagrams illustrating a method for manufacturing an electronic device according to the third embodiment of this disclosure. Specifically, as shown in Figure 6A, a cover layer 300 is first provided, which may be, for example, a substrate. Then, an adhesive layer 400 is formed on the cover layer 300, followed by a shielding layer 500, which may have a plurality of through-holes 510. As shown in Figure 6B, a plurality of semiconductor elements 200 are then disposed on the cover layer 300. For example, each semiconductor element 200, with its first electrode 200a and second electrode 200b facing upwards, can be disposed in one of the plurality of through-holes 510, and the plurality of semiconductor elements 200 can be attached to the cover layer 300 through the adhesive layer 400. As shown in Figure 6C, an encapsulation layer OL is then disposed on the semiconductor element 200, so that the encapsulation layer OL surrounds and encapsulates the semiconductor element 200.

[0048] As shown in Figure 6D, the encapsulation layer OL can then be patterned to form vias TH11 and multiple connection holes V11. In the cross-sectional view, the encapsulation layer OL has a side surface OLS corresponding to the via TH11. The side surface OLS of the encapsulation layer OL can be adjacent to or define the via TH11; that is, the sidewall of the via TH11 can correspond to the side surface OLS of the encapsulation layer OL. Next, as shown in Figure 6E, a patterned conductive layer 710 can be formed on the encapsulation layer OL, and the conductive layer 710 is electrically connected to the semiconductor device 200 through the connection holes V11. The connection holes V11 and the via TH11 can be formed simultaneously in the encapsulation layer OL through a photolithography process. Forming the via TH11 first in this step effectively reduces the complexity of the internal structure of the via TH11. In some embodiments, when forming the connecting hole V11 and the through hole TH11, a portion of the adhesive layer 400 (not shown) may be removed, such that there is a distance between the edge of the cover layer 300 and the edge of the corresponding adjacent adhesive layer 400, similar to the structure of the electronic device ED shown in FIG5, but not limited thereto.

[0049] Next, as shown in FIG6F, an insulating layer 720 can be formed on the encapsulation layer OL and the conductive layer 710. Next, as shown in FIG6G, the insulating layer 720 can be patterned to form vias TH12 and a plurality of connection holes V12, wherein the size of the formed via TH12 can be smaller than the size of the via TH11 (that is, the minimum width of via TH12 is smaller than the minimum width of via TH11), so that after patterning the insulating layer 720, the insulating layer 720 can contact the side surface OLS of the encapsulation layer OL. In the cross-sectional view, the insulating layer 720 has a side surface 720S corresponding to the via TH12. The side surface 720S of the insulating layer 720 can be adjacent to or define the via TH12, that is, the sidewall of the via TH12 can correspond to the side surface 720S of the insulating layer 720. Next, as shown in FIG6H, a patterned conductive layer 712 can be formed on the insulating layer 720, and the conductive layer 712 is electrically connected to the conductive layer 710 through the connection hole V12.

[0050] Next, as shown in FIG6I, an insulating layer 722 can be formed on the insulating layer 720 and the conductive layer 712. Next, as shown in FIG6J, the insulating layer 722 is patterned to form a through-hole TH13 and a plurality of connecting holes V13, wherein the size of the formed through-hole TH13 can be smaller than the size of the through-hole TH12 (that is, the minimum width of the through-hole TH13 is smaller than the minimum width of the through-hole TH12), so that after the insulating layer 722 is patterned, the insulating layer 722 can contact the side surface 720S of the insulating layer 720. In the cross-sectional view, the insulating layer 722 has a side surface 722S corresponding to the through-hole TH13. The side surface 722S of the insulating layer 722 can be adjacent to or define the through-hole TH13, that is, the sidewall of the through-hole TH13 can correspond to the side surface 722S of the insulating layer 722.

[0051] Next, as shown in FIG6K, a patterned conductive layer 714 can be formed on the insulating layer 722, and the conductive layer 714 can be electrically connected to the conductive layer 712 through the connection hole V13. The conductive layer 714 may include multiple conductive pads 714P, thus completing the fabrication of the circuit layer 700. Next, as shown in FIG6L, the cover layer 300 and the adhesive layer 400 can be cut, for example, by laser cutting or by a cutting wheel BL as shown in FIG6L. The position of the aforementioned through hole TH13 (i.e., the corresponding position of through hole TH11 and through hole TH12) can be regarded as the cutting path position. Then, the overall structure is flipped up and down to obtain multiple electronic devices ED. In some embodiments, when forming the connection hole V11 and the through hole TH11, a portion of the adhesive layer 400 is removed at the same time so that there is a distance between the edge of the cover layer 300 and the edge of the corresponding adjacent adhesive layer 400. After cutting, a structure of multiple electronic devices ED as shown in FIG5 can be obtained, but it is not limited thereto.

[0052] Please refer to FIG7, which is a cross-sectional schematic diagram of an electronic device according to the fourth embodiment of the present disclosure. The electronic device ED shown in FIG7 can be manufactured, for example, through a chip-first process. As shown in FIG7, the electronic device ED may include a circuit layer 800, a plurality of semiconductor elements 200, and a cover layer 310. The plurality of semiconductor elements 200 may be electrically connected to the circuit layer 800, wherein the circuit layer 800 may include an insulating layer 810, a conductive layer 820, an insulating layer 812, a conductive layer 822, an insulating layer 814, and a conductive layer 824 stacked sequentially in a direction opposite to the Y direction. In the cross-sectional view of the electronic device ED, the insulating layer 810 has two side surfaces 810S opposite to each other, for example, the left and right side surfaces of the insulating layer 810 opposite to each other in the X direction in FIG7, and the insulating layer 812 has two side surfaces 812S opposite to each other, for example, the left and right side surfaces of the insulating layer 812 opposite to each other in the X direction in FIG7. Insulating layer 812 can contact and cover two side surfaces 810S of insulating layer 810, and insulating layer 814 can contact and cover two side surfaces 812S of insulating layer 812. Conductive layer 822 can be electrically connected to conductive layer 820 via connecting hole V22 in insulating layer 812, and conductive layer 824 can be electrically connected to conductive layer 822 via connecting hole V23 in insulating layer 814, wherein conductive layer 824 may include a plurality of conductive pads 824P.

[0053] Multiple semiconductor elements 200 are disposed on and electrically connected to the conductive layer 820, i.e., the conductive layer 820 can be electrically connected to the semiconductor elements 200 via a connection hole V21 in the insulating layer 810. A cover layer 310 is disposed on the multiple semiconductor elements 200, wherein the cover layer 310 can be configured to encapsulate the multiple semiconductor elements 200, i.e., the cover layer 310 can be, for example, an encapsulation layer. The width W1 of the cover layer 310 can be greater than the width W2 of the circuit layer 800, i.e., there can be a distance d1 between the edge of the cover layer 310 and the edge of the corresponding adjacent circuit layer 800 (or insulating layer 814) in the X direction.

[0054] In some embodiments, as shown in FIG7, the electronic device ED may further include a shielding layer 500 disposed on the circuit layer 800, for example, disposed on the insulating layer 810. The shielding layer 500 may have a plurality of vias 510, at least one of the plurality of semiconductor elements 200 is disposed within one of the plurality of vias 510, and a cover layer 310 surrounds the semiconductor element 200 and the shielding layer 500. In one embodiment, when the semiconductor element 200 is a light-emitting element, the shielding layer 500 may enable the corresponding semiconductor element 200 to have the effect of light diffusion. Conversely, in the embodiment shown in FIG5, when the semiconductor element 200 is a light-emitting element, the shielding layer 500 may limit the signal emitted by the corresponding semiconductor element 200, for example, to limit the emission angle of its signal to directly upward.

[0055] Please refer to Figures 8A to 8K. Figures 8A to 8K are partial process diagrams of a manufacturing method for an electronic device according to the fourth embodiment of this disclosure. Specifically, as shown in Figure 8A, a substrate SB is first provided. Then, an adhesive layer 400 is formed on the substrate SB, followed by a shielding layer 500 formed on the adhesive layer 400, wherein the shielding layer 500 may have a plurality of through-holes 510. As shown in Figure 8B, a plurality of semiconductor elements 200 are then disposed on the substrate SB. For example, each semiconductor element 200 may be disposed face-down within one of the plurality of through-holes 510, and the plurality of semiconductor elements 200 may be attached to the substrate SB through the adhesive layer 400. As shown in Figure 8C, a cover layer 310 is then disposed on the semiconductor element 200, so that the cover layer 310 surrounds and encapsulates the semiconductor element 200. Next, as shown in Figure 8D, the adhesive layer 400 and the substrate SB can be removed.

[0056] Next, as shown in Figure 8E, the overall structure can be flipped upside down, and a patterned insulating layer 810 can be formed on the cover layer 310. The patterned insulating layer 810 has through holes TH21 and multiple connecting holes V21. In the cross-sectional view, the insulating layer 810 has a side surface 810S corresponding to the through hole TH21. The side surface 810S of the insulating layer 810 can be adjacent to or define the through hole TH21, that is, the sidewall of the through hole TH21 can correspond to the side surface 810S of the insulating layer 810. The connecting holes V21 and the through holes TH21 can be formed simultaneously in the insulating layer 810 through the photolithography process. Forming the through hole TH21 first in this step can effectively reduce the complexity of the internal structure of the through hole TH21.

[0057] Next, as shown in FIG8F, a conductive layer 820 can be formed on the insulating layer 810, and the conductive layer 820 is electrically connected to the semiconductor element 200 through the connection hole V21. Then, an insulating layer 812 can be formed on the insulating layer 810 and the conductive layer 820. Next, as shown in FIG8G, the insulating layer 812 can be patterned to form a via TH22 and a plurality of connection holes V22, wherein the size of the formed via TH22 can be smaller than the size of the via TH21 (that is, the minimum width of the via TH22 is smaller than the minimum width of the via TH21), so that after the insulating layer 812 is patterned, the insulating layer 812 can contact the side surface 810S of the insulating layer 810. In the cross-sectional view, the insulating layer 812 has a side surface 812S corresponding to the via TH22. The side surface 812S of the insulating layer 812 can be adjacent to or define the via TH22, that is, the sidewall of the via TH22 can correspond to the side surface 812S of the insulating layer 812.

[0058] Next, as shown in FIG8H, a conductive layer 822 can be formed on the insulating layer 812, and the conductive layer 822 can be electrically connected to the conductive layer 820 through the connecting hole V22. Then, an insulating layer 814 can be formed on the insulating layer 812 and the conductive layer 822. Next, as shown in FIG8I, the insulating layer 814 is patterned to form a through hole TH23 and a plurality of connecting holes V23, wherein the size of the formed through hole TH23 can be smaller than the size of the through hole TH22 (that is, the minimum width of the through hole TH23 is smaller than the minimum width of the through hole TH22), so that after the insulating layer 814 is patterned, the insulating layer 814 can contact the side surface 812S of the insulating layer 812. In the cross-sectional view, the insulating layer 814 has a side surface 814S corresponding to the through hole TH23. The side surface 814S of the insulating layer 814 can be adjacent to or define the through hole TH23, that is, the sidewall of the through hole TH23 can correspond to the side surface 814S of the insulating layer 814.

[0059] Next, as shown in Figure 8J, a conductive layer 824 can be formed on the insulating layer 814, and the conductive layer 824 can be electrically connected to the conductive layer 822 through the connection hole V23. The conductive layer 824 may include multiple conductive pads 824P, thus completing the fabrication of the circuit layer 800. Next, as shown in Figure 8K, the cover layer 310 can be cut, for example, through a laser cutting process or a cutting wheel BL as shown in Figure 8K. The position of the aforementioned through hole TH23 (i.e., the corresponding position of through holes TH21 and TH22) can be regarded as the cutting path position. Then, by flipping the overall structure upside down, multiple electronic devices ED as shown in Figure 7 can be obtained.

[0060] Please refer to Figure 9, which is a top view schematic diagram of some embodiments of the semiconductor elements and shielding layer of the electronic device disclosed herein. As shown in Examples (I) and (II) of Figure 9, a plurality of semiconductor elements 200 may be arranged in an array and surrounded by a shielding layer 500, and the plurality of semiconductor elements 200 may include semiconductor elements 210, 220, and 230 having the same function or properties, or at least one semiconductor element may have different functions or properties from other semiconductor elements. In one embodiment, for example, when the electronic device ED is a display device, semiconductor elements 210, 220, and 230 may be light-emitting elements, for example, representing light-emitting elements that can emit red light, green light, and blue light respectively, but are not limited thereto. In Example (I) of Figure 9, semiconductor elements 210, 220, and 230 can collectively constitute a semiconductor unit GR and be simultaneously disposed within one of the vias 510 of the masking layer 500. Semiconductor elements 210, 220, and 230, as a group of semiconductor units GR, can be considered as a single pixel, but are not limited thereto. In Example (II) of Figure 9, semiconductor elements 210, 220, and 230 can be disposed in different vias 510 of the masking layer 500. According to Examples (I) and (II) of Figure 9, the placement of semiconductor elements 200 may result in differences in the spacing between different semiconductor elements 200. Therefore, two adjacent semiconductor elements 200 emitting the same color of light (i.e., two adjacent semiconductor elements 210, two adjacent semiconductor elements 220, or two adjacent semiconductor elements 230) may have the same or different spacing in direction X. For example, the ratio of spacing p1 to spacing p2 may be 0.8 to 1.2, or spacing p1 may be different from spacing p2. Spacing p1 or spacing p2 can be measured, for example, from one side of one semiconductor element 210 along direction X to the corresponding side of the other adjacent semiconductor element 210. Furthermore, two adjacent vias 510 of the shielding layer 500 may have the same spacing in direction X to improve visual appeal. For example, spacing P1 may be equal to spacing P2, where spacing P1 or spacing P2 can be measured from one side of one via 510 along direction X to the corresponding side of the other adjacent via 510.

[0061] Please refer to Figures 10A and 10B. Figures 10A and 10B are schematic cross-sectional views of some embodiments of the electronic device disclosed herein. As shown in Figures 10A and 10B, the surface 300S of the cover layer 300 can be processed to form a lens structure or a roughened structure to improve light extraction efficiency. This can be formed, for example, through a physical polishing process or a chemical etching process, wherein the surface 300S can be located on the side opposite to the semiconductor element 200. In some embodiments, the lens structure or roughened structure can be formed on the upper surface of the cover layer 300 shown in Figure 1 or Figure 5, or on the upper surface of the cover layer 310 shown in Figure 2 or Figure 7.

[0062] Please refer to Figures 11A and 11B. Figures 11A and 11B are schematic cross-sectional views of some other embodiments of the electronic device disclosed herein. As shown in Figures 11A and 11B, a plurality of semiconductor elements 200 may include semiconductor elements 240 and 250, and semiconductor elements 240 and 250 may be surrounded and encapsulated by an encapsulation layer OL1. Semiconductor element 240 may include a first electrode 240a and a second electrode 240b opposite to each other in the Y direction, while semiconductor element 250 may include a first electrode 250a and a second electrode 250b adjacent to each other in the X direction. In one embodiment, when the electronic device ED is a display device, semiconductor elements 240 and 250 may be light-emitting elements. Semiconductor element 240 may be, for example, a vertical-type light-emitting element and may emit, for example, red light, thereby improving its luminous efficiency or increasing the connection area of ​​the electrodes. In the Y direction, the thickness of semiconductor element 240 may be, for example, 4 micrometers to 8 micrometers to improve structural stability. Semiconductor element 250 may be a planar-type light-emitting element or a flip-chip light-emitting element and may emit blue or green light, for example. In the Y direction, the thickness of semiconductor element 250 may be, for example, 2 micrometers to 4 micrometers, that is, it may have a thinner thickness than semiconductor element 240, so as to make the element thinner and lighter.

[0063] According to the electronic device ED shown in FIG11A, the first electrode 240a of the semiconductor element 240 can be disposed on the conductive layer 112 and electrically connected to the conductive layer 110 through patterned conductive layers 112, 116 and 114. The second electrode 240b of the semiconductor element 240 can be electrically connected to the patterned conductive layers 112 and 116 through a conductive layer TE disposed on the surface of the encapsulation layer OL1 and extending to the outer surface 500S of the shielding layer 500. The conductive layer TE is, for example, a transparent conductive layer, including indium tin oxide (ITO) and indium zinc oxide (IZO), but not limited thereto. The first electrode 250a and the second electrode 250b of the semiconductor element 250 can be disposed on the conductive layer 112. The first electrode 250a is electrically connected to the conductive layer 110 through patterned conductive layers 112, 116 and 114, and the second electrode 250b is electrically connected to the patterned conductive layers 112 and 116.

[0064] According to the electronic device ED shown in FIG11B, the first electrode 240a of the semiconductor element 240 can be disposed on the conductive layer 820 and electrically connected to the conductive layer 824 through the patterned conductive layer 820 and conductive layer 822, and the second electrode 240b of the semiconductor element 240 can be electrically connected to the patterned conductive layer 820 through the conductive layer TE disposed on the surface of the encapsulation layer OL1 and extending to the outer surface 500S of the shielding layer 500. The first electrode 250a and the second electrode 250b of the semiconductor element 250 can be disposed on the conductive layer 820 and electrically connected to the conductive layer 820.

[0065] Please refer to Figure 12, which is a cross-sectional schematic diagram of an embodiment of the electronic device disclosed herein interfacing with another device. As shown in Figure 12, the electronic device ED can interfacing with the device DD. The electronic device ED can be any of the electronic devices ED manufactured using a redistribution layer-first (RDL-first) or chip-first process as described in the foregoing embodiments. The electronic device ED shown in Figure 11B is used as an example in Figure 12, but is not limited thereto. The device DD may include a circuit layer 900 and a control element 1000. The control element 1000 can be electrically connected to the circuit layer 800 of the electronic device ED through the circuit layer 900. The control element 1000 can be, for example (but not limited to), a driving element, an integrated circuit chip, or a microcircuit chip (Micro IC). In some embodiments, the device DD may also include a package layer OL2, an adhesive layer 410, and a substrate SB1. The control element 1000 can be surrounded by the package layer OL2 and attached to the substrate SB1 through the adhesive layer 410. The circuit layer 900 can be disposed on the control element 1000.

[0066] According to the device DD shown in Figure 12, the circuit layer 900 may include a conductive layer 910, an insulating layer 920, a conductive layer 912, an insulating layer 922, and a conductive layer 914 stacked sequentially in the Y direction to allow for circuit redistribution. For example, the wiring process can be used to change the location of the line contacts and increase the fan-out area of ​​the lines. Specifically, in the cross-sectional view, the insulating layer 920 can contact and cover the two opposing side surfaces of the encapsulation layer OL2, and the insulating layer 922 can contact and cover the two opposing side surfaces of the insulating layer 920. The control element 1000 may include a plurality of conductive pads 1000P. A patterned conductive layer 910 may be electrically connected to the conductive pads 1000P of the control element 1000 via a connection hole in the encapsulation layer OL2. A patterned conductive layer 912 may be electrically connected to the conductive layer 910 via a connection hole in the insulating layer 920. A patterned conductive layer 914 may be electrically connected to the conductive layer 912 via a connection hole in the insulating layer 922. The conductive layer 914 may include a plurality of conductive pads 914P.

[0067] Multiple conductive pads 824P of the electronic device ED can be connected one-to-one with multiple conductive pads 914P of the device DD. For example, conductive pads 824P can be electrically connected to conductive pads 914P through connecting elements such as solder balls (not shown), but are not limited to this. That is, the number of conductive pads 824P can correspond to or be the same as the number of conductive pads 914P, and the placement positions of conductive pads 824P and conductive pads 914P can correspond to each other. Therefore, in the electronic device ED, the circuit layer 800 can consolidate the lines to reduce the number of conductive pads. For example, the number of conductive pads in the conductive layer 820, which is electrically connected to the electrodes of multiple semiconductor elements 200, can be reduced and consolidated into multiple conductive pads 824P. Furthermore, in the device DD, the circuit layer 900 can change the position of the line contacts and increase the line fan-out area. For example, the multiple conductive pads 1000P of the control element 1000 can be fanned out into multiple conductive pads 914P. Based on the above structural design, the conductive pad 824P of the electronic device ED and the conductive pad 914P of the device DD can be connected more easily and effectively, thereby improving the connection effect between the electronic device ED and the device DD.

[0068] In summary, the electronic device and manufacturing method thereof according to the embodiments disclosed herein provide better protection by having the upper insulating layer contact the side surface of the lower insulating layer, thereby improving the reliability of the electronic device. Furthermore, by forming the connecting holes and through holes step-by-step, the depth of the through holes can be effectively reduced, and subsequent cutting processes can be completed more easily.

[0069] The above description is merely an embodiment of this disclosure and is not intended to limit the scope of this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

[0070] 100, 700, 800, 900: Circuit layers 1000: Control element 110, 112, 114, 116, 710, 712, 714, 820, 822, 824, 910, 912, 914: Conductive layer 110P, 714P, 824P, 914P: Conductive pads 112a: First conductive element 112b: Second conductive element 120, 122, 124, 720, 722, 810, 812, 814, 920, 922: Insulation layer 120S, 122S, 124S, 720S, OLS, 722S, 810S, 812S, 814S: Side surface 200, 210, 220, 230, 240, 250: Semiconductor components 200a, 240a, 250a: First electrode 200b, 240b, 250b: Second electrode 300, 310: Overlay 300S: Surface 400, 410: Adhesive layer 500: Shielding layer 500S: Outer surface 510, 610, TH1, TH2, TH3, TH4, TH11, TH12, TH13, TH21, TH22, TH23: Through holes 600: Insulation layer BL: Blade Wheel CL: Cutting track d1, d2, d3: Distance DD: Device ED: Electronic Devices GR: Semiconductor unit H1, H2, H3, h1, h2, h3: Thickness TE: Transparent conductive layer OL, OL1, OL2: Encapsulation layer P1, P2, p1, p2: Spacing S100, S110, S120, S130, S140, S150, S160: Steps SB,SB1:Substrate V1, V2, V3, V11, V12, V13, V21, V22, V23: Connecting holes W1, W2: Width X, Y: Direction

Claims

1. An electronic device comprising: First conductive layer; A first insulating layer is disposed on the first conductive layer, wherein, in a cross-sectional view of the electronic device, the first insulating layer has two side surfaces facing each other; a second insulating layer is disposed on the first insulating layer and contacts the two side surfaces of the first insulating layer; a second conductive layer is disposed on the second insulating layer and electrically connected to the first conductive layer; a plurality of semiconductor elements are disposed on the second conductive layer and electrically connected to the second conductive layer; and a cover layer is disposed on the plurality of semiconductor elements; wherein, in the cross-sectional view of the electronic device, in one direction, the distance between the two side surfaces of the first insulating layer is the maximum width of the first insulating layer, and the width of the cover layer is greater than the width of the second insulating layer.

2. The electronic device as claimed in claim 1 further includes an adhesive layer disposed between the cover layer and the plurality of semiconductor elements.

3. The electronic device as claimed in claim 2, wherein in the cross-sectional view of the electronic device, the second insulating layer has two side surfaces opposite to each other, and the adhesive layer contacts the two side surfaces of the second insulating layer.

4. The electronic device as claimed in claim 1, wherein the cover layer is configured to encapsulate the plurality of semiconductor elements.

5. The electronic device as claimed in claim 4, wherein in the cross-sectional view of the electronic device, the second insulating layer has two side surfaces opposite to each other, and the cover layer contacts the two side surfaces of the second insulating layer.

6. The electronic device as claimed in claim 1, wherein the plurality of semiconductor elements includes at least one of a light-emitting element, an integrated circuit chip, and a passive element.

7. The electronic device of claim 6 further includes a shielding layer disposed between the cover layer and the second insulating layer, wherein the shielding layer has a plurality of through holes, and at least one of the plurality of semiconductor elements is disposed within one of the plurality of through holes.

8. The electronic device as claimed in claim 7 further includes an adhesive layer disposed between the cover layer and the shielding layer.

9. The electronic device of claim 8, wherein in the cross-sectional view of the electronic device, the second insulating layer has two side surfaces opposite to each other, the shielding layer has two outer surfaces, and the adhesive layer contacts the two side surfaces of the second insulating layer and the two outer surfaces of the shielding layer.

10. The electronic device as claimed in claim 7, wherein the cover layer is configured to encapsulate the shielding layer.

11. The electronic device of claim 10, wherein in the cross-sectional view of the electronic device, the second insulating layer has two side surfaces opposite to each other, the shielding layer has two outer surfaces, and the covering layer contacts the two side surfaces of the second insulating layer and the two outer surfaces of the shielding layer.

12. The electronic device as claimed in claim 1, wherein the function of one of the plurality of semiconductor elements is different from the function of another of the plurality of semiconductor elements.

13. A method of manufacturing an electronic device, comprising: Provide a substrate; A first insulating layer is formed on the substrate; The first insulating layer is patterned to form a first via, the first via penetrating the first insulating layer and exposing the substrate, wherein in a cross-sectional view of the electronic device, the first insulating layer has a side surface corresponding to the first via; a second insulating layer is formed on the first insulating layer, wherein the second insulating layer contacts the side surface of the first insulating layer; a conductive layer is formed on the second insulating layer; a plurality of semiconductor elements are disposed on the conductive layer and electrically connected to the conductive layer; and a capping layer is disposed on the plurality of semiconductor elements.

14. The method as described in claim 13, further comprising: The second insulating layer is patterned to form a second via, wherein in the cross-sectional view of the electronic device, the second insulating layer has one side surface corresponding to the second via.

15. The method of claim 14, wherein the covering layer contacts the side surface of the second insulating layer.

16. The method as described in claim 13, further comprising: After the cover layer is applied to the plurality of semiconductor elements, the substrate is removed; And cutting the covering layer.

17. The method as described in claim 13, further comprising: Before the capping layer is applied to the plurality of semiconductor elements, an adhesive layer is first formed on the capping layer.

18. The method as described in claim 17, further comprising: After the cover layer is applied to the plurality of semiconductor elements, the substrate is removed; And cutting the covering layer.

19. The method as described in claim 18, further comprising: Before cutting the cover layer, the adhesive layer is patterned to form a third through-hole.

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