Electronic device

Abstract

This disclosure provides an electronic device, an assembly structure, and a manufacturing method. The electronic device includes a base portion, a circuit structure, an insulating structure, a first conductive layer, a through-hole structure, a first outer layer, and a second outer layer. The circuit structure is disposed on a first surface of the base portion. The insulating structure is disposed on the circuit structure. The first conductive layer is disposed on the insulating structure. The through-hole structure extends through the insulating structure and electrically connects the first conductive layer and the circuit structure. The first outer layer is disposed on the first conductive layer. The second outer layer is disposed on the first outer layer. The second outer layer includes an oxide material to improve the coplanarity of the outermost surface of the second outer layer.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 929,989 (i.e., priority date "October 29, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to an electronic device, an assembly structure, and a manufacturing method. More specifically, this disclosure includes an electronic device having an outermost layer of oxide material, an assembly structure including the electronic device, and a manufacturing method. Prior Technology

[0003] Semiconductor structures are used in a wide variety of electronic applications, and their dimensions are constantly shrinking to meet current application requirements. However, various problems arise during the shrinkage process, affecting the final electrical characteristics, quality, cost, and yield. A typical semiconductor structure has multiple bumps arranged on its outer surface. If the outer surface is wavy, the bumps will be tilted or have different heights. As a result, poor connections will form between the semiconductor structure and another electronic device, and the yield of the assembled structure will be reduced. Therefore, the coplanarity and flatness of the outer surface of the semiconductor structure are critical issues.

[0004] This background discussion section provides background information only. The statements in this background discussion do not acknowledge that the subject matter disclosed herein constitutes prior art related to this disclosure, and no part of this background discussion should be used as an admission that any part of this application constitutes prior art related to this disclosure.

[0005] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of the "prior art" of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides an electronic device. The electronic device includes a base portion, a circuit structure, an insulating structure, a first conductive layer, a through-hole structure, a first outer layer, and a second outer layer. The base portion has a first surface. The circuit structure is disposed on the first surface of the base portion. The insulating structure is disposed on the circuit structure. The first conductive layer is disposed on the insulating structure. The through-hole structure extends through the insulating structure and electrically connects the first conductive layer and the circuit structure. The first outer layer is disposed on the first conductive layer. The second outer layer is disposed on the first outer layer. The second outer layer includes an oxide material to improve the coplanarity of an outermost surface of the second outer layer.

[0007] Another embodiment of this disclosure provides an assembly structure. The assembly structure includes a first electronic device, a second electronic device, and a substrate. The first electronic device includes a base portion, an outermost layer, and a bump. The base portion has a first surface. The outermost layer is disposed near the first surface of the base portion. The outermost layer includes an oxide material to improve the coplanarity of the outermost surface of the outermost layer. The bump extends through the outermost layer and beyond the outermost surface of the outermost layer. The second electronic device includes a base portion, a through-hole, a solder pad, and a connecting element. The base portion has a first surface and a second surface opposite to the first surface. The through-hole extends through the base portion. The solder pad is disposed near the second surface of the base portion of the second electronic device and electrically connects the through-hole and the bump of the first electronic device. The connecting element is disposed near the first surface of the base portion of the second electronic device and electrically connected to the solder pad via the through-hole. The substrate is electrically connected to the connecting element.

[0008] Another embodiment of this disclosure provides a method for manufacturing an electronic device. The method includes: providing a body including a base portion having a first surface, a circuit structure disposed on the first surface of the base portion, and an insulating structure disposed on the circuit structure; forming a through-hole extending through the insulating structure; forming a first conductive layer on the insulating structure and forming an interconnect layer on a sidewall of the through-hole, wherein the first conductive layer connects to the interconnect layer, and wherein the first conductive layer is electrically connected to the circuit structure via the interconnect layer; forming a first outer layer on the first conductive layer; and forming a second outer layer on the first outer layer, wherein the second outer layer comprises an oxide material.

[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0010] When referring to the drawings in conjunction with the embodiments and the scope of the patent application, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements. Figure 1 is a flowchart illustrating an embodiment of a method for manufacturing an electronic device. Figures 2 to 15 are schematic diagrams illustrating the various stages of a method for manufacturing an assembly structure according to an embodiment of this disclosure. Implementation

[0011] The following description of this disclosure, accompanied by drawings incorporated into and forming part of this specification, illustrates embodiments of the disclosure; however, the disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0012] The terms "an embodiment," "an embodiment," "an illustrative embodiment," "an other embodiment," and "another embodiment" refer to embodiments described in this disclosure that may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0013] To ensure a complete understanding of this disclosure, the following description provides detailed steps and structures. It is clear that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting the disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description but is defined by the claims.

[0014] Figure 1 is a flowchart illustrating a method 900 for manufacturing an electronic device 1 according to an embodiment of this disclosure. Figures 2 to 15 are schematic diagrams illustrating various stages of a method for manufacturing an assembly structure 5 according to an embodiment of this disclosure. In some embodiments, Figures 2 to 10 illustrate various stages of a method for manufacturing an electronic device 1 according to an embodiment of this disclosure. For a better understanding of the aspects of this disclosure, at least some of these figures have been simplified.

[0015] Referring to Figure 2, in step S901, a main body 6 is provided. The main body 6 includes a base portion 10, a first intermediate layer 11, a plurality of first interconnect vias 113, a circuit structure 12, a second intermediate layer 13, a plurality of second interconnect vias 133, a second conductive layer 14, and an insulating structure 18. The base portion 10 has a first surface 101 and a second surface 102 opposite to the first surface 101. The first surface 101 is the active surface. The second surface 102 is the back surface.

[0016] In some embodiments, the base portion 10 is a substrate and may include a dielectric material, such as an oxide material or a nitride material. Alternatively, the base portion 10 is a substrate and includes, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials.

[0017] In some embodiments, the base portion 10 includes a semiconductor device of circuitry, such as a memory cell. In some embodiments, the memory cell includes a dynamic random access memory cell (DRAM cell).

[0018] Furthermore, the base portion 10 is or includes portions of an integrated circuit (IC) chip, comprising various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally-diffused metal-oxide-semiconductor (LDMOS) transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable IC components, or combinations thereof.

[0019] A first intermediate layer 11 is disposed between the first surface 101 of the base portion 10 and the circuit structure 12. The first intermediate layer 11 is also referred to as a "lower intermediate layer" or "upper intermediate layer." The first intermediate layer 11 serves to electrically insulate the circuit structure 12 from the first surface 101 of the base portion 10. Therefore, the circuit structure 12 is electrically insulated from the first surface 101 of the base portion 10 by the first intermediate layer 11. In some embodiments, the first intermediate layer 11 comprises a dielectric material or an electrically insulating material, such as an oxide material or a nitride material.

[0020] A first interconnect via 113 is disposed in the first intermediate layer 11. The first interconnect via 113 extends through the first intermediate layer 11 and is used to electrically connect the circuit structure 12 and the first surface 101 of the base portion 10. Therefore, the circuit structure 12 is electrically connected to the first surface 101 of the base portion 10 via the first interconnect via 113. In some embodiments, the first interconnect via 113 comprises a conductive material, such as a metallic material. For example, the first interconnect via 113 may comprise copper (Cu).

[0021] The circuit structure 12 is disposed on or above the first intermediate layer 11 and the first surface 101 of the base portion 10. In some embodiments, the first intermediate layer 11 is disposed on and contacts the first surface 101 of the base portion 10. The circuit structure 12 is disposed on and contacts the first intermediate layer 11. Alternatively, at least one layer (e.g., an insulating layer or a conductive layer) may be present between the circuit structure 12 and the first surface 101 of the base portion 10.

[0022] The circuit structure 12 is a redistribution layer (RDL) structure and may include a plurality of dielectric layers 124, a plurality of redistribution layers (RDLs) 125, and a plurality of inner layer vias 126. The dielectric layers 124 are interlayer dielectric (ILD) layers and include silicon oxide (SiO₂), silicon nitride (SiN), and / or silicon carbonitride (SiCN). The redistribution layers 125 and the inner layer vias 126 are embedded in the dielectric layers 124. The redistribution layers 125 include a plurality of conductors and a plurality of pads. The redistribution layers 125 are electrically connected to each other vias 126. The circuit structure 12 is also referred to as a "conductive structure". In some embodiments, the redistribution layers 125 are electrically connected to a first interconnect via 113.

[0023] The second intermediate layer 13 is disposed between the second conductive layer 14 and the circuit structure 12. The second intermediate layer 13 may be referred to as the "lower intermediate layer" or the "upper intermediate layer". The second intermediate layer 13 is used to electrically insulate the circuit structure 12 from the second conductive layer 14. Therefore, the circuit structure 12 is electrically insulated from the second conductive layer 14 by the second intermediate layer 13. In some embodiments, the second intermediate layer 13 includes a dielectric material or an electrically insulating material, such as an oxide material or a nitride material.

[0024] A second interconnect via 133 is disposed in the second intermediate layer 13. The second interconnect via 133 extends through the second intermediate layer 13 and is used to electrically connect the circuit structure 12 and the second conductive layer 14. Therefore, the circuit structure 12 is electrically connected to the second conductive layer 14 via the second interconnect via 133. In some embodiments, the second interconnect via 133 includes a conductive material, such as a metallic material. For example, the second interconnect via 133 may include copper (Cu).

[0025] A second conductive layer 14 is disposed between the circuit structure 12 and the insulating structure 18. In some embodiments, a second intermediate layer 13 covers and contacts the circuit structure 12. The second conductive layer 14 is inserted between the second intermediate layer 13 and the insulating structure 18. In some embodiments, the second conductive layer 14 comprises a metal layer, such as an aluminum (Al) layer or a copper layer, and covers and contacts the second intermediate layer 13. The second conductive layer 14 may be electrically connected to the circuit structure 12 via a second interconnect via 133.

[0026] An insulating structure 18 is disposed on or above the circuit structure 12. In some embodiments, the insulating structure 18 covers and contacts the second conductive layer 14. The insulating structure 18 includes a first insulating layer 15, a second insulating layer 16, and a third insulating layer 17. Thus, the first insulating layer 15, the second insulating layer 16, and the third insulating layer 17 collectively define the insulating structure 18. The insulating structure 18 has a first surface 181 (e.g., a top surface) facing away from the circuit structure 12 and the base portion 10.

[0027] A first insulating layer 15 is disposed on or above the circuit structure 12. The first insulating layer 15 covers and contacts the second conductive layer 14. The first insulating layer 15 is a passivation layer or an electrical insulating layer and includes an oxide material or a nitride material, such as SiO₂, SiN, Si₃N₄ and / or SiCN. The first insulating layer 15 may be a buffer layer. The first insulating layer 15 has a first thickness T1.

[0028] A second insulating layer 16 is disposed on or above the first insulating layer 15. The second insulating layer 16 is inserted between the first insulating layer 15 and the third insulating layer 17. The second insulating layer 16 covers and contacts the first insulating layer 15. The second insulating layer 16 is a passivation layer or an electrical insulating layer and comprises an oxide or nitride material, such as SiO₂, SiN, Si₃N₄, and / or SiCN. The second insulating layer 16 is a protective layer and prevents external moisture from entering the circuit structure 12 and the first surface 101 of the base portion 10. The material of the second insulating layer 16 is different from the material of the first insulating layer 15. The second insulating layer 16 has a second thickness T2.

[0029] A third insulating layer 17 is disposed on or above the second insulating layer 16. The third insulating layer 17 covers and contacts the second insulating layer 16. A first surface (e.g., top surface) of the third insulating layer 17 is a first surface 181 (e.g., top surface) of the insulating structure 18. The third insulating layer 17 is a passivation layer or an electrical insulating layer and includes an oxide material or a nitride material, such as SiO₂, SiN, Si₃N₄, and / or SiCN. The third insulating layer 17 has a third thickness T3. The material of the third insulating layer 17 is the same as the material of the first insulating layer 15. The material of the third insulating layer 17 is different from the material of the second insulating layer 16. For example, the third insulating layer 17 includes an oxide material, the first insulating layer 15 may include an oxide material, and the second insulating layer 16 includes a nitride material.

[0030] The third thickness T3 of the third insulating layer 17 is greater than the second thickness T2 of the second insulating layer 16 and the first thickness T1 of the first insulating layer 15. The second thickness T2 of the second insulating layer 16 is greater than the first thickness T1 of the first insulating layer 15. In some embodiments, the first thickness T1 of the first insulating layer 15 is 0.6 μm to 1.0 μm. For example, the first thickness T1 of the first insulating layer 15 is about 0.8 μm. In some embodiments, the second thickness T2 of the second insulating layer 16 is 0.8 μm to 1.2 μm. For example, the second thickness T2 of the second insulating layer 16 is about 0.8 μm. In some embodiments, the third thickness T3 of the third insulating layer 17 is 4.0 μm to 5.0 μm. For example, the third thickness T3 of the third insulating layer 17 is about 4.5 μm.

[0031] Referring to FIG3, in step S902, a through hole 183 extending through the insulating structure 18 is formed. The through hole 183 is recessed from a first surface 181 (e.g., the top surface) of the insulating structure 18. The through hole 183 extends through the first insulating layer 15, the second insulating layer 16, and the third insulating layer 17 to expose a portion of the second conductive layer 14. Thus, the insulating structure 18 defines the through hole 183 extending through the insulating structure 18.

[0032] Referring to FIG4, in step S903, a first conductive layer 19 is formed or disposed on a first surface 181 (e.g., top surface) of the insulating structure 18. The first conductive layer 19 has a first surface 191 (e.g., top surface) that is away from the first surface 181 (e.g., top surface) of the insulating structure 18. An interconnect layer 201 is formed or disposed on the sidewalls and bottom wall of the via 183. The interconnect layer 201 contacts the exposed portion of the second conductive layer 14. The first conductive layer 19 is physically connected to and electrically connected to the interconnect layer 201. Therefore, the first conductive layer 19 is electrically connected to the circuit structure 12 via the interconnect layer 201.

[0033] Simultaneously, interconnect layer 201 forms a via structure 20 in via 183. The via structure 20 extends through insulating structure 18 (including first insulating layer 15, second insulating layer 16, and third insulating layer 17). The via structure 20 includes interconnect layer 201 formed or disposed on the sidewalls and bottom wall of via 183. The via structure 20 contacts second conductive layer 14 and electrically connects first conductive layer 19 and circuit structure 12.

[0034] In some embodiments, the first conductive layer 19 includes a metal layer, such as an aluminum layer or a copper layer. The material of the first conductive layer 19 may be the same as or different from the material of the second conductive layer 14. In some embodiments, the interconnect layer 201 includes a metal layer, such as an aluminum layer or a copper layer. The material of the interconnect layer 201 may be the same as or different from the material of the first conductive layer 19.

[0035] Interconnect layer 201 and first conductive layer 19 are formed simultaneously and integrally. Interconnect layer 201 is also referred to as an extension of first conductive layer 19. Furthermore, first conductive layer 19 includes a main portion 190 disposed on a first surface 181 (e.g., top surface) of insulating structure 18. Main portion 190 includes a first segment 193 and a second segment 194, defining a gap 195 between the first segment 193 and the second segment 194. Therefore, main portion 190 is patterned. First segment 193 is separated from second segment 194 by gap 195. A portion of third insulating layer 17 of insulating structure 18 is exposed in gap 195.

[0036] The main portion 190 of the first conductive layer 19 has a thickness T7. The interconnect layer 201 has a thickness T4. The thickness T7 of the main portion 190 of the first conductive layer 19 is greater than the thickness T4 of the interconnect layer 201. The thickness T7 of the main portion 190 of the first conductive layer 19 is from 2.6 μm to 3.0 μm. For example, the thickness T7 is approximately 2.8 μm. The thickness T4 of the interconnect layer 201 is from 0.4 μm to 1.5 μm. For example, the thickness T4 is approximately 0.5 μm or approximately 1.0 μm.

[0037] Referring to FIG5, in step S904, a first outer layer 21 is formed or disposed on the first conductive layer 19 by, for example, deposition. The first outer layer 21 is a passivation layer or an electrically insulating layer and includes an oxide material or a nitride material, such as SiO₂, SiN, Si₃N₄ and / or SiCN. In some embodiments, the first outer layer 21 includes an oxide material, such as tetraethyl orthosilicate (Si(OC₂H₅)₄, TEOS). The first outer layer 21 includes a main portion 210 and a first extension portion 214 extending from the main portion 210. The main portion 210 of the first outer layer 21 is disposed on the main portion 190 of the first conductive layer 19. A portion of the first outer layer 21 is disposed in a gap 195 of the first conductive layer 19 to contact an exposed portion of the third insulating layer 17 of the insulating structure 18. The first extension portion 214 of the first outer layer 21 is disposed on the interconnect layer 201 and extends into a via 183.

[0038] The main portion 210 of the first outer layer 21 has a thickness T8. The first extension portion 214 of the first outer layer 21 has a thickness T5. The thickness T8 of the main portion 210 of the first outer layer 21 is greater than the thickness T5 of the first extension portion 214 of the first outer layer 21. The thickness T8 of the main portion 210 of the first outer layer 21 is from 1.5 μm to 3.0 μm. For example, the thickness T8 is approximately 2.0 μm. The thickness T5 of the first extension portion 214 of the first outer layer 21 is from 0.5 μm to 1.5 μm. For example, the thickness T5 is approximately 1.0 μm. The first extension portion 214 of the first outer layer 21 does not fill the via 183.

[0039] Referring to Figure 6, the main portion 210 of the first outer layer 21 is thinned, for example, by etching. The thickness T8 of the main portion 210 of the first outer layer 21 in Figure 5 is reduced to a thickness T81. The thickness T81 of the main portion 210 of the first outer layer 21 is 0.5 μm to 1.5 μm. For example, the thickness T81 is approximately 1.0 μm.

[0040] Referring to Figure 7, in step S905, the second outer layer 22 is formed or disposed on the first outer layer 21 by, for example, deposition. The second outer layer 22 is also referred to as the "outermost layer". The second outer layer 22 is a passivation layer or an electrically insulating layer and includes an oxide material or a nitride material, such as SiO₂, SiN, Si₃N₄ and / or SiCN. In some embodiments, the second outer layer 22 includes an oxide material, such as tetraethyl orthosilicate. The material of the second outer layer 22 may be the same as or different from the material of the first outer layer 21.

[0041] The second outer layer 22 includes a main portion 220 and a second extension portion 224 extending from the main portion 220. The main portion 220 of the second outer layer 22 is disposed on the main portion 210 of the first outer layer 21. A portion of the second outer layer 22 is disposed in a gap 195 of the first conductive layer 19 to define a recessed portion 225 recessed from a first surface 221 (e.g., a top surface) of the main portion 220 of the second outer layer 22. The first surface 221 (e.g., a top surface) of the main portion 220 of the second outer layer 22 is located away from the first outer layer 21 and is also referred to as the "outermost surface 221" of the second outer layer 22. The second extension portion 224 of the second outer layer 22 is disposed on the first extension portion 214 of the first outer layer 21 and extends into a via 183.

[0042] The main portion 220 of the second outer layer 22 has a thickness T9. The second extension portion 224 of the second outer layer 22 has a thickness T6. The thickness T9 of the main portion 220 of the second outer layer 22 is greater than the thickness T6 of the second extension portion 224 of the second outer layer 22. The thickness T9 of the main portion 220 of the second outer layer 22 is 5.0 μm to 7.0 μm. For example, the thickness T9 is approximately 6.0 μm. The thickness T6 of the second extension portion 224 of the second outer layer 22 is 0.5 μm to 1.5 μm or 0.9 μm to 1.1 μm. For example, the thickness T6 is approximately 1.0 μm.

[0043] The second extension 224 of the second outer layer 22 does not fill the through-hole 183. The main portion 220 of the second outer layer 22 and the second extension 224 of the second outer layer 22 together define a closed void 23. Therefore, the second outer layer 22 defines the closed void 23. The closed void 23 is an air-filled closed space. The closed void 23 horizontally overlaps the first outer layer 21. The closed void 23 horizontally overlaps the first conductive layer 19. The closed void 23 horizontally overlaps the insulating structure 18. The closed void 23 horizontally overlaps the through-hole structure 20. The top of the closed void 23 extends beyond the top surface of the first outer layer 21.

[0044] Referring to Figure 8, the main portion 220 of the second outer layer 22 is thinned by, for example, performing a chemical-mechanical polishing (CMP) process on the first surface 221 (i.e., the outermost surface) of the main portion 220 of the second outer layer 22. Therefore, the first surface 221 (i.e., the outermost surface) of the main portion 220 of the second outer layer 22 is planarized. The thickness T9 of the main portion 220 of the second outer layer 22 in Figure 7 is reduced to a thickness T91. The thickness T91 of the main portion 220 of the second outer layer 22 can be from 2.0 μm to 4.0 μm. For example, the thickness T91 can be 3.0 μm. Furthermore, the depth of the recessed portion 225 can be reduced.

[0045] In this disclosure, the second outer layer 22 comprises an oxide material, such as tetraethoxysilane, to improve the coplanarity and smoothness of the first surface 221 (i.e., the outermost surface) of the main portion 220 of the second outer layer 22 after thinning and planarization processes. For example, the first surface 221 (i.e., the outermost surface) of the main portion 220 of the second outer layer 22 has better coplanarity and smoothness compared to the second outer layer 22 comprising a cured photoresist material (such as polyimide).

[0046] Referring to FIG9, at least one opening 223 is formed extending through the second outer layer 22 and the first outer layer 21 to expose a portion of the first conductive layer 19. Therefore, the second outer layer 22 and the first outer layer 21 together define the opening 223.

[0047] Referring to FIG10, in step S906, at least one bump 24 is formed or disposed in the opening 223. The bump 24 is formed or disposed on the second outer layer 22 and electrically connected to the first conductive layer 19. In some embodiments, the bump 24 includes a main portion 241 and an extension portion 242. The main portion 241 is disposed in the opening 223, extends through the first outer layer 21 and the second outer layer 22, and contacts the first conductive layer 19. The extension portion 242 is disposed on the first surface 221 (i.e., the outermost surface) of the main portion 220 of the second outer layer 22. Therefore, the bump 24 extends through the second outer layer 22 and extends beyond the first surface 221 (i.e., the outermost surface) of the main portion 220 of the second outer layer 22.

[0048] In some embodiments, the seed layer 25 is located below the bump 24. Therefore, the seed layer 25 is disposed between the bump 24 and the second outer layer 22. Alternatively, the seed layer 25 may be a portion of the bump 24.

[0049] In this disclosure, the first surface 221 (i.e., the outermost surface) of the main portion 220 of the second outer layer 22 has good coplanarity and flatness. That is, the first surface 221 (i.e., the outermost surface) of the main portion 220 of the second outer layer 22 may not have an irregular shape (e.g., a wavy profile). The first surface 221 (i.e., the outermost surface) of the main portion 220 of the second outer layer 22 is a flat surface, not a wavy surface. Therefore, the plurality of bumps 24 have a uniform shape, and the bumps 24 are not tilted. The bumps 24 are arranged at the same height.

[0050] Simultaneously, electronic device 1 is formed or obtained. In some embodiments, a dicing process is performed to form a plurality of electronic devices 1. Electronic device 1 is also referred to as a "first electronic device," "top electronic device," "first semiconductor die," "top semiconductor die," "first semiconductor wafer," or "top semiconductor wafer." Electronic device 1 is a logic die, such as an application processor (AP) die or an application-specific integrated circuit (ASIC) die. Alternatively, electronic device 1 is a memory die or a memory wafer.

[0051] Referring to Figures 11 and 12, where Figure 12 illustrates an enlarged view of region "A" in Figure 11, a second electronic device 3 is provided. The second electronic device 3 is also referred to as a "bottom electronic device," a "second semiconductor die," a "bottom semiconductor chip," or a "bottom semiconductor wafer." The second electronic device 3 is a logic die, such as an application processor die or an application-specific integrated circuit (die). Alternatively, the second electronic device 3 is a memory die or a memory chip.

[0052] The second electronic device 3 includes a base portion 30 (e.g., a second base portion), a first intermediate layer 31, a plurality of first interconnect vias 313, a circuit structure 32 (e.g., a second circuit structure), a second intermediate layer 33, a plurality of second interconnect vias 333, a second conductive layer 34, an insulating structure 38 (e.g., a second insulating structure), a first conductive layer 39, a first outer layer 41, a second outer layer 42, vias 48, a third outer layer 43, pads 45, and connecting elements 44.

[0053] The base portion 30 has a first surface 301 and a second surface 302 opposite to the first surface 301. The first surface 301 is an active surface. The second surface 302 may be a back surface.

[0054] In some embodiments, the base portion 30 is a substrate and includes a dielectric material, such as an oxide material or a nitride material. Alternatively, the base portion 30 is a substrate and includes, for example, silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials.

[0055] In some embodiments, the base portion 30 includes a semiconductor device of circuitry, such as a memory cell. In some embodiments, the memory cell includes a dynamic random access memory (DRAM) cell.

[0056] Furthermore, the base portion 30 is or includes an integrated circuit (IC) chip, comprising various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally-diffused metal-oxide-semiconductor (LDMOS) transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable IC components, or combinations thereof.

[0057] A first intermediate layer 31 is disposed between the first surface 301 of the base portion 30 and the circuit structure 32. The first intermediate layer 31 is also referred to as a "lower intermediate layer" or "upper intermediate layer." The first intermediate layer 31 serves to electrically insulate the circuit structure 32 from the first surface 301 of the base portion 30. Therefore, the circuit structure 32 is electrically insulated from the first surface 301 of the base portion 30 by the first intermediate layer 31. In some embodiments, the first intermediate layer 31 comprises a dielectric material or an electrically insulating material, such as an oxide material or a nitride material.

[0058] A first interconnect via 313 is disposed in the first intermediate layer 31. The first interconnect via 313 extends through the first intermediate layer 31 and serves to electrically connect the circuit structure 32 and the first surface 301 of the base portion 30. Therefore, the circuit structure 32 is electrically connected to the first surface 301 of the base portion 30 via the first interconnect via 313. In some embodiments, the first interconnect via 313 comprises a conductive material, such as a metallic material. For example, the first interconnect via 313 comprises copper.

[0059] The circuit structure 32 is disposed on the first intermediate layer 31 and the first surface 301 of the base portion 30. In some embodiments, the first intermediate layer 31 is disposed on and in contact with the first surface 301 of the base portion 30. The circuit structure 32 is disposed on and in contact with the first intermediate layer 31. Alternatively, at least one layer (e.g., an insulating layer or a conductive layer) is present between the circuit structure 32 and the first surface 301 of the base portion 30.

[0060] The circuit structure 32 is a redistribution layer structure and includes a plurality of dielectric layers 324, a plurality of redistribution layers 325, and a plurality of inner layer vias 326. The dielectric layers 324 are interlayer dielectric layers and include silicon oxide (SiO₂), silicon nitride (SiN), and / or silicon carbonitride (SiCN). The redistribution layers 325 and the inner layer vias 326 are embedded in the dielectric layers 324. The redistribution layers 325 include a plurality of conductors and a plurality of pads. The redistribution layers 325 are electrically connected to each other vias 326. The circuit structure 32 is also referred to as a "conductive structure". In some embodiments, the redistribution layers 325 are electrically connected to a first interconnect via 313.

[0061] The second intermediate layer 33 is disposed between the second conductive layer 34 and the circuit structure 32. The second intermediate layer 33 is also referred to as the "lower intermediate layer" or the "upper intermediate layer". The second intermediate layer 33 is used to electrically insulate the circuit structure 32 from the second conductive layer 34. Therefore, the circuit structure 32 is electrically insulated from the second conductive layer 34 by the second intermediate layer 33. In some embodiments, the second intermediate layer 33 includes a dielectric material or an electrically insulating material, such as an oxide material or a nitride material.

[0062] A second interconnect via 333 is disposed in the second intermediate layer 33. The second interconnect via 333 extends through the second intermediate layer 33 and is used to electrically connect the circuit structure 32 and the second conductive layer 34. Therefore, the circuit structure 32 is electrically connected to the second conductive layer 34 via the second interconnect via 333. In some embodiments, the second interconnect via 333 includes a conductive material, such as a metallic material. For example, the second interconnect via 333 includes copper.

[0063] A second conductive layer 34 is disposed between the circuit structure 32 and the insulating structure 38. In some embodiments, a second intermediate layer 33 covers and contacts the circuit structure 32. The second conductive layer 34 is inserted between the second intermediate layer 33 and the insulating structure 38. In some embodiments, the second conductive layer 34 includes a metal layer, such as an aluminum layer or a copper layer, and covers and contacts the second intermediate layer 33. The second conductive layer 34 is electrically connected to the circuit structure 32 via a second interconnect via 333.

[0064] An insulating structure 38 is disposed on the circuit structure 32. In some embodiments, the insulating structure 38 covers and contacts the second conductive layer 34. The insulating structure 38 includes a first insulating layer 35, a second insulating layer 36, and a third insulating layer 37. Thus, the first insulating layer 35, the second insulating layer 36, and the third insulating layer 37 collectively define the insulating structure 38. The insulating structure 38 has a first surface 381 (e.g., a top surface) facing away from the circuit structure 32 and the base portion 30.

[0065] A first insulating layer 35 is disposed on the circuit structure 12. The first insulating layer 35 covers and contacts the second conductive layer 34. The first insulating layer 35 is a passivation layer or an electrical insulating layer, and includes oxide or nitride materials, such as silicon oxide (SiO₂), silicon nitride (SiN), silicon nitride (Si₃N₄), and / or silicon carbonitride (SiCN). The first insulating layer 35 is a buffer layer. The first insulating layer 35 has a first thickness.

[0066] A second insulating layer 36 is disposed on or above the first insulating layer 35. The second insulating layer 36 is inserted between the first insulating layer 35 and the third insulating layer 37. The second insulating layer 36 covers and contacts the first insulating layer 35. The second insulating layer 36 is a passivation layer or an electrical insulating layer, and includes oxide or nitride materials, such as silicon oxide, silicon nitride, silicon nitride, and / or silicon carbonitride. The second insulating layer 36 is a protective layer and prevents external moisture from entering the circuit structure 32 and the first surface 301 of the base portion 30. The material of the second insulating layer 36 is different from the material of the first insulating layer 35. The second insulating layer 36 has a second thickness.

[0067] A third insulating layer 37 is disposed on the second insulating layer 36. The third insulating layer 37 covers and contacts the second insulating layer 36. A first surface (e.g., top surface) of the third insulating layer 37 is a first surface 381 (e.g., top surface) of the insulating structure 38. The third insulating layer 37 is a passivation layer or an electrical insulating layer and includes an oxide material or a nitride material, such as silicon oxide, silicon nitride, silicon nitride, and / or silicon carbonitride. The third insulating layer 37 has a third thickness. The material of the third insulating layer 37 is the same as the material of the first insulating layer 35. The material of the third insulating layer 37 is different from the material of the second insulating layer 36. For example, the third insulating layer 37 includes an oxide material, the first insulating layer 35 includes an oxide material, and the second insulating layer 36 includes a nitride material.

[0068] The third thickness of the third insulating layer 37 is greater than the second thickness of the second insulating layer 36 and the first thickness of the first insulating layer 35. The second thickness of the second insulating layer 36 is greater than the first thickness of the first insulating layer 35.

[0069] An insulating structure 38 defines a through-hole 383 that penetrates the insulating structure 38 and exposes a portion of the second conductive layer 34. A first conductive layer 39 is formed or disposed on a first surface 381 of the insulating structure 38. The first conductive layer 39 has a first surface 391 that is remote from the first surface 381 of the insulating structure 38. An interconnect layer 401 is formed or disposed on the sidewalls and bottom wall of the through-hole 383. The interconnect layer 401 contacts the exposed portion of the second conductive layer 34. The first conductive layer 39 is physically connected to and electrically connected to the interconnect layer 401. Therefore, the first conductive layer 39 is electrically connected to the circuit structure 32 via the interconnect layer 401.

[0070] Simultaneously, interconnect layer 401 forms a via structure 40 in via 383. The via structure 40 extends through insulating structure 38 (including first insulating layer 35, second insulating layer 36, and third insulating layer 37). The via structure 40 includes interconnect layer 401 formed or disposed on the sidewalls and bottom wall of via 383. The via structure 40 contacts second conductive layer 34 and electrically connects first conductive layer 39 and circuit structure 32.

[0071] In some embodiments, the first conductive layer 39 includes a metal layer, such as an aluminum layer or a copper layer. The material of the first conductive layer 39 may be the same as or different from the material of the second conductive layer 34. In some embodiments, the interconnect layer 401 includes a metal layer, such as an aluminum layer or a copper layer. The material of the interconnect layer 401 may be the same as or different from the material of the first conductive layer 39.

[0072] Interconnect layer 401 and first conductive layer 39 are formed simultaneously and integrally. Interconnect layer 401 is also referred to as an extension of first conductive layer 39. Furthermore, first conductive layer 39 includes a main portion 390 disposed on a first surface 381 of insulating structure 38. Main portion 390 of first conductive layer 39 has a thickness. Interconnect layer 401 has a thickness. The thickness of main portion 390 of first conductive layer 39 is greater than the thickness of interconnect layer 401.

[0073] A first outer layer 41 is formed or disposed on a first conductive layer 39. The first outer layer 41 includes a metal layer, such as a copper layer. The first outer layer 41 includes a main portion 410 and a first extension portion 414 extending from the main portion 410. The main portion 410 of the first outer layer 41 is disposed on a main portion 390 of the first conductive layer 39. The first extension portion 414 of the first outer layer 41 is disposed on an interconnect layer 401 and can extend into a via 383.

[0074] The main portion 410 of the first outer layer 41 has a thickness. The first extension portion 414 of the first outer layer 41 has a thickness. The thickness of the main portion 410 of the first outer layer 41 is substantially equal to the thickness of the first extension portion 414 of the first outer layer 41.

[0075] The second outer layer 42 is formed, for example, by deposition or disposed on the first outer layer 41 or the first conductive layer 39. The second outer layer 42 is also referred to as the "outer layer" or "outermost layer". The second outer layer 42 includes a cured photoresist material (e.g., polyimide). The material of the second outer layer 42 of the second electronic device 3 is different from the material of the second outer layer 22 (e.g., the outermost layer) of the electronic device 1.

[0076] The second outer layer 42 has a first surface 421 that is away from the first outer layer 41, also referred to as the "outermost surface 421" of the second outer layer 42. The first surface 421 (e.g., the outermost surface 421) of the second outer layer 42 is a wavy surface. A portion of the second outer layer 42 is disposed on the first extension portion 414 of the first outer layer 41 and fills the through-hole 383.

[0077] The second outer layer 42 and the first outer layer 41 together define an opening 425 to expose a portion of the first surface 391 of the first conductive layer 39. A connecting element 44 is disposed near the first surface 301 of the base portion 30 of the second electronic device 3. The connecting element 44 (e.g., a pillar, bump, or pad) is formed or disposed on the exposed portion of the first surface 391 of the first conductive layer 39 in the opening 425. The opening 425 of the second outer layer 42 is used to receive the connecting element 44.

[0078] The connecting element 44 comprises a metallic material, such as copper or aluminum. The connecting element 44 contacts and is electrically connected to the first conductive layer 39. In some embodiments, a metal layer 47 is disposed on the connecting element 44. The metal layer 47 is a barrier layer, such as a nickel (Ni) layer, a palladium (Pd) layer, and / or a gold (Au) layer.

[0079] The third outer layer 43 is disposed on or formed on the second surface 302 of the base portion 30. The third outer layer 43 is a passivation layer or an electrically insulating layer and includes oxide or nitride materials, such as SiO₂, SiN, Si₃N₄ and / or SiCN.

[0080] A through-hole 48 is disposed in the base portion 30. The through-hole 48 comprises a metallic material, such as copper. The through-hole 48 extends through the third outer layer 43, the base portion 30, and the first intermediate layer 31. The bottom end of the through-hole 48 contacts the circuit structure 32. The top end of the through-hole 48 is exposed in the third outer layer 43.

[0081] A solder pad 45 is disposed near the second surface 302 of the base portion 30 of the second electronic device 3. The solder pad 45 is formed or disposed on the outer layer 43 and covers and contacts the top end of the via 48. The solder pad 45 is electrically connected to the via 48. Therefore, the connecting element 44 is electrically connected to the solder pad 45 via the via 48. The material of the solder pad 45 includes copper, aluminum, or tin. In some embodiments, a metal layer 46 is disposed on the solder pad 45. The metal layer 46 is a barrier layer, such as a nickel layer, a palladium (Pd) layer, a copper layer, and / or a gold layer.

[0082] Referring to FIG13, electronic device 1 (e.g., first electronic device 1) and second electronic device 3 are bonded and electrically connected. For example, the solder pads 45 of the second electronic device 3 are electrically connected to the bumps 24 of the first electronic device 1 by means of a first solder material 52. The first solder material 52 includes a reflowable material, such as AgSn.

[0083] In this disclosure, the first surface 221 (i.e., the outermost surface) of the main portion 220 of the second outer layer 22 has good coplanarity and flatness. Therefore, the bump 24 will not tilt on the first surface 221 (i.e., the outermost surface) of the main portion 220 of the second outer layer 22. Thus, the bonding or adhesion formed by the bump 24 of the first electronic device 1 and the solder pad 45 of the second electronic device 3 is ensured. Yield is improved.

[0084] In some embodiments, if the electronic device 1 in FIG. 13 (e.g., the first electronic device 1) is a cut device, the second electronic device 3 can be cut. If the electronic device 1 in FIG. 13 (e.g., the first electronic device 1) has not yet been cut, the electronic device 1 (e.g., the first electronic device 1) and the second electronic device 3 can be cut simultaneously. Therefore, the electronic device 1 (e.g., the first electronic device 1) and the second electronic device 3 can be cut at the same time.

[0085] Referring to Figures 14 and 15, where Figure 15 illustrates an enlarged view of region "B" in Figure 14, the second electronic device 3 is bonded and electrically connected to the substrate 50 to form or obtain an assembly structure 5. For example, the substrate 50 is electrically connected to the connecting elements 44 of the second electronic device 3 by means of a second solder material 54. The second solder material 54 includes a reflowable material, such as AgSn. The substrate 50 includes a printed circuit board (PCB), a core substrate, or a coreless substrate.

[0086] One embodiment of this disclosure provides an electronic device. The electronic device includes a base portion, a circuit structure, an insulating structure, a first conductive layer, a through-hole structure, a first outer layer, and a second outer layer. The base portion has a first surface. The circuit structure is disposed on the first surface of the base portion. The insulating structure is disposed on the circuit structure. The first conductive layer is disposed on the insulating structure. The through-hole structure extends through the insulating structure and electrically connects the first conductive layer and the circuit structure. The first outer layer is disposed on the first conductive layer. The second outer layer is disposed on the first outer layer. The second outer layer includes an oxide material to improve the coplanarity of the outermost surface of the second outer layer.

[0087] Another embodiment of this disclosure provides an assembly structure. The assembly structure includes a first electronic device, a second electronic device, and a substrate. The first electronic device includes a base portion, an outermost layer, and bumps. The base portion has a first surface. The outermost layer is disposed near the first surface of the base portion. The outermost layer includes an oxide material to improve the coplanarity of the outermost surface of the outermost layer. The bumps extend through the outermost layer and beyond the outermost surface of the outermost layer. The second electronic device includes a base portion, through-holes, solder pads, and connecting elements. The base portion has a first surface and a second surface opposite to the first surface. The through-holes extend through the base portion. The solder pads are disposed near the second surface of the base portion of the second electronic device and electrically connect the through-holes and the bumps of the first electronic device. The connecting elements are disposed near the first surface of the base portion of the second electronic device and electrically connected to the solder pads via the through-holes. The substrate is electrically connected to the connecting elements.

[0088] Another embodiment of this disclosure provides a method for manufacturing an electronic device. The method includes: providing a body including a base portion having a first surface, a circuit structure disposed on the first surface of the base portion, and an insulating structure disposed on the circuit structure; forming a through-hole extending through the insulating structure; forming a first conductive layer on the insulating structure and forming an interconnect layer on the sidewall of the through-hole, wherein the first conductive layer connects to the interconnect layer, and wherein the first conductive layer is electrically connected to the circuit structure via the interconnect layer; forming a first outer layer on the first conductive layer; and forming a second outer layer on the first outer layer, wherein the second outer layer comprises an oxide material.

[0089] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0090] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0091] 1: Electronic devices 3: Second electronic device 5: Assembly Structure 6: Main Body 10: Base section 11: First Intermediate Layer 12: Circuit Structure 13: Second intermediate layer 14: Second conductive layer 15: First insulating layer 16: Second insulating layer 17: Third Insulation Layer 18: Insulation Structure 19: First conductive layer 20: Through-hole structure 21: First outer layer 22: Second outer layer 23: Enclosed gap 24: Bumps 25: Seed layer 30: Base section 31: First Intermediate Layer 32: Circuit Structure 33: Second intermediate layer 34: Second conductive layer 35: First insulating layer 36: Second insulating layer 37: Third Insulation Layer 38: Insulation structure 39: First conductive layer 40: Through-hole structure 41: First outer layer 42: Second outer layer 43: Outer layer 44: Connecting elements 45: Solder pad 46: Metal layer 47: Metal layer 48: Through-hole 50:Substrate 52: First welding material 54: Second solder material 101: First Surface 102: Second Surface 113: First interconnecting via 124: Dielectric layer 125: Rewire Layers (RDLs) 126: Inner layer through hole 133: Second interconnecting via 181: First Surface 183: Through hole 190: Main Part 191: First Surface 193: First paragraph 194: Second paragraph 195: Gap 201: Interconnection Layer 210: Main Part 214: First Extension 220: Main Part 221: First Surface 223: Opening 224: Second Extension 225: Depressed portion 241: Main Part 242: Extension 301: First Surface 302: Second Surface 313: First interconnecting via 324: Dielectric layer 325: Rewire Layers (RDLs) 326: Inner layer through hole 333: Second interconnecting via 381: First Surface 383: Through hole 390: Main Part 391: First Surface 401: Interconnection Layer 410: Main Part 414: First Extension 421: First Surface 425: Opening 900: Method A: Area B: Area T1: First thickness T2: Second thickness T3: Third Thickness T4: Thickness T5: Thickness T6: Thickness T7: Thickness T8: Thickness T81: Thickness T9: Thickness T91: Thickness S901: Steps S902: Steps S903: Steps S904: Steps S905: Steps S906: Steps

Claims

1. An electronic device comprising: A base portion having a first surface; A circuit structure is disposed on the first surface of the base portion; An insulating structure is disposed on the circuit structure; a first conductive layer is disposed on the insulating structure; a through-hole structure extends through the insulating structure and electrically connects the first conductive layer and the circuit structure; a first outer layer is disposed on the first conductive layer; and a second outer layer disposed on the first outer layer, wherein the second outer layer comprises an oxide material to improve the coplanarity of an outermost surface of the second outer layer, wherein the second outer layer defines a closed void.

2. The electronic device as claimed in claim 1, wherein the base portion comprises silicon (Si).

3. The electronic device as claimed in claim 1, wherein the first surface of the base portion is an active surface.

4. The electronic device as claimed in claim 1, wherein the circuit structure is a redistribution layer structure and includes a plurality of dielectric layers and a plurality of redistribution layers embedded in the plurality of dielectric layers.

5. The electronic device as claimed in claim 1, further comprising: A first intermediate layer is disposed between the first surface of the base portion and the circuit structure, and is used to electrically insulate the circuit structure from the first surface of the base portion; And a plurality of first interconnect vias, disposed in the first intermediate layer, for electrically connecting the circuit structure and the first surface of the base portion.

6. The electronic device as claimed in claim 1, further comprising: A second conductive layer is disposed between the circuit structure and the insulating structure, wherein the through-hole structure contacts the second conductive layer.

7. The electronic device as claimed in claim 6, further comprising: A second intermediate layer is disposed between the circuit structure and the second conductive layer, and is used to electrically insulate the circuit structure from the second conductive layer; And a plurality of second interconnecting vias are disposed in the second intermediate layer and used to electrically connect the circuit structure and the second conductive layer.

8. The electronic device as claimed in claim 1, wherein the insulating structure comprises: A first insulating layer is disposed on the circuit structure; A second insulating layer is disposed on the first insulating layer; And a third insulating layer disposed on the second insulating layer, wherein the through-hole structure extends through the first insulating layer, the second insulating layer and the third insulating layer.

9. The electronic device of claim 8, wherein the thickness of the third insulating layer is greater than the thickness of the second insulating layer and the thickness of the first insulating layer.

10. The electronic device of claim 8, wherein a material of the third insulating layer is the same as a material of the first insulating layer, and the material of the third insulating layer is different from a material of the second insulating layer.

11. The electronic device of claim 1, wherein the insulating structure defines a through-hole extending through the insulating structure, and the through-hole structure includes an interconnect layer disposed on the sidewall of the through-hole.

12. The electronic device as claimed in claim 11, wherein the interconnect layer and the first conductive layer are formed simultaneously and integrally.

13. The electronic device of claim 11, wherein the first outer layer includes a first extension disposed on the interconnect layer and extending into the via.

14. The electronic device of claim 13, wherein the second outer layer includes a second extension disposed on the first extension of the first outer layer and extending into the through-hole.

15. The electronic device as claimed in claim 1, wherein the enclosed gap horizontally overlaps the first outer layer.

16. The electronic device as claimed in claim 1, wherein the enclosed gap horizontally overlaps the first conductive layer.

17. The electronic device as claimed in claim 1, wherein the closed gap horizontally overlaps the insulating structure.

18. The electronic device as claimed in claim 1, wherein the closed gap horizontally overlaps the through-hole structure.

19. The electronic device as claimed in claim 1, further comprising: A bump disposed on the second outer layer and electrically connected to the first conductive layer; a main portion extending through the first outer layer and the second outer layer and contacting the first conductive layer; and an extension portion disposed on a first surface of the second outer layer.

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