Upper edge ring of a process kit for semiconductor substrate processing

Description

[0001] FIG. 1 is a top plan view of an upper edge ring of a process kit for semiconductor substrate processing, showing our new design.

[0002] FIG. 2 is a bottom plan view thereof.

[0003] FIG. 3 is a front elevation view thereof. The front, the back, left, and right side elevation views are identical to the elevation view shown in FIG. 3.

[0004] FIG. 4 is a top isometric view thereof.

[0005] FIG. 5 is a bottom isometric view thereof; and,

[0006] FIG. 6 is an enlarged cross-sectional view taken along line 6-6 and encircled portions labeled, “FIG. 6,” in FIG. 1.

[0007] The hatch lines in the cross-section of FIG. 6 represent unclaimed internal environment and form no part of the claimed design. The dashed break lines in FIG. 6 represent unclaimed environment and form no part of the claimed design.

[0008] In FIG. 6 the design is shown with a symbolic break shown in broken lines in its length to provide an enlarged view of cross-sectional detail of the claimed design.

Claims

The ornamental design for an upper edge ring of a process kit for semiconductor substrate processing, as shown and described.

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