Pixel drive circuit for implementing variable resolution by area, pixel circuit using capacitor network, method for manufacturing pixel circuit, computer-readable recording medium, micro display device, and display system comprising same

Abstract

Disclosed are a pixel drive circuit for implementing variable resolution by area, a pixel circuit using a capacitor network, a method for manufacturing the pixel circuit, a computer-readable recording medium, a micro display device, and a display system comprising same. The pixel drive circuit is characterized by comprising: a plurality of column lines; a plurality of row lines wired in a direction orthogonal to the plurality of column lines; a plurality of cells produced by the intersection of the plurality of column lines and the plurality of row lines; combination circuits respectively positioned in the plurality of cells and respectively connected to the plurality of column lines and the plurality of row lines; and pixels that are connected to the combination circuit and output pixel data in response to external control signals or output data values calculated from the outputs of nearby pixels, wherein images having the same resolution as the original resolution and a variable resolution are output by the combination circuit, whereby image quality is restored in a required area.

Description

A pixel driving circuit for implementing variable resolution by area, a pixel circuit using a capacitor network, a method for manufacturing the pixel circuit, a computer-readable recording medium, a microdisplay device, and a display system having the same

[0001] The present invention relates to a pixel driving circuit, a pixel circuit, a method for manufacturing a pixel circuit, a micro display device, and a display system including the same.

[0002] In general, a display device is a device that displays an image on a display panel using electrical and optical characteristics, and includes a liquid crystal display (LCD) and an organic light emitting diode (OLED) display. These display devices have a structure in which a number of pixels are arranged in a two-dimensional matrix of rows and columns.

[0003] Figure 1 is a drawing for explaining a pixel driving method of a conventional display device.

[0004] Referring to Fig. 1, in order to implement a resolution of CХR, a display device generally stores desired data in a pixel circuit by crossing a column line and a row line, and drives pixels through the pixel circuit.

[0005] In order to implement the resolution of CХR, it must be composed of C column drive lines and drive circuits, R row drive lines and drive circuits, and CХR pixel circuits.

[0006] At this time, in order to increase the resolution, the values ​​corresponding to C and R must be increased by the desired resolution. In other words, the complexity of the pixel drive line and drive circuit increases, and if the size of the driven pixel is constant, there was a problem in that the size of the display device increases by the amount of the increase in resolution.

[0007] Fig. 2 is a block diagram of a conventional pixel driving circuit, showing the configuration of pixels used in a general current-driven display device.

[0008] A conventional pixel driving circuit uses a voltage-driven pixel (10), and the voltage-driven pixel (10) stores pixel data (DATA) in the form of voltage using one or more switches (11) and pixel memory (12).

[0009] Stored voltage data (V STG ) is converted into current data through a voltage-to-current converter (VI Converter) (20) and transmitted to a current-driven display pixel (30) to output light proportional to the current.

[0010] Figure 3 is a circuit diagram showing various embodiments of a conventional pixel circuit as an example.

[0011] In the conventional technology, there is a method of storing data voltage in a capacitor as shown in (a) of FIG. 3, and a method of using a digital latch such as SRAM as shown in (b) of FIG. 3.

[0012] Regardless of the storage method used, current-driven pixels have the constraint of inevitably requiring the use of a voltage-to-current converter (VI converter).

[0013] Figure 4 is a flowchart of input and output data processing of a typical display device.

[0014] A general display device refers to a device that receives video data input and outputs it as a two-dimensional flat image, and does not include a device that performs calculations to create video data or controls it.

[0015] A typical display device is a device that receives an image with a predetermined resolution (C x R) from the outside through a video input unit (46), transmits it to a driving unit in a C x R matrix manner, stores it in the memory of a pixel driving circuit, and drives pixels with the stored memory output.

[0016] That is, in conventional display devices, the video input resolution and video output resolution are the same.

[0017] Therefore, a resolution conversion unit can be added between the video input unit (46) and the pixel array driver unit (47) to have an output video resolution different from the input video resolution, but this is the same as placing the resolution conversion unit before the input terminal of the video input unit (10), since the output after the resolution conversion unit can be defined as an actual display device.

[0018] For example, the C x R resolution pixel array driver (47) is composed of a column driver circuit that transmits data in a matrix manner and a row driver circuit that activates each column.

[0019] The C x R resolution pixel array driver (47) is a circuit that stores data for driving pixels of each row and column by the pixel array driver circuit, drives them with voltage, or converts the stored voltage into current and connects it to the pixels, thereby controlling the brightness of the pixels according to the value of the input data.

[0020] A C x R array display pixel is a device that has properties such as brightness or optical delay phase of each pixel controlled to create a C x R image into a two-dimensional flat image.

[0021] In this way, in conventional technology, there is a problem in that it is difficult to improve the integration level because pixel circuits consisting of switches, memories, and VI converters must exist as much as the resolution.

[0022] In addition, conventional technologies have the problem of requiring a small pixel driving circuit to achieve the target resolution and consuming very large amounts of power.

[0023] Figure 5 is a block diagram of a conventional display system that variably changes the resolution of a display device.

[0024] Recently, for special purposes such as tracking the gaze of users using virtual reality glasses, augmented reality glasses, etc., the image generation technique of foveated rendering, which creates and transmits images by varying the resolution of the display by area, has become widely known.

[0025] In particular, for games and graphic playback, a large amount of calculation is required to generate high-resolution images, and the increased performance and power consumption of various processors such as CPUs, GPUs, and APs for this purpose are becoming a problem.

[0026] To alleviate this, if images are generated by varying the resolution by region, the overall amount of calculation and memory can be reduced.

[0027] However, in the conventional technology, the output of the variable resolution image generator (50) for each region is transmitted to the display device (70) through the video transmission unit (60).

[0028] That is, the output of the image generator (50) has the same resolution as the output resolution of the display device (70), and has the limitation that a transmission line and transmission device with a wide bandwidth must be used to transmit it.

[0029] Additionally, conventional display devices had limitations in that they had to use high-performance displays capable of processing high-resolution input.

[0030]

[0031] An object of the present invention is to provide a pixel driving circuit capable of implementing variable resolution for each area by using a direct drive mode in an area that has a significant impact on image quality and using an interpolation mode in an area that has a relatively less impact.

[0032] In addition, an object of the present invention is to provide a pixel circuit capable of simultaneously implementing a pixel electrode and a capacitor by adopting a multilayer structure using a capacitor, which is a passive element that can be implemented in an intermediate layer in a semiconductor process.

[0033] In addition, an object of the present invention is to provide a micro display device and a display system including the same, which can improve the picture quality of a display device and reduce the amount of data transmission and the circuit capacity of an implementation means by generating an image whose resolution changes according to a person's gaze using a variable resolution display device for each area.

[0034]

[0035] In order to achieve the above object, a pixel driving circuit for implementing variable resolution by area according to the present invention comprises: a plurality of column lines; a plurality of row lines wired in a direction orthogonal to the plurality of column lines; a plurality of cells generated by intersecting the plurality of column lines and the plurality of row lines; a combination circuit positioned in each of the plurality of cells and connected to each of the plurality of column lines and the plurality of row lines; a pixel connected to the combination circuit and outputting pixel data according to an external control signal or a data value calculated from pixel output in a peripheral area; and characterized in that an image having the same resolution as the original resolution and a variable resolution is output by the combination circuit, so that image quality is restored in a required area.

[0036] The combination circuit of the pixel driving circuit implementing variable resolution by region according to the present invention for achieving the above object is characterized by including: a direct driving pixel circuit; an interpolation circuit that interpolates and outputs pixel output of the peripheral region; and a selection circuit that receives the output of the direct driving pixel circuit and the output of the interpolation circuit and selects and outputs them in response to a selection signal.

[0037] In order to achieve the above object, a pixel driving circuit implementing variable resolution by area according to the present invention is characterized in that, when the selection circuit selects the output of the direct driving pixel circuit, the display driver circuit selects the direct driving pixel circuit in a matrix manner and stores the corresponding video data.

[0038] In order to achieve the above object, a pixel driving circuit implementing variable resolution by region according to the present invention is characterized in that, when the selection circuit selects the output of the interpolation circuit, the interpolation circuit generates a spatially predicted value using the output of the pixel driving circuit of the peripheral area.

[0039] The selection signal of the pixel driving circuit implementing variable resolution by region according to the present invention to achieve the above purpose is characterized in that it is adjusted according to the input condition or input time of the display device.

[0040] The direct drive pixel circuit of the pixel drive circuit for implementing variable resolution by area according to the present invention for achieving the above purpose is characterized by receiving a data input signal, storing a value corresponding to data of the pixel, and defining the pixel to be directly driven in the form of voltage or current.

[0041] The pixel driving circuit for implementing variable resolution by area according to the present invention for achieving the above purpose is characterized in that, when the combination circuit is used, the ratio of selection of the direct driving pixel circuit and the interpolation circuit is variably adjusted according to the correlation of the displayed image quality data and the usage environment.

[0042] In order to achieve the above object, the direct driving pixel circuit and the interpolation circuit of the pixel driving circuit implementing variable resolution by area according to the present invention constitute an array of NM (wherein N and M are natural numbers of 2 or more), and the array by selection of the direct driving pixel circuit and the interpolation circuit is characterized in that one per two pixels on the vertical axis and the horizontal axis is selected by the direct driving pixel circuit, and the remaining pixels are selected by the interpolation circuit.

[0043] In order to achieve the above purpose, the pixel driving circuit according to the present invention for implementing variable resolution by region is characterized in that, in the array, the direct driving pixel circuit and the interpolation circuit are alternately selected on the horizontal axis.

[0044] In order to achieve the above object, the pixel driving circuit according to the present invention for implementing variable resolution by area comprises: a plurality of column lines; a plurality of row lines wired in a direction orthogonal to the plurality of column lines; a plurality of cells generated by intersecting the plurality of column lines and the plurality of row lines; a direct driving mode cell composed of a combinational circuit and a pixel and an interpolation mode cell composed of an interpolation circuit and a pixel are arranged to intersect in the horizontal and vertical directions, starting from an odd or even cell among the plurality of cells and positioned in each diagonally adjacent cell, and the direct driving mode or the interpolation mode is selectively used depending on the degree of influence on the image quality and whether it is close to the original data resolution, and an image having the same resolution as the original resolution and a variable resolution is output by the interpolation mode cell, so that the image quality is restored in a required area.

[0045] The combination circuit of the pixel driving circuit implementing variable resolution by region according to the present invention for achieving the above object is characterized by including: a direct driving pixel circuit; an interpolation circuit that interpolates and outputs pixel output of the peripheral region; and a selection circuit that receives the output of the direct driving pixel circuit and the output of the interpolation circuit and selects and outputs them in response to a selection signal.

[0046] In order to achieve the above object, the combination circuit of the pixel driving circuit implementing variable resolution by area according to the present invention comprises: a direct driving pixel circuit; a first selection circuit receiving an output of the direct driving pixel circuit and a first input and selecting and outputting in response to a first selection signal; and a second selection circuit receiving an output of the direct driving pixel circuit and a second input and selecting and outputting in response to a second selection signal; and an interpolation circuit receiving outputs of the first and second selection circuits and interpolating and outputting.

[0047] The combination circuit of the pixel driving circuit for implementing variable resolution by area according to the present invention for achieving the above object includes: a direct driving pixel circuit; a high impedance interpolation circuit; and a switch having one side connected to an output terminal of the direct driving pixel circuit to form a low impedance; and is characterized in that an output value of the direct driving pixel circuit or an output value of the high impedance interpolation circuit is output depending on the opening and closing of the switch.

[0048] The combination circuit of the pixel driving circuit implementing variable resolution by area according to the present invention for achieving the above object is characterized by including: an Nth voltage driving unit; an output selection unit that receives two outputs from the Nth voltage driving unit and performs a first switch, and receives outputs from the N-1th voltage driving unit and the N+1th voltage driving unit and performs a second switch; and an interpolation unit that receives outputs from the output selection unit, calculates an interpolation value, and outputs the calculated interpolation value.

[0049] In order to achieve the above object, the direct drive mode cells and the interpolation mode cells of the pixel driving circuit implementing variable resolution by area according to the present invention constitute an array of NM (wherein N and M are natural numbers greater than or equal to 2), and the array by selection of the direct drive mode cells and the interpolation mode cells is characterized in that it is composed of the direct drive mode cells in the case of (column, row) = (odd, odd) or (even, even), and is composed of interpolation mode cells in the remaining cases.

[0050] In order to achieve the above object, the array by selecting the direct drive pixel circuit and the interpolation circuit of the pixel drive circuit implementing variable resolution by area according to the present invention is characterized in that it is composed of the direct drive mode cells in a diagonal direction in the case of (column, row) = (odd, odd) or (even, even), and is composed of the interpolation mode cells in the remaining cases.

[0051] In order to achieve the above object, the present invention provides a pixel driving circuit for implementing variable resolution by region, comprising: a plurality of column lines; a plurality of row lines wired in a direction orthogonal to the plurality of column lines; a plurality of cells generated by intersecting the plurality of column lines and the plurality of row lines; and wherein among the plurality of cells, when (column, row) = (odd, odd) or (even, even), the cells are configured as super combination mode cells that are consecutively arranged in a diagonal direction, and in the remaining cases, the cells are configured as interpolation mode cells, and the interpolation mode cells output an image having the same resolution as the original resolution and a variable resolution, so that the image quality is restored in a required region.

[0052] In order to achieve the above object, the super combination mode cell of the pixel driving circuit implementing variable resolution by area according to the present invention is characterized in that it is composed of a super combination circuit and first and second pixels, and the interpolation mode cell is composed of an interpolation circuit and pixels.

[0053] In order to achieve the above object, the super combination circuit of the pixel driving circuit implementing variable resolution by area according to the present invention comprises: a direct driving pixel circuit; first and second interpolation circuits; a first selection circuit which receives an output of the direct driving pixel circuit and an output of the first interpolation circuit and selects and outputs the first pixel in response to a first selection signal; and a second selection circuit which receives an output of the direct driving pixel circuit and an output of the second interpolation circuit and selects and outputs the second pixel in response to a second selection signal.

[0054] In order to achieve the above object, the direct drive mode cells and the interpolation mode cells of the pixel driving circuit implementing variable resolution by area according to the present invention constitute an array of NM (wherein N and M are natural numbers greater than or equal to 2), and the array by selection of the direct drive mode cells and the interpolation mode cells is characterized in that it is composed of the direct drive mode cells in the case of (odd column, odd row) or (even column, even row), and is composed of interpolation mode cells in the remaining cases.

[0055] In order to achieve the above object, the present invention provides a pixel driving circuit for implementing variable resolution by region, comprising: a plurality of column lines; a plurality of row lines wired in a direction orthogonal to the plurality of column lines; a plurality of cells generated by intersecting the plurality of column lines and the plurality of row lines; and a plurality of cells configured as super combination mode cells by selecting a direct driving position among the plurality of cells as a pixel in a vertical direction, and outputting an image having the same resolution as the original resolution and a variable resolution by the super combination mode cells, thereby restoring image quality in a required region.

[0056] In order to achieve the above object, the super combination mode cell of the pixel driving circuit implementing variable resolution by area according to the present invention is characterized in that it is composed of a super combination circuit and first and second pixels, and the second pixel is located in a separate cell in the vertical direction from the cell in which the first pixel is located.

[0057] In order to achieve the above object, the super combination circuit of the pixel driving circuit implementing variable resolution by area according to the present invention comprises: a direct driving pixel circuit; first and second interpolation circuits; a first selection circuit which receives an output of the direct driving pixel circuit and an output of the first interpolation circuit and selects and outputs the first pixel in response to a first selection signal; and a second selection circuit which receives an output of the direct driving pixel circuit and an output of the second interpolation circuit and selects and outputs the second pixel in response to a second selection signal.

[0058] In order to achieve the above object, the pixel driving circuit according to the present invention for implementing variable resolution by region comprises: a plurality of column lines; a plurality of row lines wired in a direction orthogonal to the plurality of column lines; a plurality of cells generated by intersecting the plurality of column lines and the plurality of row lines; and a direct driving pixel circuit among the plurality of cells, wherein 2N pixels (N is an integer greater than or equal to 2) are selected to form a super combination mode cell in succession, and an image having the same resolution as the original resolution and a variable resolution is output by the super combination mode cell, so that the image quality is restored in a required region.

[0059] In order to achieve the above object, a pixel driving circuit implementing variable resolution by region according to the present invention comprises: a plurality of column lines; a plurality of row lines wired in a direction orthogonal to the plurality of column lines; a plurality of cells generated by intersecting the plurality of column lines and the plurality of row lines; even rows and even columns among the plurality of cells are configured as combination mode cells, and the remainder are configured as direct drive mode cells, and an image having the same resolution as the original resolution and a variable resolution is output by the combination mode cells, thereby restoring image quality in a required region.

[0060]

[0061] In order to achieve the above object, a pixel circuit using a capacitor network according to the present invention is a pixel circuit that forms a plurality of pixel cells in a vertical direction and a horizontal direction using a capacitor network, the pixel driving circuit being entirely composed of a combinational circuit, wherein each of the plurality of pixel cells includes: a voltage-driven pixel driving circuit connected to each of a plurality of pixel electrodes; first and second capacitors each positioned between two pixel electrodes among the plurality of pixel electrodes and connected in parallel with the voltage-driven pixel driving circuit; and switches each positioned between the voltage-driven pixel driving circuit and the plurality of pixel electrodes and switching; wherein the voltage-driven pixel driving circuit is characterized in that it is driven in a direct driving manner or an interpolation manner depending on whether the switch is turned on.

[0062] In order to achieve the above object, a pixel circuit using a capacitor network according to the present invention, the voltage-driven pixel driving circuit comprises: a plurality of column lines; a plurality of row lines wired in a direction orthogonal to the plurality of column lines; a plurality of cells generated by intersecting the plurality of column lines and the plurality of row lines; a combination circuit positioned in each of the plurality of cells and connected to each of the plurality of column lines and the plurality of row lines; and a pixel connected to the combination circuit and outputting pixel data according to an external control signal or a data value calculated from pixel output in a peripheral area; characterized in that an image having the same resolution as the original resolution and a variable resolution is output by the combination circuit, so that image quality is restored in a required area.

[0063] In order to achieve the above object, a pixel circuit using a capacitor network according to the present invention is characterized in that the combination circuit includes: a direct-drive pixel circuit; an interpolation circuit that interpolates and outputs pixel output of the peripheral portion; and a selection circuit that receives the output of the direct-drive pixel circuit and the output of the interpolation circuit and selects and outputs them in response to a selection signal.

[0064] A pixel circuit using a capacitor network according to the present invention for achieving the above purpose is characterized in that, when the selection circuit selects the output of the direct drive pixel circuit, the display driver circuit selects the direct drive pixel circuit in a matrix manner and stores the corresponding video data.

[0065] A pixel circuit using a capacitor network according to the present invention for achieving the above purpose is characterized in that, when the selection circuit selects the output of the interpolation circuit, the interpolation circuit generates a spatially predicted value using the output of the pixel driving circuit of the peripheral area.

[0066] A pixel circuit using a capacitor network according to the present invention to achieve the above purpose is characterized in that the selection signal is controlled according to an input condition or input time of a display device.

[0067] A pixel circuit using a capacitor network according to the present invention for achieving the above purpose is characterized in that the direct drive pixel circuit receives a data input signal, stores a value corresponding to the data of the pixel, and defines the pixel to be directly driven in the form of voltage or current.

[0068] The pixel circuit using a capacitor network according to the present invention for achieving the above purpose is characterized in that, when the combination circuit is used, the ratio of selection of the direct drive pixel circuit and the interpolation circuit is variably adjusted according to the correlation of the displayed image quality data and the usage environment.

[0069] In order to achieve the above object, a pixel circuit using a capacitor network according to the present invention is a pixel circuit in which a part of a pixel driving circuit is configured as a combinational circuit, and a plurality of pixel cells are formed in a diagonal direction and a vertical direction using a capacitor network, wherein each of the plurality of pixel cells includes a voltage-driven pixel driving circuit; first and second capacitors positioned between a plurality of pixel electrodes and connected in parallel with the voltage-driven pixel driving circuit; and a switch positioned between the voltage-driven pixel driving circuit and the pixel electrode and switched; wherein the combinational circuit includes a direct-driven pixel circuit and an interpolation circuit, and the voltage-driven pixel driving circuit is characterized in that it is driven in a direct-driven manner or by an average voltage value of peripheral pixel electrodes depending on whether the switch is turned on.

[0070] In order to achieve the above object, a pixel circuit using a capacitor network according to the present invention, the voltage-driven pixel driving circuit comprises: a plurality of column lines; a plurality of row lines wired in a direction orthogonal to the plurality of column lines; a plurality of cells generated by intersecting the plurality of column lines and the plurality of row lines; and a direct-drive mode cell composed of a combinational circuit and a pixel and an interpolation mode cell composed of an interpolation circuit and a pixel are arranged to intersect in the horizontal and vertical directions, starting from an odd or even cell among the plurality of cells and positioned in each diagonally adjacent cell, and the direct-drive mode or the interpolation mode is selectively used depending on the degree of influence on the image quality and the proximity to the original data resolution.

[0071] In order to achieve the above object, a pixel circuit using a capacitor network according to the present invention is characterized in that the combination circuit includes: a direct-drive pixel circuit; an interpolation circuit that interpolates and outputs pixel output of the peripheral portion; and a selection circuit that receives the output of the direct-drive pixel circuit and the output of the interpolation circuit and selects and outputs them in response to a selection signal.

[0072] In order to achieve the above object, a pixel circuit using a capacitor network according to the present invention is characterized in that the combination circuit includes: a direct-drive pixel circuit; a first selection circuit that receives an output of the direct-drive pixel circuit and a first input and selects and outputs in response to a first selection signal; a second selection circuit that receives an output of the direct-drive pixel circuit and a second input and selects and outputs in response to a second selection signal; and an interpolation circuit that receives outputs of the first and second selection circuits and interpolates and outputs.

[0073] In order to achieve the above object, a pixel circuit using a capacitor network according to the present invention comprises a combination circuit comprising: a direct drive pixel circuit; a high impedance interpolation circuit; and a switch having one side connected to an output terminal of the direct drive pixel circuit to form a low impedance; and is characterized in that an output value of the direct drive pixel circuit or an output value of the high impedance interpolation circuit is output depending on the opening and closing of the switch.

[0074] In order to achieve the above object, a pixel circuit using a capacitor network according to the present invention is characterized in that the combination circuit includes: an Nth voltage driving unit; an output selection unit that receives two outputs from the Nth voltage driving unit and performs a first switch, and receives outputs from the N-1th voltage driving unit and the N+1th voltage driving unit and performs a second switch; and an interpolation unit that receives outputs from the output selection unit, calculates an interpolation value, and outputs the calculated interpolation value.

[0075] In order to achieve the above object, a pixel circuit using a capacitor network according to the present invention is a pixel circuit in which a pixel driving circuit, part of which is composed of a super combinational circuit, forms a plurality of pixel cells in a diagonal direction, a horizontal direction, or a vertical direction using a capacitor network.

[0076] Each of the plurality of pixel cells includes a voltage-driven pixel driving circuit connected to each of a plurality of pixel electrodes in a diagonal direction, a horizontal direction, or a vertical direction; first and second capacitors respectively positioned between two pixel electrodes among the plurality of pixel electrodes and connected in parallel with the voltage-driven pixel driving circuit; a first switch positioned between the voltage-driven pixel driving circuit and a first pixel electrode among the plurality of pixel electrodes in a diagonal direction, a horizontal direction, or a vertical direction and switching; and a second switch positioned between the voltage-driven pixel driving circuit and a second pixel electrode adjacent to the first pixel electrode in a diagonal direction, a horizontal direction, or a vertical direction and switching; wherein the super combinational circuit includes a direct-driven pixel circuit and a plurality of interpolation circuits, and the voltage-driven pixel driving circuit is characterized in that it is driven in a direct-driven manner or an interpolation manner depending on whether the first and second switches are turned on.

[0077] In order to achieve the above object, a pixel circuit using a capacitor network according to the present invention, wherein the voltage-driven pixel driving circuit comprises: a plurality of column lines; a plurality of row lines wired in a direction orthogonal to the plurality of column lines; a plurality of cells generated by intersecting the plurality of column lines and the plurality of row lines; and among the plurality of cells, when (column, row) = (odd, odd) or (even, even), the cells are configured as super combination mode cells in a diagonal direction, and in the remaining cases, the cells are configured as interpolation mode cells.

[0078] A pixel circuit using a capacitor network according to the present invention for achieving the above purpose is characterized in that the super combination mode cell is composed of a super combination circuit and first and second pixels, and the interpolation mode cell is composed of an interpolation circuit and pixels.

[0079] In order to achieve the above object, a pixel circuit using a capacitor network according to the present invention is characterized in that the super combinational circuit includes: a direct-drive pixel circuit; first and second interpolation circuits; a first selection circuit that receives an output of the direct-drive pixel circuit and an output of the first interpolation circuit and selects and outputs the first pixel in response to a first selection signal; and a second selection circuit that receives an output of the direct-drive pixel circuit and an output of the second interpolation circuit and selects and outputs the second pixel in response to a second selection signal.

[0080]

[0081] In order to achieve the above object, a method for manufacturing a pixel circuit using a capacitor network according to the present invention is provided, in a method for manufacturing a pixel circuit in which a pixel driving circuit, part of which is composed of a super combinational circuit, forms a plurality of pixel cells in a horizontal direction using a capacitor network, comprising the steps of: (a) forming a pixel driving circuit substrate on a substrate by dividing the substrate into a plurality of pixel driving circuit output voltage layers; (b) depositing a first via material on an upper surface area of ​​the pixel driving circuit output voltage layers at both ends of the separated pixel driving circuit substrate, and depositing a first intermetallic dielectric on a remaining area of ​​the upper surface of the substrate; (c) stacking a first layer electrode on an upper surface of the first via material on an upper portion of a pixel driving circuit substrate in contact with the deposited first via material among the separated pixel driving circuit substrates; (d) depositing a second intermetallic dielectric filling the upper surfaces of the stacked first layer electrodes and a space created by forming a plurality of first layer electrodes, and then depositing a second via material on an upper surface area of ​​the pixel driving circuit output voltage layer at the center; And (e) a step of laminating a second layer electrode on the upper surface area of ​​the central pixel driving circuit output voltage layer and on both ends of the upper surface of the deposited second intermetallic dielectric.

[0082] In order to achieve the above object, the method for manufacturing a pixel circuit using a capacitor network according to the present invention is characterized in that, in the step (b), the first via is formed through a step of performing a photography process on an area corresponding to an upper surface of a pixel driver circuit output voltage layer located at both ends among an upper surface area of ​​the first intermetal dielectric; a step of forming a first intermetal dielectric exposing only an upper surface of the pixel driver circuit output voltage layer located at both ends through an etching process; a step of depositing a first via material on an upper surface of the first intermetal dielectric and an upper surface of the exposed pixel driver circuit output voltage layer; and a step of planarizing an upper surface of the deposited first via material to expose only the first via material that contacts the upper surface of the pixel driver circuit output voltage layer located at both ends.

[0083] In order to achieve the above object, the method for manufacturing a pixel circuit using a capacitor network according to the present invention is characterized in that, after the step of exposing only the first via material, the first layer electrode is formed through the steps of: depositing a first metal material on the planarized first intermetal dielectric and the upper surface of the first via using a thin film process; performing a photography process using a photoresist pattern in which only an area corresponding to the upper surface of the first via is opened; and performing an etching process to leave only the first metal film in contact with the exposed first via among the first metal films formed by the deposited first metal material.

[0084] In order to achieve the above object, a method for manufacturing a pixel circuit using a capacitor network according to the present invention is provided, wherein a pixel driving circuit, part of which is composed of a super combinational circuit, forms a plurality of pixel cells in a horizontal direction using a capacitor network, the method comprising: (a) forming a pixel driving circuit substrate on a substrate by dividing the substrate into a plurality of pixel driving circuit output voltage layers; (b) depositing a first intermetal dielectric on an upper surface of the separated pixel driving circuit substrate; (c) stacking a first layer electrode in a region of the upper surface of the deposited first intermetal dielectric that does not vertically overlap with the pixel driving circuit output voltage layer; (d) depositing a second intermetal dielectric filling the upper surface of the stacked first layer electrode and a space created by forming a plurality of first layer electrodes, and then depositing a first via material that makes contact with the plurality of pixel driving circuit output voltage layers; and (e) stacking a second layer electrode that makes contact with the upper surface of the deposited first via material.

[0085] In order to achieve the above object, a method for manufacturing a pixel circuit using a capacitor network according to the present invention is provided, wherein a pixel driving circuit, part of which is composed of a super combinational circuit, forms a plurality of pixel cells in a horizontal direction using a capacitor network, the method comprising: (a) sequentially stacking a first barrier metal layer, a first layer electrode, and a second barrier metal layer on an upper surface of a first intermetal dielectric, and metal patterning to create a plurality of metal patterned bodies; (b) depositing a second intermetal dielectric, creating a plurality of first vias penetrating the first vias, and stacking second layer electrodes; (c) metal patterning to cover the upper surfaces of first vias that do not contact a pixel circuit output voltage layer with a second layer electrode, and exposing the upper surfaces of the first vias that contact the pixel circuit output voltage layer; (d) depositing a third intermetal dielectric, and creating a second via extending from the exposed first vias; and (e) a step of stacking a third layer electrode and metal patterning to create a plurality of holes.

[0086] The method for manufacturing a pixel circuit using a capacitor network according to the present invention for achieving the above purpose is characterized by further including a step of planarizing the exposed upper surface between the steps (a) and (b) and between the steps (d) and (e).

[0087] The step (b) of the method for manufacturing a pixel circuit using a capacitor network according to the present invention for achieving the above object is characterized by further including the steps of: creating a plurality of first via holes that penetrate the second intermetallic dielectric and are connected to the upper surface of each of the plurality of metal patterning bodies; and covering the sidewalls of each of the plurality of first via holes with a third barrier metal layer and filling the plurality of first via holes with a first via material.

[0088] The step (c) of the method for manufacturing a pixel circuit using a capacitor network according to the present invention for achieving the above object is characterized by further including the steps of: depositing the second intermetal dielectric on the upper surfaces of the plurality of metal patterning bodies and the exposed upper surfaces of the first intermetal dielectric upper surfaces; and metal patterning the upper surfaces of the first vias among the upper surfaces of the first via materials so that the first vias do not contact the pixel circuit output voltage layer are covered by the second layer electrode, and exposing the upper surfaces of the first vias that contact the pixel circuit output voltage layer.

[0089] In order to achieve the above object, the step (d) of the method for manufacturing a pixel circuit using a capacitor network according to the present invention is characterized by further comprising: a step of metal patterning such that upper surfaces of first vias, among upper surfaces of the first via material, which do not contact the pixel circuit output voltage layer, are covered by the second layer electrode, thereby exposing upper surfaces of the first vias that contact the pixel circuit output voltage layer; a step of depositing a third intermetal dielectric on the upper surface of the second layer electrode, a portion of the second intermetal dielectric, and the upper surfaces of the exposed first vias; a step of creating a second via hole penetrating from a portion of the deposited third intermetal dielectric that is in contact with the upper surfaces of the exposed first vias to the upper surface of the third intermetal dielectric; and a step of covering a sidewall of the second via hole with the third barrier metal layer and filling the second via hole with a second via material.

[0090] The step (e) of the method for manufacturing a pixel circuit using a capacitor network according to the present invention for achieving the above object comprises the steps of sequentially stacking a fourth barrier metal layer and the third layer electrode on the upper surface of the third intermetallic dielectric and the upper surface of the second via material; and, through the metal patterning, creating the plurality of holes in the portion of the fourth barrier metal layer and the third layer electrode corresponding to the upper surface of the first vias that do not contact the pixel circuit output voltage layer.

[0091] In order to achieve the above purpose, the first to fourth barrier metal layers of the method for manufacturing a pixel circuit using a capacitor network according to the present invention are characterized in that they are Ti / TiN metal layers.

[0092] In order to achieve the above purpose, the first via material of the method for manufacturing a pixel circuit using a capacitor network according to the present invention is characterized in that it is tungsten.

[0093] A method for manufacturing a pixel circuit using a capacitor network according to the present invention for achieving the above purpose is characterized by reducing the thickness of the third intermetallic dielectric, thereby increasing the capacitor capacity between the second electrode layer and the third electrode layer.

[0094] In order to achieve the above purpose, the material of the fourth barrier metal layer of the method for manufacturing a pixel circuit using a capacitor network according to the present invention is characterized by being the same as the material of the second via material.

[0095] Meanwhile, information on a method for manufacturing a pixel circuit using a capacitor network according to the present invention to achieve the above purpose can be stored in a computer-readable recording medium.

[0096] In order to achieve the above object, a display system according to the present invention comprises a combinational circuit connected to each of a plurality of column lines and each of a plurality of row lines, and a pixel circuit connected to the combinational circuit, and outputting an image having a resolution variably converted by the combinational circuit, the display system comprising: an image generator which receives image data and an image source, and generates an image by changing the resolution by region for pixels reduced by a factor of 1 / r (r: data reduction rate); a video transmission unit which transmits the image of the generated 1 / r-multiplied pixels at the same resolution; and a display device which receives the transmitted image of the 1 / r-multiplied pixels, converts it into an image of r-multiplied pixels, and outputs it; wherein the change in resolution by region is characterized in that the resolution by region of the pixels changes according to the position of the user's gaze when the user's gaze changes.

[0097] In order to achieve the above object, the display device of the display system according to the present invention comprises a video data receiving unit that receives video data divided by region from the video transmitting unit; a display time driving unit that receives the video data from the video data receiving unit and converts a signal according to timing suitable for a column driving unit and a row driving unit of an active matrix type; a display pixel driving unit that receives the converted signal and stores variable data in the column driving unit; and a position variable driving interpolation processing pixel unit that receives the stored variable data and outputs a pixel image having a final resolution through a direct driving method and an interpolation driving method.

[0098] The display device of the display system according to the present invention for achieving the above purpose is characterized in that it receives video data from N separated transmission lines and causes the display time driving unit to store signals for each area in the corresponding pixel location of the active matrix circuit.

[0099] In order to achieve the above object, the display system according to the present invention is characterized in that, when the user's gaze is directed toward the center, the area in front of the gaze has no scaling, the area in front of the gaze at a short distance has a two-fold scaling using a spatial interpolation method, and the area in front of the gaze at a long distance has a four-fold scaling using a spatial interpolation method.

[0100] The image data of the display system according to the present invention for achieving the above purpose is characterized in that it can be virtual image object data.

[0101] The image generator of the display system according to the present invention for achieving the above purpose is characterized in that it changes the resolution for pixels reduced by the 1 / r factor by applying the data reduction rate (r) in a foveated rendering manner.

[0102] The display system according to the present invention for achieving the above purpose is characterized in that the display screen is divided into 1xm rectangular block units and the driving method is different for each block.

[0103] The driving method of the display system according to the present invention for achieving the above object is characterized in that it is divided into a first region in which all pixels are directly driven to directly receive an original image; a second region in which the resolution of each block adjacent to the first region is driven at 1 / 4 and the remaining pixels are driven using an interpolation circuit; and a third region in which pixels excluding the first region and the second region are driven at 1 / 16.

[0104] In order to achieve the above object, a display system according to the present invention comprises a combinational circuit connected to each of a plurality of column lines and each of a plurality of row lines, and a pixel circuit that outputs an image having a resolution variably converted by the combinational circuit, the display system comprising: an image generator that receives image data and an image source, changes the resolution by region for pixels reduced by a factor of 1 / r, divides the image into N images, and outputs them; an image recombiner that receives images changed to the same resolution, a resolution reduced by a factor of 1 / K2 for each axis, and a resolution reduced by a factor of K1 for each axis for each of the divided N images, and recombines and outputs them; and a display device that receives the recombined images and outputs them respectively with the changed resolution, wherein the change in resolution by region is characterized in that the resolution of the pixels by region changes according to the position of the user's gaze when the user's gaze changes.

[0105] In order to achieve the above object, the image generator of the display system according to the present invention transmits image data with the same resolution as the original image for the foveal area, transmits the image data by down-sampling it with a resolution reduced by 1 / K2 times for each axis with the image recombiner for the blend area, and transmits the image data by down-sampling it with a resolution reduced by K1 times for each axis with the image recombiner for the peripheral area or background area.

[0106] The image generator of the display system according to the present invention for achieving the above object maintains the same resolution in all of the image generator, the image recombiner and the display device, and the image of the blend region is input to the image recombiner with the resolution reduced by K2 times in the image generator, and is converted back to a resolution increased by K22 times in the display device and output.

[0107] The image of the peripheral area or the background area is input to the image recombiner with a resolution reduced by K1 times from the original image resolution by the image generator, and is converted to a resolution increased by K12 times and output by the display device.

[0108] In order to achieve the above object, a microdisplay device according to the present invention comprises a combinational circuit connected to each of a plurality of column lines and each of a plurality of row lines, and first and second pixel circuits having pixels connected to the combinational circuits and outputting images having a resolution variably changed by the combinational circuits, the display system comprising: a video input unit for receiving an image to be displayed on a screen; a pixel driving circuit for driving the pixels at the converted resolution; and a capacitor-coupled pixel array comprising the first pixel circuit driven by a voltage and the second pixel circuit driven through capacitor coupling with the first pixel circuit; characterized in that the resolution of the final display output of the pixel array is the same as the resolution of an image input to the video input unit.

[0109] In order to achieve the above object, a micro-display device according to the present invention comprises a combinational circuit connected to each of a plurality of column lines and each of a plurality of row lines, and a pixel circuit that is connected to the combinational circuit and outputs an image having a resolution variably converted by the combinational circuit, the display system comprising: a video input unit that receives an image to be displayed on a screen; a pixel compensation preprocessor that receives the input image and preprocesses it by reflecting the characteristics of capacitor coupling; a resolution converter that converts the resolution of the preprocessed image to 1 / 2 resolution; and a pixel driving circuit that drives the pixel with the converted resolution; and is characterized in that the display is driven in a direct driving manner or an interpolation manner depending on whether a switch connecting the pixel driving circuit and an output terminal is turned on.

[0110] In order to achieve the above object, a microdisplay device according to the present invention comprises a combinational circuit connected to each of a plurality of column lines and each of a plurality of row lines, and a pixel circuit for outputting an image having a resolution variably converted by the combinational circuit, the display system comprising: a video input unit for receiving an image to be displayed on a screen; an image pattern detection unit for receiving an image having a first resolution output from the video input unit and detecting an image pattern; a pixel compensation preprocessor for preprocessing an image in which the image pattern is detected by reflecting the characteristics of capacitor coupling; a direct drive pixel selection unit for selecting a pixel to be directly driven using a direct drive pixel selection algorithm for the preprocessed pixels; a resolution converter for converting the resolution of the selected pixel to a resolution half the first resolution; a pixel driving and interpolation circuit for driving and interpolating the pixel at the converted resolution; and an array of pixels for receiving the driven and interpolated pixel and operating at a resolution twice the first resolution. It is characterized in that it is driven in a direct driving manner or an interpolation manner depending on whether a switch connecting the pixel driving and interpolation circuit and the output terminal is turned on.

[0111] In order to achieve the above object, a microdisplay device according to the present invention comprises a combinational circuit connected to each of a plurality of column lines and each of a plurality of row lines, and a pixel circuit for outputting an image having a resolution variably converted by the combinational circuit, the display system comprising: a video input unit for receiving an image to be displayed on a screen; a pixel compensation preprocessor for preprocessing the input image by reflecting the characteristics of capacitor coupling; a driving pixel selector for selecting a pixel to be driven for the preprocessed pixel; a resolution converter for converting the resolution of the selected pixel to a resolution 1 / n times higher; a pixel driving and interpolation circuit for driving and interpolating the pixel with the converted resolution; and an array display pixel for receiving the driven and interpolated pixel and operating at a resolution 1 / n times higher; characterized in that the display is driven in a direct driving manner or an interpolation manner depending on whether a switch connecting the pixel driving and interpolation circuit and an output terminal is turned on.

[0112]

[0113] According to the present invention, the driving mode setting can be varied according to the input conditions or input time of the display device, thereby optimizing the image quality of the input image, the bandwidth of the system, and the power consumption.

[0114] Additionally, the resolution can be varied according to the area of ​​focus of the user wearing virtual reality glasses, augmented reality glasses, etc., to efficiently improve image quality.

[0115] In addition, by reducing the number of voltage pixel driving circuits required for direct driving, the integration level of the entire display pixel circuit can be increased.

[0116] Additionally, when the user's gaze changes, the resolution of the image can be adjusted for each area depending on the position of the gaze.

[0117] In addition, by implementing a capacitor network circuit for creating a combinational circuit in a voltage-driven manner and arranging multiple layers in an overlapping manner, an interpolation circuit network can be constructed without separate wiring.

[0118] In addition, the area of ​​the pixel circuit can be minimized by implementing the capacitor in the intermediate layer without having to implement the circuit that drives the data of each pixel and the interpolation circuit on the same plane.

[0119] In addition, the capacity of the capacitor in the pixel circuit using the capacitor network can be increased, thereby improving and enhancing the performance of the pixel circuit, and the cost and time required for the manufacturing process can be significantly reduced by reducing the additional process for manufacturing the pixel circuit.

[0120] In addition, in order to generate high-resolution images, a large amount of calculations are required, and in the case of games and graphic playback that require high performance and power consumption of the processor, by generating images by varying the resolution by area, the required amount of calculations and memory can be reduced, and efficient power consumption can be achieved.

[0121] In addition, by using only the position variable drive interpolation processing pixel part, the desired display resolution can be obtained in the final stage, and by driving the average value of the voltage of the directly driven pixel, an improved image quality can be obtained compared to the low resolution image of the conventional technology.

[0122] In addition, it is possible to connect a variable resolution display device by area without changing the conventional video transmitter.

[0123] The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

[0124] Figure 1 is a drawing for explaining a pixel driving method of a conventional display device.

[0125] Figure 2 is a block diagram of a conventional pixel circuit.

[0126] Figure 3 is a circuit diagram showing various embodiments of a conventional pixel circuit as an example.

[0127] Figure 4 is a flowchart of input and output data processing of a typical display device.

[0128] Figure 5 is a block diagram of a conventional display system that variably changes the resolution of a display device.

[0129] FIG. 6 is a configuration diagram of a pixel circuit according to the first embodiment (Embodiment 1-1) of the first embodiment of the present invention.

[0130] FIG. 7 is a drawing showing an example of an arrangement of output image pixels according to selection of a direct drive pixel or an interpolation drive circuit according to the first embodiment of the present invention illustrated in FIG. 6.

[0131] FIG. 8 is a configuration diagram of a pixel circuit according to the second embodiment (Embodiment 1-2) of the first embodiment of the present invention.

[0132] FIG. 9 is a drawing showing an example of an arrangement of output image pixels according to selection of a direct drive pixel or an interpolation drive circuit according to the first and second embodiments of the present invention.

[0133] FIG. 10 is a configuration diagram of a third embodiment (Embodiment 1-3) of the first embodiment using a super combinational circuit that is a modification of the combinational circuit in Embodiment 1-2 shown in FIG. 9.

[0134] FIG. 11 is a drawing showing an example of an arrangement of output image pixels according to selection of a direct drive pixel or an interpolation drive circuit according to the first to third embodiment of the present invention.

[0135] FIG. 12 is a configuration diagram of the fourth embodiment (Embodiment 1-4) of the first embodiment utilizing the super combinational circuit (1310-N) illustrated in FIG. 10.

[0136] Figure 13 is a configuration diagram of the fifth embodiment (Embodiment 1-5) of the first embodiment of the present invention.

[0137] FIG. 14 is a configuration diagram of a pixel driving circuit according to the sixth embodiment (embodiment 1-6) of the first embodiment of the present invention.

[0138] Figure 15 is a block diagram of a first embodiment of a combination circuit used in the present invention.

[0139] Figure 16 is a block diagram of a second embodiment of a combination circuit used in the present invention.

[0140] Figure 17 is a block diagram of a third embodiment of a combination circuit used in the present invention.

[0141] Figure 18 is a block diagram of a fourth embodiment of a combination circuit used in the present invention.

[0142] Figure 19 is a block diagram of a fifth embodiment of a combination circuit used in the present invention.

[0143] Figure 20 is a block diagram of a sixth embodiment of a combination circuit used in the present invention.

[0144] Figures 21a to 21c are photographs comparing the results of actually applying the present invention with the original image and a case using conventional technology.

[0145] Fig. 22 is a first embodiment of a capacitor network implemented using a capacitor network for the pixel driving circuit of Fig. 6 (Embodiment 1-1) in which all pixels are formed by combinational circuits.

[0146] Fig. 23a shows a pixel of a diagonal pixel as a combination circuit of a direct-drive pixel circuit and an interpolation circuit (the 2nd embodiment of a capacitor network), and Fig. 23b shows a pixel of a vertical pixel as a combination circuit of a direct-drive pixel circuit and an interpolation circuit (the 2nd embodiment of a capacitor network).

[0147] FIGS. 24a to 24c are drawings for explaining a third embodiment of a capacitor network implemented using a capacitor network for the pixel driving circuit of FIG. 10 in which some pixels are formed of super combinational circuits.

[0148] Fig. 25 is a plan view (a) and an equivalent circuit (b) for explaining a method of arranging the interpolation circuit arrangement for actually implementing the circuits illustrated in Figs. 24a to 24c in two layers on a semiconductor substrate.

[0149] Fig. 26 is a plan view (a) and an equivalent circuit (b) for explaining a method of arranging the interpolation circuit arrangement for actually implementing the Fig. 24a circuit and the Fig. 24c circuit in two layers on a semiconductor substrate.

[0150] Fig. 27 is a plan view (a) and an equivalent circuit (b) for explaining a method of arranging the interpolation circuit arrangement for actually implementing the Fig. 23b circuit in two layers on a semiconductor substrate.

[0151] Fig. 28 is a cross-sectional view of an interpolation circuit arrangement for actually implementing the circuit of Fig. 23b.

[0152] FIG. 29 is a process diagram for explaining a method for manufacturing a pixel circuit according to the first embodiment (2-1 embodiment) of the second embodiment of the present invention.

[0153] FIG. 30 is a flowchart for a pixel circuit manufacturing method according to the first embodiment (2-1 embodiment) of the second embodiment of the present invention illustrated in FIG. 29.

[0154] Figure 31 is a process diagram for explaining the detailed process of step (S2120) of the manufacturing method illustrated in Figure 30.

[0155] Figure 32 is a flowchart of the detailed process of step (S2120) of the manufacturing method illustrated in Figure 30.

[0156] Figure 33 is a process diagram for explaining the detailed process of step (S2140) of the manufacturing method illustrated in Figure 30.

[0157] Figure 34 is a flowchart of the detailed process of step (S2140) of the manufacturing method illustrated in Figure 30.

[0158] FIG. 35 is a process diagram for explaining a manufacturing method of a pixel driving circuit according to the second embodiment (2-2 embodiment) of the second embodiment of the present invention.

[0159] Figure 36 is a flowchart of a method for manufacturing a pixel driving circuit according to the second embodiment of the present invention.

[0160] FIG. 37 is a process diagram for explaining a method of manufacturing a pixel driving circuit that is commonly used in the third embodiment (Embodiment 2-3) and the fourth embodiment (Embodiment 2-4) of the second embodiment of the present invention.

[0161] Figure 38 is a process diagram for explaining a manufacturing method of a pixel driving circuit according to the second-third embodiment of the present invention.

[0162] Figure 39 is a flowchart of a method for manufacturing a pixel driving circuit according to the second-third embodiment of the present invention.

[0163] Figure 40 is a flowchart for the detailed operation of step (S2380) in the second-third embodiment illustrated in Figure 39.

[0164] Figure 41 is a process diagram for explaining a manufacturing method of a pixel driving circuit according to the second-fourth embodiment of the present invention.

[0165] Figure 42 is a flowchart of a method for manufacturing a pixel driving circuit according to the second-fourth embodiment of the present invention.

[0166] FIG. 43 is a configuration diagram for explaining the direct drive mode of a micro display device according to the first embodiment (embodiment 3-1) of the third embodiment of the present invention.

[0167] FIG. 44 is a configuration diagram for explaining the x / 2-y / 2 mode of a micro display device according to the second embodiment (embodiment 3-2) of the third embodiment of the present invention.

[0168] FIG. 45 is a configuration diagram for explaining a 1 / 4 pixel selection mode of a micro display device according to the third embodiment (embodiment 3-3) of the third embodiment of the present invention.

[0169] FIG. 46 is a configuration diagram for explaining a 1 / n pixel selection mode of a micro display device according to the fourth embodiment (embodiment 3-4) of the third embodiment of the present invention.

[0170] Figure 47 is a block diagram of a display system according to one embodiment of the present invention.

[0171] Figure 48 is a conceptual diagram for explaining an image when using a display device for variable resolution by area as shown in Figure 47.

[0172] Figures 49a to 49d are drawings for explaining an embodiment of distinguishing each area of ​​a display device for variable resolution by area.

[0173] Figure 50 is a block diagram of a device implementing a data transmission method of a display device having variable resolution by area.

[0174] Figure 51 is a conceptual diagram for explaining the interrelationship between outputs of each component of a device implementing the data transmission method illustrated in Figure 50.

[0175]

[0176] Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or similar components will be assigned the same reference numbers, and redundant descriptions thereof will be omitted. The suffix "부" used for components in the following description is assigned or used interchangeably solely for the convenience of writing the specification, and does not in itself have a distinct meaning or role.

[0177] In addition, when describing the embodiments disclosed in this specification, if it is determined that a detailed description of a related known technology may obscure the gist of the embodiments disclosed in this specification, the detailed description thereof will be omitted. In addition, the attached drawings are only intended to facilitate easy understanding of the embodiments disclosed in this specification, and the technical ideas disclosed in this specification are not limited by the attached drawings, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and technical scope of the present invention.

[0178] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the present invention, and the present invention is defined solely by the scope of the claims.

[0179] The terminology used herein is for the purpose of describing embodiments only and is not intended to limit the present invention. In this specification, the singular also includes the plural unless specifically stated otherwise. As used herein, the terms "comprises" and / or "comprising" do not exclude the presence or addition of one or more other components in addition to the mentioned components. Like reference numerals refer to like components throughout the specification, and "and / or" includes each and any combination of one or more of the mentioned components. Although "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, it should be understood that a first component mentioned below may also be a second component within the technical spirit of the present invention.

[0180] Unless otherwise defined, all terms (including technical and scientific terms) used herein may be used in their common sense to those skilled in the art to which the present invention pertains. Furthermore, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.

[0181]

[0182] Hereinafter, embodiments according to the present invention will be described in detail with reference to the attached drawings.

[0183] Pixel circuit (first embodiment)

[0184] Example 1-1

[0185] FIG. 6 is a configuration diagram of a pixel circuit according to a first embodiment (Embodiment 1-1) of the first embodiment of the present invention, which includes a plurality of column lines, a plurality of row lines, and a plurality of first unit cells (1100-N).

[0186] Each of the plurality of first unit cells (1100-N) includes a pixel driving circuit (1110-N) and a pixel (1120-N).

[0187] Among them, the pixel driving circuit (1110-N) is located in each of the plurality of cells generated by intersecting a plurality of column lines and a plurality of row lines, and drives the pixel (1120-N) included in the first unit cell.

[0188] That is, in the first embodiment of the present invention, a plurality of first unit cells illustrated in FIG. 6 include a combination circuit (1110-N) and a pixel (1120-N).

[0189] In addition, the combination circuit (1110-N) is located within the Nth cell among the plurality of cells created by intersecting a plurality of column lines and a plurality of row lines, and internally includes a direct drive pixel circuit (1111-N), an interpolation circuit (1112-N), and a selection circuit (1113-N), as shown in the enlarged view of FIG. 6.

[0190] For example, the Nth combinational circuit (1110-N) is located in the Nth cell created by the Nth column line and the Nth row line intersecting each other, and internally includes an Nth direct drive pixel circuit (1111-N), an Nth interpolation circuit (1112-N), and an Nth selection circuit (1113-N).

[0191] The Nth selection circuit (1113-N) receives the output of the Nth direct drive pixel circuit (1111-N) and the output of the Nth interpolation circuit (1112-N), and selects and outputs one of the two inputs in response to the Nth selection signal.

[0192] Each pixel (1120-N) can output pixel data received from an active matrix driving circuit according to an external control signal, or can output a data value determined by an interpolation circuit (1112-N) calculated from pixel output in the periphery.

[0193] If the selection circuit (1113-N) selects the output of the direct drive pixel circuit (1111-N), the display driver circuit (not shown) selects the direct drive pixel circuit (1111-N) in a matrix manner and stores the corresponding video data.

[0194] On the other hand, when the selection circuit (1113-N) selects the output of the interpolation circuit (1112-N), the corresponding pixel (1120-N) does not need to receive video data, and further, there is no need to generate or transmit the data throughout the system.

[0195] The interpolation circuit (1112-N) is a circuit that does not directly store data driven by the pixel array driving circuit, but instead generates a spatially predicted value using the output of the surrounding pixel driving circuit.

[0196] For example, when three pixels are positioned side by side, the data of the middle pixel is generally more likely to be close to the median value of the data on the left and right.

[0197] Using these properties, the left and right voltages or the output values ​​of the surrounding pixel driving circuits are used to produce the average left and right voltage values ​​or the predicted output values ​​of the surrounding pixel driving circuits.

[0198] The direct drive pixel circuit (1111-N) defines a pixel that receives a data input signal, stores a value corresponding to pixel data, and directly drives it in the form of voltage or current, as described in the example of the prior art.

[0199] In the case of a current-driven device, it is a concept of connecting a voltage-current converter to a voltage-driven circuit, and conceptually, it can also be defined as a pixel circuit that includes a voltage-current converter in a voltage-driven circuit.

[0200] When using this combination circuit (1110-N), the selection ratio of the direct drive pixel circuit (1111-N) and the interpolation circuit (1112-N) can be variably adjusted according to the correlation of the displayed image quality data and the usage environment.

[0201] If the selectivity of the interpolation circuit (1112-N) is increased, the amount of video input data is reduced because the data driven by the direct drive pixel circuit (1111-N) is not directly stored, and the requirements of the system to drive it are lowered by the selectivity.

[0202] FIG. 7 is a drawing showing an example of an arrangement of output image pixels according to selection of a direct drive pixel or an interpolation drive circuit according to the first embodiment (Embodiment 1-1) of the first embodiment of the present invention illustrated in FIG. 6.

[0203] By selecting pixels in direct drive mode, direct drive mode can be used for pixels that have a significant impact on image quality, and an interpolation circuit can be used for pixels that have relatively less impact or are close to the original data using interpolation using direct drive pixels.

[0204] The settings of these driving modes can change depending on the input conditions or time of the display device, and can optimize the image quality of the input image and the bandwidth and power consumption of the system.

[0205] That is, the increase in the selection ratio of these interpolation circuits has the effect of reducing the amount of calculation, transmission bandwidth, and power consumption required for data generation in the system.

[0206] Specifically, (a) is a case where all pixels are directly driven, desired data is stored in the pixel circuit by crossing the column line and the row line, and video data is generated and transmitted by driving the pixels through the pixel circuit.

[0207] (b) is a mode in which one pixel per two is directly driven on the vertical and horizontal axes, and the remaining pixels are selected by an interpolation circuit, so that the input video data of the display device is reduced to 1 / 4 compared to (a).

[0208] (c) allows selection of only one per two axes on the horizontal axis, so that the input video data of the display device is reduced by half compared to (a).

[0209] In the case of (d), the selection of direct drive pixels and interpolation pixels is random, and the generation and transmission of video data is reduced by the number of direct drive modes due to the overall selection ratio.

[0210]

[0211] Examples 1-2

[0212] FIG. 8 is a configuration diagram of a pixel circuit according to a second embodiment (Embodiment 1-2) of the first embodiment of the present invention, which includes a plurality of column lines, a plurality of row lines, a plurality of second unit cells (1200-N), and a plurality of third unit cells (1200-(N+1)).

[0213] The plurality of second unit cells (1200-N) each include a combination circuit (1210-N) and a pixel (1220-N), and the plurality of third unit cells (1200-(N+1)) each include an interpolation circuit (1210-(N+1)) and a pixel (1220-(N+1)).

[0214] FIG. 9 is a drawing showing an example of an arrangement of output image pixels according to selection of a direct drive pixel or an interpolation drive circuit according to the first and second embodiments of the present invention.

[0215] Each of the plurality of pairs of combinational circuits (1210-N) is positioned in each cell diagonally adjacent to the plurality of cells created by intersecting a plurality of column lines and a plurality of row lines, starting from an odd or even cell, and a plurality of second unit cells (1200-N) and a plurality of third unit cells (1200-(N+1)) are arranged to intersect in the horizontal and vertical directions.

[0216] For example, the Nth combinational circuit is located in the Nth cell created by the intersection of the Nth column line and the Mth row line, and again includes the Nth direct drive pixel circuit, the Nth interpolation circuit, and the Nth selection circuit, and in the case of some cells, it always operates only as an interpolation circuit without the direct drive pixel circuit.

[0217] That is, in Fig. 9(a) and Fig. 9(b), only in the case of (column, row) = (odd, odd) or (even, even), it is in direct driving mode, i.e., it is composed of a combinational circuit and a pixel, and in all other cases, it is in interpolation mode, i.e., it is composed of an interpolation circuit and a pixel circuit.

[0218] Through this, the pixel size and circuit complexity can be reduced.

[0219] In addition, in Fig. 9(c), when (column, row) = (odd, odd) or (even, even), it is configured in a diagonal direction in a direct driving mode, i.e., a combinational circuit and a pixel circuit, and in all other cases, it is configured in an interpolation mode, i.e., an interpolation circuit and a pixel circuit.

[0220] Meanwhile, in Fig. 9(d), any pixel is randomly configured in direct drive mode, i.e., a combination circuit and a pixel circuit, and the remaining cases are all configured in interpolation mode, i.e., an interpolation circuit and a pixel circuit.

[0221] In this embodiment, for the convenience of understanding, examples are provided for the cases of (column, row) = (odd, odd), (even, even), but depending on the display requirements and application fields, the arrangement of combinational circuits and interpolation circuits may vary.

[0222] For example, we can place combinational circuits on (column, row) = (odd columns, all rows) or (all columns, odd rows).

[0223]

[0224] Example 1-3

[0225] FIG. 10 is a configuration diagram of a third embodiment (Embodiment 1-3) of the first embodiment using a super combinational circuit that is a modification of the combinational circuit in Embodiment 1-2 shown in FIG. 9, and includes a plurality of column lines, a plurality of row lines, and a plurality of fourth unit cells.

[0226] Each of the plurality of fourth unit cells includes a direct drive mode cell (1300-N) and an interpolation mode cell (1310-(N+1)), the direct drive mode cell (1300-N) includes a super combinational circuit (1310-N) and pixels (1320-N, 1330-N), and the interpolation mode cell (1310-(N+1)) includes an interpolation circuit (1310-(N+1)) and pixels (1320-(N+1)).

[0227] The super combinational circuit (1310-N) describes an example of a case where (column, row) = (odd, odd) among multiple cells created by multiple column lines and multiple row lines intersecting each other.

[0228] The super combination mode cell composed of the super combination circuit (1310-N) and the first pixel (1320-N) has an arrangement in which the position is moved by one diagonal space, and the interpolation mode cell composed of the interpolation circuit (1310-(N+1)) and the pixel (1320-(N+1)) is arranged above, below, left, and right of the second pixel cell composed only of the second pixel (1330-N) of the super combination mode.

[0229] Here, the super combinational circuit (1310-N) includes a first path that receives the output of the direct drive pixel circuit (1311-N) and the output of the first interpolation circuit (1312-N) and selects one output according to a first selection signal and outputs it to the first pixel circuit, and a second path that receives the output of the direct drive pixel circuit (1311-N) and the output of the second interpolation circuit (1313-N) and selects one output according to a second selection signal and outputs it to the second pixel circuit.

[0230] That is, the 1-3 embodiment of FIG. 10 modifies the configuration of the combination circuit including the direct drive pixel circuit (111-N) and the single interpolation circuit (112-N) in the 1-1 embodiment illustrated in FIG. 6, and replaces it with a super combination circuit (1310-N) including the direct drive pixel circuit (1311-N) and multiple interpolation circuits (1312-N, 1313-N).

[0231] As shown in Fig. 10, in the first embodiment illustrated in Fig. 6, a second interpolation circuit (1313-N) and a second selection circuit (1315-N) are added, and in Fig. 10, (row, column) = (M, N), (M+1, N+1) are selected according to the first and second selection circuits (1314-N, 1315-N) in the super combinational circuit (1310-N).

[0232] In response to a first selection signal or a second selection signal depending on various conditions such as an input image, application method, environment, etc., the super combination circuit (1310-N) outputs pixel 1 or pixel 2, and the remainder uses the output of the interpolation circuit (1312-N, 1313-N).

[0233] FIG. 11 is a drawing showing an example of an arrangement of output image pixels according to selection of a direct drive pixel or an interpolation drive circuit according to a third embodiment (Embodiment 1-3) of the first embodiment of the present invention.

[0234] As shown in Fig. 11, the pixels of (row, column) = (M, N), (M+1, N+1) optionally have direct drive mode output, so Fig. 11(a) is a case where the pixels of (odd column, odd row) are directly driven, Fig. 11(b) is a case where the pixels of (even column, even row) are directly driven, and Fig. 11(c) and Fig. 11(d) are cases where any pixel is directly driven.

[0235]

[0236] Examples 1-4

[0237] FIG. 12 is a configuration diagram of a fourth embodiment (Embodiment 1-4) of the first embodiment utilizing the super combination circuit (1310-N) illustrated in FIG. 10, which includes a plurality of column lines, a plurality of row lines, a plurality of pairs of super combination circuits (1410-N), and first and second pixels (1420-N, 1430-N).

[0238] In the first-fourth embodiment of Fig. 12, two pixels (1420-N, 1430-N) of the super combinational circuit are formed as vertical pixels.

[0239] That is, the super combinational circuit describes an example of a case where (column, row) = (all columns, odd) among multiple cells created by multiple column lines and multiple row lines intersecting each other.

[0240] The first cell, which is composed of a super combinational circuit (1410-N) and a first pixel (1420-N), has an arrangement in which the position is moved one space in the horizontal direction, and the second cell, which is composed only of a second pixel (1430-N), is arranged below the first cell.

[0241] Here, the super combinational circuit includes a first path that receives the output of the direct drive pixel circuit and the output of the first interpolation circuit as inputs, selects one output according to a first selection signal, and outputs it to the first pixel circuit, and a second path that receives the output of the direct drive pixel circuit and the output of the second interpolation circuit as inputs, selects one output according to a second selection signal, and outputs it to the second pixel circuit.

[0242]

[0243] Example 1-5

[0244] FIG. 13 is a configuration diagram of a fifth embodiment (Embodiment 1-5) of the first embodiment of the present invention, which includes a plurality of column lines, a plurality of row lines, a plurality of pairs of four-terminal super combinational circuits (1510-N), and first to fourth pixels (1520-N, 1530-N, 1540-N, 1550-N).

[0245] The difference from the first to fourth embodiments of the present invention illustrated in Fig. 12 is that the super combinational circuit has four outputs.

[0246] In the first embodiment, there are four pixel outputs as an example, and the four pixels of (row, column) = (M, N), (M, N+1), (M+1, N), (M+1, N+1) are configured to be selected as direct drive pixel outputs and interpolation circuit outputs.

[0247] For this purpose, the super combinational circuit is a 4-terminal output super combinational circuit, and includes a direct drive pixel circuit (1511-N), 4 interpolation circuits (1512-N, 1513-N, 1514-N, 1515-N), and 4 selection circuits (1516-N, 1517-N, 1518-N, 1519-N).

[0248] That is, each of the first to fourth selection circuits (1516-N, 1517-N, 1518-N, 1519-N) responds to each of the first to fourth selection signals according to various conditions such as the input image, application method, environment, etc., and outputs one of pixels 1 to 4 (1520-N, 1530-N, 1540-N, 1550-N) or the output of the interpolation circuit.

[0249] FIG. 14 is a configuration diagram of a pixel driving circuit according to the sixth embodiment (the first-sixth embodiment) of the first embodiment of the present invention, which includes a plurality of column lines, a plurality of row lines, a plurality of pairs of direct driving pixel circuits (1610-N) and pixels (1620-N), and a plurality of pairs of combination circuits (1610-(N+1)) and pixels (1620-(N+1)).

[0250] In this embodiment, the direct driving pixels are always determined, and it is used when an output image is to be composed through variable driving of the remaining pixels.

[0251] In this way, by reducing the number of voltage pixel driving circuits required for direct driving, the integration level of the entire display pixel circuit can be increased.

[0252]

[0253] Next, we will look at examples of constructing various combinational circuits using direct drive pixel circuits and interpolation circuits.

[0254] Fig. 15 is a block diagram of a first embodiment of a combinational circuit used in the present invention, in which V1 is internally stored by a storage device directly driven by an input, and V2 and V3 are input by receiving voltages of surrounding pixels through an interpolation circuit.

[0255] In addition, the interpolation circuit is a circuit that creates an intermediate voltage using the inputs of V2 and V3, and may have a value other than the intermediate voltage as an output value depending on the purpose.

[0256] Here, V2 and V3 are exemplified as inputs to the interpolation circuit, but cases where there are N inputs, or more than three, are also possible.

[0257] Additionally, the selection circuit can receive the output of the interpolation circuit and the output of the direct drive pixel circuit and output the selected input in response to a selection signal.

[0258] That is, if this is expressed in mathematical formulas, it is as follows: Mathematical Formula 1 and Mathematical Formula 2.

[0259] [Mathematical Formula 1]

[0260]

[0261]

[0262] [Equation 2]

[0263]

[0264]

[0265] Fig. 16 is a block diagram of a second embodiment of a combination circuit used in the present invention, in which the output of a direct drive pixel circuit and the output of an interpolation circuit are applied as inputs to a selection circuit, and the selection circuit selects and outputs one of the two inputs in response to a selection signal.

[0266] At this time, the output voltage is expressed as in the above mathematical expressions 1 and 2.

[0267] Fig. 17 is a block diagram of a third embodiment of a combination circuit used in the present invention, in which the output of a direct drive pixel circuit is selected by the input of a selection circuit, and the selected direct drive pixel circuit output or external input is input to an interpolation circuit.

[0268] It is expressed as in the above mathematical expression 1 and the mathematical expression 3 below.

[0269]

[0270] [Equation 3]

[0271]

[0272]

[0273] Fig. 18 is a block diagram of a fourth embodiment of a combination circuit used in the present invention, in which when the output of the direct drive pixel circuit has a low impedance value (Z1) and the output of the interpolation circuit has a high impedance value (Zi), a switch is placed at the output of the direct drive circuit without an additional selection circuit.

[0274] That is, when the switch (S1) is closed, V1 has low impedance, so the output voltage (V O ) is approximated to V1, and when the switch (S1) is opened, the output voltage (V O ) becomes the output of the interpolation circuit.

[0275] At this time, the output voltage is as shown in the following mathematical expressions 4 and 5.

[0276]

[0277] [Equation 4]

[0278]

[0279]

[0280] [Equation 5]

[0281]

[0282]

[0283] Fig. 19 is a block diagram of a fifth embodiment of a combination circuit used in the present invention. When the interpolation circuit uses a capacitor charge distribution circuit, if the capacitor value is sufficiently lower than the impedance of the direct drive pixel voltage output, the same operation as Fig. 18 is performed.

[0284] Fig. 20 is a block diagram of a sixth embodiment of a combination circuit used in the present invention, which includes a plurality of voltage driving units (1710), an output selection unit (1720), and a voltage-current converter (1750).

[0285] Here, the interpolation unit (1730), voltage driving unit (1710), and output selection unit (1720) within the voltage-current converter form a combination circuit (1740), thereby selecting an input according to the operation of multiple switches (S0 to S3) within the output selection unit.

[0286] That is, when switches (S0, S3) are OFF and switches (S1, S2) are ON, the current output becomes IDATA2, and when switches (S0, S3) are ON and switches (S1, S2) are OFF, the output becomes the interpolated value of IDATA1 and IDATA3.

[0287] At this time, the interpolation value is set to the intermediate value for convenience of understanding, but it is not necessary to have the intermediate value depending on the circuit configuration.

[0288]

[0289] Figures 21a to 21c are photographs comparing the results of actually applying the present invention with the original image and a case using conventional technology.

[0290] (a) is a high-resolution original image, (b) is an output image of an image generator for variable resolution by region using a conventional technique, and (c) is an output image of a display device for variable resolution by region using the present invention.

[0291] As seen in (b), when applying conventional technology, the FOVEAL area has high image quality with the same resolution as the original resolution, while the BLEND area has a resolution slightly lower than the original resolution.

[0292] At this time, conventional display devices do not have a device that can improve this again, so the image quality deteriorates significantly compared to the original as it moves away from the center.

[0293] Additionally, the PERIPHERAL area is an area with very low resolution, and it can be seen that the image quality deteriorates significantly due to resolution degradation.

[0294] On the other hand, as seen in (c), when the present invention is applied, it can be confirmed that the image quality of the BLEND area and the PERIPHERAL area is clearly restored by the interpolation circuit to a degree close to the resolution of the original image.

[0295] By utilizing these features of the present invention, the resolution can be varied according to the area of ​​the user's gaze when wearing virtual reality glasses, augmented reality glasses, etc., thereby efficiently improving the image quality.

[0296] That is, depending on the line of sight of the user wearing the glasses, etc., the center of the line of sight generates an image of the original resolution.

[0297] On the other hand, areas slightly out of the line of sight receive images with variable resolution (e.g., ¼ (½ each on the horizontal and vertical axes)) and improve image quality using interpolation.

[0298] Accordingly, the present invention can adjust the resolution of an image for each region according to the position of the user's gaze when the user's gaze changes.

[0299]

[0300] Pixel circuit and manufacturing method using a capacitor network (second embodiment)

[0301] Meanwhile, semiconductors are made up of a layered structure, and each layer is made up of vias and metal wiring to enable electrical connections.

[0302] The process involves numerous steps, and among them, the metal wiring process is broadly divided into two categories: those that process vias and metal separately, and those that process vias and metal simultaneously. The latter is more difficult than the former and allows for more precise processing.

[0303] Therefore, semiconductor process technology usually becomes a key factor in how small and precisely metals and vias are made.

[0304] Additionally, semiconductor processes are layered and must be electrically connected. This means that there must be no short circuits, so there is always an insulator (dielectric) between each layer.

[0305] Since all layers are metal and insulators exist between them, unwanted capacitors (parasitic capacitors) inevitably form between all layers. Because these unwanted capacitors are a major factor in degrading circuit performance, extensive research is being conducted to reduce them.

[0306] FIG. 22 is a first embodiment of a capacitor network implemented using a capacitor network for the pixel driving circuit of FIG. 6 (Embodiment 1-1) in which all pixels are formed by combinational circuits, wherein multiple pairs of pixel cells composed of a voltage-driven pixel circuit, two capacitors connected in parallel, and a switch are arranged in the vertical and horizontal directions.

[0307] The switch performs an opening and closing operation while being located between the contacts of two capacitors connected in parallel with the voltage-driven pixel circuit.

[0308] That is, each pixel is driven in a direct driving manner when the switch between the pixel electrode and the voltage-driven pixel circuit is turned on, and is driven by the average value of the voltages of the surrounding pixels when the switch is turned off.

[0309] FIG. 23a shows a pixel of a diagonal pixel (Px(n,n)) as a combination circuit of a direct driving pixel circuit and an interpolation circuit (the second embodiment of a capacitor network), and the pixel driving circuit is configured alternately with a combination circuit and an interpolation circuit.

[0310] That is, the direct drive pixel electrode is connected to the voltage drive pixel circuit through a switch, and the interpolation circuit does not include a switch.

[0311] In addition, Fig. 23b shows a pixel of a vertical pixel (Px(n,2k+1)) as a combination circuit of a direct driving pixel circuit and an interpolation circuit (2-2 embodiment of a capacitor network), and the pixel driving circuit is configured alternately with a combination circuit and an interpolation circuit.

[0312] As in Fig. 23a, the direct drive pixel electrode is connected to the voltage drive pixel circuit through a switch, and the interpolation circuit does not include a switch.

[0313] FIG. 24 is a third embodiment of a capacitor network implemented using a capacitor network for the pixel driving circuit of FIG. 10, in which some pixels are formed by super combinational circuits, and includes a voltage-driven pixel circuit, multiple pairs of cells formed by n capacitors and n switches connected in parallel.

[0314] That is, Fig. 24a is an example of a third embodiment of a capacitor network, in which a pixel of a diagonal pixel (Px(n,n)) is a super combination circuit of a direct driving pixel circuit and an interpolation circuit, and the pixel driving circuit is configured alternately with a combination circuit and an interpolation circuit and is arranged in a diagonal direction.

[0315] The pixel electrodes connected to the super combinational circuit operate so that the output of each voltage-driven pixel circuit can directly drive the pixel electrode through a switch.

[0316] FIG. 24b is another example of a third embodiment of a capacitor network, in which multiple pairs of cells each consisting of a voltage-driven pixel circuit, two capacitors connected in parallel with the voltage-driven pixel circuit, and two switches are arranged in a horizontal direction.

[0317] That is, this is an example of a case where the super combinational circuit output is connected to pixels in the horizontal direction, and the same can be applied to the vertical direction.

[0318] FIG. 24c is another example of a third embodiment of a capacitor network, in which the output of one voltage-driven pixel circuit is configured to select each of four adjacent pixel electrodes by each of four switches.

[0319] At this time, for the convenience of understanding, the number of switches and pixel electrodes is exemplified as 4, but 5 or more is also possible.

[0320] Fig. 25 is a plan view (a) and an equivalent circuit (b) for explaining a method of arranging the interpolation circuit arrangement for actually implementing the circuits illustrated in Figs. 24a to 24c in two layers on a semiconductor substrate.

[0321] Fig. 26 is a plan view (a) and an equivalent circuit (b) for explaining a method of arranging the interpolation circuit arrangement for actually implementing the Fig. 24a circuit and the Fig. 24c circuit in two layers on a semiconductor substrate.

[0322] Fig. 27 is a plan view (a) and an equivalent circuit (b) for explaining a method of arranging the interpolation circuit arrangement for actually implementing the Fig. 23b circuit in two layers on a semiconductor substrate.

[0323] Fig. 28 is a cross-sectional view of an interpolation circuit arrangement for actually implementing the circuit of Fig. 23b.

[0324] First, in order to implement the equivalent circuit of Fig. 24b, the first layer is arranged as in the plan view of Fig. 24a, and the second layer is arranged in the form of a pixel electrode on top of the first layer.

[0325] As shown in FIG. 28(a), the first via electrode (2130) is connected to the first layer (2140).

[0326] Also, as seen in Fig. 25(a), pixels at coordinates (1,1), (3,1), (1,3), and (3,3) completely overlap the first layer, so they are driven with the same voltage as the voltage of the first layer through the capacitor.

[0327] On the other hand, pixels at coordinates (1,2), (2,1), (3,2), (2,3) overlap half of the adjacent first layers on the left and right, and thus have the average value of the output values ​​of the first layers on the left and right or above and below.

[0328] Additionally, the pixel at coordinate (2,2) overlaps with the first layer electrodes in the diagonal direction by ¼, so it has the average value of four pixels in the diagonal direction.

[0329] In order to implement the equivalent circuit of Fig. 26(b), the first layer is arranged to overlap the second layer by half in the left and right or top and bottom directions, and the second layer is configured to be directly connected to the output of the voltage-driven pixel circuit or switch through the second VIA (2260) or without connection, as shown in Fig. 28(b).

[0330] When the voltage-driven pixel circuit voltage is connected to the pixel electrode through a switch or direct connection, the driven voltage is output, and when the voltage-driven pixel circuit output is disconnected, the voltage is determined according to the distribution of the surrounding pixels and capacitors.

[0331] In order to implement the equivalent circuit of Fig. 27(a), the first layer is arranged as in the plan view of Fig. 27(a), and the second layer is arranged in the form of a pixel electrode on top of the first layer.

[0332] In addition, in order to implement the equivalent circuit of Fig. 27(b), the first layer is arranged to overlap the second layer by half on the left and right, and the second layer is configured to be directly connected to the output of the voltage-driven pixel circuit or switch through the second via (2260), as shown in Fig. 28(b).

[0333]

[0334] Example 2-1

[0335] Next, a method for manufacturing a pixel circuit according to the first embodiment (2-1 embodiment) of the second embodiment of the present invention will be described with reference to the drawings illustrated in FIGS. 29 to 34.

[0336] FIG. 29 is a process diagram for explaining a method for manufacturing a pixel circuit according to the first embodiment (2-1 embodiment) of the second embodiment of the present invention.

[0337] FIG. 30 is a flowchart for a pixel circuit manufacturing method according to the first embodiment (2-1 embodiment) of the second embodiment of the present invention illustrated in FIG. 29.

[0338] Figure 31 is a process diagram for explaining the detailed process of step (S2120) of the manufacturing method illustrated in Figure 30.

[0339] Figure 32 is a flowchart of the detailed process of step (S2120) of the manufacturing method illustrated in Figure 30.

[0340] Figure 33 is a process diagram for explaining the detailed process of step (S2140) of the manufacturing method illustrated in Figure 30.

[0341] Figure 34 is a flowchart of the detailed process of step (S2140) of the manufacturing method illustrated in Figure 30.

[0342] In process (a) of Fig. 29, a plurality of layers (e.g., first to third pixel circuit output voltage layers (2110)) are separated and formed at a predetermined distance on the substrate (S2110).

[0343] In process (b) of Fig. 29, a first inter-metal dielectric (IMD) (2120) is deposited on the upper surface of the separated pixel circuit output voltage layer (S2121), and a first via (2130) is formed through the via formation process described below (S2120).

[0344] The upper surface of the deposited first intermetallic dielectric (2120) is planarized through CMP.

[0345] Here, the first intermetallic dielectric (2120) includes silicon oxide (SiOx), silicon nitride (SiNx), or the like.

[0346] That is, the following via formation process is performed.

[0347] As shown in Fig. 31(b), among the upper surface areas of the flattened first intermetallic dielectric (2120), only the areas corresponding to the upper surfaces of the first and third pixel circuit output voltage layers (2110) located at both ends are subjected to a photography process using an open photoresist pattern (S2122).

[0348] By performing an etching process and a photoresist removal process, a first intermetal dielectric (2120) is formed in which only the first and third pixel circuit output voltage layers (2110) are exposed among the first intermetal dielectric (2120), as shown in Fig. 31(c) (S2123).

[0349] Next, a first via material (2130) is deposited to cover both the upper surface of the first intermetallic dielectric (2120) and the exposed first and third pixel circuit output voltage layers (2110) (S2124).

[0350] The upper surface of the deposited first via material (2130) is planarized through CMP to expose the first via material (2130) (S2125).

[0351] In addition, the following electrode formation process is performed.

[0352] Among the upper surface areas of the flattened first metal dielectric (2120), the first layer electrode (2140) is laminated so that the lower portion is in contact with the upper surface of the first via material (2130) (S2141).

[0353] That is, as shown in Fig. 29, a metal electrode thin film including a first metal material such as tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al), or copper (Cu) is deposited on the upper surface of the flattened first intermetallic dielectric (2120) and the first via (2130) using a thin film process (e.g., sputtering, deposition process, etc.).

[0354] As shown in Fig. 33(b), a photography process is performed using a photoresist pattern in which only the area corresponding to the upper surface of the first via (2130) is opened (S2142).

[0355] By performing an etching process and a photoresist removal process, only the first metal film in contact with the first via (2130) exposed among the first metal films remains, as shown in Fig. 29(c), thereby forming a first laser electrode (2140) (S2143).

[0356] Next, as shown in Fig. 29(d), a second intermetallic dielectric (2150) is deposited to fill the space between the upper surface of the stacked first layer electrode (2140) and the first layer electrode (2140).

[0357] Additionally, a second via material (2160) penetrating the first intermetal dielectric (2120) and the second intermetal dielectric (2150) is deposited to contact the upper surface of the second pixel circuit output voltage layer (S2160).

[0358] The formation process of the second via (2160) is the same as the formation process of the first via (2130).

[0359] After contacting the upper surface of the second pixel circuit output voltage layer with the second via material (2160), the upper surface of the deposited second via material (2160) is planarized through CMP.

[0360] A second layer electrode (2170) is laminated so that the lower surface of the central portion is in contact with the upper surface of the second via material (2160) (S2170).

[0361] The formation process of the second layer electrode (2170), which is the second metal film, is the same as the formation process of the first layer electrode (2140), which is the first metal film.

[0362] The formation process of the second via (2160) is the same as the formation process of the first via (2130).

[0363] After contacting the upper surface of the second pixel circuit output voltage layer with the second via material (2160), the upper surface of the deposited second via material (2160) is planarized through CMP.

[0364] A second layer electrode (2170) is laminated so that the lower surface of the central portion is in contact with the upper surface of the second via material (2160) (S2170).

[0365] The formation process of the second layer electrode (2170), which is the second metal film, is the same as the formation process of the first layer electrode (2140), which is the first metal film.

[0366]

[0367] Example 2-2

[0368] Next, a method for manufacturing a pixel circuit according to the second embodiment (Embodiment 2-2) of the second embodiment of the present invention will be described with reference to the drawings illustrated in FIGS. 35 and 36.

[0369] FIG. 35 is a process diagram for explaining a manufacturing method of a pixel driving circuit according to the second embodiment (2-2 embodiment) of the second embodiment of the present invention.

[0370] FIG. 36 is a flowchart of a method for manufacturing a pixel driving circuit according to the second embodiment (Embodiment 2-2) of the second embodiment of the present invention.

[0371] In process (a), a plurality of pixel circuit output voltage layers (e.g., first to third pixel circuit output voltage layers (2210)) are separated from each other on the substrate and formed at a predetermined distance (S2210).

[0372] In process (b), a first intermetal dielectric (2220) (Inter-Metal Dielectric, IMD) is deposited on the upper surface of the substrate (S2220).

[0373] The upper surface of the deposited first intermetallic dielectric (2220) is planarized through CMP.

[0374] Among the upper surface areas of the flattened first intermetallic dielectric (2220), a first layer electrode (2240) is formed in an area that does not correspond to the upper surfaces of the first and third pixel circuit output voltage layers (2210) located at both ends, i.e., an area where an imaginary vertical line does not overlap the center of the pixel circuit output voltage layer (2210) (S2230).

[0375] The formation process of the first layer electrode (2240) is the same as the formation process of the first layer electrode (140) of the second embodiment illustrated in FIG. 33, so a detailed description is omitted in this embodiment.

[0376] A second intermetal dielectric (2250) is deposited on the upper surface of the plurality of stacked first layer electrodes (2240) and the upper surface of the exposed first intermetal dielectric (2220) (S2240).

[0377] A plurality of first via materials (2260) penetrating the first intermetal dielectric (2220) and the second intermetal dielectric (2250) are deposited to contact the first to third pixel circuit output voltage layers (2210) (S2250).

[0378] The formation process of the first via (2260) is the same as the formation process of the first via (130) of the second embodiment illustrated in FIG. 29, so a detailed description thereof is omitted in this embodiment.

[0379] The upper surface of the deposited first via material (2260) is planarized through CMP.

[0380] Among the upper surface areas of the flattened second intermetallic dielectric (2250), a second layer electrode (2270) is laminated so that the lower portion is in contact with the upper surface of the first via material (2260) (S2260).

[0381] The formation process of the second layer electrode (2270) is the same as the formation process of the second layer electrode (2170) of the second-1 embodiment illustrated in FIG. 29, so a detailed description thereof is omitted in this embodiment.

[0382]

[0383] Next, a method for manufacturing a pixel circuit according to a third embodiment (Embodiment 2-3) and a fourth embodiment (Embodiment 2-4) of the second embodiment of the present invention will be described with reference to the drawings illustrated in FIGS. 37 to 42.

[0384] FIG. 37 is a process diagram for explaining a method of manufacturing a pixel driving circuit that is commonly used in the third embodiment (Embodiment 2-3) and the fourth embodiment (Embodiment 2-4) of the second embodiment of the present invention.

[0385] FIG. 38 is a process diagram for explaining a manufacturing method of a pixel driving circuit according to the third embodiment (the second-third embodiment) of the second embodiment of the present invention.

[0386] FIG. 39 is a flowchart of a method for manufacturing a pixel driving circuit according to the third embodiment (the second-third embodiment) of the second embodiment of the present invention.

[0387] Figure 40 is a flowchart for the detailed operation of step (S2380) in the second-third embodiment illustrated in Figure 39.

[0388] As shown in Fig. 37(a), a first barrier metal layer (2320), which is a Ti / TiN metal layer that functions as a barrier and adhesive layer, is laminated on the upper surface of the first intermetal dielectric (2310) (IMD).

[0389] A first layer electrode (2330) and a second barrier metal layer (2340) are sequentially laminated on the upper surface of the first barrier metal layer (2320) (S2310).

[0390] At this time, the second barrier metal layer (2340) is an upper Ti / TiN metal layer, which functions as a barrier and antireflection coating.

[0391] Here, the antireflection coating function refers to the role of reducing diffuse reflection during the photography process of creating the shape of the wiring, thereby improving the desired shape.

[0392] Since the above first layer electrode (2330) is manufactured using only a Ti metal process, not a general Al metal process, the thickness can be reduced and the number of process steps can be reduced compared to a conventional first layer electrode, which has the advantage of reducing the manufacturing time and cost of the pixel driving circuit.

[0393] In addition, when the pixel circuit output voltage layer (2335) and the third layer electrode (2460) are connected, a second via (2440) is formed directly on top of the first via (2390) without going through the second layer electrode (2410).

[0394] In addition, the thickness of the second via (2440) is manufactured to a minimum thickness that can be processed using a general via process, and the second intermetal dielectric (2350) uses a material having a higher dielectric constant than a conventional second intermetal dielectric.

[0395] In this case, the vertical distance between the second layer electrode (2410) and the third layer electrode (2460) is reduced and the dielectric constant is increased, which has the effect of increasing the capacitor capacity, and the process of the second layer electrode (2410) is simplified, so that the process cost and process time are significantly reduced.

[0396] As shown in Fig. 37(b), a photography process and an etching process are performed on the stack of the first barrier metal layer (2320), the first layer electrode (2330), and the second barrier metal layer (2340) to perform metal patterning, thereby creating a plurality of metal patterned bodies (S2320).

[0397] As shown in Fig. 37(c), a second intermetal dielectric (2350) is deposited on a portion of the upper surface of a plurality of metal patterning bodies and the upper surface of the first intermetal dielectric (2310) (S2330).

[0398] As shown in Fig. 37(d), a photography process and an etching process are performed on the second intermetal dielectric (2350) to create a first via hole (2360) that penetrates the second intermetal dielectric (2350) and is connected to the upper surface of each of the plurality of metal patterning bodies.

[0399] As shown in Fig. 37(e), after covering the upper surface of the second intermetallic dielectric (2350) and the sidewall of the first via hole (2360) with a third barrier metal layer (2370), a first metal material and a second metal material (2380) are sequentially deposited in the first via hole (2360) to create a plurality of first vias (2390) (S2340).

[0400] At this time, a Ti / TiN metal layer that functions as a barrier and adhesive layer may be used for the first metal material, and tungsten may be used for the second metal material to fill the via well (gap fill).

[0401] As shown in Fig. 37(f), among the deposited first and second metal materials, the materials deposited outside the first via hole (2360) are planarized through an etching process or a CMP process.

[0402] As shown in Fig. 38(b), a second layer electrode (2410) of a thin film is laminated on the flattened upper surface (S2350), the upper surfaces of the first vias that contact the pixel circuit output voltage layer are exposed, and the upper surfaces of the first vias on both sides that do not contact the pixel circuit output voltage layer are metal patterned to be covered with the second layer electrode (2410) of the thin film (S2360, S2370).

[0403] At this time, the second layer electrode (2410) is deposited only using a Ti metal process, not a general Al metal process.

[0404] Through this, the present invention can reduce the thickness of the entire circuit and the number of process steps, thereby reducing manufacturing time and cost, compared to a conventional pixel driver circuit manufacturing method using a general Al metal process.

[0405] Up to this process, the following 2-3 embodiments of the present invention and the 2-4 embodiments described later are identical.

[0406]

[0407] Example 2-3

[0408] The difference in the second-third embodiment of the present invention is that, as shown in Fig. 38(c), a third intermetallic dielectric (2420) is deposited on the upper surface of the result of the process 38(b), and a second via hole is formed that penetrates to the upper surface of the first via exposed to the outside.

[0409] A second via (2440) is created by filling a second via material into the second via hole (S2380), and is planarized through an etching process or a CMP process.

[0410] That is, among the upper surfaces of the first via material, the upper surfaces of the first vias (2390) that do not contact the pixel circuit output voltage layer are metal-patterned (S2381) so that they are covered by the second layer electrode (2410), thereby exposing the upper surfaces of the first vias that contact the pixel circuit output voltage layer.

[0411] As shown in Fig. 38(c), a third intermetal dielectric (2420) is deposited on the upper surface of the second layer electrode (2410), a portion of the second intermetal dielectric (2350), and the upper surface of the exposed first vias (2390) (S2382).

[0412] A second via hole is created that penetrates from a portion of the deposited third intermetallic dielectric that is in contact with the upper surface of the exposed first vias to the upper surface of the third intermetallic dielectric (S2383).

[0413] The sidewall of the second via hole is covered with a third barrier metal layer (2430) (S2384), and the second via hole is filled with a second via material to create a second via (2440) (S2385).

[0414] As shown in Fig. 38(d), a fourth barrier metal layer (2450) and a third layer electrode (2460) are sequentially deposited on the upper surface of the result of the process of Fig. 38(c) (S2390), and a plurality of holes (2470) are created by metal patterning the fourth barrier metal layer (2450) and the third layer electrode (2460) (S2400).

[0415] Accordingly, the third embodiment (the second-third embodiment) of the second embodiment of the present invention has the effect of increasing the capacitor capacity and simplifying the process of the second layer electrode (2410) by reducing the vertical distance between the second layer electrode (2410) and the third layer electrode (2460) compared to the conventional pixel driving circuit, thereby significantly reducing the overall process cost and time.

[0416]

[0417] Example 2-4

[0418] Next, a method for manufacturing a pixel circuit according to the fourth embodiment (the second-fourth embodiment) of the second embodiment of the present invention will be described with reference to the drawings illustrated in FIGS. 37, 41, and 42.

[0419] FIG. 41 is a process diagram for explaining a manufacturing method of a pixel driving circuit according to the fourth embodiment (2-4 embodiment) of the second embodiment of the present invention.

[0420] FIG. 42 is a flowchart of a method for manufacturing a pixel driving circuit according to the fourth embodiment (the second-fourth embodiment) of the second embodiment of the present invention.

[0421] The steps of laminating the first intermetallic dielectric (2310), the first barrier metal layer (2320), the first layer electrode (2330), and the second barrier metal layer (2340) in FIG. 37(a) to the planarizing step in FIG. 37(f) are the same as in the above-described embodiment 2-3, and therefore, a detailed description thereof is omitted here.

[0422] As shown in Fig. 41(c), the 2-4 embodiment of the present invention has a difference from the 2-3 embodiment in that the thickness of the third intermetal dielectric (2425) laminated (S2480) is much smaller than the thickness of the third intermetal dielectric (2420) laminated in the 2-3 embodiment.

[0423] Due to this, the distance between the second layer electrode (2410) and the third layer electrode (2460) is shortened, and the capacitor capacity is increased compared to the second-third embodiment.

[0424] In addition, the second via material (2445) filled in the second via hole is made of the same material as the fourth barrier metal layer (2450), and the two processes are performed simultaneously (S2490), thereby creating multiple holes (2470) by metal patterning the fourth barrier metal layer (2450) and the third layer electrode (2460) (S2500), thereby significantly reducing the overall process time.

[0425]

[0426] Microdisplay device (third embodiment)

[0427] Examples 3-1 and 3-2

[0428] FIG. 43 is a configuration diagram for explaining a direct drive mode of a micro display device according to the first embodiment (embodiment 3-1) of the third embodiment of the present invention, which may include a video input unit (3110), a pixel array driver unit (3120), an array pixel driver circuit (3130), and an array display pixel (3140).

[0429] Since all pixels are directly driven, the resolution of the final display output of the pixel array, i.e., the array display pixels (3140), is the same as the resolution (C x R) of the image input to the video input unit (3110).

[0430] FIG. 44 is a configuration diagram for explaining the x / 2-y / 2 mode of a micro display device according to the second embodiment (the third-2 embodiment) of the third embodiment of the present invention, which may include a video input unit (3210), a pixel compensation preprocessor (3220), a pixel array driving circuit (3230), a resolution converter (3240), a pixel array driving unit (3250), and an array display pixel (3260).

[0431] This is the case where each row and column directly drives two pixels, and the remaining pixels are driven by an interpolation circuit.

[0432] The video input unit (3210) can receive a predetermined video or image to be displayed on the screen.

[0433] For example, the input image may be an image with a resolution of C x R.

[0434] The pixel compensation preprocessor (3220) can preprocess an input image by reflecting the characteristics of capacitor coupling in order to improve the deterioration of image quality due to the average value operation of capacitor coupling.

[0435] Briefly describing the pixel compensation preprocessor (3220), the pixel enhancement technology of the present invention mainly uses a resolution improvement method through average value insertion.

[0436] That is, if the image of the corresponding inserted pixel of the original image is significantly different from the average value, the color of the pixel that determines the image to be inserted is preprocessed so that the image quality becomes similar to the original image within a range that is acceptable for change.

[0437] The resolution converter (3240) can convert the resolution of C x R to the resolution of (C / 2) x (R / 2).

[0438] The pixel array driver (3250) can drive the pixel array at a resolution of (C / 2) x (R / 2).

[0439] The pixel array, i.e., the array display pixel (3260), may be a capacitor-coupled pixel circuit comprising a first pixel circuit that is voltage-driven and a second pixel circuit that is driven through capacitor coupling with the first pixel circuit.

[0440] At this time, capacitor coupling means that in a circuit having multiple pairs of pixel cells composed of a voltage-driven pixel driving circuit, two capacitors connected in parallel, and a switch, each pixel is driven in a direct driving manner when the switch between the pixel electrode and the voltage-driven pixel circuit is turned on, and is driven by an average value or interpolated value of the voltages of surrounding pixels when the switch is turned off.

[0441] As shown in the bottom of Fig. 44, with this operation, it can be seen that the displayed output is divided into 1 / 2 pixels compared to the input image.

[0442]

[0443] Example 3-3

[0444] FIG. 45 is a configuration diagram for explaining a 1 / 4 pixel selection mode of a micro display device according to a third embodiment (3-3 embodiment) of the third embodiment of the present invention, which may include a video input unit (3310), an image pattern detection unit (3320), a pixel compensation preprocessor (3330), a direct drive pixel selection unit (3340), a pixel array driving unit (3350), a pixel driving and interpolation circuit (3360), and an array display pixel (3370).

[0445] In this case, each row and column operates in a direct drive manner with one pixel per 2x2 pixel, but the positions of the direct drive pixels are not arranged regularly, and random positions are selected based on the positions of the pixels, and the remaining pixels are determined by interpolated values.

[0446] In such cases, loss of display information can be minimized by determining the positions of pixels containing particularly important information.

[0447] The video input unit (3310) can receive a predetermined video or image to be displayed on the screen. For example, the input image may be an image having a resolution of C / 2 x R / 2.

[0448] The image pattern detection unit (3320) receives an image with a resolution of C / 2 x R / 2 output from the video input unit (3310) and detects an image pattern.

[0449] The pixel compensation preprocessor (3330) can preprocess the image detected by the image pattern detection unit (3320) by reflecting the characteristics of the capacitor coupling in order to improve the deterioration of image quality due to the average value operation of the capacitor coupling.

[0450] The direct drive pixel selection unit (3340) selects pixels to be directly driven using a direct drive pixel selection algorithm for pixels preprocessed by the pixel compensation preprocessor (3330).

[0451] The pixel driving and interpolation circuit (3360) can drive and interpolate a pixel array with a resolution of (C / 2) x (R / 2) by receiving the direct driving pixels selected from the direct driving pixel selection unit (3340).

[0452] The pixel array, i.e., the array display pixel (3370), receives pixels driven and interpolated from the pixel driving and interpolation circuit (3360) and operates at a resolution of C x R.

[0453] As shown at the bottom of Figure 45, it can be seen that the displayed output is divided into 1 / 2 pixels or 1 / 4 pixels compared to the input image.

[0454]

[0455] Examples 3-4

[0456] FIG. 46 is a configuration diagram for explaining a 1 / n pixel selection mode of a micro display device according to the fourth embodiment (the third-fourth embodiment) of the third embodiment of the present invention, which may include a video input unit (3410), a pixel compensation preprocessor (3420), a driving pixel selector (3430), a pixel array driving circuit (3440), a resolution converter (3450), a pixel array driving unit (3460), a pixel driving and interpolation circuit (3470), and an array display pixel (3480).

[0457] In the case of driving by arbitrarily determining the ratio of the number of direct drive pixels, additional direct drive is performed for pixels containing important information to prevent loss of image quality, and for pixels with a small amount of information, an interpolation circuit is used to obtain optimal driving efficiency.

[0458] The video input unit (3410) can receive a predetermined video or image to be displayed on the screen. For example, the input image may be an image having a resolution of C x R.

[0459] The pixel compensation preprocessor (3420) can preprocess an image input from a video input unit (100) by reflecting the characteristics of capacitor coupling in order to improve the deterioration of image quality due to the average value operation of capacitor coupling.

[0460] The driving pixel selector (3430) selects a pixel to be driven with respect to the pixels preprocessed in the pixel compensation preprocessor (3420).

[0461] The resolution converter (3450) can convert the resolution of C x R to the resolution of (C x R) / n.

[0462] The pixel driving and interpolation circuit (3470) can receive driving pixels whose resolution has been converted from the resolution converter (3450) and drive and interpolate a pixel array with a resolution of (C x R) / n.

[0463] The pixel array, i.e., the array display pixel (3480), receives pixels driven and interpolated from the pixel driving and interpolation circuit (3470) and operates at a resolution of (C x R) / n.

[0464] As shown at the bottom of Figure 46, it can be seen that the displayed output is subdivided into 1 / 2 pixels, 1 / 4 pixels, or 1 / n pixels compared to the input image.

[0465] FIG. 47 is a block diagram of a display system according to one embodiment of the present invention, which includes an image generator (3500), a video transmission unit (3600), and a display device (3700).

[0466] This is to overcome the limitations of the conventional display system illustrated in Fig. 5, which require the use of a transmission line and transmission device with a wide bandwidth, and the limitations of requiring the use of a high-performance display.

[0467] That is, the display system of the present invention transmits the output of the image generator (3500) through the video transmission unit (3600) with a reduced resolution for each area, such as the calculated result (C x R) / r, and inputs it to the display device (3700).

[0468] As shown in Fig. 47, the image generator (3500) receives image data or virtual image object data and an image source, applies a data reduction rate (r) using a foveated rendering method, and generates an image by changing the resolution for each area for pixels reduced by (C x R) / r.

[0469] The video transmission unit (3600) transmits an image of (C x R) / r pixels generated by the image generator (3500) at the same resolution as a conventional display system.

[0470] The display device (3700) can receive an image of (C x R) / r pixels transmitted from the video transmission unit (3600), convert it into an image of C x R pixels, and output it.

[0471] At this time, as seen in the enlarged view in FIG. 47, the amount of drive data of the video data receiving unit (3710), the display time driving unit (3720), and the display pixel driving unit (3730), which are internal components of the display device (3700), is reduced by the data reduction rate (r) and output as (C x R) / r, but the position variable drive interpolation processing pixel unit (3740) ultimately outputs an image of C x R pixels.

[0472] To explain this in more detail, the video data receiving unit receives video data divided by region from the video transmitting unit (600).

[0473] In the case of conventional fixed-resolution display devices, in order to receive a video resolution of C x R, data reception and processing had to be performed at a bit rate calculated as C x R x (number of colors) x (number of bits per color) x FR (frame rate).

[0474] However, in the present invention, the bit rate is sent as a value divided by the pixel reduction rate r to lower the reception transmission rate.

[0475] The display time driving unit (3720) receives video data from the video data receiving unit (3710) and converts the signal according to the timing suitable for the column driving unit and row driving unit of the active matrix method.

[0476] Meanwhile, the time driver of a conventional general display device sequentially transmits video data from the top of the screen at a fixed bit rate according to a fixed resolution.

[0477] On the other hand, since the present invention generates a signal at a data rate that varies for each area, the display pixel driver (3730) stores variable data in the column driver and transmits it to the position variable drive interpolation processing pixel driver (3740).

[0478] In this way, only data corresponding to the directly driven pixels among the pixels of the variable resolution display device (3700) by area is transmitted.

[0479] The data stored in the position variable drive interpolation processing pixel unit (3740) outputs the final C x R pixel image through direct drive and interpolation drive methods.

[0480] Through this, the present invention reduces the bandwidth of the transmission line by the data reduction rate, and makes the up-scaling function that adjusts the output of the image generator (3500) to a high-resolution output unnecessary.

[0481] In addition, the desired display resolution can be obtained at the final stage by using only the position variable drive interpolation processing pixel unit (3740) proposed in the present invention.

[0482] In addition, the interpolation circuit of the present invention can have improved image quality compared to low-resolution images of the prior art by driving the voltage average value of the direct-drive pixels.

[0483] Figure 48 is a conceptual diagram for explaining an image when using a display device for variable resolution by area as shown in Figure 47.

[0484] Depending on the line of sight of the user wearing virtual reality glasses, augmented reality glasses, etc., the center of the line of sight generates an image with the original resolution.

[0485] On the other hand, an area slightly out of sight receives an image with its resolution changed by ¼ (½ each for the horizontal and vertical axes) times, and the display device (3700) uses interpolation to improve the image quality.

[0486] In this way, when the gaze changes, the resolution for each area changes according to the position of the gaze.

[0487] That is, as seen in Fig. 48(a) and Fig. 48(b), when the line of sight is looking at the center and when the line of sight is looking at the edge, the first area (transparent color) in front of the line of sight has no scaling, the second area (dot pattern) that is close to the line of sight has a scaling of 2 times using the spatial interpolation method, and the third area (hatched pattern) that is far away from the line of sight has a scaling of 4 times using the spatial interpolation method.

[0488] Accordingly, by enabling the display device (3700) in the final stage of this embodiment to receive a variable resolution image, the amount of data transmitted and the circuit size of the display device (3700) can be reduced, and the image quality of the display device (3700) can be improved by using an interpolation method.

[0489]

[0490] FIGS. 49a to 49d are drawings for explaining an embodiment of distinguishing each area of ​​a display device for variable resolution by area. FIG. 49a is a diagram of a display device that divides a display screen into 16 x 9 block units, FIG. 49b is a diagram for an example of arranging a driving block in the display device illustrated in FIG. 49a, FIG. 49c is a photograph showing a case where the driving block is divided into blocks in the photograph illustrated in FIG. 21c, and FIG. 49d is a conceptual diagram for controlling the variable resolution of each block area.

[0491] Applying variable resolution to all pixel areas may be the best configuration, but in many cases where there are restrictions due to data transmission methods and circuit configurations, the screen can be reconstructed in block units at an appropriate level, and pixels in the same block can be defined to have inputs with the same resolution.

[0492] That is, as shown in Fig. 49a, the display device of the present invention divides the display screen into 1 x m rectangular block units (e.g., 16 x 9), and uses a different driving method for each block.

[0493] In addition, as shown in Fig. 49b, all pixels are directly driven with 'All Drive' and can be driven by dividing them into a first area (transparent color) that directly receives the original image, a second area (light gray) that is close to the first area and drives each block with a resolution of 1 / 2, 1 / 2, that is, ¼ data, and drives the remaining pixels using an interpolation circuit, and a third area (dark gray) that drives pixels other than the first area and the second area of ​​the display screen with 1 / 4, 1 / 4, that is, 1 / 16 data.

[0494] As a result, as shown in Fig. 49c, when the driving block of Fig. 49b is block-ized in the photograph shown in Fig. 21c, the area of ​​the solid line block represents the resolution of the original image, the area of ​​the dotted line represents ¼ transmission area, and the area of ​​the dashed line represents 1 / 16 transmission area.

[0495] In addition, as seen in Fig. 49d, when no downscaling is performed, when 1 / 2 downscaling is performed, when 1 / 4 downscaling is performed, and when 1 / 16 downscaling is performed, the configuration of the direct drive and interpolation circuit for each area and the variable resolution are controlled differently.

[0496] FIG. 50 is a block diagram of a device implementing a data transmission method of a display device having variable resolution by region, and includes an image generator (3810), an image recombiner (3820), and a display device (3830).

[0497] Additionally, the display device (3830) includes a timing control display driver IC (TCON DDI) (3831), an active matrix pixel circuit (3832), an on-pixel reconstruction unit, and a pixel electrode (3833).

[0498] Since conventional video interface devices do not support variable resolution per region, a new transmission method is required to support video transmission data with variable resolution per region.

[0499] Therefore, the present invention proposes a new method of transmitting video data having variable resolution for each region.

[0500] The region-specific image generated by the image generator (3810) (e.g., application processor) is divided into N video outputs according to the region. For ease of understanding, this example assumes N=3.

[0501] First, the foveal area transmits image data with the same resolution as the original image.

[0502] For example, as shown in Fig. 50, the C1 x R1 region is transmitted to the image recombiner (3820) at its original resolution.

[0503] In this case, the pixel resolution of the foveal area becomes (C3 x R3), which is lower than the resolution of the display device (3830), resulting in a low transmission data rate.

[0504] Additionally, the blend region transmits the C2 x R2 region to the image recombiner (3820) by down-sampling it to a resolution reduced by 1 / K2 for each axis.

[0505] In this case, the pixel resolution is reduced to (C2 / K2) x (R2 / K2), and the amount of video transmission data is also reduced to the value of (C2 / K2) x (R2 / K2).

[0506] In this embodiment, the downsampling values ​​of rows and columns are defined as the same value, but they may be defined as different values.

[0507] Additionally, the peripheral area or background area is down-sampled to a resolution reduced by K1 times per axis in the C x R area and transmitted to the image recombiner (3820).

[0508] That is, the image generator (3810) divides the signal of each region into N regions (e.g., 3), as shown in FIG. 50, and separates each region into three image signals and transmits them through individual transmission lines.

[0509] The display device (3830) receives video data from three separate transmission lines.

[0510] At this time, the display time driver (TCON DDI) stores the signal for each area in the corresponding pixel location of the active matrix pixel circuit (3832).

[0511] The advantages of using individual transmitters and receivers in this way are as follows.

[0512] As shown in Fig. 47, in order to transmit video, the video transmission unit (3600) must transmit and receive using a set protocol, but conventional processors (AP) or video transmission devices have limitations in that they do not support such protocols.

[0513] Accordingly, there are limitations in the use of components to construct an actual display system.

[0514] However, when the present invention is applied, a conventional video transmission method is used as is, and by using a method of increasing the transmission channel, a general processor (AP, GPU, etc.) video transmission device can be used.

[0515] Accordingly, the present invention enables connection of a variable resolution display device for each area without changing a conventional video transmitter.

[0516] Figure 51 is a conceptual diagram for explaining the interrelationship between outputs of each component of a device implementing the data transmission method illustrated in Figure 50.

[0517] The original image is divided into three areas: a foveal image, a blend image, and a background image, and these are input to an image recombiner (3820) using three video transmission lines, the first to third lanes.

[0518] The image recombiner (3820) stores data in the form of an image with variable resolution for each region, and then transmits it to a variable resolution display device (3830) for output.

[0519] That is, as seen in FIG. 50, the foveal image maintains a resolution of (C3 x R3) in all of the image generator (3810), the image recombiner (3820), and the display device (3830).

[0520] On the other hand, the blended image is input to the image recombiner (3820) with the resolution reduced by K2 times (e.g., K2 = 2) from (C2 x R2) in the image generator (3810) to (C2 / K2) x (R2 / K2), and is input to the variable resolution display device (3830) for each area to K2. 2 It is then converted back to (C2 x R2), which is a resolution that has been increased by a factor of 2, and output.

[0521] In addition, the background image is input to the image recombiner (3820) as (C / K1) x (R / K1) with the resolution reduced by K1 times (e.g., K1 = 4) from the original image which was (C x R) in the image generator (3810), and is input to the image recombiner (3820) as K1 in the variable resolution display device (3830) by region. 2 It is then converted back to (C x R), which is the resolution of the original image that has been increased by a factor of 1, and output.

[0522]

[0523] In this way, the present invention provides a pixel driving circuit that can implement variable resolution for each area by using a direct drive mode for areas that have a significant impact on image quality and an interpolation mode for areas that have a relatively less impact.

[0524] In addition, the present invention provides a pixel circuit capable of simultaneously implementing a pixel electrode and a capacitor by adopting a multilayer structure using a capacitor, which is a passive element that can be implemented in an intermediate layer in a semiconductor process.

[0525] In addition, the present invention provides a micro display device and a display system including the same, which can improve the picture quality of a display device and reduce the amount of data transmission and the circuit capacity of an implementation means by generating an image whose resolution changes according to a person's gaze using a variable resolution display device for each area.

[0526] Through this, the present invention can change the setting of the driving mode according to the input conditions or input time of the display device, thereby optimizing the image quality of the input image, the bandwidth of the system, and the power consumption.

[0527] Additionally, the resolution can be varied according to the area of ​​focus of the user wearing virtual reality glasses, augmented reality glasses, etc., to efficiently improve image quality.

[0528] In addition, by reducing the number of voltage pixel driving circuits required for direct driving, the integration level of the entire display pixel circuit can be increased.

[0529] Additionally, when the user's gaze changes, the resolution of the image can be adjusted for each area depending on the position of the gaze.

[0530] In addition, by implementing a capacitor network circuit for creating a combinational circuit in a voltage-driven manner and arranging multiple layers in an overlapping manner, an interpolation circuit network can be constructed without separate wiring.

[0531] In addition, the area of ​​the pixel circuit can be minimized by implementing the capacitor in the intermediate layer without having to implement the circuit that drives the data of each pixel and the interpolation circuit on the same plane.

[0532] In addition, the capacity of the capacitor in the pixel circuit using the capacitor network can be increased, thereby improving and enhancing the performance of the pixel circuit, and the cost and time required for the manufacturing process can be significantly reduced by reducing the additional process for manufacturing the pixel circuit.

[0533] In addition, in order to generate high-resolution images, a large amount of calculations are required, and in the case of games and graphic playback that require high performance and power consumption of the processor, by generating images by varying the resolution by area, the required amount of calculations and memory can be reduced, and efficient power consumption can be achieved.

[0534] In addition, by using only the position variable drive interpolation processing pixel part, the desired display resolution can be obtained in the final stage, and by driving the average value of the voltage of the directly driven pixel, an improved image quality can be obtained compared to the low resolution image of the conventional technology.

[0535] In addition, it is possible to connect a variable resolution display device by area without changing the conventional video transmitter.

[0536]

[0537] The method for manufacturing a pixel circuit according to the present invention may be implemented in the form of program commands that can be executed by various computer means and recorded on a computer-readable medium. The computer-readable recording medium may include program commands, data files, data structures, etc., alone or in combination. The program commands recorded on the medium may be those specifically designed and configured for the present invention or may be those known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and hardware devices specifically configured to store and execute program commands, such as ROMs, RAMs, and flash memories. Examples of program commands include not only machine language codes generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter, etc. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

[0538] In addition, although the above description focuses on examples, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present invention. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. Multiple column lines; A plurality of row lines wired in a direction orthogonal to the plurality of column lines; A plurality of cells generated by intersecting the plurality of column lines and the plurality of row lines; and A combination circuit positioned in each of the plurality of cells and connected to each of the plurality of column lines and each of the plurality of row lines; Including, Characterized in that an image having the same resolution as the original resolution and a variable resolution is output by the above combination circuit. Pixel driving circuit that implements variable resolution by area.

2. In paragraph 1, The above combination circuit is, Direct drive pixel circuit; An interpolation circuit that interpolates and outputs pixel output of the peripheral area; and A selection circuit that receives the output of the above direct drive pixel circuit and the output of the above interpolation circuit and selects and outputs them in response to a selection signal; characterized by including, Pixel driving circuit that implements variable resolution by area.

3. Multiple column lines; A plurality of row lines wired in a direction orthogonal to the plurality of column lines; and A plurality of cells generated by intersecting the plurality of column lines and the plurality of row lines; Unit cells including a direct drive mode cell composed of a combination circuit and a pixel and an interpolation mode cell composed of an interpolation circuit and a pixel and located to the right of the direct drive mode cell are arranged in a horizontal and vertical direction, Depending on the degree of influence on image quality and proximity to the original data resolution, the direct drive mode or the interpolation mode is selectively used. Characterized in that an image having the same resolution as the original resolution and a variable resolution is output by the interpolation mode cell. Pixel driving circuit that implements variable resolution by area.

4. In paragraph 3, The above combination circuit is, Direct drive pixel circuit; An interpolation circuit that interpolates and outputs pixel output of the peripheral area; and A selection circuit that receives the output of the above direct drive pixel circuit and the output of the above interpolation circuit and selects and outputs them in response to a selection signal; characterized by including, Pixel driving circuit that implements variable resolution by area.

5. In paragraph 3, The above combination circuit is, Direct drive pixel circuit; A first selection circuit that receives the output of the above direct drive pixel circuit and the first input and selects and outputs in response to a first selection signal; A second selection circuit that receives the output of the above direct drive pixel circuit and the second input and selects and outputs in response to a second selection signal; and An interpolation circuit that receives the outputs of the first and second selection circuits, interpolates them, and outputs them; characterized in that it includes: Pixel driving circuit that implements variable resolution by area.

6. In paragraph 3, The above combination circuit is, Direct drive pixel circuit; High impedance interpolation circuit; and A switch having one side connected to the output terminal of the direct drive pixel circuit to form a low impedance; Characterized in that the output of the direct drive pixel circuit or the output value of the high impedance interpolation circuit is output according to the opening and closing of the switch. Pixel driving circuit that implements variable resolution by area.

7. In paragraph 3, The above combination circuit is, Nth voltage drive unit; An output selection unit that receives two outputs from the Nth voltage driving unit and performs a first switch, and receives outputs from the N-1th voltage driving unit and the N+1th voltage driving unit and performs a second switch; and An interpolation unit that receives output from the above output selection unit, calculates an interpolation value, and outputs it; characterized by including, Pixel driving circuit that implements variable resolution by area.

8. Multiple column lines; A plurality of row lines wired in a direction orthogonal to the plurality of column lines; and A plurality of cells generated by intersecting the plurality of column lines and the plurality of row lines; Among the above multiple cells, if (column, row) = (odd, odd) or (even, even), it is composed of super combination mode cells in a diagonal direction, and in the remaining cases, it is composed of interpolation mode cells. Characterized in that an image having the same resolution as the original resolution and a variable resolution is output by the interpolation mode cell. Pixel driving circuit that implements variable resolution by area.

9. Multiple column lines; A plurality of row lines wired in a direction orthogonal to the plurality of column lines; and A plurality of cells generated by intersecting the plurality of column lines and the plurality of row lines; Among the above multiple cells, the direct drive position is selected as a pixel in the vertical direction and is sequentially configured as a super combination mode cell, Characterized in that the super combination mode cell outputs an image having the same resolution as the original resolution and a variable resolution. Pixel driving circuit that implements variable resolution by area.

10. Multiple column lines; A plurality of row lines wired in a direction orthogonal to the plurality of column lines; and A plurality of cells generated by intersecting the plurality of column lines and the plurality of row lines; By selecting 2N pixels (N is an integer greater than or equal to 2) as a direct drive pixel circuit among the above-mentioned multiple cells, the cells are sequentially configured as super combination mode cells. Characterized in that the super combination mode cell outputs an image having the same resolution as the original resolution and a variable resolution. Pixel driving circuit that implements variable resolution by area.

11. Multiple column lines; A plurality of row lines wired in a direction orthogonal to the plurality of column lines; and A plurality of cells generated by intersecting the plurality of column lines and the plurality of row lines; Among the above multiple cells, even rows and even columns are composed of combination mode cells, and the rest are composed of direct drive mode cells. Characterized in that the above combination mode cell outputs an image having the same resolution as the original resolution and a variable resolution. Pixel driving circuit that implements variable resolution by area.

12. In a pixel circuit that forms a plurality of pixel cells in the vertical and horizontal directions using a capacitor network, the pixel driving circuit is composed entirely of combinational circuits. Each of the above plurality of pixel cells A voltage-driven pixel circuit connected to each of a plurality of pixel electrodes; First and second capacitors each positioned between two pixel electrodes among the plurality of pixel electrodes and connected in parallel with the voltage-driven pixel circuit; and A switch configured to switch while being positioned between the voltage-driven pixel circuit and the plurality of pixel electrodes; The voltage-driven pixel circuit is characterized in that it is driven in a direct driving manner or an interpolation manner depending on whether the switch is turned on. Pixel circuit using a capacitor network.

13. In paragraph 12, The above voltage-driven pixel circuit, Multiple column lines; A plurality of row lines wired in a direction orthogonal to the plurality of column lines; A plurality of cells generated by intersecting the plurality of column lines and the plurality of row lines; and A combination circuit positioned in each of the plurality of cells and connected to each of the plurality of column lines and each of the plurality of row lines; Including, The combination circuit outputs an image having the same resolution as the original resolution and a variable resolution, thereby restoring image quality in a required area. Pixel circuit using a capacitor network.

14. In paragraph 13, The above combination circuit is, Direct drive pixel circuit; An interpolation circuit that interpolates and outputs pixel output of the peripheral area; and A selection circuit that receives the output of the above direct drive pixel circuit and the output of the above interpolation circuit and selects and outputs them in response to a selection signal; characterized by including, Pixel circuit using a capacitor network.

15. In paragraph 13, The above direct drive pixel circuit, Defines the pixel that receives a data input signal, stores a value corresponding to the pixel's data, and directly drives it in the form of voltage or current. The above pixel is connected to the combination circuit and outputs pixel data according to an external control signal or outputs a data value calculated from the pixel output of the periphery. Pixel circuit using a capacitor network.

16. In a pixel circuit that forms a plurality of pixel cells in a diagonal direction and a vertical direction using a capacitor network, a pixel driving circuit composed of a combinational circuit, Each of the above plurality of pixel cells Voltage-driven pixel circuit; First and second capacitors connected in parallel with the voltage-driven pixel circuit while positioned between a plurality of pixel electrodes; and A switch that is switched and located between the voltage-driven pixel circuit and the pixel electrode; The above combination circuit includes a direct drive pixel circuit and an interpolation circuit, The voltage-driven pixel circuit is characterized in that it is driven by a direct driving method or an average voltage value of surrounding pixel electrodes depending on whether the switch is turned on. Pixel circuit using a capacitor network.

17. In paragraph 16, The above voltage-driven pixel circuit, Multiple column lines; A plurality of row lines wired in a direction orthogonal to the plurality of column lines; and A plurality of cells generated by intersecting the plurality of column lines and the plurality of row lines; Unit cells including a direct drive mode cell composed of a combination circuit and a pixel and an interpolation mode cell composed of an interpolation circuit and a pixel and located to the right of the direct drive mode cell are arranged in a horizontal and vertical direction, Characterized in that the direct drive mode or the interpolation mode is selectively used depending on the degree of influence on the image quality and the proximity to the original data resolution. Pixel circuit using a capacitor network.

18. In paragraph 17, The above combination circuit is, Direct drive pixel circuit; An interpolation circuit that interpolates and outputs pixel output of the peripheral area; and A selection circuit that receives the output of the above direct drive pixel circuit and the output of the above interpolation circuit and selects and outputs them in response to a selection signal; characterized by including, Pixel circuit using a capacitor network.

19. In paragraph 17, The above combination circuit is, Direct drive pixel circuit; A first selection circuit that receives the output of the above direct drive pixel circuit and the first input and selects and outputs in response to a first selection signal; A second selection circuit that receives the output of the above direct drive pixel circuit and the second input and selects and outputs in response to a second selection signal; and An interpolation circuit that receives the outputs of the first and second selection circuits, interpolates them, and outputs them; characterized in that it includes: Pixel circuit using a capacitor network.

20. In paragraph 17, The above combination circuit is, Direct drive pixel circuit; High impedance interpolation circuit; and A switch having one side connected to the output terminal of the direct drive pixel circuit to form a low impedance; Characterized in that the output of the direct drive pixel circuit or the output value of the high impedance interpolation circuit is output according to the opening and closing of the switch. Pixel circuit using a capacitor network.

21. In a pixel circuit that forms a plurality of pixel cells in a diagonal, horizontal or vertical direction using a capacitor network, a pixel driving circuit composed of a super combinational circuit, Each of the above plurality of pixel cells A voltage-driven pixel circuit connected to each of a plurality of pixel electrodes in a diagonal, horizontal or vertical direction; First and second capacitors each positioned between two pixel electrodes among the plurality of pixel electrodes and connected in parallel with the voltage-driven pixel circuit; A first switch that switches while being positioned between the voltage-driven pixel circuit and the first pixel electrode among the plurality of pixel electrodes in the diagonal, horizontal or vertical direction; and The voltage-driven pixel circuit comprises a second switch that switches while being positioned between the first pixel electrode and a second pixel electrode that is adjacent in a diagonal direction, a horizontal direction, or a vertical direction; The above super combinational circuit includes a direct drive pixel circuit and multiple interpolation circuits, The voltage-driven pixel circuit is characterized in that it is driven in a direct driving manner or an interpolation manner depending on whether the first and second switches are turned on. Pixel circuit using a capacitor network.

22. In paragraph 21, The above voltage-driven pixel circuit, Multiple column lines; A plurality of row lines wired in a direction orthogonal to the plurality of column lines; and A plurality of cells generated by intersecting the plurality of column lines and the plurality of row lines; Among the above multiple cells, (column, row) = (odd, odd) or (even, even) and are characterized in that they are composed of super combination mode cells in a diagonal direction, and the remaining cases are composed of interpolation mode cells. Pixel circuit using a capacitor network.

23. In paragraph 22, The above super combination mode cell is composed of a super combination circuit and first and second pixels, The above interpolation mode cell is composed of an interpolation circuit and pixels. Pixel circuit using a capacitor network.

24. In a method for manufacturing a pixel circuit that forms a plurality of pixel cells in a horizontal direction using a capacitor network, a pixel driving circuit comprising a part of a super combinational circuit, (a) A step of forming a plurality of pixel circuit output voltage layers separately on a substrate; (b) a step of depositing a first intermetallic dielectric on the upper surface of the substrate, forming a first via hole, and creating a first via (130) to form a pixel driver circuit substrate; (c) a step of stacking a first layer electrode on the upper surface of the pixel driving circuit substrate, and removing the central portion of the first layer electrode corresponding to the pixel circuit output voltage layer located in the center among the plurality of pixel circuit output voltage layers; (d) a step of depositing a second intermetal dielectric on the upper surface of the first layer electrode laminated above and the upper surface of the first intermetal dielectric exposed by the removal; (e) a step of creating a second via (160) that penetrates the first and second intermetal dielectrics and is connected to the pixel circuit output voltage layer at the center; and (f) a step of laminating a second layer electrode covering the upper surface of the second intermetallic dielectric and the upper surface of the second via; characterized by including, A method for manufacturing a pixel circuit using a capacitor network.

25. In paragraph 24, In step (b) above, The above first via, A step of performing a photography process on an area corresponding to the upper surface of a pixel circuit output voltage layer located at both ends among the upper surface areas of the first intermetallic dielectric; A step of forming the first via hole exposing only the upper surface of the pixel circuit output voltage layer located at both ends through an etching process; A step of filling a first via material into the first via hole; and A step of flattening the upper surface of the filled first via material to expose only the first via material that contacts the upper surface of the pixel circuit output voltage layer located at both ends; characterized by being formed through, A method for manufacturing a pixel circuit using a capacitor network.

26. In a method for manufacturing a pixel circuit that forms a plurality of pixel cells in a horizontal direction using a capacitor network, a pixel driving circuit comprising a part of a super combinational circuit, (a) A step of forming a plurality of pixel circuit output voltage layers separately on a substrate; (b) a step of depositing a first intermetallic dielectric on the upper surface of the substrate; (c) a step of forming a first layer electrode in an area where the center of an imaginary vertical line on the upper surface of the first intermetallic dielectric deposited above does not overlap with the pixel circuit output voltage layer; (d) a step of depositing a second intermetallic dielectric that fills the upper surface of the first layer electrode formed above and the space created by forming a plurality of first layer electrodes; (e) a step of creating a plurality of first vias (260) that penetrate the first and second intermetal dielectrics and are connected to each of the plurality of pixel circuit output voltage layers; and (f) a step of laminating a second layer electrode on the upper surface of the second intermetallic dielectric and the upper surface of the plurality of first vias (260); (g) a step of creating a plurality of holes by metal patterning a portion of the second layer electrode corresponding to the first layer electrode in a vertical line; characterized by including, A method for manufacturing a pixel circuit using a capacitor network.

27. In a method for manufacturing a pixel circuit that forms a plurality of pixel cells in a horizontal direction using a capacitor network, a pixel driving circuit comprising a part of a super combinational circuit, (a) a step of sequentially stacking a first barrier metal layer, a first layer electrode, and a second barrier metal layer on the upper surface of a first intermetallic dielectric, and performing metal patterning to create a plurality of metal patterned bodies; (b) depositing a second intermetallic dielectric, creating a plurality of first vias penetrating the second intermetallic dielectric, and laminating a second layer electrode; (c) a step of metal patterning so that a second layer electrode covers the upper surface of the first vias that do not contact the pixel circuit output voltage layer, and exposes the upper surface of the first vias that contact the pixel circuit output voltage layer; (d) depositing a third intermetallic dielectric and creating a second via extending from the exposed first vias; and (e) a step of stacking a third layer electrode and metal patterning to create a plurality of holes; characterized by including, A method for manufacturing a pixel circuit using a capacitor network.

28. In paragraph 27, Between steps (a) and (b), and between steps (d) and (e), Step of flattening the exposed upper surface; characterized by further including, A method for manufacturing a pixel circuit using a capacitor network.

29. In paragraph 27, Step (b) above, A step of creating a plurality of first via holes that penetrate the second intermetallic dielectric and connect to the upper surface of each of the plurality of metal patterning bodies; and A step of covering the sidewalls of each of the plurality of first via holes with a third barrier metal layer and filling the plurality of first via holes with a first via material; characterized by further including, A method for manufacturing a pixel circuit using a capacitor network.

30. In paragraph 29, Step (c) above, A step of depositing the second intermetal dielectric on the upper surface of the plurality of metal patterning bodies and the exposed upper surface of the first intermetal dielectric; and A step of metal patterning the upper surfaces of the first vias among the upper surfaces of the first via material so that the upper surfaces of the first vias that do not contact the pixel circuit output voltage layer are covered by the second layer electrode, and exposing the upper surfaces of the first vias that contact the pixel circuit output voltage layer; characterized by further including, A method for manufacturing a pixel circuit using a capacitor network.

31. In paragraph 30, Step (d) above, A step of metal patterning so that the upper surfaces of the first vias among the upper surfaces of the first via material, which do not contact the pixel circuit output voltage layer, are covered by the second layer electrode, thereby exposing the upper surfaces of the first vias that contact the pixel circuit output voltage layer; A step of depositing a third intermetal dielectric on the upper surface of the second layer electrode, a portion of the second intermetal dielectric, and the upper surface of the exposed first vias; A step of creating a second via hole penetrating from a portion of the deposited third intermetal dielectric in contact with the upper surface of the exposed first vias to the upper surface of the third intermetal dielectric; and A step of covering the sidewall of the second via hole with the third barrier metal layer and filling the second via hole with a second via material; characterized by further including, A method for manufacturing a pixel circuit using a capacitor network.

32. In paragraph 31, Step (e) above, A step of sequentially stacking a fourth barrier metal layer and the third layer electrode on the upper surface of the third intermetallic dielectric and the upper surface of the second via material; and Characterized in that, through the metal patterning, the plurality of holes are created in the fourth barrier metal layer and the third layer electrode portion corresponding to the upper surface of the first vias that do not contact the pixel circuit output voltage layer. A method for manufacturing a pixel circuit using a capacitor network.

33. In paragraph 27, The first to fourth barrier metal layers are, characterized by a Ti / TiN metal layer, A method for manufacturing a pixel circuit using a capacitor network.

34. In paragraph 27, The above first via material is, characterized by being tungsten, A method for manufacturing a pixel circuit using a capacitor network.

35. A program for performing on a computer a method for manufacturing a pixel circuit using a capacitor network as described in any one of Articles 27 to 34, A computer-readable recording medium for a method of manufacturing a pixel circuit using a capacitor network.

36. In a method for manufacturing a pixel circuit using a capacitor network described in any one of claims 27 to 34, Characterized in that the thickness of the third intermetallic dielectric is reduced, thereby increasing the capacitor capacity between the second electrode layer and the third electrode layer. A method for manufacturing a pixel circuit using a capacitor network.

37. In a method for manufacturing a pixel circuit using a capacitor network described in any one of claims 27 to 34, The material of the fourth barrier metal layer is characterized by being the same as the material of the second via material. A method for manufacturing a pixel circuit using a capacitor network.

38. A display system including a combination circuit connected to each of a plurality of column lines and each of a plurality of row lines, and a pixel circuit having pixels connected to the combination circuit, and outputting an image having a resolution variably converted by the combination circuit, An image generator that receives image data and an image source as input and generates an image by changing the resolution by region for pixels reduced by a factor of 1 / r (r: data reduction rate); A video transmission unit that transmits the image of the above-mentioned generated 1 / r-fold pixels at the same resolution; and A display device that receives the image of the 1 / r-fold pixel transmitted above, converts it into an image of r-fold pixel, and outputs it; The above change in resolution by region is characterized in that the resolution of the pixel region changes depending on the position of the gaze when the user's gaze changes. Display system.

39. In paragraph 38, The above display device, A video data receiving unit that receives video data divided by region from the above video transmitting unit; A display timing driver that receives the video data from the video data receiving unit and converts the signal according to timing suitable for the column driver and row driver of the active matrix type; A display pixel driver that receives the converted signal and stores variable data in the column driver; and A pixel unit for position variable drive interpolation processing that receives the stored variable data and outputs a pixel image with a final resolution through a direct drive and interpolation drive method; characterized in that it includes; Display system.

40. In paragraph 38, The above image generator, A method characterized in that the resolution is changed for pixels reduced by the 1 / r factor by applying the data reduction rate (r) in the foveated rendering method. Display system.

41. A display system comprising a combination circuit connected to each of a plurality of column lines and each of a plurality of row lines, and a pixel circuit having pixels connected to the combination circuit, and outputting an image having a resolution variably converted by the combination circuit, An image generator that receives image data and an image source as input, divides the image into N images by changing the resolution for each region for pixels reduced by a factor of 1 / r, and outputs the images; An image recombiner that receives and outputs images with the same resolution, a resolution reduced by 1 / K2 times for each axis, and a resolution reduced by K1 times for each axis for each of the N images divided above; and A display device that receives the recombined image and outputs it with the changed resolution; The above change in resolution by region is characterized in that the resolution of the pixel region changes depending on the position of the gaze when the user's gaze changes. Display system.

42. In paragraph 41, The above image generator, For the foveal area, image data is transmitted so that it has the same resolution as the original image, For the blend area, the image is down-sampled and transmitted with a resolution reduced by 1 / K2 times for each axis using the image recombiner. For the peripheral area or background area, it is characterized in that the image is down-sampled and transmitted with a resolution reduced by K1 times for each axis by the image recombiner. Display system.

43. A display system comprising a combination circuit connected to each of a plurality of column lines and each of a plurality of row lines, and first and second pixel circuits having pixels connected to the combination circuits, and outputting an image having a resolution that is variably changed by the combination circuits, A video input unit that receives the video to be displayed on the screen; a pixel driving circuit for driving the pixel at the converted resolution; and A capacitor-coupled pixel array comprising a first pixel circuit driven by voltage and a second pixel circuit driven through capacitor coupling with the first pixel circuit; Including, Characterized in that the resolution of the final display output of the pixel array is the same as the resolution of the image input to the video input unit. Microdisplay device.

44. A display system comprising a combination circuit connected to each of a plurality of column lines and each of a plurality of row lines, and a pixel circuit having pixels connected to the combination circuit, and outputting an image having a resolution variably converted by the combination circuit, A video input unit that receives the video to be displayed on the screen; A pixel compensation preprocessor that receives the input image and preprocesses it to reflect the characteristics of capacitor coupling; A resolution converter that converts the resolution of the above-mentioned preprocessed image to half the resolution; and A pixel driving circuit for driving the pixel at the converted resolution; Including, Depending on whether the switch connecting the pixel driving circuit and the output terminal is turned on, it is characterized in that it is driven in a direct driving manner or an interpolation manner. Microdisplay device.

45. A display system comprising a combination circuit connected to each of a plurality of column lines and each of a plurality of row lines, and a pixel circuit having pixels connected to the combination circuit, and outputting an image having a resolution variably converted by the combination circuit, A video input unit that receives the video to be displayed on the screen; An image pattern detection unit that receives an image having a first resolution output from the video input unit and detects an image pattern; A pixel compensation preprocessor that preprocesses an image in which the above image pattern is detected by reflecting the characteristics of capacitor coupling; A direct driving pixel selection unit that selects pixels to be directly driven using a direct driving pixel selection algorithm for the above preprocessed pixels; A resolution converter that converts the resolution of the selected pixels to a resolution half the first resolution; A pixel driving and interpolation circuit for driving and interpolating the pixels at the converted resolution; and An array of pixels that receives the above driven and interpolated pixels and operates at a resolution twice that of the first resolution; Including, Depending on whether the switch connecting the pixel driving and interpolation circuit and the output terminal is turned on, it is characterized in that it is driven in a direct driving manner or an interpolation manner. Microdisplay device.

46. ​​A display system including a combination circuit connected to each of a plurality of column lines and each of a plurality of row lines, and a pixel circuit having pixels connected to the combination circuit, and outputting an image having a resolution variably converted by the combination circuit, A video input unit that receives the video to be displayed on the screen; A pixel compensation preprocessor that preprocesses the input image by reflecting the characteristics of capacitor coupling; A driving pixel selector for selecting a pixel to be driven for the above preprocessed pixels; A resolution converter that converts the resolution of the selected pixels to a resolution 1 / n times higher; A pixel driving and interpolation circuit for driving and interpolating the pixels at the converted resolution; and An array display pixel that operates at a resolution of 1 / n times by receiving the above driven and interpolated pixels; Including, Depending on whether the switch connecting the pixel driving and interpolation circuit and the output terminal is turned on, it is characterized in that it is driven in a direct driving manner or an interpolation manner. Microdisplay device.

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