Driving backplane, light-emitting substrate, display panel, and display apparatus

Abstract

The present disclosure belongs to the technical field of displays. Provided are a driving backplane (DBP), a light-emitting substrate, a display panel, and a display apparatus. The driving backplane (DBP) comprises a first substrate (BPA), a thick copper layer (CL), a second substrate (BPB) and a driving layer (DRL), which are sequentially arranged in a stacked manner, wherein the thick copper layer (CL) is provided with a driving wiring for loading a driving signal; and the driving layer (DRL) is provided with a driving circuit (PDC), the driving circuit (PDC) being electrically connected to the driving wiring by means of a via hole. By means of the driving backplane (DBP), the manufacturing yield of the driving backplane (DBP) can be improved. (FIG. 1)

Description

Driving backplane, light-emitting substrate, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving backplane, a light-emitting substrate, a display panel, and a display device. Background Art

[0002] Micro LEDs (micro light-emitting diodes) are characterized by their small size, high integration, and self-luminescence. Compared with display technologies such as LCDs (liquid crystal displays) and OLEDs (organic electroluminescent displays), Micro LED direct displays offer significant advantages in brightness, resolution, contrast, energy consumption, lifespan, response speed, and thermal stability.

[0003] Micro LED display panels typically feature a thick copper layer, which can be used to form signal traces to reduce the voltage drop of the driving signal. This layer is typically placed above the thin-film transistors, significantly impacting the subsequent manufacturing process of the display panel.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0005] Summary of the Invention

[0006] The purpose of the present disclosure is to overcome the deficiencies of the above-mentioned prior art, provide a driving backplane, a light-emitting substrate, a display panel and a display device, and improve the manufacturing yield of the driving backplane.

[0007] According to a first aspect of the present disclosure, a driving backplane is provided, comprising a first substrate, a thick copper layer, a second substrate and a driving layer stacked in sequence; wherein the thick copper layer is provided with a driving trace for loading a driving signal; the driving layer is provided with a driving circuit, and the driving circuit is electrically connected to the driving trace through a via.

[0008] According to an embodiment of the present disclosure, the second substrate includes a second polyimide layer covering the thick copper layer and a second inorganic barrier layer provided on a side of the second polyimide layer away from the first substrate.

[0009] According to one embodiment of the present disclosure, the thickness of the second polyimide layer is greater than the thickness of the thick copper layer.

[0010] According to one embodiment of the present disclosure, the thickness of the thick copper layer is between 0.2 and 20 microns.

[0011] According to an embodiment of the present disclosure, the first substrate includes a first polyimide layer and a first inorganic barrier layer that are stacked, and the thick copper layer is provided on a surface of the first inorganic barrier layer away from the first polyimide layer.

[0012] According to one embodiment of the present disclosure, the driving layer includes a transistor layer, an interlayer dielectric layer and a source-drain metal layer stacked in sequence on the side of the second substrate away from the first substrate; the source-drain metal layer is directly or indirectly electrically connected to the thick copper layer through vias.

[0013] According to an embodiment of the present disclosure, the driving trace includes a driving voltage trace for applying a driving voltage and a reference voltage trace for applying a reference voltage;

[0014] The source-drain metal layer is provided with a first device pad, a second device pad, a first connection structure and a second connection structure;

[0015] In which, the driving circuit is electrically connected to the first connection structure, and the first connection structure is electrically connected to the driving voltage line; the first device pad is electrically connected to the output end of the driving circuit; the second device pad is electrically connected to the second connection structure, and the second connection structure is electrically connected to the reference voltage line.

[0016] According to one embodiment of the present disclosure, the transistor layer includes transistors; at least some of the transistors have a top gate and a bottom gate, and the top gate and the bottom gate of the transistor are electrically connected through the source-drain metal layer.

[0017] According to one embodiment of the present disclosure, a transfer pad is provided on the driving backplane between the source-drain metal layer and the thick copper layer; a first portion of the transfer pad is electrically connected to the thick copper layer through a via; and a second portion of the transfer pad is electrically connected to the source-drain metal layer through a via.

[0018] According to one embodiment of the present disclosure, the driving backplane further comprises a transfer layer and a third inorganic barrier layer stacked in sequence on a side of the second substrate away from the first substrate; the transistor layer is provided on a side of the third inorganic barrier layer away from the first substrate;

[0019] The transfer pad is arranged on the transfer layer.

[0020] According to one embodiment of the present disclosure, the transistor layer includes a semiconductor layer; the semiconductor layer includes a channel structure and a semiconductor conductive structure;

[0021] Wherein, at least part of the channel structures are electrically connected through the semiconductor conductive structure; at least part of the semiconductor conductive structure is connected to the source / drain metal layer through a via.

[0022] According to one embodiment of the present disclosure, the transistor layer includes a semiconductor layer; the semiconductor layer includes a semiconductor structure and a metal conductive structure;

[0023] The semiconductor structure includes a channel structure, and at least a portion of the channel structures are electrically connected via the metal conductive structure.

[0024] According to an embodiment of the present disclosure, at least a portion of the semiconductor structure includes a channel structure and a lap structure located on both sides of the channel structure; the lap structure overlaps the metal conductive structure.

[0025] According to an embodiment of the present disclosure, at least a portion of the metal conductive structure is connected to the source / drain metal layer through a via.

[0026] According to one embodiment of the present disclosure, the semiconductor layer is composed of a semiconductor structure and a metal conductive structure; any one of the semiconductor structures is composed of a channel structure and overlapping structures located on both sides of the channel structure;

[0027] The overlapping structure overlaps the metal conductive structure; the metal conductive structure is used to electrically connect the channel structures and to connect with the source and drain metal layer through vias.

[0028] According to an embodiment of the present disclosure, the driving backplane includes a display area and a peripheral area located on at least one side of the display area; the thick copper layer is not provided in the peripheral area.

[0029] According to one embodiment of the present disclosure, the driving backplane further includes a supporting substrate, and the first substrate is disposed on a side of the supporting substrate away from the peripheral area; the supporting substrate is not disposed in at least a portion of the peripheral area.

[0030] According to an embodiment of the present disclosure, the supporting substrate is not provided in the peripheral area; the peripheral area can be bent to the back side of the driving back plate.

[0031] According to one embodiment of the present disclosure, the source-drain metal layer is provided with a binding pad and a connecting trace; the binding pad is provided in the peripheral area; the connecting trace is electrically connected to the binding pad and extends to the display area, and is electrically connected to the thick copper layer through a via.

[0032] According to a second aspect of the present disclosure, a light-emitting substrate is provided, comprising the aforementioned driving backplane and electronic components; the electronic components are electrically connected to the driving layer of the driving backplane; wherein the electronic components include light-emitting components.

[0033] According to one embodiment of the present disclosure, the light-emitting element includes Mini LED or Micro LED.

[0034] According to a third aspect of the present disclosure, a display panel is provided, comprising the aforementioned driving backplane and a light-emitting element, wherein the light-emitting element is electrically connected to the driving layer of the driving backplane.

[0035] According to a fourth aspect of the present disclosure, a display device is provided, comprising the above-mentioned light-emitting substrate or the above-mentioned display panel.

[0036] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0038] FIG1 is a schematic structural diagram of a light-emitting substrate in one embodiment of the present disclosure.

[0039] FIG2 is a schematic diagram showing the principle of a driving circuit driving a light-emitting element in one embodiment of the present disclosure.

[0040] FIG3 is a schematic diagram showing the principle of a driving circuit driving a light-emitting element in one embodiment of the present disclosure.

[0041] FIG4 is a schematic diagram showing the principle of a driving circuit driving a light-emitting element in one embodiment of the present disclosure.

[0042] FIG5 is a schematic structural diagram of a driving backplane in one embodiment of the present disclosure.

[0043] FIG6 is a schematic structural diagram of a first substrate and a thick copper layer formed sequentially on a supporting substrate in one embodiment of the present disclosure.

[0044] FIG7 is a schematic structural diagram of forming a second substrate covered with a thick copper layer in one embodiment of the present disclosure.

[0045] FIG8 is a schematic structural diagram of forming a first gate layer on a second substrate in one embodiment of the present disclosure.

[0046] FIG9 is a schematic structural diagram of forming a first gate insulating layer and a semiconductor layer in one embodiment of the present disclosure.

[0047] FIG10 is a schematic structural diagram of forming a second gate insulating layer and a second gate layer in one embodiment of the present disclosure.

[0048] FIG. 11 is a schematic structural diagram of forming an interlayer dielectric layer in one embodiment of the present disclosure.

[0049] FIG12 is a schematic structural diagram of forming a source-drain metal layer in one embodiment of the present disclosure.

[0050] FIG13 is a schematic structural diagram of forming an organic solderability protective layer in one embodiment of the present disclosure.

[0051] FIG14 is a schematic structural diagram of forming a soldering layer in one embodiment of the present disclosure.

[0052] FIG15 is a schematic structural diagram of an embodiment of the present disclosure in which a transfer pad is disposed on the second gate layer.

[0053] FIG16 is a schematic structural diagram of an embodiment of the present disclosure in which a transfer pad is disposed on the first gate layer.

[0054] FIG17 is a schematic structural diagram of an embodiment of the present disclosure in which a transfer pad is disposed on a first gate layer and a second gate layer.

[0055] FIG18 is a schematic structural diagram of an embodiment of the present disclosure in which a transfer pad is disposed on a transfer layer.

[0056] FIG19 is a schematic structural diagram of a first substrate and a thick copper layer formed sequentially on a supporting substrate in one embodiment of the present disclosure.

[0057] FIG20 is a schematic structural diagram of sequentially forming a second substrate, a transfer layer, and a third inorganic barrier layer in one embodiment of the present disclosure.

[0058] FIG21 is a schematic structural diagram of forming a first gate layer on a third inorganic barrier layer in one embodiment of the present disclosure.

[0059] FIG22 is a schematic structural diagram of forming a first gate insulating layer and a semiconductor layer in one embodiment of the present disclosure.

[0060] FIG23 is a schematic structural diagram of forming a second gate insulating layer and a second gate layer in one embodiment of the present disclosure.

[0061] FIG. 24 is a schematic structural diagram of forming an interlayer dielectric layer in one embodiment of the present disclosure.

[0062] FIG25 is a schematic structural diagram of forming a source-drain metal layer in one embodiment of the present disclosure.

[0063] FIG26 is a schematic diagram of the partial coordination between the semiconductor layer, the gate layer, and the source / drain metal layer in one embodiment of the present disclosure.

[0064] FIG27 is a schematic diagram of the partial coordination between the semiconductor layer, the gate layer, and the source / drain metal layer in one embodiment of the present disclosure.

[0065] FIG28-1 is a schematic partial top view of the metal conductive structure in the embodiment described in FIG27 .

[0066] FIG28-2 is a schematic diagram of a partial top view of the semiconductor structure in the embodiment described in FIG27 .

[0067] FIG28-3 is a schematic partial cross-sectional view of the semiconductor layer in the embodiment described in FIG27 .

[0068] FIG29 is a schematic structural diagram of sequentially preparing a semiconductor material layer and a photoresist mask layer on a substrate surface in accordance with an embodiment of the present disclosure.

[0069] FIG30 is a schematic structural diagram of forming a semiconductor structure in one embodiment of the present disclosure.

[0070] FIG31 is a schematic structural diagram of forming a release adhesive pattern layer in one embodiment of the present disclosure.

[0071] FIG32 is a schematic structural diagram of forming a metal material layer in one embodiment of the present disclosure.

[0072] FIG33 is a schematic structural diagram of forming a metal conductive structure in one embodiment of the present disclosure.

[0073] FIG34 is a schematic structural diagram of a driving backplane including a display area and a peripheral area in one embodiment of the present disclosure.

[0074] FIG35 is a schematic diagram of a structure in which a driving back plate can be bent in a peripheral area in one embodiment of the present disclosure.

[0075] FIG36 is a schematic structural diagram of a bonding pad bent to the back side of a driving backplane in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0076] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0077] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0078] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0079] A transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), through which current can flow. The channel region is the area where current primarily flows.

[0080] Micro LED direct display technology uses self-luminous micron-sized Micro LEDs as sub-pixels, assembling them onto a driver panel to form a high-density Micro LED array. Micro LEDs generally require high drive currents, so the driver backplane is often equipped with a thick copper layer to reduce voltage drop and power consumption in the driver traces.

[0081] In related technologies, a thick copper layer is formed on the side of the transistor layer away from the substrate. After the thick copper layer is formed, a large step difference will form on the surface of the driver backplane, which will adversely affect the subsequent processing of the driver backplane. Moreover, since the thick copper layer is formed after the transistor layer, the film quality and difficulty of the thick copper layer are also affected by the previous layer processing, especially the uniformity of the thick copper layer.

[0082] The embodiment of the present disclosure provides a light-emitting substrate, see Figure 1, which includes a driving backplane DBP and electronic components bound to the surface of the driving backplane DBP. These electronic components include at least a light-emitting element LE, which can emit light under the drive of the driving backplane DBP. Optionally, the light-emitting element LE can be a Micro LED (micro light-emitting diode) or a Mini LED (mini light-emitting diode). Of course, the light-emitting element LE can also be other self-luminous electronic components, such as organic electroluminescent diodes, quantum dot light-emitting diodes, etc., subject to the light-emitting element LE being able to be bound to the surface of the driving backplane DBP and to be controlled to emit light.

[0083] Optionally, the size of the Mini LED can be no larger than 1 mm, in particular no larger than 400 microns. Furthermore, the light emitting area of ​​the Mini LED can be less than 1 mm. 2 , especially less than 10000μm 2 , further can be less than 3000μm 2 .

[0084] Optionally, the size of the Micro LED may be no larger than 300 microns, and in particular, no larger than 80 microns. Thus, when the light-emitting element LE is a Micro LED, the light-emitting substrate may have a larger resolution.

[0085] In the embodiments of the present disclosure, the light-emitting substrate can be a lighting panel, a vehicle light panel, an ambient light panel, a backlight panel for a liquid crystal display device, a backlight panel for a billboard, or a direct display panel. Of course, the light-emitting substrate of the embodiments of the present disclosure is not limited to the above uses or types, and is capable of emitting light, displaying, or providing a light source.

[0086] In one example, each light-emitting element LE can be independently controlled to emit light under the drive of the driving backplane DBP, so that the light-emitting substrate can function as a display panel and achieve direct display. In this case, each light-emitting element LE can serve as a sub-pixel of the light-emitting substrate. Furthermore, the light-emitting element LE is a Micro LED, which enables the light-emitting substrate to have a higher resolution.

[0087] Optionally, the light-emitting substrate may be provided with light-emitting elements LE of multiple different colors, for example, a red light-emitting element LE, a green light-emitting element LE and a blue light-emitting element LE, so that the light-emitting substrate can emit colored light or achieve color display.

[0088] It is understandable that, in some embodiments, the electronic components bound to the surface of the driver backplane DBP may also include other components, such as one or more of a photoelectric sensor, a temperature sensor, a micro driver chip, etc.

[0089] The present disclosure also provides a display device, which may include the above-mentioned light-emitting substrate. In one example, the display device is a liquid crystal display device, and the light-emitting substrate may serve as a backlight panel for the liquid crystal display device. In another example, the display device may be a Micro LED display device or a Mini LED display device, and the light-emitting substrate may serve as a direct display panel for the display device. Optionally, the display device may be a smartphone screen, a smartwatch screen, a television screen, an advertising screen, or other types of display devices.

[0090] Referring to Figure 1 , the driver backplane DBP includes a first substrate BPA, a thick copper layer CL, a second substrate BPB, and a driver layer DRL, which are stacked in sequence. Electronic components are electrically connected to the driver layer DRL. The driver layer DRL is provided with a driver circuit PDC for driving the light-emitting elements LE, and the thick copper layer CL is provided with drive traces for applying drive signals to the driver circuit PDC. The driver layer DRL and the thick copper layer CL are electrically connected directly or indirectly through vias to enable the application of drive signals to the driver circuit PDC.

[0091] In one embodiment of the present disclosure, referring to FIG1 , the driving layer DRL may include a transistor layer TL, an interlayer dielectric layer ILD, and a source / drain metal layer SD, which are sequentially arranged on the side of the second substrate BPB away from the first substrate BPA. The transistor layer TL has transistors TFT required for the driving circuit PDC. When the driving circuit PDC is provided with a storage capacitor, at least part of the electrode plates of the storage capacitor may also be provided on the transistor layer TL; of course, if necessary, part of the electrode plates may also be provided on the source / drain metal layer SD. The devices of the driving circuit PDC (such as the transistor TFT and the storage capacitor) are electrically connected through the conductive structure located on the transistor layer TL and the source / drain metal layer SD to form the required electrical connection relationship.

[0092] In the disclosed embodiment, the thick copper layer CL is primarily made of copper and has a relatively large thickness, thereby reducing its square resistance. The drive lines provided by the thick copper layer CL are lines that can deliver drive signals to multiple drive circuits PDC or multiple light-emitting elements LE. In this case, the distribution area of ​​the drive signal spans across multiple sub-pixel regions, spanning a long distance. Because the thick copper layer CL utilizes a thick copper process, the impedance of the drive lines is low, thus avoiding the problem of large drive signal voltage drop and high drive line power consumption caused by excessively long drive lines.

[0093] In this embodiment, the thick copper layer CL is disposed on the surface of the first substrate BPA, so that the thick copper layer CL is formed on a flat surface, avoiding the problem of insufficient surface flatness leading to insufficient thickness uniformity of the thick copper layer CL. In addition, when forming the thick copper layer CL, no other conductive structures are formed on the first substrate BPA, or relatively few conductive structures are formed. The thick copper layer CL is prepared before the drive layer DRL, so the preparation process of the thick copper layer CL does not affect the electrical properties of the drive layer DRL. This can not only avoid the impact of the preparation process of the thick copper layer CL on the performance of the drive layer DRL, but also make the process used for the thick copper layer CL more free and flexible, facilitating more flexible process optimization to produce a thicker, more uniform, and lower-cost thick copper layer CL.

[0094] In this embodiment, the second substrate BPB covers the thick copper layer CL, and the drive layer DRL is disposed on the side of the second substrate BPB away from the thick copper layer CL. Although the thick copper layer CL has a large thickness and a large step difference, the second substrate BPB can block the conduction of this step difference to subsequent film layers, that is, providing a flat surface for the subsequent preparation of the drive layer DRL. In other words, the surface unevenness caused by the large thickness and large step difference of the thick copper layer CL will not be transmitted to the transistor layer TL, which can reduce the difficulty of preparing the transistor layer TL and optimize the morphology and size of each film layer of the transistor layer TL.

[0095] Therefore, the light-emitting substrate and the driving backplane DBP provided by the embodiments of the present disclosure can reduce the difficulty of preparing the driving backplane DBP, thereby helping to improve the yield of the driving backplane DBP and the light-emitting substrate.

[0096] As follows, the structure, principle and effect of the driving backplane DBP according to the embodiment of the present disclosure are further explained and illustrated with reference to the accompanying drawings.

[0097] In one embodiment of the present disclosure, referring to FIG1 , a driver circuit PDC is electrically connected to a thick copper layer CL via a source / drain metal layer SD, such that a drive signal on the thick copper layer CL is applied to the driver circuit PDC. Optionally, the thickness of the thick copper layer CL may be greater than the thickness of the source / drain metal layer SD. Furthermore, the main material of the thick copper layer CL includes copper.

[0098] In one embodiment of the present disclosure, as shown in FIG1 , the source / drain metal layer SD further forms a device pad for bonding the light emitting element LE, and the light emitting element LE is bonded to the device pad. For example, the pins of the light emitting element LE are electrically connected to the device pad via a conductive connection structure XB.

[0099] Optionally, the conductive connection structure XB is solder paste, so that the electrical connection between the light-emitting element LE and the device pad can be completed by applying the solder paste (e.g., printing the solder paste), mounting the light-emitting element LE (die bonding), and reflow soldering. It is understood that the conductive connection structure can also be made of other structures or materials. For example, in some other embodiments, the conductive connection structure can also be a conductive adhesive, or a hard metal with a spike-like concave-convex structure.

[0100] Optionally, the light-emitting element LE has an anode pin and a cathode pin. Referring to FIG1 , the device pad includes a first device pad PADA for connecting to the anode pin of the light-emitting element LE and a second device pad PADB for connecting to the cathode pin of the light-emitting element LE. One of the first device pad PADA and the second device pad PADB is connected to the drive circuit PDC, and the other is electrically connected to a drive trace provided in the thick copper layer CL. The drive circuit PDC can control whether the connected light-emitting element LE is in an electrical path, and the state of the electrical path (e.g., the magnitude of the drive current, the duration of the drive current, etc.), thereby controlling the light-emitting state of the light-emitting element LE.

[0101] As an example, referring to Figure 1 , the drive traces on the thick copper layer CL include a drive voltage trace VDDL for applying a drive voltage VDD and a reference voltage trace VSSL for applying a reference voltage VSS. The source / drain metal layer SD is provided with a first connection structure SDA, a second connection structure SDB, a first device pad PADA, and a second device pad PADB. The drive circuit PDC is electrically connected to the drive voltage trace VDDL via the first connection structure SDA, allowing the drive voltage VDD to be applied to the drive circuit PDC. The first device pad PADA is electrically connected to the output terminal of the drive circuit PDC, allowing the drive current provided by the drive circuit PDC to be applied to the first device pad PADA. The second device pad PADB is electrically connected to the reference voltage trace VSSL via the second connection structure SDB, allowing the drive current flowing from the light-emitting element LE to the second device pad PADB to flow to the reference voltage trace VSSL. When the drive circuit PDC is turned on, the light-emitting element LE is in an electrical path and, thereby, emits light under the control of the drive current provided by the drive circuit PDC.

[0102] In this example, the second connection structures SDB of different drive circuits PDC can each be independently electrically connected to the reference voltage trace VSSL through a via. At this time, adjacent second device pads PADB are not electrically connected to each other through the structure located in the source and drain metal layer SD. In other examples of the present disclosure, at least part of the second connection structures SDB can be electrically connected to each other through a conductive structure located in the source and drain metal layer SD, and electrically connected to the reference voltage trace VSSL. For example, the second connection structures SDB arranged in the same column can be connected to each other to form a reference voltage auxiliary trace located in the source and drain metal layer SD; further, the second device pads PADB can be a local area on the reference voltage auxiliary trace. In this way, the conductive structure (such as the reference voltage auxiliary trace) that electrically connects the second device pads PADB can be arranged in parallel with the reference voltage trace VSSL, which can further reduce the voltage drop and impedance of the reference voltage VSS during distribution, and reduce the power consumption of the reference voltage trace VSSL.

[0103] In this example, the first connection structures SDA of different drive circuits PDC can be independently electrically connected to the drive voltage line VDDL through vias. In other examples of the present disclosure, at least part of the first connection structures SDA can be electrically connected to each other through the conductive structure located in the source and drain metal layer SD, and electrically connected to the drive voltage line VDDL. For example, the first connection structures SDA arranged in the same column can be connected to each other to form a drive voltage auxiliary line located in the source and drain metal layer SD. In this way, the conductive structure (such as the drive voltage auxiliary line) that electrically connects the drive circuits PDC can be arranged in parallel with the drive voltage line VDDL, which can further reduce the voltage drop and impedance of the drive voltage VDD during distribution, and reduce the power consumption of the drive voltage line VDDL.

[0104] In the above example, the first device pad PADA is electrically connected to the driver circuit PDC, and the second device pad PADB is electrically connected to the reference voltage trace VSSL. It will be understood that in some other examples of the present disclosure, the second device pad PADB can be electrically connected to the output end of the driver circuit PDC, the first device pad PADA can be electrically connected to the driver voltage trace VDDL via the first connection structure SDA, and the driver circuit PDC can be electrically connected to the reference voltage trace VSSL via the first connection structure SDA.

[0105] In the disclosed embodiments, the driver circuit PDC can adopt different architectures as needed to achieve the desired driving effect on the light-emitting element LE. For example, in the example of FIG2 , the driver circuit PDC can include a time control module UA and a current control module UB connected in series. The time control module UA is used to control the total duration of the driver circuit PDC's conduction, and the current control module UB is used to control the magnitude of the drive current provided by the driver circuit PDC when it is on. During operation, the driver circuit PDC can control the brightness of the light-emitting element LE by controlling either the magnitude of the drive current, the total duration of the conduction, or both. For example, in low-grayscale display mode, the drive current remains unchanged when the driver circuit PDC is on, and the brightness of the light-emitting element LE is controlled by controlling the total duration of the conduction. In high-grayscale display mode, the total duration of the conduction of the driver circuit PDC remains unchanged, and the brightness of the light-emitting element LE is controlled by controlling the magnitude of the drive current. For another example, in the example of FIG3 , the driver circuit PDC can include only the time control module UA. In this example, the drive current provided by the driver circuit PDC can remain constant when it is on. By controlling the total duration of the driver circuit PDC's on-state, the brightness of the light-emitting element LE can be controlled. For another example, in the example of FIG. 4 , the driver circuit PDC can include only the current control module UB. In this example, the total duration of each on-state of the driver circuit PDC remains constant, and the brightness of the light-emitting element LE can be controlled by controlling the drive current during the on-state of the driver circuit PDC.

[0106] As follows, the film structure and preparation method of the light-emitting substrate according to the embodiment of the present disclosure are further explained and illustrated with reference to the accompanying drawings.

[0107] In one embodiment of the present disclosure, referring to FIG5 , the first substrate BPA may include a first polyimide layer PIA and a first inorganic barrier layer BuffA stacked in sequence. During preparation, the first polyimide layer PIA and the first inorganic barrier layer BuffA may be formed in sequence on the supporting substrate BPG. The first polyimide layer PIA is disposed between the thick copper layer CL and the supporting substrate BPG, which can balance the stress between the thick copper layer CL and the supporting substrate BPG, thereby preventing the thick copper layer CL from causing warping of the supporting substrate BPG during the preparation process. The first inorganic barrier layer BuffA can achieve isolation between the thick copper layer CL and the first polyimide layer PIA. On the one hand, it can improve the adhesion between the thick copper layer CL and the first polyimide layer PIA, thereby reducing the risk of film peeling on the driver backplane DBP. On the other hand, it can also protect the thick copper layer CL, thereby preventing the thick copper layer CL from being corroded by ions or water oxygen that may be precipitated from the first polyimide layer PIA.

[0108] It is understood that after the driving backplane DBP or the light-emitting substrate is prepared, the support substrate BPG can be peeled off, so that the light-emitting substrate formed is a flexible light-emitting substrate. Of course, the support substrate BPG can also be retained, so that the light-emitting substrate is a rigid light-emitting substrate.

[0109] Optionally, the material of the support substrate BPG can be a hard material to provide support for the preparation of subsequent film layers. In one example, the material of the support substrate BPG can be glass.

[0110] Optionally, the thickness of the first polyimide layer PIA may be between 1 and 30 micrometers, for example, 5 micrometers, 10 micrometers, 15 micrometers or 20 micrometers.

[0111] Optionally, the first inorganic barrier layer BuffA may be a layer of inorganic insulating material, such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The first inorganic barrier layer BuffA may also be a composite film layer composed of multiple stacked inorganic material layers, wherein the film layer adjacent to the thick copper layer CL is made of an insulating material. For example, the first inorganic barrier layer BuffA may include a first silicon nitride layer, an amorphous silicon layer, and a second silicon nitride layer stacked on the surface of the first polyimide layer PIA.

[0112] In one example, the thickness of the first silicon nitride layer may be between 1000 and 10000 angstroms, for example, 2000 angstroms, 3000 angstroms, 4000 angstroms, 5000 angstroms, 6000 angstroms, 7000 angstroms, 8000 angstroms, or 9000 angstroms.

[0113] In an example, the thickness of the amorphous silicon layer may be between 1 and 100 angstroms, for example, 3 angstroms, 10 angstroms, 20 angstroms, 30 angstroms, 40 angstroms, or 50 angstroms.

[0114] In one example, the thickness of the second silicon nitride layer may be between 10 and 10,000 angstroms, such as 100 angstroms, 500 angstroms, 1,000 angstroms, 2,000 angstroms, 3,000 angstroms, 4,000 angstroms, 5,000 angstroms, 6,000 angstroms, 7,000 angstroms, 8,000 angstroms, or 9,000 angstroms.

[0115] Referring to FIG. 6 , after forming the first substrate BPA, a thick copper layer CL can be formed on the surface of the first substrate BPA. The thickness of the thick copper layer CL can be no less than 0.2 microns, and in particular no less than 2 microns. In some embodiments, the thickness of the thick copper layer CL is between 0.2 and 20 microns, and can be, for example, 2 microns, 3 microns, 4 microns, 5 microns, 10 microns, 15 microns, or 20 microns. It will be appreciated that the thicker the thick copper layer CL, the lower the impedance of the drive traces on the thick copper layer CL, and the better the uniformity of the drive signals applied to the drive traces.

[0116] Optionally, the thick copper layer CL may be prepared by using an evaporation process, a sputtering process, an electroplating process, a chemical plating process or other feasible processes, or by using a combination of multiple processes.

[0117] For example, in the example of FIG6 , a copper seed layer can be sputtered to form a full-surface copper seed layer on the side of the first substrate BPA away from the supporting substrate BPG, and then a copper growth layer can be formed on the surface of the copper seed layer through an electroplating process. In this way, a full-surface thick copper material layer is obtained. The thick copper material layer is then patterned (e.g., etched) to form a patterned thick copper layer CL. In this example, a sputtering process combined with an electroplating process is used to prepare the thick copper layer CL. Optionally, the copper seed layer may include a first functional layer, a copper layer, and a second functional layer stacked in sequence. The first and second functional layers may be material layers for protecting the copper layer or improving adhesion, and in particular, may be alloy layers. For example, the first functional layer may be an alloy layer that improves adhesion between the copper layer and the first inorganic barrier layer BuffA; the second functional layer may be an alloy layer that prevents oxidation of the copper layer. In one example, both the first and second functional layers are molybdenum-nickel-titanium alloy layers. Optionally, the thickness of the copper seed layer may be less than that of the copper growth layer, for example, the thickness of the copper seed layer may be between 300 nanometers and 600 nanometers.

[0118] It is understood that in other examples of the present disclosure, other strategies can also be used to prepare the thick copper layer CL. For example, in one example, a thick copper material layer can be formed by multiple sputtering processes, and then the thick copper material layer can be patterned to form the thick copper layer CL. For another example, in one example, the thick copper layer CL can include a plurality of stacked sub-film layers, and the patterns of each sub-film layer can be basically the same; each patterned sub-film layer can be prepared in sequence to obtain a patterned thick copper layer CL. When preparing any sub-film layer, a sub-material layer can be first formed by sputtering, and then the sub-material layer can be patterned. For another example, in one example, a patterned copper seed layer can be formed first, and then a patterned copper growth layer can be formed on the patterned copper seed layer by an electroplating process or a chemical plating process, thereby obtaining a patterned thick copper layer CL. For another example, in one example, a copper seed layer can be formed on the entire surface first, and then a pattern definition layer can be prepared on the surface of the copper seed layer; the pattern definition layer has pattern definition holes that expose the copper seed layer, and the pattern of the pattern definition holes is the same as the pattern of the thick copper layer CL to be formed. A patterned copper growth layer can be grown in the pattern definition hole by electroplating or chemical plating; after removing the pattern definition layer, the patterned copper growth layer can be used as a mask to pattern the entire copper seed layer, and the remaining copper seed layer and copper growth layer can form a patterned thick copper layer CL.

[0119] 7 , after forming the thick copper layer CL on the surface of the first substrate BPA, a second substrate BPB covering the thick copper layer CL may be formed.

[0120] In one embodiment of the present disclosure, the second substrate BPB may include a second polyimide layer PIB and a second inorganic barrier layer BuffB stacked in sequence on the side of the thick copper layer CL away from the first substrate BPA. During preparation, the second polyimide layer PIB can be first coated to cover the thick copper layer CL, and then the second inorganic barrier layer BuffB can be formed on the surface of the second polyimide layer PIB. In this embodiment, the second polyimide layer PIB can achieve a good leveling effect, thereby providing a flat surface for subsequent film layers, avoiding the large thickness and high step difference of the thick copper layer CL affecting the preparation of subsequent film layers.

[0121] Optionally, the thickness of the second polyimide layer PIB is greater than the thickness of the thick copper layer CL to ensure that the second polyimide layer PIB can cover the thick copper layer CL and provide a flat surface for subsequent film layers. For example, the thickness of the second polyimide layer PIB can be 3 to 10 microns greater than the thickness of the thick copper layer CL, such as 3 microns, 5 microns, 7 microns, or 9 microns. Moreover, the second polyimide layer PIB directly covers the thick copper layer CL, which allows the second polyimide layer PIB and the thick copper layer CL to be interlocked and have a larger attachment area, which can reduce the risk of film separation between the second polyimide layer PIB and the thick copper layer CL.

[0122] The second inorganic barrier layer BuffB may include a layer of inorganic insulating material, or may include multiple stacked layers of inorganic insulating material. For example, the second inorganic barrier layer BuffB includes one or a combination of a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, etc. In one example, the second inorganic barrier layer BuffB may be a layer of silicon nitride. In another example, the second inorganic barrier layer BuffB may include a stacked silicon nitride layer and a silicon oxide layer, wherein the silicon oxide layer is located on the side of the silicon nitride layer away from the first substrate BPA. The second inorganic barrier layer BuffB can effectively block the second polyimide layer PIB and the drive layer DRL, preventing ions in the second polyimide layer PIB from being precipitated toward the drive layer DRL, thereby changing the material properties of the drive layer DRL.

[0123] Optionally, the thickness of the second inorganic barrier layer BuffB may be between 100 and 10,000 angstroms, for example, 1,000 angstroms, 2,000 angstroms, 3,000 angstroms, 4,000 angstroms, etc.

[0124] Referring to FIG. 1 , in an embodiment of the present disclosure, the driving layer DRL is provided with a driving circuit PDC for driving the light-emitting element LE. In the driving layer DRL, any one of the driving circuits PDC may include a transistor TFT and a storage capacitor. Furthermore, the transistor TFT may be a thin film transistor, which may be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor may be an amorphous silicon semiconductor material, a low-temperature polycrystalline silicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material, or other types of semiconductor materials; the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

[0125] It is understandable that, among the transistors in the drive circuit PDC, the types of any two transistors may be the same or different. For example, in one embodiment, in a drive circuit PDC, some transistors may be N-type transistors and some transistors may be P-type transistors. For another example, in another embodiment of the present disclosure, in a drive circuit PDC, the material of the active layer of some transistors may be a low-temperature polysilicon semiconductor material, and the material of the active layer of some transistors may be a metal oxide semiconductor material. For another example, in one embodiment of the present disclosure, in a drive circuit PDC, the material of the active layer of each transistor is a low-temperature polysilicon semiconductor material.

[0126] Optionally, the drive layer DRL may include a stacked transistor layer TL and an interlayer dielectric layer ILD and a source / drain metal layer SD disposed on a side of the transistor layer TL away from the first substrate BPA. The transistor layer TL may include a stacked semiconductor layer SCL, a gate insulating layer GI, and a gate layer GT. The positional relationship among the semiconductor layer SCL, the gate insulating layer GI, and the gate layer GT, as well as the number of layers of each layer, may be determined based on the film structure of the thin film transistor.

[0127] Optionally, the semiconductor layer SCL can be used to form the active layer of a transistor, which may include the channel region of the transistor. The gate layer can be used to form gate layer traces such as scan traces, reset control traces, and light control traces, and can also be used to form the gate of a transistor, or can also be used to form part or all of the electrode plates of a storage capacitor. The gate insulating layer GI is used to isolate the semiconductor layer SCL from the gate layer GT.

[0128] In the embodiment of the present disclosure, the gate layer GT may be a single layer or may be configured as multiple layers as needed. The semiconductor layer SCL may be a single layer or may be configured as multiple layers as needed. It is understood that when at least one of the gate layer GT and the semiconductor layer SCL is multiple layers, the gate insulating layer GI used to isolate the gate layer GT and the semiconductor layer SCL also needs to be adaptively configured as multiple layers.

[0129] For example, in one example, the transistor layer TL may include a gate layer GT, a gate insulating layer GI, and a semiconductor layer SCL stacked in sequence on the side of the second substrate BPB away from the first substrate BPA, and the thin film transistor formed by the transistor layer TL is a bottom-gate thin film transistor.

[0130] For another example, in one example, the transistor layer TL may include a semiconductor layer SCL, a gate insulating layer GI, and a gate layer GT stacked in sequence on the side of the second substrate BPB away from the first substrate BPA, and the thin film transistor formed by the transistor layer TL is a top-gate thin film transistor.

[0131] For another example, in one example, the transistor layer TL may include a first gate layer GT1, a first gate insulating layer GI1, a semiconductor layer SCL, a second gate insulating layer GI2, and a second gate layer GT2, which are sequentially stacked on the side of the second substrate BPB away from the first substrate BPA. Then, among the thin-film transistors formed by the transistor layer TL, at least some of the thin-film transistors may be dual-gate thin-film transistors. In this example, gates are provided above and below the channel region of the dual-gate thin-film transistor. On the one hand, the upper and lower dual gates can both shield the channel region of the transistor TFT from light, thereby improving the stability of the semiconductor characteristics of the channel region; on the other hand, the upper and lower dual gates can reduce the floating body effect of the channel region. In this way, the dual-gate thin-film transistor can improve the stability of the output current, thereby facilitating the control of the luminous brightness of the light-emitting element LE.

[0132] In this example, some or all of the thin film transistors may be dual-gate thin film transistors. Furthermore, the drive transistors in the drive circuit PDC for generating the drive current are dual-gate thin film transistors; the remaining thin film transistors may be top-gate thin film transistors, bottom-gate thin film transistors, or dual-gate thin film transistors.

[0133] In this example, the top gate and bottom gate of the dual-gate thin-film transistor can optionally be electrically connected via a source-drain metal layer SD, so that the electrical properties of the top gate and bottom gate remain uniform. For example, the source-drain metal layer SD is provided with a bridge structure, the first portion of which is electrically connected to the bottom gate located on the first gate layer GT1 via a via, and the second portion of which is electrically connected to the top gate located on the second gate layer GT2 via a via. For another example, the bottom gate located on the first gate layer GT1 can be electrically connected to a first gate trace located on the first gate layer GT1, and the top gate located on the second gate layer GT2 can be electrically connected to a second gate trace located on the second gate layer GT2; the source-drain metal layer SD is provided with a bridge structure, the first portion of which is electrically connected to the first gate trace via a via, and the second portion of which is electrically connected to the second gate structure via a via.

[0134] In the embodiments of the present disclosure, the gate layer GT may be a molybdenum layer. Alternatively, the gate layer GT may be another metal layer or alloy layer, or may be a composite film layer comprising multiple metal layers or alloy layers. Optionally, the thickness of the gate layer GT may be between 100 angstroms and 10,000 angstroms, for example, 1,000 angstroms, 2,000 angstroms, 3,000 angstroms, 4,000 angstroms, 5,000 angstroms, 6,000 angstroms, etc.

[0135] It can be understood that when the transistor layer TL has two gate layers GT, the materials, thicknesses, etc. of the two gate layers GT may be the same or different.

[0136] In the embodiment of the present disclosure, the gate insulating layer GI can be a single insulating material layer or a composite film layer composed of multiple insulating material layers. For example, the gate insulating layer GI can be a single layer or a combination of multiple layers of film layers such as a silicon nitride layer, a silicon oxynitride layer, or a silicon oxide layer. Adjusting the thickness and material of the gate insulating layer GI can adjust the threshold voltage of the thin film transistor. It is understood that when the transistor layer TL has multiple gate insulating layers GI, the materials, thicknesses, etc. of any two gate insulating layers GI can be the same or different.

[0137] As follows, a method for preparing the transistor layer TL is exemplarily described by taking an example in which the transistor layer TL includes a first gate layer GT1 , a first gate insulating layer GI1 , a semiconductor layer SCL, a second gate insulating layer GI2 , and a second gate layer GT2 stacked in sequence.

[0138] 8 , after forming the second substrate BPB, a first gate layer GT1 can be formed on the side of the second substrate BPB away from the first substrate BPA. Specifically, a first gate material layer can be formed on the entire surface, and then the first gate material layer can be patterned to form a patterned first gate layer GT1.

[0139] In this example, the material of the first gate layer GT1 may be molybdenum, and the thickness may be between 100 and 10,000 angstroms.

[0140] 9 , after the first gate layer GT1 is formed, a first gate insulating layer GI1 may be formed, and then a semiconductor layer SCL may be formed on a surface of the first gate insulating layer GI1 .

[0141] In this example, the first gate insulating layer GI1 currently formed can be a full-surface film layer, and no patterning operation is required. When the interlayer dielectric layer ILD is patterned, the first gate insulating layer GI1 can be patterned at the same time, thereby reducing the patterning process and lowering the manufacturing cost of the driving backplane DBP. It is understood that, if necessary, the first gate insulating layer GI1 can also be patterned before forming the semiconductor layer SCL.

[0142] In this example, the first gate insulating layer GI1 may be a silicon oxide layer, or a composite film layer of a silicon oxide layer and a silicon nitride layer. Furthermore, the thickness of the first gate insulating layer GI1 may be between 100 angstroms and 5000 angstroms.

[0143] In one example, in the first gate insulating layer GI1 , the thickness of the silicon nitride layer is between 100 and 300 angstroms, and the thickness of the silicon oxide layer is between 2000 and 5000 angstroms; the silicon oxide layer is located on a side of the silicon nitride layer away from the first substrate BPA.

[0144] In this example, the material of the semiconductor layer SCL can be low-temperature polycrystalline silicon. When preparing the semiconductor layer SCL, an amorphous silicon layer can be first deposited on the surface of the first gate insulating layer GI1, followed by dehydrogenation, pickling (e.g., surface cleaning using hydrofluoric acid), crystallization, and patterning. Finally, the channel region of the transistor is doped to adjust the threshold voltage of the thin film transistor. Optionally, thermal annealing or laser annealing can be used to achieve crystallization of the amorphous silicon.

[0145] In an example, the thickness of the semiconductor layer SCL may be between 100 and 10,000 angstroms, and more particularly, between 100 and 800 angstroms.

[0146] 10 , after the semiconductor layer SCL is formed, a second gate insulating layer GI2 and a second gate layer GT2 may be sequentially formed on a side of the semiconductor layer SCL away from the first substrate BPA.

[0147] In this example, the material of the second gate insulating layer GI2 may be silicon nitride, and the thickness thereof may be between 100 angstroms and 10,000 angstroms.

[0148] In this example, the second gate insulating layer GI2 currently being prepared can be a full-surface film layer and does not require patterning. When the interlayer dielectric layer ILD is patterned, the second gate insulating layer GI2 can be patterned at the same time, thereby reducing the patterning process and lowering the manufacturing cost of the driving backplane DBP. It is understood that, if necessary, the second gate insulating layer GI2 can also be patterned before forming the second gate layer GT2.

[0149] In this example, when forming the second gate layer GT2 , a second gate material layer may be formed on the entire surface first, and then the second gate material layer may be patterned to form a patterned second gate layer GT2 .

[0150] In this example, the material of the second gate layer GT2 may be molybdenum, and the thickness may be between 100 and 10,000 angstroms.

[0151] In the embodiment of the present disclosure, referring to FIG. 11 and FIG. 12 , after forming the transistor layer TL, an interlayer dielectric layer ILD and a source / drain metal layer SD may be sequentially prepared on a side of the transistor layer TL away from the first substrate BPA to achieve interconnection between thin film transistors.

[0152] Referring to Figure 11 , when preparing the interlayer dielectric layer ILD, an interlayer dielectric material layer can be first formed, and then patterned to form vias, resulting in the interlayer dielectric layer ILD being patterned. Referring to Figure 12 , the source / drain metal layer SD is electrically connected to the thick copper layer CL and the transistor layer TL through the formed vias. During the patterning of the interlayer dielectric material layer, multiple vias can be formed as needed to meet the requirement for electrically connecting the source / drain metal layer SD to different film layers through different vias. For example, in the example of Figure 11 , four different vias can be formed: a first via HA, a second via HB, a third via HC, and a fourth via HD. The first via HA penetrates the interlayer dielectric layer ILD to expose the second gate layer GT2; the second via HB penetrates the interlayer dielectric layer ILD and the second gate insulating layer GI2 to expose the semiconductor layer SCL; the third via HC penetrates the interlayer dielectric layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1 to expose the first gate layer GT1; and the fourth via HD penetrates the interlayer dielectric layer ILD, the second gate insulating layer GI2, the first gate insulating layer GI1, and the second substrate BPB to expose the thick copper layer CL. In this way, when forming the source / drain metal layer SD, the source / drain metal layer SD can be electrically connected to the second gate layer GT2 through the first via HA, the source / drain metal layer SD can be electrically connected to the semiconductor layer SCL through the second via HB, the source / drain metal layer SD can be electrically connected to the first gate layer GT1 through the third via HC, and the source / drain metal layer SD can be electrically connected to the thick copper layer CL through the fourth via HD.

[0153] It can be understood that when the film layer structure of the driving backplane DBP is different or the electrical connection relationship is different, the type, quantity and position of the vias formed before forming the source and drain metal layer SD may be different, so as to enable the thick copper layer CL and the transistor layer TL to be electrically connected to the source and drain metal layer SD.

[0154] In this embodiment, the second substrate BPB, the first gate insulating layer GI1, and the second gate insulating layer GI2 may not require patterning during preparation; before forming the source / drain metal layer SD, these film layers may be patterned together with the interlayer dielectric layer ILD to form the required vias, which can reduce the number of required masks and the manufacturing process, thereby reducing the preparation cost of the driving backplane DBP and the light-emitting substrate.

[0155] In this embodiment, each via can be formed using a single mask or by combining multiple masks. When forming two or more different vias using the same mask, selective etching of different film layers can be achieved by selecting and controlling etching conditions, thereby controlling the depth of each via.

[0156] For example, in one example, a single mask can be used to simultaneously define the positions of four vias: a first via HA, a second via HB, a third via HC, and a fourth via HD. When etching the vias, multiple etching passes can be used, with etching conditions with a high selectivity ratio selected for each pass based on the material being etched. In this way, four vias of different depths can be achieved through multiple etching passes.

[0157] For example, in another embodiment, two masks can be used to define the positions of the various vias. For example, the first mask can be used to define the position of the fourth via HD, and then the fourth via HD can be formed by etching. Subsequently, the second mask can be used to define the positions of the first via HA, the second via HB, and the third via HC, and then the first via HA, the second via HB, and the third via HC can be formed by etching.

[0158] In the embodiments of the present disclosure, the interlayer dielectric layer ILD may include a single layer of inorganic insulating material, or may include multiple stacked layers of inorganic insulating material. In one example, the interlayer dielectric layer ILD includes a stacked silicon oxide layer and a silicon nitride layer, with the silicon nitride layer located on a side of the silicon oxide layer away from the first substrate BPA. In another example, the interlayer dielectric layer ILD is made of silicon nitride.

[0159] Optionally, the thickness of the interlayer dielectric layer ILD may be between 2000 and 20000 angstroms.

[0160] In this embodiment, the source / drain metal layer SD may be prepared by a sputtering process, for example, first forming a whole surface of a source / drain metal material layer, and then patterning the source / drain metal material layer to form a patterned source / drain metal layer SD.

[0161] Optionally, the source-drain metal layer SD may include a single metal layer, or may include multiple metal layers or alloy layers. For example, the source-drain metal layer SD may include a third functional layer, a main metal layer, and a fourth functional layer stacked on the surface of the interlayer dielectric layer ILD. The third functional layer and the fourth functional layer may provide protection for the main metal layer or improve the adhesion of the main metal layer to other film layers. Optionally, the third functional layer and the fourth functional layer may be made of alloy materials (such as molybdenum-nickel-titanium alloy, molybdenum-niobium alloy, copper-nickel alloy, nickel-tungsten alloy, nickel-vanadium alloy, etc.), inert metal materials (such as titanium or molybdenum) or conductive metal compounds (such as conductive metal oxides or titanium nitride), etc.; further, the materials of the third functional layer and the fourth functional layer may be the same or different. Optionally, the material of the main metal layer may be a material with high conductivity, such as aluminum or copper.

[0162] In one example, the third functional layer and the fourth functional layer are made of molybdenum nickel titanium alloy, and the main metal layer is made of copper.

[0163] Optionally, the thickness of the third protective layer is between 100 and 1000 angstroms, the thickness of the fourth protective layer is between 100 and 1000 angstroms, and the thickness of the main metal layer is between 100 and 100,000 angstroms. For example, the thickness of the main metal layer is 3000 angstroms, 4000 angstroms, 5000 angstroms, 6000 angstroms, 7000 angstroms, or 8000 angstroms.

[0164] Optionally, the drive layer DRL may further include an insulating protective layer located on the side of the source / drain metal layer SD away from the first substrate BPA. The insulating protective layer covers the source / drain metal layer SD and has an opening exposing the device pads. The insulating protective layer may be a single layer or a multi-layer composite film layer.

[0165] In one example, referring to Figure 13 , the insulating protective layer is an organic solderability protective layer (OSP). Optionally, the organic solderability protective layer can be formed by a coating process.

[0166] In another example, referring to FIG5 , the insulating protective layer may include a passivation layer PVX and a planarization layer PLN that are stacked. The passivation layer PVX may be an inorganic material, and the planarization layer PLN may be an organic material. Optionally, a passivation material (e.g., silicon nitride) may be deposited first to form a passivation layer PVX on the entire surface, and then a planarization material (e.g., resin) may be coated or printed to form a planarization layer PLN on the entire surface; and then the planarization layer PLN and the passivation layer PVX may be patterned to form a binding opening that exposes the device pad.

[0167] In some embodiments of the present disclosure, referring to Figures 1 and 14, the driver backplane DBP may further include a soldering layer XA disposed on the surface of the device pad. The light-emitting element LE is electrically connected to the soldering layer XA via a conductive connection structure XB to improve the stability and rework performance of the light-emitting element LE binding. For example, after forming the insulating protective layer, a nickel layer XA1 and a gold layer XA2 may be sequentially grown in the binding opening via a chemical plating process or an electroplating process. The nickel layer XA1 and the gold layer XA2 together serve as the soldering layer XA; wherein the nickel layer is thicker than the gold layer. It is understood that in other embodiments of the present disclosure, the soldering layer XA may also be of other structures or materials; alternatively, the driver backplane DBP may not be provided with the soldering layer XA, and the light-emitting element LE may be directly bonded to the device pad via the conductive connection structure XB.

[0168] In the example of Figure 5 , the source / drain metal layer SD is directly electrically connected to the thick copper layer CL through vias. It will be appreciated that in other embodiments of the present disclosure, the source / drain metal layer SD can also be electrically connected to the thick copper layer CL through a transition through other film layers; that is, the source / drain metal layer SD is indirectly electrically connected to the thick copper layer CL through vias. For example, the driver backplane DBP includes a transition pad between the source / drain metal layer SD and the thick copper layer CL. The first portion of the transition pad is connected to the thick copper layer CL through a via, and the second portion of the transition pad is electrically connected to the source / drain metal layer SD through a via. The transition pad can be provided on the first gate layer GT1 or the second gate layer GT2, or it can be a multilayer structure spanning the first and second gate layers GT1 and GT2, or it can be a newly added metal film layer on the driver backplane DBP, or other feasible methods can be adopted. This can avoid the excessive depth of a single via hole, which in turn prevents the via hole from being too large, thereby preventing the via hole size from affecting and restricting the resolution of the light-emitting substrate, and reduces the difficulty of manufacturing the driver backplane DBP.

[0169] For example, in one embodiment of the present disclosure, referring to FIG15 , a transfer pad TRP is provided on the second gate layer GT2. A first portion of the transfer pad TRP is connected to the thick copper layer CL via a via that penetrates the second gate insulating layer GI2, the first gate insulating layer GI1, and the second substrate BPB. A second portion of the transfer pad TRP is connected to the source / drain metal layer SD via a via that penetrates the interlayer dielectric layer ILD.

[0170] For another example, in one embodiment of the present disclosure, referring to FIG16 , a transfer pad TRP is provided on the first gate layer GT1. A first portion of the transfer pad TRP is connected to the thick copper layer CL via a via that passes through the second substrate BPB. A second portion of the transfer pad TRP is connected to the source / drain metal layer SD via a via that passes through the interlayer dielectric layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0171] For another example, in one embodiment of the present disclosure, referring to FIG17 , the transfer pad TRP includes a first portion of the transfer pad TRP disposed on the first gate layer GT1 and a second portion of the transfer pad TRP disposed on the second gate layer GT2. The first portion of the transfer pad TRP is electrically connected to the thick copper layer CL via a via penetrating the second substrate BPB; the second portion of the transfer pad TRP is electrically connected to the source / drain metal layer SD via a via penetrating the interlayer dielectric layer ILD; and the first portion of the transfer pad TRP and the second portion of the transfer pad TRP are electrically connected via a via penetrating the second gate insulating layer GI2 and the first gate insulating layer GI1.

[0172] For example, in one embodiment of the present disclosure, see FIG18 . A transfer layer TRL and a third inorganic barrier layer BuffC covering the transfer layer TRL are provided between the second substrate BPB and the transistor layer TL on the driver backplane DBP. The transistor layer TL is provided on the side of the third inorganic barrier layer BuffC away from the first substrate BPA. The transfer layer TRL is provided with a transfer pad TRP. The first portion of the transfer pad TRP is electrically connected to the thick copper layer CL via a via penetrating the second substrate BPB. The second portion of the transfer pad TRP is connected to the source / drain metal layer SD via a via penetrating the interlayer dielectric layer ILD, the transistor layer TL, and the third inorganic barrier layer BuffC.

[0173] In this embodiment, the third inorganic barrier layer BuffC may include a single inorganic insulating material layer, or may include multiple stacked inorganic material layers, such as one or more of a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer. In one example, the third inorganic barrier layer BuffC is a silicon nitride layer, and its thickness may be between 100 and 10,000 angstroms.

[0174] In this embodiment, the transition layer TRL may include a single layer or a stacked multilayer structure. These film layers may be metal layers or alloy layers. In one example, the transition layer TRL may be a molybdenum layer. Optionally, the thickness of the transition layer TRL may be between 100 and 10,000 angstroms, for example, 1,000 angstroms, 2,000 angstroms, 3,000 angstroms, 4,000 angstroms, 5,000 angstroms, 6,000 angstroms, 7,000 angstroms, or 8,000 angstroms.

[0175] As follows, the structure and preparation process of the driving backplane DBP are exemplarily described by taking the example that the driving backplane DBP is provided with a transfer layer TRL and the transistor layer TL includes a double-layer gate layer.

[0176] 19 , a first substrate BPA and a thick copper layer CL may be sequentially prepared on a supporting substrate BPG.

[0177] Referring to Figure 20 , after the thick copper layer CL is formed, the second substrate BPB with vias can be prepared. For example, a second polyimide layer PIB can be formed by coating or printing to cover the entire surface of the thick copper layer CL. A second inorganic barrier layer BuffB can then be formed on the surface of the second polyimide layer PIB by deposition. The entire second inorganic barrier layer BuffB and the second polyimide layer PIB can then be patterned to form vias that expose the thick copper layer CL.

[0178] After preparing the second substrate BPB with vias, a transfer material layer can be formed on the entire surface through a deposition process (e.g., sputtering process), and then the entire transfer material layer is patterned to form a patterned transfer layer TRL having a transfer pad TRP. The first portion of the transfer pad TRP is electrically connected to the thick copper layer CL through the vias on the second substrate BPB.

[0179] After forming the transition layer TRL, a third inorganic barrier layer BuffC is formed to cover the transition layer TRL. Referring to FIG. 20 , the third inorganic barrier layer BuffC may not be patterned, but may be patterned during the patterning of the interlayer dielectric layer ILD. Of course, if desired, the third inorganic barrier layer BuffC may also be patterned before forming the transistor layer TL.

[0180] 21 , after forming the third inorganic barrier layer BuffC, a patterned first gate layer GT1 may be formed on the surface of the third inorganic barrier layer BuffC.

[0181] 22 , after the first gate layer GT1 is formed, a first gate insulating layer GI1 covering the first gate layer GT1 may be formed, and then a patterned semiconductor layer SCL may be formed on a surface of the first gate insulating layer GI1 .

[0182] 23 , after the semiconductor layer SCL is formed, a second gate insulating layer GI2 covering the semiconductor layer SCL may be formed; and then, a patterned second gate layer GT2 may be formed on a surface of the second gate insulating layer GI2 .

[0183] Referring to Figure 24, after forming the patterned second gate layer GT2, an interlayer dielectric material layer is formed to cover the entire surface of the second gate layer GT2. Then, a patterning operation is performed to form the required vias, such as a first via HA exposing the second gate layer GT2, a second via HB exposing the semiconductor layer SCL, a third via HC exposing the first gate layer GT1, and a fourth via HD exposing the second portion of the transfer pad TRP. In this example, the fourth via HD does not need to penetrate the second substrate BPB, so its via depth is reduced and the difficulty of preparation is reduced. In this process, the interlayer dielectric material is patterned into an interlayer dielectric layer ILD; the third inorganic barrier layer BuffC, the first gate insulating layer GI1, the second gate insulating layer GI2, etc. are also patterned.

[0184] In this embodiment, one mask plate can be used to define each via hole, or multiple masks can be used to define each via hole. For example, in one example, the same mask plate can be used to define each via hole; by selecting appropriate etching conditions, such as selecting an etching solution with a high selectivity ratio, four different via holes can be prepared. For another example, in another example, two masks can be used to define each via hole. Among them, the first mask plate can be used to define the location of the fourth via hole HD, and the fourth via hole HD can be prepared by etching. Then, the second mask plate is used to define the location of the first via hole HA, the second via hole HB, and the third via hole HC, and then the first via hole HA, the second via hole HB, and the third via hole HC are prepared by etching.

[0185] 25 , after forming the required vias, a patterned source / drain metal layer SD is formed on the side of the interlayer dielectric layer ILD away from the first substrate BPA. Thus, the source / drain metal layer SD is electrically connected to the thick copper layer CL through the transfer pad TRP located on the transfer layer TRL.

[0186] In the above-described embodiment, the various structures of the semiconductor layer SCL are constructed from the same bulk material. When there are differences in the conductivity of the various structures of the semiconductor layer SCL, these differences arise from differences in the doping materials incorporated into the bulk material, such as different doping concentrations or doping types. For example, referring to FIG. 26 , the semiconductor layer SCL may include a channel structure SCL1 that maintains semiconductor properties and a conductive semiconductor conductive structure SCL2. The bulk materials of both the channel structure SCL1 and the conductive semiconductor structure SCL2 are semiconductor materials, such as polycrystalline silicon. The difference between the channel structure SCL1 and the conductive semiconductor structure SCL2 lies solely in the type or concentration of doped ions. In the conductive semiconductor structure SCL2, the semiconductor material is conductive through heavy doping, while in the channel structure SCL1, the semiconductor material maintains its semiconductor properties through light doping. The channel structure SCL1 may serve as the channel region of a thin-film transistor and overlap with the gate of the thin-film transistor, for example, by overlapping the gate layer GT. The conductive semiconductor structure SCL2 may be connected to the source / drain metal layer SD, or may be used to electrically connect the channel structures SCL1 of different thin-film transistors. In other words, at least a portion of the channel structures SCL1 are electrically connected to each other via the semiconductor conductive structure SCL2, and at least a portion of the semiconductor conductive structure SCL2 is connected to the source / drain metal layer SD via vias. However, when the semiconductor conductive structure SCL2 needs to transmit a large current, for example, when the light-emitting element LE is a Micro LED and the driver circuit PDC needs to provide a large drive current, the conductivity of the semiconductor conductive structure SCL2 is insufficient, resulting in high power consumption of the driver circuit PDC.

[0187] In some other embodiments of the present disclosure, in the semiconductor layer SCL, part or all of the semiconductor conductive structures can be replaced with metal conductive structures to utilize the better conductivity of metal materials to reduce the power consumption of the driving circuit PDC. The power consumption of the driving circuit PDC is reduced, and the heat generation of the driving circuit PDC is reduced in response, which can reduce the impact of heat on the characteristics of the thin film transistor and improve the stability and display effect of the display. In these embodiments, the semiconductor layer SCL includes two or more main materials, one of which is a semiconductor material and the other is a metal or an alloy. Among them, the main material of the channel structure is a semiconductor material, and the main material of part or all of the conductive structure is a metal or an alloy.

[0188] For example, in one embodiment of the present disclosure, referring to Figures 27, 28-1, 28-2, and 28-3, the semiconductor layer SCL includes a semiconductor structure SCLA and a metal conductive structure SCLB. The semiconductor structure SCLA includes a channel structure SCLA1, at least portions of which are electrically connected via the metal conductive structure SCLB. Furthermore, the semiconductor structure SCLA includes the channel structure SCLA1 and a lap structure SCLA2 located on either side of the channel structure SCLA1. The metal conductive structure SCLB overlaps the lap structure SCLA2. This allows the two channel structures SCLA1 to be electrically connected via the metal conductive structure SCLB, thereby reducing power consumption. Furthermore, when the source / drain metal layer SD is connected to the semiconductor layer SCL, the source / drain metal layer SD is connected to the metal conductive structure SCLB. This reduces the ohmic contact resistance between the source / drain metal layer SD and the semiconductor layer SCL, further reducing power consumption. In this embodiment, the channel structure SCLA1 overlaps the gate layer GT to serve as the channel region of the thin-film transistor, maintaining semiconductor properties. In this embodiment, the overlapping structure SCLA2 can maintain semiconductor properties or be made conductive. As a preferred solution, the overlapping structure SCLA2 can be made conductive by being heavily doped.

[0189] Optionally, the metal conductive structure SCLB may be made of metal or alloy, or a stacked structure consisting of multiple metal layers or alloy layers. For example, the metal conductive structure SCLB may be made of molybdenum, molybdenum alloy, copper, copper alloy, titanium, or titanium alloy.

[0190] Optionally, the thickness of the metal conductive structure SCLB may be substantially the same as the thickness of the semiconductor structure SCLA, so as to reduce the step difference of the semiconductor layer SCL itself.

[0191] Optionally, an electron beam evaporation process may be used to prepare the metal conductive structure SCLB to avoid damaging the semiconductor structure SCLA.

[0192] Alternatively, a lift-off process may be used to prepare the metal conductive structure SCLB. The following describes the process of preparing the semiconductor layer SCL by taking the process shown in FIG. 29 to FIG. 33 as an example.

[0193] Referring to FIG. 29 , a semiconductor material layer SCLAx can be formed on the surface of the preparation substrate BPX. The preparation substrate BPX is an intermediate substrate in the preparation process of the driving backplane DBP. The intermediate substrate has formed various film layers before the semiconductor layer SCL and is waiting for the further formation of the semiconductor layer SCL. In this example, the preparation substrate BPX may include a supporting substrate BPG, a first substrate BPA, a thick copper layer CL, a second substrate BPB, a first gate layer GT1, and a first gate insulating layer GI1 stacked in sequence. It can be understood that the structure of the driving backplane DBP is different, and the preparation substrates in the present disclosure are different.

[0194] 29 , after the semiconductor material layer SCLAx is formed, a photoresist mask layer PRA may be formed on the semiconductor material layer to define a pattern of the semiconductor structure SCLA.

[0195] Referring to FIG. 30 , the semiconductor material layer SCLAx is further patterned to obtain a semiconductor structure SCLA. Optionally, the semiconductor structure SCLA may also be doped. Specifically, the channel structure SCLA1 is doped to adjust the threshold voltage of the thin-film transistor; the lap structure SCLA2 is doped to make it conductive, thereby reducing the contact resistance between the lap structure SCLA2 and the metal conductive structure SCLB.

[0196] 31 , after obtaining the semiconductor structure SCLA, a release resin pattern layer PRB may be formed on the surface of the substrate to define the pattern of the metal conductive structure SCLB.

[0197] 32 , after the release resin pattern layer PRB is formed, a metal material layer SCLBx may be formed on the entire surface by processes such as sputtering and evaporation (eg, electron beam evaporation).

[0198] 33 , after forming the entire metal material layer SCLBx, the stripping adhesive pattern layer PRB is stripped; the metal material on the stripping adhesive pattern layer PRB is removed, so that the metal material layer SCLBx is patterned to form a metal conductive structure SCLB.

[0199] Thus, in this embodiment, the semiconductor layer SCL includes two sub-layers: a semiconductor sub-layer and a metal sub-layer. The semiconductor sub-layer forms the semiconductor structure SCLA, and the metal sub-layer forms the metal conductive structure SCLB. The metal conductive structure SCLB overlaps the overlapping structure SCLA2 of the semiconductor structure SCLA, and the metal conductive structure SCLB exposes the channel structure SCLA1 of the semiconductor structure SCLA. Subsequently, the other film layers of the drive backplane DBP are prepared, for example, the second gate insulation layer GI2 is prepared on the surface of the semiconductor layer SCL.

[0200] In the above embodiment, the semiconductor layer SCL is composed of a semiconductor structure SCLA and a metal conductive structure SCLB; any one of the semiconductor structures SCLA is composed of a channel structure SCLA1 and a overlapping structure SCLA2 located on both sides of the channel structure SCLA1; the overlapping structure SCLA2 overlaps the metal conductive structure SCLB; the metal conductive structure SCLB is used to make electrical connections between the channel structures SCLA1, and to be connected to the source and drain metal layer SD through vias.

[0201] In the above-described embodiment, when the channel regions of the two thin film transistors are electrically connected via a conductive structure located in the semiconductor layer SCL, the conductive structure is a metal conductive structure SCLB. It is understood that in other embodiments of the present disclosure, part of the conductive structure may be a semiconductor conductive structure (the main material of the semiconductor conductive structure is a semiconductor material that is made conductive by heavy doping), and the remaining conductive structure may be a metal conductive structure SCLB; or, in the same conductive structure, one or some parts may be made of metal material, and the remaining parts may be made of conductive semiconductor material.

[0202] In the above-described embodiment, when the source / drain metal layer SD is connected to the semiconductor layer SCL via vias, the source / drain metal layer SD is also connected to the metal conductive structure SCLB located in the semiconductor layer SCL via vias. It will be appreciated that in other embodiments of the present disclosure, when the source / drain metal layer SD is connected to the conductive structure located in the semiconductor layer SCL via vias, the conductive structure may also be a semiconductor conductive structure; or part of the conductive structure may be the metal conductive structure SCLB, and part of the conductive structure may be a semiconductor conductive structure.

[0203] In the above-described embodiment, within the semiconductor layer SCL, the metal conductive structure SCLB overlaps the surface of the semiconductor structure SCLA that is distal to the first substrate BPA. In other words, during fabrication, the semiconductor sub-film layer is prepared first, followed by the metal sub-film layer. In other embodiments of the present disclosure, the metal sub-film layer may also be prepared first, followed by the semiconductor sub-film layer. In this way, the overlapping structure SCLA2 of the semiconductor structure SCLA overlaps the surface of the metal conductive structure SCLB that is distal to the first substrate BPA.

[0204] In one embodiment of the present disclosure, referring to FIG. 34 , a driver backplane DBP may include a display area AA and a peripheral area BB on at least one side of the display area AA, for example, the peripheral area BB surrounding the display area AA. Light-emitting elements LE may be bonded to the display area AA for display. Bonding pads PADC may be provided on the peripheral area BB, which may be used to electrically connect to an external driver circuit, such as a flexible printed circuit board, a driver circuit board, or a driver chip.

[0205] Optionally, referring to Figures 35 and 36, the supporting substrate BPG of the driving backplane DBP can be partially removed so that the driving backplane DBP retains the supporting substrate BPG only in the display area AA. In this way, the driving backplane DBP is flexible in the peripheral area BB and can be bent to the back of the driving backplane DBP, thereby allowing the binding pads PADC to be bent to the back of the driving backplane DBP. This arrangement facilitates the mutual splicing of the driving backplane DBP and the light-emitting substrate, can reduce the size of the splicing seam, and achieve the effect of seamless splicing or narrow seam splicing. In this way, a large-sized panel can be spliced ​​out of a smaller-sized light-emitting substrate, reducing the difficulty of preparing large-sized panels.

[0206] Optionally, the peeling of part of the support substrate BPG may be completed by a laser lift-off process, for example, the support substrate BPG located in the peripheral area BB may be removed by a laser lift-off process.

[0207] Optionally, the bonding pads PADC are provided on the source / drain metal layer SD. The thick copper layer CL may not be provided in at least a portion of the peripheral area BB, for example, the entire peripheral area BB may not be provided with the thick copper layer CL. The bonding pads PADC are connected to the thick copper layer CL located in the display area AA via connecting traces located on the source / drain metal layer SD. In this way, a decrease in the yield during laser lift-off caused by providing the thick copper layer CL in the peripheral area BB can be avoided. As an example, the source / drain metal layer SD is provided with bonding pads PADC and connecting traces connected to the bonding pads PADC in the peripheral area BB. The connecting traces extend to the display area AA and are electrically connected to the thick copper layer CL.

[0208] Optionally, the peripheral area BB may include a binding area and a bending area, with the bending area being located between the binding area and the display area AA. The binding pads PADC are disposed in the binding area, and the bending area is thinned (particularly by reducing inorganic materials) to reduce the bending radius. During bending, the driver backplane DBP can be bent in the bending area to bend the binding area toward the back of the driver backplane DBP.

[0209] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A driving backplane, comprising a first substrate, a thick copper layer, a second substrate and a driving layer stacked in sequence; wherein: The thick copper layer is provided with a driving trace for loading a driving signal; the driving layer is provided with a driving circuit, and the driving circuit is electrically connected to the driving trace through a via.

2. The driving backplane according to claim 1, wherein: The second substrate includes a second polyimide layer covering the thick copper layer and a second inorganic barrier layer disposed on a side of the second polyimide layer away from the first substrate.

3. The driving backplane according to claim 2, wherein: The thickness of the second polyimide layer is greater than the thickness of the thick copper layer.

4. The driving backplane according to claim 1, wherein: The thickness of the thick copper layer is between 0.2 and 20 microns.

5. The driving backplane according to claim 1, wherein: The first substrate includes a first polyimide layer and a first inorganic barrier layer which are stacked, and the thick copper layer is disposed on a surface of the first inorganic barrier layer away from the first polyimide layer.

6. The driving backplane according to any one of claims 1 to 5, wherein: The driving layer includes a transistor layer, an interlayer dielectric layer and a source-drain metal layer which are sequentially stacked on a side of the second substrate away from the first substrate; the source-drain metal layer is directly or indirectly electrically connected to the thick copper layer through vias.

7. The driving backplane according to claim 6, wherein: The driving wiring includes a driving voltage wiring for loading a driving voltage and a reference voltage wiring for loading a reference voltage; The source-drain metal layer is provided with a first device pad, a second device pad, a first connection structure and a second connection structure; Among them, the driving circuit is electrically connected to the first connection structure, and the first connection structure is electrically connected to the driving voltage routing; the first device pad is electrically connected to the output end of the driving circuit; the second device pad is electrically connected to the second connection structure, and the second connection structure is electrically connected to the reference voltage routing.

8. The driving backplane according to claim 6, wherein: The transistor layer includes transistors; at least some of the transistors have a top gate and a bottom gate, and the top gate and the bottom gate of the transistor are electrically connected through the source-drain metal layer.

9. The driving backplane according to claim 6, wherein: The driving backplane is provided with a transfer pad between the source-drain metal layer and the thick copper layer; a first portion of the transfer pad is electrically connected to the thick copper layer through a via hole; and a second portion of the transfer pad is electrically connected to the source-drain metal layer through a via hole.

10. The driving backplane according to claim 9, wherein: The driving backplane further comprises a transfer layer and a third inorganic barrier layer which are sequentially stacked and arranged on a side of the second substrate away from the first substrate; the transistor layer is arranged on a side of the third inorganic barrier layer away from the first substrate; The transfer pad is arranged on the transfer layer.

11. The driving backplane according to claim 6, wherein: The transistor layer includes a semiconductor layer; the semiconductor layer includes a channel structure and a semiconductor conductive structure; Among them, at least part of the channel structures are electrically connected through the semiconductor conductive structure; at least part of the semiconductor conductive structure is connected to the source-drain metal layer through a via.

12. The driving backplane according to claim 6, wherein: The transistor layer includes a semiconductor layer; the semiconductor layer includes a semiconductor structure and a metal conductive structure; Wherein, the semiconductor structure includes a channel structure, and at least part of the channel structures are electrically connected through the metal conductive structure.

13. The driving backplane according to claim 12, wherein: At least part of the semiconductor structure includes a channel structure and a lap joint structure located on both sides of the channel structure; the lap joint structure is lap jointed with the metal conductive structure.

14. The driving backplane according to claim 12, wherein: At least part of the metal conductive structure is connected to the source-drain metal layer through a via.

15. The driving backplane according to claim 12, wherein: The semiconductor layer is composed of a semiconductor structure and a metal conductive structure; any one of the semiconductor structures is composed of a channel structure and overlapping structures located on both sides of the channel structure; The overlapping structure overlaps the metal conductive structure; the metal conductive structure is used to electrically connect the channel structures and to connect with the source and drain metal layer through vias.

16. The driving backplane according to claim 6, wherein: The driving backplane includes a display area and a peripheral area located at least on one side of the display area; the thick copper layer is not arranged in the peripheral area.

17. The driving backplane according to claim 16, wherein: The driving backplane further comprises a supporting substrate, and the first substrate is arranged on a side of the supporting substrate away from the peripheral area; the supporting substrate is not arranged in at least a part of the peripheral area.

18. The driving backplane according to claim 17, wherein: The supporting substrate is not provided in the peripheral area; the peripheral area can be bent to the back side of the driving back plate.

19. The driving backplane according to claim 17, wherein: The source-drain metal layer is provided with a binding pad and a connecting wire; the binding pad is provided in the peripheral area; the connecting wire is electrically connected to the binding pad and extends to the display area, and is electrically connected to the thick copper layer through a via.

20. A light-emitting substrate, comprising the driving backplane according to any one of claims 1 to 19, and an electronic component; the electronic component is electrically connected to the driving layer of the driving backplane; wherein, The electronic component includes a light emitting element.

21. The light emitting substrate according to claim 20, wherein: The light emitting element includes Mini LED or Micro LED.

22. A display panel, comprising the driving backplane according to any one of claims 1 to 19, and a light-emitting element, wherein the light-emitting element is electrically connected to a driving layer of the driving backplane.

23. A display device comprising the light-emitting substrate according to claim 20 or 21, or the display panel according to claim 22.

Images