Apparatus for correcting time skew

Abstract

The present invention provides a time skew correction apparatus for correcting skew by controlling the delay of a data signal and a clock signal. The time skew correction apparatus may comprise: a data path correction unit that performs a first step of, in response to the result of comparing the phases of delayed random data and a delayed clock signal, controlling the delay of the random data, and when the random data is aligned with the clock signal, holds the delay of the random data; and a clock path correction unit that, after the delay of the random data is held, performs a second step of, in response to the result of comparing the phases of the delayed random data and the delayed clock signal, controlling the delay of the clock signal, and controls the delay of the clock signal so that a pre-selected edge of the clock signal is positioned on a pre-configured position of the random data.

Description

Time skew compensation device

[0001] The present invention relates to a time skew correction device, and more specifically, to a time skew correction device that corrects time skew by controlling the delay of a data signal and a clock signal.

[0002] In devices that require high speed and high functionality, fast data processing speeds are required, and as the number of parallel data bits increases, the difficulty of hardware design increases.

[0003] Skew between data buses is particularly problematic for high-speed signals. Skew problems in this case can generally be resolved by ensuring the path lengths of parallel data paths are equal. However, structurally, it may be difficult to ensure equal path lengths, and in these cases, hardware design to ensure equal path lengths can be challenging.

[0004] Furthermore, the skew problem in parallel data can be addressed using a variable delay buffer. However, as the number of bits in parallel data increases, the skew problem in parallel data becomes more difficult to resolve.

[0005] For example, skews occurring within 1 bit could be recovered by delay buffering or clock phase modulation.

[0006] FIG. 1 is a block diagram of a data recovery device according to an example proposed in the past, and illustrates a process of extracting data by modulating the clock phase for a skew that occurs within 1 bit of parallel data among data recovery methods.

[0007] Referring to FIG. 1, a conventional data recovery device is composed of a phase modulation unit (11) that modulates the phase of an input clock, an input data latch unit (12), and a selection unit (13), and solves a skew problem by using a clock phase modulation or delay buffer when a clock CLK_IN (1-10-1) and 4-bit parallel data DATA_IN[3:0] (1-10-2) are input.

[0008] Here, the phase modulation unit (11) can use clock 1 / 8 cycle delay buffers composed of multiple stages, and generates phase modulation clocks CLK(1-1-1), CLK(1-1-2), CLK(1-1-3), CLK(1-1-4), CLK(1-1-5), CLK(1-1-6), CLK(1-1-7) and CLK(1-1-8) using eight stages of phase delay taps of 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees and 315 degrees, and finds a phase modulation clock that can clock all parallel data and clocks it to restore data DATA_OUT[3:0](1-10-3) corresponding to parallel data DATA_IN[3:0](1-10-2). When applying the phase adjustment function with an accurate clock frequency, a phase modulation clock using a delay-locked loop method can be used.

[0009] The input data latch unit (12) includes 4-bit D flip-flops (DF / F) (12-1 to 12-8) that clock data using clocks input from each phase delay tap, and is a data recovery method that selects the most appropriate phase clock Sel_CLK (1-10-4) from the selection unit (13) as shown in the timing diagram in (a) of FIG. 2 and clocks with the selected clock.

[0010] Fig. 2 is an example of a data timing diagram restored by a conventional data recovery device. Fig. 2 (a) is a skew timing diagram of data reaching a receiver, and is an example of restoring data using a 180-degree delayed clock, Sel_CLK (1-10-4).

[0011] DATA_IN[3:0] can be restored normally if skew occurs within 1 clock cycle and there is a phase-shifted clock that can clock each data.

[0012] However, the data skew timing diagram of Fig. 2 (b) illustrates an example in which data skew occurs within one clock cycle but cannot be restored even if any phase-modulated clock is used. This is an example in which DATA_OUT[1] and DATA_OUT[2] are misaligned by one bit, making normal data restoration impossible, regardless of which phase-modulated clock is used.

[0013] In addition, the data skew timing diagram of Fig. 2 (c) illustrates an example in which restoration is impossible when DATA_IN[1] among the received parallel data has a +1 bit skew. If the skew differs significantly within 1 bit or a ±1 bit data skew occurs, normal data restoration is impossible regardless of which delay tap is used.

[0014] As shown in (b) and (c) of Fig. 2, a conventional data recovery device has a limitation in that normal data recovery is impossible when a skew occurs within one clock cycle, regardless of which delay buffer or clock phase modulation clock is used.

[0015] The present invention is derived from this technical background, and has the purpose of providing a time skew correction device that can correct the time skew of data by controlling the delay of a data signal and a clock signal and secure a time margin for setup and hold.

[0016] In addition, another object of the present invention is to provide a time skew correction device that can provide optimal conditions for securing a time margin for setup and hold by delaying a clock signal to sample data at the center of a data signal after correcting the time skew of data.

[0017] However, the technical task that this embodiment seeks to achieve is not limited to the technical task described above, and other technical tasks may exist.

[0018] The time skew correction device of the present invention for achieving the above object is characterized by including: a data path correction unit which performs a first step of controlling the delay of the random data in response to a result of comparing the phases of delayed random data and a delayed clock signal, and holds the delay of the random data when the random data is aligned with the clock signal; and a clock path correction unit which performs a second step of controlling the delay of the clock signal in response to a result of comparing the phases of the delayed random data and the delayed clock signal after the delay of the random data is held, and controls the delay of the clock signal so that a pre-selected edge of the clock signal is positioned at a preset position of the random data.

[0019] According to the present invention, it is possible to provide a time skew correction device capable of controlling the delay of a data signal and a clock signal to correct data skew and secure a time margin for setup and hold.

[0020] In particular, a time skew correction device can be provided that can provide optimal conditions for securing a time margin for setup and hold by delaying the clock signal so that it is sampled at the center of the data signal after compensating for data skew.

[0021] Figure 1 is a configuration diagram of a conventional data recovery device.

[0022] Figure 2 is an example of a data timing diagram restored by a conventional data restoration device.

[0023] FIG. 3 is a block diagram illustrating one embodiment of a time skew correction device of the present invention.

[0024] Fig. 4 is a detailed circuit diagram illustrating one embodiment of the first comparison unit of Fig. 3,

[0025] Fig. 5 is a detailed circuit diagram illustrating one embodiment of the second comparison unit of Fig. 3.

[0026] FIG. 6 is a timing diagram for explaining a skew correction process that operates based on the rising edge of a data signal according to one embodiment of the present invention.

[0027] FIG. 7 is a timing diagram for explaining a skew correction process that operates based on the falling edge of a data signal according to one embodiment of the present invention.

[0028] It should be noted that the technical terms used herein are used solely to describe specific embodiments and are not intended to limit the present invention. Furthermore, unless specifically defined otherwise, the technical terms used herein should be interpreted in the same sense as would be generally understood by those skilled in the art to which the present invention pertains, and should not be interpreted in an overly broad or overly narrow sense.

[0029] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0030] FIG. 3 is a block diagram illustrating one embodiment of a time skew correction device of the present invention.

[0031] Time skew between signals critically affects the setup and hold time margin for data samples. Insufficient setup and hold time margin can lead to data errors. Therefore, ideally, the clock samples data at the center of the signal, ensuring optimal setup and hold time margin.

[0032] In one embodiment, the time skew correction device may be exemplified by including a data path correction unit (100) and a clock path correction unit (200).

[0033] The data path correction unit (100) is intended to control the delay of random data Random Data in response to the result of comparing the phases of delayed random data Random Data and delayed clock signal Clock. The operation of the data path correction unit (100), i.e., the control of the delay of random data Random Data, can be defined as the first step Step 1.

[0034] The clock path correction unit (200) is for controlling the delay of the clock signal Clock in response to the result of comparing the phases of the delayed random data Random Data and the delayed clock signal Clock after the delay of the random data Random Data is held in the first step. The operation of the clock path correction unit (100), i.e., the control of the delay of the clock signal Clock, can be defined as the second step Step 2.

[0035] First, the data path correction unit (100) may include a first delay unit (110), a first comparison unit (120), and a first correction control unit (140) for the first step Step 1 described above, and the first correction control unit (140) may include a first control unit (130) and a first counter (135).

[0036] Among these, the first delay unit (110) may be configured to receive pre-random data Pre_Random Data and output random data Random Data that is the delayed pre-random data Pre_Random Data according to the first delay control signal CNT1. The first delay control signal CNT1 is an output value of the first counter (135) described below, and may be understood to have a delay control value for delay control of the pre-random data Pre_Random Data.

[0037] The first comparison unit (120) may be configured to receive random data Random Data and a clock signal Clock. Here, the clock signal Clock may be understood to be provided from the second delay unit (210) described below. In addition, the first comparison unit (120) may be configured to compare the phases of the random data Random Data and the clock signal Clock by sampling the state of the clock signal Clock by the random data Random Data, and as a result, may output the first phase comparison signal PV1. For example, the first comparison unit (120) may be configured to output the first phase comparison signal PV1 that samples the state of the clock signal Clock by the random data Random Data in a state where the clock signal Clock is at a low level.

[0038] The first comparison unit (120) described above can be exemplified as shown in FIG. 4. Referring to FIG. 4, the first comparison unit (120) can include a plurality of AND gates (G1 to G4), a delay unit (DU), and a phase comparator (PC1). The AND gate (G1) is configured to output a result of AND combining a clock signal Clock and a high level, the AND gate (G2) is configured to output a result of AND combining random data Random Data and a clock signal Clock, the AND gate (G3) is configured to output a result of AND combining the output of the AND gate (G1) and a high level, the delay unit (DU) is configured to delay the output of the AND gate (G2) for a preset time, and the AND gate (G4) is configured to output a result of combining the output of the AND gate (G2) and the output of the inversion delay unit (DU). In addition, the phase comparator (PC1) is configured to output a first phase comparison signal PV1 corresponding to the result of comparing the phases of random data Random Data and a clock signal Clock by using the output of the AND gate (G4) as a clock and inverting and outputting the output of the AND gate (G3).

[0039] Meanwhile, the first control unit (130) may be configured to receive the first phase comparison signal PV1 of the first comparison unit (120), determine whether the first counter (135) operates based on the result of comparing the phase of the random data Random Data of the first comparison unit (120) and the clock signal Clock, i.e., the first phase comparison signal PV1, and output the first control signal Step1_end regarding the operation. For example, the initial value of the first phase comparison signal PV1 may be set to “0”, and when the first phase comparison signal PV1, which is the comparison result of the first comparison unit (120), maintains the initial value of “0”, the first control unit (130) may be configured to maintain the value of the first control signal Step1_end as “0”. In contrast, when the first phase comparison signal PV1, which is the comparison result of the first comparison unit (120), changes from the initial value of “0” to the value of “1”, the first control unit (130) outputs the value of the first control signal Step1_end as the value of “1”, and ends the correction for the data path, i.e., the first step Step1.

[0040] When the first control unit (130) finishes the correction for the data path, the count value output from the first counter (135) according to the value of the first control signal Step1_end, that is, the delay control value of the first delay control signal CNT1, is held, and the delay time of the random data Random Data of the first delay unit (110) is held.

[0041] The first counter (135) may be configured to receive the first control signal Step1_end output from the first control unit (130) and provide the first delay control signal CNT1 corresponding to the first control signal Step1_end to the first delay unit (110). More specifically, the first counter (135) may provide a count value gradually increased by a preset unit value as the first delay control signal CNT when the value of the first control signal Step1_end of the first control unit (130) is maintained as “0”, and may hold the delay control value of the first delay control signal CNT as the currently counted value when the value of the first control signal Step1_end of the first control unit (130) is changed to “1”.

[0042] Meanwhile, the clock pass correction unit (200) may include a second delay unit (210), a second comparison unit (220), and a second correction control unit (240) for the second step Step 2 described above, and the second correction control unit (240) may include a second control unit (230) and a second counter (235).

[0043] Among these, the second delay unit (210) may be configured to receive a pre-clock Pre_Clock and output a clock signal Clock that delays the pre-clock Pre_Clock according to a second delay control signal CNT2. The second delay control signal CNT2 is an output value of a second counter (235) described below, and may be understood to have a delay control value for delay control of the pre-clock Pre_Clock.

[0044] The second comparison unit (220) may be configured to receive random data Random Data and a clock signal Clock after the first step Step1 is completed. The second comparison unit (220) may be configured to compare the phases of the random data Random Data and the clock signal Clock by sampling the random data Random Data by the clock signal Clock, and as a result, may output a second phase comparison signal PV2. For example, the second comparison unit (220) may be configured to output the second phase comparison signal PV2 with an initial value of “0”. In addition, the second comparison unit (220) may be configured to output the second phase comparison signal PV2, which is changed from an initial value of “0” to a value of “1” by a level change of the random data Random Data sampled by the clock signal Clock, and then maintains the value of “1” for a predetermined time and then changes back to a value of “0”.

[0045] The second comparison unit (220) described above can be exemplified as shown in FIG. 5. Referring to FIG. 5, the second comparison unit (220) can include AND gates (G5, G6) and a phase comparator (PC2). The AND gate (G5) is configured to output a result of AND combining random data Random Data with a high level, and the AND gate (G6) is configured to output a result of AND combining the first control signal Step1_end and the clock signal Clock. The AND gate (G6) can transmit the clock signal Clock to the phase comparator (PC2) when the first control signal Step1_end is provided with a value of “1”. In addition, the phase comparator (PC2) is configured to output a second phase comparison signal PV2 corresponding to a result of comparing the phases of the random data Random Data and the clock signal Clock by using the output of the AND gate (G6) as a clock and inverting and outputting the output of the AND gate (G5).

[0046] Meanwhile, the second control unit (230) may be configured to receive the second phase comparison signal PV2 of the second comparison unit (220), and output the second control signal Step2_end for controlling the operation of the second counter (235) according to the result of comparing the phase of the random data Random Data of the second comparison unit (220) and the clock signal Clock, i.e., the second phase comparison signal PV2. For example, when the second phase comparison signal PV2 changes from the initial value “0” to “1” at the first time point and then changes back to “0” at the second time point, the second control unit (230) outputs the value of the second control signal Step2_end as “1”, and ends the correction for the clock pass.

[0047] The second counter (235) may be configured to receive the second control signal Step2_end output from the second control unit (230) and provide the second delay control signal CNT2 corresponding to the second control signal Step2_end to the second delay unit (210). More specifically, the second counter (235) may be configured to store a first count value at a first point in time when the value of the second phase comparison signal PV2 of the second comparison unit (220) changes from the initial value “0” to “1” and a second count value at a second point in time when the value changes from “1” to “0”, and to provide an intermediate value between the stored first count value and the second count value as the final second control signal Step2_end. As a result, the rising edge of the clock signal Clock may be positioned at the center of the random data Random Data. According to another embodiment, it may be understood that the falling edge of the clock signal Clock is positioned at the center of the random data Random Data. A rising edge is the moment when the value changes from “0” to “1”, and a falling edge is the moment when the value changes from “1” to “0”.

[0048] FIG. 6 is a timing diagram for explaining a skew correction process that operates based on the rising edge of a data signal according to one embodiment of the present invention.

[0049] In a time skew correction device according to one embodiment, in a first step (Step 1) of a mode in which the time skew correction device operates based on the rising edge of a data signal, the comparison unit (120) samples the clock signal Clock delayed in the second delay unit (210) using the rising edge information of the random data Random Data delayed in the first delay unit (110), and the delay of the first delay unit (110) is increased in response to the result sampled by the comparison unit (120), so that the rising edge of the random data Random Data is aligned with the rising edge of the clock signal Clock, which is an output signal of the second delay unit (210). In the first step described above, only the rising edge information of the data signal delayed in the first delay unit (110), which occurs in a section in which the delayed clock signal delayed in the second delay unit (210) is low, is used as a signal for sampling. When the output of the first comparison unit (120) becomes “1” in the first step described above, the data path correction process ends when the first control signal Step1_end of the first control unit (130) becomes “1”, and the first counter (135) holds the first delay control signal CNT1, thereby storing the first delay control signal CNT1 of the first delay unit (110).

[0050] When the first control signal Step1_end becomes “1”, the first step (Step 1) ends and the second step (Sep 2) starts. In the second step (Step 2), the clock signal Clock, which is the output of the second delay unit (210), samples the random data Random Data, which is the output signal of the first delay unit (110), and the delay of the clock signal Clock of the second delay unit (210) is controlled according to the result of the random data Random Data being sampled by the comparison unit (220). In Step 2, first, the second delay unit (210) reduces the delay of the clock signal Clock by the second control signal Step2_end corresponding to the result of the random data Random Data being sampled, and the second comparison unit (220) outputs the second phase comparison signal PV2 as “0”. After that, the delay of the clock signal Clock of the second delay unit (210) increases, and the second comparison unit (220) outputs the second phase comparison signal PV2 as “1” at the first point in time. After that, the delay of the clock signal Clock of the second delay unit (210) continues to increase, and the second comparison unit (220) controls until the second point in time when the second phase comparison signal PV2 becomes “0”. By the process of the above-described Step 2, when the clock signal Clock, which is the output signal of the second delay unit (210), is aligned with the rising edge and falling edge of the random data Random Data, which is the output signal of the first delay unit (110), the rising edge or falling edge of the clock signal Clock is positioned at the center of the random data Random Data.

[0051] FIG. 7 is a timing diagram for explaining a skew correction process that operates based on the falling edge of random data according to one embodiment of the present invention.

[0052] In this process, the sample in the first comparator (120) can be performed using only the falling edge information of the random data delayed in the first delay unit (110) that occurs during the period in which the delayed clock signal delayed in the second delay unit (210) is high. Since the process thereafter is performed in the same manner as the process of Fig. 6, a duplicate description thereof will be omitted.

[0053] In an embodiment of the present invention, the data may be random data or pulse-shaped training pattern data.

[0054] Accordingly, the present invention can control the delay of random data and clock signals by sequentially performing the first step for data path correction and the second step for clock path correction, thereby compensating for time skew and securing a time margin for setup and hold.

[0055] In particular, the present invention can provide optimal conditions for securing a time margin for setup and hold by delaying a clock signal so that the clock signal is sampled at the center of random data after controlling the delay of data.

[0056] Although the invention has been described above with reference to embodiments, it will be understood by those skilled in the art that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as set forth in the claims below.

Claims

1. A data path compensation unit that performs a first step of controlling the delay of the random data in response to the result of comparing the phases of the delayed random data and the delayed clock signal, and holds the delay of the random data when the random data is aligned with the clock signal; and A time skew correction device characterized by comprising a clock path correction unit that performs a second step of controlling the delay of the clock signal in response to a result of comparing the phases of the delayed random data and the delayed clock signal after the delay of the random data is held, and controls the delay of the clock signal so that a pre-selected edge of the clock signal is located at a pre-set position of the random data.

2. In paragraph 1, The above data path correction unit is a time skew correction device that samples the state of the clock signal in response to the rising edge of the clock signal by the random data while the clock signal is at a low level and generates a result of comparing the phases.

3. In paragraph 1, The above data path correction unit is a time skew correction device that samples the state of the clock signal in response to the falling edge of the clock signal by the random data while the clock signal is at a high level and generates a result of comparing the phases.

4. In the first paragraph, the data path correction unit, A first delay unit that delays the random data in response to a first delay control signal corresponding to a result of comparing the phases of the clock signal and the random data in the first step; A first comparison unit that outputs a first phase comparison signal by comparing the phases of the clock signal and the random data by sampling the state of the clock signal by the random data of the first delay unit; A first control unit that receives the first phase comparison signal and outputs a first control signal according to the first phase comparison signal; and A time skew correction device comprising a first counter for holding the first delay control signal or providing the first delay control signal to increase the delay of the random data, depending on the value of the first control signal.

5. In paragraph 4, A time skew correction device in which the first comparison unit samples the state of the clock signal in response to the rising edge of the clock signal by the random data while the clock signal is at a low level and generates a result of comparing the phases.

6. In paragraph 4, A time skew correction device in which the first comparison unit samples the state of the clock signal in response to the falling edge of the clock signal by the random data while the clock signal is at a high level and generates a result of comparing the phases.

7. In paragraph 4, The first comparison unit is set to an initial value of the first phase comparison signal, A time skew correction device in which the first control unit provides the first control signal so that the counter provides the first delay control signal for increasing the delay of the random data when the initial value of the first phase comparison signal is maintained, and provides the first control signal so that the first step is terminated and the counter holds the first delay control signal when the value of the first phase comparison signal is changed.

8. In the first paragraph, the clock pass correction unit, A second delay unit that delays the clock signal in response to a second delay control signal corresponding to a result of comparing the phases of the clock signal and the random data; After the first step is completed, a second comparison unit that outputs a second phase comparison signal by comparing the phases of the clock signal and the random data by sampling the random data by the clock signal of the second delay unit; A second control unit that receives the second phase comparison signal and outputs a second control signal according to the second phase comparison signal; and A time skew compensation device comprising a second counter for holding the second delay control signal or providing the second delay control signal to increase the delay of the clock signal, depending on the value of the second control signal.

9. In the 8th paragraph, the second comparison unit sets the initial value of the second phase comparison signal, The second phase comparison signal is changed from an initial value at a first point in time by a level change of the random data being sampled, and then is changed from the changed value to the initial value at a second point in time. A time skew correction device in which the counter stores a first count value at the first time point and a second count value at the second time point according to the value of the second control signal, and provides an intermediate value between the first count value and the second count value as the second control signal.

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