Array substrate and display device

Abstract

Embodiments of the present disclosure provide an array substrate and a display device. The array substrate comprises: a substrate; a gate line layer, located on one side of the substrate and comprising a gate line extending in a first direction; an insulating layer, located on the side of the gate line layer facing away from the substrate and provided with a first through hole exposing part of the gate line; a first electrode, located on the side of the insulating layer facing away from the gate line layer and comprising a first sub-electrode part and a second sub-electrode part connected to the first sub-electrode part, the orthographic projection of the first sub-electrode part on the substrate partially overlapping the orthographic projection of the gate line on the substrate, and the first sub-electrode part being electrically connected to the gate line by means of the first through hole; and an active layer, the orthographic projection of the second sub-electrode part on the substrate overlapping the orthographic projection of the active layer on the substrate, and the orthographic projection of the active layer on the substrate not overlapping the orthographic projection of the gate line on the substrate.

Description

Array substrate and display device Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an array substrate and a display device. Background Art

[0002] 8K ultra-high-definition (7680×4320) display products are currently attracting increasing attention in the market. Their high resolution and exquisite image quality provide a superior viewing experience for those pursuing the ultimate in image quality. However, due to the excessive number of sub-pixels on the screen, 8K products have smaller pixel sizes (size) and smaller liquid crystal capacitance (Cst). The stored voltage is significantly affected by the coupling capacitance (Cgs) between the gate line (Gate) and the transistor source (TFT Source), which can easily cause undesirable phenomena such as afterimages and moving head lines. Therefore, reducing Cgs is very meaningful for improving the image quality of 8K products.

[0003] Summary of the Invention

[0004] An embodiment of the present disclosure provides an array substrate, comprising:

[0005] substrate;

[0006] a gate line layer, located on one side of the substrate, comprising gate lines extending along a first direction;

[0007] an insulating layer, located on a side of the gate line layer facing away from the substrate, and having a first via hole exposing a portion of the gate line;

[0008] a first electrode, located on a side of the insulating layer facing away from the gate line layer, comprising a first sub-electrode portion and a second sub-electrode portion connected to the first sub-electrode portion; an orthographic projection of the first sub-electrode portion on the substrate partially overlaps with an orthographic projection of the gate line on the substrate, and the first sub-electrode portion is electrically connected to the gate line through the first via hole;

[0009] active layer, the orthographic projection of the second sub-electrode portion on the substrate overlaps with the orthographic projection of the active layer on the substrate, and the orthographic projection of the active layer on the substrate does not overlap with the orthographic projection of the gate line on the substrate.

[0010] In a possible implementation, the array substrate includes a pixel electrode layer, the pixel electrode layer includes a plurality of pixel electrodes; the first electrode is located in the pixel electrode layer and is insulated from the pixel electrodes.

[0011] In a possible implementation, the array substrate further includes a data line layer, and the data line layer is located between the gate line layer and the first electrode;

[0012] The data line layer includes: a plurality of data lines extending along the second direction, a first electrode of a transistor connected to one side of the data line, and a second electrode of a transistor arranged opposite to the first electrode of the transistor;

[0013] The first electrode of the transistor includes: a first sub-section, a second sub-section, and a third sub-section; wherein one end of the first sub-section is electrically connected to the data line, and the other end is electrically connected to one end of the second sub-section, and the other end of the second sub-section is electrically connected to the third sub-section; the orthographic projection of the second sub-section on the substrate overlaps with the orthographic projection of the active layer on the substrate, and the orthographic projection of the third sub-section on the substrate does not overlap with the orthographic projection of the active layer on the substrate;

[0014] The second electrode of the transistor includes: a fourth sub-section, a fifth sub-section, and a sixth sub-section; wherein, the orthographic projection of the fourth sub-section on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate, the orthographic projection of the fifth sub-section on the substrate overlaps with the orthographic projection of the active layer on the substrate, and the orthographic projection of the sixth sub-section on the substrate does not overlap with the orthographic projection of the active layer on the substrate.

[0015] In a possible implementation manner, the first sub-portion, the second sub-portion, and the third sub-portion all extend along the first direction.

[0016] In a possible implementation, the fifth sub-portion and the sixth sub-portion both extend along the first direction, and the fourth sub-portion extends along the second direction.

[0017] In a possible implementation manner, the active layer is located between the data line layer and the gate line layer.

[0018] In a possible implementation manner, the active layer is located between the data line layer and the first electrode.

[0019] In a possible implementation manner, the first via hole partially exposes the gate line and partially exposes the substrate, and the orthographic projection of the first electrode on the substrate covers the orthographic projection of the first via hole on the substrate.

[0020] In a possible implementation, the insulating layer includes: a gate insulating layer and / or a passivation layer.

[0021] In a possible implementation manner, the gate insulating layer has a thickness of 0.35 μm to 0.45 μm.

[0022] In a possible implementation manner, the gate line layer further includes a gate, and the orthographic projection of the gate on the substrate covers the orthographic projection of the active layer on the substrate.

[0023] In a possible implementation manner, the gate and the gate line are insulated from each other and have a gap therebetween.

[0024] In a possible implementation, the gate line includes a first gate line portion and a second gate line portion arranged along the first direction, wherein an orthographic projection of the first gate line portion on the substrate is located between orthographic projections of adjacent data lines on the substrate, and an orthographic projection of the second gate line portion on the substrate overlaps with an orthographic projection of the data line on the substrate;

[0025] The first gate line portion has a missing portion, and the gate is located in a region where the missing portion is located.

[0026] In a possible embodiment, the first electrode further includes a third sub-electrode portion located between the first sub-electrode portion and the second sub-electrode portion, the orthographic projection of the third sub-electrode portion on the substrate covers the orthographic projection of the gap on the substrate, and the first sub-electrode portion and the second sub-electrode portion are electrically connected through the third sub-electrode portion.

[0027] An embodiment of the present disclosure provides a display device, which includes the array substrate provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1A is a schematic top view of an array substrate according to an embodiment of the present disclosure;

[0029] FIG1B is a schematic cross-sectional view of FIG1A along the dotted line S1;

[0030] FIG1C is another schematic cross-sectional view along the dotted line S1 in FIG1A ;

[0031] FIG1D is a schematic cross-sectional view of FIG1A along the dotted line S2;

[0032] FIG1E is a schematic diagram of a single film layer of the gate line layer in FIG1A ;

[0033] FIG1F is a schematic diagram of a single film layer of the active layer in FIG1A ;

[0034] FIG1G is a schematic diagram of a single film layer of the data line layer in FIG1A ;

[0035] FIG1H is a schematic diagram of a single-sided film formation of the pixel electrode layer in FIG1A ;

[0036] FIG2 is a second schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0037] FIG3 is a third schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0038] FIG. 4 is a fourth schematic top view of an array substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiments of the present invention. It should be noted that the sizes and shapes of the figures in the drawings do not reflect the actual proportions, and the purpose is only to illustrate the contents of the present invention. And the same or similar numbers throughout represent the same or similar elements or elements with the same or similar functions. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the invention belongs. The words "first", "second" and similar terms used in the specification and claims of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0041] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0042] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0043] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0044] In response to the above-mentioned problems existing in the related art, embodiments of the present disclosure provide an array substrate, a manufacturing method thereof, and a flat panel detector.

[0045] The following describes in detail the array substrate, its manufacturing method, and the specific implementation of the flat panel detector provided by the embodiment of the present disclosure in conjunction with the accompanying drawings. The thickness and shape of each film layer in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the content of the present disclosure.

[0046] An embodiment of the present disclosure provides an array substrate, as shown in FIG. 1A to FIG. 1H , wherein FIG. 1B is a schematic cross-sectional view taken along dotted line S1 in FIG. 1A , FIG. 1C is another schematic cross-sectional view taken along dotted line S1 in FIG. 1A , FIG. 1D is a schematic cross-sectional view taken along dotted line S2 in FIG. 1A , FIG. 1E is a schematic diagram of a single film layer of a gate line layer in FIG. 1A , FIG. 1F is a schematic diagram of a single film layer of an active layer in FIG. 1A , FIG. 1G is a schematic diagram of a single film layer of a data line layer in FIG. 1A , and FIG. 1H is a schematic diagram of a single-sided film layer of a pixel electrode layer in FIG. 1A . The array substrate includes:

[0047] Substrate 1;

[0048] The gate line layer 2 is located on one side of the substrate 1 and includes gate lines 20 extending along a first direction X;

[0049] The insulating layer 6 is located on a side of the gate line layer 2 facing away from the substrate 1 and has a first via hole K1 exposing a portion of the gate line 20;

[0050] The first electrode 31 is located on a side of the insulating layer 6 facing away from the gate line layer 2, and includes a first sub-electrode portion 311 and a second sub-electrode portion 312 connected to the first sub-electrode portion 311; the orthographic projection of the first sub-electrode portion 311 on the substrate 1 partially overlaps with the orthographic projection of the gate line 20 on the substrate 1, and the first sub-electrode portion 311 is electrically connected to the gate line 20 through a first via K1;

[0051] The orthographic projection of the active layer 4 and the second sub-electrode portion 312 on the substrate 1 overlaps with the orthographic projection of the active layer 4 on the substrate 1 , and the orthographic projection of the active layer 4 on the substrate 1 does not overlap with the orthographic projection of the gate line 20 on the substrate 1 .

[0052] In the embodiment of the present disclosure, a first electrode 31 is provided on the side of the insulating layer 6 facing away from the gate line layer 2. The first electrode 31 includes a first sub-electrode portion 311 and a second sub-electrode portion 312. The first sub-electrode portion 311 is electrically connected to the gate line 20 through a first via K1. The first electrode 31 can serve as a top gate. There is an insulating layer between the first electrode 31 and the gate line 20. The insulating layer 6 can have a large thickness, which can greatly reduce the coupling capacitance Cgs value, thereby facilitating image quality improvement, and further improving the storage voltage of the positive and negative frames when the pixel is charged, which is caused by the difference in ΔVp due to the pulling of the coupling capacitance or the excessive ΔVp value, resulting in adverse problems such as afterimages or shaking head wrinkles.

[0053] In one possible implementation, as shown in Figures 1A-1H , the array substrate includes a pixel electrode layer, which includes a plurality of pixel electrodes 32. A first electrode 31 is located in the pixel electrode layer and is insulated from the pixel electrodes 32. In the disclosed embodiment, the first electrode 31 is located in the pixel electrode layer, which allows the bottom-gate design to be modified to a top-gate design without increasing the number of mask layers used on the array substrate. This significantly reduces the coupling capacitance Cgs, improves image quality, and alleviates issues such as afterimages and moving head wrinkles.

[0054] In one possible embodiment, referring to FIG. 1A to FIG. 1H , the array substrate further includes a data line layer, which is located between the gate line layer 2 and the first electrode 31 . The data line layer includes: a plurality of data lines 51 extending along the second direction Y; a first transistor electrode 52 connected to one side of the data line 51; and a second transistor electrode 53 disposed opposite the first transistor electrode 52 .

[0055] The first electrode 52 of the transistor includes a first sub-portion 521, a second sub-portion 522, and a third sub-portion 523. One end of the first sub-portion 521 is electrically connected to the data line 51, and the other end is electrically connected to one end of the second sub-portion 522. The other end of the second sub-portion 522 is electrically connected to the third sub-portion 523. The orthographic projection of the second sub-portion 522 on the substrate 1 overlaps with the orthographic projection of the active layer 4 on the substrate 1, and the orthographic projection of the third sub-portion 523 on the substrate 1 does not overlap with the orthographic projection of the active layer 4 on the substrate 1.

[0056] The transistor second electrode 53 includes a fourth sub-section 531, a fifth sub-section 532, and a sixth sub-section 533. The orthographic projection of the fourth sub-section 531 on substrate 1 overlaps with the orthographic projection of the pixel electrode 32 on substrate 1, the orthographic projection of the fifth sub-section 532 on substrate 1 overlaps with the orthographic projection of the active layer 4 on substrate 1, and the orthographic projection of the sixth sub-section 533 on substrate 1 does not overlap with the orthographic projection of the active layer 4 on substrate 1. Specifically, the pixel electrode 32 is electrically connected to the fourth sub-section 531 through the second via K2.

[0057] In conventional designs, in order to ensure that the source and drain electrodes can completely overlap with the active layer when the active layer and the data line layer are offset, the active layer area will be increased, and an active layer tail will exist outside the source and drain electrodes. Tail), so that the active layer completely wraps the source and drain, but this will make the capacitance between the active layer and the gate line larger. In the embodiment of the present disclosure, the first electrode 52 of the transistor includes: a first sub-portion 521, a second sub-portion 522, and a third sub-portion 523, the orthographic projection of the third sub-portion 523 on the substrate 1 and the orthographic projection of the active layer 4 on the substrate 1 do not overlap each other, and the second electrode 53 of the transistor includes: a fourth sub-portion 531, a fifth sub-portion 532, and a sixth sub-portion 533, the orthographic projection of the sixth sub-portion 533 on the substrate 1 and the orthographic projection of the active layer 4 on the substrate 1 do not overlap each other. That is, in the embodiment of the present disclosure, the first electrode 52 of the transistor and the second electrode 53 of the transistor are patterns protruding from the active layer 4 (specifically, by reducing the area of ​​the active layer 4), which can reduce the overlapping area between the active layer 4 and the gate line 20. On the one hand, it can reduce the load on the gate line 20 and improve the charging rate. On the other hand, it can effectively reduce the coupling capacitance Cgs value, which is beneficial to improving image quality.

[0058] In one possible implementation, referring to Figures 1A to 1H , the first sub-portion 521, the second sub-portion 522, and the third sub-portion 523 all extend along the first direction X. Compared to a case where the first electrode 52 of the transistor includes a structure parallel to the data line 51, as shown in Figure 2 , the gate line 20 has limited space to be set at this position, has a narrow line width, and has a large resistance, which is not conducive to signal transmission. In the embodiment of the present disclosure, the first electrode 52 of the transistor is designed to be perpendicular to the data line 51. The first electrode 52 of the transistor can occupy a smaller area, and more space can be reserved for the gate line 20, thereby avoiding the problem that the line resistance of the gate line 20 at this position is too large, which is not conducive to signal transmission.

[0059] In one possible implementation, as shown in Figures 1A-1H , the fifth sub-portion 532 and the sixth sub-portion 533 both extend along the first direction X, and the fourth sub-portion 531 extends along the second direction Y. In the disclosed embodiment, the fifth sub-portion 532 and the sixth sub-portion 533 both extend along the first direction X, which allows the second electrode 53 of the transistor to occupy a smaller area, leaving more space for the gate line 20, thereby avoiding the problem of excessive line resistance of the gate line 20 at this location, which is not conducive to signal transmission. The fourth sub-portion 531 extends along the second direction Y to achieve electrical connection with the pixel electrode 32.

[0060] In a possible implementation, referring to FIG2 , in the embodiment of the present disclosure, the first electrode 52 of the transistor and the second electrode 53 of the transistor may also extend along the second direction Y. By setting the first electrode 31, the coupling capacitance Cgs value can be greatly reduced with minor changes to the array substrate, thereby facilitating image quality improvement and improving adverse issues such as afterimages or shaking head wrinkles.

[0061] In a possible implementation, as shown in FIG3 , in the embodiment of the present disclosure, the first electrode 52 of the transistor and the second electrode 53 of the transistor can also be set as a pattern protruding from the active layer 4 (specifically, by reducing the area of ​​the active layer 4) only on the basis of a conventional array substrate, so as to reduce the overlapping area between the active layer 4 and the gate line 20. On the one hand, it can reduce the load on the gate line 20 and improve the charging rate. On the other hand, it can effectively reduce the coupling capacitance Cgs value, which is beneficial to improving image quality.

[0062] In a possible implementation, referring to FIG. 1B , the active layer 4 is located between the data line layer and the gate line layer 2 .

[0063] In a possible implementation, referring to FIG. 1C , the active layer 4 is located between the data line layer and the first electrode 31 .

[0064] In one possible embodiment, as shown in FIG1D , the first via K1 partially exposes the gate line 20 and partially exposes the substrate 1, and the orthographic projection of the first electrode 31 on the substrate 1 covers the orthographic projection of the first via K1 on the substrate 1. In the disclosed embodiment, the first via K1 partially exposes the gate line 20 and partially exposes the substrate 1, forming a semi-via design. A stepped structure is formed within the first via K to drain the alignment liquid, preventing it from sticking and avoiding the appearance of moiré patterns on the image.

[0065] In a possible implementation, the first via hole K1 may also expose only a portion of the gate line 20 , forming a full via hole design, so as to improve the process yield.

[0066] In one possible embodiment, as shown in Figures 1B-1D , the insulating layer 6 includes: a gate insulating layer 61 and / or a passivation layer 62. Specifically, the insulating layer 6 may include: a gate insulating layer 61 and a passivation layer 62. The passivation layer 62 may be located on the side of the gate insulating layer 61 facing away from the substrate 1. The thickness of the passivation layer 62 can be adjusted over a wide range, typically around 0.1μm to 0.7μm. Its thickness can be much higher than that of the gate insulating layer 61. Therefore, the top gate design is more conducive to significantly reducing the coupling capacitance Cgs value, thereby improving image quality.

[0067] In a possible embodiment, as shown in FIG1A to FIG1H , the thickness of the gate insulating layer 61 is 0.35 μm to 0.45 μm. In the embodiment of the present disclosure, the thickness of the gate insulating layer 61 is relatively large, and according to the formula As can be seen, increasing the thickness of the gate insulating layer 61 reduces the overlap capacitance between the active layer and the gate line 20, that is, reduces the Cgs value, thereby reducing the ΔVp value and improving image quality. However, the thickness of the gate insulating layer 61 generally has a significant impact on the process yield, and the thickness is usually fixed. Therefore, based on process yield, the gate insulating layer 61 can be adjusted to a lower thickness, usually around 0.35μm to 0.45μm.

[0068] In a possible implementation, as shown in FIG4 , in the embodiment of the present disclosure, the gate insulating layer 61 between the active layer 4 and the gate line layer 2 may be thickened only on the basis of a conventional array substrate to increase the thickness of the gate insulating layer 61 and reduce the overlapping capacitance between the active layer and the gate line 20, that is, the Cgs value is reduced, thereby reducing the ΔVp value and improving the image quality.

[0069] In one possible implementation, referring to Figures 1A-1H , the gate line layer further includes a gate 23, the orthographic projection of the gate 23 on the substrate 1 covering the orthographic projection of the active layer 4 on the substrate 1. In the disclosed embodiment, the gate line layer further includes a gate 23, which can be formed at the same time as the gate line 20 is formed. The gate 23 can be set to a floating state, with no voltage applied and no connection to other gate layer metals. The purpose is to shield the active layer 4 (the active layer 4 can be A-Si, which is not suitable for light exposure) from light and protect the characteristics of the active layer 4.

[0070] In one possible embodiment, as shown in Figures 1A to 1H, the gate 23 and the gate line 20 are insulated from each other and have a gap P. In the embodiment of the present disclosure, the gate 23 and the gate line 20 are insulated from each other and have a gap P to avoid that when the gate 23 and the gate line 20 are connected together, the gate 23 will be completely co-pressed with the gate line 20, and a large amount of parasitic capacitance will be generated between the gate 23 and the upper transistor (including the active layer, the first pole of the transistor, and the second pole of the transistor). The pixel load and the coupling capacitance Cgs value will increase significantly, which is not conducive to display quality. Specifically, the minimum length of the gap P in the first direction X is more than 6um to avoid that the gate 23 and the gate line 20 cannot be completely etched and disconnected due to being too close.

[0071] In a possible embodiment, referring to Figures 1A-1H, the gate line 20 includes a first gate line portion 201 arranged along a first direction X, and a second gate line portion 202, wherein the orthographic projection of the first gate line portion 201 on the substrate 1 is located between the orthographic projections of adjacent data lines 51 on the substrate 1, and the orthographic projection of the second gate line portion 202 on the substrate 1 overlaps with the orthographic projection of the data line 51 on the substrate 1; the first gate line portion 201 has a missing portion Q, and the gate 23 is located in the area where the missing portion Q is located.

[0072] In a possible embodiment, referring to Figures 1A-1H, the first electrode 31 also includes a third sub-electrode portion 313 located between the first sub-electrode portion 311 and the second sub-electrode portion 312, the orthographic projection of the third sub-electrode portion 313 on the substrate 1 covers the orthographic projection of the gap P on the substrate 1, and the first sub-electrode portion 311 and the second sub-electrode portion 312 are electrically connected through the third sub-electrode portion 313.

[0073] In a possible embodiment, as shown in the figure, the array substrate may further include a common electrode 7 located between the substrate 1 and the gate line layer 2; specifically, the array substrate may further include a common electrode lead 24 located in the gate line layer 2, the common electrode lead 24 is in direct contact with and overlapped with the common electrode 7, the common electrode lead 24 is located in the gate line layer 2, the gate line layer 2 is generally made of metal with low resistivity and strong conductivity, the common electrode lead 24 runs through the pixel row, and can enhance the uniformity of the overall voltage of the common electrode 7 on the display panel.

[0074] Based on the same inventive concept, the embodiments of the present disclosure also provide a display device, which includes an array substrate as provided in the embodiments of the present disclosure. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, etc. Other essential components of the display device should be understood by those of ordinary skill in the art and will not be described in detail here, nor should they be used as limitations on the present invention. In addition, since the principle of solving the problem by the display device is similar to the principle of solving the problem by the above-mentioned display panel, the implementation of the display device can refer to the embodiment of the above-mentioned liquid crystal display panel, and the repeated parts will not be described in detail.

[0075] It should be noted that in this disclosure, "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for producing a specific pattern, and then using the same mask through a single patterning process. That is, one patterning process corresponds to one mask (also known as a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0076] In some embodiments, the pixel electrode layer can be a transparent structure, and the material of the pixel electrode layer includes metal oxide (e.g., indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide, etc.

[0077] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0078] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; A gate line layer, located on one side of the substrate, comprising gate lines extending along a first direction; An insulating layer, located on a side of the gate line layer facing away from the substrate, and having a first via hole exposing a portion of the gate line; A first electrode, located on a side of the insulating layer away from the gate line layer, comprising a first sub-electrode portion and a second sub-electrode portion connected to the first sub-electrode portion; The orthographic projection of the first sub-electrode portion on the substrate partially overlaps with the orthographic projection of the gate line on the substrate, and the first sub-electrode portion is electrically connected to the gate line through the first via hole; The orthographic projection of the second sub-electrode portion on the substrate overlaps with the orthographic projection of the active layer on the substrate, and the orthographic projection of the active layer on the substrate does not overlap with the orthographic projection of the gate line on the substrate.

2. The array substrate according to claim 1, wherein: The array substrate comprises a pixel electrode layer, and the pixel electrode layer comprises a plurality of pixel electrodes; the first electrode is located in the pixel electrode layer and is insulated from the pixel electrodes.

3. The array substrate according to claim 2, wherein: The array substrate further comprises a data line layer, and the data line layer is located between the gate line layer and the first electrode; The data line layer includes: a plurality of data lines extending along the second direction, a first electrode of a transistor connected to one side of the data line, and a second electrode of a transistor arranged opposite to the first electrode of the transistor; The first electrode of the transistor includes: a first sub-section, a second sub-section, and a third sub-section; wherein one end of the first sub-section is electrically connected to the data line, and the other end is electrically connected to one end of the second sub-section, and the other end of the second sub-section is electrically connected to the third sub-section; the orthographic projection of the second sub-section on the substrate overlaps with the orthographic projection of the active layer on the substrate, and the orthographic projection of the third sub-section on the substrate does not overlap with the orthographic projection of the active layer on the substrate; The second electrode of the transistor includes: a fourth sub-section, a fifth sub-section, and a sixth sub-section; wherein the orthographic projection of the fourth sub-section on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate, the orthographic projection of the fifth sub-section on the substrate overlaps with the orthographic projection of the active layer on the substrate, and the orthographic projection of the sixth sub-section on the substrate does not overlap with the orthographic projection of the active layer on the substrate.

4. The array substrate according to claim 3, wherein: The first sub-portion, the second sub-portion, and the third sub-portion all extend along the first direction.

5. The array substrate according to claim 3 or 4, wherein: The fifth sub-portion and the sixth sub-portion both extend along the first direction, and the fourth sub-portion extends along the second direction.

6. The array substrate according to any one of claims 3 to 5, wherein: The active layer is located between the data line layer and the gate line layer.

7. The array substrate according to any one of claims 3 to 5, wherein: The active layer is located between the data line layer and the first electrode.

8. The array substrate according to any one of claims 1 to 7, wherein: The first via hole partially exposes the gate line and partially exposes the substrate, and the orthographic projection of the first electrode on the substrate covers the orthographic projection of the first via hole on the substrate.

9. The array substrate according to any one of claims 1 to 8, wherein: The insulating layer includes: a gate insulating layer and / or a passivation layer.

10. The array substrate according to any one of claims 1 to 9, wherein: The gate insulating layer has a thickness of 0.35 μm to 0.45 μm.

11. The array substrate according to any one of claims 1 to 10, wherein: The gate line layer further includes: a gate, and the orthographic projection of the gate on the substrate covers the orthographic projection of the active layer on the substrate.

12. The array substrate according to claim 11, wherein: The gate and the gate line are insulated from each other and have a gap therebetween.

13. The array substrate according to claim 12, wherein: The gate line comprises a first gate line portion and a second gate line portion arranged along the first direction, wherein an orthographic projection of the first gate line portion on the substrate is located between orthographic projections of adjacent data lines on the substrate, and an orthographic projection of the second gate line portion on the substrate overlaps an orthographic projection of the data line on the substrate; The first gate line portion has a missing portion, and the gate is located in a region where the missing portion is located.

14. The array substrate according to claim 12, wherein: The first electrode also includes a third sub-electrode portion located between the first sub-electrode portion and the second sub-electrode portion, the orthographic projection of the third sub-electrode portion on the substrate covers the orthographic projection of the gap on the substrate, and the first sub-electrode portion and the second sub-electrode portion are electrically connected via the third sub-electrode portion.

15. A display device, wherein: It comprises the array substrate as described in any one of claims 1 to 14.

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