High-energy efficiency, low-power consumption passive radio frequency identification tag chip

Abstract

A high-energy efficiency, low-power consumption passive radio frequency identification tag chip. A high-energy efficiency bridge rectifier circuit is constructed in an analog circuit portion by using an NMOS transistor, and an alternating-current voltage signal is converted into a direct-current signal. Meanwhile, a three-stage amplitude-limiting circuit is added to prevent an induced voltage from being too large and thus breaking down a transistor. The load at two ends of an antenna is changed by using an encoded signal to control the MOS transistor turning on and off, and then voltage values at the two ends of the antenna are adjusted by controlling a leakage current, achieving the purposes of load modulation and signal transmission. High-precision, high-speed decoding is achieved at a digital circuit portion by using a pulse position modulation decoder. The encoded signal is generated by using a Manchester encoder based on FSM control. An anti-collision circuit is used to handle a possible situation in which a plurality of RFID tags simultaneously exist in an interrogation zone. A uniquely designed read timing control circuit is used in an EEPROM memory portion, so that the power consumption of the circuit may be effectively reduced. The described chip has the characteristics of high energy efficiency, low power consumption, and low adjustment index, and is widely applied to the field of RFID identification.

Description

A high-efficiency, low-power passive radio frequency identification tag chip Technical Field

[0001] The present invention relates to the field of radio frequency identification technology, and in particular to a high-energy-efficiency and low-power-consumption passive radio frequency identification tag chip. Background Art

[0002] Radio Frequency Identification (RFID) is a wireless communication technology that uses radio frequency signals to transmit information contactlessly through electromagnetic fields, and then uses this information to identify individuals. RFID technology is widely used in industries such as manufacturing, logistics, and public services.

[0003] The core of RFID technology is the RFID tag, which exchanges information with the RFID reader / writer via radio frequency signals. Existing high-frequency passive RFID identification chips primarily consist of three components: RF analog circuitry, digital circuitry, and EEPROM memory. High-frequency passive RFID tags derive their energy from electromagnetic waves emitted by the RFID reader / writer through antenna inductive coupling. Therefore, the operating range of RFID tags is primarily limited by the energy conversion efficiency and ultra-low modulation index signal demodulation capabilities of the tag chip's RF analog circuitry. Furthermore, the power consumption of the digital circuitry and the electrically erasable programmable read-only memory (EEPROM) is also a major limitation.

[0004] Summary of the Invention

[0005] In view of this, an embodiment of the present invention provides a high-efficiency, low-power passive radio frequency identification tag chip.

[0006] A first aspect of the present invention provides a high energy efficiency and low power consumption passive radio frequency identification tag chip, comprising a radio frequency analog circuit, a digital circuit and an EEPROM memory;

[0007] The radio frequency analog circuit specifically includes a bridge rectifier circuit, a three-stage limiter circuit, a resistive load modulation circuit, an ASK demodulation circuit, a linear voltage regulator circuit and a clock extraction circuit; the bridge rectifier circuit is used to convert the input signals ant1 and ant2 of the RFID tag antenna into VHD DC signals, and provide the VHD DC signals to the radio frequency analog circuit, the digital circuit and the EEPROM memory; the three-stage limiter circuit is used to discharge the VHD DC signal output of the bridge rectifier circuit according to the field strength; the linear voltage regulator circuit is used to stabilize the VHD DC signal output of the bridge rectifier circuit and output a VDD stabilized voltage signal to the digital circuit and the EEPROM memory; the resistive load modulation circuit is used to load modulate the input signals ant1 and ant2; the ASK demodulation circuit is used to generate an ASK encoded signal according to the input signals ant1 and ant2 and input it into the digital circuit; the clock extraction circuit is used to generate a clock signal and input it into the digital circuit;

[0008] The digital circuit specifically includes a Manchester encoder, a pulse position modulation decoder, and an anti-collision circuit; the pulse position modulation decoder is used to generate a logic signal according to the ASK encoding signal and the clock signal; the Manchester encoder is used to generate a Manchester encoding signal; and the anti-collision circuit is used to detect collisions generated by RFID tags;

[0009] The EEPROM memory is used to store the logic signal output by the pulse position modulation decoder.

[0010] Furthermore, the bridge rectifier circuit includes NMOS transistors MN1, MN2, MN3, and MN4 and a storage capacitor CVHD; wherein the drain and gate of MN1, the gate of MN4, and the drain of MN3 are connected to the input signal ant1, and the drain and gate of MN2, the gate of MN3, and the drain of MN4 are connected to the input signal ant2; the sources of MN1 and MN2 form a VHD output, and the sources of MN3 and MN4 are connected to signal ground; the input signals ant1 and ant2 are obtained from the RFID tag antenna;

[0011] When the input signal ant1 inputs a high level signal and the input signal ant2 inputs a low level signal, MN1 and MN4 are turned on, connecting the C between the VHD output and the signal ground. VHD Charge and form VHD DC signal output;

[0012] When the input signal ant1 inputs a low level signal and the input signal ant2 inputs a high level signal, MN2 and MN3 are turned on, connecting the C between the VHD output and the signal ground. VHD Charge and form VHD DC signal output.

[0013] Furthermore, the three-stage amplitude limiting circuit includes a first amplitude limiting circuit, a second amplitude limiting circuit and a third amplitude limiting circuit; the inputs of the first amplitude limiting circuit and the second amplitude limiting circuit are connected through a resistor R BC Isolation; the input of the second and third limiter circuits are connected through resistor R AB Isolation; each limiter circuit includes a turn-on resistor, a limiter PMOS transistor, a leakage branch, a high-pass filter, and a leakage tube; wherein the high-pass filter is composed of a resistor and a capacitor connected in series and is used to filter the noise input to the limiter circuit; the leakage tube is composed of two discharge NMOS transistors, the drains of the two discharge NMOS transistors are respectively input with signals ant1 and ant2, the sources are connected to the signal ground, and the gates are connected to the output of the leakage branch;

[0014] The first leakage branch in the first limiting circuit includes five PMOS tubes with gates and drains connected, the drain output of the previous PMOS tube is connected to the source input of the next PMOS tube, and the drain of the last PMOS tube outputs the first turn-on voltage;

[0015] The second leakage branch in the second limiting circuit includes four PMOS tubes with gates and drains connected, the drain output of the previous PMOS tube is connected to the source input of the next PMOS tube, and the drain of the last PMOS tube outputs the second turn-on voltage;

[0016] The third leakage branch in the third limiting circuit includes three PMOS tubes with gates and drains connected, the drain output of the previous PMOS tube is connected to the source input of the next PMOS tube, and the drain of the last PMOS tube outputs a third turn-on voltage;

[0017] When the field strength of the RF analog circuit exceeds the threshold voltage of the limiting PMOS tube in the third limiting circuit, the limiting PMOS tube is turned on to generate a third turn-on voltage; when the third turn-on voltage exceeds the threshold voltage of the discharge NMOS tube in the leakage tube of the third limiting circuit, the leakage tube of the third limiting circuit starts to discharge current;

[0018] When the field strength of the RF analog circuit exceeds the threshold voltage of the limiting PMOS tube in the second limiting circuit, the limiting PMOS tube is turned on to generate a second turn-on voltage; when the second turn-on voltage exceeds the threshold voltage of the discharge NMOS tube in the leakage tube of the second limiting circuit, the leakage tube of the second limiting circuit starts to discharge current;

[0019] When the field strength of the RF analog circuit exceeds the threshold voltage of the limiting PMOS tube in the first limiting circuit, the limiting PMOS tube is turned on to generate a first turn-on voltage; when the first turn-on voltage exceeds the threshold voltage of the discharge NMOS tube in the leakage tube of the first limiting circuit, the leakage tube of the first limiting circuit starts to discharge current.

[0020] Furthermore, the resistive load modulation circuit includes a modulation control circuit and a level conversion circuit; the modulation control circuit receives a Manchester coded signal; the output of the modulation control circuit is connected to the input of the level conversion circuit, and the output of the level conversion circuit is connected to the antenna resonant circuit;

[0021] The modulation control circuit is composed of two inverters consisting of PMOS transistors MP11 and MP12 and NMOS transistors MN11 and MN12, which are used to provide binary-coded control signals for the level conversion circuit; the level conversion circuit generates a high-level or low-level signal according to the control signal, and adds the modulation signal dem_in to the input signals ant1 and ant2.

[0022] Furthermore, the linear voltage stabilization circuit includes a startup circuit, a reference current source, a mirror circuit and a regulation circuit;

[0023] The startup circuit includes a resistor R21, a PMOS transistor MP21, and NMOS transistors MN21 and MN22; the startup circuit is used to provide an initial voltage to the reference current source;

[0024] The reference current source includes a diode B21, a resistor R22, NMOS transistors MN23, MN24 and PMOS transistors MP22, MP23; the reference current source is used to generate a reference current I1 according to the initial voltage;

[0025] The mirror circuit includes PMOS transistors MP24 and MP25 and NMOS transistors MN25, MN26 and MN27, and is used to generate a mirror current I4 according to the reference current I1;

[0026] The regulating circuit includes PMOS transistors MP26 and MP27, and is used for performing feedback regulation on the output VDD voltage stabilization signal.

[0027] Furthermore, the ASK demodulation circuit includes an envelope extraction circuit, a pre-amplification circuit, a post-amplification circuit and a decision circuit;

[0028] The extraction circuit includes a resistor divider, a first low-pass filter and a second low-pass filter; the resistor divider is used to divide the input signals ant1 and ant2 so that the voltage of the input signal matches the operating voltage of the first low-pass filter and the second low-pass filter; the first low-pass filter is used to extract the first envelope signal V from the input signals ant1 and ant2 fast The second low-pass filter is used to extract the second envelope signal V from the input signals ant1 and ant2. slow ;

[0029] The pre-amplifier circuit is used to amplify the first envelope signal Vfast and the second envelope signal V slow , get the first amplified signal V r1 and the second amplified signal V s1 The post-amplification circuit is used to amplify the first signal V r1 and the second amplified signal V s1 Perform secondary amplification to obtain the third amplified signal V r and the fourth amplified signal V s The decision circuit is used according to the third amplified signal V r and the fourth amplified signal V s An ASK encoded signal is generated to be input into the digital circuit.

[0030] Furthermore, the pulse position modulation decoder includes a synchronization circuit, an SOF / EOF detection circuit, a 9-bit counter, a decoding circuit, a shift register, and an FSM circuit; the synchronization circuit is used to synchronize the ASK encoded signal and the clock signal; the SOF / EOF detection circuit is used to detect the start frame and end frame of the ASK encoded signal; the 9-bit counter is used to generate a logic signal according to the ASK encoded signal; the decoding circuit and the shift register are used to decode and output the logic signal; the FSM circuit is used to control the operating status of the pulse position modulation decoder and the Manchester encoder;

[0031] The pulse position modulation decoder performs decoding by the following steps:

[0032] Synchronously processing the ASK coded signal and the clock signal;

[0033] Comparing the ASK coded signal with a clock signal to determine the relative time of the ASK coded signal pulse position;

[0034] Determine the start frame and end frame of the ASK encoded signal;

[0035] Inputting the ASK encoded signal into a 9-bit counter, the 9-bit counter comparing the count value of the ASK encoded signal with a preset threshold at the end of a clock cycle of the clock signal, and generating a logic signal 0 when the count value is less than the preset threshold; and generating a logic signal 1 when the count value is greater than the preset threshold;

[0036] The logic signal is decoded and outputted through the decoding circuit and the shift register.

[0037] Furthermore, the Manchester encoder supports the use of one or two subcarriers;

[0038] When one subcarrier is used, the Manchester-encoded signal dout generated by the Manchester encoder has a subcarrier frequency of f / 32;

[0039] When two subcarriers are used, the Manchester-encoded signal dout generated by the Manchester encoder has a subcarrier frequency that is a combination of f / 32 and f / 28.

[0040] Furthermore, the anti-collision circuit is implemented by one of the following methods:

[0041] The time slots are divided into several time slots. Each RFID tag sends its own ID information in different time slots. The anti-collision circuit determines whether a collision occurs based on the read ID information.

[0042] The ID information of the RFID tag is converted into a binary number and inverted from high to low according to the number of bits. The anti-collision circuit determines whether a collision occurs based on the read ID information;

[0043] The ID information of the RFID tag is stored in a query tree and queried according to preset rules. The anti-collision circuit determines whether a collision occurs based on the query result;

[0044] A hash function is used to map the ID information of the RFID tag to a unique hash value, and identification and differentiation are performed based on the hash value. The anti-collision circuit determines whether a collision occurs based on the received hash value.

[0045] Furthermore, the EEPROM memory includes a storage cell array, an erase circuit, a read circuit and a charge pump; the erase circuit is used to control the erase of the storage cell array; the read circuit is used to control the read of the storage cell array; and the charge pump is used to generate an erase signal to erase the storage cell array.

[0046] The present invention has the following beneficial effects: In the analog circuit portion, the present invention utilizes NMOS transistors to construct a high-efficiency bridge rectifier circuit to convert the AC voltage signal coupled from both ends of the antenna into a DC signal; a three-stage limiting circuit is added to prevent the induced voltage from being too large and subsequently breaking down the transistor connected to the antenna; a coded signal is used to control the on and off of the MOS transistor to change the load at both ends of the antenna, and then the voltage value at both ends of the antenna is adjusted by controlling the leakage current, thereby achieving the purpose of load modulation and signal transmission. In the digital circuit portion, the present invention utilizes a pulse position modulation decoder to achieve high-precision and high-speed decoding; a Manchester encoder based on FSM control is used to generate Manchester coded signals; and an anti-collision circuit is used to handle the situation where multiple RFID tags may be present in the interrogation area at the same time. In the EEPROM memory portion, the present invention avoids the use of a high-power reference source and adopts a uniquely designed read timing control circuit to effectively reduce circuit power consumption. Simulation results show that the high-efficiency, low-power passive radio frequency identification tag chip designed by the present invention has the characteristics of high energy efficiency, low power consumption, and a low adjustment index.

[0047] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0049] FIG1 is a general structural diagram of a high-efficiency, low-power passive radio frequency identification tag chip according to the present invention;

[0050] FIG2 is a structural diagram of a partial analog circuit of a high-efficiency, low-power passive radio frequency identification tag chip according to the present invention;

[0051] FIG3 is a structural diagram of a high-efficiency, low-power passive RFID tag chip bridge rectifier circuit according to the present invention;

[0052] FIG4 is a diagram showing one of the three-stage limiting circuit structures of a high-efficiency, low-power passive radio frequency identification tag chip according to the present invention;

[0053] FIG5 is a second structural diagram of a three-stage limiting circuit of a high-efficiency, low-power passive radio frequency identification tag chip according to the present invention;

[0054] FIG6 is a structural diagram of a load modulation circuit of a high-efficiency and low-power passive radio frequency identification tag chip according to the present invention;

[0055] FIG7 is a structural diagram of a linear voltage stabilization circuit of a high-efficiency, low-power passive radio frequency identification tag chip according to the present invention;

[0056] FIG8 is a structural diagram of an ASK demodulation circuit of a high-efficiency and low-power passive radio frequency identification tag chip according to the present invention;

[0057] Figure 9 is a diagram showing the structure of a pulse position modulation decoder for a high energy efficiency and low power consumption passive RFID tag chip according to the present invention.

[0058] 10 is a diagram showing a structure of a synchronization circuit in a pulse position modulation decoder of a high-efficiency and low-power passive radio frequency identification tag chip according to the present invention;

[0059] FIG11 is a structural diagram of a Manchester encoder of a high-efficiency and low-power passive radio frequency identification tag chip according to the present invention;

[0060] FIG12 is a schematic diagram of parsing carrier frequency in a Manchester encoder of a high-efficiency, low-power passive radio frequency identification tag chip according to the present invention;

[0061] FIG13 is a structural diagram of an anti-collision circuit of a high-efficiency, low-power passive radio frequency identification tag chip according to the present invention;

[0062] FIG14 is a diagram showing the structure of an EEPROM memory of a high-efficiency, low-power passive radio frequency identification tag chip according to the present invention. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0064] The high-efficiency and low-power passive RFID tag chip of the embodiment of the present invention mainly includes three parts: a high-efficiency and ultra-low modulation index RF analog circuit, a low-power digital circuit, and a low-power EEPROM memory. The chip structure is shown in Figure 1.

[0065] As shown in Figure 2, the RF analog circuit portion of the high-efficiency, low-power passive RFID tag chip according to an embodiment of the present invention mainly includes: a bridge rectifier circuit, a three-stage limiter circuit, a resistive load modulation circuit, a linear voltage regulator (LDO, Low Dropout Regulator) circuit, a clock extraction circuit, and an amplitude shift keying (ASK, Amplitude Shift Keying) demodulation circuit.

[0066] The low-power digital circuit part of the high-frequency passive radio frequency identification tag chip of the present invention mainly includes: a pulse position modulation (PPM) decoder, a Manchester encoder and an anti-collision circuit.

[0067] The low-power EEPROM memory part of the high-frequency passive radio frequency identification tag chip of the present invention mainly comprises: an EEPROM erasing circuit, an EEPROM reading circuit and a charge pump.

[0068] Bridge Rectifier Circuit: In this embodiment, the bridge rectifier circuit converts the RFID tag antenna's input signals, ant1 and ant2, into VHD DC signals, which are then supplied to the RF analog circuit, digital circuit, and EEPROM memory. Specifically, because the signals ant1 and ant2 coupled from the RFID tag antenna are sinusoidal waves, representing alternating voltages, they cannot directly power the analog and digital circuits. Therefore, additional circuitry is required to convert the AC signals into DC signals. Therefore, a bridge rectifier circuit is used for this signal conversion.

[0069] As shown in FIG3 , the bridge rectifier circuit of this embodiment includes NMOS transistors MN1, MN2, MN3, and MN4 and a storage capacitor CVHD. The drain and gate of MN1, the gate of MN4, and the drain of MN3 are connected to the input signal ant1, and the drain and gate of MN2, the gate of MN3, and the drain of MN4 are connected to the input signal ant2. The sources of MN1 and MN2 form a VHD output, and the sources of MN3 and MN4 are connected to signal ground. The input signals ant1 and ant2 are obtained from the RFID tag antenna.

[0070] In particular, since the input signals ant1 and ant2 are not necessarily continuous signals, in the gaps where the signals are interrupted (i.e. when a groove appears), the energy storage capacitor C VHD The power supply work at the gap is completed, and at the same time the energy storage capacitor CVHD can also stabilize the VHD DC signal.

[0071] When the input signal ant1 inputs a high level signal and the input signal ant2 inputs a low level signal, MN1 and MN4 are turned on, connecting the C between the VHD output and the signal ground. VHD Charge and form VHD DC signal output;

[0072] When the input signal ant1 inputs a low level signal and the input signal ant2 inputs a high level signal, MN2 and MN3 are turned on, connecting the C between the VHD output and the signal ground. VHD Charge and form VHD DC signal output.

[0073] Since the carrier of the input signal always exists during the operation of the bridge rectifier circuit, a relatively stable VHD voltage can be formed, and the energy storage capacitor C VHD During the charging and discharging process, VHD is always DC, thus achieving the purpose of converting AC signals into DC signals.

[0074] Since the voltage value of the rectified VHD DC signal may still exceed the critical value of the MOS breakdown voltage, a limiting circuit must be further provided to protect the circuit at high field strengths.

[0075] As shown in Figures 4 and 5, the three-stage limiter circuit in this embodiment includes a first limiter circuit level 1, a second limiter circuit level 2, and a third limiter circuit level 3. The inputs of the first limiter circuit level 1 and the second limiter circuit level 2 are isolated by a resistor RBC, while the inputs of the second limiter circuit level 2 and the third limiter circuit level 3 are isolated by a resistor RAB. Each limiter circuit includes a turn-on resistor, a limiter PMOS transistor (MPc, MPb, MPa), a leakage branch, a high-pass filter, and a leakage tube. The high-pass filter is composed of series-connected resistors and capacitors R1 and C1, R2 and C2, and R3 and C3, and is used to filter ripple noise on the VHD. The leakage tube is composed of two discharge NMOS transistors MN1c and MN2c, MN1b and MN2b, and MN1a and MN2a. The drains of the two discharge NMOS transistors are respectively input with signals ant1 and ant2, their sources are connected to signal ground, and their gates are connected to the output of the leakage branch.

[0076] The first leakage branch in the first limiter circuit level 1 includes five PMOS transistors MP1c, MP2c, MP3c, MP4c, and MP5c with gates connected to drains. The drain output of the previous PMOS transistor is connected to the source input of the next PMOS transistor, and the drain of the last PMOS transistor MP5c outputs the first turn-on voltage V T1 ;

[0077] The second leakage branch in the second limiting circuit level 2 includes four PMOS transistors MP1b, MP2b, MP3b, and MP4b with gates connected to drains. The drain output of the preceding PMOS transistor is connected to the source input of the succeeding PMOS transistor. The drain of the last PMOS transistor MP4b outputs the second turn-on voltage V T2 ;

[0078] The third leakage branch in the third limiting circuit level 3 includes three PMOS transistors MP1a, MP2a, and MP3a with gates connected to drains. The drain output of the preceding PMOS transistor is connected to the source input of the succeeding PMOS transistor. The drain of the last PMOS transistor MP3a outputs a third turn-on voltage V T3 .

[0079] Specifically, the RF analog circuit of this embodiment obtains a total current I after mutual inductance coupling and rectification. I is divided into two branches. One current flows through the LDO to provide the required current to the subsequent load modulation circuit, and the remaining current is released through the three-stage limiting circuit. Since the total current of the RF analog circuit I = I LDO +I a +I b +I c , if the required load current I LDO decreases, then the remaining current can flow through Ia , I b and I c Bleeder, if the required load current I LDO Increase, then the required load current can be achieved by reducing the leakage current value. a , I b and I c When the load current I is almost 0 LDO Reached maximum value.

[0080] The field strength of the RF analog circuit is calculated using the following formula:

[0081] Where x is the vertical distance between the antenna and the antenna interface, a and b are the side lengths of the antenna, N is the number of antenna coils, and I is the current flowing through the antenna.

[0082] The current discharge of the three-stage limiting circuit of this embodiment is performed through the following steps:

[0083] When the field strength H of the RF analog circuit exceeds the threshold voltage V of the limiting PMOS tube in the third limiting circuit level 3, Aon When the amplitude limiting PMOS tube MPa is turned on, the current formed passes through the resistor R2a to generate the third turn-on voltage V T3 ; When the third turn-on voltage V T3 When the voltage exceeds the threshold voltage of the discharge NMOS tube in the leakage tube of the third limiter circuit, the leakage tube of the third limiter circuit level 3 starts to discharge the excess current I a Release.

[0084] When the third limiter circuit level 3 starts to discharge current, due to the resistance R AB The voltage of the second limiting circuit level 2 gradually increases. When the field strength H of the RF analog circuit exceeds the threshold voltage V of the limiting PMOS tube in the second limiting circuit Bon When the limiter PMOS tube MPB is turned on, the current generated by the resistor R2b generates the second turn-on voltage V T2 ; When the second turn-on voltage V T2 When the voltage exceeds the threshold voltage of the discharge NMOS tube in the leakage tube of the second amplitude limiting circuit, the leakage tube of the second amplitude limiting circuit level 2 starts to discharge the excess current I b Release;

[0085] When the second limiter circuit level 2 starts to discharge current, due to the resistance R BC The voltage of the first limiter circuit level 1 gradually increases. When the field strength H of the RF analog circuit exceeds the threshold voltage V of the limiter PMOS tube in the first limiter circuit, ConWhen the amplitude limiting PMOS tube MPc is turned on, the generated current passes through the resistor R2c to generate the first turn-on voltage V T1 ; When the first turn-on voltage V T1 When the voltage exceeds the threshold voltage of the discharge NMOS tube in the leakage tube of the first amplitude limiting circuit, the leakage tube of the first amplitude limiting circuit level 1 starts to discharge the excess current I c Release.

[0086] This embodiment uses a three-level limiting circuit to achieve current and voltage regulation at different field intensities. For example, at low field strength (such as 1.5A / m), all leakage tubes are in a closed state, and all current is supplied to the subsequent circuit. At medium field strength (such as 3A / m), the third limiting circuit level 3 is turned on, and part of the unused current is passed through I a For high field strength (such as 7.5A / m), all limiting circuits are turned on to discharge a larger current to protect the transistor from being broken down due to too high operating voltage.

[0087] As shown in FIG6 , the resistive load modulation circuit of this embodiment includes a modulation control circuit and a level conversion circuit. The modulation control circuit receives a Manchester-coded signal. The output of the modulation control circuit is connected to the input of the level conversion circuit, and the output of the level conversion circuit is connected to the antenna resonant circuit.

[0088] The modulation control circuit, consisting of two inverters formed by PMOS transistors MP11 and MP12 and NMOS transistors MN11 and MN12, is used to provide a binary-coded control signal to the level conversion circuit. The level conversion circuit generates a high-level or low-level signal based on the control signal and adds the modulation signal dem_in to the input signals ant1 and ant2. Specifically, when the digital circuit outputs dout at a low level, MN13 and MP14 are both turned on, causing node A to be at a high level, MN15 and MN16 to conduct, and current will flow from the RFID antenna to R4 and R5. A modulation signal of several millivolts will be applied to the carrier. When the load modulation circuit is turned on, MP16 is short-circuited by MP15 and MN13, and the on-state voltage of node B will increase by 1V. TH , the amplitude of load modulation deepens.

[0089] As shown in FIG7 , the linear voltage stabilization circuit of this embodiment includes a startup circuit, a reference current source, a mirror circuit, and a regulation circuit;

[0090] The startup circuit includes resistor R21, PMOS transistor MP21 and NMOS transistors MN21 and MN22. The startup circuit is used to provide an initial voltage to the reference current source. Resistor R21 is used to prevent excessive current from occurring during the instantaneous conduction of the startup circuit. The net1 node voltage V net1At the beginning, it is 0, at this time the PMOS tube MP21 is turned on, as the chip is slowly powered on, V net1 When the threshold voltage of MN22 is reached, the PMOS tube MN22 and MP21 form an inverter, which instantly reduces the net2 voltage V net2 Pull to high level and turn on PMOS tube MN21, the voltage V on net3 net3 It immediately drops to 0, giving the reference circuit an initial value. At this moment, the PMOS tubes MP22 and MP23 are turned on and enter the cut-off state, the reference source starts to work, and V net1 Pull high, after inversion V net2 Pull low to turn off the PMOS tube MN21.

[0091] The reference current source includes a diode B21 , a resistor R22 , NMOS transistors MN23 , MN24 , and PMOS transistors MP22 , MP23 ; the reference current source is used to generate a reference current I1 according to an initial voltage.

[0092] The mirror circuit includes PMOS transistors MP24 and MP25 and NMOS transistors MN25, MN26, and MN27. The mirror circuit is used to generate a mirror current I4 based on a reference current I1. The width-to-length ratios of the PMOS transistors MP24 and MP25 and the NMOS transistors MN25 and MN27 are all W / L, while the width-to-length ratio of the NMOS transistor MN26 is 3W / L. Since I5 = 3I2 and I1 = 2I2, we know that I4 = I5 - I2 = 2I2 = I1.

[0093] The regulation circuit includes PMOS transistors MP26 and MP27, which provide feedback regulation of the output VDD regulated voltage signal. Specifically, MP26 is a PMOS regulator. Once VDD changes, it dynamically adjusts via the feedback circuit to stabilize VDD within a set range. For example, when VDD rises, current I4 flowing through MP27 increases. Since I5 = 3I2 and is constant, the increase in I4 means a decrease in I2 and I3, which in turn reduces the VDS of the PMOS transistor MP25. VDS equals the VGS of MP26, which means that VGS also decreases, and thus VDD drops, achieving the regulation goal.

[0094] As shown in FIG8 , the ASK demodulation circuit of this embodiment includes an envelope extraction circuit, a pre-amplifier circuit, a post-amplifier circuit, and a decision circuit.

[0095] The envelope extraction circuit includes a resistor divider (R31, R32), a first low-pass filter (R32, C31) and a second low-pass filter (R33, C32); the resistor divider is used to divide the input signals ant1 and ant2 so that the voltage of the input signal matches the operating voltage of the first low-pass filter and the second low-pass filter; the first low-pass filter (R32, C31) is used to extract a first envelope signal V from the input signals ant1 and ant2 fast The second low-pass filter (R33, C32) is used to extract the second envelope signal V from the input signals ant1 and ant2. slow Specifically, since the input voltage of the RFID antenna is about 6V, which is higher than the normal operating voltage (1.8V) of the rest of the ASK demodulation circuit, the resistor divider (R31, R32) is applied to one of the envelope signals V fast The second low-pass filter (R33, C32) obtains the average voltage of the envelope signal, and its time constant is greater than that of the first low-pass filter. At this time, the overshoot disappears, and another envelope signal V slow .

[0096] The function of the pre-amplifier circuit is to amplify V fast and V slow The voltage signal is converted into a current signal I through the current mirror (MP31, MP32, MP33, MP34). fast and I slow The transconductances gm32 and gm33 of MN32 and MN33 determine the amplification factor of the pre-amplifier circuit.

[0097] In order to further suppress the influence of noise and enable the demodulator to correctly identify the useful ASK modulated signal, the pre-amplifier circuit should have an internal positive feedback hysteresis structure. Here, four NMOS transistors (MN35, MP36, MP37, MN38) are used to connect to the ground. slow and I fast is amplified and converted into a voltage V r1 and V s1 .

[0098] Since the two differential signals obtained by the pre-amplifier circuit do not meet the full-swing requirement, their voltage values ​​may still be at the sub-threshold. In addition, when the data rate is high, the sub-ideal differential signal may still cause an erroneous flip. Therefore, this embodiment sets a differential input post-amplifier circuit to convert the two voltage signals V r1 and V s1 Amplify to a level close to the full swing. The decision circuit is based on the third amplified signal V r and the fourth amplified signal V sGenerate ASK encoded signals to input into digital circuits to achieve analog signal to digital signal conversion.

[0099] As shown in Figure 9, the pulse position modulation decoder includes a synchronization circuit, an SOF / EOF detection circuit, a 9-bit counter, a decoding circuit, a shift register and an FSM circuit; the synchronization circuit is used to synchronize the ASK encoded signal and the clock signal; the SOF / EOF detection circuit is used to detect the start frame and end frame of the ASK encoded signal; the 9-bit counter is used to generate a logic signal according to the ASK encoded signal; the decoding circuit and the shift register are used to decode and output the logic signal; the FSM circuit is used to control the operating status of the pulse position modulation decoder and the Manchester encoder.

[0100] In this embodiment, the PPM decoder detects the 1 / 256 or 1 / 4 coded signal generated by the ASK demodulator. Its modulation index supports 100% and 10%, thereby achieving data rates of 1.65 Kbit / s and 26.48 Kbit / s. Specifically, clk_decoder is a 4x clock with a clock gating unit, por is the power-on reset signal, rx_en is the decoder enable signal, and din_100 and din_10 are the output signals of the ASK demodulation circuit. rx_data is the received 8-bit data, and din_100_en and din_10_en are the enable signals of the ASK demodulation circuit.

[0101] The pulse position modulation decoder performs decoding in the following steps:

[0102] Synchronize the ASK coding signal and clock signal;

[0103] Compare the ASK coded signal and the clock signal to determine the relative time of the ASK coded signal pulse position;

[0104] Determine the start frame and end frame of the ASK encoded signal;

[0105] The ASK encoded signal is input into a 9-bit counter. The 9-bit counter compares the count value of the ASK encoded signal with a preset threshold at the end of a clock cycle of the clock signal. When the count value is less than the preset threshold, a logic signal 0 is generated; when the count value is greater than the preset threshold, a logic signal 1 is generated.

[0106] The logic signal is decoded and output through the decoding circuit and shift register.

[0107] In this embodiment, the PPM decoder converts the input signal into digital data and outputs it to subsequent circuits for processing. This PPM decoder achieves high-precision, high-speed decoding, and has advantages such as low power consumption and a small footprint. It has broad application prospects in applications such as RFID tag chips.

[0108] Specifically, in the PPM decoder of this embodiment, the clock signal is continuous for 10% ASK signals, but discontinuous for 100% ASK signals. This causes the output demodulated signals din_100 or din_10 to be asynchronous, and the clock may contain glitches at the edges of each pause signal. Therefore, the synchronization circuit shown in Figure 10 must be used to process the output signals.

[0109] This embodiment's synchronization circuit uses four registers to synchronize one of the demodulated signals (din_100 or din_10). The first register's data input is connected to a logic 1, and either din_100 or din_10 is connected to the register's reset port. The first two registers eliminate metastability, while the second two registers generate a positive pulse synchronization signal. Finally, a multiplexer selects one of the demodulated signals as the output signal, din.

[0110] In particular, due to the special properties of the 1 / 256 or 1 / 4 coded signal generated by the PPM decoder from the ASK demodulation circuit in this embodiment, precise synchronization and decoding are required. Therefore, a finite state machine (FSM) is used to precisely control each state during the decoding process, thereby ensuring decoding accuracy and reliability. The FSM also improves system efficiency and response speed, making the entire RFID system more stable and reliable.

[0111] Specifically, the FSM circuit in the PPM decoder has seven states: IDLE, SOF, DATA256, SOF_END, DATA4, EOF, and ERROR. When in the IDLE state, the PPM decoder waits for the ASK signal. Once a pause signal occurs, the PPM decoder switches to the SOF state. Using a 9-bit counter and different SOF sequences, the FSM circuit can identify one of the data encoding modes. It then switches to the DATA256 or DATA4 state. In one of the 256 encoding modes, the value of a single byte can be represented by the position of a pause. This results in a data rate of 1.66 Kbit / s (13.56 MHz / 8192). In this case, the value can be determined using a 9-bit counter that records the data position. For the 1-out-4 encoding mode, a pause position determines two bits at a time, so a byte can consist of four pairs of two consecutive bits. This results in a data rate of 26.48 Kbit / s (13.56 MHz / 512). These techniques ensure precise control of each state during the decoding process, improving system efficiency and response speed.

[0112] The Manchester encoder in this embodiment converts the binary data signal output by the PPM decoder into a Manchester-encoded signal. Figure 11 shows the structure of the Manchester encoder controlled by the FSM circuit in this embodiment. SOF stands for the start-of-frame signal and consists of four components: SOF1, SOF2, SOF3, and SOF4. The first two waveforms are generated by circuit 1, and the last two waveforms are generated by circuit 2. Both circuits consist of multiple multiplexers, and the multiplexer inputs represent the pulse number configuration. sub_carrier is used to select one or two subcarriers. When using two subcarriers, the encoder should transmit 27 f / 28 pulses; otherwise, it transmits 24 clock cycles (clk32) of unmodulated time. To generate f / 28 or f / 32 pulses, two timers are used. Since the encoder input clock is divided by 2, a divide-by-16 timer is used to generate f / 32, and a divide-by-14 timer is used to generate f / 28. The FSM selects one of the timer outputs to generate the Manchester-encoded signal "dout," which is connected to the input of the load modulation circuit. Because the data to be sent is a series of bytes, a shift register is needed to generate the data bit by bit.

[0113] Specifically, the Manchester encoder divides each data bit into two time intervals and uses a different level in each interval to represent the bit value. If the data bit is 0, a high level is used in the first interval and a low level in the second interval; if the data bit is 1, a low level is used in the first interval and a high level in the second interval. Therefore, this embodiment uses the Manchester encoder to encode the response signal, supporting the use of one or two subcarriers. As shown in Figure 12, when using one subcarrier, the subcarrier frequency should be f / 32 (f is the carrier frequency, 13.56MHz). When using two subcarriers, the subcarrier frequency should be a combination of f / 32 and f / 28. Taking the start of frame (SOF) as an example, the SOF of a subcarrier consists of an unmodulated time of 24 clock cycles (clk32), 24 f / 32 pulses, and a logic 1 (clk32) that begins with an unmodulated time of 8 clock cycles, followed by 8 f / 32 pulses. The SOF of two subcarriers consists of 27 f / 28 pulses, 24 f / 32 pulses and logic 1. Logic 1 starts with 9 f / 28 pulses and then 8 f / 32 pulses.

[0114] Since multiple RFID tags may respond to the chip simultaneously during RFID communication, causing collisions between tags, this embodiment combines analog and digital circuits to detect the exact location of the collision, so that the anti-collision circuit can select one of the tags for communication. The anti-collision circuit is implemented by one of the following methods:

[0115] The time slots are divided into several time slots. Each RFID tag sends its own ID information in different time slots. The anti-collision circuit determines whether a collision occurs based on the read ID information.

[0116] The RFID tag's ID information is converted into a binary number and reversed from high to low according to the number of bits. The anti-collision circuit determines whether a collision occurs based on the read ID information;

[0117] The ID information of the RFID tag is stored in a query tree and queried according to preset rules. The anti-collision circuit determines whether a collision occurs based on the query results.

[0118] A hash function is used to map the ID information of the RFID tag to a unique hash value, and identification and differentiation are performed based on the hash value. The anti-collision circuit determines whether a collision occurs based on the received hash value.

[0119] For example, anti-collision detection is performed using a time-slot method. As shown in Figure 13, if tag 1 transmits a series of binary numbers "1100..." and tag 2 transmits "1111...", a logic 1 begins with an unmodulated time, followed by eight subcarrier pulses (negative transitions), while a logic 0 begins with eight subcarrier pulses, followed by an unmodulated time (positive transitions). The reader's combined signal will then have no transitions at the collision location. Therefore, the reader can easily detect this collision and select a tag to communicate with. In the ISO / IEC 15693 protocol, the tag's task is to compare the mask value received from the reader and, based on the comparison result, decide whether to send back its own UID stored in EEPROM memory. The anti-collision command (also known as the inventory command) is used to read the RFID tag's unique identifier (UID). By changing flags in the anti-collision command, the tag can determine the total number of time slots (1 or 16) and add parameters such as the mask length and mask value. Once a tag receives an inventory request, it resets the slot number register to zero and increments the slot number by 1 upon receiving the EOF signal from the reader. In each slot, the tag compares its own UID with the slot number plus the mask value. If the two values ​​are equal, the tag returns its unique ID; otherwise, it remains silent. As you can see, using anti-collision circuitry in an RFID system makes it easy to detect collisions and select a tag for communication.

[0120] As shown in Figure 14, the EEPROM memory of this embodiment includes a memory cell array, an erase / write circuit, a read circuit, and a charge pump. The erase / write circuit is used to control the erase / write operation of the memory cell array; the read circuit is used to control the read operation of the memory cell array; and the charge pump is used to generate an erase signal to erase the memory cell array.

[0121] Specifically, the EEPROM memory in this embodiment utilizes an 8-bit parallel input circuit structure. By providing an internal buffer circuit, the memory cell can achieve high-speed erasing and writing of any number of bytes within a page. A charge pump based on forward and reverse clock control is designed, optimizing the clock supply circuit to reduce charge pump power consumption. The memory circuit layout and routing are optimized, and a symmetrical design is added to address erasing and writing reliability issues caused by process variations. The EEPROM memory in this embodiment also features a serial output circuit structure, avoiding the use of a power-hungry reference source. Instead, a single sense amplifier is used to output serial data, effectively reducing read circuit power consumption. The EEPROM memory in this embodiment is designed to operate at low voltages, with all circuits capable of operating at voltages as low as 1.2V, effectively controlling read power consumption to less than 1μA. Simulation results demonstrate that the EEPROM memory in this embodiment operates stably across a supply voltage range of 1-1.8V, utilizing a read / write circuit design with parallel input and serial output and a single sense amplifier. Test data indicates that the read power consumption is only 0.68μA, while maintaining an access time of 1.7μs.

[0122] In some optional embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the present invention is provided in an exemplary manner for the purpose of providing a more comprehensive understanding of the technology. The disclosed method is not limited to the operation and logic flow presented herein. Optional embodiments are contemplated in which the order of the various operations is changed and the sub-operations described as a part of a larger operation are performed independently.

[0123] Furthermore, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise indicated, one or more of the functions and / or features described may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It will also be understood that a detailed discussion of the actual implementation of each module is not necessary for understanding the present invention. More specifically, given the properties, functions, and internal relationships of the various functional modules in the devices disclosed herein, the actual implementation of the module will be understood within the ordinary skill of an engineer. Therefore, a person skilled in the art using ordinary skill will be able to implement the present invention set forth in the claims without undue experimentation. It will also be understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0124] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0125] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

[0126] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A high-efficiency, low-power passive RFID tag chip, It is characterized in that Including radio frequency analog circuit, digital circuit and EEPROM memory; The radio frequency analog circuit specifically includes a bridge rectifier circuit, a three-level limiting circuit, a resistive load modulation circuit, an ASK demodulation circuit, a linear voltage stabilization circuit and a clock extraction circuit; the bridge rectifier circuit is used to convert the input signals ant1 and ant2 of the RFID tag antenna into VHD DC signals, and provide the VHD DC signals to the radio frequency analog circuit, the digital circuit and the EEPROM memory; the three-level limiting circuit is used to discharge the VHD DC signal output of the bridge rectifier circuit according to the field strength; the linear voltage stabilization circuit is used to stabilize the VHD DC signal output of the bridge rectifier circuit, and output the VDD stabilized voltage signal to the digital circuit and the EEPROM memory; the resistive load modulation circuit is used to load modulate the input signals ant1 and ant2; the ASK demodulation circuit is used to generate ASK coded signals according to the input signals ant1 and ant2 and input them into the digital circuit; the clock extraction circuit is used to generate a clock signal and input it into the digital circuit; The digital circuit specifically includes a Manchester encoder, a pulse position modulation decoder, and an anti-collision circuit; the pulse position modulation decoder is used to generate a logic signal according to the ASK encoding signal and the clock signal; the Manchester encoder is used to generate a Manchester encoding signal; the anti-collision circuit is used to detect the collision generated by the RFID tag; The EEPROM memory is used to store the logic signal output by the pulse position modulation decoder.

2. A high energy efficiency and low power consumption passive radio frequency identification tag chip according to claim 1, It is characterized in that The bridge rectifier circuit includes NMOS tubes MN1, MN2, MN3 and MN4 and an energy storage capacitor C VHD ; The drain and gate of MN1, the gate of MN4 and the drain of MN3 are connected to the input signal ant1, the drain and gate of MN2, the gate of MN3 and the drain of MN4 are connected to the input signal ant2; the source of MN1 and MN2 forms a VHD output, and the source of MN3 and MN4 is connected to the signal ground; the input signals ant1 and ant2 are obtained from the RFID tag antenna; When the input signal ant1 inputs a high level signal and the input signal ant2 inputs a low level signal, MN1 and MN4 are turned on, and the C between the VHD output and the signal ground is connected. VHD Charge and form VHD DC signal output; When the input signal ant1 inputs a low level signal and the input signal ant2 inputs a high level signal, MN2 and MN3 are turned on, and the C between the VHD output and the signal ground is connected. VHD Charge and form VHD DC signal output.

3. A high energy efficiency and low power consumption passive radio frequency identification tag chip according to claim 2, It is characterized in that The three-stage amplitude limiting circuit includes a first amplitude limiting circuit, a second amplitude limiting circuit and a third amplitude limiting circuit; the inputs of the first amplitude limiting circuit and the second amplitude limiting circuit are connected through a resistor R BC Isolation; the input of the second limiting circuit and the third limiting circuit is connected through the resistor R AB Isolation; each limiting circuit comprises a turn-on resistor, a limiting PMOS tube, a leakage branch, a high-pass filter and a leakage tube; wherein the high-pass filter is composed of a resistor and a capacitor connected in series, and is used to filter the noise input by the limiting circuit; the leakage tube is composed of two discharge NMOS tubes, the drains of the two discharge NMOS tubes are respectively input with signals ant1 and ant2, the sources are connected to the signal ground, and the gates are connected to the output of the leakage branch; The first leakage branch in the first limiting circuit includes five PMOS tubes with gates and drains connected, the drain output of the previous PMOS tube is connected to the source input of the next PMOS tube, and the drain of the last PMOS tube outputs a first turn-on voltage; The second leakage branch in the second limiting circuit includes four PMOS tubes with gates and drains connected, the drain output of the previous PMOS tube is connected to the source input of the next PMOS tube, and the drain of the last PMOS tube outputs a second turn-on voltage; The third leakage branch in the third limiting circuit includes three PMOS tubes with gates and drains connected, the drain output of the previous PMOS tube is connected to the source input of the next PMOS tube, and the drain of the last PMOS tube outputs a third turn-on voltage; When the field strength of the RF analog circuit exceeds the threshold voltage of the limiting PMOS tube in the third limiting circuit, the limiting PMOS tube is turned on to generate a third turn-on voltage; when the third turn-on voltage exceeds the threshold voltage of the discharge NMOS tube in the leakage tube of the third limiting circuit, the leakage tube of the third limiting circuit starts to discharge current; When the field strength of the RF analog circuit exceeds the threshold voltage of the limiting PMOS tube in the second limiting circuit, the limiting PMOS tube is turned on to generate a second turn-on voltage; when the second turn-on voltage exceeds the threshold voltage of the discharge NMOS tube in the leakage tube of the second limiting circuit, the leakage tube of the second limiting circuit starts to discharge current; When the field strength of the RF analog circuit exceeds the threshold voltage of the limiting PMOS tube in the first limiting circuit, the limiting PMOS tube is turned on to generate a first turn-on voltage; when the first turn-on voltage exceeds the threshold voltage of the discharge NMOS tube in the leakage tube of the first limiting circuit, the leakage tube of the first limiting circuit starts to discharge current.

4. The high energy efficiency and low power consumption passive radio frequency identification tag chip according to claim 1, It is characterized in that The resistive load modulation circuit includes a modulation control circuit and a level conversion circuit; the modulation control circuit receives a Manchester coded signal; the output of the modulation control circuit is connected to the input of the level conversion circuit, and the output of the level conversion circuit is connected to the antenna resonant circuit; The modulation control circuit is composed of two inverters consisting of PMOS tubes MP11, MP12 and NMOS tubes MN11, MN12, which are used to provide a binary-coded control signal for the level conversion circuit; the level conversion circuit generates a high-level or low-level signal according to the control signal, and adds a modulation signal dem_in to the input signal ant1, ant2.

5. The high energy efficiency and low power consumption passive radio frequency identification tag chip according to claim 1, It is characterized in that The linear voltage stabilization circuit includes a startup circuit, a reference current source, a mirror circuit and a regulating circuit; The startup circuit includes a resistor R21, a PMOS tube MP21, and NMOS tubes MN21 and MN22; the startup circuit is used to provide an initial voltage to the reference current source; The reference current source includes a diode B21, a resistor R22, NMOS tubes MN23, MN24 and PMOS tubes MP22, MP23; the reference current source is used to generate a reference current I according to the initial voltage 1 ; The mirror circuit includes PMOS transistors MP24, MP25 and NMOS transistors MN25, MN26, MN27. The mirror circuit is used to 1 Generates mirror current I 4 ; The regulating circuit includes PMOS tubes MP26 and MP27, and the regulating circuit is used for performing feedback regulation on the output VDD voltage stabilization signal.

6. The high energy efficiency and low power consumption passive radio frequency identification tag chip according to claim 1, It is characterized in that The ASK demodulation circuit comprises an envelope extraction circuit, a front amplifier circuit, a rear amplifier circuit and a decision circuit; The extraction circuit includes a resistor divider, a first low-pass filter and a second low-pass filter; the resistor divider is used to divide the input signals ant1 and ant2 so that the voltage of the input signal matches the working voltage of the first low-pass filter and the second low-pass filter; the first low-pass filter is used to extract the first envelope signal V from the input signals ant1 and ant2 fast The second low-pass filter is used to extract the second envelope signal V from the input signals ant1 and ant2. slow ; The pre-amplifier circuit is used to amplify the first envelope signal V fast and the second envelope signal V slow , and obtain the first amplified signal V r1 and the second amplified signal V s1 The post-amplification circuit is used to amplify the first signal V r1 and the second amplified signal V s1 Perform secondary amplification to obtain the third amplified signal V r and the fourth amplified signal V s The decision circuit is used to amplify the third signal V r and the fourth amplified signal V s An ASK encoded signal is generated for input into the digital circuit.

7. The high energy efficiency and low power consumption passive radio frequency identification tag chip according to claim 1, It is characterized in that The pulse position modulation decoder includes a synchronization circuit, a SOF / EOF detection circuit, a 9-bit counter, a decoding circuit, a shift register and an FSM circuit; the synchronization circuit is used to synchronize the ASK coded signal and the clock signal; the SOF / EOF detection circuit is used to detect the start frame and the end frame of the ASK coded signal; The 9-bit counter is used to generate a logic signal according to the ASK coded signal; the decoding circuit and the shift register are used to decode and output the logic signal; the FSM circuit is used to control the operation status of the pulse position modulation decoder and the Manchester encoder; The pulse position modulation decoder performs decoding by the following steps: Synchronously processing the ASK coded signal and the clock signal; Comparing the ASK coded signal with a clock signal to determine the relative time of the pulse position of the ASK coded signal; Determine the start frame and the end frame of the ASK encoded signal; Inputting the ASK coded signal into a 9-bit counter, the 9-bit counter compares the count value of the ASK coded signal with a preset threshold value at the end of a clock cycle of the clock signal, and generates a logic signal 0 when the count value is less than the preset threshold value; and generates a logic signal 1 when the count value is greater than the preset threshold value; The logic signal is decoded and outputted through the decoding circuit and the shift register.

8. The high energy efficiency and low power consumption passive radio frequency identification tag chip according to claim 7, It is characterized in that The Manchester encoder supports the use of one or two subcarriers; When one subcarrier is used, the Manchester coded signal dout generated by the Manchester encoder has a subcarrier frequency of f / 32; When two subcarriers are used, the Manchester coded signal dout generated by the Manchester encoder has a subcarrier frequency that is a combination of f / 32 and f / 28.

9. The high energy efficiency and low power consumption passive radio frequency identification tag chip according to claim 1, It is characterized in that The anti-collision circuit is implemented by one of the following methods: The time slots are divided into several time slots. Each RFID tag sends its ID information in different time slots. The anti-collision circuit determines whether a collision occurs based on the read ID information. The ID information of the RFID tag is converted into a binary number and inverted from high to low according to the number of bits. The anti-collision circuit determines whether a collision occurs based on the read ID information; The ID information of the RFID tag is stored in a query tree, and a query is performed according to a preset rule, and the anti-collision circuit determines whether a collision occurs according to the query result; The ID information of the RFID tag is mapped to a unique hash value using a hash function, and identification and differentiation are performed based on the hash value. The anti-collision circuit determines whether a collision occurs based on the received hash value.

10. The high energy efficiency and low power consumption passive radio frequency identification tag chip according to claim 1, It is characterized in that The EEPROM memory includes a storage cell array, an erase circuit, a read circuit and a charge pump; the erase circuit is used to perform erase control on the storage cell array; the read circuit is used to perform read control on the storage cell array; the charge pump is used to generate an erase signal to erase the storage cell array.

Images