Image sensor and reading method therefor, and electronic device

Abstract

Provided in the present invention is an image sensor, comprising a plurality of pixel units arranged in an array and at least one gain control circuit. Each pixel unit comprises at least one photosensitive unit, a floating diffusion node, a gain control transistor, a source follower transistor and a reset transistor, wherein the photosensitive unit is connected to the floating diffusion node by means of a corresponding transmission transistor, and the reset transistor and the gain control transistor are sequentially connected to the floating diffusion node and are jointly connected to a gate electrode end of the source follower transistor. For each row of pixel units in the same column, every X rows of pixel units share the same column line, and adjacent (X*Y) rows of pixel units are respectively read out by means of Y column lines. The gain control circuit is connected to drain electrode ends of gain control transistors in K rows of pixel units in the same column. The present invention solves the problems of existing image sensors being unable to output finer images on the basis of different highlight scenes, a final synthesized image exhibiting a trailing phenomenon, circuit reading noise being large, etc.

Description

Image sensor, reading method thereof, and electronic device Technical Field

[0001] The present application relates to the technical field of image sensors, and in particular to an image sensor, a reading method thereof, and an electronic device. Background Art

[0002] Image sensors are used in a variety of electronic products (such as smart phones, digital cameras, video surveillance equipment, intelligent AI, face recognition, drones, etc.) to capture and recognize images.

[0003] With the continuous advancement of process technology and pixel performance, the full well capacity of traditional image sensors has become increasingly higher. During the signal readout stage, high conversion gain is generally used to obtain images in low-light scenes, while low conversion gain is used to obtain images in bright-light scenes. However, as the full well capacity of pixels increases, the demand for low conversion gain in bright-light scenes is increasing.

[0004] As shown in FIG1 , a conventional image sensor 10 with dual-gain conversion comprises multiple pixel units 100 arranged in a matrix, with each pixel unit 100 in each column read out via the same column line. Each pixel unit has the same circuit structure, as shown in FIG2 , including: a photodiode PD, a transfer transistor M1, a floating diffusion node FD, a reset transistor M2, a gain control transistor M3, a source follower transistor M4, and a select transistor M5. Furthermore, a capacitor Ca is provided between the reset transistor M2 and the gain control transistor M3. This capacitor Ca can be either a parasitic capacitor or a device capacitor.

[0005] The pixel unit 100 has two conversion gain modes when in operation, namely a high conversion gain (HCG) mode and a low conversion gain (LCG) mode. Taking any row of pixel units as an example, wherein:

[0006] In HCG mode, the gain control transistor M3 is turned off, and the gain capacitance value of the pixel unit in this row is the capacitance value of the floating diffusion node in this row, that is, Cfd. At this time, the circuit operates in HCG mode and can capture images in low-light scenes.

[0007] In LCG mode, the gain control transistor M3 is turned on, and the charge storage capacity is improved by connecting the capacitor Ca. The gain capacitance value of the pixel unit in this row is equal to the sum of the capacitance value of the floating diffusion node in this row and the capacitor Ca, that is, Cfd+Ca. At this time, the circuit operates in LCG mode and can capture images in high-light scenes.

[0008] Existing image sensors can achieve a large dynamic range by setting HCG mode and LCG mode, but the pixel full well capacity in LCG mode is fixed and cannot be adjusted for different high-light scenes. As a result, the fineness of the output image is stretched as the demand for high-light scenes gradually increases.

[0009] In addition, each pixel unit 100 in the same column is read out through the same column line. When performing multi-frame reading, there is a time difference between the reading processes, which will cause a tailing phenomenon in the final synthesized image. In addition, the circuit has a large read noise.

[0010] Summary of the Invention

[0011] In view of the shortcomings of the prior art described above, the purpose of this application is to provide an image sensor and its reading method, as well as an electronic device, to solve the problems such as the inability of existing image sensors to output more delicate images based on different high-light scenes, the presence of tailing in the final synthesized image, and large circuit reading noise.

[0012] To achieve the above-mentioned and other related objectives, the present application provides an image sensor, comprising a plurality of pixel units arranged in an array and at least one gain control circuit, wherein:

[0013] The pixel unit includes: at least one photosensitive unit, a floating diffusion node, a gain control transistor, a source follower transistor and a reset transistor, wherein the photosensitive unit is connected to the floating diffusion node through a corresponding transfer transistor, the reset transistor and the gain control transistor are sequentially connected to the floating diffusion node and are commonly connected to the gate terminal of the source follower transistor;

[0014] The pixel units in each row of the same column share the same column line for every X rows, and the pixel units in adjacent (X×Y) rows are read out via Y column lines, where X is an integer greater than or equal to 1, and Y is an integer greater than or equal to 2.

[0015] The gain control circuit is connected to the drain terminals of the gain control transistors in the K rows of pixel units in the same column, where K is an integer greater than or equal to 2.

[0016] Optionally, the gain control circuit includes (K-1) segments of connecting lines, and the (K-1) segments of connecting lines are sequentially connected to the drain ends of the gain control transistors in the K rows of pixel units.

[0017] Optionally, among the (K-1) sections of connecting lines, at least one section of the connecting line is provided with a switching transistor.

[0018] Optionally, when K is an even number, among the connection lines in the (K-1) segment, a switching transistor is provided only on the connection line between the pixel units in the K / 2th row and the pixel units in the (K / 2+1)th row.

[0019] Optionally, in the (K-1) segments of connecting lines, each segment of the connecting line is provided with a switching transistor.

[0020] Optionally, in a direction perpendicular to the pixel unit, the orthographic projection of the connecting line overlaps with the orthographic projection of the photosensitive unit, and the overlapping area ratio is no more than 50%.

[0021] Optionally, every K rows of pixel units in the same column constitute a first pixel group, and each of the first pixel groups corresponds to one of the gain control circuits.

[0022] Optionally, each (X×Y) row of pixel units in the same column constitutes a second pixel group, and corresponding rows in each second pixel group are connected to the same column line.

[0023] Optionally, when the number of the photosensitive units in the pixel unit is greater than one, the plurality of photosensitive units are configured to receive light of the same color; wherein the plurality of photosensitive units constitute a shared pixel unit.

[0024] Optionally, the number of the photosensitive units in the pixel unit is four, and the four photosensitive units are arranged in a 2×2 array; wherein the photosensitive unit includes a photosensitive element and a transfer transistor, and the photosensitive element is connected to the floating diffusion node through the transfer transistor.

[0025] Optionally, the pixel unit further includes a selection transistor connected to the source terminal of the source follower transistor.

[0026] The present invention further provides a method for reading an image sensor as described in any one of the above items, which reads image signals of K rows of pixel units row by row, wherein the image signals include a reset signal and a pixel signal.

[0027] Optionally, the image sensor reading method includes:

[0028] Turning on the reset transistor and the gain control transistor in the pixel unit of the selected row to reset the floating diffusion node in the pixel unit of the selected row; turning off the gain control transistor in the pixel unit of the selected row to read the reset signal of the pixel unit of the selected row;

[0029] The transfer transistors in the pixel units in the selected row are turned on, charge transfer is performed in a high conversion gain mode, and pixel signals of the pixel units in the selected row are read.

[0030] Optionally, the reset transistors in the pixel units in the K rows are always turned on; when the gain control transistors in the pixel units in the selected row are turned off, the gain control transistors in the pixel units in other rows except the selected row are turned on; the pixel units also include selection transistors, and when reading the reset signal and the pixel signal, the selection transistors in the pixel units in the selected row are turned on, and the selection transistors in the pixel units in other rows except the selected row are turned off.

[0031] Optionally, the image sensor reading method includes:

[0032] Turning on the reset transistor and the gain control transistor in the pixel unit of the selected row, turning off the gain control transistor in the pixel units of the other rows except the selected row, and performing a reset operation on the floating diffusion node in the pixel unit of the selected row; turning off the reset transistor in the pixel unit of the selected row, and reading the reset signal of the pixel unit of the selected row;

[0033] The transfer transistors in the pixel units in the selected row are turned on, charge transfer is performed in a first low conversion gain mode, and pixel signals of the pixel units in the selected row are read.

[0034] Optionally, when the gain control circuit further includes switching transistors, before performing the reset operation on the floating diffusion node in the pixel unit in the selected row, the step of turning off all switching transistors is further included.

[0035] Optionally, the pixel unit further includes a selection transistor, and when the reset signal and the pixel signal are read, the selection transistor in the pixel unit of the selected row is turned on, and the selection transistors in the pixel units of other rows except the selected row are turned off.

[0036] Optionally, the image sensor reading method includes:

[0037] Turning on the gain control transistors in the K rows of pixel units, turning on the reset transistors in the selected row of pixel units, and performing a reset operation on the floating diffusion nodes in the selected row of pixel units; turning off the reset transistors in the selected row of pixel units, and reading the reset signals of the selected row of pixel units;

[0038] The transfer transistors in the pixel units in the selected row are turned on, charge transfer is performed in a Zth lowest conversion gain mode, and pixel signals of the pixel units in the selected row are read, where Z is an integer greater than or equal to K.

[0039] Optionally, when the gain control circuit further includes switching transistors, before performing the reset operation on the floating diffusion node in the pixel unit of the selected row, the step of turning on all switching transistors is further included.

[0040] Optionally, the pixel unit further includes a selection transistor. When reading the reset signal and the pixel signal, the selection transistor in the pixel unit of the selected row is turned on, and the selection transistors in the pixel units of other rows except the selected row are turned off, or the selection transistors in the pixel units of row K are always turned on.

[0041] The present invention also provides an electronic device, comprising the image sensor as described in any one of the above items.

[0042] As described above, the image sensor, its reading method, and electronic device of the present application provide more and richer low conversion gains by using a gain control circuit in the image sensor to connect the drain ends of the gain control transistors in K rows of pixel units located in the same column. In other words, by controlling the number of capacitors connected to one end of the gain control transistor in the LCG mode of the image sensor to adjust the conversion gain and thus improve the dynamic range, more delicate images can be output for different high-light scenes; the image signal readout efficiency of the present invention is higher and the noise level of the circuit is lower, which can further improve the performance of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1 is a schematic structural diagram of an image sensor according to background technology.

[0044] FIG2 is a circuit diagram of a pixel unit in an image sensor according to background art.

[0045] FIG3 is a schematic structural diagram of an image sensor provided in this application.

[0046] FIG4 is a schematic diagram of the structure of another image sensor provided by the present application.

[0047] 5 to 9 are circuit diagrams of a pixel unit in the image sensor shown in FIG. 3 of the present application, wherein FIG. 5 to 9 only show one of the four photosensitive units.

[0048] 10-12 are schematic structural diagrams of the photosensitive unit in the pixel unit provided in this application.

[0049] 13-16 are schematic diagrams of the circuit layout of the image sensor provided in this application.

[0050] 17-19 are schematic structural diagrams of three more image sensors provided in this application.

[0051] FIG20 is a timing diagram of an image sensor provided by the present application reading an image signal in a high conversion gain mode.

[0052] FIG21 is a timing diagram of an image sensor provided by the present application reading an image signal in a first low conversion gain mode.

[0053] 22 and 23 are timing diagrams of an image sensor provided by the present application for reading image signals in the Zth lowest conversion gain mode.

[0054] Component Reference Numerals 10 Image sensor 100 Pixel unit 101 Photosensitive unit 102 Orthographic projection of connecting line 200 Gain control circuit DETAILED DESCRIPTION

[0055] The following describes the embodiments of the present application through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present application from the disclosure herein. The present application may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present application.

[0056] Please refer to Figures 3 to 23. It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present application in a schematic manner. Therefore, the figures only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0057] Example 1

[0058] As shown in Figures 3 to 9, this embodiment provides an image sensor 10, which includes a plurality of pixel units 100 arranged in an array and at least one gain control circuit 200. Each pixel unit 100 has the same circuit structure, including: at least one photosensitive unit 101, a floating diffusion node (such as FD1), a reset transistor M2, a gain control transistor M3, and a source follower transistor M4; further, it also includes a select transistor M5.

[0059] The photosensitive unit 101 is connected between a floating diffusion node (e.g., FD1) and a reference ground, and is configured to generate and transfer charge based on the photoelectric effect. Specifically, the photosensitive unit 101 includes a photosensitive element PD and a transfer transistor M1. The photosensitive element PD is connected to the floating diffusion node via the transfer transistor M1 (e.g., one end of the photosensitive element PD is connected to the reference ground, the other end is connected to the source of the transfer transistor M1, the gate of the transfer transistor M1 is connected to the transmission control signal TX1, and the drain of the transfer transistor M1 is connected to the floating diffusion node FD1). The photosensitive element PD converts a light signal carrying image information into charge based on the photoelectric effect. The transfer transistor M1 is controlled by the transmission control signal TX1 to turn on and transfer the charge to the floating diffusion node FD1.

[0060] It can be understood that the photosensitive element PD mentioned in the present application can be any one of a photodiode, a grating or a photoconductor. As a preferred solution, the photosensitive element PD in this embodiment is a photodiode. At this time, the anode end of the photodiode is connected to the reference ground, and the cathode end is connected to the source end of the transfer transistor.

[0061] In actual applications, the number of photosensitive units 101 in the pixel unit 100 can be designed according to actual needs, such as 1, 2, 3, 4, 8, etc.; when the pixel unit 100 includes one photosensitive unit 101, the power consumption of the pixel unit 100 is lower, but correspondingly, the photoelectric conversion efficiency is also lower; when the pixel unit 100 includes more than one photosensitive unit 101, the multiple photosensitive units 101 are configured to receive light of the same color, and the multiple photosensitive units 101 constitute a shared pixel unit. In this way, the fill factor of the pixel unit can be improved, thereby improving the photoelectric conversion efficiency of the image sensor, as shown in Figures 10-12.

[0062] As a preferred embodiment, in the image sensor 10 disclosed in this embodiment, the pixel unit 100 includes four photosensitive units 101, and the four photosensitive units 101 are arranged in a 2×2 array, as shown in FIG11 . Of course, the four photosensitive units 101 can also be arranged in sequence laterally instead of in a 2×2 array. The embodiment of the present application does not limit the arrangement form or shape of the multiple photosensitive units 101 in the pixel unit 100. In other embodiments, the number of photosensitive units included in the pixel unit 100 can also be an odd number. By providing multiple photosensitive units in the pixel unit, the photoelectric conversion efficiency of the image sensor 10 can be effectively improved.

[0063] In the image sensor 10 provided in this embodiment, the four photosensitive units 101 in the same pixel unit 100 are configured to receive light of the same color, which may be red (R), green (G), or blue (B). In other embodiments, the four photosensitive units 101 may also be configured to receive white (W) light. Specifically, the color of the photosensitive unit 101 is implemented by adding a color filter of the corresponding color to the optical path corresponding to the pixel unit, and by accurately selecting a small range of wavelength bands of light waves to pass through during the process of collecting light signals in the photosensitive unit, while reflecting other wavelength bands that are not desired to pass through.

[0064] In some embodiments, as shown in Figures 3 and 4, four pixel units 100 are grouped together and arranged in an array. The difference is that in the image sensor 10 shown in Figure 3, the four pixel units 100 in each group are configured to receive three primary colors of red (R), green (G), and blue (B), while the image sensor 10 shown in Figure 4 has increased receivable white (W) light compared to the former. Receiving white (W) light can ensure the clarity of photos in low-light environments when the image sensor 10 is in operation, and at the same time helps to improve the dynamic range of the image sensor 10.

[0065] Among them, the image sensor shown in Figure 3 adopts a traditional Bayer array pixel unit arrangement, that is, the four pixel units 100 in each 2×2 pixel array receive red (R), green (G), blue (B) and green (G) light respectively; in the image sensor shown in Figure 4, the four pixel units 100 in each 2×2 pixel array receive red (R), green (G), blue (B) and white (W) light respectively. The pixel arrangement provided in this embodiment is only an example. In fact, other forms of pixel array arrangement can also be used.

[0066] The floating diffusion node (eg, FD1 ) includes a capacitor (eg, Cfd1 ) for storing the charge transferred from the transfer transistor M1 and converting the charge into a voltage.

[0067] The reset transistor M2 and the gain control transistor M3 are sequentially connected to the floating diffusion node and are connected to the gate terminal of the source follower transistor M4. For example, the gate terminal of the reset transistor M2 is connected to the reset control signal RST1, the drain terminal is connected to the power supply VDD, and the source terminal is connected to the drain terminal of the gain control transistor M3; the gate terminal of the gain control transistor M3 is connected to the gain control signal DCG1, and the source terminal is connected to the floating diffusion node FD1; the gate terminal of the source follower transistor M4 is connected to the floating diffusion node FD1, the drain terminal is connected to the power supply VDD, and the source terminal outputs a voltage signal (such as a reset signal and a pixel signal).

[0068] The reset transistor M2 is used to reset the voltage of the floating diffusion node (such as FD1) according to the reset control signal (such as RST1). When the gain control transistor M3 is turned on, it provides the voltage of the power supply VDD as a reset voltage to achieve the potential reset of the floating diffusion node.

[0069] The gain control transistor M3 is used to switch each pixel unit 100 between a high conversion gain mode and a low conversion gain mode. When turned off, the pixel unit is switched to a high conversion gain (HCG) mode, and when turned on, the pixel unit is switched to a low conversion gain (LCG) mode. It should be noted that the image sensor provided in this embodiment has multiple LCG modes, such as a first low conversion gain (LCG1) mode and a second low conversion gain (LCG2) mode. The relevant descriptions are detailed below.

[0070] The source-follower transistor M4 is used to transfer the voltage stored at the floating diffusion node (converted from the charge transferred by the transfer transistor M1) to the source terminal of the source-follower transistor M4 and amplify the output. It should be noted that when the pixel unit 100 does not include the select transistor M5, the source terminal of the source-follower transistor M4 is connected to the corresponding column line; when the pixel unit 100 includes the select transistor M5, the source terminal of the source-follower transistor M4 is connected to the drain terminal of the select transistor M5.

[0071] As a preferred solution, the pixel unit 100 provided in an embodiment of the present application includes a select transistor M5, wherein the select transistor M5 is connected to the source terminal of the source-follower transistor M4. For example, the gate terminal of the select transistor M5 is connected to the row select signal RS1, the drain terminal is connected to the source terminal of the source-follower transistor M4, and the source terminal is connected to the corresponding column line. The select transistor M5 is controlled by the row select signal RS1 to turn on and off to select the voltage signal output by the source-follower transistor M4 for output. When it is necessary to sequentially output a predetermined sequence of pixel units 100 in the same column of the image sensor 10, the sequential output can be achieved by turning on or off the select transistors M5 of different rows.

[0072] The gain control circuit 200 is connected to the drain terminals of the gain control transistors M3 in K rows of pixel units 100 located in the same column, and is used to regulate the pixel full well capacity of the floating diffusion node in the corresponding row, thereby providing more conversion gains and enriching the low conversion gain mode; wherein K is an integer greater than or equal to 2.

[0073] In one embodiment, each column includes K rows, in which case the number of gain control circuits 200 is one; in another embodiment, each column includes more than K rows, in which case every K rows of pixel units 100 in the same column constitute a first pixel group, and each first pixel group corresponds to a gain control circuit 200, that is, there are multiple gain control circuits 200 in each column.

[0074] As far as one column is concerned, regardless of whether the number of gain control circuits 200 is one or more, the principle of regulating the full well capacity of the floating diffusion node pixel of the corresponding row remains unchanged. It is just that when the gain control circuit 200 is connected to more rows, more conversion gains can be provided, but the corresponding control will be more complicated. In fact, the image sensor generally includes many rows and columns of pixel units. Considering the conversion gain and control complexity, multiple first pixel groups are usually set in one column, and the first pixel group can include pixel units of different numbers of rows, such as 2 rows, 3 rows, or 4 rows.

[0075] In the K rows of pixel units in this embodiment, any row of pixel units includes (Z+1) different conversion gain modes, namely, one high conversion gain mode and Z low conversion gain modes, where Z is an integer greater than or equal to K. It should be noted that the value of Z is determined by the value of K and the circuit structure of the gain control circuit 200. For example, when the gain control circuit 200 includes (K-1) connecting lines, Z=K; when the gain control circuit 200 also includes a switching transistor, Z>K.

[0076] As an example, as shown in FIG5 and FIG7 , the gain control circuit 200 includes (K-1) segments of connecting lines, which sequentially connect the drain terminals of the gain control transistors M3 in K rows of pixel units 100 .

[0077] In this embodiment, in K rows of pixel units 100, a connecting line is provided between the drain terminals of the gain control transistors M3 of adjacent rows of pixel units 100 to form a capacitor. Since the connecting line is located at a high-resistance node, the characteristic impedance can be reduced by adjusting the line width of the connecting line to form a capacitor that meets the gain conversion switching requirements. Alternatively, a capacitor that meets the gain conversion switching requirements can be formed by providing a device capacitor. It is understandable that the connecting line is not limited to a single line, and is only required to achieve connectivity with the gain control transistors M3 of the adjacent rows of pixel units 100 when the gain control transistors M3 of the adjacent rows are turned on.

[0078] Assume that the capacitance value of the floating diffusion node of each row of pixel units 100 in K rows of pixel units is Cfd1-Cfdk, and the capacitance value of the (K-1) segment of the connecting line is Ca; then:

[0079] When all gain control transistors M3 in the K-row pixel units 100 are turned off, the gain capacitance value of the first row of pixel units 100 is the capacitance value of the floating diffusion node of that row, i.e., Cfd1. The conversion gain is q / Cfd1, where q is the amount of charge generated in the first row of pixel units when the photoelectric effect occurs. The conversion gain is maximum at this time, so it can be used as a high conversion gain (HCG) mode.

[0080] When the gain control transistors M3 in the first row of pixel cells 100 are turned on and the gain control transistors M3 in the remaining (K-1) rows of pixel cells 100 are turned off, the gain capacitance of the first row of pixel cells 100 is the sum of the capacitance of the floating diffusion node in that row and the capacitance of the (K-1) segment of the connecting line, i.e., Cfd1+Ca. Due to the addition of the capacitance Ca of the (K-1) segment of the connecting line, its conversion gain is q / (Cfd1+Ca), which is smaller than the conversion gain in the HCG mode. Therefore, it can be used as the first low conversion gain (LCG1) mode to provide a lower conversion gain in a relatively bright environment. However, the LCG1 mode has the highest conversion gain among all low conversion gain modes.

[0081] When the gain control transistors M3 in the first two rows of pixel units 100 are turned on and the gain control transistors M3 in the remaining rows of pixel units 100 are turned off, the gain capacitance of the first row of pixel units 100 is the sum of the capacitance of the floating diffusion nodes of the first two rows of pixel units 100 and the capacitance of the (K-1) segment of the connecting line, i.e., Cfd1+Ca+Cfd2. The conversion gain is q / (Cfd1+Ca+Cfd2). Because the drain terminals of the gain control transistors M3 of only two adjacent pixel units 100 are connected to each other via corresponding connecting lines, the conversion gain in this mode is lower than that in the LCG1 mode, resulting in a second low conversion gain (LCG2) mode.

[0082] For the case where K = 2, the LCG2 mode has the lowest conversion gain among the low conversion gain modes. For the case where K is greater than 2, in practice, in the previous mode, the gain control transistors M3 in the next row of pixel cells 100 can be turned on to set a lower conversion gain. For example, in the third low conversion gain (LCG3) mode, the gain control transistors M3 in the first three rows of pixel cells 100 are turned on, while the gain control transistors M3 in the remaining rows of pixel cells 100 are turned off. In this case, the gain capacitance of the first row of pixel cells 100 is the sum of the capacitance of the floating diffusion nodes of the first three rows of pixel cells 100 and the capacitance of the (K-1) segment of the connecting line, i.e., Cfd1 + Ca + Cfd2 + Cfd3. The conversion gain is q / (Cfd1 + Ca + Cfd2 + Cfd3), which is lower than that of the LCG2 mode.

[0083] This process continues in this way until all the gain control transistors M3 in the K-row pixel units 100 are turned on. The K-row pixel units 100 will share the capacitance of each other's floating diffusion nodes. At this time, the gain capacitance of the first row of pixel units 100 is the sum of the capacitance of the floating diffusion node of the K-row pixel units 100 and the capacitance of the (K-1)-segment connecting line, i.e., Cfd1+Ca+Cfd2+…+Cfdk. Its conversion gain is q / (Cfd1+Ca+Cfd2+…+Cfdk), which is the Zth low conversion gain (LCGz) mode. The LCGz mode has the lowest conversion gain among all low conversion gain modes.

[0084] It can be understood that as the number of connected gain control transistors M3 increases, the gain capacitance value of the corresponding row pixel unit 100 also increases, thereby providing a greater expansion of the gain capacitance value, thereby making the conversion gain lower; by providing more and richer low conversion gain modes, more delicate images can be output for different high-light scenes.

[0085] Based on the same principle, the pixel units 100 in other rows in row K can also provide more low conversion gain modes. By controlling the opening and closing of the gain control transistors M3 in each row of pixel units 100, the gain capacitance value of each row of pixel units 100 is controlled, thereby making the pixel full well capacity of the image sensor 10 more controllable; therefore, the image sensor 10 provided in this embodiment can provide more gain modes, thereby adapting to a wider variety of scene usage requirements.

[0086] As another example, as shown in Figures 6, 8, and 9, at least one of the (K-1) segments of connecting lines is provided with a switching transistor; when the switching transistor is controlled by a switching control signal and is turned off, the segment of the connecting line is separated into at least two connecting sub-lines. Since the connecting line itself has a capacitance value, and in some embodiments, the connecting line is also provided with a device capacitor, each separated connecting sub-line segment can provide a new conversion gain, thereby expanding the pixel full well capacity and the selectable range of gain modes of the pixel unit 100. It can be understood that each additional switching transistor can at least add a new conversion gain and corresponding gain selection mode to the image sensor 10.

[0087] In one embodiment, as shown in Figures 6 and 8 , each of the (K-1) connecting lines is provided with a switching transistor. The number of switching transistors on each connecting line can be one or more than one, and the number of switching transistors on each connecting line can be the same or different. This allows the pixel units 100 in the image sensor 10 to have more adjustable gain capacitance values, thereby making the image sensor 10 more detailed when capturing bright images. As a preferred solution, in this embodiment, each connecting line has only one switching transistor.

[0088] In FIG8 , K=4, meaning that the gain control circuit 200 includes three connecting lines and three switching transistors disposed on the three connecting lines. The three connecting lines sequentially connect the drain terminals of the gain control transistors M3 in the first to fourth rows of pixel units 100. The floating diffusion nodes of the first to fourth rows of pixel units 100 have capacitances of Cfd1, Cfd2, Cfd3, and Cfd4, respectively. The three connecting lines are divided into six connecting sub-lines by the switching transistors M01, M02, and M03. The capacitances of the six connecting sub-lines are Cb, Cc, Cd, Ce, Cf, and Cg, respectively, where Ca=Cb+Cc+Cd+Ce+Cf+Cg.

[0089] When all the gain control transistors M3 in the four rows of pixel units 100 are turned off, the gain capacitance value of the first row of pixel units 100 is the capacitance value of the floating diffusion node itself, that is, Cfd1, and its conversion gain is q / Cfd1. At this time, the image sensor 10 operates in the HCG mode.

[0090] When the gain control transistor M3 in the first row of pixel units 100 is turned on and the switch transistor M01 provided on the first segment of the connecting line is turned off, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion node of the row itself and the capacitance value of the first connecting sub-line separated by the switch transistor M01 from the first segment of the connecting line, that is, Cfd1+Cb. The conversion gain is q / (Cfd1+Cb), which is lower than the conversion gain in the HCG mode and serves as the first low conversion gain (LCG1) mode. The LCG1 mode has the highest conversion gain among all low conversion gain modes.

[0091] When the gain control transistor M3 in the first row of pixel units 100 is turned on, the switch transistor M01 provided on the first segment of the connecting line is turned on, and the gain control transistor M3 in the second row of pixel units 100 and the switch transistor M02 provided on the second segment of the connecting line are turned off, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion node of the row itself, the capacitance value of the first segment of the connecting line, and the capacitance value of the first connecting sub-line separated by the switch transistor M02 from the second segment of the connecting line, that is, Cfd1+Cb+Cc+Cd. The conversion gain is q / (Cfd1+Cb+Cc+Cd), which is lower than the aforementioned conversion gain and serves as a second low conversion gain (LCG2) mode.

[0092] When the gain control transistor M3 in the first row of pixel units 100 is turned on, the switch transistor M01 provided on the first segment of the connecting line is turned on, the switch transistor M02 provided on the second segment of the connecting line is turned on, the gain control transistors M3 in the second and third rows of pixel units 100 are turned off, and the switch transistor M03 provided on the third segment of the connecting line is turned off, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion node of the row itself, the capacitance value of the first segment of the connecting line, the capacitance value of the second segment of the connecting line, and the capacitance value of the first connecting sub-line separated by the switch transistor M03 from the third segment of the connecting line, that is, Cfd1+Cb+Cc+Cd+Ce+Cf, and its conversion gain is q / (Cfd1+Cb+Cc+Cd+Ce+Cf), which is lower than the aforementioned conversion gain, serving as a third low conversion gain (LCG3) mode;

[0093] Similarly, by turning on the gain control transistor M3 in the corresponding row of pixel units 100 and / or the switch transistor on the corresponding segment connection line, the gain capacitance value of the first row of pixel units 100 can be adjusted, thereby generating more low conversion gain modes;

[0094] Until all the gain control transistors M3 in the four rows of pixel units 100 are turned on and all the three switching transistors on the three connecting lines are turned on, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion node itself of the four rows of pixel units 100 and the capacitance value of the three connecting lines, that is, Cfd1+Cfd2+Cfd3+Cfd4+Ca, and its conversion gain is q / (Cfd1+Cfd2+Cfd3+Cfd4+Ca), which is the Zth low conversion gain (LCGz) mode. The LCGz mode has the lowest conversion gain among all low conversion gain modes.

[0095] In another embodiment, not every segment of the (K-1) connecting line is provided with a switching transistor, but rather only one or more segments of the connecting line are provided with a switching transistor. Of course, the number of switching transistors can be one or more than one. As a preferred embodiment, when K is an even number, only the connecting line between the pixel units 100 in the K / 2th row and the pixel units 100 in the (K / 2+1)th row in the (K-1) connecting line is provided with a switching transistor. By providing only the connecting line between the pixel units 100 in the K / 2th row and the pixel units in the (K / 2+1)th row in the (K-1) connecting line, the conversion gain of the image sensor 10 can be increased while maximizing the area of ​​the pixel array formed by the plurality of pixel units 100 in the image sensor 10, reducing the actual scale loss of the pixel array due to the increase in the number of switching transistors in the gain control circuit, and thereby improving the photosensitivity of the image sensor 10.

[0096] In FIG9 , K=4, and the gain control circuit 200 includes three connecting lines and one switching transistor. The switching transistor is provided on the second connecting line between the second row of pixel units 100 and the third row of pixel units 100. Assuming that the capacitance values ​​of the floating diffusion nodes of the four rows of pixel units 100 are Cfd1, Cfd2, Cfd3, and Cfd4, respectively, the capacitance value of the first connecting line is (Cb+Cc). The second connecting line is divided into two connecting sub-lines by the switching transistor. The two connecting sub-lines correspond to capacitance values ​​Cd and Ce, respectively. The capacitance value of the third connecting line is (Cf+Cg), and Ca=Cb+Cc+Cd+Ce+Cf+Cg.

[0097] When all the gain control transistors M3 in the four rows of pixel units 100 are turned off, the gain capacitance value of the first row of pixel units 100 is the capacitance value of the floating diffusion node itself, that is, Cfd1, and its conversion gain is q / Cfd1. At this time, the image sensor 10 operates in the HCG mode.

[0098] When the gain control transistor M3 in the first row of pixel units 100 is turned on, the switch transistor M0 is turned off, and the gain control transistor M3 in the second row of pixel units 100 is turned off, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion node of the row itself, the capacitance value of the first section of the connecting line, and the capacitance value of the first connecting sub-line separated by the switch transistor M0 from the second section of the connecting line, that is, Cfd1+Cb+Cc+Cd. Its conversion gain is q / (Cfd1+Cb+Cc+Cd), which is lower than the conversion gain in the HCG mode, serving as the first low conversion gain (LCG1) mode. The LCG1 mode has the highest conversion gain among all low conversion gain modes.

[0099] When the gain control transistor M3 in the first row of pixel cells 100 is turned on, the switch transistor M0 is turned on, and the gain control transistors M3 in the other rows of pixel cells are turned off, the gain capacitance value of the first row of pixel cells 100 is the sum of the capacitance value of the floating diffusion node of the row itself, the capacitance value of the first segment of the connecting line, the capacitance value of the second segment of the connecting line, and the capacitance value of the third segment of the connecting line, that is, Cfd1+Ca. The conversion gain is q / (Cfd1+Ca), which is lower than the aforementioned conversion gain, and serves as the second low conversion gain (LCG2) mode.

[0100] When the gain control transistors M3 in the first and second rows of pixel units 100 are turned on and the switch transistors M0 are turned off, the gain capacitance of the first row of pixel units 100 is the sum of the capacitance of the floating diffusion nodes of the first two rows, the capacitance of the first section of the connecting line, and the capacitance of the first connecting sub-line separated by the switch transistor M0 from the second section of the connecting line, i.e., Cfd1+Cb+Cc+Cfd2+Cd. The conversion gain is q / (Cfd1+Cb+Cc+Cfd2+Cd), which is lower than the aforementioned conversion gain and serves as a third low conversion gain (LCG3) mode.

[0101] When the gain control transistors M3 in the first two rows of pixel units 100 are turned on, the gain control transistors M3 in the other rows of pixel units 100 are turned off, and the switch transistor M0 is turned on, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion node of the first two rows of pixel units 100, the capacitance value of the first section of the connecting line, the capacitance value of the second section of the connecting line, and the capacitance value of the third section of the connecting line, that is, Cfd1+Cfd2+Ca. The conversion gain is q / (Cfd1+Cfd2+Ca), which is lower than the above conversion gain and serves as the fourth low conversion gain (LCG4) mode.

[0102] When the gain control transistors M3 in the first three rows of pixel units 100 are turned on, the gain control transistors M3 in the fourth row of pixel units 100 are turned off, and the switch transistor M0 is turned on, the gain capacitance of the first row of pixel units 100 is the sum of the capacitance of the floating diffusion node of the first three rows of pixel units 100, the capacitance of the first connecting line, the capacitance of the second connecting line, and the capacitance of the third connecting line, that is, Cfd1+Cfd2+Cfd3+Ca. The conversion gain is q / (Cfd1+Cfd2+Cfd3+Ca), which is lower than the aforementioned conversion gain and serves as the fifth low conversion gain (LCG5) mode.

[0103] When all the gain control transistors M3 in the four rows of pixel units 100 are turned on and the switch transistor M0 is turned on, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance values ​​of the floating diffusion nodes themselves in the first four rows, the capacitance values ​​of the first section of the connecting line, the capacitance values ​​of the second section of the connecting line, and the capacitance values ​​of the third section of the connecting line, that is, Cfd1+Cfd2+Cfd3+Cfd4+Ca. Its conversion gain is q / (Cfd1+Cfd2+Cfd3+Cfd4+Ca), which is lower than the aforementioned conversion gain and serves as the sixth low conversion gain (LCG6) mode. The LCG6 mode has the lowest conversion gain among all low conversion gain modes (i.e., Z=6).

[0104] Specifically, in a direction perpendicular to the pixel unit, the orthographic projection 102 of the connecting line overlaps with the orthographic projection of the photosensitive unit 101, and the overlapping area ratio is no greater than 50%. As shown in Figure 13, taking four photosensitive units 101 arranged in a 2×2 pattern to form a pixel unit 100 as an example, the shaded area in the figure is the projection of the connecting line on each pixel unit 100. Considering the effective photosensitive area of ​​the photosensitive unit 101, it is necessary to control the orthographic projection 102 of the connecting line in a direction perpendicular to the pixel unit 100 so that the overlapping area ratio of the orthographic projection 102 of the connecting line and the orthographic projection of the photosensitive unit 101 is no greater than 50%. In other words, the ratio of the routing area of ​​the connecting line to the area of ​​the photosensitive unit 101 is less than 1:2. The routing of the connecting line can adopt various distribution methods, as shown in Figures 14 to 16.

[0105] It should be noted that the above examples all take the case where the capacitance value Ca of the (K-1) segment connecting line is less than the capacitance value of any floating diffusion node itself as an example, and the low conversion gain modes are sorted from high to low. However, those skilled in the art should understand that this scheme is only used as an exemplary description and does not limit the embodiments of the present application. In actual applications, the capacitance value Ca of the (K-1) segment connecting line can be made greater than any floating diffusion node, or even greater than all floating diffusion nodes by adjusting the line width, line type, etc. These are all feasible and have no substantial impact on the embodiments of the present application. It is only necessary to adjust the sorting of the low conversion gain modes accordingly.

[0106] The embodiment of the present application provides a greater variety of low conversion gains by utilizing a gain control circuit 200 in the image sensor 10 to connect the drain terminals of the gain control transistors M3 of K rows of pixel units 100 located in the same column. In other words, by controlling the number of capacitors connected to one terminal of the gain control transistors in each row of pixel units in the LCG mode of the image sensor to adjust the conversion gain, the dynamic range is improved, and more detailed images can be output in high-light environments.

[0107] For the image sensor 10 provided in the embodiment of the present application, when outputting signals via column lines, as shown in FIG3 and FIG17-19 , each row of pixel units 100 located in the same column shares the same column line for every X rows of pixel units 100, and adjacent (X×Y) rows of pixel units 100 are read out via Y column lines, respectively, where X is an integer greater than or equal to 1, and Y is an integer greater than or equal to 2. Such an arrangement of column lines can make the readout faster and more efficient. Since the output of the pixel circuit does not need to be sampled and held, the KT / C noise of the circuit can be reduced, resulting in a lower noise level for the circuit, which can further improve the performance of the image sensor.

[0108] In one embodiment, each column includes (X×Y) rows, and from top to bottom, every X rows share a column line, with a total of Y column lines being used for readout. In another embodiment, each column includes more than (X×Y) rows. In this case, every (X×Y) rows of pixel units in the same column constitute a second pixel group, and corresponding rows in each second pixel group are connected to the same column line. FIG3 illustrates a column line connection method for each row of pixel units in each second pixel group when X=1 and Y=2, FIG17 illustrates a column line connection method for each row of pixel units in each second pixel group when X=2 and Y=2, FIG18 illustrates a column line connection method for each row of pixel units in each second pixel group when X=4 and Y=2, and FIG19 illustrates a column line connection method for each row of pixel units in each second pixel group when X=1 and Y=4.

[0109] In practical applications, the values ​​of X and Y should be set according to specific requirements, for example, X is 1, 2, 4, etc., and Y is 2, 4, 8, etc. This embodiment does not impose any limitation on this.

[0110] In addition, during the image signal readout process, pixel units receiving the same color light need to be binned, so that the sampling resolution can be reduced while the channel bandwidth is fixed, thereby improving the frame rate. Binning readout is divided into horizontal binning readout and vertical binning readout. Horizontal binning readout is to add the charges of adjacent rows together for reading out; vertical binning readout is to add the charges of adjacent columns together for reading out.

[0111] This embodiment uses horizontal binning readout as an example. In this embodiment, the connection method of the column lines is positively correlated with the data bit width (unit: bit) of the image signal readout of the image sensor. When the data bit width of the readout image signal is Y bits, Y column lines are connected, the pixel units connected to each column line have the same color, and the multiple pixel units connected to each column line have an equal number of rows spaced apart. For example, in FIG3 , the data bit width is 2 bits, 2 column lines are connected, the pixel units connected to each column line have the same color, and the pixel units connected to each column line are spaced apart by one row. In FIG19 , the data bit width is 4 bits, 4 column lines are connected, the pixel units connected to each column line have the same color, and the pixel units connected to each column line are spaced apart by three rows. By connecting pixel units of the same color to the same column line, the technical effect of faster pixel binning can be achieved. It should be noted that because the column lines increase the actual area of ​​the quantization circuit and occupy the layout area of ​​the image sensor, as a preferred solution, Y≤4, that is, the data bit width of the readout image signal is 4 bits and 4 column lines are connected.

[0112] Example 2

[0113] This embodiment provides a method for reading the image sensor 10 described in the first embodiment, comprising: reading image signals from K rows of pixel units 100 row by row. Specifically, when reading the image sensor 10 provided in the first embodiment, the image signals of the pixel units 100 in the image sensor 10 are read row by row, starting from the first row. The image signals include a reset signal and a pixel signal.

[0114] As shown in Figures 5-9, among K rows of pixel units, any row of pixel units includes (Z+1) different conversion gain modes, namely, one high conversion gain mode and Z low conversion gain modes, where Z ≥ K. It should be noted that the value of Z is determined by the value of K and the structure of the gain control circuit. For example, when the gain control circuit includes (K-1) connecting lines, Z = K. When the gain control circuit also includes switching transistors, Z > K. Below, this solution uses any row among the K rows (e.g., row 1) as the selected row to illustrate the read control of different conversion gain modes:

[0115] As shown in FIG20 , the specific steps for reading the image signal of the first row of pixel units 100 in the high conversion gain (HCG) mode are as follows: turning on the reset transistor M2 and the gain control transistor M3 in the first row of pixel units 100 to reset the floating diffusion node FD1 in the first row of pixel units 100; turning off the gain control transistor M3 in the first row of pixel units 100 to read the reset signal of the first row of pixel units 100 (e.g., at moment N_1); turning on the transfer transistor M1 in the first row of pixel units 100 to perform charge transfer in the HCG mode and read the pixel signal of the first row of pixel units 100 (e.g., at moment S_1).

[0116] Specifically, for different circuit structures of the gain control circuit 200 (including the case of the (K-1) segment connecting line, as shown in Figures 5 and 7, and the case of also including the switching transistor, as shown in Figures 6, 8 and 9), reading the reset signal, charge transfer and reading the pixel signal are all performed during the period when the gain control transistor M3 in the first row of pixel units 100 is turned off. At this time, the gain capacitance value of the first row of pixel units 100 is the capacitance value of the floating diffusion node itself in this row, that is, Cfd1, and its conversion gain is q / Cfd1.

[0117] When executing this step, the reset transistors M2 in the K rows of pixel units 100 are always turned on. In fact, the reset transistors M2 in each row of pixel units 100 can also be turned off after the reset operation is performed; however, since the gain control transistors M3 in each row of pixel units 100 are in a turned-off state when reading the reset signal and the pixel signal, even if the reset transistors M2 in each row of pixel units 100 are turned on for a long time, it will not affect the signal reading of the selected row.

[0118] When the gain control transistor M3 in the pixel unit 100 of the selected row is turned off, the gain control transistors M3 in the pixel units 100 of the other rows except the selected row are turned on. In practice, the gain control transistors M3 in the pixel units 100 of each row are turned off only when reading a reset signal, transferring charge, and reading pixel signals, and remain turned on at all other times. Of course, when the gain control transistor M3 in the pixel unit 100 of the selected row is turned off, the gain control transistors M3 in the pixel units 100 of the other rows can also be turned off, which has no effect on the signal reading of the selected row.

[0119] The pixel unit 100 further includes a selection transistor M5, through which the reset signal and the pixel signal are read out in a row selection manner; when reading the reset signal and the pixel signal, the selection transistor M5 in the pixel unit 100 of the selected row is turned on, and the selection transistors M5 in the pixel units 100 of the other rows except the selected row are turned off, thereby completing the readout of the reset signal and the pixel signal of the selected row.

[0120] Taking the first low conversion gain (LCG1) mode as an example, the LCG1 mode is the mode with the highest conversion gain among all low conversion gain modes; as shown in Figure 21, the specific steps of reading the image signal of the first row of pixel units 100 in the LCG1 mode are as follows: turning on the reset transistor M2 and the gain control transistor M3 in the first row of pixel units 100, turning off the gain control transistor M3 in the pixel units 100 in other rows except the first row, and performing a reset operation on the floating diffusion node in the first row of pixel units 100; turning off the reset transistor M2 in the first row of pixel units 100, and reading the reset signal of the first row of pixel units 100 (such as at the N_1 moment); turning on the transfer transistor M1 in the first row of pixel units 100, performing charge transfer in the LCG1 mode and reading the image signal of the first row of pixel units 100 (such as at the S_1 moment).

[0121] Specifically, for the case where the gain control circuit 200 includes (K-1) segments of connecting lines, as shown in Figures 5 and 7, the reset transistor M2 and the gain control transistor M3 in the pixel units 100 in the first row are turned on, and the gain control transistors M3 in the pixel units 100 in other rows except the first row are turned off. At this time, the gain capacitance value of the pixel units 100 in the first row is Cfd1+Ca, and its conversion gain is q / (Cfd1+Ca), which is smaller than the conversion gain in the HCG mode and is the maximum conversion gain in all low conversion gain modes.

[0122] For the case where the gain control circuit 200 also includes a switching transistor, as shown in Figures 6, 8 and 9, before the floating diffusion node in the selected row of pixel units 100 is reset, the reset transistor M2 and the gain control transistor M3 in the first row of pixel units 100 are turned on and the gain control transistors M3 in the pixel units 100 in other rows except the first row are turned off, and all switching transistors on the connecting lines need to be turned off. At this time, the gain capacitance value of the first row of pixel units 100 is Cfd1+Cb, and its conversion gain is q / (Cfd1+Cb), which is smaller than the conversion gain in the HCG mode and is the maximum conversion gain of all low conversion gain modes.

[0123] The pixel unit 100 also includes a select transistor M5, which performs row-select readout of the reset signal and pixel signal for the selected row. When reading the reset signal and image signal, the select transistor M5 in the pixel unit 100 in the selected row is turned on, while the select transistors M5 in the pixel units 100 in all rows other than the selected row are turned off, completing the readout of the reset signal and pixel signal for the selected row.

[0124] Taking the second low conversion gain (LCG2) mode as an example, for the case where the gain control circuit 200 includes (K-1) segments of connecting lines (as shown in Figures 5 and 7), the specific steps for reading the image signals of the first row of pixel units 100 in the LCG2 mode are as follows: turning on the reset transistor M2 and the gain control transistor M3 in the first row of pixel units 100, turning on the gain control transistor M3 in the second row of pixel units 100, turning off the gain control transistors M3 in the pixel units 100 in rows other than the first and second rows, and performing a reset operation on the floating diffusion nodes in the first row of pixel units 100; turning off the reset transistor M2 in the first row of pixel units 100, and reading the reset signal of the first row of pixel units 100; turning on the transfer transistor M1 in the first row of pixel units 100, performing charge transfer in the LCG2 mode, and reading the image signals of the first row of pixel units 100. The gain capacitance value of the pixel units 100 in the first row is Cfd1+Ca+Cfd2, and the conversion gain thereof is q / (Cfd1+Ca+Cfd2), which is smaller than the conversion gain corresponding to the LCG1 mode.

[0125] By analogy, the third to (Z-1)th low conversion gain modes are achieved by increasing the number of open gain control transistors M3 in the non-selected row pixel units 100. For example, in the third low conversion gain (LCG3) mode, the gain control transistors M3 in the 1st to 3rd row pixel units 100 are opened and the gain control transistors M3 in the other rows of pixel units 100 are closed; in the fourth low conversion gain (LCG4) mode, the gain control transistors M3 in the 1st to 4th row pixel units 100 are opened and the gain control transistors M3 in the other rows of pixel units 100 are closed, etc. Accordingly, the conversion gains in different low conversion gain modes gradually decrease.

[0126] For the case where the gain control circuit 200 also includes a switching transistor (as shown in Figures 6, 8, and 9), the specific steps for reading the image signal of the first row of pixel units 100 in the LCG2 mode are as follows: turning on the reset transistor M2 and the gain control transistor M3 in the first row of pixel units 100, turning off the gain control transistor M3 in the pixel units 100 in other rows except the first row, turning on the first switching transistor, turning off the other switching transistors except the first switching transistor, and performing a reset operation on the floating diffusion node in the first row of pixel units 100; turning off the reset transistor M2 in the first row of pixel units 100, and reading the reset signal of the first row of pixel units 100; turning on the transfer transistor M1 in the first row of pixel units 100, performing charge transfer in the LCG2 mode, and reading the image signal of the first row of pixel units 100. 6 and 9 , the gain capacitance value of the pixel unit 100 in the first row is Cfd1+Ca, and its conversion gain is q / (Cfd1+Ca), which is less than the conversion gain in the LCG1 mode; for the structure shown in FIG8 , the gain capacitance value of the pixel unit 100 in the first row is Cfd1+Cb+Cc+Cd, and its conversion gain is q / (Cfd1+Cb+Cc+Cd), which is less than the conversion gain in the LCG1 mode.

[0127] The third to (Z-1)th low conversion gain modes are achieved by increasing the number of open gain control transistors M3 in the non-selected row pixel units 100 and / or the number of open switch transistors in the gain control circuit 200. Accordingly, the conversion gains in different low conversion gain modes gradually decrease.

[0128] In the second through (Z-1)th low conversion gain modes, when performing row-selective readout of the reset signal and pixel signal of the selected row via the select transistor M5, when reading the reset signal and image signal, the select transistor M5 in the pixel unit 100 of the selected row is turned on, while the select transistors M5 in the pixel units 100 of all rows other than the selected row are turned off, completing the readout of the reset signal and pixel signal of the selected row. Of course, the select transistors M5 of the row in which the gain control transistor M3 is turned on can also be turned on, using a multi-row shared readout method to read the reset signal and pixel signal of the first row of pixel units 100, which can effectively improve the signal readout speed.

[0129] Taking the Zth lowest conversion gain (LCGz) mode as an example, the LCGz mode is the mode with the lowest conversion gain among all low conversion gain modes; as shown in Figures 22 and 23, the specific steps of reading the image signal of the first row of pixel units 100 in the Zth lowest conversion gain mode LCGz are as follows: turning on the gain control transistor M3 in the K rows of pixel units 100, turning on the reset transistor M2 in the first row of pixel units 100, and performing a reset operation on the floating diffusion node in the first row of pixel units 100; turning off the reset transistor M2 in the first row of pixel units 100, and reading the reset signal of the first row of pixel units 100 (such as at moment N_1); turning on the transfer transistor M1 in the first row of pixel units 100, performing charge transfer in the LCGz mode and reading the pixel signal of the first row of pixel units 100 (such as at moment S_1).

[0130] Specifically, when the gain control circuit 200 includes (K-1) segments of connecting lines, as shown in Figures 5 and 7 , when the gain control transistors M3 in K rows of pixel cells 100 are turned on, the K rows of pixel cells 100 will share each other's floating diffusion nodes. When the gain control circuit 200 also includes switching transistors, as shown in Figures 6 , 8 , and 9 , before resetting the floating diffusion nodes in the selected row of pixel cells, when the gain control transistors M3 in K rows of pixel cells 100 are turned on, all switching transistors must also be turned on. In this case, the K rows of pixel cells 100 will share each other's floating diffusion nodes. The gain capacitance of the first row of pixel cells 100 is Cfd1+Ca+Cfd2+…+Cfdk, and its conversion gain is q / (Cfd1+Ca+Cfd2+…+Cfdk), which is the minimum conversion gain value among all low conversion gain modes.

[0131] The pixel unit 100 also includes a selection transistor M5, which performs row-selection reading of the reset signal and pixel signal of the selected row through the selection transistor M5. In one embodiment, when reading the reset signal and image signal, as shown in FIG22, the selection transistor M5 in the pixel unit 100 of the selected row is turned on, and the selection transistors M5 in the pixel units 100 of the other rows except the selected row are turned off, completing the reading of the reset signal and pixel signal of the selected row. In another embodiment, when reading the reset signal and image signal, as shown in FIG23, the selection transistor M5 in the pixel unit 100 of the K row is always turned on, and the reset signal and pixel signal of the pixel unit 100 of the first row are read out by using a joint readout method of the selected row and the non-selected row, which can effectively improve the signal readout speed.

[0132] It is understandable that when facing changes in dynamic images, for example, when entering a high-light scene from a dark-light scene, the conversion gain mode needs to be switched from a high-conversion gain mode to a low-conversion gain mode. For example, when entering a dark-light scene from a high-light scene, the conversion gain mode needs to be switched from a low-conversion gain mode to a high-conversion gain mode. No reset operation is performed during the switching between high and low conversion gains.

[0133] Example 3

[0134] This embodiment provides an electronic device including the image sensor 10 described in the first embodiment. In practice, the electronic device may include, but is not limited to, security cameras, automotive electronic cameras, mobile phone cameras, drones, machine vision systems, and existing cameras.

[0135] In summary, the image sensor, its reading method, and electronic device of the present application provide more and richer low conversion gains by using a gain control circuit in the image sensor to connect the drain ends of the gain control transistors in K rows of pixel units located in the same column. In other words, by controlling the number of capacitors connected to one end of the gain control transistor in the LCG mode of the image sensor to adjust the conversion gain and thus improve the dynamic range, more delicate images can be output for different high-light scenes; the image signal readout efficiency of the present invention is higher, the noise level of the circuit is lower, and the performance of the image sensor can be further improved.

[0136] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. An image sensor, characterized in that: The invention comprises a plurality of pixel units arranged in an array and at least one gain control circuit, wherein: The pixel unit comprises: at least one photosensitive unit, a floating diffusion node, a gain control transistor, a source follower transistor and a reset transistor, wherein the photosensitive unit is connected to the floating diffusion node through a corresponding transmission transistor, and the reset transistor and the gain control transistor are sequentially connected to the floating diffusion node and are commonly connected to the gate terminal of the source follower transistor; The pixel units in each row in the same column share the same column line in every X rows, and the pixel units in adjacent (X×Y) rows are read out through Y column lines respectively, where X is an integer greater than or equal to 1, and Y is an integer greater than or equal to 2; The gain control circuit is connected to the drain ends of the gain control transistors in the K rows of pixel units in the same column, where K is an integer greater than or equal to 2.

2. The image sensor according to claim 1, characterized in that The gain control circuit includes (K-1) segments of connecting wires, and the (K-1) segments of the connecting wires are sequentially connected to the drain ends of the gain control transistors in the K rows of pixel units.

3. The image sensor according to claim 2, characterized in that Among the (K-1) sections of connecting wires, at least one section of the connecting wire is provided with a switching transistor.

4. The image sensor according to claim 3, characterized in that: When K is an even number, in the (K-1)th segment of the connecting lines, a switch transistor is provided only on the connecting line between the pixel units in the K / 2th row and the pixel units in the (K / 2+1)th row.

5. The image sensor according to claim 3, characterized in that: In the (K-1) segment of connecting wires, each segment of the connecting wires is provided with a switching transistor.

6. The image sensor according to any one of claims 2 to 5, characterized in that: In a direction perpendicular to the pixel unit, the orthographic projection of the connecting line overlaps with the orthographic projection of the photosensitive unit, and the overlapping area ratio is no more than 50%.

7. The image sensor according to claim 1, characterized in that: The pixel units in every K rows in the same column constitute a first pixel group, and each of the first pixel groups corresponds to one of the gain control circuits.

8. The image sensor according to claim 1, characterized in that The pixel units in each (X×Y) row in the same column form a second pixel group, and corresponding rows in each of the second pixel groups are connected to the same column line.

9. The image sensor according to claim 1, characterized in that: When the number of the photosensitive units in the pixel unit is greater than one, the plurality of photosensitive units are configured to receive light of the same color; wherein the plurality of photosensitive units constitute a shared pixel unit.

10. The image sensor according to claim 9, characterized in that: The number of the photosensitive units in the pixel unit is four, and the four photosensitive units are arranged in a 2×2 array; wherein the photosensitive unit includes a photosensitive element and a transfer transistor, and the photosensitive element is connected to the floating diffusion node through the transfer transistor.

11. The image sensor according to claim 1, characterized in that: The pixel unit further includes a selection transistor connected to a source terminal of the source follower transistor.

12. A method for reading an image sensor according to any one of claims 1 to 11, characterized in that: The image signals of the K rows of pixel units are read row by row, wherein the image signals include a reset signal and a pixel signal.

13. The method for reading an image sensor according to claim 12, characterized in that: The image sensor reading method comprises: Turning on the reset transistor and the gain control transistor in the pixel unit of the selected row to reset the floating diffusion node in the pixel unit of the selected row; turning off the gain control transistor in the pixel unit of the selected row to read the reset signal of the pixel unit of the selected row; The transfer transistors in the pixel units in the selected row are turned on, and charge transfer is performed in a high conversion gain mode and pixel signals of the pixel units in the selected row are read.

14. The method for reading an image sensor according to claim 13, characterized in that: The reset transistors in the pixel units of the K rows are always turned on; when the gain control transistors in the pixel units of the selected row are turned off, the gain control transistors in the pixel units of the other rows except the selected row are turned on; the pixel units also include selection transistors, and when reading the reset signal and the pixel signal, the selection transistors in the pixel units of the selected row are turned on, and the selection transistors in the pixel units of the other rows except the selected row are turned off.

15. The method for reading an image sensor according to claim 12, characterized in that: The image sensor reading method comprises: Turning on the reset transistor and the gain control transistor in the pixel unit of the selected row, turning off the gain control transistor in the pixel units of other rows except the selected row, and performing a reset operation on the floating diffusion node in the pixel unit of the selected row; turning off the reset transistor in the pixel unit of the selected row, and reading a reset signal of the pixel unit of the selected row; The transfer transistors in the pixel units of the selected row are turned on, and charge transfer is performed in a first low conversion gain mode and pixel signals of the pixel units of the selected row are read.

16. The method for reading an image sensor according to claim 15, characterized in that: When the gain control circuit further includes a switch transistor, before performing a reset operation on the floating diffusion node in the pixel unit of the selected row, a step of turning off all the switch transistors is also included.

17. The method for reading an image sensor according to claim 15, characterized in that: The pixel unit further includes a selection transistor. When the reset signal and the pixel signal are read, the selection transistor in the pixel unit of the selected row is turned on, and the selection transistors in the pixel units of other rows except the selected row are turned off.

18. The method for reading an image sensor according to claim 12, characterized in that: The image sensor reading method comprises: Turning on the gain control transistors in the pixel units of the K rows, turning on the reset transistors in the pixel units of the selected row, and performing a reset operation on the floating diffusion nodes in the pixel units of the selected row; turning off the reset transistors in the pixel units of the selected row, and reading the reset signals of the pixel units of the selected row; The transfer transistors in the pixel units in the selected row are turned on, charge transfer is performed in a Zth lowest conversion gain mode, and pixel signals of the pixel units in the selected row are read, wherein Z is an integer greater than or equal to K.

19. The method for reading an image sensor according to claim 18, characterized in that: When the gain control circuit further includes a switch transistor, before performing a reset operation on the floating diffusion node in the pixel unit of the selected row, a step of turning on all the switch transistors is also included.

20. The method for reading an image sensor according to claim 18, characterized in that: The pixel unit also includes a selection transistor. When reading the reset signal and the pixel signal, the selection transistor in the pixel unit of the selected row is turned on, and the selection transistors in the pixel units of other rows except the selected row are turned off, or the selection transistors in the pixel units of row K are always turned on.

21. An electronic device, characterized in that: Comprising the image sensor as claimed in any one of claims 1 to 11.

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