L1d cache to l2 cache-based alias processing system and method, and related device

Abstract

The present invention is suitable for the field of hardware chip design, and particularly relates to an L1D cache to L2 cache-based alias processing method and system, and a related device. The present invention provides a method based on an L1D cache to L2 cache structure and used for solving an alias problem of an L1D cache, and corresponding system modules. The method provided by the present invention can maximize the hardware resource efficiency, and does not limit the structures of chips, the types of hardware systems, the compatibility of operating systems, and the performance of chips; in addition, modules realized on the basis of a cache do not greatly increase the overall power consumption of systems and have good expandability.

Description

Alias ​​processing system, method and related equipment based on L1D-L2 cache Technical Field

[0001] The present invention is applicable to the field of hardware chip design, and in particular relates to an alias processing method, system and related equipment based on L1D-L2 cache. Background Art

[0002] As the industry's performance requirements for processor chips continue to increase, processor chips are being used in more scenarios. As one of the most important modules affecting the performance of modern computer systems, multi-level cache technology has been widely discussed and studied.

[0003] Most modern multi-level cache subsystems include three levels of cache: L1, L2, and L3. The L1 cache further includes the L1D cache (level 1 data cache) and the L1I cache (level 1 instruction cache). Modern L1D caches are often designed as VIPT (virtual address indexed). This design allows virtual addresses sent from the CPU core to access the TLB (translation lookaside buffer) and L1D cache in parallel, improving performance and preventing ambiguity, as shown in Figure 1. Furthermore, the L1D cache typically implements a write-allocate, write-back policy, meaning that write requests from the CPU core are allocated to the L1D cache and written back to main memory only when evicted or instructed to do so.

[0004] However, this approach of using virtual address indexing carries the risk of cache aliasing, a problem caused by multiple virtual addresses mapping to the same physical address but being cached in different cache lines, as shown in Figure 2. For example, assume that virtual addresses VA1 and VA2, which map to the same physical address, are initially populated into the L1D cache's set x and set y (data groups), respectively. Process A writes data Dx to VA1, followed by process B writing data Dy to VA2. Process A then reads data from VA1. According to program execution order, process A should read data Dy (VA1 and VA2 correspond to the same physical address). However, because the read request is detected as a hit in the L1D cache's set x, it reads data Dx instead, resulting in a coherency error. If the L1D cache is designed to be 32KB in size and 4-way set associative, with a total of 128 groups, a 7-bit VA index is required, while the physical page index is only 6 bits, as shown in Figure 3. This can cause virtual addresses that should index the same group to index different groups.

[0005] There are four existing methods to solve the cache alias problem:

[0006] The first solution is to modify the L1D cache size or set associativity to ensure that the number of bits in the virtual address index is less than or equal to the number of bits in the physical address index. However, this method places significant restrictions on the hardware architecture, greatly compresses the cache storage size, and significantly reduces the performance of the processor chip.

[0007] Second, at the software level, the operating system uses page coloring and other technologies to force the alias bits of the virtual address to remain the same, so that the virtual address will always be mapped to the same cache data group. However, this method increases the burden on the operating system design and reduces the processor chip's compatibility with the operating system.

[0008] Third, at the hardware level, by adding banks to the VIPT cache, banks are divided according to alias bits, and cache lines in two banks are written simultaneously during write operations (Yao Yongbin, Superscalar Processor Design, Tsinghua University Press, 2014). However, this approach reduces cache storage capacity, increases bandwidth pressure for write requests, and increases cache module power consumption. Furthermore, this solution is not scalable, meaning the number of banks increases exponentially with the addition of alias bits.

[0009] Fourth, at the hardware level, the directory of the downstream cache is used to record the alias bit of the corresponding L1D cache line in the directory of the L2 cache to detect aliasing problems. When a read request from the same physical address is detected and it is inconsistent with the alias bit in the directory, an aliasing problem occurs. At this time, the data corresponding to the physical address stored in the L1D cache is forcibly evicted and the data corresponding to the new virtual address is filled back. At the same time, the alias bit recorded in the directory of the L2 cache is changed. However, this method requires the cache subsystem to be designed as a directory-based type, which is not applicable to the snoop-based cache subsystem.

[0010] In summary, existing technologies for solving the aliasing problem have limitations in hardware architecture, cache subsystem type, and scalability.

[0011] Summary of the Invention

[0012] The present invention provides an L1D-L2 cache-based alias processing method, system and related equipment, aiming to solve the limitations of hardware architecture, cache subsystem type and scalability in the existing technology when processing alias problems.

[0013] In a first aspect, the present invention provides an alias processing method based on L1D-L2 cache, the alias processing method comprising the following steps:

[0014] Establishing a tag copy random cache, wherein the tag copy random cache is used to copy the tag random cache in the L1D cache, and the tag random cache and the tag copy random cache are both composed of multiple data groups;

[0015] Establishing a valid array, and using the valid array to mark the data validity of each data group in the tag copy random cache;

[0016] Obtaining a check request sent by the L1D cache, wherein the check request is issued by the L1D when requesting data from the L2 cache;

[0017] The tag copy random cache is checked based on the valid array, and it is determined whether the check request hits the data group in the tag copy random cache. If so:

[0018] Invalidating the inspection request in the L2 cache and storing the inspection request;

[0019] A flush request having a physical address corresponding to the check request is sent to the L1D cache, where the flush request is used to delete the data group corresponding to the physical address in the L1D cache.

[0020] Furthermore, the data groups of the tag random cache are associative in N ways, and the data groups of the tag copy random cache are associative in 2N ways.

[0021] Furthermore, after the step of invalidating the inspection request in the L2 cache and storing the inspection request, the method further includes the following steps:

[0022] Receive a cache line corresponding to the physical address from the L1D cache, and release the check request to the L2 cache.

[0023] Furthermore, the alias processing method further includes the following steps:

[0024] Obtaining a fill request sent by the L1D cache, wherein the fill request is issued by the L1D cache when filling data into the L2 cache;

[0025] Based on the fill request, a data group having the same physical address as the fill request is written into the tag copy random access cache, and the valid array is updated to mark the validity of the data group in the tag copy random access cache.

[0026] Furthermore, after the step of invalidating the inspection request in the L2 cache and storing the inspection request, the method further includes the following steps:

[0027] The data group corresponding to the physical address is marked as invalid in the valid array.

[0028] In a second aspect, the present invention further provides an alias processing system based on an L1D-L2 cache, the alias processing system comprising:

[0029] A tag replication module is used to establish a tag replication random cache, wherein the tag replication random cache is used to replicate the tag random cache in the L1D cache, and the tag random cache and the tag replication random cache are both composed of multiple data groups;

[0030] A valid array module, configured to establish a valid array and use the valid array to mark the data validity of each data group in the tag copy random cache;

[0031] A fill-back buffer module is used to obtain a check request sent by the L1D cache, wherein the check request is issued by the L1D when requesting data from the L2 cache;

[0032] A control unit module is configured to perform a check in the tag copy random cache based on the valid array and determine whether the check request hits a data group in the tag copy random cache. If so:

[0033] Invalidating the inspection request in the L2 cache and storing the inspection request;

[0034] A flush request having a physical address corresponding to the check request is sent to the L1D cache, where the flush request is used to delete the data group corresponding to the check request in the L1D cache.

[0035] Furthermore, the control unit module is also used for:

[0036] Receive a cache line corresponding to the physical address from the L1D cache, and release the check request to the L2 cache.

[0037] Furthermore, the control unit module is also used for:

[0038] Obtaining a fill request sent by the L1D cache, wherein the fill request is issued by the L1D cache when filling data into the L2 cache;

[0039] Based on the fill request, a data group having the same physical address as the fill request is written into the tag copy random access cache, and the valid array is updated to mark the validity of the data group in the tag copy random access cache.

[0040] In a third aspect, the present invention further provides a computer device comprising: a memory, a processor, and an L1D-L2 cache-based alias processing program stored in the memory and executable on the processor, wherein the processor implements the steps of the L1D-L2 cache-based alias processing method as described in any one of the above embodiments when executing the L1D-L2 cache-based alias processing program.

[0041] In a fourth aspect, the present invention further provides a computer-readable storage medium, on which an alias processing program based on an L1D-L2 cache is stored. When the alias processing program based on the L1D-L2 cache is executed by a processor, the steps of the alias processing method based on the L1D-L2 cache as described in any one of the above embodiments are implemented.

[0042] The beneficial effect achieved by the present invention lies in proposing a method and corresponding system module for solving the alias problem of L1D cache based on the L1D cache-L2 cache structure. The method proposed by the present invention can maximize the efficiency of hardware resources without imposing restrictions on chip structure, hardware system type, operating system compatibility, and chip performance. At the same time, the module implemented based on the cache will not significantly increase the overall system power consumption and has good scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1 is a schematic diagram of the process of virtual address indexing in the L1D cache;

[0044] FIG2 is a schematic diagram showing the principle of virtual address indexing;

[0045] FIG3 is a schematic diagram of allocation of virtual addresses and physical addresses;

[0046] FIG4 is a flowchart of the steps of an alias processing method based on L1D-L2 cache provided by an embodiment of the present invention;

[0047] FIG5 is a schematic diagram showing a structural comparison between a tag random cache in an L1D and a tag copy random cache provided by an embodiment of the present invention;

[0048] FIG6 is a schematic structural diagram of an alias processing system 200 based on an L1D-L2 cache according to an embodiment of the present invention;

[0049] FIG7 is a schematic diagram of the structure of a computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0051] Please refer to FIG. 4 , which is a flowchart of a method for handling aliases based on an L1D-L2 cache according to an embodiment of the present invention. The method comprises the following steps:

[0052] S1. Establish a tag copy random access cache, where the tag copy random access cache is used to copy the tag random access cache in the L1D cache. Both the tag random access cache and the tag copy random access cache are composed of multiple data groups.

[0053] Specifically, the tag copy RAM is independently constructed and maintained in the L2 cache. The embodiments of the present invention implement detection and processing of aliasing issues based on the tag copy RAM. Furthermore, the data group associativity of the tag copy RAM is N-way, while the data group associativity of the tag copy RAM is 2N-way. Exemplarily, the tag copy RAM can be obtained by copying the tag RAM in the L1D cache. The difference is that the number of associative ways of the data group needs to be modified during construction. As shown in FIG5 , the tag copy RAM is 4-way set associative, while the tag copy RAM is 8-way set associative. More specifically, the tag copy RAM is of the PIPT (Physical Address Index) type. Furthermore, unless otherwise specified, the L1D-L2 cache-based aliasing processing method in the embodiments of the present invention is implemented in a system environment where the L1D cache and the L2 cache are strictly mutually exclusive. In such an environment, the L1D cache and the L2 cache will store completely different data. This design method is intended to maximize cache utilization.

[0054] S2. Establish a valid array, and use the valid array to mark the data validity of each data group in the tag copy random cache.

[0055] The valid data is consistent with the array in the L1D cache and is used to mark the validity of the data. The valid array is used to quickly filter out data groups with valid data when the cache receives a read request, thereby improving the speed of data processing.

[0056] S3. Obtain a check request sent by the L1D cache, where the check request is sent by the L1D cache when requesting data from the L2 cache.

[0057] The read request sent by the L1D cache to the L2 cache is treated as a check request and is used to read the data of the corresponding physical address through the L2 cache. This is because of the multi-level design of the cache. Only when the read request of the L1D cache misses the data in the L1D cache itself will the read request be further sent to the L2 cache. In other words, whether it will cause aliasing problems is determined only after the L1D cache sends the check request.

[0058] S4. Check the tag copy random cache based on the valid array and determine whether the check request hits the data group in the tag copy random cache. If so:

[0059] Invalidating the inspection request in the L2 cache and storing the inspection request;

[0060] A flush request having a physical address corresponding to the check request is sent to the L1D cache, where the flush request is used to delete the data group containing the physical address in the L1D cache.

[0061] Regarding the detection of aliasing problems, specifically, two virtual addresses with different alias bits will be mapped to different data groups in the L1D cache, but will be mapped to the same data group in the tag copy random cache. This is because the number of associative ways of the data group of the tag copy random cache in the embodiment of the present invention is twice that of the tag random cache in the L1D cache. In the index of the physical address corresponding to the virtual address, since the number of bits is the same, but the latter has a larger index range, a request that is judged to be a miss due to the aliasing problem in the L1D cache will be judged to be a hit in the tag copy random cache in the embodiment of the present invention, and the aliasing problem is detected at this time.

[0062] For example, a read request with a virtual address index of 0x1d accesses the L1D cache for the first time. At this time, the alias bit of the read request is 0, and a compulsory miss occurs in the L1D cache. miss), and sends a check request to the L2 cache. When the L2 cache returns the data to the L1D cache from the downstream for filling, the tag corresponding to the data is filled back into the data group (set) 29 of the tag random cache. At the same time, the tag copy random cache will also receive the signal and fill the corresponding copy tag back into the copied data group 29. Afterwards, a read request with a virtual address index of 0x5d accesses the L1D cache. At this time, the alias bit of the read request is 1, and an alias problem occurs in the L1D cache (the lower six bits of the physical address index of 0x1d and 0x5d are the same), and the data group 93 is incorrectly addressed, resulting in a non-true miss (the data at the same physical address already exists in the L1D cache), and a check request is sent to the L2 cache. At this time, since the index of the tag copy random cache in the embodiment of the present invention includes the address of 0x5d, the copied data group 29 will be addressed, and a hit will occur in the tag copy random cache, thereby realizing the detection of the alias problem.

[0063] Regarding the handling of aliasing issues, specifically, when an aliasing issue is detected, the check request that caused the aliasing issue will be immediately terminated, and a flush request for the same physical address will be sent to the L1D cache. This step has two functions:

[0064] First, the check request that caused the aliasing problem is terminated because the check request is already in the L2 cache. After invalidating it, the execution of the request that caused the aliasing problem can be temporarily stopped. The aliasing processing method implemented in the embodiment of the present invention is implemented based on an independent cache architecture. After the check request is invalidated, the check request can be saved based on the independent cache architecture to facilitate subsequent processing.

[0065] Secondly, a flush request with the physical address is sent to the L1D cache because an aliasing problem has been detected at this time, that is, data groups with different alias bits but the same indexed physical address already exist in the tag random cache of the L1D cache. In order to avoid the aliasing problem caused by these data groups again, the data group containing the physical address is deleted from the L1D cache through a flush request.

[0066] On the other hand, since step S4 is designed as a judgment step for detecting an alias problem, when the inspection request does not hit the data group in the tag copy random cache, the alias problem will not be detected, that is, there is no need to process the current inspection request.

[0067] Furthermore, after the step of invalidating the inspection request in the L2 cache, the method further includes the following steps:

[0068] Receive a cache line corresponding to the physical address from the L1D cache, and release the check request to the L2 cache.

[0069] This step is to continue executing the original inspection request after handling the alias problem. From the perspective of program execution, although the inspection request has an alias problem, the request is not illegal, so it needs to be executed normally. In the above steps, the embodiment of the present invention saves the inspection request based on an independent cache architecture. When the cache line corresponding to the physical address issued by the L1D cache is received again, it means that the data corresponding to the inspection request address is requested to be filled into the L1D cache. Furthermore, the cache line issued by the L1D cache is to read data from the physical address, but the corresponding instruction has been independently saved. In order to improve processing efficiency, the embodiment of the present invention can directly release the corresponding inspection request from the saved request to the L2 cache to realize the re-execution of the request.

[0070] Furthermore, the alias processing method further includes the following steps:

[0071] Obtaining a fill request sent by the L1D cache, wherein the fill request is issued by the L1D cache when filling data with the L2 cache;

[0072] Based on a fill request, a data group having the same physical address as the fill request is written into the tag copy random access cache, and the valid array is updated to mark the validity of the data group in the tag copy random access cache.

[0073] This step is to ensure that the content of the tag copy random cache established and maintained by the embodiment of the present invention is consistent with the L1D cache when the tag random cache in the L1D cache is filled with new data.

[0074] Furthermore, after the step of invalidating the inspection request in the L2 cache, the method further includes the following steps:

[0075] The data group corresponding to the physical address is marked as invalid in the valid array.

[0076] This step is to improve the reading and writing efficiency when reading and writing through the tag copy random cache. In an embodiment of the present invention, the valid array is used to mark the validity of the data group. After the check request is invalid in the L2 cache, the data in the tag copy random cache is also hit due to the data group of the alias problem in the L1D cache. Therefore, the hit data group is marked as invalid by the valid array, which can improve the inspection efficiency during subsequent data reading and writing.

[0077] The beneficial effect achieved by the present invention lies in proposing a method and corresponding system module for solving the alias problem of L1D cache based on the L1D cache-L2 cache structure. The method proposed by the present invention can maximize the efficiency of hardware resources without imposing restrictions on chip structure, hardware system type, operating system compatibility, and chip performance. At the same time, the module implemented based on the cache will not significantly increase the overall system power consumption and has good scalability.

[0078] An embodiment of the present invention further provides an alias processing system based on an L1D-L2 cache. Referring to FIG. 6 , FIG. 6 is a schematic diagram of the structure of an alias processing system based on an L1D-L2 cache provided by an embodiment of the present invention. The alias processing system 200 based on an L1D-L2 cache is implemented using a two-stage pipeline and includes:

[0079] A tag copy RAM module 201 is configured to establish a tag copy random access cache, wherein the tag copy random access cache is configured to copy the tag random access cache in the L1D cache, wherein both the tag random access cache and the tag copy random access cache are composed of multiple data groups.

[0080] A valid array module 202 (valid array), configured to establish a valid array and use the valid array to mark the data validity of each data group in the tag copy random cache;

[0081] A refill prestation module 203 is configured to obtain a check request sent by the L1D cache, wherein the check request is sent by the L1D cache when requesting data from the L2 cache.

[0082] A control unit module 204 is configured to perform a check in the tag copy random cache based on the valid array and determine whether the check request hits a data group in the tag copy random cache. If so:

[0083] Invalidating the inspection request in the L2 cache and storing the inspection request;

[0084] A flush request having a physical address corresponding to the check request is sent to the L1D cache, where the flush request is used to delete the data group containing the physical address in the L1D cache.

[0085] Furthermore, the control unit module 204 is further configured to:

[0086] receiving a cache line corresponding to the physical address from the L1D cache, and releasing the check request to the L2 cache;

[0087] Obtaining a fill request sent by the L1D cache, wherein the fill request is issued by the L1D cache when filling data into the L2 cache;

[0088] Based on the fill request, a data group having the same physical address as the fill request is written into the tag copy random access cache, and the valid array is updated to mark the validity of the data group in the tag copy random access cache.

[0089] Specifically, based on the pipeline design of the L1D-L2 cache alias processing system 200 shown in FIG6 , the input and output signals of the system 200 can be divided into the following parts:

[0090] Input signals: check request, sent from the L1D cache to the L2 cache; evict signal, a write request sent from the L1D cache to the L2 cache, equivalent to a cache line; refill signal, a signal sent by the L1D cache when data is filled back into the L1D cache;

[0091] Output signals: L1D flush request, sent by the system 200 of the embodiment of the present invention to the L1D cache when an aliasing problem is detected; alias kill, sent by the system 200 of the embodiment of the present invention to the L2 cache pipeline to invalidate an instruction when an aliasing problem is detected; L1D read replay, sent by the system 200 of the embodiment of the present invention to the L2 cache to re-execute a check request that was once terminated when the corresponding cache line is flushed from the L1D cache.

[0092] Based on the above input and output signals, the data flows in the L1D-L2 cache alias processing system 200 provided by the embodiment of the present invention mainly include the following four types:

[0093] 1. Alias ​​Problem Check Data Flow: A read request sent by the L1D cache to the L2 cache is treated as a check request and loaded into the fill-back buffer module 203 for inspection. The fill-back buffer module 203 sends a read signal to the valid array module 202 and the tag copy module 201. The control unit module 204 compares the read tag with the data validity, determines whether the data is hit, and generates the necessary signals.

[0094] 2. Alias ​​processing system updates data flow: After receiving data returned from the L2 cache, the L1D cache fills the corresponding RAM and sends a flush request to the alias processing system 200. The corresponding check request has been stored in the fill-back buffer module 203. After receiving the fill-back signal, the fill-back buffer module 203 releases the corresponding request and writes it to the valid array module 202 and the tag copy module 201, completing the data group update.

[0095] 3. Alias ​​Processing System Invalidation Data Flow: The write request sent by the L1D cache to the L2 cache will be regarded as an invalidation signal, and the corresponding entry of the valid array module 202 will be invalidated;

[0096] 4. Alias ​​problem processing data flow: When the control unit module 204 detects the occurrence of an alias problem, it immediately pulls up the alias termination signal to terminate the corresponding read request in the L2 cache pipeline, saves the request at the same time, sends a flush signal to the L1D cache, and waits for the corresponding cache line with the same physical address to be evicted from the L1D cache; when the control unit module 204 receives the evicted same-address signal, it sends the originally terminated read request to the L2 cache pipeline and re-executes it.

[0097] The L1D-L2 cache-based alias processing system 200 can implement the steps of the L1D-L2 cache-based alias processing method in the above embodiment and can achieve the same technical effects. Please refer to the description in the above embodiment and will not be repeated here.

[0098] An embodiment of the present invention further provides a computer device. Please refer to Figure 7, which is a structural diagram of a computer device provided by an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and an L1D-L2 cache-based alias processing program stored in the memory 302 and executable on the processor 301.

[0099] The processor 301 calls the L1D-L2 cache-based alias processing program stored in the memory 302 to execute the steps of the L1D-L2 cache-based alias processing method provided in an embodiment of the present invention. Referring to FIG. 4 , the method specifically includes the following steps:

[0100] S1. Establish a tag copy random cache, where the tag copy random cache is used to copy the tag random cache in the L1D cache, and both the tag random cache and the tag copy random cache are composed of multiple data groups;

[0101] S2. Establish a valid array, and use the valid array to mark the data validity of each data group in the tag copy random cache;

[0102] S3. Obtain a check request sent by the L1D cache, where the check request is issued by the L1D cache when requesting data from the L2 cache;

[0103] S4. Check the tag copy random cache based on the valid array and determine whether the check request hits the data group in the tag copy random cache. If so:

[0104] Invalidating the inspection request in the L2 cache and storing the inspection request;

[0105] A flush request having a physical address corresponding to the check request is sent to the L1D cache, where the flush request is used to delete the data group containing the physical address in the L1D cache.

[0106] Furthermore, after the step of invalidating the inspection request in the L2 cache, the method further includes the following steps:

[0107] Receive a cache line corresponding to the physical address from the L1D cache, and release the check request to the L2 cache.

[0108] This step is to continue executing the original inspection request after handling the alias problem.

[0109] Furthermore, the alias processing method further includes the following steps:

[0110] Obtaining a fill request sent by the L1D cache, wherein the fill request is issued by the L1D cache when filling data into the L2 cache;

[0111] Based on the fill request, a data group having the same physical address as the fill request is written into the tag copy random access cache, and the valid array is updated to mark the validity of the data group in the tag copy random access cache.

[0112] This step is to ensure that the content of the tag copy random cache established and maintained by the embodiment of the present invention is consistent with the L1D cache when the tag random cache in the L1D cache is filled with new data.

[0113] Furthermore, after the step of invalidating the inspection request in the L2 cache, the method further includes the following steps:

[0114] The data group corresponding to the physical address is marked as invalid in the valid array.

[0115] This step is to improve the reading and writing efficiency when reading and writing are performed through the tag replication random cache.

[0116] The computer device 300 provided in the embodiment of the present invention can implement the steps in the alias processing method based on L1D-L2 cache as in the above embodiment, and can achieve the same technical effects. Please refer to the description in the above embodiment and will not be repeated here.

[0117] An embodiment of the present invention further provides a computer-readable storage medium, on which an alias processing program based on the L1D-L2 cache is stored. When the alias processing program based on the L1D-L2 cache is executed by a processor, the various processes and steps in the alias processing method based on the L1D-L2 cache provided in an embodiment of the present invention are implemented, and the same technical effects can be achieved. To avoid repetition, they are not described here.

[0118] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing related hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above-described method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0119] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0120] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better embodiment. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0121] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only a preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. An alias processing method based on L1D-L2 cache, characterized in that: The alias processing method comprises the following steps: Establishing a tag copy random cache, the tag copy random cache is used to copy the tag random cache in the L1D cache, and the tag random cache and the tag copy random cache are both composed of multiple data groups; Establishing a valid array, and using the valid array to mark the data validity of each data group in the tag copy random cache; Obtaining a check request sent by the L1D cache, wherein the check request is issued by the L1D cache when requesting data from the L2 cache; Based on the valid array, the tag copy random cache is checked, and it is determined whether the check request hits the data group in the tag copy random cache. If so: Invalidating the inspection request in the L2 cache and saving the inspection request; A flush request having a physical address corresponding to the check request is sent to the L1D cache, wherein the flush request is used to delete the data group corresponding to the physical address in the L1D cache.

2. The alias processing method based on L1D-L2 cache according to claim 1, characterized in that: The data groups of the tag random cache are connected in N ways, and the data groups of the tag copy random cache are connected in 2N ways.

3. The alias processing method based on L1D-L2 cache according to claim 1, characterized in that: After the step of invalidating the inspection request in the L2 cache and saving the inspection request, the step further includes: Receive a cache line corresponding to the physical address from the L1D cache, and release the check request to the L2 cache.

4. The alias processing method based on L1D-L2 cache according to claim 1, characterized in that: The alias processing method further comprises the following steps: Obtaining a fill request sent by the L1D cache, wherein the fill request is issued when the L1D cache fills data to the L2 cache; Based on the fill request, a data group having the same physical address as the fill request is written into the tag copy random access cache, and the valid array is updated to mark the validity of the data group in the tag copy random access cache.

5. The alias processing method based on L1D-L2 cache according to claim 1, characterized in that: After the step of invalidating the inspection request in the L2 cache and saving the inspection request, the step further includes: The data group corresponding to the physical address is marked as invalid in the valid array.

6. An alias processing system based on L1D-L2 cache, characterized in that: The alias processing system comprises: A tag replication module, used for establishing a tag replication random cache, wherein the tag replication random cache is used for replicating the tag random cache in the L1D cache, wherein both the tag random cache and the tag replication random cache are composed of a plurality of data groups; A valid array module is used to establish a valid array and use the valid array to mark the tag copy random cache Data validity for each data group; A fill back buffer module is used to obtain a check request sent by the L1D cache, wherein the check request is sent by the L1D cache when requesting data from the L2 cache; A control unit module is used to check the tag copy random cache based on the valid array and determine whether the check request hits the data group in the tag copy random cache. If so: Invalidating the inspection request in the L2 cache and saving the inspection request; A flush request having a physical address corresponding to the check request is sent to the L1D cache, wherein the flush request is used to delete the data group corresponding to the physical address in the L1D cache.

7. The alias processing system based on L1D-L2 cache according to claim 6, characterized in that: The control unit module is also used for: Receive a cache line corresponding to the physical address from the L1D cache, and release the check request to the L2 cache.

8. The alias processing system based on L1D-L2 cache according to claim 6, characterized in that: The control unit module is also used for: Obtaining a fill request sent by the L1D cache, wherein the fill request is issued when the L1D cache fills data to the L2 cache; Based on the fill request, a data group having the same physical address as the fill request is written into the tag copy random access cache, and the valid array is updated to mark the validity of the data group in the tag copy random access cache.

9. A computer device, characterized in that: include: A memory, a processor, and an alias processing program based on L1D-L2 cache stored in the memory and executable on the processor, wherein the processor implements the steps of the alias processing method based on L1D-L2 cache as claimed in any one of claims 1 to 5 when executing the alias processing program based on L1D-L2 cache.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores an alias processing program based on L1D-L2 cache, and when the alias processing program based on L1D-L2 cache is executed by the processor, the steps of the alias processing method based on L1D-L2 cache are implemented.

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