Data access method, switch and storage medium

Abstract

A data access method, a switch and a storage medium, which relate to the technical field of switches. The method is applied to a switch. The switch comprises a central processing unit, a substrate management controller, a main controller and at least one device, wherein the central processing unit and the substrate management controller are each connected to the main controller, and the main controller is connected to the at least one device. The method comprises: by means of a main controller, receiving an interface state corresponding to a target interface, and by means of the main controller, allowing, according to the interface state, a central processing unit or a substrate management controller to access at least one device.

Description

Data access method, switch and storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on June 13, 2023, with application number 202310696054.5 and application name “Data Access Method, Switch and Storage Medium”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to a data access method, a switch and a storage medium. Background Art

[0004] As we all know, the I2C bus (Inter-Integrated Circuit, a two-wire serial bus) can include the SMBus (System Management Bus) and the PMBus (Power Management Bus). The I2C bus is a low-speed signal bus widely used in switch systems. Basic hardware management functions of switch systems, including temperature monitoring, voltage and current monitoring, and fan speed monitoring, are all implemented through the I2C bus. The system can even use the I2C bus to complete the on / off control of the PSU (Power Supply Unit) output voltage, realizing the system power-off restart.

[0005] However, the inventors realized that for functions such as temperature monitoring, voltage and current monitoring, fan speed control, and PSU power-off restart in switch systems (especially white-box switches), some customers require them to be implemented by the central processing unit, while some customers require them to be implemented by the baseboard management controller. Therefore, to meet different needs, the I2C bus needs to be connected to different I2C hosts (central processing unit or baseboard management controller). If the same switch needs to meet different customer needs, the conventional design is to implement it by using an I2C multi-host arbitration chip, which not only increases the system design cost, but also increases the complexity of software control.

[0006] Summary of the Invention

[0007] According to an embodiment of the present application, in a first aspect, a data access method is provided. The method is applied to a switch, wherein the switch includes a central processing unit (CPU), a baseboard management controller (BMC), a main controller (MC), and at least one device. The CPU and the BMC are respectively connected to the main controller, and the main controller is connected to the at least one device. The method includes:

[0008] receiving, through the main controller, an interface status corresponding to the target interface; and

[0009] The main controller allows the central processing unit or the baseboard management controller to access at least one device according to the interface status.

[0010] According to an embodiment of the present application, in a second aspect, a switch is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the following steps are implemented:

[0011] receiving, through the main controller, an interface status corresponding to the target interface; and

[0012] The main controller allows the central processing unit or the baseboard management controller to access at least one device according to the interface status.

[0013] According to a third aspect of an embodiment of the present application, a non-volatile computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0014] receiving, through the main controller, an interface status corresponding to the target interface; and

[0015] The main controller allows the central processing unit or the baseboard management controller to access at least one device according to the interface status.

[0016] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0018] FIG1 is a schematic flow chart of a data access method in one or more embodiments;

[0019] FIG2 is a schematic diagram of the structure of a switch in one or more embodiments;

[0020] FIG3 is a schematic flow diagram of an interface status receiving step in one or more embodiments;

[0021] FIG4 is a schematic flow diagram of an access step in one or more embodiments;

[0022] FIG5 is a schematic flow diagram of an access step in one or more embodiments;

[0023] FIG6 is a schematic diagram of the structure of a baseboard management controller access device in a switch in one or more embodiments;

[0024] FIG7 is a schematic diagram of the structure of a central processing unit access device in a switch in one or more embodiments;

[0025] FIG8 is a schematic diagram of the structure of a central processing unit access device in a switch in one or more embodiments;

[0026] FIG9 is a schematic diagram illustrating the principles of data access in one or more embodiments;

[0027] FIG10 is a block diagram of a data access device according to one or more embodiments;

[0028] FIG11 is a diagram of the internal structure of a switch in one or more embodiments;

[0029] FIG12 is a schematic diagram of the structure of a non-volatile computer-readable storage medium in one or more embodiments. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0031] In some embodiments, as shown in FIG1 , a data access method is provided. This method is described using a switch as an example. The switch includes a central processing unit (CPU), a baseboard management controller (BMC), a main controller (MC), and at least one device. The CPU and the BMC are respectively connected to the main controller, which is connected to the at least one device. The method includes the following steps:

[0032] Step 102: Receive the interface status corresponding to the target interface through the main controller.

[0033] 2 shows a schematic diagram of the structure of a switch in one or more embodiments. The switch includes a central processing unit (CPU), a baseboard management controller (BMC), a main controller (MCU), and at least one device. The CPU can be any SOC (System on Chip) controller with an I2C interface / SMBus interface, such as Intel Broadwell D1527 / D1627, Feiteng FT2000 / D2000, etc. The CPU is mainly used for management and control functions of the switch system.

[0034] The baseboard management controller BMC can be any model of baseboard management controller, such as Aspeed AST2520, and the main controller MCU can be any embedded control chip, such as ST's STM32F103RBT6.

[0035] The device may be an I2C device, and the I2C device may be at least one of a board EEPROM, a voltage detection chip, a temperature detection chip, and other I2C device units.

[0036] As shown in FIG2 , the design method of the switch includes a central processing unit, a baseboard management controller, a main controller, and at least one device. The central processing unit and the baseboard management controller are respectively connected to the main controller, and the main controller is connected to at least one device.

[0037] Specifically, when the switch system includes a baseboard management controller (BMC), the BMC controls the interface state of the target interface. Specifically, the BMC outputs the interface state of the target interface, and the main controller receives the interface state corresponding to the target interface. The interface state here includes a low-level state and a high-level state.

[0038] Step 104: Allow the central processing unit or the baseboard management controller to access at least one device according to the interface status through the main controller.

[0039] Specifically, after the main controller receives the interface status corresponding to the target interface, it can control the central processing unit or baseboard management controller to access at least one downstream device based on the interface status. Specifically, when the interface status received by the main controller is in a low-level state, it indicates that the baseboard management controller has not raised the interface status of the target interface and the output voltage value is 0V. Therefore, the main controller determines that the switch system is controlled by the central processing unit, that is, the central processing unit can access at least one downstream device. Conversely, when the interface status received by the main controller is in a high-level state, it indicates that the baseboard management controller has raised the interface status of the target interface and the output voltage value is not 0V. Therefore, the main controller determines that the switch system is controlled by the baseboard management controller, that is, the baseboard management controller can access at least one downstream device.

[0040] In the above data access method, the designed switch includes a central processing unit, a baseboard management controller, a main controller and at least one device. The central processing unit and the baseboard management controller are respectively connected to the main controller, and the main controller is connected to at least one device. There is no need to add additional hardware circuits. The main controller controls the switch to access at least one downstream device by the central processing unit or the baseboard management controller according to the interface status corresponding to the target interface. The switch system is dynamically switched to be controlled by the central processing unit or the baseboard management controller according to demand. The same switch can be used to be compatible with the design requirements of different customers without adding additional hardware, thereby reducing the design cost of the switch system.

[0041] In some embodiments, as shown in FIG3 , receiving, by the main controller, the interface status corresponding to the target interface includes:

[0042] Step 302: Control the interface status corresponding to the general input and output interface via the baseboard management controller.

[0043] Step 304: Receive, via the main controller, the interface status corresponding to the general input / output interface output by the baseboard management controller.

[0044] The baseboard management controller is connected to the main controller and includes an I2C interface and a general-purpose input / output interface (GPIO interface) for outputting I2C bus signals and general-purpose input / output interface signals. The I2C bus signals are used for data communication with the embedded controller's I2C interface. At the same time, the general-purpose input / output interface signals (GPIO interface signals) are used to connect to the general-purpose input / output interface (GPIO interface) of the embedded controller MCU to implement I2C bus switching between the central processing unit and the baseboard management controller. Therefore, the baseboard management controller can control the interface state corresponding to the output of the general-purpose input / output interface (GPIO interface), and the main controller connected to it can receive the interface state corresponding to the general-purpose input / output interface (GPIO interface) output by the baseboard management controller, including low-level state and high-level state.

[0045] In some embodiments, as shown in FIG4 , allowing a central processing unit or a baseboard management controller to access at least one device according to an interface state through a main controller includes:

[0046] Step 402: The main controller determines whether the interface state is a high level state or a low level state.

[0047] Step 404 : When the main controller determines that the interface state is a high level state, the main controller allows the baseboard management controller to access at least one device.

[0048] Specifically, after the main controller receives the interface status corresponding to the universal input and output interface output by the baseboard management controller, it determines whether the received interface status is a high-level state or a low-level state. When the interface status is a high-level state, it means that the baseboard management controller has pulled up the interface status of the universal input and output interface, and the output voltage value is not 0V. Therefore, at this time, the main controller determines that the switch system is controlled by the baseboard management controller, that is, the baseboard management controller can access at least one downstream device.

[0049] In some embodiments, as shown in FIG5 , allowing a baseboard management controller to access at least one device through a host controller includes:

[0050] Step 502: Send a channel selection instruction to the main controller via the baseboard management controller.

[0051] Step 504 : Connecting the target interface channel corresponding to the baseboard management controller to the matching target device bus through the main controller according to the channel selection instruction.

[0052] Step 506: When the connection is successful, access the target device corresponding to the target device bus through the baseboard management controller.

[0053] Among them, when the main controller allows the baseboard management controller to access at least one downstream device, the baseboard management controller can send a channel selection instruction to the main controller. After receiving the channel selection instruction, the main controller parses the information in the channel selection instruction, determines the target interface channel, and connects the target interface channel corresponding to the baseboard management controller with the downstream matching target device bus. When the connection is successful, the baseboard management controller can directly access the target device corresponding to the target device bus.

[0054] In this embodiment, sending the channel selection instruction to the main controller through the baseboard management controller includes: using the corresponding I2C interface through multiple interface channels of the baseboard management controller to send the corresponding channel selection instruction to the main controller.

[0055] For example, as shown in FIG6 , FIG6 is a schematic diagram showing the structure of the baseboard management controller access device in a switch in one or more embodiments. The switch in FIG6 includes a baseboard management controller BMC and a central processing unit CPU. The main controller is an embedded controller MCU. The embedded controller MCU determines that the BCM accesses at least one downstream device, such as a board EEPROM (Electrically Erasable Programmable Read Only Memory), a voltage detection chip, a temperature detection chip, and other I2C devices, based on the interface state corresponding to the general input and output interface (GPIO interface) output by the baseboard management controller BMC being in a high-level state. As can be seen from FIG6 , in addition to the general input and output interface, the baseboard management controller also includes multiple interface channels, each of which corresponds to an I2C interface. Each interface channel of the baseboard management controller can send the corresponding channel selection instruction to the embedded controller through the corresponding I2C interface.

[0056] In this embodiment, the main controller connects the target interface channel corresponding to the baseboard management controller to the matching target device bus according to the channel selection instruction, including: connecting each I2C interface to the matching target device bus according to each channel selection instruction.

[0057] For example, as shown in Figure 6, each interface channel of the baseboard management controller sends a channel selection instruction to the embedded controller through the corresponding I2C interface. After receiving each channel selection instruction, the embedded controller connects each I2C interface corresponding to the baseboard management controller to the matching target device bus according to each channel selection instruction. When the connection is successful, the switch is controlled by the baseboard management controller, and the baseboard management controller can directly access the corresponding downstream device through each I2C interface. For example, the baseboard management controller BMC in Figure 6 can directly access the corresponding board EEPROM (downstream device) through the I2C1 interface. For example, the baseboard management controller BMC in Figure 6 can directly access the corresponding temperature detection chip (downstream device) through the I2C3 interface.

[0058] In some embodiments, the above method further includes: when the main controller determines that the interface state is a low level state, allowing the central processing unit to access at least one device through the main controller.

[0059] Specifically, after the main controller receives the interface status corresponding to the universal input and output interface output by the baseboard management controller, it determines whether the received interface status is a high level state or a low level state. When the interface status is a low level state, it means that the baseboard management controller has not pulled up the interface status of the universal input and output interface, and the output voltage value is 0V. Therefore, at this time, the main controller of the switch determines that the switch system is controlled by the central processing unit, that is, the central processing unit can access at least one downstream device.

[0060] In this embodiment, allowing the central processing unit to access at least one device through the main controller includes: sending a control instruction to the main controller through the central processing unit, selecting a target control mode according to the control instruction through the main controller, and allowing the central processing unit to access at least one device according to the target control mode through the main controller.

[0061] Specifically, after the central processing unit sends a control instruction to the main controller, the main controller selects a target control mode based on the control instruction. Different target control modes correspond to different access methods. Furthermore, the main controller controls the central processing unit's access to at least one downstream device based on the target control mode. Target control modes include a switch mode and a cache mode. In the switch mode, the main controller controls the corresponding channel interface to connect to the matching target device bus, enabling the central processing unit to access the corresponding device. In the cache mode, the main controller caches the register information corresponding to all downstream devices in a cache area. The central processing unit can read the corresponding register information from the cache area and access the corresponding target device using the register information.

[0062] In this embodiment, the main controller allows the central processing unit to access at least one device according to the target control mode, including: when the target control mode is the switch mode, the central processing unit sends a channel selection instruction to the main controller, the main controller determines the corresponding target interface channel according to the channel selection instruction, and the main controller connects the channel interface corresponding to the target interface channel to the matching target device bus. When the connection is successful, the central processing unit accesses the target device corresponding to the target device bus.

[0063] For example, as shown in FIG7 , FIG7 is a schematic diagram of the structure of the central processing unit accessing the device in the switch in one or more embodiments. The switch in FIG7 includes a baseboard management controller (BMC) and a central processing unit (CPU), and the main controller is an embedded controller (MCU). The embedded controller determines that the central processing unit accesses at least one downstream device, such as a board EEPROM, a voltage detection chip, a temperature detection chip, and other I2C devices, based on the interface status of the general input and output interface output by the baseboard management controller being in a low level state. As can be seen from FIG7 , when the target control mode is a switch mode, the embedded controller sets a switch between the I2C interface of the central processing unit and the downstream device. For example, the I2 interface of the central processing unit is respectively connected to the downstream board EEPROM, the voltage detection chip, the temperature detection chip, and other I2C devices. The central processing unit can send a channel selection instruction to the embedded controller via the I2C interface. The embedded controller analyzes the received channel selection instruction to obtain the target interface channel, connects the channel interface corresponding to the target interface channel to the matching target device bus, that is, closes the switch corresponding to the target interface. When the connection is successful, the central processing unit can access the corresponding target device via the target device bus. For example, as shown in FIG7 , the central processor sends a channel selection instruction to the embedded controller, and the embedded controller closes the switch of the third channel. The central processor can access the downstream temperature detection chip through the closed channel.

[0064] In this embodiment, the main controller allows the central processing unit to access at least one device according to the target control mode, including: when the target control mode is the cache mode, the central processing unit sends a device read instruction to the main controller, and the main controller reads the register information corresponding to the matching target device from the cache area according to the device read instruction, the cache area includes the register information corresponding to each device, and the central processing unit accesses the target device according to the register information.

[0065] For example, as shown in FIG8 , FIG8 is a schematic diagram illustrating a structure of a central processing unit accessing a device in a switch in one or more embodiments. The switch in FIG8 includes a baseboard management controller (BMC) and a central processing unit (CPU). The main controller is an embedded controller (MCU). The embedded controller determines that the central processing unit accesses at least one downstream device, such as a board EEPROM, a voltage detection chip, a temperature detection chip, and other I2C devices, based on the low-level interface status of the general input / output interface output by the baseboard management controller. As can be seen from FIG8 , when the target control mode is the cache mode, the embedded controller stores the register information of all downstream devices in advance in the buffer. The downstream devices include board EEPROM, voltage detection chip, temperature detection chip, and other I2C devices. The central processing unit can send a device read instruction to the embedded controller via the I2C interface. After receiving the device read instruction, the embedded controller parses the information carried in the device read instruction and reads the register information corresponding to the matching target device from the cache. The central processing unit can access the corresponding target device through the read register information.

[0066] In some embodiments, when the switch does not include a baseboard management controller, that is, when the baseboard management controller in the switch is not enabled, the method further includes: receiving, through the main controller, an interface status corresponding to the general input and output interface as a low level state, and allowing the central processing unit to access at least one device according to the low level state through the main controller.

[0067] Among them, the baseboard management controller in the switch can be set according to actual needs and actual application scenarios. The baseboard management controller may not be included in the switch. In this case, the switch is controlled by the central processing unit, and the interface state corresponding to the general input and output interface is also controlled by the pull-up resistor. Therefore, the interface state corresponding to the general input and output interface received by the main controller is a low-level state. Further, the main controller allows the central processing unit to access at least one downstream device based on the low-level state.

[0068] In this embodiment, the main controller allows the central processing unit to access at least one device according to the low-level state, including: sending a control instruction to the main controller by the central processing unit, selecting a target control mode according to the control instruction by the main controller, and allowing the central processing unit to access at least one device according to the target control mode by the main controller.

[0069] Specifically, after the central processing unit sends a control instruction to the main controller, the main controller selects a target control mode based on the control instruction. Different target control modes correspond to different access methods. Furthermore, the main controller controls the central processing unit's access to at least one downstream device based on the target control mode. Target control modes include a switch mode and a cache mode. In the switch mode, the main controller controls the corresponding channel interface to connect to the matching target device bus, enabling the central processing unit to access the corresponding device. In the cache mode, the main controller caches the register information corresponding to all downstream devices in a cache area. The central processing unit can read the corresponding register information from the cache area and access the corresponding target device using the register information.

[0070] In this embodiment, the main controller allows the central processing unit to access at least one device according to the target control mode, including: when the target control mode is the switch mode, the central processing unit sends a channel selection instruction to the main controller, the main controller determines the corresponding target interface channel according to the channel selection instruction, and the main controller connects the channel interface corresponding to the target interface channel to the matching target device bus. When the connection is successful, the central processing unit accesses the target device corresponding to the target device bus.

[0071] For example, as shown in FIG7 , FIG7 is a schematic diagram of the structure of the central processing unit accessing the device in the switch in one or more embodiments. The switch in FIG7 includes a baseboard management controller (BMC) and a central processing unit (CPU), and the main controller is an embedded controller (MCU). The embedded controller determines that the central processing unit accesses at least one downstream device, such as a board EEPROM, a voltage detection chip, a temperature detection chip, and other I2C devices, based on the low-level interface state of the general input and output interface output by the baseboard management controller. As can be seen from FIG7 , when the target control mode is the switch mode, the embedded controller is provided with a switch between the I2C interface of the central processing unit and the downstream device. For example, the I2C interface of the central processing unit is provided with corresponding switches for the downstream board EEPROM, the voltage detection chip, the temperature detection chip, and other I2C devices. The central processing unit can send a channel selection instruction to the embedded controller via the I2C interface. The embedded controller analyzes the received channel selection instruction to obtain the target interface channel, connects the channel interface corresponding to the target interface channel to the matching target device bus, that is, closes the switch corresponding to the target interface. When the connection is successful, the central processing unit can access the corresponding target device via the target device bus. For example, as shown in FIG7 , the central processor sends a channel selection instruction to the embedded controller, and the embedded controller closes the switch of the third channel. The central processor can access the downstream temperature detection chip through the closed channel.

[0072] In this embodiment, the main controller allows the central processing unit to access at least one device according to the target control mode, including: when the target control mode is the cache mode, the central processing unit sends a device read instruction to the main controller, and the main controller reads the register information corresponding to the matching target device from the cache area according to the device read instruction, the cache area includes the register information corresponding to each device, and the central processing unit accesses the target device according to the register information.

[0073] For example, as shown in FIG8 , FIG8 is a schematic diagram illustrating a structure of a central processing unit accessing a device in a switch in one or more embodiments. The switch in FIG8 includes a baseboard management controller (BMC) and a central processing unit (CPU). The main controller is an embedded controller (MCU). The embedded controller determines that the central processing unit accesses at least one downstream device, such as a board EEPROM, a voltage detection chip, a temperature detection chip, and other I2C devices, based on the low-level interface status of the general input / output interface output by the baseboard management controller. As can be seen from FIG8 , when the target control mode is the cache mode, the embedded controller stores the register information of all downstream devices in advance in the buffer. The downstream devices include board EEPROM, voltage detection chip, temperature detection chip, and other I2C devices. The central processing unit can send a device read instruction to the embedded controller via the I2C interface. After receiving the device read instruction, the embedded controller parses the information carried in the device read instruction and reads the register information corresponding to the matching target device from the cache. The central processing unit can access the corresponding target device through the read register information.

[0074] In some embodiments, the device is an I2C device and / or a device compatible with the I2C protocol.

[0075] I2C, or Inter-Integrated Circuit, is a commonly used serial communication protocol. Devices can be I2C devices and / or I2C-compatible devices. I2C-compatible devices can include devices using the SMBus protocol or the PMBus protocol. SMBus is a two-wire bus used in applications requiring critical parameter monitoring, most commonly in computer motherboards and embedded systems. PMBus is an open standard power management protocol for digital management of power supplies with power control and management devices. It has commands and structures that support power management requirements. I2C, SMBus, and PMBus are compatible, so devices can include devices using the SMBus protocol or the PMBus protocol.

[0076] In some embodiments, the I2C device is at least one of a board EEPROM, a voltage detection chip, a temperature detection chip, and other I2C device units.

[0077] Among them, the board EEPROM (Electrically Erasable Programmable Read Only Memory) refers to an electrically erasable programmable read-only memory, a storage chip that does not lose data after power failure. The EEPROM can erase existing information on the switch and reprogram it.

[0078] In some embodiments, the main controller is an embedded controller, the central processing unit is connected to the embedded controller, the central processing unit includes an SMBus bus interface and a first general input / output interface, and the embedded controller includes an I2C bus interface and a second general input / output interface, wherein the SMBus bus interface of the central processing unit communicates data with the I2C bus interface of the embedded controller, and the first general input / output interface of the central processing unit communicates data with the second general input / output interface of the embedded controller.

[0079] In this embodiment, the baseboard management controller is connected to the embedded controller. The baseboard management controller includes multiple I2C bus interfaces and a third general input and output interface. The third general input and output interface of the baseboard management controller is respectively connected to the first general input and output interface and the second general input and output interface. Each I2C bus interface of the baseboard management controller is connected to the second general input and output interface of the embedded controller.

[0080] The switch includes a central processing unit, a baseboard management controller, a main controller and at least one device. For example, as shown in Figure 2, it may include a central processing unit, a baseboard management controller unit, an embedded controller unit, a board EEPROM, a voltage detection chip, a temperature detection chip, and other I2C device units.

[0081] Among them, the central processing unit can be any SOC controller with an SMBus interface, such as Intel Broadwell D1527 / D1627, Feiteng FT2000 / D2000, etc., which is mainly used for the management and control functions of the switch system. The central processing unit also includes a first general input and output interface, which obtains control signals from the baseboard management controller through the first general input and output interface, and sends control instructions and I2C read and write instructions through the SMBus interface.

[0082] The baseboard management controller can be any type of baseboard management controller, such as Aspeed AST2520. The baseboard management controller realizes I2C master controller switching through the third general input and output interface control signal, and realizes the issuance of control instructions and read and write instructions through each I2C interface.

[0083] The embedded controller can be any embedded control chip, such as the ST Microelectronics STM32F103RBT6. Its internal code is divided into a control logic module and an I2C logic module. The control logic module is used to implement I2C master controller switching based on the interface status of the corresponding general-purpose input and output interface. The I2C logic module is used to implement I2C bus control based on the master controller type and control instructions. The embedded controller includes an I2C bus interface and a second general-purpose input and output interface.

[0084] The board EEPROM can be any I2C interface EEPROM storage chip, which is mainly used to store switch system and board information, including but not limited to switch model, manufacturer information, serial number, etc.

[0085] Voltage detection chips include, but are not limited to, DC / DC converter chips with an I2C interface and voltage and current ADC detection chips, primarily used to monitor the voltage amplitudes of the switch's power supply domains in real time. Temperature detection chips can be any model, such as the Shensi Ling CT7432 / CT7112, primarily used to monitor the switch's internal temperature in real time. Furthermore, other I2C device units refer to other devices / components within the switch that have an I2C interface (including SMBus and PMBus interfaces), including but not limited to CPLD chips, RTC chips, and PSU modules.

[0086] In some embodiments, the above method can also be applied to a server.

[0087] That is to say, the above method can be applied not only to switches but also to servers.

[0088] In an embodiment of a specific switch application scenario, as shown in FIG9 , FIG9 shows a schematic diagram of a principle of data access in one or more embodiments, including the following steps:

[0089] (1) The switch system starts and goes to step (2);

[0090] (2) If the system does not have a BMC, go to step (3); otherwise, go to step (10);

[0091] (3) When the CPU and BMC receive the GPIO status as low, the MCU determines that the I2C master controller in the system is the CPU based on the GPIO status being low, and proceeds to step (4);

[0092] (4) The CPU sends control instructions to the MCU I2C interface through the SMBus bus, selects the CPU-side I2C bus control mode, and proceeds to step (5);

[0093] (5) If the control mode selected by the control instruction issued by the CPU is the switch mode by default, proceed to step (6); if the selected control mode is the cache mode, proceed to step (8);

[0094] (6) The CPU sends a channel selection instruction to the MCU I2C interface through the SMBus bus. The MCU connects the upstream SMBus bus to the selected downstream I2C device bus according to the channel selected by the CPU. The CPU can directly access the register information of the I2C device and enter step (7).

[0095] (7) Whether to continue accessing, if so, return to step (4); otherwise, go to step (16);

[0096] (8) The CPU sends a device read instruction through the SMBus interface, and the MCU reads the corresponding device I2C register information into the buffer and enters step (9);

[0097] (9) The CPU reads the corresponding device I2C register information from the MCU buffer and returns to step (7);

[0098] (10) BMC controls the GPIO signal state. If the BMC output GPIO is low, go to step (3); if the BMC controls its output GPIO to be high, go to step (11);

[0099] (11) When the CPU and BMC receive the GPIO status as high, the MCU determines that the I2C master controller in the system is the BMC based on the GPIO status being high, and proceeds to step (12);

[0100] (12) Each channel of the BMC sends the channel selection instruction to the MCU through the I2C interface, and enters step (13);

[0101] (13) The MCU connects the BMC I2C interface to the corresponding downstream I2C device bus according to the channel selection instructions of each I2C interface of the BMC, and enters step (14);

[0102] (14) Each I2C interface of the BMC directly accesses the downstream I2C device information and proceeds to step (15);

[0103] (15) Whether to continue accessing, if so, return to step (10); otherwise, go to step (16);

[0104] (16)End.

[0105] It should be understood that, although the various steps in the above flow chart are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the above flow chart may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these sub-steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0106] In some embodiments, as shown in FIG10 , a data access device 1000 is provided. The device is applied to a switch. The switch includes a central processing unit (CPU), a baseboard management controller (BMC), a main controller (MC), and at least one device. The CPU and the BMC are respectively connected to the main controller, and the main controller is connected to the at least one device. The device includes a receiving module 1002 and a control module 1004.

[0107] The receiving module 1002 is configured to receive the interface status corresponding to the target interface through the main controller.

[0108] The control module 1004 is configured to allow the central processing unit or the baseboard management controller to access at least one device according to the interface status through the main controller.

[0109] In some embodiments, the receiving module 1002 controls the interface status corresponding to the universal input / output interface through the baseboard management controller, and receives the interface status corresponding to the universal input / output interface output by the baseboard management controller through the main controller.

[0110] In some embodiments, the control module 1004 determines whether the interface state is high or low through the main controller, and allows the baseboard management controller to access at least one device through the main controller when the interface state is high.

[0111] In some embodiments, the control module 1004 sends a channel selection instruction to the main controller through the baseboard management controller, and the main controller connects the target interface channel corresponding to the baseboard management controller to the matching target device bus according to the channel selection instruction. When the connection is successful, the target device corresponding to the target device bus is accessed through the baseboard management controller.

[0112] In some embodiments, the control module 1004 sends the corresponding channel selection instruction to the main controller via the corresponding I2C interface through the multiple interface channels of the baseboard management controller.

[0113] In some embodiments, the control module 1004 connects each I2C interface to a matching target device bus according to each channel selection instruction through the main controller.

[0114] In some embodiments, when the main controller determines that the interface status is a low level state, the control module 1004 allows the central processor to access at least one device through the main controller.

[0115] In some embodiments, the control module 1004 sends a control instruction to the main controller via the central processor, the main controller selects a target control mode according to the control instruction, and the main controller allows the central processor to access at least one device according to the target control mode.

[0116] In some embodiments, when the target control mode is the switch mode, the control module 1004 sends a channel selection instruction to the main controller through the central processing unit, and the main controller determines the corresponding target interface channel according to the channel selection instruction, and connects the channel interface corresponding to the target interface channel to the matching target device bus through the main controller. When the connection is successful, the target device corresponding to the target device bus is accessed through the central processing unit.

[0117] In some embodiments, when the target control mode is the cache mode, the control module 1004 sends a device read instruction to the main controller through the central processing unit, and the main controller reads the register information corresponding to the matching target device from the cache area according to the device read instruction. The cache area includes the register information corresponding to each device, and the target device is accessed through the central processing unit according to the register information.

[0118] In some embodiments, when the baseboard management controller in the switch is not enabled, the data access device 1000 receives a low-level interface state corresponding to the general input and output interface through the main controller, and allows the central processor to access at least one device through the main controller according to the low-level state.

[0119] In some embodiments, when the baseboard management controller in the switch is not enabled, the data access device 1000 sends a control instruction to the main controller through the central processor, the main controller selects a target control mode according to the control instruction, and the main controller allows the central processor to access at least one device according to the target control mode.

[0120] In some embodiments, when the baseboard management controller in the switch is not enabled, the data access device 1000 sends a channel selection instruction to the main controller through the central processing unit when the target control mode is the switch mode, and the main controller determines the corresponding target interface channel according to the channel selection instruction, and connects the channel interface corresponding to the target interface channel to the matching target device bus through the main controller. When the connection is successful, the target device corresponding to the target device bus is accessed through the central processing unit.

[0121] In some embodiments, when the baseboard management controller in the switch is not enabled, the data access device 1000 sends a device read instruction to the main controller through the central processing unit when the target control mode is the cache mode, and the main controller reads the register information corresponding to the matching target device from the cache area according to the device read instruction. The cache area includes the register information corresponding to each device, and the target device is accessed through the central processing unit according to the register information.

[0122] In some embodiments, the device is at least one of a board EEPROM, a voltage detection chip, a temperature detection chip, and other I2C device units.

[0123] In some embodiments, the main controller is an embedded controller, the central processing unit is connected to the embedded controller, the central processing unit includes an SMBus bus interface and a first general input / output interface, and the embedded controller includes an I2C bus interface and a second general input / output interface, wherein the SMBus bus interface of the central processing unit communicates data with the I2C bus interface of the embedded controller, and the first general input / output interface of the central processing unit communicates data with the second general input / output interface of the embedded controller.

[0124] In some embodiments, the baseboard management controller is connected to the embedded controller, and the baseboard management controller includes multiple I2C bus interfaces and a third general input and output interface. The third general input and output interface of the baseboard management controller is respectively connected to the first general input and output interface and the second general input and output interface, and each I2C bus interface of the baseboard management controller is connected to the second general input and output interface of the embedded controller.

[0125] In some embodiments, the data access device 1000 may also be applied to a server.

[0126] The specific definition of the data access device can be found in the definition of the data access method above and will not be repeated here. Each module in the aforementioned data access device may be implemented in whole or in part via software, hardware, or a combination thereof. Each module may be embedded in or independent of the processor in the switch in hardware form, or may be stored in memory in the switch in software form, allowing the processor to call and execute the corresponding operations of each module.

[0127] In some embodiments, a switch is provided, which may be a server, and its internal structure diagram may be as shown in Figure 11. The switch includes a processor, a memory, a network interface, and a database connected via a system bus. The processor of the switch is used to provide computing and control capabilities. The memory of the switch includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the switch is used to store interface status. The network interface of the switch is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a data access method is implemented.

[0128] Those skilled in the art will understand that the structure shown in Figure 11 is merely a block diagram of a partial structure related to the solution of the present application, and does not constitute a limitation on the switch to which the solution of the present application is applied. A specific switch may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0129] In some embodiments, a switch is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the following steps are implemented: receiving an interface status corresponding to a target interface through a main controller, and allowing a central processing unit or a baseboard management controller to access at least one device according to the interface status through the main controller.

[0130] In some embodiments, when a processor executes a computer program, the data access method of any one or more of the above embodiments is implemented.

[0131] In some embodiments, a non-volatile computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: receiving an interface status corresponding to a target interface through a main controller, and allowing a central processing unit or a baseboard management controller to access at least one device according to the interface status through the main controller.

[0132] In some embodiments, when a processor executes a computer program, the data access method of any one or more of the above embodiments is implemented.

[0133] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0134] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0135] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A data access method, the method is applied to a switch, the switch comprises a central processing unit, a baseboard management controller, a main controller and at least one device, the central processing unit and the baseboard management controller are respectively connected to the main controller, the main controller is connected to the at least one device, wherein: The method comprises: receiving, by the main controller, an interface status corresponding to the target interface; and The main controller allows the central processing unit or the baseboard management controller to access the at least one device according to the interface status.

2. The method according to claim 1, characterized in that The receiving, by the main controller, an interface status corresponding to the target interface comprises: Controlling the interface state corresponding to the general input and output interface by the baseboard management controller; and The main controller receives the interface status corresponding to the general input / output interface output by the baseboard management controller.

3. The method according to claim 2, characterized in that The allowing the central processing unit or the baseboard management controller to access the at least one device according to the interface state through the main controller includes: Determining, by the main controller, whether the interface state is a high level state or a low level state; and In response to the main controller determining that the interface state is a high level state, the baseboard management controller is allowed to access the at least one device through the main controller.

4. The method according to claim 3, characterized in that The allowing the baseboard management controller to access the at least one device through the main controller includes: Sending a channel selection instruction to the main controller through the baseboard management controller; Connecting the target interface channel corresponding to the baseboard management controller to a matching target device bus through the main controller according to the channel selection instruction; and In response to successful connection, the target device corresponding to the target device bus is accessed through the baseboard management controller.

5. The method according to claim 4, characterized in that The sending of the channel selection instruction to the main controller through the baseboard management controller includes: The corresponding channel selection instruction is sent to the main controller through the corresponding I2C interface via the multiple interface channels of the baseboard management controller.

6. The method according to claim 5, characterized in that The method of connecting the target interface channel corresponding to the baseboard management controller to a matching target device bus through the main controller according to the channel selection instruction includes: The main controller connects each of the I2C interfaces to a matching target device bus according to each of the channel selection instructions.

7. The method according to claim 3, characterized in that The method further comprises: In response to the main controller determining that the interface state is a low level state, the main controller allows the central processor to access the at least one device.

8. The method according to claim 7, characterized in that The step of allowing the central processor to access the at least one device through the main controller comprises: Sending control instructions to the main controller via the central processing unit; Selecting a target control mode according to the control instruction by the main controller; and The central processor is allowed to access the at least one device according to the target control mode through the main controller.

9. The method according to claim 8, characterized in that The step of allowing the central processor to access the at least one device according to the target control mode by the main controller includes: In response to the target control mode being the switch mode, sending a channel selection instruction to the main controller through the central processor; Determining the corresponding target interface channel according to the channel selection instruction by the main controller; Connecting the channel interface corresponding to the target interface channel to a matching target device bus through the main controller; and In response to successful connection, the target device corresponding to the target device bus is accessed through the central processing unit.

10. The method according to claim 8, characterized in that The step of allowing the central processor to access the at least one device according to the target control mode by the main controller includes: In response to the target control mode being a cache mode, sending a device read instruction to the main controller through the central processor; Reading register information corresponding to a matching target device from a buffer area according to the device read instruction by the main controller, wherein the buffer area includes register information corresponding to each of the devices; and The target device is accessed by the central processing unit according to the register information.

11. The method according to claim 1, characterized in that: In response to the baseboard management controller in the switch being not enabled, the method further includes: The interface state corresponding to the general input and output interface received by the main controller is a low level state; and The main controller allows the central processing unit to access the at least one device according to the low level state.

12. The method according to claim 11, characterized in that The step of allowing the central processor to access the at least one device according to the low level state by the main controller comprises: Sending control instructions to the main controller via the central processing unit; Selecting a target control mode according to the control instruction by the main controller; and The central processor is allowed to access the at least one device according to the target control mode through the main controller.

13. The method according to claim 12, characterized in that The step of allowing the central processor to access the at least one device according to the target control mode by the main controller includes: In response to the target control mode being the switch mode, sending a channel selection instruction to the main controller through the central processor; Determining the corresponding target interface channel according to the channel selection instruction by the main controller; Connecting the channel interface corresponding to the target interface channel to a matching target device bus through the main controller; and In response to successful connection, the target device corresponding to the target device bus is accessed through the central processing unit.

14. The method according to claim 12, characterized in that The step of allowing the central processor to access the at least one device according to the target control mode by the main controller includes: In response to the target control mode being a cache mode, sending a device read instruction to the main controller through the central processor; Reading register information corresponding to a matching target device from a buffer area according to the device read instruction by the main controller, wherein the buffer area includes register information corresponding to each of the devices; and The target device is accessed by the central processing unit according to the register information.

15. The method according to claim 1, characterized in that The device is an I2C device and / or a device compatible with the I2C protocol.

16. The method according to claim 15, characterized in that The I2C device is at least one of a board EEPROM, a voltage detection chip, a temperature detection chip, and other I2C device units.

17. The method according to claim 1, characterized in that The main controller is an embedded controller, the central processing unit is connected to the embedded controller, the central processing unit includes an SMBus bus interface and a first general input / output interface, the embedded controller includes an I2C bus interface and a second general input / output interface, wherein the SMBus bus interface of the central processing unit communicates data with the I2C bus interface of the embedded controller, and the first general input / output interface of the central processing unit communicates data with the second general input / output interface of the embedded controller.

18. The method according to claim 17, characterized in that The baseboard management controller is connected to the embedded controller, and the baseboard management controller includes multiple I2C bus interfaces and a third general input and output interface. The third general input and output interface of the baseboard management controller is respectively connected to the first general input and output interface and the second general input and output interface, and each of the I2C bus interfaces of the baseboard management controller is connected to the second general input and output interface of the embedded controller.

19. The method according to claim 1, characterized in that The method is also applied to the server.

20. A switch, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method according to any one of claims 1 to 19 when executing the computer program.

21. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 19 are implemented.

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