Display panel and display apparatus

Abstract

Provided in at least one embodiment of the present invention are a display panel and a display apparatus. The display panel comprises a base substrate; and a pixel circuit, which is provided on the base substrate, the pixel circuit comprising an induction transistor, a drive transistor, a first gate line and a second gate line, wherein a first source-drain electrode of the induction transistor is electrically connected to a first source-drain electrode of the drive transistor by means of a first connecting electrode; the first gate line and the second gate line extend in a first direction; spacing portions are provided between the first connecting electrode and the first gate line and between the first connecting electrode and the second gate line in a second direction that intersects with the first direction; the first connecting electrode, the first gate line, the second gate line and the spacing portions are provided on the same layer; and spacing portions, which are located on a third metal layer, are respectively provided between the induction transistor and the first gate line and the second gate line which are located on the two sides of the induction transistor in the second direction, and the spacing portions can shield the coupling between the first source-drain electrode of the induction transistor and the first gate line or the second gate line.

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202310699370.8 filed on June 14, 2023. The contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present invention relate to a display panel and a display device. Background Art

[0003] Currently, widely used display devices in the display field include thin-film transistor liquid crystal display devices (TFT-LCD) and active-matrix organic light-emitting diode (AMOLED) display devices. Active-matrix organic light-emitting diode (AMOLED) display devices have the advantages of long life, high display brightness, high contrast, and a wide color gamut.

[0004] Organic light-emitting diode (OLED) displays, which use active-matrix organic light-emitting diodes (AMOLEDs) as their light-emitting elements, are thinner and lighter than conventional liquid crystal displays (LCDs). They also feature fast response times, wide viewing angles, and low-voltage drive. Consequently, they are widely used in cellular phones, portable information terminals, televisions, and monitors. The structure of an OLED display primarily includes a cathode and an anode, with a light-emitting functional layer sandwiched between them. In an AMOLED display, each subpixel has a switching transistor and a driving transistor. Adjusting these transistors causes the light-emitting layer in the OLED display to emit light.

[0005] Summary of the Invention

[0006] At least one embodiment of the present invention provides a display panel and a display device, the display panel comprising: a pixel circuit arranged on a base substrate, the pixel circuit comprising a sensing transistor, a driving transistor, a first gate line, and a second gate line, wherein a first source-drain electrode of the sensing transistor and a first source-drain electrode of the driving transistor are electrically connected via a first connecting electrode; the first gate line and the second gate line extend in a first direction, and in a second direction intersecting the first direction, a spacer is provided between the first connecting electrode and the first gate line, and between the first connecting electrode and the second gate line, and the first connecting electrode, the first gate line, the second gate line, and the spacer are arranged on the same layer. In an embodiment of the present invention, by providing a spacer between the first connecting electrode and the first gate line, and between the first connecting electrode and the second gate line, and by providing the first connecting electrode, the first gate line, the second gate line, and the spacer on the same layer, a voltage change on the first connecting electrode caused by a voltage jump in the first gate line or the second gate line can be reduced, thereby reducing damage to the light-emitting diode, thereby ensuring the service life of the light-emitting diode.

[0007] At least one embodiment of the present invention provides a display panel, comprising: a base substrate; a pixel circuit arranged on the base substrate, the pixel circuit comprising a sensing transistor, a driving transistor, a first gate line, and a second gate line, wherein a first source-drain electrode of the sensing transistor and a first source-drain electrode of the driving transistor are electrically connected via a first connecting electrode; the first gate line and the second gate line extend in a first direction, and in a second direction intersecting the first direction, spacers are provided between the first connecting electrode and the first gate line, and between the first connecting electrode and the second gate line, and the first connecting electrode, the first gate line, the second gate line, and the spacers are provided on the same layer.

[0008] For example, the display panel provided by at least one embodiment of the present invention further includes a switching transistor and a storage capacitor arranged on the base substrate, wherein the first source and drain electrodes of the switching transistor and the gate of the driving transistor are connected through a second connecting electrode, the first plate of the storage capacitor is connected to the second connecting electrode, and the second plate of the storage capacitor is connected to the first connecting electrode.

[0009] For example, the display panel provided by at least one embodiment of the present invention further includes a first metal layer, an active layer, a second metal layer and a third metal layer stacked in sequence on the base substrate, wherein the first metal layer includes an initialization signal line extending in the second direction, a power supply voltage signal line extending at least partially in the second direction, the first electrode and a data line; the active layer includes a channel region of the sensing transistor, a channel region of the driving transistor and a channel region of the switching transistor; the second metal layer includes a gate of the sensing transistor, a gate of the driving transistor, a gate of the switching transistor and the second electrode; the third metal layer includes the first connecting electrode, the spacer, the second gate line extending in the first direction and the first gate line.

[0010] For example, in the display panel provided by at least one embodiment of the present invention, the gate of the sensing transistor extends in the second direction to be electrically connected to the first gate line, the gate of the switching transistor extends in a direction opposite to the second direction to be electrically connected to the second gate line, and the first gate line connected to the gate of the sensing transistor and the second gate line connected to the gate of the switching transistor are located on different sides of any of the spacers in the second direction.

[0011] For example, in the display panel provided by at least one embodiment of the present invention, the third metal layer also includes a first connecting structure, a second connecting structure and a third connecting structure extending in the second direction, wherein the orthographic projection of the first connecting structure on the base substrate is located within the orthographic projection of the initialization signal line on the base substrate, the orthographic projection of the second connecting structure on the base substrate is located within the orthographic projection of the first electrode on the base substrate, and the orthographic projection of the third connecting structure on the base substrate is located within the orthographic projection of the data line on the base substrate.

[0012] For example, the display panel provided by at least one embodiment of the present invention further includes a buffer layer arranged on the side of the first metal layer away from the base substrate, a gate insulation layer arranged between the active layer and the second metal layer, an interlayer insulation layer arranged between the second metal layer and the third metal layer, and a passivation layer and a planarization layer arranged on the side of the third metal layer away from the base substrate.

[0013] For example, in the display panel provided in at least one embodiment of the present invention, a first via structure and a third via structure are provided in the interlayer insulating layer, the third metal layer is electrically connected to the active layer through the first via structure, and the third metal layer is electrically connected to the second metal layer through the third via structure; a second via structure is passed through the interlayer insulating layer and the buffer layer, and the third metal layer is electrically connected to the first metal layer through the second via structure.

[0014] For example, in the display panel provided by at least one embodiment of the present invention, the first connection structure is electrically connected to the initialization signal line through the second via structure, and is electrically connected to the second source-drain electrode of the sensing transistor through the first via structure; the second connection structure is electrically connected to the first source-drain electrode of the switching transistor through the first via structure, and is electrically connected to the second electrode plate through the third via structure; the third connection structure is electrically connected to the data line through the second via structure, and is electrically connected to the second source-drain electrode of the switching transistor through the first via structure.

[0015] For example, in the display panel provided in at least one embodiment of the present invention, at least a portion of the third metal layer has an overlapping area with the first metal layer and the second metal layer to form the storage capacitor between the first metal layer and the second metal layer, and to form a capacitor structure between the second metal layer and the third metal layer.

[0016] For example, in the display panel provided by at least one embodiment of the present invention, the orthographic projection of the first source-drain electrode of the sensing transistor on the base substrate overlaps with the orthographic projection of the power voltage signal line on the base substrate.

[0017] For example, in the display panel provided in at least one embodiment of the present invention, the power supply voltage signal line includes a first power supply voltage signal line extending in the second direction, the first power supply voltage signal line includes a first part, a second part and a third part extending in the second direction and connected in sequence, the first part and the third part have the same width in the first direction, the second part has a width in the first direction that is smaller than the first part in the first direction, and one end of the second part in the second direction is connected to an edge of the first part close to the third part and away from the initialization signal line, and the other end of the second part in the second direction is connected to an edge of the third part close to the first part and away from the initialization signal line.

[0018] For example, in the display panel provided by at least one embodiment of the present invention, an orthographic projection of the first source-drain electrode of the sensing transistor on the base substrate is spaced apart from an orthographic projection of the second portion of the power voltage signal line on the base substrate.

[0019] For example, in the display panel provided in at least one embodiment of the present invention, the first electrode plate includes a first electrode plate sub-block and a second electrode plate sub-block connected to each other in the first direction, the second metal layer includes a first extension portion and a second extension portion extending from a portion of the second electrode plate corresponding to the second electrode plate sub-block in the second direction, and two second connecting electrodes are respectively connected to the first extension portion and the second extension portion.

[0020] For example, the display panel provided by at least one embodiment of the present invention further includes an organic light emitting diode, wherein: A st is the area of ​​the storage capacitor, d gc is the minimum distance between the first gate line and the storage capacitor, L c is the length of the side of the first plate sub-block adjacent to the first gate line, W g is the width of the first gate line in the second direction, THK ILD is the thickness of the interlayer insulating layer corresponding to the storage capacitor.

[0021] For example, in a display panel provided by at least one embodiment of the present invention, V gON is the turn-on voltage of the second gate line, V gOFF is the off voltage of the second gate line, V oled is the voltage across the organic light emitting diode, and γ is an optical constant.

[0022] For example, in the display panel provided by at least one embodiment of the present invention, the storage capacitor is a three-layer structure formed by the first metal layer, the second metal layer and the third metal layer. THK BUF is the thickness of the buffer layer between the first metal layer and the second metal layer in the storage capacitor.

[0023] For example, in a display panel provided by at least one embodiment of the present invention,

[0024] For example, in a display panel provided by at least one embodiment of the present invention, W DD is the length of the spacer between the first gate line and the first connecting electrode in the second direction, d gdis the minimum distance between the first gate line and the spacer between the first gate line and the first connecting electrode, d sd is the minimum distance between the first connecting electrode and the spacer between the first gate line and the first connecting electrode.

[0025] For example, in a display panel provided by at least one embodiment of the present invention, L c is the length of the side of the first plate sub-block adjacent to the first gate line, L p is the sum of the lengths of the first plate sub-block and the second plate sub-block in the first direction, R l is the ratio of the length of the side of the first plate sub-block adjacent to the first gate line to the sum of the lengths of the first plate sub-block and the second plate sub-block in the first direction.

[0026] For example, in a display panel provided by at least one embodiment of the present invention, W c is the width of the storage capacitor in the first direction, and Pitch is the width of a sub-pixel in the first direction.

[0027] For example, the display panel provided by at least one embodiment of the present invention further includes a first metal layer, an active layer, and a second metal layer stacked in sequence on the base substrate, wherein the first metal layer includes an initialization signal line extending in the second direction, a power supply voltage signal line extending at least partially in the second direction, the first electrode and a data line; the active layer includes a channel region of the sensing transistor, a channel region of the driving transistor, and a channel region of the switching transistor; the second metal layer includes a gate of the sensing transistor, a gate of the driving transistor, a gate of the switching transistor, the second electrode, the first connecting electrode, the spacer, the second gate line extending in the first direction, and the first gate line.

[0028] For example, in the display panel provided by at least one embodiment of the present invention, the gate of the switching transistor is electrically connected to the second gate line, the gate of the sensing transistor is electrically connected to the first gate line, and the second gate line connected to the gate of the switching transistor and the first gate line connected to the gate of the sensing transistor are located on different sides of the first electrode plate in the second direction, and in the second direction, the second connecting electrode is between the first connecting electrode and the second gate line connected to the gate of the switching transistor.

[0029] For example, the display panel provided by at least one embodiment of the present invention further includes a switching transistor disposed on the base substrate, wherein the first source-drain electrode of the switching transistor and the gate of the driving transistor are connected via a second connecting electrode.

[0030] For example, the display panel provided by at least one embodiment of the present invention further includes a first metal layer, an active layer, a second metal layer and a third metal layer stacked in sequence on the base substrate, wherein the first metal layer includes an initialization signal line, a power supply voltage signal line and a data line extending in the second direction, and a light shielding portion; the active layer includes a channel region of the sensing transistor, a channel region of the driving transistor and a channel region of the switching transistor; the second metal layer includes a gate of the sensing transistor, a gate of the driving transistor and a gate of the switching transistor; the third metal layer includes the first connecting electrode, the spacer, the second gate line extending in the first direction and the first gate line.

[0031] For example, in the display panel provided by at least one embodiment of the present invention, the third metal layer also includes a first connecting structure and a second connecting structure extending in the second direction, the orthographic projection of the first connecting structure on the base substrate is located within the orthographic projection of the initialization signal line on the base substrate, and the orthographic projection of the second connecting structure on the base substrate is located within the orthographic projection of the data line on the base substrate.

[0032] For example, the display panel provided by at least one embodiment of the present invention further includes a buffer layer arranged on the side of the first metal layer away from the base substrate, a gate insulation layer arranged between the active layer and the second metal layer, an interlayer insulation layer arranged between the second metal layer and the third metal layer, and a passivation layer and a planarization layer arranged on the side of the third metal layer away from the base substrate.

[0033] For example, in the display panel provided in at least one embodiment of the present invention, a first via structure is provided in the interlayer insulating layer, and the third metal layer is electrically connected to the active layer through the first via structure; a second via structure is passed through the interlayer insulating layer and the buffer layer, and the third metal layer is electrically connected to the power supply voltage signal line through the second via structure.

[0034] For example, in the display panel provided by at least one embodiment of the present invention, a storage capacitor is formed between the third metal layer and the second metal layer.

[0035] For example, the display panel provided by at least one embodiment of the present invention further includes a switching transistor and a storage capacitor arranged on the base substrate, wherein the first source-drain electrode of the switching transistor and the first plate of the storage capacitor are connected via a second connecting electrode.

[0036] For example, the display panel provided by at least one embodiment of the present invention further includes a first metal layer, an active layer, and a second metal layer stacked in sequence on the base substrate, wherein the first metal layer includes an initialization signal line, a power supply voltage signal line, and a data line extending in the second direction; the active layer includes a channel region of the sensing transistor, a channel region of the driving transistor, a channel region of the switching transistor, and the first electrode; the second metal layer includes a gate of the sensing transistor, a gate of the driving transistor, and a gate of the switching transistor, the first connecting electrode, the spacer, the second electrode of the storage capacitor, the second gate line extending in the first direction, and the first gate line.

[0037] For example, in the display panel provided by at least one embodiment of the present invention, the edge of the first electrode of the storage capacitor on the side close to the second gate line extends in the first direction to just above the power voltage signal line.

[0038] For example, in the display panel provided by at least one embodiment of the present invention, the second metal layer further includes a first connection structure extending in the second direction, and the orthographic projection of the first connection structure on the base substrate is located within the orthographic projection of the initialization signal line on the base substrate.

[0039] For example, the display panel provided by at least one embodiment of the present invention further includes a buffer layer arranged on the side of the first metal layer away from the base substrate, a gate insulation layer and an interlayer insulation layer arranged between the active layer and the second metal layer, and a passivation layer and a planarization layer arranged on the side of the second metal layer away from the base substrate, wherein a first via structure is provided in the interlayer insulation layer, and the second metal layer is electrically connected to the active layer through the first via structure; a second via structure is passed through the interlayer insulation layer and the buffer layer, and the second metal layer is electrically connected to the power supply voltage signal line through the second via structure.

[0040] For example, the display panel provided by at least one embodiment of the present invention further includes a cathode voltage line, wherein the cathode voltage line includes a first cathode voltage line extending in the first direction and a second cathode voltage line extending in the second direction, and the first cathode voltage line and the second cathode voltage line intersect; the power supply voltage signal line also includes a second power supply voltage signal line extending in the first direction, and the first power supply voltage signal line and the second power supply voltage signal line intersect.

[0041] For example, in the display panel provided in at least one embodiment of the present invention, the second cathode voltage routing includes a three-layer stacked structure, and the second cathode voltage routing includes a first sublayer of the second cathode voltage routing located in the first metal layer, a second sublayer of the second cathode voltage routing located in the second metal layer, and a third sublayer of the second cathode voltage routing located in the third metal layer, the first sublayer of the second cathode voltage routing and the third sublayer of the second cathode voltage routing are electrically connected through a fourth via structure, and the second sublayer of the second cathode voltage routing and the third sublayer of the second cathode voltage routing are electrically connected through a fifth via structure.

[0042] For example, the display panel provided by at least one embodiment of the present invention further includes an organic light-emitting diode, wherein the organic light-emitting diode includes an anode, and any one of the first sublayer of the second cathode voltage routing, the second sublayer of the second cathode voltage routing, and the third sublayer of the second cathode voltage routing is electrically connected to the anode through a sixth via structure.

[0043] For example, in the display panel provided by at least one embodiment of the present invention, the third sub-layer of the first cathode voltage wiring is electrically connected to the anode through the sixth via structure.

[0044] For example, the display panel provided by at least one embodiment of the present invention further includes an encapsulation layer arranged on the organic light-emitting diode, and a quantum dot layer arranged on the encapsulation layer, wherein the quantum dot layer is configured to process light emitted from the organic light-emitting diode.

[0045] At least one embodiment of the present invention further provides a display device, which includes the display panel provided by any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0047] FIG1 is a block diagram of a display panel provided by at least one embodiment of the present invention;

[0048] FIG2 shows a schematic diagram of a 3T1C pixel circuit for the display panel;

[0049] FIG3 shows a signal timing diagram of the pixel circuit in FIG2 during the display process;

[0050] FIG4 shows a signal timing diagram of the pixel circuit in FIG2 during a detection process;

[0051] FIG5 shows another signal timing diagram of the pixel circuit in FIG2 during the detection process;

[0052] FIG6 is a layout diagram of a multi-layer structure stacked in a display panel;

[0053] FIG7 is a schematic planar structural diagram of a first metal layer included in a display panel provided by at least one embodiment of the present invention;

[0054] FIG8 is a schematic planar structural diagram of a first metal layer and an active layer stack included in a display panel provided by at least one embodiment of the present invention;

[0055] 9 is a schematic planar structure diagram of a stack of a first metal layer, an active layer, and a second metal layer included in a display panel provided by at least one embodiment of the present invention;

[0056] FIG10 is a schematic plan view of a via structure formed in the stacked structure shown in FIG9 ;

[0057] FIG11 is a schematic planar structural diagram of a third metal layer included in a display panel provided by at least one embodiment of the present invention;

[0058] FIG12 is a schematic planar structure diagram of a stack of a first metal layer, an active layer, a second metal layer, and a third metal layer, included in a display panel provided by at least one embodiment of the present invention;

[0059] FIG13 is a schematic cross-sectional view of a display panel according to at least one embodiment of the present invention;

[0060] FIG14 is a schematic plan view of a stacked structure of a first metal layer, an active layer, a second metal layer, and a third metal layer, including another display panel provided by at least one embodiment of the present invention;

[0061] FIG15 is a schematic planar structural diagram of a first metal layer included in the display panel in FIG14 ;

[0062] FIG16 is a schematic planar structural diagram of a first metal layer and an active layer stack included in the display panel of FIG14 ;

[0063] FIG17 is a schematic plan view of a stacked structure of a first metal layer, an active layer, and a second metal layer included in the display panel of FIG14 ;

[0064] FIG18 is a schematic plan view of a via structure formed in the stacked structure shown in FIG14 ;

[0065] FIG19 is a schematic planar structural diagram of a third metal layer included in the display panel in FIG14 ;

[0066] FIG20 is a schematic plan view of a stacked structure of a first metal layer, an active layer, and a second metal layer, including another display panel provided by at least one embodiment of the present invention;

[0067] FIG21 is a schematic planar structural diagram of a first metal layer and an active layer stack included in the display panel of FIG20 ;

[0068] FIG22 is a schematic planar structural diagram of a second metal layer included in the display panel in FIG20 ;

[0069] FIG23 is a schematic plan view of a stacked structure of a first metal layer, an active layer, a second metal layer, and a third metal layer, including another display panel provided by at least one embodiment of the present invention;

[0070] FIG24 is a schematic planar structural diagram of a first metal layer included in the display panel in FIG23 ;

[0071] FIG25 is a schematic planar structural diagram of a first metal layer and an active layer stack included in the display panel of FIG23;

[0072] FIG26 is a schematic plan view of a stacked structure of a first metal layer, an active layer, and a second metal layer included in the display panel of FIG23 ;

[0073] FIG27 is a schematic plan view of a via structure formed in the stacked structure shown in FIG26 ;

[0074] FIG28 is a schematic planar structural diagram of a third metal layer included in the display panel in FIG23 ;

[0075] FIG29 is a schematic diagram of the cross-sectional structure of the display panel in FIG23;

[0076] FIG30 is a schematic planar structure diagram of a stack of a first metal layer, an active layer, and a second metal layer, including another display panel provided by at least one embodiment of the present invention;

[0077] FIG31 is a schematic planar structural diagram of a first metal layer and an active layer stack included in the display panel of FIG30 ;

[0078] FIG32 is a schematic diagram of the planar structure of the second metal layer in FIG30;

[0079] FIG33 is a schematic diagram of the cross-sectional structure of the display panel in FIG30;

[0080] FIG34 is a schematic plan view of a stacked structure of a first metal layer, an active layer, a second metal layer, and a third metal layer, including another display panel provided by at least one embodiment of the present invention;

[0081] FIG35 is a schematic planar structure diagram of a stacked first metal layer and a third metal layer included in the display panel in FIG34 ;

[0082] FIG36 is a schematic plan view of a stacked structure of a first metal layer, an active layer, a second metal layer, and a third metal layer, including another display panel provided by at least one embodiment of the present invention;

[0083] FIG37 is a schematic diagram of a cross-sectional structure of the second cathode voltage trace of the display panel shown in FIG36 cut along the second direction;

[0084] FIG38 is a schematic cross-sectional view of the structure shown in FIG37 with a cathode and a pixel defining layer added;

[0085] FIG39 is a schematic diagram of a cross-sectional structure after an organic light emitting diode is added to the display panel shown in FIG36;

[0086] FIG40 is a schematic plan view of a stacked structure of a first metal layer, an active layer, a second metal layer, and a third metal layer, including another display panel provided by at least one embodiment of the present invention;

[0087] FIG41 is a schematic diagram of a cross-sectional structure of the display panel shown in FIG40; and

[0088] FIG42 is a block diagram of a display device provided by at least one embodiment of the present invention. DETAILED DESCRIPTION

[0089] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0090] Unless otherwise defined, the technical or scientific terms used in the present invention shall have the usual meanings understood by persons of ordinary skill in the field to which the present invention belongs. The words "first", "second" and similar terms used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0091] Unless otherwise defined, the features such as "parallel", "perpendicular" and "same" used in the embodiments of the present invention include the situations of "parallel", "perpendicular", "same" in a strict sense, as well as the situations of "approximately parallel", "approximately perpendicular", "approximately the same" and the like that contain a certain error. For example, the above-mentioned "approximately" may mean that the difference between the compared objects is 10% of the average value of the compared objects, or within 5%. When the number of a component or element is not specifically indicated below in the embodiments of the present invention, it means that the component or element may be one or more, or may be understood as at least one. "At least one" refers to one or more, and "multiple" refers to at least two. The "same-layer setting" in the embodiments of the present invention refers to the relationship between multiple film layers formed by the same material after the same step (for example, a one-step patterning process). The "same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same.

[0092] FIG1 is a block diagram of a display panel provided by at least one embodiment of the present invention. As shown in FIG1 , the display panel 10 includes a plurality of sub-pixels 100 arranged in an array. For example, each sub-pixel 100 includes a light-emitting element and a pixel circuit that drives the light-emitting element to emit light. For example, the display panel is an organic light-emitting diode (OLED) display panel, and the light-emitting element is an organic light-emitting diode. The display panel may also include a plurality of scan lines and a plurality of data lines for providing scan signals (control signals) and data signals to the plurality of sub-pixels, thereby driving the plurality of sub-pixels for display. As needed, the display panel may further include power lines, detection lines, etc.

[0093] For example, the pixel circuit includes a driving subcircuit for driving the light-emitting element to emit light and a detection subcircuit for detecting the electrical characteristics of the subpixel to achieve external compensation. The embodiment of the present invention does not limit the specific structure of the pixel circuit.

[0094] For example, Figure 2 shows a schematic diagram of a 3T1C pixel circuit for the display panel. Depending on the application scenario, the pixel circuit may further include a compensation circuit and a reset circuit, etc., which are not limited in the embodiments of the present invention.

[0095] In conjunction with Figures 1 and 2 above, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst. The first electrode of the first transistor T1 is electrically connected to the first capacitor electrode of the storage capacitor Cst and the gate of the third transistor T3. The second electrode of the first transistor T1 is configured to receive a data signal GT. The first transistor T1 is configured to write the data signal DT into the gate of the third transistor T3 and the storage capacitor Cst in response to a first control signal G1. The first electrode of the third transistor T3 is electrically connected to the second capacitor electrode of the storage capacitor Cst and is configured to be electrically connected to the first electrode of the light-emitting element. The second electrode of the third transistor T3 is configured to receive a first power supply voltage V1 (for example, a high power supply voltage VDD). The transistor T3 is configured to control the current used to drive the light-emitting element under the control of the voltage of the gate of the third transistor T3. The first electrode of the second transistor T2 is electrically connected to the first electrode of the third transistor T3 and the second capacitor electrode of the storage capacitor Cst. The second electrode of the second transistor T2 is configured to be connected to the detection line 230 to connect to the external detection circuit 21. The second transistor T2 is configured to detect the electrical characteristics of the sub-pixel to which it belongs in response to the second control signal G2 to achieve external compensation. The electrical characteristics may include, for example, the threshold voltage and / or carrier mobility of the third transistor T3, or the threshold voltage and drive current of the light-emitting element. The external detection circuit 21 is, for example, a conventional circuit including a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), and is not described in detail in the embodiments of the present invention.

[0096] The transistors used in the embodiments of the present invention may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The embodiments of the present invention are described using thin film transistors as an example. The source and drain of the transistors used here may be symmetrical in structure, so their source and drain may be structurally indistinguishable. In the embodiments of the present invention, in order to distinguish the two poles of the transistor other than the gate, one pole is directly described as the first pole and the other pole is directly described as the second pole. In addition, transistors can be divided into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V, or other suitable voltages); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V, or other suitable voltages). It should be noted that in the following description, the transistor in Figure 2 is an N-type transistor as an example for description, but this is not intended to limit the present invention.

[0097] The working principle of the pixel circuit shown in Figure 2 is explained below in conjunction with the signal timing diagrams shown in Figures 3 to 5, where Figure 3 shows a signal timing diagram of the pixel circuit in Figure 2 during the display process, Figure 4 shows a signal timing diagram of the pixel circuit in Figure 2 during the detection process, and Figure 5 shows another signal timing diagram of the pixel circuit in Figure 2 during the detection process.

[0098] For example, as shown in FIG3 , the display process of each frame of image includes a data writing and reset phase 1 and a light-emitting phase 2. FIG3 shows the timing waveforms of each signal in each phase. An operation process of the 3T1C pixel circuit includes: in the data writing and reset phase 1, the first control signal G1 and the second control signal G2 are both on signals, the first transistor T1 and the second transistor T2 are turned on, the data signal DT is transmitted to the gate of the third transistor T3 via the first transistor T1, the first switch K1 is turned off, the analog-to-digital converter writes a reset signal to the first electrode of the light-emitting element (e.g., the anode of the OLED) through the detection line 130 and the second transistor T2, the third transistor T3 is turned on and generates a driving current to charge the first electrode of the light-emitting element to the operating voltage; in the light-emitting phase 2, the first control signal G1 and the second control signal G2 are both off signals, due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the third transistor T3 operates in a saturated state and the current remains unchanged, and drives the light-emitting element to emit light.

[0099] For example, Figure 4 shows a signal timing diagram of the pixel circuit when detecting the threshold voltage. An operating process of the 3T1C pixel circuit includes: the first control signal G1 and the second control signal G2 are both on signals, the first transistor T1 and the second transistor T2 are turned on, and the data signal DT is transmitted to the gate of the third transistor T3 via the first transistor T1; the first switch K1 is closed, the analog-to-digital converter writes a reset signal to the first electrode (node ​​N3) of the light-emitting element through the detection line 230 and the second transistor T2, the third transistor T3 is turned on and charges the node N3 until the third transistor T3 is turned off, and the digital-to-analog converter samples the voltage on the detection line 230 to obtain the threshold voltage of the third transistor T3. This process can be performed, for example, when the display device is turned off.

[0100] For example, FIG5 shows a signal timing diagram of the pixel circuit when performing carrier mobility detection. An operation process of the 3T1C pixel circuit includes: in a first stage, the first control signal G1 and the second control signal G2 are both on signals, the first transistor T1 and the second transistor T2 are turned on, and the data signal DT is transmitted to the gate of the third transistor T3 via the first transistor T1; the first switch K1 is closed, and the analog-to-digital converter writes a reset signal to the first electrode (node ​​N3) of the light-emitting element through the detection line 230 and the second transistor T2; in a second stage, the first control signal G1 is an off signal, and the second control signal G1 is an on signal, the first transistor T1 is turned off, the second transistor T2 is turned on, and the first switch K1 and the second switch K2 are disconnected to float the detection line 130; due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the third transistor T3 operates in a saturated state and the current remains unchanged and drives the light-emitting element to emit light, and then the digital-to-analog converter samples the voltage on the detection line 130 and calculates the carrier mobility in the third transistor T3 based on the magnitude and duration of the light-emitting current. For example, this process can be performed during the blanking phase between display phases.

[0101] Through the above detection, the electrical characteristics of the third transistor T3 can be obtained and a corresponding compensation algorithm can be implemented.

[0102] For example, as shown in FIG1 , the display panel 10 may further include a data driving circuit 23 and a scan driving circuit 24. The data driving circuit 23 is configured to send a data signal, such as the above-mentioned data signal DT, as needed (e.g., an image signal input to the display device); the pixel circuit of each sub-pixel is further configured to receive the data signal and apply the data signal to the gate of the first transistor. The scan driving circuit 24 is configured to output various scan signals, such as the above-mentioned first control signal G1 and the second control signal G2, and is, for example, an integrated circuit chip (IC) or a gate driver circuit (GOA) directly prepared on the display substrate.

[0103] For example, with reference to FIG1 , the display panel 10 further includes a control circuit 22. For example, the control circuit 22 is configured to control the data drive circuit 23 to apply data signals and to control the gate drive circuit to apply scan signals. An example of the control circuit 22 is a timing control circuit (T-con). The control circuit 22 can be in various forms, for example, including a processor 121 and a memory 127, the memory 121 including executable code, and the processor 121 running the executable code to perform the above-described detection method.

[0104] For example, the processor 121 may be a central processing unit (CPU) or other forms of processing devices with data processing capabilities and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0105] For example, the memory 127 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 121 may execute the functions desired by the program instructions. Various applications and various data may also be stored in the computer-readable storage medium, such as the electrical characteristic parameters obtained in the above-mentioned detection method, etc.

[0106] For example, FIG6 is a layout diagram of a display panel including a stacked multi-layer structure. As shown in FIG6 , the first source-drain electrode T2a of the sensing transistor T2 and the first source-drain electrode T3a of the driving transistor T3 are electrically connected via a connecting electrode corresponding to the N3 node. The connecting electrode corresponding to the N3 node is adjacent to the sensing gate line 201 in the second direction Y. The first source-drain electrode T1a of the switching transistor T1 and the second source-drain electrode T3b of the driving transistor T3 are electrically connected via a connecting electrode corresponding to the N1 node. The inventors of the present invention have noted that because the sensing gate line 201 and the connecting electrode corresponding to the N3 node are relatively close in the second direction Y, when the sensing gate line 201 generates a voltage jump, it will cause a voltage jump at the N3 node. This will generate a large instantaneous current at the N3 node, which will impact the organic light-emitting diode, causing damage to the organic light-emitting diode and reducing its lifespan. The voltage jump at the N3 node will also cause a voltage change at the N1 node. Since the voltage change at the N3 node is larger than the voltage change at the N1 node, the voltage change at the N3 node causes greater damage to the organic light-emitting diode device than the damage caused by the voltage change at the N1 node. Therefore, it is possible to consider providing a spacer between the connection electrode corresponding to the N3 node and the sensing gate line to reduce the voltage change at the N3 node caused by the voltage jump of the sensing gate line.

[0107] At least one embodiment of the present invention provides a display panel, which includes: a base substrate; a pixel circuit arranged on the base substrate, the pixel circuit including a sensing transistor, a driving transistor, a first gate line, and a second gate line, wherein the first source-drain electrode of the sensing transistor and the first source-drain electrode of the driving transistor are electrically connected via a first connecting electrode; the first gate line and the second gate line extend in a first direction, and in a second direction intersecting the first direction, a spacer is provided between the first connecting electrode and the first gate line, and between the first connecting electrode and the second gate line, and the first connecting electrode, the first gate line, the second gate line, and the spacer are provided on the same layer. In an embodiment of the present invention, by providing a spacer between the first connecting electrode and the first gate line, and between the first connecting electrode and the second gate line, and by providing the first connecting electrode, the first gate line, the second gate line, and the spacer on the same layer, a voltage change on the first connecting electrode caused by a voltage jump of the first gate line or the second gate line can be reduced, thereby reducing damage to the light-emitting diode and ensuring the service life of the light-emitting diode.

[0108] For example, Figure 7 is a schematic diagram of the planar structure of a first metal layer included in a display panel provided by at least one embodiment of the present invention, Figure 8 is a schematic diagram of the planar structure of a first metal layer and an active layer stacked layer included in a display panel provided by at least one embodiment of the present invention, Figure 9 is a schematic diagram of the planar structure of a first metal layer, an active layer and a second metal layer stacked layer included in a display panel provided by at least one embodiment of the present invention, Figure 10 is a schematic diagram of the planar structure of a via structure formed in the stacked structure shown in Figure 9, Figure 11 is a schematic diagram of the planar structure of a third metal layer included in a display panel provided by at least one embodiment of the present invention, and Figure 12 is a schematic diagram of the planar structure of a first metal layer, an active layer, a second metal layer and a third metal layer stacked layer included in a display panel provided by at least one embodiment of the present invention.

[0109] For example, as shown in conjunction with FIG2 and FIG12, the display panel 30 includes a base substrate 31, a pixel circuit 32 provided on the base substrate 31, the pixel circuit 32 including a sensing transistor T2, a driving transistor T3, a first gate line 321 and a second gate line 323, a first source-drain electrode T2a of the sensing transistor T2 and a first source-drain electrode T3a of the driving transistor T3 being electrically connected via a first connecting electrode M; the first gate line 321 and the second gate line 323 extend in a first direction X, and in a second direction Y intersecting the first direction X, a spacer is provided between the first connecting electrode M and the first gate line 321, and between the first connecting electrode M and the second gate line 323. 322, and the first connecting electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are arranged on the same layer, the spacer 322 is arranged between the first connecting electrode M and the first gate line 321, and between the first connecting electrode M and the second gate line 323, and the first connecting electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are arranged on the same layer, which can reduce the voltage change on the first connecting electrode M caused by the voltage jump of the first gate line 321 or the second gate line 323, and further reduce the damage to the light-emitting diode caused by the voltage change of the first connecting electrode M, so as to ensure the service life of the light-emitting diode.

[0110] For example, in one example, the first gate line 321 is a sensing gate line, and the second gate line 323 is a switching gate line, but the embodiments of the present invention are not limited thereto. The first gate line 321 and the second gate line 323 may also be other gate lines.

[0111] For example, the embodiment of the present invention is described by taking the first direction X as the row direction and the second direction Y as the column direction. In other embodiments, the first direction X may be the column direction and the second direction Y may be the row direction, which is not limited in the embodiment of the present invention.

[0112] For example, in combination with Figures 2 and 12, the display panel 30 also includes a switching transistor T1 and a storage capacitor Cst arranged on the base substrate 31, the first source-drain electrode T1a of the switching transistor T1 and the gate T3g of the driving transistor T3 are connected through the second connecting electrode K, the first plate Ca of the storage capacitor Cst is also connected to the second connecting electrode K, and the second plate Cb of the storage capacitor Cst is connected to the first connecting electrode M.

[0113] 12 , the first connection electrode M and the second connection electrode K are both strip-shaped and disposed on the third metal layer. In subsequent embodiments, the first connection electrode M and the second connection electrode K are disposed at different positions but are both strip-shaped.

[0114] For example, referring to Figures 7 to 12 , the display panel 30 includes a first metal layer 301, an active layer 302, a second metal layer 303, and a third metal layer 304, which are sequentially stacked on a base substrate 31. Although the insulating layer is not directly shown in the plan views shown in Figures 7 to 12 , and is represented by a via structure, an insulating layer structure is provided between the adjacent layers, and a via structure is provided in the insulating layer structure, so that the layer structures that need to be connected are connected through the via structure.

[0115] For example, FIG7 and FIG12 illustrate a pixel circuit corresponding to two sub-pixels arranged in a first direction X. As shown in FIG7 and FIG12 , the first metal layer 301 includes an initialization signal line 3011, a power supply voltage signal line 3012, a first electrode Ca, and a data line 3013 extending in a second direction Y. In one pixel circuit, the initialization signal line 3011, the power supply voltage signal line 3012, and the data line 3013 have equal or substantially equal lengths in the second direction Y. The length of the first electrode Ca in the second direction Y is less than the lengths of the initialization signal line 3011, the power supply voltage signal line 3012, and the data line 3013 in the second direction Y. The widths of the initialization signal line 3011 and the data line 3013 in the first direction X are equal or substantially equal, and both are less than the width of the power supply voltage signal line 3012 in the first direction X. The width of the power supply voltage signal line 3012 in the first direction X is less than the width of the first electrode Ca in the first direction X. The minimum distance between the first electrode Ca and the adjacent power supply voltage signal line 3012 in the first direction X is smaller than the minimum distance between the initialization signal line 3011 and the power supply voltage signal line 3012 in the first direction X, and is smaller than the minimum distance between the first electrode Ca and the adjacent data line 3013 in the first direction X.

[0116] It should be noted that, although FIG7 and FIG12 only show that the power supply voltage signal line 3012 includes a portion extending in the second direction Y, in other embodiments, the power supply voltage signal line 3012 may also include a portion extending in the first direction X.

[0117] For example, as shown in FIG8 , a first metal layer 301 and an active layer 302 are stacked. The active layer 302 includes the channel region T2c of the sensing transistor T2, the channel region T3c of the driving transistor T3, and the channel region T1c of the switching transistor T1. For example, referring to FIG8 and FIG12 , the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate 31 overlaps with the orthographic projection of the initialization signal line 3011 and the orthographic projection of the power supply voltage signal line 3012 on the substrate 31. The orthographic projection of the channel region T3c of the driving transistor T3 on the substrate 31 overlaps with the orthographic projection of the power supply voltage signal line 3012 and the orthographic projection of the first electrode Ca on the substrate 31. The orthographic projection of the channel region T1c of the switching transistor T1 on the substrate 31 overlaps with the orthographic projection of the first electrode Ca and the orthographic projection of the data line 3013 on the substrate 31.

[0118] For example, as shown in Figure 9, a first metal layer 301, an active layer 302, and a second metal layer 303 are stacked in sequence. The second metal layer 303 includes the gate T2g of the sensing transistor T2, the gate T3g of the driving transistor T3, the gate T1g of the switching transistor T1, and the second electrode Cb. The gate T2g of the sensing transistor T2 and the gate T1g of the switching transistor T1 are both long strips extending parallel to the second direction Y. The gate T2g of the sensing transistor T2 extends from the channel region T2c of the sensing transistor T2 in a direction opposite to the second direction Y, while the gate T1g of the switching transistor T1 extends from the channel region T1c of the switching transistor T1 in the second direction Y. The gate T3g of the driving transistor T3 and the second electrode Cb form an integral structure. Referring to Figures 9 and 12, the orthographic projection of the second electrode Cb on the substrate 31 is smaller than the orthographic projection of the first electrode Ca on the substrate 31.

[0119] For example, FIG10 shows that the via structure includes a first via structure 3071, a second via structure 3072, and a third via structure 3073. The connection relationship between the first via structure 3071, the second via structure 3072, and the third via structure 3073 is described below. For example, FIG10 shows six first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e, and 3071f), six second via structures 3072 (3072a, 3072b, 3072c, 3072d, 3072e, and 3072f), and three third via structures 3073 (3073a, 3073b, and 3073c) at a position corresponding to one sub-pixel.

[0120] For example, in conjunction with Figures 10 and 12, the six first via structures 3071 respectively correspond to the positions of both ends of the channel region T2c of the sensing transistor T2, the positions of both ends of the channel region T3c of the driving transistor T3, and the positions of both ends of the channel region T1c of the switching transistor T1. Specifically, the first via structure 3071a and the first via structure 3071b respectively correspond to the positions of both ends of the channel region T2c of the sensing transistor T2; the first via structure 3071c and the first via structure 3071d respectively correspond to the positions of both ends of the channel region T3c of the driving transistor T3; and the first via structure 3071e and the first via structure 3071f respectively correspond to the positions of both ends of the channel region T1c of the switching transistor T1. The orthographic projections of the second via structure 3072a and the second via structure 3072b on the substrate 31 are located within the orthographic projection of the initialization signal line 3011 on the substrate 31 and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate 31 in the second direction Y. The orthographic projections of the second via structure 3072c and the second via structure 3072d on the substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the substrate 31 and are located on both sides of the channel region T2c of the sensing transistor T2 in the second direction Y. The orthographic projection of the second via structure 3072e on the substrate 31 is located within the orthographic projection of the first electrode plate Ca on the substrate 31 and is not located within the orthographic projection of the second electrode plate Cb on the substrate 31. The orthographic projection of the second via structure 3072f on the substrate 31 is located within the orthographic projection of the data line 3013 on the substrate 31. The orthographic projection of the third via structure 3073a on the base substrate 31 is located within the orthographic projection of the gate T2g of the sensing transistor T2 on the base substrate 31; the orthographic projection of the third via structure 3073b on the base substrate 31 is located within the orthographic projection of the first electrode plate Ca on the base substrate 31 and within the orthographic projection of the second electrode plate Cb on the base substrate 31; and the orthographic projection of the third via structure 3073c on the base substrate 31 is located within the orthographic projection of the gate T1g of the switching transistor T1 on the base substrate 31.

[0121] For example, as shown in FIG11 , the third metal layer 304 includes a first connection electrode M, a spacer 322, a second gate line 323 and a first gate line 321 extending in a first direction X, and a first connection structure 3041, a second connection structure 3042, and a third connection structure 3043 extending in a second direction Y. The second gate line 323 and the first gate line 321 are both in an elongated strip shape and extend in the first direction X. The first connection electrode M is also in an elongated strip shape and extends in the first direction X. The first connection structure 3041, the second connection structure 3042, and the third connection structure 3043 are used to achieve connections between the third metal layer 304 and other layer structures. In the second direction Y, the spacer 322b is located between the first connection electrode M and the first gate line 321, thereby reducing the voltage change on the first connection electrode M caused by the first gate line 321 generating a voltage jump. The spacer 322a is located between the first connection electrode M and the second gate line 323, thereby reducing the voltage change on the first connection electrode M caused by the second gate line 323 generating a voltage jump, thereby reducing the damage to the light-emitting diode caused by the voltage change of the first connection electrode M, thereby ensuring the service life of the light-emitting diode.

[0122] For example, with reference to Figures 7 to 12, in the display panel 30, the channel region T2c of the sensing transistor T2 is electrically connected to the first connection structure 3041 through the first via structure 3071a, and is electrically connected to the first connection electrode M through the first via structure 3071b; the channel region T3c of the driving transistor T3 is electrically connected to the spacer 322a through the first via structure 3071c, and is electrically connected to the main body 326 through the first via structure 3071d; the channel region T1c of the switching transistor T1 is electrically connected to the second connection structure 3042 through the first via structure 3071e, and is electrically connected to the third connection structure 3043 through the first via structure 3071f.

[0123] For example, with reference to Figures 7 to 12, in the display panel 30, the first connection structure 3041 is electrically connected to the initialization signal line 3011 located on the first metal layer 301 through the second via structure 3072a and the second via structure 3072b. The spacer 322a is electrically connected to the power supply voltage signal line 3012 through the second via structure 3072c, and the spacer 322b is electrically connected to the power supply voltage signal line 3012 through the second via structure 3072d. The first connection electrode M is electrically connected to the first electrode plate Ca through the second via structure 3072e. The third connection structure 3043 is electrically connected to the data line 3013 through the second via structure 3072f.

[0124] For example, referring to Figures 7 to 12 , in the display panel 30, the gate T2g of the sensing transistor T2 extends in the second direction Y to electrically connect to the first gate line 321. The gate T2g of the sensing transistor T2 and the first gate line 321 are electrically connected via a third via structure 3073a. The gate T1g of the switching transistor T1 extends in a direction opposite to the second direction Y to electrically connect to the second gate line 323. The first gate line 321 connected to the gate T2g of the sensing transistor T2 and the second gate line 323 connected to the gate T1g of the switching transistor T1 are located on different sides of the spacer 322 in the second direction Y. The gate T1g of the switching transistor T1 and the second gate line 323 are electrically connected via a third via structure 3073c. The gate T3g of the driving transistor T3 and the second plate Cb are integrally formed. The second plate Cb is electrically connected to the second connection structure 3042 via a third via structure 3073b.

[0125] It should be noted that, in the structure shown in FIG. 12 , the second connection structure 3042 is reused as the second connection electrode K.

[0126] For example, referring to Figures 7 to 12 , the orthographic projection of the first connection structure 3041 on the base substrate 31 is located within the orthographic projection of the initialization signal line 3011 on the base substrate 31. The orthographic projection of the second connection structure 3042 on the base substrate 31 is located within the orthographic projection of the first electrode plate Ca on the base substrate 31. The orthographic projection of the third connection structure 3043 on the base substrate 31 is located within the orthographic projection of the data line 3013 on the base substrate 31. The orthographic projections of the spacers 322a and 322b on the base substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the base substrate 31.

[0127] For example, in FIG12 , a spacer 322 a and a spacer 322 b located in the third metal layer 304 are located between the sensing transistor T2 and the first gate line 321 and the second gate line 323 located on either side of the sensing transistor T2 in the second direction Y, respectively. The spacer 322 b can shield the coupling between the first source / drain electrode T2a of the sensing transistor T2 and the first gate line 321 connected thereto. The first source / drain electrode T2a of the sensing transistor T2 is located in the third metal layer 304, and the power supply voltage signal line 3012 is located in the first metal layer 301. The spacer 322 b located in the third metal layer 304 between the first gate line 321 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 via a second via structure 3072 d. The spacer 322 a located in the third metal layer 304 between the second gate line 323 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 via a second via structure 3072 c. The switching transistor T1 can reduce the coupling between the second connection electrode K and the gate line (first gate line 321 or second gate line 323). The storage capacitor Cst is a double-layer capacitor, which is respectively between the third metal layer 304 and the second metal layer 303 and between the first metal layer 301 and the second metal layer 303.

[0128] It should be noted that changes in the voltage of the first connection electrode M will cause changes in the voltage of the second connection electrode K. During the data writing phase, it is desirable for the voltage of the first connection electrode M to be more stable. However, during the lighting phase, a voltage rise in the first connection electrode M is normal. During the lighting phase, the voltage rise of the second connection electrode K is caused by coupling with the voltage rise of the first connection electrode M. At this time, the gate of the driving transistor T3 and the power supply voltage signal line 3012 act as a capacitor, and the storage capacitor Cst is also a capacitor. During the coupling process, there is a capacitive voltage divider, so the voltage rise of the second connection electrode K is not as high as the voltage rise of the first connection electrode M. During the data writing phase, it is desirable for the voltage of the first connection electrode M to be more stable. Therefore, the first connection electrode M is protected and shielded by a spacer 322 to reduce the trip voltage. The above design allows the spacer 322 to be provided between the first connection electrode M and the first gate line 321, and the first connection electrode M is formed in the third metal layer 304, on the same layer as the first gate line 321. The shielding effect of the spacer 322 can extend the life of the organic light-emitting diode display device. The sensing transistor T2 and the first connection electrode M connected thereto have spacers 322 on both sides of the second direction Y, which respectively shield the influence of the first gate line 321 and the second gate line 323 on the voltage change of the first connection electrode M. That is, due to the presence of the spacers 322, no parasitic capacitance is formed between the first gate line 321 or the second gate line 323 and the first connection electrode M.

[0129] For example, FIG13 is a schematic diagram of the cross-sectional structure of a display panel provided by at least one embodiment of the present invention. As shown in FIG13 , the display panel 30 further includes a buffer layer 305 disposed on a side of the first metal layer 301 away from the base substrate 31. The buffer layer 305 is formed as a single layer on the base substrate 31. A power supply voltage signal line 3012 is shown on the first metal layer 301. A gate insulating layer 306 is disposed between the active layer 302 and the second metal layer 303, and an interlayer insulating layer 307 is disposed between the second metal layer 303 and the third metal layer 304. A passivation layer 308 and a planarization layer 309 are sequentially disposed on the side of the third metal layer 304 away from the base substrate 31. The interlayer insulating layer 307, the passivation layer 308, and the planarization layer 309 are also formed as a single layer.

[0130] For example, with reference to Figures 12 and 13 , a first via structure 3071 is provided in the interlayer insulating layer 307, and the third metal layer 304 is electrically connected to the active layer 302 via the first via structure 3071. A second via structure 3072 is provided through the interlayer insulating layer 307 and the buffer layer 305, and the third metal layer 304 is electrically connected to the first metal layer 301 via the second via structure 3072. Although not shown in Figure 13 , with reference to Figure 12 , a third via structure 3073 is provided in the interlayer insulating layer 307, and the third metal layer 304 is electrically connected to the second metal layer 303 via the third via structure 3073.

[0131] For example, a double-layer capacitor structure is shown on the left side of Figure 13, that is, a first capacitor structure is formed between the third metal layer 304 and the second metal layer 303, and a second capacitor structure is formed between the second metal layer 303 and the first metal layer 301, and the orthographic projections of the third metal layer 304, the second metal layer 303 and the first metal layer 301 on the substrate 31 all have overlapping parts.

[0132] For example, with reference to FIG12 , in the display panel 30, the first connection structure 3041 is electrically connected to the second source-drain electrode T2b of the sensing transistor T2 through the first via structure 3071a. The second connection structure 3042 is electrically connected to the first source-drain electrode T1a of the switching transistor T1 through the first via structure 3071e, and is electrically connected to the second electrode plate Cb through the third via structure 3073b. The third connection structure 3043 is electrically connected to the data line 3013 through the second via structure 3072f, and is electrically connected to the second source-drain electrode T1b of the switching transistor T1 through the first via structure 3071f.

[0133] For example, in combination with Figure 12, at least a portion of the third metal layer 304 has an overlapping area with the first metal layer 301 and the second metal layer 303, so as to form a storage capacitor Cst between the first metal layer 301 and the second metal layer 303, and a capacitor structure between the second metal layer 303 and the third metal layer 304, thereby forming a dual capacitor structure.

[0134] For example, referring to FIG. 12 , the orthographic projection of the first source-drain electrode T2 a of the sensing transistor T2 on the substrate 31 overlaps with the orthographic projection of the power supply voltage signal line 3012 on the substrate 31 .

[0135] For example, Figure 14 is a schematic diagram of the planar structure of a stack of a first metal layer, an active layer, a second metal layer and a third metal layer included in another display panel provided by at least one embodiment of the present invention, Figure 15 is a schematic diagram of the planar structure of the first metal layer included in the display panel in Figure 14, Figure 16 is a schematic diagram of the planar structure of the stack of the first metal layer and the active layer included in the display panel in Figure 14, Figure 17 is a schematic diagram of the planar structure of the stack of the first metal layer, the active layer and the second metal layer included in the display panel in Figure 14, Figure 18 is a schematic diagram of the planar structure of a via structure formed in the stacked structure shown in Figure 14, and Figure 19 is a schematic diagram of the planar structure of the third metal layer included in the display panel in Figure 14.

[0136] For example, as shown in conjunction with FIG2 and FIG14, the display panel 30 includes a base substrate 31, a pixel circuit 32 provided on the base substrate 31, the pixel circuit 32 including a sensing transistor T2, a driving transistor T3, a switching transistor T1, a first gate line 321, a second gate line 323 and a storage capacitor Cst, a first source-drain electrode T2a of the sensing transistor T2 and a first source-drain electrode T3a of the driving transistor T3 are electrically connected via a first connecting electrode M; the first gate line 321 and the second gate line 323 extend in a first direction X, and in a second direction Y intersecting the first direction X, between the first connecting electrode M and the first gate line 321, between the first connecting electrode M and the second gate line 323 A spacer 322 is provided between each of the first connection electrode M, the first gate line 321, the second gate line 323, and the spacer 322, and the first connection electrode M and the first gate line 321, as well as between the first connection electrode M and the second gate line 323. The first connection electrode M, the first gate line 321, the second gate line 323, and the spacer 322 are provided on the same layer. This can reduce the voltage change on the first connection electrode M caused by a voltage jump on the first gate line 321 or the second gate line 323, thereby reducing the damage to the light-emitting diode caused by the voltage change on the first connection electrode M, thereby ensuring the service life of the light-emitting diode. The first source-drain electrode T1a of the switching transistor T1 and the gate T3g of the driving transistor T3 are connected via the second connection electrode K, the first plate Ca of the storage capacitor Cst is connected to the second connection electrode K, and the second plate Cb of the storage capacitor Cst is connected to the first connection electrode M, to form an entire pixel circuit.

[0137] For example, in FIG14 , a spacer 322 a and a spacer 322 b located in the third metal layer 304 are respectively located between the sensing transistor T2 and the first gate line 321 and the second gate line 323 located on either side thereof in the second direction Y. The spacer 322 b can shield the coupling between the first source-drain electrode T2a of the sensing transistor T2 and the first gate line 321. The first source-drain electrode T2a of the sensing transistor T2 is located in the third metal layer 304, and the power supply voltage signal line 3012 is located in the first metal layer 301. The spacer 322 b located in the third metal layer 304 between the first gate line 321 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 via a second via structure 3072 d. The spacer 322 a located in the third metal layer 304 between the second gate line 323 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 via a second via structure 3072 c. The switching transistor T1 can reduce the coupling between the second connection electrode K and the gate line (first gate line 321 or second gate line 323). The storage capacitor Cst is a double-layer capacitor, which is respectively between the third metal layer 304 and the second metal layer 303 and between the first metal layer 301 and the second metal layer 303.

[0138] For example, in the display panel shown in FIG14 , a portion of the first metal layer 301 is removed below the first source-drain electrode T2a of the sensing transistor T2, thereby reducing parasitic capacitance. That is, the power supply voltage signal line 3012 is narrowed at a position corresponding to the first source-drain electrode T2a of the sensing transistor T2 and the first connection electrode M. This reduces the overlapping area and parasitic capacitance between the power supply voltage signal line 3012 and the first source-drain electrode T2a of the sensing transistor T2.

[0139] For example, in the display panel shown in FIG14 , the switching transistor T1 is two thin-film transistors connected in parallel, one of which is arranged at a position close to the second gate line 323 on the upper side, and the other is arranged at a position close to the first gate line 321 on the lower side, that is, arranged on both sides of the first connection electrode M in the second direction. At the same time, the length of a portion of the first plate Ca of the storage capacitor Cst in the second direction Y is reduced. The above design can increase the channel width-to-length ratio and driving current of the switching transistor T1, thereby facilitating the driving of a high-resolution display panel and reducing the charging time. In addition, the spacing between a portion of the third metal layer corresponding to a portion of the storage capacitor and the first gate line 321 or the second gate line 323 on both sides thereof in the second direction Y can be increased to reduce the coupling between the first plate Ca of the storage capacitor Cst connected to the first connection electrode M and the first gate line 321 or the second gate line 323, and reduce the length of the parasitic capacitance coupled between the first connection electrode M and the gate line.

[0140] For example, in the display panel shown in FIG14 , a portion of the first metal layer 301 below the first source-drain electrode T2 a of the sensing transistor T2 is removed, thereby preventing the first connection electrode M from coupling with the bottom gate of the sensing transistor T2 to generate leakage current.

[0141] For example, in the display panel shown in FIG14 , other structures of the switch transistor T1 except the first source-drain electrode T1 a are not covered by the third metal layer, which can reduce the coupling effect between the switch transistor T1 and the first connection electrode M.

[0142] For example, referring to Figures 14 to 19 , in the display panel 30, the display panel 30 includes a first metal layer 301, an active layer 302, a second metal layer 303, and a third metal layer 304, which are sequentially stacked on a base substrate 31. Although the insulating layer is not directly shown in the plan views shown in Figures 14 to 19 , and is represented by a via structure, an insulating layer structure is provided between the adjacent layers, and a via structure is provided in the insulating layer structure, so that the layer structures that need to be connected are connected through the via structure.

[0143] For example, Figures 14 and 15 illustrate pixel circuits corresponding to two sub-pixels arranged in a first direction X. As shown in Figures 14 and 15 , the first metal layer 301 includes an initialization signal line 3011, a power supply voltage signal line 3012, a first electrode Ca, and a data line 3013 extending in a second direction Y. The initialization signal line 3011 and the data line 3013 are both straight lines extending in the second direction Y. The power supply voltage signal line 3012 includes a first power supply voltage signal line 3012a extending in the second direction Y. The first power supply voltage signal line 3012a includes a first portion 3012b, a second portion 3012c and a third portion 3012d extending in the second direction Y and connected in sequence. The first portion 3012b and the third portion 3012d have the same width in the first direction X. The width of the second portion 3012c in the first direction X is smaller than the width of the first portion 3012b in the first direction X. One end of the second portion 3012c in the second direction Y is connected to an edge of the first portion 3012b close to the third portion 3012d and away from the initialization signal line 3011. The other end of the second portion 3012c in the second direction Y is connected to an edge of the third portion 3012d close to the first portion 3012b and away from the initialization signal line 3011. The edge of second portion 3012c farthest from initialization signal line 3011, the edge of first portion 3012b farthest from initialization signal line 3011, and the edge of third portion 3012d farthest from initialization signal line 3011 are all aligned and in a straight line, thereby forming a notch between second portion 3012c and initialization signal line 3011. The first plate Ca includes a first plate sub-block Ca1 and a second plate sub-block Ca2 connected to each other in a first direction X. The second plate sub-block Ca2 is closer to data line 3013 than the first plate sub-block Ca1, and the length of the second plate sub-block Ca2 in the second direction Y is shorter than the length of the first plate sub-block Ca1 in the second direction Y. In FIG. 15 , the upper edge of the second plate sub-block Ca2 is lower than the upper edge of the first plate sub-block Ca1, and the lower edge of the second plate sub-block Ca2 is higher than the lower edge of the first plate sub-block Ca1.

[0144] For example, as shown in Figures 14 and 16, a first metal layer 301 and an active layer 302 are stacked. The active layer 302 includes the channel region T2c of the sensing transistor T2, the channel region T3c of the driving transistor T3, and the channel regions T1c of the two switching transistors T1. For example, referring to Figures 14 and 16, the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate 31 overlaps with the orthographic projection of the initialization signal line 3011 on the substrate 31. The orthographic projection of the channel region T3c of the driving transistor T3 on the substrate 31 overlaps with the orthographic projection of the power supply voltage signal line 3012 on the substrate 31, as well as the orthographic projection of the first electrode Ca on the substrate 31. The orthographic projections of the channel regions T1c of the two switching transistors T1 on the substrate 31 overlap with the orthographic projection of the data line 3013 on the substrate 31.

[0145] For example, as shown in Figure 17, a first metal layer 301, an active layer 302, and a second metal layer 303 are stacked in sequence. The second metal layer 303 includes the gate T2g of the sensing transistor T2, the gate T3g of the driving transistor T3, the gate T1g of the switching transistor T1, and the second plate Cb. The gates of the two switching transistors T1 are integrally formed. The gates T2g of the sensing transistor T2 and T1g of the switching transistor T1 are both elongated strips extending parallel to a second direction Y. The gate T2g of the sensing transistor T2 extends from the channel region T2c of the sensing transistor T2 in a direction opposite to the second direction Y, while the gate T1g of the switching transistor T1 extends from the channel region T1c of the switching transistor T1 located below it in the second direction Y. The gate T3g of the driving transistor T3 and the second plate Cb are integrally formed. 17 and 14 , the second metal layer 303 includes a first extension 3031 and a second extension 3032 extending from a portion of the second electrode plate Cb corresponding to the second electrode sub-block Ca2 in the second direction Y. Two second connection structures 3042 are respectively connected to the first extension 3031 and the second extension 3032. The orthographic projections of the first extension 3031 and the second extension 3032 on the base substrate 31 do not overlap with the orthographic projection of the first electrode plate Ca on the base substrate 31.

[0146] For example, in one example, the first extension portion 3031 and the second extension portion 3032 are both in the shape of long strips. Of course, the embodiments of the present invention are not limited thereto, and the first extension portion 3031 and the second extension portion 3032 may also be in other shapes such as a block shape.

[0147] For example, FIG18 shows a first via structure 3071, a second via structure 3072, and a third via structure 3073. The connection relationship between the first via structure 3071, the second via structure 3072, and the third via structure 3073 is described below. For example, FIG18 shows eight first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e1, 3071e2, 3071f1, and 3071f2), six second via structures 3072 (3072a, 3072b, 3072c, 3072d, 3072e, and 3072f), and four third via structures 3073 (3073a, 3073b, 3073c, and 3073d) at a position corresponding to one sub-pixel.

[0148] For example, in conjunction with FIG18 and FIG14 , the eight first via structures 3071 respectively correspond to positions at both ends of the channel region T2c of the sensing transistor T2, positions at both ends of the channel region T3c of the driving transistor T3, and positions at both ends of the channel region T1c of the two switching transistors T1. Specifically, the first via structure 3071a and the first via structure 3071b respectively correspond to positions at both ends of the channel region T2c of the sensing transistor T2; the first via structure 3071c and the first via structure 3071d respectively correspond to positions at both ends of the channel region T3c of the driving transistor T3; the first via structure 3071e1 and the first via structure 3071f1 respectively correspond to positions at both ends of the channel region T1c of one of the switching transistors T1; and the first via structure 3071e2 and the first via structure 3071f2 respectively correspond to positions at both ends of the channel region T1c of the other switching transistor T1. The orthographic projections of the second via structure 3072a and the second via structure 3072b on the base substrate 31 are located within the orthographic projection of the initialization signal line 3011 on the base substrate 31, and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 on the base substrate 31 in the second direction Y; the orthographic projections of the second via structure 3072c and the second via structure 3072d on the base substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the base substrate 31, and are located on both sides of the orthographic projection of the sensing transistor T2 on the second direction Y. The two sides of the channel region T2c of the transistor T2 correspond to the first part 3012b and the third part 3012d included in the first power supply voltage signal line 3012a respectively; the orthographic projection of the second via structure 3072e on the base substrate 31 is located within the orthographic projection of the first electrode plate Ca on the base substrate 31, and is not located within the orthographic projection of the second electrode plate Cb on the base substrate 31; the orthographic projection of the second via structure 3072f on the base substrate 31 is located within the orthographic projection of the data line 3013 on the base substrate 31. The orthographic projection of the third via structure 3073a on the base substrate 31 is located within the orthographic projection of the gate T2g of the sensing transistor T2 on the base substrate 31; the orthographic projections of the third via structure 3073b1 and the third via structure 3073b2 on the base substrate 31 are respectively located within the orthographic projections of the first extension portion 3031 and the second extension portion 3032 on the base substrate 31; and the orthographic projection of the third via structure 3073c on the base substrate 31 is located within the orthographic projection of the gate T1g of the switching transistor T1 on the base substrate 31.

[0149] For example, as shown in FIG19 , the third metal layer 304 includes a first connection electrode M, a spacer 322, a second gate line 323 and a first gate line 321 extending in a first direction X, a first connection structure 3041 and a third connection structure 3043 extending in a second direction Y, and two second connection structures 3042 extending in the first direction X. The second gate line 323 and the first gate line 321 are both in an elongated strip shape and extend in the first direction X. The first connection electrode M is also in an elongated strip shape and extends in the first direction X. The first connection structure 3041, the second connection structure 3042, and the third connection structure 3043 are used to achieve connections between the third metal layer 304 and other layer structures. In the second direction Y, the spacer 322b is located between the first connection electrode M and the first gate line 321, thereby reducing the voltage change on the first connection electrode M caused by the first gate line 321 generating a voltage jump. The spacer 322a is located between the first connection electrode M and the second gate line 323, thereby reducing the voltage change on the first connection electrode M caused by the second gate line 323 generating a voltage jump, thereby reducing the damage to the light-emitting diode caused by the voltage change of the first connection electrode M, thereby ensuring the service life of the light-emitting diode.

[0150] It should be noted that, in the embodiment shown in FIG. 14 , the second connection electrode K is reused as the second connection structure 3042 .

[0151] For example, with reference to Figures 14 to 19, in the display panel 30, the channel region T2c of the sensing transistor T2 is electrically connected to the first connection structure 3041 through the first via structure 3071a, and is electrically connected to the first connection electrode M through the first via structure 3071b; the channel region T3c of the driving transistor T3 is electrically connected to the spacer 322a through the first via structure 3071c, and is electrically connected to the main body 326 through the first via structure 3071d; the channel region T1c of the upper switching transistor T1 is electrically connected to the upper second connection structure 3042 through the first via structure 3071e1, and is electrically connected to the third connection structure 3043 through the first via structure 3071f1; and the channel region T1c of the lower switching transistor T1 is electrically connected to the lower second connection structure 3042 through the first via structure 3071e2, and is electrically connected to the third connection structure 3043 through the first via structure 3071f2.

[0152] For example, with reference to Figures 14 to 19, in the display panel 30, the first connection structure 3041 is electrically connected to the initialization signal line 3011 located on the first metal layer 301 through the second via structure 3072a and the second via structure 3072b. The spacer 322a is electrically connected to the first portion 3012b of the first power supply voltage signal line 3012a through the second via structure 3072c, and the spacer 322b is electrically connected to the third portion 3012d of the first power supply voltage signal line 3012a through the second via structure 3072d. The first connection electrode M is electrically connected to the first electrode plate Ca through the second via structure 3072e. The third connection structure 3043 is electrically connected to the data line 3013 through the second via structure 3072f.

[0153] For example, referring to Figures 14 to 19 , in the display panel 30, the gate T2g of the sensing transistor T2 extends in the second direction Y to be electrically connected to the first gate line 321. The gate T2g of the sensing transistor T2 and the first gate line 321 are electrically connected via a third via structure 3073a. The gate T1g of the switching transistor T1 extends in a direction opposite to the second direction Y to be electrically connected to the second gate line 323. The first gate line 321 connected to the gate T2g of the sensing transistor T2 and the second gate line 323 connected to the gate T1g of the switching transistor T1 are located on different sides of the spacer 322 in the second direction Y. The gate T1g of the switching transistor T1 and the second gate line 323 are electrically connected via a third via structure 3073c. The first extension portion 3031 is electrically connected to the second connection structure 3042 located at the upper side through the third via structure 3073b1, and the second extension portion 3032 is electrically connected to the second connection structure 3042 located at the lower side through the third via structure 3073b2.

[0154] For example, referring to Figures 14 to 19 , the orthographic projection of the first connection structure 3041 on the base substrate 31 is located within the orthographic projection of the initialization signal line 3011 on the base substrate 31, and the orthographic projection of the third connection structure 3043 on the base substrate 31 is located within the orthographic projection of the data line 3013 on the base substrate 31. The orthographic projections of the spacers 322a and 322b on the base substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the base substrate 31.

[0155] For example, in FIG14 , a spacer 322 a and a spacer 322 b located in the third metal layer 304 are located between the sensing transistor T2 and the first gate line 321 and the second gate line 323 located on either side of the sensing transistor T2 in the second direction Y, respectively. The spacer 322 b can shield the coupling between the first source / drain electrode T2a of the sensing transistor T2 and the first gate line 321 connected thereto. The first source / drain electrode T2a of the sensing transistor T2 is located in the third metal layer 304, and the power supply voltage signal line 3012 is located in the first metal layer 301. The spacer 322 b located in the third metal layer 304 between the first gate line 321 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 via a second via structure 3072 d. The spacer 322 a located in the third metal layer 304 between the second gate line 323 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 via a second via structure 3072 c. The switching transistor T1 can reduce the coupling between the second connection electrode K and the gate line (first gate line 321 or second gate line 323). The storage capacitor Cst is a double-layer capacitor, which is respectively between the third metal layer 304 and the second metal layer 303 and between the first metal layer 301 and the second metal layer 303.

[0156] It should be noted that changes in the voltage of the first connection electrode M will cause changes in the voltage of the second connection electrode K. During the data writing phase, it is desirable for the voltage of the first connection electrode M to be more stable. However, during the lighting phase, a voltage rise in the first connection electrode M is normal. During the lighting phase, the rise in the voltage of the second connection electrode K is caused by coupling with the voltage rise of the first connection electrode M. At this time, the second connection electrode K and the power supply voltage signal line 3012 act as a capacitor, and the storage capacitor Cst is also a capacitor. During the coupling process, there is a capacitive voltage divider, so the voltage rise of the second connection electrode K is not as high as the voltage rise of the first connection electrode M. During the data writing phase, it is desirable for the voltage of the first connection electrode M to be more stable. Therefore, a spacer 322 is used to protect and shield the first connection electrode M to reduce the jump voltage. The above design allows the spacer 322 to be provided between the first connection electrode M and the first gate line 321, and the first connection electrode M is formed in the third metal layer 304, disposed on the same layer as the first gate line 321. The shielding effect of the spacer 322 can extend the life of the organic light-emitting diode display device. The sensing transistor T2 and the first connection electrode M connected thereto have spacers 322 on both sides of the second direction Y, which respectively shield the influence of the first gate line 321 and the second gate line 323 on the voltage change of the first connection electrode M. That is, due to the presence of the spacers 322, no parasitic capacitance is formed between the first gate line 321 or the second gate line 323 and the first connection electrode M.

[0157] For example, with reference to FIG14 , the orthographic projection of the first source-drain electrode T2 a of the sensing transistor T2 on the substrate 31 is spaced from the orthographic projection of the power supply voltage signal line 3012 on the substrate 31 , that is, the first source-drain electrode T2 a of the sensing transistor T2 is located at the recess between the second portion 3012 c and the initialization signal line 3011 .

[0158] For example, in combination with Figure 2, Figure 14 to Figure 19, the data line 3013 is configured to provide a data signal (data voltage) to the pixel circuit, the second gate line 323 is configured to provide a first scanning signal to the pixel circuit, the first gate line 321 is configured to provide a second scanning signal to the pixel circuit, the initialization signal line 3011 is configured to provide an initialization signal to the pixel circuit, and the power supply voltage signal line 3012 is configured to provide a first power supply voltage VDD to the pixel circuit.

[0159] For example, the cross-sectional structures corresponding to the embodiments shown in the plan views of FIG. 14 to FIG. 19 can refer to the above description of FIG. 13 , which will not be repeated here.

[0160] For example, in conjunction with FIG14 , the driving current of the driving transistor T3 is Wherein, W is the width of the channel of the driving transistor T3 (the width in the second direction), L is the length of the channel of the driving transistor T3 (the length in the first direction), μ n is the carrier mobility of the driving transistor T3, V TH is the threshold voltage of the driving transistor T3, C GI is the capacitance of the gate insulation layer, V GS is the voltage difference between the gate electrode T3g and the first source-drain electrode T3a of the driving transistor T3, V DS is the voltage difference between the first source-drain electrode T3 a and the second source-drain electrode T3 b of the driving transistor T3 .

[0161] For example, in conjunction with FIG. 2 and FIG. 14 , the display panel 30 further includes an organic light emitting diode, and the display panel 30 includes a storage capacitor Cst. and satisfy Greater than or equal to 0.013, ΔV dr is the jump voltage when the first connection electrode M is not shielded, ΔV g is the jump voltage of the first gate line 321, C gc The first gate line 321 and the storage capacitor C st The parasitic capacitance between st is the size of the storage capacitor, A st is the storage capacitor C st The area, d gc The first gate line 321 and the storage capacitor Cst The minimum distance between (the minimum distance in the second direction Y), L c is the length of the portion of the first electrode plate sub-block closest to the first gate line 321 in the first direction (ie, the length of the side of the first electrode plate Ca closest to the first gate line 321), W g is the width of the first gate line 321, d st is the storage capacitor C st The thickness of the corresponding insulating medium is the thickness THK of the interlayer insulating layer between the first plate Ca and the second plate Cb. ILD ,ε is the dielectric constant of the organic material forming the interlayer insulating layer, A gc is the area of ​​the parasitic capacitance formed between the first gate line and the storage electrode.

[0162] For example, in one example, V gON is the turn-on voltage of the second gate line, V gOFF is the turn-off voltage of the second gate line, V oled is the voltage across the organic light-emitting diode, γ is the optical constant, ΔV gray is the change of grayscale voltage.

[0163] For example, in one example, the storage capacitor is a three-layer structure formed by a first metal layer, a second metal layer and a third metal layer. and satisfy Greater than or equal to 0.006, ΔV dr is the jump voltage of the first connection electrode M, ΔV g is the jump voltage of the first gate line 321, C gc The first gate line 321 and the storage capacitor C st The parasitic capacitance between st is the size of the storage capacitor, A st is the area of ​​the storage capacitor, d gc is the minimum distance between the first gate line 321 and the storage capacitor (the minimum distance in the second direction Y), d stu The thickness of the insulating medium corresponding to the upper capacitor in the storage capacitor, that is, the thickness of the interlayer insulating layer between the first plate Ca and the second plate Cb THK ILD , d std The thickness of the insulating medium between the lower layer capacitor of the storage capacitor, that is, the first metal layer and the second metal layer, is the thickness of the buffer layer THK BUF , Lc is the length of the side of the first plate sub-block adjacent to the first gate line 321 (ie, the length of the side of the first plate Ca closest to the first gate line 321), W g is the width of the first gate line, d stThe thickness of the insulating medium corresponding to the storage capacitor, that is, the thickness of the interlayer insulating layer between the first plate Ca and the second plate Cb THK ILD , ε is the dielectric constant of the organic material forming the interlayer insulating layer, A gc is the area of ​​the parasitic capacitance formed between the first gate line and the storage electrode.

[0164] For example, in one example, V gON is the turn-on voltage of the first gate line 321, V gOFF is the off voltage of the first gate line 321, V oled is the voltage across the organic light-emitting diode, γ is the optical constant, ΔV gray is the change of grayscale voltage.

[0165] For example, in one example,

[0166] For example, in one example, W DD is the length of the spacer 322b between the first gate line 321 and the first connection electrode M in the second direction Y, d gd is the minimum distance between the first gate line 321 and the spacer 322b, d sd is the minimum distance between the first connection electrode M and the spacer 322b.

[0167] For example, in one example, L c L is the length of the side of the first plate sub-block adjacent to the first gate line 321, that is, the length of the portion of the first plate sub-block closest to the first gate line 321 in the first direction, that is, the length of the side of the first plate Ca closest to the first gate line 321, p is the sum of the lengths of the first plate sub-block and the second plate sub-block in the first direction X, R l The ratio of the length of the side of the first plate sub-block adjacent to the first gate line 321 to the sum of the lengths of the first plate sub-block and the second plate sub-block in the first direction X is .

[0168] For example, in one example, W c is the width of the storage capacitor in the first direction, d gc is the minimum distance between the first gate line 321 and the storage capacitor, and Pitch is the width of one sub-pixel.

[0169] For example, in conjunction with FIG14, in one example, d gc =10.2μm,d gd=7.9μm, d sd =10.2μm,d c1d =9.03μm, A st =5605μm 2 , C st Length = 90.3 μm, C st Width = 62.07μm, THK ILD =0.5μm, THK BUF =0.3μm, THK GI =0.15μm, Pitch=231μm.

[0170] For example, in the display panel shown in the above embodiment, the size of the storage capacitor C st and the parasitic capacitance C between the second plate Cb of the storage capacitor and the first gate line 321. gc The proportional relationship is: Among them, C gc is the parasitic capacitance between the second plate Cb of the storage capacitor and the first gate line, C st is the size of the storage capacitor, A st is the area of ​​the storage capacitor, d gc is the minimum distance between the first gate line and the storage capacitor, L c is the length of the side of the first plate sub-block adjacent to the first gate line, W c is the width of the storage capacitor, d st The thickness of the insulating medium corresponding to the storage capacitor, that is, the thickness of the interlayer insulating layer between the first plate and the second plate, THK ILD ,ε is the dielectric constant of the organic material forming the interlayer insulating layer, A gc is the area of ​​parasitic capacitance formed between the first gate line and the second electrode plate.

[0171] For example, the size of P involves the thickness of the interlayer insulating layer between the first electrode plate and the second electrode plate, as well as the horizontal parameters of the pixel. When calculating, it is assumed that P is the vertical direction of the pixel (W c and d gc ) is an irrelevant constant. Since W c and d gc It is related to the pixel size and aperture ratio. Their size is positively correlated with the width of the pixel characteristic sub-pixel and the size of the storage capacitor C. st The parasitic capacitance C between the second plate Cb of the storage capacitor and the first gate line 321 is gcThe larger the ratio is, the less the voltage of the first connection electrode M is affected by the parasitic capacitance generated by the first gate line or the second gate line, and the more stable the voltage of the first connection electrode M is.

[0172] For example, Figure 20 is a schematic diagram of the planar structure of a stack of a first metal layer, an active layer, and a second metal layer included in another display panel provided by at least one embodiment of the present invention, Figure 21 is a schematic diagram of the planar structure of the stack of the first metal layer and the active layer included in the display panel in Figure 20, and Figure 22 is a schematic diagram of the planar structure of the second metal layer included in the display panel in Figure 20.

[0173] For example, as shown in conjunction with FIG2 and FIG20, the display panel 30 includes a base substrate 31, a pixel circuit 32 provided on the base substrate 31, the pixel circuit 32 including a sensing transistor T2, a driving transistor T3, a switching transistor T1, a first gate line 321, a second gate line 323, and a storage capacitor Cst, a first source-drain electrode T2a of the sensing transistor T2 and a first source-drain electrode T3a of the driving transistor T3 are electrically connected via a first connecting electrode M; the first gate line 321 and the second gate line 323 extend in a first direction X, In a second direction Y intersecting the first direction X, a spacer 322 is provided between the first connection electrode M and the first gate line 321, and between the first connection electrode M and the second gate line 323, and the first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are provided on the same layer. The spacer 322 is provided between the first connection electrode M and the first gate line 321, and between the first connection electrode M and the second gate line 323, and the first connection electrode M, the first gate line 321, the second gate line 323 and the spacer 322 are provided on the same layer. This can reduce the voltage change on the first connection electrode M caused by a voltage jump in the first gate line 321 or the second gate line 323, thereby reducing the damage to the light-emitting diode caused by the voltage change on the first connection electrode M, thereby ensuring the service life of the light-emitting diode.

[0174] For example, as shown in FIG20 , the display panel 30 further includes a first metal layer 301, an active layer 302, and a second metal layer 303 sequentially stacked on a base substrate 31. The first metal layer 301 includes an initialization signal line 3011 extending in a second direction Y, a power supply voltage signal line 3012 extending at least partially in the second direction Y, a first electrode Ca, and a data line 3013 extending in the second direction Y. The active layer 302 includes a channel region T2c of a sensing transistor T2, a channel region T3c of a driving transistor T3, and a channel region T1c of a switching transistor T1. The channel region T1c of the switching transistor T1, the channel region T3c of the driving transistor T3, and the channel region T2c of the sensing transistor T2 are sequentially arranged in the second direction Y. The second metal layer 303 includes a gate T2g of the sensing transistor T2, a gate T3g of the driving transistor T3, a gate T1g of the switching transistor T1, a second electrode Cb, a first connection electrode M, a second connection electrode K, a spacer 322, and a second gate line 323 and a first gate line 321 extending in the first direction X and spaced apart from each other.

[0175] For example, with reference to Figures 20 and 21 , in the second direction Y, the second connection electrode K is between the first connection electrode M and the second gate line 323 located on the upper side, the gate T1g of the switching transistor T1 is electrically connected to the second gate line 323 located on the upper side, the gate T2g of the sensing transistor T2 is electrically connected to the first gate line 321 located on the lower side, and the second gate line 323 located on the upper side connected to the gate T1g of the switching transistor T1 and the first gate line 321 located on the lower side connected to the gate T2g of the sensing transistor T2 are located on different sides of the first electrode plate Ca in the second direction Y.

[0176] For example, as shown in conjunction with Figures 20 and 21 , the first source-drain electrode T1a of the switching transistor T1 is connected to the second connection electrode K, which also serves as the gate electrode T3g of the driving transistor T3. The first plate Ca of the storage capacitor Cst is connected to the second connection electrode K, and the second plate Cb of the storage capacitor Cst is connected to the first connection electrode M, thereby forming an entire pixel circuit.

[0177] For example, as shown in FIG20 , a portion of the first metal layer 301 is removed below the first source-drain electrode T2a of the sensing transistor T2, thereby reducing parasitic capacitance. That is, the power supply voltage signal line 3012 is narrowed at a position corresponding to the first source-drain electrode T2a of the sensing transistor T2 and the first connection electrode M. This reduces the overlapping area and parasitic capacitance between the power supply voltage signal line 3012 and the first source-drain electrode T2a of the sensing transistor T2.

[0178] 20 and 21 , the initialization signal line 3011 and the data line 3013 are both straight lines extending in the second direction Y. The power supply voltage signal line 3012 includes a first power supply voltage signal line 3012a extending in the second direction Y. The first power supply voltage signal line 3012a includes a first portion 3012b, a second portion 3012c, and a third portion 3012d extending in the second direction Y and connected in sequence. The first portion 3012b and the third portion 3012d have the same width in the first direction X. The second portion 3012c has a smaller width in the first direction X than the first portion 3012b. One end of the second portion 3012c in the second direction Y is connected to an edge of the first portion 3012b that is close to the third portion 3012d and away from the initialization signal line 3011. The other end of the second portion 3012c in the second direction Y is connected to an edge of the third portion 3012d that is close to the first portion 3012b and away from the initialization signal line 3011. The edge of the second portion 3012c farthest from the initialization signal line 3011, the edge of the first portion 3012b farthest from the initialization signal line 3011, and the edge of the third portion 3012d farthest from the initialization signal line 3011 are all aligned and on a straight line, thereby forming a notch between the second portion 3012c and the initialization signal line 3011. The planar shape of the first electrode Ca is rectangular.

[0179] For example, as shown in FIG21 , the first metal layer 301 and the active layer 302 are stacked. For example, referring to FIG20 and FIG21 , the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate 31 overlaps with the orthographic projection of the initialization signal line 3011 on the substrate 31. The orthographic projection of the channel region T3c of the driving transistor T3 on the substrate 31 also overlaps with the orthographic projection of the power supply voltage signal line 3012 on the substrate 31 and the orthographic projection of the first electrode Ca on the substrate 31. The orthographic projection of the channel region T1c of the switching transistor T1 on the substrate 31 does not overlap with the structure on the first metal layer 301.

[0180] For example, as shown in FIG20 and FIG22 , the gate T1g of the driving transistor T3, the gate T2g of the sensing transistor T2, and the gate T1g of the switching transistor T1 are all strip-shaped, extending parallel to the second direction Y. The gate T2g of the sensing transistor T2 extends from the channel region T2c of the sensing transistor T2 in a direction opposite to the second direction Y, and the gate T1g of the switching transistor T1 extends from the channel region T1c of the switching transistor T1 in the second direction Y. The gate T3g of the driving transistor T3 and the second connection electrode K are formed as an integral structure. The first connection electrode M and the second electrode plate Cb are formed as an integral structure.

[0181] For example, as shown in conjunction with Figures 20 and 22, the second metal layer 303 further includes a first connection structure 3041 and a second connection structure 3042 extending in the second direction Y, and a third connection structure 3042 extending in the first direction X. The second connection electrode K is reused as the second connection structure 3042. The second gate line 323 and the first gate line 321 are both in the shape of an elongated strip and extend in the first direction X. The first connection electrode M is also in the shape of an elongated strip and extends in the first direction X. The first connection structure 3041, the second connection structure 3042, and the third connection structure 3043 are used to achieve connections between the third metal layer 304 and other layer structures.

[0182] For example, a first via structure 3071 and a second via structure 3072 are shown in FIG20 , and the connection relationship between the first via structure 3071 and the second via structure 3072 is described below. For example, six first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e, and 3071f) and six second via structures 3072 (3072a, 3072b, 3072c, 3072d, 3072e, and 3072f) are shown at a position corresponding to one sub-pixel in FIG20 .

[0183] For example, in conjunction with Figures 20 and 21, the six first via structures 3071 respectively correspond to the positions of both ends of the channel region T2c of the sensing transistor T2, the positions of both ends of the channel region T3c of the driving transistor T3, and the positions of both ends of the channel region T1c of the switching transistor T1. Specifically, the first via structure 3071a and the first via structure 3071b respectively correspond to the positions of both ends of the channel region T2c of the sensing transistor T2; the first via structure 3071c and the first via structure 3071d respectively correspond to the positions of both ends of the channel region T3c of the driving transistor T3; and the first via structure 3071e and the first via structure 3071f respectively correspond to the positions of both ends of the channel region T1c of the switching transistor T1. The orthographic projections of the second via structure 3072a and the second via structure 3072b on the substrate 31 are located within the orthographic projection of the initialization signal line 3011 on the substrate 31, and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate 31 in the second direction Y. The orthographic projections of the second via structure 3072c and the second via structure 3072d on the substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the substrate 31, and are located on both sides of the orthographic projection of the sensing transistor T2 in the second direction Y. 2, namely, corresponding to the first portion 3012b and the third portion 3012d included in the first power supply voltage signal line 3012a; the orthographic projection of the second via structure 3072e on the base substrate 31 is located within the orthographic projection of the second connection electrode K and the first electrode plate Ca on the base substrate 31, and is not located within the orthographic projection of the second electrode plate Cb on the base substrate 31; the orthographic projection of the second via structure 3072f on the base substrate 31 is located within the orthographic projection of the data line 3013 on the base substrate 31.

[0184] For example, with reference to Figures 20 to 22, in the display panel 30, the channel region T2c of the sensing transistor T2 is electrically connected to the first connection structure 3041 through the first via structure 3071a, and is electrically connected to the first connection electrode M through the first via structure 3071b; the channel region T3c of the driving transistor T3 is electrically connected to the spacer 322a through the first via structure 3071c, and is electrically connected to the second electrode plate Cb through the first via structure 3071d; the channel region T1c of the switching transistor T1 is electrically connected to the second connection structure 3042 through the first via structure 3071e, and is electrically connected to the third connection structure 3043 through the first via structure 3071f.

[0185] For example, with reference to Figures 20 to 22, in the display panel 30, the first connection structure 3041 is electrically connected to the initialization signal line 3011 located on the first metal layer 301 through the second via structure 3072a and the second via structure 3072b. The spacer 322a is electrically connected to the first portion 3012b of the first power supply voltage signal line 3012a through the second via structure 3072c, and the spacer 322b is electrically connected to the third portion 3012d of the first power supply voltage signal line 3012a through the second via structure 3072d. The second connection electrode K is electrically connected to the first electrode plate Ca through the second via structure 3072e. The third connection structure 3043 is electrically connected to the data line 3013 through the second via structure 3072f.

[0186] For example, Figure 23 is a schematic diagram of the planar structure of a stack of a first metal layer, an active layer, a second metal layer and a third metal layer included in another display panel provided by at least one embodiment of the present invention, Figure 24 is a schematic diagram of the planar structure of the first metal layer included in the display panel in Figure 23, Figure 25 is a schematic diagram of the planar structure of the stack of the first metal layer and the active layer included in the display panel in Figure 23, Figure 26 is a schematic diagram of the planar structure of the stack of the first metal layer, the active layer and the second metal layer included in the display panel in Figure 23, Figure 27 is a schematic diagram of the planar structure of a via structure formed in the stacked structure shown in Figure 26, and Figure 28 is a schematic diagram of the planar structure of the third metal layer included in the display panel in Figure 23.

[0187] For example, as shown in FIG23 , the display panel 30 includes a base substrate 31, a pixel circuit 32 provided on the base substrate 31, the pixel circuit 32 including a sensing transistor T2, a driving transistor T3, a switching transistor T1, a first gate line 321, a second gate line 323, and a storage capacitor Cst. The first source-drain electrode T2a of the sensing transistor T2 and the first source-drain electrode T3a of the driving transistor T3 are electrically connected via a first connecting electrode M. The first gate line 321 and the second gate line 323 extend in a first direction X, and in a second direction Y intersecting the first direction X, there are two electrodes between the first connecting electrode M and the first gate line 321 and between the first connecting electrode M and the second gate line 323. A spacer 322 is provided, and the first connection electrode M, the first gate line 321, the second gate line 323, and the spacer 322 are arranged in the same layer. The spacer 322 is arranged between the first connection electrode M and the first gate line 321, and between the first connection electrode M and the second gate line 323. The first connection electrode M, the first gate line 321, the second gate line 323, and the spacer 322 are arranged in the same layer. This can reduce the voltage change on the first connection electrode M caused by the voltage jump of the first gate line 321 or the second gate line 323, thereby reducing the damage to the light-emitting diode caused by the voltage change of the first connection electrode M, thereby ensuring the service life of the light-emitting diode. The first source-drain electrode T1a of the switching transistor T1 and the gate T3g of the driving transistor T3 are connected via the second connection electrode K. The first plate Ca of the storage capacitor Cst is connected to the second connection electrode K. The second plate Cb of the storage capacitor Cst is connected to the first connection electrode M, thereby forming an integral pixel circuit.

[0188] For example, in FIG23 , a spacer 322 a and a spacer 322 b located in the third metal layer 304 are located between the sensing transistor T2 and the first gate line 321 and the second gate line 323 located on either side thereof in the second direction Y. The spacer 322 b can shield the coupling between the first source / drain electrode T2a of the sensing transistor T2 and the first gate line 321. The first source / drain electrode T2a of the sensing transistor T2 is located in the third metal layer 304, and the power supply voltage signal line 3012 is located in the first metal layer 301. The spacer 322 b located in the third metal layer 304 between the first gate line 321 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 via a second via structure 3072 d. The spacer 322 a located in the third metal layer 304 between the second gate line 323 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 via a second via structure 3072 c. The switching transistor T1 can reduce the coupling between the second connection electrode K and the first gate line 321 or the second gate line 323 .

[0189] For example, FIG23 and FIG24 illustrate a pixel circuit corresponding to two sub-pixels arranged in a first direction X. As shown in FIG23 and FIG24 , the first metal layer 301 includes an initialization signal line 3011, a power supply voltage signal line 3012, a first electrode Ca, a data line 3013, and a light shielding portion 3014 extending in a second direction Y. The initialization signal line 3011 and the data line 3013 are both straight lines extending in the second direction Y. The power supply voltage signal line 3012 includes a first power supply voltage signal line 3012a extending in the second direction Y. The first power supply voltage signal line 3012a includes a first portion 3012b, a second portion 3012c and a third portion 3012d extending in the second direction Y and connected in sequence. The first portion 3012b and the third portion 3012d have the same width in the first direction X. The width of the second portion 3012c in the first direction X is smaller than the width of the first portion 3012b in the first direction X. One end of the second portion 3012c in the second direction Y is connected to an edge of the first portion 3012b close to the third portion 3012d and away from the initialization signal line 3011. The other end of the second portion 3012c in the second direction Y is connected to an edge of the third portion 3012d close to the first portion 3012b and away from the initialization signal line 3011. The edge of the second part 3012c farthest from the initialization signal line 3011, the edge of the first part 3012b farthest from the initialization signal line 3011, and the edge of the third part 3012d farthest from the initialization signal line 3011 are all aligned and on a straight line, so a notch is formed between the second part 3012c and the initialization signal line 3011.

[0190] For example, referring to FIG. 23 and FIG. 24 , in the display panel shown in FIG. 23 , a portion of the first metal layer 301 is removed below the first source-drain electrode T2a of the sensing transistor T2. This can reduce parasitic capacitance. That is, the power supply voltage signal line 3012 is narrowed at a position corresponding to the first source-drain electrode T2a of the sensing transistor T2 and the first connection electrode M. This can reduce the overlapping area and parasitic capacitance between the power supply voltage signal line 3012 and the first source-drain electrode T2a of the sensing transistor T2.

[0191] For example, referring to FIG26 , a first metal layer 301, an active layer 302, and a second metal layer 303 are stacked in sequence. The second metal layer 303 includes the gate T2g of the sensing transistor T2, the gate T3g of the driving transistor T3, the gate T1g of the switching transistor T1, and a first electrode Ca. The gates of the two switching transistors T1 are integrally formed. The gates T2g of the sensing transistor T2 and the gate T1g of the switching transistor T1 are both elongated strips extending parallel to a second direction Y. The gate T2g of the sensing transistor T2 extends from the channel region T2c of the sensing transistor T2 in a direction opposite to the second direction Y. The gate T1g of the switching transistor T1 extends from the channel region T1c of the switching transistor T1 located below it in the second direction Y. The gate T3g of the driving transistor T3 and the first electrode Ca are integrally formed. 23 and 26 , the first electrode plate Ca includes a first electrode plate sub-block Ca1 and a second electrode plate sub-block Ca2 connected to each other. The second electrode plate sub-block Ca2 includes a first extension portion 3031 and a second extension portion 3032 extending in a second direction Y. Two second connection structures 3042 are respectively connected to the first extension portion 3031 and the second extension portion 3032. The orthographic projections of the first extension portion 3031 and the second extension portion 3032 on the base substrate 31 do not overlap with the orthographic projection of the first metal layer 301 on the base substrate 31.

[0192] For example, FIG23 shows a first via structure 3071, a second via structure 3072, and a third via structure 3073. The connection relationship between the first via structure 3071, the second via structure 3072, and the third via structure 3073 is described below. For example, FIG23 shows eight first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e1, 3071e2, 3071f1, and 3071f2), five second via structures 3072 (3072a, 3072b, 3072c, 3072d, and 3072e), and four third via structures 3073 (3073a, 3073b, 3073c, and 3073d) at a position corresponding to one sub-pixel.

[0193] For example, with reference to Figures 23, 26, and 27, the eight first via structures 3071 correspond to positions at both ends of the channel region T2c of the sensing transistor T2, positions at both ends of the channel region T3c of the driving transistor T3, and positions at both ends of the channel region T1c of the two switching transistors T1, respectively. Specifically, the first via structure 3071a and the first via structure 3071b correspond to positions at both ends of the channel region T2c of the sensing transistor T2, respectively; the first via structure 3071c and the first via structure 3071d correspond to positions at both ends of the channel region T3c of the driving transistor T3, respectively; the first via structure 3071e1 and the first via structure 3071f1 correspond to positions at both ends of the channel region T1c of one of the switching transistors T1, respectively; and the first via structure 3071e2 and the first via structure 3071f2 correspond to positions at both ends of the channel region T1c of the other switching transistor T1, respectively. The orthographic projections of the second via structure 3072a and the second via structure 3072b on the base substrate 31 are located within the orthographic projection of the initialization signal line 3011 on the base substrate 31 and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 on the base substrate 31 in the second direction Y. The orthographic projections of the second via structure 3072c and the second via structure 3072d on the base substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the base substrate 31 and are located on both sides of the channel region T2c of the sensing transistor T2 in the second direction Y, that is, they correspond to the first portion 3012b and the third portion 3012d included in the first power supply voltage signal line 3012a, respectively. The orthographic projection of the second via structure 3072e on the base substrate 31 is located within the orthographic projection of the data line 3013 on the base substrate 31. The orthographic projection of the third via structure 3073a on the base substrate 31 is located within the orthographic projection of the gate T2g of the sensing transistor T2 on the base substrate 31; the orthographic projections of the third via structure 3073b and the third via structure 3073c on the base substrate 31 are respectively located within the orthographic projections of the first extension portion 3031 and the second extension portion 3032 on the base substrate 31; and the orthographic projection of the third via structure 3073d on the base substrate 31 is located within the orthographic projection of the gate T1g of the switching transistor T1 on the base substrate 31.

[0194] For example, in combination with Figures 26 and 27, in the display panel shown in Figure 23, the switching transistor T1 is two thin-film transistors connected in parallel, one of which is arranged at a position close to the second gate line 323 on the upper side, and the other is arranged at a position close to the first gate line 321 on the lower side, that is, arranged on both sides of the first connection electrode M in the second direction Y, and at the same time, the length of a portion of the second electrode sub-block Ca2 in the second direction Y is reduced. The above design can increase the channel width-to-length ratio and driving current of the switching transistor T1, which is beneficial to the driving of the high-resolution display panel and reduces the charging time.

[0195] For example, in the display panel shown in FIG23 , a portion of the first metal layer 301 below the first source-drain electrodes T1a of the two switching transistors T1 is removed, thereby preventing the first connection electrode M and the bottom gate of the switching transistor T1 from coupling and generating leakage current.

[0196] For example, referring to FIG24 and FIG25 , in the display panel shown in FIG23 , no other structures exist between the power supply voltage signal line 3012 and the data line 3013 except for the light shielding portion 3014. The light shielding portion 3014 includes a light shielding portion 3014a located below the channel region T3c of the driving transistor T3, a light shielding portion 3014b located below the channel region T1c of the upper switching transistor T1, and a light shielding portion 3014c located below the channel region T1c of the lower switching transistor T1.

[0197] For example, in the display panel shown in FIG23 , other structures of the switch transistor T1 except the first source-drain electrode T1 a are not covered by the third metal layer, which can reduce the coupling effect between the switch transistor T1 and the first connection electrode M.

[0198] For example, referring to Figures 23 to 28 , in the display panel 30, the display panel 30 includes a first metal layer 301, an active layer 302, a second metal layer 303, and a third metal layer 304, which are sequentially stacked on a base substrate 31. Although the insulating layer is not directly shown in the plan views shown in Figures 23 to 28 , and is represented by a via structure, an insulating layer structure is provided between the adjacent layers, and a via structure is provided in the insulating layer structure, so that the layer structures that need to be connected are connected through the via structure.

[0199] For example, as shown in Figures 23 and 25 , a first metal layer 301 and an active layer 302 are stacked. The active layer 302 includes the channel region T2c of the sensing transistor T2, the channel region T3c of the driving transistor T3, and the channel regions T1c of the two switching transistors T1. For example, referring to Figures 23 and 25 , the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate 31 overlaps with the orthographic projection of the initialization signal line 3011 on the substrate 31. The orthographic projection of the channel region T3c of the driving transistor T3 on the substrate 31 also overlaps with the orthographic projection of the power supply voltage signal line 3012 on the substrate 31 and the orthographic projection of the light shielding portion 3014a on the substrate 31. The orthographic projections of the channel regions T1c of the two switch transistors T1 on the base substrate 31 overlap with the orthographic projections of the data line 3013 on the base substrate 31 and overlap with the orthographic projections of the light shielding portion 3014b and the light shielding portion 3014c on the base substrate 31 respectively.

[0200] For example, as shown in FIG28 , in the display panel shown in FIG23 , the third metal layer 304 includes a first connection electrode M, a spacer 322, a second gate line 323 and a first gate line 321 extending in a first direction X and having an elongated shape, a first connection structure 3041 and a third connection structure 3043 extending in a second direction Y, and two second connection structures 3042 extending in the first direction X. The orthographic projection of the first connection structure 3041 on the base substrate 31 is located within the orthographic projection of the initialization signal line 3011 on the base substrate 31, and the orthographic projection of the third connection structure 3043 on the base substrate 31 is located within the orthographic projection of the data line 3013 on the base substrate 31. The first connection electrode M is also elongated and extends in the first direction X. The first connection structure 3041, the second connection structure 3042, and the third connection structure 3043 are used to connect the third metal layer 304 to other layer structures. In the second direction Y, the spacer 322b is located between the first connection electrode M and the first gate line 321, thereby reducing the voltage change on the first connection electrode M caused by the first gate line 321 generating a voltage jump. The spacer 322a is located between the first connection electrode M and the second gate line 323, thereby reducing the voltage change on the first connection electrode M caused by the second gate line 323 generating a voltage jump, thereby reducing the damage to the light-emitting diode caused by the voltage change of the first connection electrode M, thereby ensuring the service life of the light-emitting diode.

[0201] For example, Figure 29 is a schematic diagram of the cross-sectional structure of the display panel in Figure 23. As shown in Figure 29, the display panel 30 also includes a buffer layer 305 arranged on the side of the first metal layer 301 away from the base substrate 31, a gate insulation layer 306 arranged between the active layer 302 and the second metal layer 303, an interlayer insulation layer 307 arranged between the second metal layer 303 and the third metal layer 304, and a passivation layer 308 and a planarization layer 309 arranged on the side of the third metal layer 304 away from the base substrate 31.

[0202] For example, as shown in FIG. 29 , a first via structure 3071 is provided in the interlayer insulating layer 307 , and the third metal layer 304 is electrically connected to the active layer 302 through the first via structure 3071 .

[0203] For example, as shown in FIG29 , a storage capacitor is formed between the third metal layer 304 and the second metal layer 303. In conjunction with FIG23 and FIG29 , the first source-drain electrode T1a of the switching transistor T1 and the first plate Ca of the storage capacitor Cst are connected via the second connection electrode K. That is, the first source-drain electrodes T1a of the two switching transistors T1 are respectively connected to the first extension portion 3031 and the second extension portion 3032 of the second plate sub-block Ca2.

[0204] For example, Figure 30 is a schematic diagram of the planar structure of a stack of a first metal layer, an active layer, and a second metal layer included in another display panel provided by at least one embodiment of the present invention, Figure 31 is a schematic diagram of the planar structure of the stack of the first metal layer and the active layer included in the display panel in Figure 30, Figure 32 is a schematic diagram of the planar structure of the second metal layer in Figure 30, and Figure 33 is a schematic diagram of the cross-sectional structure of the display panel in Figure 30.

[0205] For example, as shown in combination with Figures 2 and 30, the display panel 30 includes a base substrate 31, a pixel circuit 32 provided on the base substrate 31, the pixel circuit 32 includes a sensing transistor T2, a driving transistor T3, a switching transistor T1, a first gate line 321, a second gate line 323 and a storage capacitor Cst, and a first source-drain electrode T2a of the sensing transistor T2 and a first source-drain electrode T3a of the driving transistor T3 are electrically connected via a first connecting electrode M. The first gate line 321 and the second gate line 323 extend in a first direction X. In a second direction Y intersecting the first direction X, a spacer 322 is provided between the first connection electrode M and the first gate line 321, and between the first connection electrode M and the second gate line 323. The first connection electrode M, the first gate line 321, the second gate line 323, and the spacer 322 are provided on the same layer. The spacer 322 is provided between the first connection electrode M and the first gate line 321, and between the first connection electrode M and the second gate line 323. The first connection electrode M, the first gate line 321, the second gate line 323, and the spacer 322 are provided on the same layer. This can reduce a voltage change on the first connection electrode M caused by a voltage jump in the first gate line 321 or the second gate line 323, thereby reducing damage to the light-emitting diode caused by the voltage change in the first connection electrode M, thereby ensuring the service life of the light-emitting diode. The first source-drain electrode T1a of the switching transistor T1 and the gate T3g of the driving transistor T3 are connected via the second connection electrode K, the first plate Ca of the storage capacitor Cst is connected to the second connection electrode K, and the second plate Cb of the storage capacitor Cst is connected to the first connection electrode M to form an entire pixel circuit.

[0206] For example, in FIG30 , a spacer 322 a and a spacer 322 b located in the second metal layer 303 are respectively located between the sensing transistor T2 and the first gate line 321 and the second gate line 323 located on either side thereof in the second direction Y. The spacer 322 b can shield the coupling between the first source-drain electrode T2a of the sensing transistor T2 and the first gate line 321. The first source-drain electrode T2a of the sensing transistor T2 is located in the second metal layer 303, and the power supply voltage signal line 3012 is located in the first metal layer 301. The spacer 322 b located in the second metal layer 303 between the first gate line 321 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 via a second via structure 3072 d. The spacer 322 a located in the second metal layer 303 between the second gate line 323 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 via a second via structure 3072 c. The switch transistor T1 can reduce the coupling between the second connection electrode K and the gate line (the first gate line 321 or the second gate line 323 ). The storage capacitor Cst includes a first electrode Ca located in the active layer 302 and a second electrode Cb located in the second metal layer 303 .

[0207] For example, in the display panel shown in FIG30 , a portion of the first metal layer 301 is removed below the first source-drain electrode T2a of the sensing transistor T2, thereby reducing parasitic capacitance. That is, the power supply voltage signal line 3012 is narrowed at a position corresponding to the first source-drain electrode T2a of the sensing transistor T2 and the first connection electrode M. This reduces the overlapping area and parasitic capacitance between the power supply voltage signal line 3012 and the first source-drain electrode T2a of the sensing transistor T2.

[0208] For example, in the display panel shown in FIG30 , a portion of the first metal layer 301 under the first source-drain electrode T1a, the channel region T1c, and the second source-drain electrode T1b of the switching transistor T1 is removed, thereby preventing the first connection electrode M and the bottom gate of the switching transistor T1 from coupling and generating leakage current.

[0209] For example, referring to Figures 30 to 32 , the display panel 30 includes a first metal layer 301, an active layer 302, and a second metal layer 303, which are sequentially stacked on a base substrate 31. Although the insulating layer is not directly shown in the plan views of Figures 30 to 32 , and is represented by a via structure, an insulating layer structure is provided between the adjacent layers, and a via structure is provided in the insulating layer structure, so that the layer structures that need to be connected are connected through the via structure.

[0210] For example, FIG30 and FIG31 illustrate pixel circuits corresponding to two sub-pixels arranged in the first direction X. As shown in FIG30 and FIG31 , the first metal layer 301 includes an initialization signal line 3011, a power supply voltage signal line 3012, and a data line 3013 extending in the second direction Y. The initialization signal line 3011 and the data line 3013 are both straight lines extending in the second direction Y. The power supply voltage signal line 3012 includes a first power supply voltage signal line 3012a extending in the second direction Y. The first power supply voltage signal line 3012a includes a first portion 3012b, a second portion 3012c and a third portion 3012d extending in the second direction Y and connected in sequence. The first portion 3012b and the third portion 3012d have the same width in the first direction X. The width of the second portion 3012c in the first direction X is smaller than the width of the first portion 3012b in the first direction X. One end of the second portion 3012c in the second direction Y is connected to an edge of the first portion 3012b close to the third portion 3012d and away from the initialization signal line 3011. The other end of the second portion 3012c in the second direction Y is connected to an edge of the third portion 3012d close to the first portion 3012b and away from the initialization signal line 3011. The edge of the second part 3012c farthest from the initialization signal line 3011, the edge of the first part 3012b farthest from the initialization signal line 3011, and the edge of the third part 3012d farthest from the initialization signal line 3011 are all aligned and on a straight line, so a notch is formed between the second part 3012c and the initialization signal line 3011.

[0211] For example, as shown in Figures 30 and 31, a first metal layer 301 and an active layer 302 are stacked. The active layer 302 includes a channel region T2c of the sensing transistor T2, a channel region T3c of the driving transistor T3, a channel region T1c of the switching transistor T1, and a first plate Ca of the storage capacitor Cst. The channel region T3c of the driving transistor T3 and the first plate Ca of the storage capacitor Cst are integrally formed. For example, referring to Figures 30 and 31, the orthographic projection of the channel region T2c of the sensing transistor T2 on the substrate 31 overlaps with the orthographic projection of the initialization signal line 3011 on the substrate 31. The orthographic projection of the channel region T3c of the driving transistor T3 on the substrate 31 overlaps with the orthographic projection of the power supply voltage signal line 3012 on the substrate 31. For example, the edge of the first plate Ca of the storage capacitor Cst on the side closest to the second gate line 321 extends in the first direction X to directly above the power supply voltage signal line 3012.

[0212] For example, as shown in FIG32 , the second metal layer 303 includes the gate T2g of the sensing transistor T2, the gate T3g of the driving transistor T3, the gate T1g of the switching transistor T1, a second electrode Cb, a first connection electrode M, a spacer 322, a second gate line 323, a first gate line 321, a first connection structure 3041, a second connection structure 3042, and a third connection structure 3043. Referring to FIG30 and FIG32 , the gate T2g of the sensing transistor T2, the gate T3g of the driving transistor T3, and the gate T1g of the switching transistor T1 are all in the shape of elongated strips extending parallel to the second direction Y. The gate T2g of the sensing transistor T2 extends from the channel region T2c of the sensing transistor T2 in a direction opposite to the second direction Y, and the gate T1g of the switching transistor T1 extends from the channel region T1c of the switching transistor T1 in the second direction Y. The orthographic projection of the second electrode Cb on the base substrate 31 is located within the orthographic projection of the first electrode Ca on the base substrate 31. The second gate line 323 and the first gate line 321 are both elongated and extend in the first direction X. The first connection electrode M is also elongated and extends in the first direction X. The first connection structure 3041 extends in the second direction Y, and the second connection structure 3042 and the third connection structure 3043 extend in the first direction X. The first connection structure 3041, the second connection structure 3042, and the third connection structure 3043 are used to connect the third metal layer 304 and other layer structures. In the second direction Y, the spacer 322b is located between the first connection electrode M and the first gate line 321, thereby reducing the voltage change caused to the first connection electrode M when the first gate line 321 generates a voltage jump. The spacer 322a is located between the first connection electrode M and the second gate line 323, thereby reducing the voltage change caused to the first connection electrode M when the second gate line 323 generates a voltage jump. This can further reduce the damage caused to the light-emitting diode by the voltage change of the first connection electrode M, thereby ensuring the service life of the light-emitting diode.

[0213] For example, a first via structure 3071 and a second via structure 3072 are shown in FIG30 , and the connection relationship between the first via structure 3071 and the second via structure 3072 is described below. For example, six first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e, and 3071f) and six second via structures 3072 (3072a, 3072b, 3072c, 3072d, 3072e, and 3072f) are shown at a position corresponding to one sub-pixel in FIG30 .

[0214] For example, in conjunction with Figures 30 and 31, the six first via structures 3071 respectively correspond to the positions of both ends of the channel region T2c of the sensing transistor T2, the positions of both ends of the channel region T3c of the driving transistor T3, and the positions of both ends of the channel region T1c of the two switching transistors T1. Specifically, the first via structure 3071a and the first via structure 3071b respectively correspond to the positions of both ends of the channel region T2c of the sensing transistor T2; the first via structure 3071c and the first via structure 3071d respectively correspond to the positions of both ends of the channel region T3c of the driving transistor T3; and the first via structure 3071e and the first via structure 3071f respectively correspond to the positions of both ends of the channel region T1c of the switching transistor T1. The orthographic projections of the second via structure 3072a and the second via structure 3072b on the base substrate 31 are located within the orthographic projection of the initialization signal line 3011 on the base substrate 31, and are located on both sides of the orthographic projection of the channel region T2c of the sensing transistor T2 on the base substrate 31 in the second direction Y; the orthographic projections of the second via structure 3072c and the second via structure 3072d on the base substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the base substrate 31, and are located on both sides of the orthographic projection of the sensing transistor T2 on the second direction Y. The two sides of the channel region T2c of the transistor T2 correspond to the first part 3012b and the third part 3012d included in the first power supply voltage signal line 3012a respectively; the orthographic projection of the second via structure 3072e on the base substrate 31 is located within the orthographic projection of the first electrode plate Ca on the base substrate 31, and is not located within the orthographic projection of the second electrode plate Cb on the base substrate 31; the orthographic projection of the second via structure 3072f on the base substrate 31 is located within the orthographic projection of the data line 3013 on the base substrate 31.

[0215] For example, with reference to Figures 30 to 32, in the display panel 30, the channel region T2c of the sensing transistor T2 is electrically connected to the first connection structure 3041 through the first via structure 3071a, and is electrically connected to the first connection electrode M through the first via structure 3071b; the channel region T3c of the driving transistor T3 is electrically connected to the spacer 322a through the first via structure 3071c, and is electrically connected to the second electrode plate Cb through the first via structure 3071d; the channel region T1c of the switching transistor T1 is electrically connected to the second connection structure 3042 through the first via structure 3071e, and is electrically connected to the third connection structure 3043 through the first via structure 3071f.

[0216] For example, with reference to Figures 30 to 32 , in the display panel 30, the first connection structure 3041 is electrically connected to the initialization signal line 3011 located on the first metal layer 301 through the second via structure 3072a and the second via structure 3072b. The spacer 322a is electrically connected to the first portion 3012b of the first power supply voltage signal line 3012a through the second via structure 3072c, and the spacer 322b is electrically connected to the third portion 3012d of the first power supply voltage signal line 3012a through the second via structure 3072d. The second connection electrode K is electrically connected to the first electrode plate Ca through the second via structure 3072e. The third connection structure 3043 is electrically connected to the data line 3013 through the second via structure 3072f.

[0217] For example, referring to Figures 30 to 32 , in the display panel 30 , the gate T2g of the sensing transistor T2 extends in the second direction Y to be directly electrically connected to the first gate line 321 or formed integrally therewith. The gate T1g of the switching transistor T1 extends in a direction opposite to the second direction Y to be directly electrically connected to the second gate line 323 or formed integrally therewith. Furthermore, the first gate line 321 connected to the gate T2g of the sensing transistor T2 and the second gate line 323 connected to the gate T1g of the switching transistor T1 are located on different sides of the spacer 322 in the second direction Y.

[0218] For example, referring to Figures 30 to 32 , the orthographic projection of the first connection structure 3041 on the base substrate 31 is located within the orthographic projection of the initialization signal line 3011 on the base substrate 31. The orthographic projection of the third connection structure 3043 on the base substrate 31 and the orthographic projection of the second connection structure 3042 on the base substrate 31 do not overlap with the orthographic projection of the first metal layer 301 on the base substrate 31. The orthographic projections of the spacers 322a and 322b on the base substrate 31 are located within the orthographic projection of the power supply voltage signal line 3012 on the base substrate 31.

[0219] For example, in FIG30 , a spacer 322 a and a spacer 322 b located in the second metal layer 303 are respectively located between the sensing transistor T2 and the first gate line 321 and the second gate line 323 located on either side thereof in the second direction Y. The spacer 322 b can shield the coupling between the first source / drain electrode T2a of the sensing transistor T2 and the first gate line 321. The first source / drain electrode T2a of the sensing transistor T2 is located in the second metal layer 303, and the power supply voltage signal line 3012 is located in the first metal layer 301. The spacer 322 b located in the second metal layer 304 between the first gate line 321 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 via a second via structure 3072 d. The spacer 322 a located in the second metal layer 303 between the second gate line 323 and the sensing transistor T2 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 via a second via structure 3072 c.

[0220] It should be noted that changes in the voltage of the first connection electrode M will cause changes in the voltage of the second connection electrode K. During the data writing phase, it is desirable for the voltage of the first connection electrode M to be more stable. However, during the lighting phase, a voltage rise in the first connection electrode M is normal. During the lighting phase, the rise in the voltage of the second connection electrode K is caused by coupling with the voltage rise of the first connection electrode M. At this time, the second connection electrode K and the power supply voltage signal line 3012 act as a capacitor, and the storage capacitor Cst is also a capacitor. During the coupling process, there is a capacitive voltage divider, so the voltage rise of the second connection electrode K is not as high as the voltage rise of the first connection electrode M. During the data writing phase, it is desirable for the voltage of the first connection electrode M to be more stable. Therefore, a spacer 322 is used to protect and shield the first connection electrode M to reduce the jump voltage. The above design allows the spacer 322 to be provided between the first connection electrode M and the first gate line 321, and the first connection electrode M is formed in the second metal layer 303, disposed on the same layer as the first gate line 321. The shielding effect of the spacer 322 can extend the life of the organic light-emitting diode display device. The sensing transistor T2 and the first connection electrode M connected thereto have spacers 322 on both sides of the second direction Y, which respectively shield the influence of the first gate line 321 and the second gate line 323 on the voltage change of the first connection electrode M. That is, due to the presence of the spacers 322, no parasitic capacitance is formed between the first gate line 321 or the second gate line 323 and the first connection electrode M.

[0221] For example, with reference to FIG30 , the orthographic projection of the first source-drain electrode T2 a of the sensing transistor T2 on the substrate 31 is spaced apart from the orthographic projection of the power supply voltage signal line 3012 on the substrate 31 , that is, the first source-drain electrode T2 a of the sensing transistor T2 is located at the recess between the second portion 3012 c and the initialization signal line 3011 .

[0222] For example, in the cross-sectional structural schematic diagram shown in Figure 33, the display panel 30 also includes a buffer layer 305 arranged on the side of the first metal layer 301 away from the base substrate 31, a gate insulation layer 306 and an interlayer insulation layer 307 arranged between the active layer 302 and the second metal layer 303, and a passivation layer 308 and a planarization layer 309 arranged on the side of the second metal layer 303 away from the base substrate 31, a first via structure 3071 is provided in the interlayer insulation layer 307, and the second metal layer 303 is electrically connected to the active layer 302 through the first via structure 3071; a second via structure 3072 is passed through the interlayer insulation layer 307 and the buffer layer 305, and the second metal layer 303 is electrically connected to the power supply voltage signal line 3012 located in the first metal layer 301 through the second via structure 3072.

[0223] For example, Figure 34 is a schematic diagram of the planar structure of a stack of a first metal layer, an active layer, a second metal layer and a third metal layer included in another display panel provided by at least one embodiment of the present invention, and Figure 35 is a schematic diagram of the planar structure of the stack of the first metal layer and the third metal layer included in the display panel in Figure 34.

[0224] For example, in conjunction with FIG35 , the display panel shown in FIG34 differs from the display panel shown in FIG14 in that the display panel shown in FIG34 further includes a cathode voltage trace 324. The cathode voltage trace 324 includes a first cathode voltage trace 3241 located in the third metal layer 304 between the first gate line 321 and the second gate line 323. The first cathode voltage trace 3241 extends in the first direction X. The cathode voltage trace 324 also includes a second cathode voltage trace 3242 located in the first metal layer 301 between two adjacent data lines 3013. For example, the first cathode voltage trace 3241 extending in the first direction X (transverse direction) and the second cathode voltage trace 3242 extending in the second direction Y (vertical direction) intersect and are electrically connected, thereby reducing voltage drop in medium and large-sized organic light-emitting diode display devices. Furthermore, the second cathode voltage trace 3242, disposed between the two data lines 3013, can also shield against crosstalk between data signals. The first cathode voltage trace 3241 is disposed between the first gate line 321 and the second gate line 323 , and can also shield crosstalk between gate line signals.

[0225] For example, the display panel shown in Figure 34 is different from the display panel shown in Figure 14 in that the third metal layer 304 also includes a power supply voltage signal line 3012 extending in the first direction X, that is, the power supply voltage signal line 3012 also includes a second power supply voltage signal line 3012e extending laterally, and the second power supply voltage signal line 3012e intersects and is electrically connected to the first power supply voltage signal line 3012a, which can reduce the voltage drop of medium and large-sized organic light-emitting diode display devices.

[0226] For example, a first via structure 3071, a second via structure 3072, and a third via structure 3073 are shown in FIG34. For example, eight first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e1, 3071e2, 3071f1, and 3071f2), eight second via structures 3072 (3072a, 3072b, 3072c, 3072d, 3072e, 3072f, 3072g, and 3072h), and four third via structures 3073 (3073a, 3073b2, 3073b2, and 3073c) are shown at a position corresponding to one sub-pixel in FIG34.

[0227] For example, the difference between the above-mentioned via structures corresponding to the display panel shown in Figure 34 and the display panel shown in Figure 14 is that the display panel shown in Figure 34 has two more second via structures, namely the second via structure 3072g and the second via structure 3072h. The layer structure connected by the other second via structures, the first via structure and the third via structure can be found in the above-mentioned description of Figure 14 and will not be repeated here.

[0228] For example, in FIG34 , the second power supply voltage signal line 3012e is electrically connected to the first power supply voltage signal line 3012a located on the first metal layer 301 through the second via structure 3072g. The first cathode voltage trace 3241 is electrically connected to the second cathode voltage trace 3242 located on the first metal layer 301 through the second via structure 3072h, thereby further reducing the resistance between the first metal layer 301 and the third metal layer 304.

[0229] For example, the positional relationship of the structures shown in FIG35 , such as the sensing transistor T2, the driving transistor T3, the switching transistor T1, the first gate line 321, the second gate line 323, the storage capacitor Cst, the first connection electrode M, the spacer 322, the second connection electrode K, the initialization signal line 3011, the power supply voltage signal line 3012, the first electrode Ca and the data line 3013, the channel region T2c of the sensing transistor T2, the channel region T3c of the driving transistor T3, the channel regions T1c of the two switching transistors T1, the gate T2g of the sensing transistor T2, the gate T3g of the driving transistor T3, the gate T1g of the switching transistor T1 and the second electrode Cb, can be referred to the relevant description regarding FIG14 above and will not be repeated here.

[0230] For example, Figure 36 is a schematic diagram of the planar structure of a stack of a first metal layer, an active layer, a second metal layer, and a third metal layer, including another display panel provided by at least one embodiment of the present invention. Figure 37 is a schematic diagram of the cross-sectional structure of the display panel shown in Figure 36 , taken along a second direction, along which a second cathode voltage trace is cut. Figure 38 is a schematic diagram of the cross-sectional structure of the display panel shown in Figure 37 with a cathode and a pixel defining layer added. Figure 39 is a schematic diagram of the cross-sectional structure of the display panel shown in Figure 36 with an organic light-emitting diode added.

[0231] For example, the display panel shown in FIG36 differs from the display panel shown in FIG34 in that the first cathode voltage trace 3241 includes a three-layer stacked structure. In conjunction with FIG36 and FIG37 , the second cathode voltage trace 3242 includes a second cathode voltage trace first sublayer 3242a located on the first metal layer 301, a second cathode voltage trace second sublayer 3242b located on the second metal layer 303, and a second cathode voltage trace third sublayer 3242c located on the third metal layer 304. The second cathode voltage trace first sublayer 3242a and the second cathode voltage trace third sublayer 3242c are electrically connected via a fourth via structure 3074. The second cathode voltage trace first sublayer 3242a and the second cathode voltage trace third sublayer 3242c are electrically connected at two locations, respectively, via a fourth via structure 3074a and a fourth via structure 3074b. The second sublayer 3242b of the second cathode voltage trace and the third sublayer 3242c of the second cathode voltage trace are electrically connected through the fifth via structure 3075. The second sublayer 3242b of the second cathode voltage trace and the third sublayer 3241c of the second cathode voltage trace are electrically connected at two locations through the fifth via structure 3075a and the fifth via structure 3075b respectively, so that the resistance of the second cathode voltage trace can be reduced.

[0232] For example, a first via structure 3071 , a second via structure 3072 , and a third via structure 3073 are shown in FIG. 36 . For example, in FIG36 , eight first via structures 3071 (3071a, 3071b, 3071c, 3071d, 3071e1, 3071e2, 3071f1, and 3071f2), seven second via structures 3072 (3072a, 3072b, 3072c, 3072d, 3072e, 3072f, 3072g, and 3072j), four third via structures 3073 (3073a, 3073b2, 3073b2, and 3073c), two fourth via structures 3074 (3074a and 3074b), and two fifth via structures 3075 (3075a and 3075b) are shown at the position corresponding to one sub-pixel. Except for the fourth via structure 3074 and the fifth via structure 3075 , the relationship between other via structures and layer structures can be found in the above description of FIG. 34 , which will not be repeated here.

[0233] For example, as shown in FIG39 , the display panel also includes an organic light-emitting diode (OLED). For example, the OLED may comprise three luminescent materials (R, G, and B) deposited in corresponding pixel regions, or may comprise a single luminescent material, such as a blue OLED luminescent material and device combined with a photoluminescent quantum dot material. The OLED includes an anode 312, a light-emitting functional layer 313, and a cathode 311. The light-emitting functional layer 313 is disposed within the opening defined by the pixel defining layer 310. Any of the second cathode voltage trace first sublayer 3242a, the second cathode voltage trace second sublayer 3242b, and the second cathode voltage trace third sublayer 3242c is electrically connected to the anode 312 via a sixth via structure 3076. For example, in the cross-sectional view shown in FIG39 , the second cathode voltage trace third sublayer 3242c is electrically connected to the anode 312 via the sixth via structure 3076, thereby reducing the step difference of the anode 312.

[0234] For example, as shown in FIG39 , the display panel 30 further includes a buffer layer 305 disposed on a side of the first metal layer 301 away from the base substrate 31. The buffer layer 305 is formed as a single layer on the base substrate 31. A first sublayer 3242a of the second cathode voltage trace is shown on the first metal layer 301. A gate insulating layer 306 is disposed between the active layer 302 and the second metal layer 303, and an interlayer insulating layer 307 is disposed between the second metal layer 303 and the third metal layer 304. A passivation layer 308, a planarization layer 309, and a pixel defining layer 310 are sequentially disposed on the side of the third metal layer 304 away from the base substrate 31. The interlayer insulating layer 307, the passivation layer 308, and the planarization layer 309 are also formed as a single layer.

[0235] For example, FIG38 shows that the cathode 311 is directly electrically connected to the third metal layer 304, which can also reduce the cathode step.

[0236] 39 , the active layer 302 may be made of low-temperature polysilicon or an oxide semiconductor such as IGZO. The first metal layer 301 , the second metal layer 303 , and the third metal layer 304 may be made of copper, aluminum, molybdenum, or alloys thereof.

[0237] For example, Figure 40 is a schematic diagram of the planar structure of a stack of a first metal layer, an active layer, a second metal layer and a third metal layer included in another display panel provided by at least one embodiment of the present invention, and Figure 41 is a schematic diagram of the cross-sectional structure of the display panel shown in Figure 40. As shown in Figures 40 and 41, the display panel also includes an encapsulation layer 314 arranged on the organic light-emitting diode, a quantum dot layer 315 arranged on the encapsulation layer 314, and a protective layer 316 arranged on the side of the quantum dot layer 315 away from the base substrate 31, wherein the quantum dot layer 315 is configured to process the light emitted from the organic light-emitting diode to improve the purity of the emitted light and make the mixed light more uniform.

[0238] For example, other structures of the display panel shown in FIG40 can be found in the relevant description of the above embodiment and will not be repeated here.

[0239] For example, FIG42 is a block diagram of a display device provided by at least one embodiment of the present invention. As shown in FIG42 , the display device includes any of the display panels described above, and the display device 200 includes a display panel 30. For example, the display panel 100 can be the display panel provided by any embodiment of the present invention.

[0240] For example, the display device 200 may be a display device having a display function. For example, the display device 200 may be a monitor, an OLED display panel, an OLED TV, a liquid crystal display panel, a liquid crystal display TV, a QLED display panel, a QLED TV, an electronic paper, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigation system, or any other product or component having a display function and a touch function.

[0241] A display panel and a display device provided by at least one embodiment of the present invention have at least one of the following beneficial technical effects:

[0242] (1) In at least one embodiment of the present invention, a display panel is provided, wherein a spacer located in the third metal layer is provided between the sensing transistor and the first gate line and the second gate line located on both sides of the sensing transistor in the second direction, respectively. The spacer can shield the coupling between the first source-drain electrode of the sensing transistor and the first gate line.

[0243] (2) In the display panel provided by at least one embodiment of the present invention, the switching transistor is two thin film transistors connected in parallel, one of which is arranged at a position close to the second gate line on the upper side, and the other is arranged at a position close to the first gate line on the lower side, that is, they are arranged on both sides of the first connecting electrode in the second direction, and at the same time, the length of a portion of the first electrode plate of the storage capacitor in the second direction is reduced. This design can increase the channel width-to-length ratio and driving current of the switching transistor, thereby facilitating the driving of a high-resolution display panel and reducing the charging time.

[0244] (3) In the display panel provided by at least one embodiment of the present invention, a portion of the first metal layer is removed below the first source-drain electrode of the sensing transistor, thereby reducing parasitic capacitance. That is, the power supply voltage signal line is narrowed at positions corresponding to the first source-drain electrode and the first connection electrode of the sensing transistor, thereby reducing the overlapping area and parasitic capacitance between the power supply voltage signal line and the first source-drain electrode of the sensing transistor.

[0245] (4) In the display panel provided by at least one embodiment of the present invention, the second cathode voltage trace includes a first sublayer of the second cathode voltage trace located in the first metal layer, a second sublayer of the second cathode voltage trace located in the second metal layer, and a third sublayer of the second cathode voltage trace located in the third metal layer, so that the resistance can be reduced. Any one of the first sublayer of the second cathode voltage trace, the second sublayer of the second cathode voltage trace, and the third sublayer of the second cathode voltage trace is electrically connected to the anode through the sixth via structure, so that the anode step difference can be reduced.

[0246] There are a few points to note:

[0247] (1) The drawings of the embodiments of the present invention only relate to the structures related to the embodiments of the present invention. Other structures may refer to conventional designs.

[0248] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present invention, the thickness of layers or regions are exaggerated or reduced, that is, these drawings are not drawn according to the actual scale.

[0249] (3) In the absence of conflict, the embodiments of the present invention and the features therein may be combined with each other to form new embodiments.

[0250] The above description is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A display panel, comprising: substrate substrate; A pixel circuit is provided on the substrate, wherein the pixel circuit comprises a sensing transistor, a driving transistor, a first gate line and a second gate line, wherein: The first source-drain electrode of the sensing transistor and the first source-drain electrode of the driving transistor are electrically connected via a first connecting electrode; The first gate line and the second gate line extend in a first direction, and in a second direction intersecting the first direction, a spacer is provided between the first connecting electrode and the first gate line, and between the first connecting electrode and the second gate line, and the first connecting electrode, the first gate line, the second gate line and the spacer are provided in the same layer.

2. The display panel according to claim 1, further comprising a switching transistor and a storage capacitor disposed on the base substrate, wherein: The first source-drain electrode of the switch transistor and the gate of the drive transistor are connected via a second connection electrode, the first plate of the storage capacitor is connected to the second connection electrode, and the second plate of the storage capacitor is connected to the first connection electrode.

3. The display panel according to claim 2, further comprising a first metal layer, an active layer, a second metal layer and a third metal layer sequentially stacked on the base substrate, wherein: The first metal layer includes an initialization signal line extending in the second direction, a power supply voltage signal line extending at least partially in the second direction, the first electrode plate, and a data line; The active layer includes a channel region of the sensing transistor, a channel region of the driving transistor, and a channel region of the switching transistor; The second metal layer includes a gate of the sensing transistor, a gate of the driving transistor, a gate of the switching transistor and the second electrode plate; The third metal layer includes the first connection electrode, the spacer, the second gate line extending in the first direction, and the first gate line.

4. The display panel according to claim 3, wherein: The gate of the sensing transistor extends in the second direction to be electrically connected to the first gate line, the gate of the switching transistor extends in a direction opposite to the second direction to be electrically connected to the second gate line, and the first gate line connected to the gate of the sensing transistor and the second gate line connected to the gate of the switching transistor are located on different sides of any of the spacers in the second direction.

5. The display panel according to claim 3, wherein: The third metal layer also includes a first connection structure, a second connection structure and a third connection structure extending in the second direction, wherein the orthographic projection of the first connection structure on the substrate is located within the orthographic projection of the initialization signal line on the substrate, the orthographic projection of the second connection structure on the substrate is located within the orthographic projection of the first electrode on the substrate, and the orthographic projection of the third connection structure on the substrate is located within the orthographic projection of the data line on the substrate.

6. The display panel according to claim 5, further comprises a buffer layer arranged on a side of the first metal layer away from the base substrate, a gate insulation layer arranged between the active layer and the second metal layer, an interlayer insulation layer arranged between the second metal layer and the third metal layer, and a passivation layer and a planarization layer arranged on a side of the third metal layer away from the base substrate.

7. The display panel according to claim 6, wherein: A first via structure and a third via structure are provided in the interlayer insulating layer, the third metal layer is electrically connected to the active layer through the first via structure, and the third metal layer is electrically connected to the second metal layer through the third via structure; A second via structure penetrates the interlayer insulating layer and the buffer layer, and the third metal layer is electrically connected to the first metal layer through the second via structure.

8. The display panel according to claim 7, wherein: The first connection structure is electrically connected to the initialization signal line through the second via structure, and is electrically connected to the second source-drain electrode of the sensing transistor through the first via structure; The second connection structure is electrically connected to the first source-drain electrode of the switch transistor through the first via structure, and is electrically connected to the second electrode plate through the third via structure; The third connection structure is electrically connected to the data line through the second via structure, and is electrically connected to the second source-drain electrode of the switch transistor through the first via structure.

9. The display panel according to any one of claims 4 to 8, wherein: At least a portion of the third metal layer has an overlapping area with the first metal layer and the second metal layer, so as to form the storage capacitor between the first metal layer and the second metal layer and form a capacitor structure between the second metal layer and the third metal layer.

10. The display panel according to claim 3, wherein: An orthographic projection of the first source-drain electrode of the sensing transistor on the substrate overlaps with an orthographic projection of the power supply voltage signal line on the substrate.

11. The display panel according to claim 3, wherein: The power supply voltage signal line includes a first power supply voltage signal line extending in the second direction, the first power supply voltage signal line includes a first part, a second part and a third part extending in the second direction and connected in sequence, the first part and the third part have the same width in the first direction, the second part has a width in the first direction that is smaller than the first part in the first direction, and one end of the second part in the second direction is connected to an edge of the first part close to the third part and away from the initialization signal line, and the other end of the second part in the second direction is connected to an edge of the third part close to the first part and away from the initialization signal line.

12. The display panel according to claim 11, wherein: An orthographic projection of the first source-drain electrode of the sensing transistor on the substrate and an orthographic projection of the second portion of the power supply voltage signal line on the substrate are spaced apart from each other.

13. The display panel according to claim 11, wherein: The first electrode plate includes a first electrode plate sub-block and a second electrode plate sub-block connected to each other in the first direction, the second metal layer includes a first extension portion and a second extension portion extending from a portion of the second electrode plate corresponding to the second electrode plate sub-block in the second direction, and two second connecting electrodes are respectively connected to the first extension portion and the second extension portion.

14. The display panel according to claim 13, further comprising an organic light emitting diode, wherein: A st is the area of ​​the storage capacitor, d gc is the minimum distance between the first gate line and the storage capacitor, L c is the length of the side of the first plate sub-block adjacent to the first gate line, W g is the width of the first gate line in the second direction, THK ILD is the thickness of the interlayer insulating layer corresponding to the storage capacitor.

15. The display panel according to claim 14, wherein: V gON is the turn-on voltage of the second gate line, V gOFF is the off voltage of the second gate line, V oled is the voltage across the organic light emitting diode, and γ is an optical constant.

16. The display panel according to claim 15, wherein: The storage capacitor is a three-layer structure formed by the first metal layer, the second metal layer and the third metal layer. THK BUF is the thickness of the buffer layer between the first metal layer and the second metal layer in the storage capacitor.

17. The display panel according to claim 16, wherein:

18. The display panel according to any one of claims 14 to 17, wherein: W DD is the length of the spacer between the first gate line and the first connecting electrode in the second direction, d gd is the minimum distance between the first gate line and the spacer between the first gate line and the first connecting electrode, d sd is a minimum distance between the first connecting electrode and the spacer between the first gate line and the first connecting electrode.

19. The display panel according to any one of claims 14 to 17, wherein: L c is the length of the side of the first plate sub-block adjacent to the first gate line, L p is the sum of the lengths of the first plate sub-block and the second plate sub-block in the first direction, R l is the ratio of the length of the side of the first plate sub-block adjacent to the first gate line to the sum of the lengths of the first plate sub-block and the second plate sub-block in the first direction.

20. The display panel according to any one of claims 14 to 17, wherein: W c is the width of the storage capacitor in the first direction, and Pitch is the width of a sub-pixel in the first direction.

21. The display panel according to claim 2, further comprising a first metal layer, an active layer, and a second metal layer sequentially stacked on the base substrate, wherein: The first metal layer includes an initialization signal line extending in the second direction, a power supply voltage signal line extending at least partially in the second direction, the first electrode plate, and a data line; The active layer includes a channel region of the sensing transistor, a channel region of the driving transistor, and a channel region of the switching transistor; The second metal layer includes a gate of the sensing transistor, a gate of the driving transistor, a gate of the switching transistor, the second electrode plate, the first connecting electrode, the spacer, the second gate line extending in the first direction, and the first gate line.

22. The display panel according to claim 21, wherein: The gate of the switching transistor is electrically connected to the second gate line, the gate of the sensing transistor is electrically connected to the first gate line, and the second gate line connected to the gate of the switching transistor and the first gate line connected to the gate of the sensing transistor are located on different sides of the first electrode plate in the second direction, and in the second direction, the second connecting electrode is between the first connecting electrode and the second gate line connected to the gate of the switching transistor.

23. The display panel according to claim 1, further comprising a switching transistor disposed on the base substrate, wherein: The first source-drain electrode of the switch transistor and the gate of the drive transistor are connected via a second connection electrode.

24. The display panel according to claim 23, further comprising a first metal layer, an active layer, a second metal layer and a third metal layer sequentially stacked on the base substrate, wherein: The first metal layer includes an initialization signal line, a power supply voltage signal line and a data line extending in the second direction, and a light shielding portion; The active layer includes a channel region of the sensing transistor, a channel region of the driving transistor, and a channel region of the switching transistor; The second metal layer includes a gate of the sensing transistor, a gate of the driving transistor and a gate of the switching transistor; The third metal layer includes the first connection electrode, the spacer, the second gate line extending in the first direction, and the first gate line.

25. The display panel according to claim 24, wherein: The third metal layer also includes a first connection structure and a second connection structure extending in the second direction, the orthographic projection of the first connection structure on the base substrate is located within the orthographic projection of the initialization signal line on the base substrate, and the orthographic projection of the second connection structure on the base substrate is located within the orthographic projection of the data line on the base substrate.

26. The display panel according to claim 25, further comprises a buffer layer arranged on a side of the first metal layer away from the base substrate, a gate insulation layer arranged between the active layer and the second metal layer, an interlayer insulation layer arranged between the second metal layer and the third metal layer, and a passivation layer and a planarization layer arranged on a side of the third metal layer away from the base substrate.

27. The display panel according to claim 26, wherein: A first via structure is provided in the interlayer insulating layer, and the third metal layer is electrically connected to the active layer through the first via structure; A second via structure penetrates the interlayer insulating layer and the buffer layer, and the third metal layer is electrically connected to the power supply voltage signal line through the second via structure.

28. The display panel according to any one of claims 25 to 27, wherein: A storage capacitor is formed between the third metal layer and the second metal layer.

29. The display panel according to claim 1, further comprising a switching transistor and a storage capacitor disposed on the base substrate, wherein: The first source-drain electrode of the switch transistor and the first electrode plate of the storage capacitor are connected via a second connecting electrode.

30. The display panel according to claim 29, further comprising a first metal layer, an active layer, and a second metal layer sequentially stacked on the base substrate, wherein: The first metal layer includes an initialization signal line, a power supply voltage signal line and a data line extending in the second direction; the active layer includes a channel region of the sensing transistor, a channel region of the driving transistor, a channel region of the switching transistor and the first electrode plate; the second metal layer includes a gate of the sensing transistor, a gate of the driving transistor and a gate of the switching transistor, the first connecting electrode, the spacer, a second electrode plate of the storage capacitor, the second gate line extending in the first direction and the first gate line.

31. The display panel according to claim 30, wherein: An edge of the first electrode plate of the storage capacitor on a side close to the second gate line extends in the first direction to just above the power supply voltage signal line.

32. The display panel according to claim 30, wherein: The second metal layer further includes a first connection structure extending in the second direction, and an orthographic projection of the first connection structure on the base substrate is located within an orthographic projection of the initialization signal line on the base substrate.

33. The display panel according to claim 32, further comprising a buffer layer disposed on a side of the first metal layer away from the base substrate, a gate insulating layer and an interlayer insulating layer disposed between the active layer and the second metal layer, and a passivation layer and a planarization layer disposed on a side of the second metal layer away from the base substrate, wherein: A first via structure is provided in the interlayer insulating layer, and the second metal layer is electrically connected to the active layer through the first via structure; A second via structure penetrates the interlayer insulating layer and the buffer layer, and the second metal layer is electrically connected to the power voltage signal line through the second via structure.

34. The display panel according to claim 11, further comprising a cathode voltage trace, wherein: The cathode voltage routing includes a first cathode voltage routing extending in the first direction and a second cathode voltage routing extending in the second direction, and the first cathode voltage routing and the second cathode voltage routing intersect; The power supply voltage signal line further includes a second power supply voltage signal line extending in the first direction, and the first power supply voltage signal line and the second power supply voltage signal line intersect each other.

35. The display panel according to claim 34, wherein: The second cathode voltage routing includes a three-layer stacked structure, and the second cathode voltage routing includes a second cathode voltage routing first sublayer located in the first metal layer, a second cathode voltage routing second sublayer located in the second metal layer, and a second cathode voltage routing third sublayer located in the third metal layer, the second cathode voltage routing first sublayer and the second cathode voltage routing third sublayer are electrically connected through a fourth via structure, and the second cathode voltage routing second sublayer and the second cathode voltage routing third sublayer are electrically connected through a fifth via structure.

36. The display panel according to claim 35 further includes an organic light emitting diode, wherein the organic light emitting diode includes an anode, and any one of the first sublayer of the second cathode voltage routing, the second sublayer of the second cathode voltage routing, and the third sublayer of the second cathode voltage routing is electrically connected to the anode through a sixth via structure.

37. The display panel according to claim 36, wherein: The third sublayer of the first cathode voltage wiring is electrically connected to the anode through the sixth via structure.

38. The display panel according to claim 37, further comprising an encapsulation layer disposed on the organic light emitting diode, and a quantum dot layer disposed on the encapsulation layer, wherein: The quantum dot layer is configured to process light emitted from the organic light emitting diode.

39. A display device comprising: The display panel according to any one of claims 1 to 38.

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