Balance-type amplifier

Abstract

Provided is a balance-type amplifier configured to comprise: a signal splitting circuit (2) that splits a signal to be amplified into two signals, outputs a first signal as one signal after the splitting into the two signals, and outputs a second signal as the other signal after the splitting into the two signals; a first amplifier (3) that amplifies the first signal output from the signal splitting circuit (2); a second amplifier (6) that amplifies the second signal output from the signal splitting circuit (2); and a combiner circuit (7) that combines the first signal amplified by the first amplifier (3) and the second signal amplified by the second amplifier (6) with each other. Moreover, the first amplifier (3) of the balance-type amplifier has a first matching circuit for matching an output impedance of the first amplifier (3) to a first impedance different from an impedance of a load connected to an output side of the combiner circuit (7). The second amplifier (6) of the balance-type amplifier has a second matching circuit for matching an output impedance of the second amplifier (6) to a second impedance different from the impedance of the load. Any one impedance of the first impedance or the second impedance is higher than the impedance of the load and the other impedance is lower than the impedance of the load.

Description

Balanced Amplifier

[0001] The present disclosure relates to a balanced amplifier.

[0002] Amplifiers for wireless communication include, for example, balanced amplifiers that include two amplifiers. Patent Document 1, for example, discloses a high-frequency circuit that includes a 90° hybrid circuit, a first amplifier, a second amplifier, a 90° phase shifter, and an isolator module. The 90° hybrid circuit splits a high-frequency signal into two and outputs the first high-frequency signal to the first amplifier as one of the split signals, and outputs the second high-frequency signal to the second amplifier as the other split signal. The first amplifier amplifies the first high-frequency signal and outputs the amplified first high-frequency signal to the 90° phase shifter. The 90° phase shifter delays the phase of the amplified first high-frequency signal by 90° and outputs the phase-shifted first high-frequency signal to the isolator module. The second amplifier amplifies the second high-frequency signal and outputs the amplified second high-frequency signal to the isolator module. The isolator module combines the first high-frequency signal output from the 90° phase shifter and the second high-frequency signal output from the second amplifier, and outputs the combined signal of the first and second high-frequency signals to a load.

[0003] JP 2013-236144 A

[0004] The high-frequency circuit disclosed in Patent Document 1 has a problem in that the output power and efficiency may both decrease due to changes in the impedance of the load connected to the output side of the isolator module.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a balanced amplifier that can suppress a decrease in both output power and efficiency even when the load impedance changes.

[0006] A balanced amplifier according to the present disclosure includes a signal distribution circuit that divides a signal to be amplified into two and outputs a first signal as one of the divided signals and a second signal as the other of the divided signals, a first amplifier that amplifies the first signal output from the signal distribution circuit, a second amplifier that amplifies the second signal output from the signal distribution circuit, and a combiner circuit that combines the first signal amplified by the first amplifier and the second signal amplified by the second amplifier. The first amplifier of the balanced amplifier includes a first matching circuit for matching the output impedance of the first amplifier to a first impedance different from the impedance of a load connected to the output side of the combiner circuit. The second amplifier of the balanced amplifier includes a second matching circuit for matching the output impedance of the second amplifier to a second impedance different from the impedance of the load. One of the first impedance and the second impedance is higher than the impedance of the load, and the other impedance is lower than the impedance of the load.

[0007] According to the present disclosure, even if the impedance of the load changes, it is possible to suppress a decrease in both the output power and the efficiency.

[0008] 2A is a configuration diagram showing a balanced amplifier according to a first embodiment. FIG. 2B is a configuration diagram showing the inside of a first amplifier 3, and FIG. 3A is a configuration diagram showing the inside of a second amplifier 6. FIG. 3A is a configuration diagram showing a load impedance Z ０ 3B is a Smith chart showing the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 after the load impedance Z changes from 50 Ω to 25 Ω. ０ 4A is a Smith chart showing the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 after the load impedance Z is changed from 50Ω to 75Ω. ０ 4A is a Smith chart showing the output impedance of the first amplifier and the output impedance of the second amplifier in a typical balanced amplifier after the load impedance Z changes from 50 Ω to 25 Ω. ０1 is a Smith chart showing the output impedance of a first amplifier and the output impedance of a second amplifier in a general balanced amplifier after the load impedance of the first amplifier has changed from 50Ω to 75Ω. FIG. 2 is a Smith chart showing the load impedance dependency of efficiency in the balanced amplifier shown in FIG. 1 and a general balanced amplifier as contour lines. FIG. 3 is a Smith chart showing the load impedance dependency of output power in the balanced amplifier shown in FIG. 1 and a general balanced amplifier as contour lines. FIG. 4 is a configuration diagram showing a balanced amplifier according to a second embodiment. FIG. 5 is a configuration diagram showing a balanced amplifier according to a third embodiment. FIG. 6 is a configuration diagram showing a balanced amplifier according to a fourth embodiment. FIG. 7 is a configuration diagram showing a balanced amplifier according to a fifth embodiment. FIG. 8 is a configuration diagram showing a balanced amplifier according to a sixth embodiment. FIG. 9 is a configuration diagram showing a balanced amplifier according to a seventh embodiment.

[0009] In order to explain the present disclosure in more detail, embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0010] Embodiment 1. Fig. 1 is a configuration diagram showing a balanced amplifier according to embodiment 1. The balanced amplifier shown in Fig. 1 includes a signal input terminal 1, a signal distribution circuit 2, a first amplifier 3, an output phase shift circuit 4, an input phase shift circuit 5, a second amplifier 6, a combining circuit 7, and a signal output terminal 8.

[0011] A high-frequency signal is applied to the signal input terminal 1 as a signal to be amplified. The signal distribution circuit 2 has a first terminal 2a, a second terminal 2b, and a third terminal 2c. The high-frequency signal applied to the signal input terminal 1 is applied to the first terminal 2a of the signal distribution circuit 2. The signal distribution circuit 2 distributes the high-frequency signal into two. The signal distribution circuit 2 outputs the first signal from the second terminal 2b to the first amplifier 3 as one of the two signals after distribution, and outputs the second signal from the third terminal 2c to the input phase circuit 5 as the other of the two signals after distribution.

[0012] The first amplifier 3 is realized by, for example, a semi-discrete amplifier enclosed in a high-frequency package or an MMIC (Monolithic Microwave Integrated Circuit) amplifier configured on a semiconductor substrate. The first amplifier 3 calculates the output impedance of the first amplifier 3 by dividing the output impedance of the first amplifier 3 by the impedance of a load connected to the output side of the combining circuit 7 (hereinafter referred to as "load impedance Z ０ In the balanced amplifier shown in FIG. 1 , the first impedance is a load impedance Z ０ The first amplifier 3 amplifies the first signal output from the second terminal 2b of the signal distribution circuit 2. The first amplifier 3 outputs the amplified first signal to the output phase circuit 4.

[0013] One end of the output phase shift circuit 4 is connected to the output side of the first amplifier 3. The other end of the output phase shift circuit 4 is connected to a first terminal 7a, which is an input side terminal of the combiner circuit 7. The output phase shift circuit 4 is a circuit having an electrical length of 90 degrees. The first signal amplified by the first amplifier 3 passes through the output phase shift circuit 4, causing the phase of the amplified first signal to be delayed by 90 degrees. The first signal phase-shifted by the output phase shift circuit 4 is provided to the first terminal 7a of the combiner circuit 7.

[0014] One end of the input phase shift circuit 5 is connected to the third terminal 2c of the signal distribution circuit 2. The other end of the input phase shift circuit 5 is connected to the input side of the second amplifier 6. The input phase shift circuit 5 changes the phase of the second signal output from the third terminal 2c of the signal distribution circuit 2 so that the phase of the amplified first signal and the phase of the amplified second signal are in phase at the combining point in the combining circuit 7 of the first signal amplified by the first amplifier 3 and the second signal amplified by the second amplifier 6. The third terminal 7c of the combining circuit 7 corresponds to the combining point of the combining circuit 7.

[0015] The second amplifier 6 is realized by, for example, a semi-discrete amplifier enclosed in a high-frequency package or an MMIC type amplifier formed on a semiconductor substrate. The second amplifier 6 has an output impedance that is a load impedance Z ０ In the balanced amplifier shown in FIG. 1 , the second impedance is a load impedance Z ０ The second amplifier 6 amplifies the second signal output from the input phase shift circuit 5. The second amplifier 6 outputs the amplified second signal to a second terminal 7b, which is a terminal on the input side of the combining circuit 7.

[0016] The combiner circuit 7 is realized by, for example, a 90-degree hybrid circuit. The combiner circuit 7 has a first terminal 7a, a second terminal 7b, a third terminal 7c, and a fourth terminal 7d. The first terminal 7a and the second terminal 7b are input terminals, the third terminal 7c is an output terminal, and the fourth terminal 7d is an isolation terminal grounded via a resistor. The first terminal 7a of the combiner circuit 7 is supplied with a first signal output from the output phase circuit 4. The second terminal 7b of the combiner circuit 7 is supplied with a second signal amplified by the second amplifier 6. The combiner circuit 7 combines the first signal and the second signal. The combiner circuit 7 outputs a combined signal of the first signal and the second signal from the third terminal 7c to a signal output terminal 8. A load (not shown) is connected to the signal output terminal 8. A load impedance Z ０ may vary from, for example, 50 Ω.

[0017] 2A is a configuration diagram showing the inside of the first amplifier 3. The first amplifier 3 shown in Fig. 2A includes an input matching circuit 3a, a first amplifying element 3b, and an output matching circuit 3c. One end of the input matching circuit 3a is connected to the second terminal 2b of the signal distribution circuit 2. The other end of the input matching circuit 3a is connected to the input terminal of the first amplifying element 3b. The input matching circuit 3a matches the input impedance of the first amplifying element 3b to the input impedance of the signal input terminal 1.

[0018] The input terminal of the first amplifying element 3b is connected to the other end of the input matching circuit 3a. The output terminal of the first amplifying element 3b is connected to one end of the output matching circuit 3c. The first amplifying element 3b is realized by, for example, a silicon semiconductor transistor, an LDMOS (Lateral Double Diffused MOS) semiconductor transistor, a gallium arsenide semiconductor transistor, or a gallium nitride semiconductor transistor. The first amplifying element 3b amplifies the first signal that has passed through the input matching circuit 3a. The first amplifying element 3b outputs the amplified first signal to the output matching circuit 3c.

[0019] One end of the output matching circuit 3c is connected to the output terminal of the first amplifying element 3b. The other end of the output matching circuit 3c is connected to one end of the output phase circuit 4. The output matching circuit 3c functions as a first matching circuit and adjusts the output impedance of the first amplifying element 3b to a load impedance Z ０ The load impedance Z is matched to a first impedance that is higher than ０ Since the impedance of the first amplifying element 3b is generally 50Ω, the output matching circuit 3c matches the output impedance of the first amplifying element 3b to a first impedance higher than 50Ω.

[0020] 2B is a configuration diagram showing the inside of the second amplifier 6. The second amplifier 6 shown in FIG. 2B includes an input matching circuit 6a, a second amplifying element 6b, and an output matching circuit 6c. One end of the input matching circuit 6a is connected to the other end of the input phase shift circuit 5. The other end of the input matching circuit 6a is connected to the input terminal of the second amplifying element 6b. The input matching circuit 6a matches the input impedance of the second amplifying element 6b to the input impedance of the signal input terminal 1.

[0021] The input terminal of the second amplifying element 6b is connected to the other end of the input matching circuit 6a. The output terminal of the second amplifying element 6b is connected to one end of the output matching circuit 6c. The second amplifying element 6b is realized by, for example, a silicon semiconductor transistor, an LDMOS semiconductor transistor, a gallium arsenide semiconductor transistor, or a gallium nitride semiconductor transistor. The second amplifying element 6b amplifies the second signal that has passed through the input matching circuit 6a. The second amplifying element 6b outputs the amplified second signal to the output matching circuit 6c.

[0022] One end of the output matching circuit 6c is connected to the output terminal of the second amplifying element 6b. The other end of the output matching circuit 6c is connected to the second terminal 7b of the combining circuit 7. The output matching circuit 6c functions as a second matching circuit and adjusts the output impedance of the second amplifying element 6b to a load impedance Z ０ The load impedance Z is matched to a second impedance that is lower than ０ Since the output impedance of the second amplifying element 6b is generally 50Ω, the output matching circuit 6c matches the output impedance of the second amplifying element 6b to a second impedance lower than 50Ω.

[0023] Next, the operation of the balanced amplifier shown in Fig. 1 will be described. The signal distribution circuit 2 divides a high-frequency signal applied to the signal input terminal 1 into two. The signal distribution circuit 2 outputs a first signal from the second terminal 2b to the first amplifier 3 as one of the divided signals. The signal distribution circuit 2 outputs a second signal from the third terminal 2c to the input phase circuit 5 as the other of the divided signals.

[0024] The first amplifying element 3b of the first amplifier 3 amplifies the first signal output from the second terminal 2b of the signal distribution circuit 2. At this time, the output matching circuit 3c of the first amplifier 3 matches the output impedance of the first amplifying element 3b with the load impedance Z ０ The load impedance Z is matched to a first impedance that is higher than ０is 50Ω, the output matching circuit 3c matches the output impedance of the first amplifying element 3b to a first impedance higher than 50Ω. The first amplifier 3 outputs the amplified first signal to the output phase circuit 4.

[0025] The output phase circuit 4 delays the phase of the first signal amplified by the first amplifier 3 by 90 degrees. The first signal phase-shifted by the output phase circuit 4 is provided to a first terminal 7a of the combiner circuit 7. The phase of the first signal provided to the first terminal 7a of the combiner circuit 7 is further delayed by 90 degrees in the combiner circuit 7. As a result, the phase of the first signal is delayed by a total of 180 degrees, and the first signal delayed by 180 degrees is provided to a third terminal 7c of the combiner circuit 7.

[0026] The input phase circuit 5 changes the phase of the second signal output from the third terminal 2c of the signal distribution circuit 2 so that the phase of the first signal amplified by the first amplifier 3 and the phase of the second signal amplified by the second amplifier 6 are in phase at the third terminal 7c of the combining circuit 7. Specifically, when the phase of the first signal amplified at the third terminal 7c is θ １ , when the input phase circuit 5 is not present, the phase of the amplified second signal at the third terminal 7c is θ ２ , the phase delayed by the input phase circuit 5 is θ ３ If so, the phase θ that the input phase circuit 5 delays is ３ is expressed as, for example, the following formula (1) or formula (2): ３ = 360 - |θ １ +θ ２ | (1) θ ３ = 0 - |θ １ +θ ２ | (2)

[0027] For example, the phase θ of the first signal １ is -180 degrees, and the phase θ of the second signal ２is 0 degrees, the input phase shift circuit 5 has an electrical length that causes a phase change of −180 degrees or a phase change of +180 degrees, so that the phases of the first signal and the second signal are in phase at the third terminal 7c. ３ is expressed as in equation (1) or equation (2). At the third terminal 7c of the combining circuit 7, the phase of the first signal and the phase of the second signal should be in phase, and the phase θ ３ However, it is not limited to those expressed as formula (1) or formula (2).

[0028] The second amplifying element 6b of the second amplifier 6 amplifies the second signal output from the input phase shift circuit 5. At this time, the output matching circuit 6c of the second amplifier 6 matches the output impedance of the second amplifying element 6b with the load impedance Z ０ The load impedance Z is matched to a second impedance that is lower than ０ is 50Ω, the output matching circuit 6c matches the output impedance of the second amplifying element 6b to a second impedance lower than 50Ω. The second amplifier 6 outputs the amplified second signal to the second terminal 7b of the combining circuit 7.

[0029] The first signal output from the output phase circuit 4 is applied to a first terminal 7a of the combiner circuit 7. The second signal amplified by the second amplifier 6 is applied to a second terminal 7b of the combiner circuit 7. The combiner circuit 7 delays the phase of the first signal applied to the first terminal 7a by 90 degrees, and then combines the first and second signals in phase. The combiner circuit 7 outputs a combined signal of the first and second signals from a third terminal 7c via a signal output terminal 8 to a load (not shown).

[0030] Next, the effect of the balanced amplifier shown in FIG. 1 will be described. ０3A is a Smith chart showing the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 after the load impedance Z changes from 50Ω to 25Ω. In FIG. 3A, the circle marks indicate the output impedance of the first amplifier 3, and the square marks indicate the output impedance of the second amplifier 6. FIG. 4A is a Smith chart showing the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 after the load impedance Z changes from 50Ω to 25Ω. ０ 1 is a Smith chart showing the output impedance of the first amplifier and the output impedance of the second amplifier in a typical balanced amplifier after the load impedance Z changes from 50Ω to 25Ω. The typical balanced amplifier corresponds to the high-frequency circuit disclosed in Patent Document 1. The output impedance of the first amplifier in a typical balanced amplifier is ０ The output impedance of the second amplifier in a typical balanced amplifier is matched to the load impedance Z ０ 4A, the circles indicate the output impedance of the first amplifier, and the black squares indicate the output impedance of the second amplifier.

[0031] In a typical balanced amplifier, the load impedance Z ０ As the load impedance Z changes from 50Ω to 25Ω, the output impedance of the first amplifier and the output impedance of the second amplifier change in opposite directions, as shown in FIG. ０ and the output impedance of the second amplifier varies in the same direction as the load impedance Z ０ As a result, the load impedance Z ０ When the load impedance Z changes from 50Ω to 25Ω, the difference between the output impedance of the first amplifier and the output impedance of the second amplifier increases. ０3A, the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 change in the same direction. That is, the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 change in the same direction as the load impedance Z ０ As a result, the load impedance Z ０ Even if the impedance of the first amplifier 3 changes from 50 Ω to 25 Ω, the difference between the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 does not become larger than the difference between the output impedance of the first amplifier and the output impedance of the second amplifier in a typical balanced amplifier.

[0032] Here, the difference between the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 will be specifically described. However, for simplicity of explanation, the explanation will ignore the respective actions of the output matching circuit 3c of the first amplifier 3 and the output matching circuit 6c of the second amplifier 6. Assume that there is a change in the reflection coefficient Γ as a change in output impedance at the signal output terminal of a general balanced amplifier and at the signal output terminal 8 of the balanced amplifier shown in FIG. 1. In a general balanced amplifier, when the reflection coefficient of the first amplifier is Γ, １ , the reflection phase of the first amplifier is θ １ , the reflection coefficient of the second amplifier is Γ ２ , the reflection phase of the second amplifier is θ ２ If this is the case, the balanced amplifier includes a 90-degree hybrid circuit as a combining circuit, and therefore the following equations (3) and (4) hold: Γ １ =Γ ２　　　　　　 (3) θ １ = θ ２ +180 (4) Each of the formulas (3) and (4) expresses the relationship between the reflection coefficient Γ of the first amplifier and the output impedance of the signal output terminal. １ and the reflection coefficient of the second amplifier, Γ ２ This means that the load impedance Z ０As a result of the change in Γ, the difference between the output impedance of the first amplifier and the output impedance of the second amplifier increases. As the difference increases, a loss occurs when the combiner circuit combines the two signals, resulting in a decrease in output power and efficiency. In contrast, the balanced amplifier shown in FIG. 1 is equipped with an output phase shift circuit 4 and an input phase shift circuit 5, and therefore the following equations (5) and (6) hold. Γ １ =Γ ２　　　　　　 (5) θ １ = θ ２　　　　　　 (6) Each of the formulas (5) and (6) expresses the relationship between the reflection coefficient Γ of the first amplifier 3 and the output impedance of the signal output terminal 8 when the output impedance of the signal output terminal 8 changes. １ and the reflection coefficient Γ of the second amplifier 6 ２ This means that the load impedance Z ０ Even if the impedance of the first amplifier 3 changes, the difference between the output impedance of the second amplifier 6 does not increase. Since the difference does not increase, loss when the combiner circuit 7 combines two signals is reduced, resulting in improved output power and efficiency.

[0033] FIG. 3B shows the load impedance Z ０ 3B is a Smith chart showing the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 after the load impedance Z has changed from 50Ω to 75Ω. In FIG. 3B, the circle marks indicate the output impedance of the first amplifier 3, and the square marks indicate the output impedance of the second amplifier 6. FIG. 4B is a Smith chart showing the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 after the load impedance Z has changed from 50Ω to 75Ω. ０ 1 is a Smith chart showing the output impedance of the first amplifier and the output impedance of the second amplifier in a typical balanced amplifier after the load impedance Z ０ The output impedance of the second amplifier in a typical balanced amplifier is matched to the load impedance Z ０4B, the circles indicate the output impedance of the first amplifier, and the squares indicate the output impedance of the second amplifier.

[0034] In a typical balanced amplifier, the load impedance Z ０ As the load impedance Z changes from 50Ω to 75Ω, the output impedance of the first amplifier and the output impedance of the second amplifier change in opposite directions, as shown in FIG. ０ and the output impedance of the second amplifier varies in the same direction as the load impedance Z ０ As a result, the load impedance Z ０ When the load impedance Z changes from 50Ω to 75Ω, the difference between the output impedance of the first amplifier and the output impedance of the second amplifier increases. ０ 3B, the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 change in the same direction. That is, the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 change in the same direction as the load impedance Z ０ As a result, the load impedance Z ０ Even if the impedance of the first amplifier 3 changes from 50 Ω to 75 Ω, the difference between the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 does not become larger than the difference between the output impedance of the first amplifier and the output impedance of the second amplifier in a typical balanced amplifier.

[0035] 5 is a Smith chart showing the load impedance dependency of efficiency in the balanced amplifier shown in FIG. 1 and a general balanced amplifier as contour lines. In FIG. 5, the efficiency contour lines are displayed as 10 pt contour lines. As shown in FIG. 5, the 10 pt efficiency contour range in the balanced amplifier shown in FIG. 1 is wider than that in the general balanced amplifier. For this reason, the balanced amplifier shown in FIG. 1 can be used with a load impedance Z other than 50 Ω. ０ It can be seen that high efficiency is achieved.

[0036] 6 is a Smith chart showing the load impedance dependency of the output power as contour lines for the balanced amplifier shown in FIG. 1 and a general balanced amplifier. In FIG. 6, the output power contour lines are displayed as 2 dB contour lines. As shown in FIG. 6, the 2 dB output power contour range for the balanced amplifier shown in FIG. 1 is wider than that for the general balanced amplifier. For this reason, the balanced amplifier shown in FIG. 1 is suitable for load impedances Z 100Ω and Z 20Ω, which are different from 50Ω. ０ It can be seen that high output power is obtained at

[0037] In the first embodiment described above, the balanced amplifier is configured to include a signal distribution circuit 2 that divides a signal to be amplified into two and outputs a first signal as one of the divided signals and a second signal as the other divided signal, a first amplifier 3 that amplifies the first signal output from the signal distribution circuit 2, a second amplifier 6 that amplifies the second signal output from the signal distribution circuit 2, and a combiner circuit 7 that combines the first signal amplified by the first amplifier 3 and the second signal amplified by the second amplifier 6. The first amplifier 3 of the balanced amplifier also includes a first matching circuit for matching the output impedance of the first amplifier 3 to a first impedance different from the impedance of a load connected to the output side of the combiner circuit 7. The second amplifier 6 of the balanced amplifier also includes a second matching circuit for matching the output impedance of the second amplifier 6 to a second impedance different from the impedance of the load. One of the first impedance and the second impedance is higher than the impedance of the load, and the other impedance is lower than the impedance of the load. Therefore, the balanced amplifier can suppress a decrease in both output power and efficiency even if the impedance of the load changes.

[0038] In the balanced amplifier shown in FIG. 1, the output matching circuit 3c of the first amplifier 3 matches the output impedance of the first amplifying element 3b with the load impedance Z ０ The output matching circuit 6c of the second amplifier 6 matches the output impedance of the second amplifying element 6b to a load impedance Z ０ However, this is only an example, and the output matching circuit 3c of the first amplifier 3 matches the output impedance of the first amplifying element 3b to a load impedance Z ０ The output matching circuit 6c of the second amplifier 6 matches the output impedance of the second amplifying element 6b to a load impedance Z ０ In this case, the balanced amplifier can suppress the decrease in output power and efficiency even if the load impedance changes.

[0039] Second Embodiment In a second embodiment, a balanced amplifier will be described in which an output phase control circuit 4 is provided between a second amplifier 6 and a combining circuit 7, and an input phase control circuit 5 is provided between a signal distribution circuit 2 and a first amplifier 3.

[0040] FIG. 7 is a configuration diagram showing a balanced amplifier according to a second embodiment. In FIG. 7, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts, and detailed description thereof will be omitted. In the balanced amplifier shown in FIG. 7, an output phase circuit 4 is provided between the second amplifier 6 and the combining circuit 7. Also, in the balanced amplifier shown in FIG. 7, an input phase circuit 5 is provided between the signal distribution circuit 2 and the first amplifier 3. The input phase circuit 5 changes the phase of the first signal output from the second terminal 2b of the signal distribution circuit 2 so that the phase of the amplified first signal and the phase of the amplified second signal are in phase at the combining point in the combining circuit 7, where the first signal amplified by the first amplifier 3 and the second signal amplified by the second amplifier 6 are combined. The third terminal 7c of the combining circuit 7 corresponds to the combining point of the combining circuit 7.

[0041] In the balanced amplifier shown in FIG. 7, as in the balanced amplifier shown in FIG. 1, either one of the first impedance and the second impedance is a load impedance Z ０ is higher than the load impedance Z ０ Therefore, the balanced amplifier shown in FIG. ０ Even if the voltage Vcc changes, the decrease in the output power and the efficiency can be suppressed.

[0042] Third Embodiment In a third embodiment, a balanced amplifier in which a signal distribution circuit 2 includes a 90-degree hybrid circuit 9 will be described.

[0043] FIG. 8 is a configuration diagram showing a balanced amplifier according to a third embodiment. In FIG. 8, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts, and detailed description thereof will be omitted. The 90-degree hybrid circuit 9 includes a first terminal 9a, a second terminal 9b, a third terminal 9c, and a fourth terminal 9d. The first terminal 9a is an input terminal to which a high-frequency signal to be amplified is applied, and the second terminal 9b is an isolation terminal grounded via a resistor. The third terminal 9c is an output terminal for outputting a first signal, and the fourth terminal 9d is an output terminal for outputting a second signal. When a high-frequency signal is applied to the first terminal 9a, the 90-degree hybrid circuit 9 divides the high-frequency signal into two. The 90-degree hybrid circuit 9 outputs the first signal from the third terminal 9c to the first amplifier 3 as one of the divided signals, and outputs the second signal from the fourth terminal 9d to the input phase shift circuit 5 as the other of the divided signals.

[0044] In the balanced amplifier shown in Fig. 8, the 90-degree hybrid circuit 9 is applied to the balanced amplifier shown in Fig. 1. However, this is merely an example, and the 90-degree hybrid circuit 9 may also be applied to the balanced amplifier shown in Fig. 7.

[0045] 8, the input phase circuit 5 also changes the phase of the second signal output from the fourth terminal 9d of the 90-degree hybrid circuit 9 so that the phase of the first signal amplified by the first amplifier 3 and the phase of the second signal amplified by the second amplifier 6 are in phase at the third terminal 7c of the combining circuit 7. Specifically, when the phase of the first signal amplified at the third terminal 7c is θ １ , when the input phase circuit 5 is not present, the phase of the amplified second signal at the third terminal 7c is θ ２ , the phase delayed by the input phase circuit 5 is θ ３ If so, the phase θ that the input phase circuit 5 delays is ３ is expressed as, for example, Equation (1) or Equation (2).

[0046] Even in a balanced amplifier in which the signal distribution circuit 2 is provided with a 90-degree hybrid circuit 9, the load impedance Z ０ Even if the voltage Vcc changes, the decrease in the output power and the efficiency can be suppressed.

[0047] Fourth Embodiment In a fourth embodiment, a balanced amplifier in which the signal distribution circuit 2 includes a Wilkinson distribution circuit 10 will be described.

[0048] FIG. 9 is a configuration diagram showing a balanced amplifier according to a fourth embodiment. In FIG. 9, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts, and detailed description thereof will be omitted. The Wilkinson distribution circuit 10 includes a first terminal 10a, a second terminal 10b, and a third terminal 10c. The first terminal 10a is an input terminal to which a high-frequency signal, which is a signal to be amplified, is applied. The second terminal 10b is an output terminal from which a first signal is output, and the third terminal 10c is an output terminal from which a second signal is output. When a high-frequency signal is applied to the first terminal 10a, the Wilkinson distribution circuit 10 divides the high-frequency signal into two. The Wilkinson distribution circuit 10 outputs the first signal from the second terminal 10b to the first amplifier 3 as one of the two divided signals, and outputs the second signal from the third terminal 10c to the input phase shift circuit 5 as the other of the two divided signals.

[0049] In the balanced amplifier shown in Fig. 9, the Wilkinson distribution circuit 10 is applied to the balanced amplifier shown in Fig. 1. However, this is merely an example, and the Wilkinson distribution circuit 10 may also be applied to the balanced amplifier shown in Fig. 7.

[0050] 9, the input phase circuit 5 also changes the phase of the second signal output from the third terminal 10c of the Wilkinson distribution circuit 10 so that the phase of the first signal amplified by the first amplifier 3 and the phase of the second signal amplified by the second amplifier 6 are in phase at the third terminal 7c of the combining circuit 7. Specifically, when the phase of the first signal amplified at the third terminal 7c is θ １, when the input phase circuit 5 is not present, the phase of the amplified second signal at the third terminal 7c is θ ２ , the phase delayed by the input phase circuit 5 is θ ３ If so, the phase θ that the input phase circuit 5 delays is ３ is expressed as, for example, Equation (1) or Equation (2).

[0051] Even in a balanced amplifier in which the signal distribution circuit 2 is provided with the Wilkinson distribution circuit 10, the load impedance Z ０ Even if the voltage Vcc changes, the decrease in the output power and the efficiency can be suppressed.

[0052] Fifth Embodiment In a fifth embodiment, a balanced amplifier including a third amplifier 11 and a fourth amplifier 12 will be described.

[0053] 10 is a block diagram showing a balanced amplifier according to a fifth embodiment. In Fig. 10, the same reference numerals as in Fig. 1 indicate the same or corresponding parts, and detailed description thereof will be omitted. The balanced amplifier shown in Fig. 10 includes a signal input terminal 1, a signal distribution circuit 2, a third amplifier 11, a first amplifier 3, an output phase shift circuit 4, an input phase shift circuit 5, a fourth amplifier 12, a second amplifier 6, a combining circuit 7, and a signal output terminal 8.

[0054] The third amplifier 11 is realized, for example, by a semi-discrete amplifier enclosed in a high-frequency package or an MMIC-type amplifier formed on a semiconductor substrate. The third amplifier 11 is connected in series with the first amplifier 3. In the balanced amplifier shown in FIG. 10 , the third amplifier 11 is connected to the input side of the first amplifier 3. However, this is merely an example, and the third amplifier 11 may also be connected to the output side of the first amplifier 3. When the third amplifier 11 is connected to the output side of the first amplifier 3, the output impedance of the third amplifier 11 is matched to the first impedance. The third amplifier 11 amplifies the first signal output from the second terminal 2 b of the signal distribution circuit 2. The third amplifier 11 outputs the amplified first signal to the first amplifier 3.

[0055] The fourth amplifier 12 is realized, for example, by a semi-discrete amplifier enclosed in a high-frequency package or an MMIC-type amplifier formed on a semiconductor substrate. The fourth amplifier 12 is connected in series with the second amplifier 6. In the balanced amplifier shown in FIG. 10 , the fourth amplifier 12 is connected to the input side of the second amplifier 6. However, this is merely an example, and the fourth amplifier 12 may also be connected to the output side of the second amplifier 6. When the fourth amplifier 12 is connected to the output side of the second amplifier 6, the output impedance of the fourth amplifier 12 is matched to the second impedance. The fourth amplifier 12 amplifies the second signal output from the input phase circuit 5. The fourth amplifier 12 outputs the amplified second signal to the second amplifier 6.

[0056] In the balanced amplifier shown in Fig. 10, the third amplifier 11 and the fourth amplifier 12 are applied to the balanced amplifier shown in Fig. 1. However, this is merely an example, and the third amplifier 11 and the fourth amplifier 12 may also be applied to the balanced amplifier shown in Fig. 7.

[0057] Even when the balanced amplifier includes a third amplifier 11 connected in series with the first amplifier 3 and a fourth amplifier 12 connected in series with the second amplifier 6, the load impedance Z ０ Even if the voltage Vcc changes, the decrease in the output power and the efficiency can be suppressed.

[0058] Sixth Embodiment In a sixth embodiment, a balanced amplifier including a fifth amplifier 13 will be described.

[0059] 11 is a block diagram showing a balanced amplifier according to a sixth embodiment. In Fig. 11, the same reference numerals as in Fig. 1 indicate the same or corresponding parts, and detailed description thereof will be omitted. The balanced amplifier shown in Fig. 11 includes a signal input terminal 1, a fifth amplifier 13, a signal distribution circuit 2, a first amplifier 3, an output phase shift circuit 4, an input phase shift circuit 5, a second amplifier 6, a combining circuit 7, and a signal output terminal 8.

[0060] The fifth amplifier 13 is realized by, for example, a semi-discrete amplifier enclosed in a high-frequency package or an MMIC amplifier formed on a semiconductor substrate. The fifth amplifier 13 amplifies the high-frequency signal to be amplified that is applied to the signal input terminal 1. The fifth amplifier 13 outputs the amplified high-frequency signal to the first terminal 2 a of the signal distribution circuit 2.

[0061] In the balanced amplifier shown in Fig. 11, the fifth amplifier 13 is applied to the balanced amplifier shown in Fig. 1. However, this is merely an example, and the fifth amplifier 13 may also be applied to the balanced amplifier shown in Fig. 7.

[0062] Even when the balanced amplifier includes the fifth amplifier 13, the load impedance Z ０ Even if the voltage Vcc changes, the decrease in the output power and the efficiency can be suppressed.

[0063] Seventh Embodiment In a seventh embodiment, a balanced amplifier including a sixth amplifier 14 will be described.

[0064] 12 is a block diagram showing a balanced amplifier according to a seventh embodiment. In Fig. 12, the same reference numerals as in Fig. 1 indicate the same or corresponding parts, and detailed description thereof will be omitted. The balanced amplifier shown in Fig. 12 includes a signal input terminal 1, a signal distribution circuit 2, a first amplifier 3, a sixth amplifier 14, an output phase shift circuit 4, an input phase shift circuit 5, a second amplifier 6, a combining circuit 7, and a signal output terminal 8.

[0065] The sixth amplifier 14 is realized by, for example, a semi-discrete amplifier enclosed in a high-frequency package or an MMIC-type amplifier formed on a semiconductor substrate. The sixth amplifier 14 is connected in parallel with the first amplifier 3. The sixth amplifier 14 amplifies the first signal output from the second terminal 2b of the signal distribution circuit 2. The sixth amplifier 14 outputs the amplified first signal to the output phase circuit 4. When the first amplifier 3 and the sixth amplifier 14 are connected in parallel, the output impedance of the first amplifier 3 and the output impedance of the sixth amplifier 14 are each matched to the first impedance.

[0066] 12, the sixth amplifier 14 is connected in parallel with the first amplifier 3. However, this is merely an example, and the sixth amplifier 14 may also be connected in parallel with the second amplifier 6. When the second amplifier 6 and the sixth amplifier 14 are connected in parallel, the output impedance of the second amplifier 6 and the output impedance of the sixth amplifier 14 are each matched to the second impedance.

[0067] In the balanced amplifier shown in Fig. 12, the sixth amplifier 14 is applied to the balanced amplifier shown in Fig. 1. However, this is merely an example, and the sixth amplifier 14 may also be applied to the balanced amplifier shown in Fig. 7.

[0068] Even when the balanced amplifier includes the sixth amplifier 14, the load impedance Z ０ Even if the voltage Vcc changes, the decrease in the output power and the efficiency can be suppressed.

[0069] In the balanced amplifiers according to the first to seventh embodiments, the output impedance of the first amplifier 3 is matched to the first impedance, and the output impedance of the second amplifier 6 is matched to the second impedance. However, this is only an example, and the output impedance of the first amplifier 3 is matched to the load impedance Z before the change. ０ The output impedance of the second amplifier 6 is matched to the first impedance corresponding to the load impedance Z before the change.０ Each of the output matching circuits 3c and 6c may be an adjustable matching circuit so as to match the load impedance Z before the change to a second impedance corresponding to Z ０ is 60Ω, the output matching circuit 3c is adjusted so that the output impedance of the first amplifier 3 becomes higher than 60Ω, and the output matching circuit 6c is adjusted so that the output impedance of the second amplifier 6 becomes lower than 60Ω. ０ is 70Ω, the output matching circuit 3c is adjusted so that the output impedance of the first amplifier 3 becomes higher than 70Ω, and the output matching circuit 6c is adjusted so that the output impedance of the second amplifier 6 becomes lower than 70Ω.

[0070] In addition, the present disclosure allows for free combination of the respective embodiments, modification of any of the components of the respective embodiments, or omission of any of the components of the respective embodiments.

[0071] The present disclosure is suitable for balanced amplifiers.

[0072] 1 signal input terminal, 2 signal distribution circuit, 2a first terminal, 2b second terminal, 2c third terminal, 3 first amplifier, 3a input matching circuit, 3b first amplifying element, 3c output matching circuit, 4 output phase circuit, 5 input phase circuit, 6 second amplifier, 6a input matching circuit, 6b second amplifying element, 6c output matching circuit, 7 combining circuit, 7a first terminal, 7b second terminal, 7c third terminal, 7d fourth terminal, 8 signal output terminal, 9 90 degree hybrid circuit, 9a first terminal, 9b second terminal, 9c third terminal, 9d fourth terminal, 10 Wilkinson distribution circuit, 10a first terminal, 10b second terminal, 10c third terminal, 11 third amplifier, 12 fourth amplifier, 13 fifth amplifier, 14 sixth amplifier.

Claims

1. A balanced amplifier comprising: a signal distribution circuit that divides a signal to be amplified into two, outputting a first signal as one of the two signals after the division and a second signal as the other of the two signals after the division; a first amplifier that amplifies the first signal output from the signal distribution circuit; a second amplifier that amplifies the second signal output from the signal distribution circuit; and a combining circuit that combines the first signal after amplified by the first amplifier and the second signal after amplified by the second amplifier, wherein the first amplifier has a first matching circuit for matching the output impedance of the first amplifier to a first impedance different from the impedance of a load connected to the output side of the combining circuit, and the second amplifier has a second matching circuit for matching the output impedance of the second amplifier to a second impedance different from the impedance of the load, wherein one of the first impedance and the second impedance is higher than the impedance of the load, and the other impedance is lower than the impedance of the load.

2. A balanced amplifier as described in claim 1, characterized in that an output phase circuit having an electrical length of 90 degrees is provided between the first amplifier and the combining circuit, and an input phase circuit is provided between the signal distribution circuit and the second amplifier for changing the phase of the second signal output from the signal distribution circuit so that the phase of the amplified first signal and the phase of the amplified second signal are in phase at the combining point of the amplified first signal and the amplified second signal in the combining circuit.

3. The balanced amplifier according to claim 2, characterized in that the first amplifier comprises: a first amplifying element which amplifies a first signal output from the signal distribution circuit; and an output matching circuit as the first matching circuit, one end of which is connected to the output side of the first amplifying element and the other end of which is connected to the input side of the output phase circuit, for matching the output impedance of the first amplifying element to the first impedance; and the second amplifier comprises: a second amplifying element which amplifies a second signal after phase shifting by the input phase circuit; and an output matching circuit as the second matching circuit, one end of which is connected to the output side of the second amplifying element and the other end of which is connected to the input side of the combining circuit, for matching the output impedance of the second amplifying element to the second impedance.

4. A balanced amplifier as described in claim 1, characterized in that an output phase circuit having an electrical length of 90 degrees is provided between the second amplifier and the combining circuit, and an input phase circuit is provided between the signal distribution circuit and the first amplifier for changing the phase of the first signal output from the signal distribution circuit so that the phase of the amplified first signal and the amplified second signal are in phase at the combining point of the amplified first signal and the amplified second signal in the combining circuit.

5. The balanced amplifier according to claim 4, characterized in that the first amplifier comprises: a first amplifying element which amplifies the first signal after phase shift by the input phase circuit; and an output matching circuit as the first matching circuit, one end of which is connected to the output side of the first amplifying element and the other end of which is connected to the input side of the combining circuit, for matching the output impedance of the first amplifying element to the first impedance; and the second amplifier comprises: a second amplifying element which amplifies the second signal output from the signal distribution circuit; and an output matching circuit as the second matching circuit, one end of which is connected to the output side of the second amplifying element and the other end of which is connected to the input side of the output phase circuit, for matching the output impedance of the second amplifying element to the second impedance.

6. A balanced amplifier as claimed in claim 1, characterized in that the combining circuit comprises a 90-degree hybrid circuit having a first terminal to which a first signal amplified by the first amplifier is applied, a second terminal to which a second signal amplified by the second amplifier is applied, and a third terminal for outputting a combined signal of the amplified first signal and the amplified second signal.

7. A balanced amplifier as claimed in claim 1, characterized in that the signal distribution circuit comprises a 90-degree hybrid circuit having a first terminal to which the signal to be amplified is applied, a second terminal for outputting a first signal which is one of the signals after the two-way distribution, and a third terminal for outputting a second signal which is one of the signals after the two-way distribution.

8. A balanced amplifier as claimed in claim 1, characterized in that the signal distribution circuit comprises a Wilkinson distribution circuit having a first terminal to which the signal to be amplified is applied, a second terminal for outputting a first signal which is one of the signals after the two-way distribution, and a third terminal for outputting a second signal which is one of the signals after the two-way distribution.

9. The balanced amplifier according to claim 1, further comprising: a third amplifier connected in series with said first amplifier; and a fourth amplifier connected in series with said second amplifier.

10. The balanced amplifier according to claim 1, further comprising a fifth amplifier for amplifying the signal to be amplified and outputting the amplified signal to the signal distribution circuit.

11. The balanced amplifier according to claim 1, further comprising a sixth amplifier connected in parallel with either said first amplifier or said second amplifier.

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