Method for manufacturing semiconductor device
By filling through-holes in the adhesive layer with a higher modulus filler, the method addresses die shift issues in FOWLP, improving yield and alignment precision in semiconductor device manufacturing.
Patent Information
- Application Number
- PCT/JP2023/022191
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-06-15
- Publication Date
- 2024-12-19
AI Technical Summary
Die shift during the mold sealing process in Fan Out Wafer Level Packaging (FOWLP) leads to reduced manufacturing yield and limitations in designing wiring due to unpredictable thermal expansion and shear deformation of the adhesive tape, making it difficult to achieve desired chip alignment and packaging density.
The method involves forming through-holes in a sheet-like base material with an adhesive layer, filling these holes with a filler having a higher Young's modulus than the base material and adhesive layer, and using this configuration to suppress die shift by reducing shear deformation during the mold sealing process.
This approach effectively reduces die shift, enhancing manufacturing yield and allowing for more precise chip alignment and smaller package designs by stabilizing the adhesive layer and chip position during the molding process.
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Figure JP2023022191_19122024_PF_FP_ABST
Abstract
Description
Semiconductor device manufacturing method
[0001] The present invention relates to a method for manufacturing a semiconductor device.
[0002] As electronic devices become smaller and denser, there is a growing demand in the semiconductor packaging field for smaller, thinner, more functional, and more pin-count components. Fan-out wafer-level packaging (FOWLP) is gaining attention as a promising solution to these demands. FOWLP is a general term for a technology that uses wafer processing to form a rewiring layer that pulls out wiring from the chip terminals.
[0003] A typical FOWLP manufacturing method is the chip-first face-down method described in Non-Patent Document 1. In this technique, first, an adhesive tape having adhesive layers on both sides is attached to a support substrate. Next, a chip transfer machine is used to mount a semiconductor chip on the adhesive layer of the adhesive tape. In this process, the circuit-forming surface of the semiconductor chip is brought into contact with the adhesive layer (chip mounting process). Next, the semiconductor chip is encapsulated with a molding resin to form a molded wafer (mold encapsulation process).
[0004] The adhesive strength of the adhesive layer is then weakened using a method appropriate for the adhesive layer's material, such as thermal peeling or UV irradiation, to separate the mold wafer from the support substrate (support substrate peeling process). Next, a rewiring layer is formed on the exposed circuit-forming surface of the semiconductor chip using a build-up method (rewiring process). Finally, the wafer is diced into individual packages (dicing process).
[0005] The manufacturing method described above allows for a thinner package without using a conventional package substrate. Furthermore, the terminals can be extended to the outside of the die, resulting in a package area larger than the die, enabling more pins and a looser terminal pitch.
[0006] M. Brunnbauer et al., "An Embedded Device Technology Based on a Molded Reconfigured Wafer", 56th Electronic Components and Technology Conference 2006, 9061351, ISBN:1-4244-0152-6, 06, pp. 574-551, 2006.G. Sharma et al., "Solutions Strategies for Die Shift Problem in Wafer Level Compression Molding", IEEE Transactions on Components, Packaging and Manufacturing Technology , vol. 1, No. 4, pp. 502-509, 2011.HS Ling et al., "Comprehensive Study on the Interactions of Multiple Die Shift Mechanisms During Wafer Level Molding of Multichip-Embedded Wafer Level Packages", IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 4, no. 6, pp. 1090-1098, 2014.
[0007] However, the above-mentioned mold encapsulation process presents many manufacturing challenges specific to FOWLP. A typical challenge is die shift. A semiconductor chip mounted on a support substrate is encapsulated in mold resin while heated, and then cooled together with the mold resin. Die shift is a phenomenon in which the chip position shifts due to thermal expansion and contraction of the components during this process. A large amount of die shift leads to a decrease in manufacturing yield. Alternatively, the alignment margin of the redistribution layer must be widened, which places restrictions on the minimum formation dimensions and makes it difficult to design wiring with the desired characteristics.
[0008] Pre-shifting is a well-known typical method for dealing with such die shift (Non-Patent Document 2). Pre-shifting is a method for reducing the net amount of die shift by predicting the amount of die shift at the design stage before manufacturing and mounting the chip at a position that is the inverse vector of the movement vector caused by the die shift. However, to effectively utilize this method, it is important to accurately predict the amount of die shift at the design stage.
[0009] As introduced in Non-Patent Document 3, there are two main mechanisms that cause die shift. The first is die shift due to thermal expansion or contraction of components. This exhibits linear behavior and can be predicted using simulation techniques.
[0010] The second problem is die shift caused by shear deformation of the adhesive tape. As shown in (a) of Figure 3, when a chip 303 attached to a support substrate 301 with adhesive tape 302 is mold-sealed, a molding resin (not shown) flows on the surface of the adhesive tape 302. The shear force (indicated by the arrows) on the adhesive tape 302 caused by this flow causes shear deformation of the adhesive tape 302, as shown in (b) of Figure 3. This deformation of the adhesive tape 302 causes the chip 303 to move, resulting in a die shift. This die shift exhibits nonlinear behavior, making it difficult to predict at the time of design.
[0011] The present invention has been made to solve the above problems, and has as its object to suppress die shift during mold sealing of FOWLP.
[0012] The method for manufacturing a semiconductor device according to the present invention includes a through hole forming step of forming a through hole penetrating the adhesive layer and the substrate in a mounting area of a sheet-like substrate having an adhesive layer formed on its main surface; a chip bonding step of bonding a chip with its circuit formation surface facing the adhesive layer in the mounting area to block the adhesive layer side of the through hole with the chip; a filling step of filling the through hole with a filler having a higher Young's modulus than the substrate and the adhesive layer; an attachment step of attaching the back surface of the substrate to a support substrate; a molding step of forming a molded resin layer on the adhesive layer on which the through hole has been filled with the filler and the back surface of the substrate has been attached to the support substrate and the chip has been attached to the adhesive layer, thereby molding the chip on the adhesive layer; and a removal step of removing the adhesive layer, the substrate, and the support substrate from the molded resin layer.
[0013] As described above, according to the present invention, a filler having a higher Young's modulus than the base material and adhesive layer is filled into the through holes that penetrate the adhesive layer and base material, thereby making it possible to suppress die shift during mold sealing of FOWLP.
[0014] FIG. 1A is a cross-sectional view showing a state of a semiconductor device in an intermediate step for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1B is a cross-sectional view showing a state of a semiconductor device in an intermediate step for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1C is a cross-sectional view showing a state of a semiconductor device in an intermediate step for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1D is a cross-sectional view showing a state of a semiconductor device in an intermediate step for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1E is a cross-sectional view showing a state of a semiconductor device in an intermediate step for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1F is a cross-sectional view showing a state of a semiconductor device in an intermediate step for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1G is a cross-sectional view showing a state of a semiconductor device in an intermediate step for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1H is a cross-sectional view showing a state of a semiconductor device in an intermediate step for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1I is a cross-sectional view showing a state of a semiconductor device in an intermediate step for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1J is a cross-sectional view showing a state of a semiconductor device in an intermediate step for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2A is a cross-sectional view showing a state of a semiconductor device in an intermediate step for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2B is a cross-sectional view showing a state of a semiconductor device in an intermediate step for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 3 is an explanatory diagram illustrating die shift caused by shear deformation of the adhesive tape.
[0015] A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to FIGS. 1A to 1J.
[0016] First, as shown in FIG. 1A , a sheet-like substrate 101 having a first adhesive layer 102 formed on its main surface is prepared. In this example, a second adhesive layer 103 is also formed on the back surface of the substrate 101. The first adhesive layer 102 and the second adhesive layer 103 are formed over the entire surface of the substrate 101. The entire surface of the first adhesive layer 102 is covered with a first separator film 104. The entire surface of the second adhesive layer 103 is covered with a second separator film 105. These can be made of well-known dicing tape. The thickness of each of the above-mentioned layers is typically about several tens of μm.
[0017] The substrate 101 has the role of maintaining mechanical strength and holding the first adhesive layer 102 (second adhesive layer 103). The substrate 101 can be made of, for example, polyethylene terephthalate or polyimide. In the molding process described below, the substrate 101 may be heated to 120 to 150°C, so it is important that the substrate 101 be resistant to this temperature. The substrate 101 can also be circular in plan view. For example, the substrate 101 can be circular with a diameter of 180 mm in plan view.
[0018] The first adhesive layer 102 and the second adhesive layer 103 can be made of, for example, a resin that has adhesiveness and hardens when irradiated with ultraviolet light. This type of resin undergoes a polymerization reaction when irradiated with ultraviolet light, reducing its adhesiveness. The first adhesive layer 102 and the second adhesive layer 103 can also be made of a resin whose adhesiveness decreases when heated (for example, at 210°C / min).
[0019] The first separator film 104 and the second separator film 105 have no adhesive strength and are used to protect the first adhesive layer 102 and the second adhesive layer 103. The first separator film 104 and the second separator film 105 are used to prevent unnecessary objects from adhering to the first adhesive layer 102 and the second adhesive layer 103. For example, when using the first adhesive layer 102, the first separator film 104 is released to expose the first adhesive layer 102. Similarly, when using the second adhesive layer 103, the second separator film 105 is released to expose the second adhesive layer 103. The first separator film 104 and the second separator film 105 can be made of, for example, an alkyl-based or silicone-based polymer material.
[0020] 1B and 1C, through holes 106 are formed in the substrate 101, penetrating the first adhesive layer 102, the substrate 101, and the second adhesive layer 103 (through hole forming process). In this example, the through holes 106 are formed by penetrating the first separator film 104, the first adhesive layer 102, the substrate 101, the second adhesive layer 103, and the second separator film 105. In addition, the through holes 106 are formed in multiple locations. The through holes 106 are formed in a chip mounting region, which will be described later.
[0021] Although it depends on the circuit design of the semiconductor device of the chip to be mounted, the larger the diameter of the through hole 106, the greater the effect of suppressing shear deformation of the adhesive layer. The through hole 106 can be formed, for example, by punching using a press. Alternatively, the through hole 106 can be formed using a laser processing machine depending on the materials of the base material 101 and each adhesive layer.
[0022] Next, after the first separator film 104 is released from the first adhesive layer 102, as shown in Figures 1D and 1E, a chip 107 is mounted and adhered to the first adhesive layer 102 in a predetermined mounting area with the circuit formation surface facing the first adhesive layer 102. By adhering the chip 107, the side of the through hole 106 facing the first adhesive layer 102 is blocked by the chip 107 (chip adhering process). The first separator film 104 can be easily peeled off (released) using tweezers or the like.
[0023] The chip 107 can be mounted using a chip transfer machine such as a die bonder or a flip chip bonder. As will be described later, when filling the through hole 106 with solder, it is desirable to form a metal pad or the like on the circuit formation surface of the chip 107 in a corresponding location so that the filled solder will be soldered to the circuit formation surface of the chip 107. In this case, the chip 107 is mounted and bonded after being aligned so that the formation position of the metal pad and the position of the through hole 106 overlap.
[0024] 1F, solder paste (solder cream) 108 is filled into through holes 106. For example, by using a screen printing method in which second separator film 105, in which through holes 106 are formed, is used as a screen, solder paste is applied to this surface with a squeegee, thereby filling through holes 106 with solder paste 108.
[0025] Next, second separator film 105 is released from second adhesive layer 103 to expose the adhesive surface of second adhesive layer 103. By peeling second separator film 105, unnecessary solder paste adhering to second separator film 105 is removed, and solder paste 108 is filled into through holes 106. Depending on the thickness of second separator film 105, part of solder paste 108 may protrude from the adhesive surface of second adhesive layer 103.
[0026] 1G, the back surface of the substrate 101 is attached to the support substrate 111 (attachment process). The back surface of the substrate 101 can be attached to the support substrate 111 by the second adhesive layer 103. For example, by using a vacuum laminating device, the lamination is performed while applying pressure to prevent air bubbles from entering the attachment surface. By applying pressure, the portion of the solder paste 108 protruding from the second adhesive layer 103 is crushed, thereby reducing the variation in height of the chip 107 due to the solder paste 108 formed in multiple locations.
[0027] The support substrate 111 may have a size that corresponds to a semiconductor manufacturing device used when forming a rewiring layer after a molding process described later. The support substrate 111 may be made of, for example, a semiconductor such as silicon, glass, resin, or metal.
[0028] After the back surface of the substrate 101 is attached to the support substrate 111 by the second adhesive layer 103 in the manner described above, the substrate and the support substrate 111 are heated to bake the solder paste 108, resulting in a state in which the filler 109 made of solder is filled into the through holes 106, as shown in FIG. 1H (filling step). The solder constituting the filler 109 is a material with a higher Young's modulus than the substrate 101 and the first adhesive layer 102 (second adhesive layer 103). The baking of the solder paste 108 needs to be carried out within a temperature range that does not adversely affect the properties of the substrate 101 or each adhesive layer.
[0029] As described above, after the through hole 106 is filled with the filler 109, the back surface of the base material 101 is attached to the support substrate 111, and the chip 107 is adhered to the first adhesive layer 102, a molded resin layer 112 is formed on the first adhesive layer 102 to mold the chip 107 on the first adhesive layer 102 (molding process), as shown in Fig. 1I. For example, a resin pattern to be the molded resin layer 112 can be formed by a known compression molding method or transfer molding method, and the resin pattern can be hardened to form the molded resin layer 112.
[0030] Next, the first adhesive layer 102, the second adhesive layer 103, the base material 101, and the support substrate 111 are removed from the molded resin layer 112, thereby exposing the circuit formation surface of the chip 107 to the outside of the molded resin layer 112, as shown in FIG. 1J (removal process). The support substrate 111 can be removed together with the base material 101 and the second adhesive layer 103, for example, by releasing the first adhesive layer 102 from the molded resin layer 112. For example, a method that does not deteriorate the characteristics of the integrated circuit of the chip 107, such as a laser peeling method, a thermal peeling method, a mechanical peeling method, or a solvent peeling method, can be selected.
[0031] After this, a rewiring layer is formed using a known build-up method, and the module is separated into individual modules to form the desired semiconductor device. The first adhesive layer 102 is prone to shear deformation during the molding process, leading to die shift, which causes the chip position to shift. However, according to the above-described embodiment, the presence of the filler 109, which has a higher Young's modulus than the base material 101 and the first adhesive layer 102 (second adhesive layer 103), suppresses the shear deformation and thus the die shift.
[0032] In the above description, the attaching step is performed after the chip bonding step, but this is not limiting. For example, the chip bonding step can be performed after the attaching step.
[0033] 2A , for example, the back surface of the substrate 101 is attached to the support substrate 111 (attaching step). After the second separator film 105 is released from the second adhesive layer 103, the back surface of the substrate 101 is attached to the support substrate 111 by the second adhesive layer 103. Next, a through hole 106 is formed in the substrate 101, penetrating the first adhesive layer 102, the substrate 101, and the second adhesive layer 103 (through hole forming step). In this example, the through hole 106 is formed by penetrating the first separator film 104, the first adhesive layer 102, the substrate 101, and the second adhesive layer 103.
[0034] Next, the through holes 106 are filled with solder paste (solder cream) 108. For example, by using a screen printing method in which the first separator film 104 in which the through holes 106 are formed is used as a screen, the solder paste is applied to this surface with a squeegee, thereby filling the through holes 106 with the solder paste 108.
[0035] Next, second separator film 105 is released from second adhesive layer 103 to expose the adhesive surface of second adhesive layer 103, as shown in Fig. 2B. By peeling second separator film 105, unnecessary solder paste adhering to second separator film 105 is removed, and through-holes 106 are left filled with solder paste 108.
[0036] Thereafter, a chip 107 is mounted and bonded to the first adhesive layer 102 in a predetermined mounting area with the circuit formation surface facing the first adhesive layer 102. By bonding the chip 107, the side of the through hole 106 facing the first adhesive layer 102 is blocked by the chip 107 (chip bonding process). This results in the same state as described with reference to FIG. 1G. Thereafter, as described above, the solder paste 108 is baked by heating, and as shown in FIG. 1H, the through hole 106 is filled with filler material 109 made of solder (filling process).
[0037] 1I, a mold resin layer 112 is formed on the first adhesive layer 102, and the chip 107 on the first adhesive layer 102 is molded (molding step). Next, the first adhesive layer 102, the second adhesive layer 103, the base material 101, and the support substrate 111 are removed from the mold resin layer 112, thereby exposing the circuit formation surface of the chip 107 to the outside of the mold resin layer 112, as shown in FIG. 1J (removal step).
[0038] As described above, according to the present invention, a filler having a higher Young's modulus than the substrate and adhesive layer is filled into the through-hole that penetrates the adhesive layer and substrate, thereby making it possible to suppress die shift during mold sealing of FOWLP.
[0039] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention.
[0040] 101...base material, 102...first adhesive layer, 103...second adhesive layer, 104...first separator film, 105...second separator film, 106...through hole, 107...chip, 108...solder paste (solder cream), 109...filler, 111...support substrate, 112...molded resin layer.
Claims
1. A method for manufacturing a semiconductor device comprising: a through hole forming step of forming a through hole penetrating the adhesive layer and the substrate in a mounting area of a sheet-like substrate having an adhesive layer formed on a main surface thereof; a chip bonding step of bonding a chip with its circuit formation surface facing the adhesive layer in the mounting area to close the adhesive layer side of the through hole with the chip; a filling step of filling the through hole with a filler having a higher Young's modulus than the substrate and the adhesive layer; an attachment step of attaching the back surface of the substrate to a support substrate; a molding step of forming a molded resin layer on the adhesive layer on which the through hole is filled with the filler and the back surface of the substrate is attached to the support substrate, and molding the chip on the adhesive layer; and a removal step of removing the adhesive layer, the substrate, and the support substrate from the molded resin layer.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the attaching step is carried out after the chip bonding step.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the chip bonding step is carried out after the attachment step.
4. A method for manufacturing a semiconductor device as claimed in any one of claims 1 to 3, further comprising a step of filling the through holes with solder paste before the rear surface of the base material is attached to the support board and the chip is bonded to the adhesive layer, the filling step heating the solder paste filled in the through holes to fill the through holes with the filler material consisting of solder.
Citation Information
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