High electron mobility transistor and manufacturing method thereof

Abstract

An embodiment provides a high electron mobility transistor (HEMT) comprising: a first drain terminal; a gate terminal; a second drain terminal; a channel layer, of which a portion forms a first element together with the first drain terminal and the gate terminal and the other portion forms a second element together with the second drain terminal and the gate terminal; and a barrier layer including a first barrier layer that forms, in the first element, a first two-dimensional electron gas (2 DEG) region at the interface with the channel layer, and a second barrier layer that forms, in the second element, a second two-dimensional electron gas region at the interface with the channel layer, wherein the physical properties of the first barrier layer and the second barrier layer are different from each other.

Description

High electron mobility transistor and its manufacturing method

[0001] The present invention relates to a high electron mobility transistor and a manufacturing technique thereof.

[0002] All silicon power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) have an intrinsic body diode connected in parallel with the drain and source. As is well known, a diode is a unidirectional conducting device in the forward biased state. Therefore, when a MOSFET is operated in the third quadrant of the current-voltage (IV) graph, its body diode is in the forward biased state, exhibiting either a typical diode-like current-voltage (IV) characteristic when the gate bias is zero or negative, or a resistive behavior at positive gate bias values. Therefore, as a conduction control device, MOSFETs are primarily used in the first quadrant, i.e., for switching and amplification, in most applications. In other words, silicon MOSFETs are unidirectional devices operating in the first quadrant.

[0003] Over the past several decades, the power industry has begun to utilize gallium nitride (GaN) materials in transistor fabrication due to their high energy bandgap and high electron mobility. This enables high performance. GaN-based transistors, known as high electron mobility transistors (HEMTs), offer low on-resistance. This type of composite transistor has become a key emerging device in power electronics due to its numerous advantages, including high switching frequency, high power density, and high thermal conductivity. It also offers numerous benefits in efficient system design and small footprints.

[0004] Unlike silicon transistors, GaN HEMTs have no body diode, and their current conduction is achieved through a two-dimensional electron gas (2DEG) layer a few nanometers thick. The 2DEG arises from the spontaneous and piezoelectric polarization of the two layers at the interface between the AlxGa1-xN barrier layer and the GaN channel layer.

[0005] There are several ways to tune the 2DEG surface charge density. For example, changing the aluminum mole fraction in the barrier layer or applying N-type doping to both layers is possible. If a uniform epitaxial layer is used and the same layout dimensions are applied across the drain and source regions, a GaN HEMT will have identical IV curves in the first and third quadrants, but in opposite directions. That is, these curves are symmetrical about the origin in the IV regime. In this sense, GaN HEMTs are bidirectional devices, in contrast to unidirectional silicon MOSFETs.

[0006] When these devices are used for bidirectional conduction, there is no need to distinguish between the source and drain of a GaN HEMT. The transistor nomenclature can be simplified to bidirectional GaN (bi-GaN). In the case of bi-GaN, the first drain (D1), second drain (D2), and gate are labeled to represent the three terminals of the transistor, and the D1 / D2 terminals are interchangeable as long as a uniform epitaxial layer and the same layout dimensions are used in the D1 and D2 regions.

[0007] Meanwhile, several applications are gaining popularity based on the bidirectional nature of GaN HEMTs. Examples include overvoltage protection (OVP) circuits for smartphone charging and high-side load switching. The structure of bi-GaN HEMT devices is symmetrical across D1 and D2, providing identical high-voltage capabilities. Consequently, the Ron of bi-GaN HEMTs increases compared to unidirectional devices. This poses challenges for dual-function applications and can limit performance when one function requires low Ron.

[0008] GaN HEMTs are also known for their high material and process costs compared to silicon and other compound semiconductor processes. While their performance is highly attractive, the high cost has been a major factor in the market's hesitation in making this technology a more commercial option. Reducing die size and improving packaging density are fundamental goals for this industry, not only for performance but also, more importantly, for the industry.

[0009] Against this backdrop, the purpose of the present invention is to provide a solution that improves the on-resistance (Ron) performance and to provide a technique that enables expansion of bi-GaN applications and reduction of die size for better packaging density and lower die cost.

[0010] Bi-GaN can provide solutions for new applications that silicon transistors cannot address. For example, there are features such as bidirectional switching. In this case, a single Bi-GaN transistor can replace two reverse-connected MOSFETs to achieve bidirectional switching in a common-source configuration, simplifying the design and reducing chip size.

[0011] Through an innovative gate driver design, bi-GaN can simultaneously perform two different functions. A typical application for bi-GaN involves symmetrically arranging D1 and D2 around the gate, maintaining the same drain-to-gate extension distance, and maintaining the same 2DEG density. However, different performance requirements for D1 and D2 in bi-GaN may vary depending on specific application requirements. For example, one function may be high-voltage switching in the first quadrant, while the other may be reverse-blocking in the third quadrant. A symmetrically designed bi-GaN may perform one function well but may compromise the other, limiting overall performance.

[0012] Functionally, bi-GaN may face situations where the roles of D1 and D2 compete with each other, limiting each other. For example, the high-voltage switching side may require high withstand voltage and switching capability, while the reverse-blocking side may focus on voltage blocking capability. The high-voltage switching side with its high withstand voltage will result in a higher Ron. The Ron of the reverse-blocking side is in series with the Ron of the high-voltage switching side. This additional Ron, added to the Ron requirement for minimizing in the high-switching and high-withstand voltage aspects, can negatively impact switching performance. Therefore, balancing the individual performance of bi-GaN across various modes becomes challenging due to the differing device performance goals.

[0013] Our solution is to customize the 2DEG of D1 and D2 using fundamental GaN device principles and processing essentials to maximize performance on each side while simultaneously reducing device spacing to improve packaging density.

[0014] In order to achieve the above-described object, one embodiment provides a HEMT (high electron mobility transistor), comprising: a first drain terminal; a gate terminal; a second drain terminal; a channel layer, a portion of which forms a first element together with the first drain terminal and the gate terminal and the other portion of which forms a second element together with the second drain terminal and the gate terminal; and a first barrier layer forming a first two-dimensional electron gas (2DEG) region at an interface with the channel layer within the first element, and a second barrier layer forming a second two-dimensional electron gas region at an interface with the channel layer within the second element, wherein the first barrier layer and the second barrier layer have different physical properties.

[0015] The first element can operate as a voltage blocking element, and the second element can operate as a switching element.

[0016] The first barrier layer and the second barrier layer include an AlGaN material, and the Al molar fractions in the first barrier layer and the second barrier layer may be different from each other.

[0017] Due to the difference in the physical properties of the first barrier layer and the second barrier layer, the electron densities of the first two-dimensional electron gas region and the second two-dimensional electron gas region may be different from each other.

[0018] The electron density of the second two-dimensional electron gas region may be higher than the electron density of the first two-dimensional electron gas region.

[0019] The length between the first drain terminal and the gate terminal on the upper surface of the channel layer and the length between the second drain terminal and the gate terminal may be different from each other.

[0020] The doping concentrations in the first barrier layer and the second barrier layer may be different from each other.

[0021] The HEMT is of a horizontal type, and the channel layer is arranged below the first drain terminal, the gate terminal, and the second drain terminal in the vertical direction, and the first drain terminal, the gate terminal, and the second drain terminal are arranged in that order in the horizontal direction, and a ground plate may be arranged between the gate terminal and the second drain terminal in the horizontal direction.

[0022] The above ground plate may be arranged between the gate terminal and the second drain terminal, and may not be arranged between the gate terminal and the first drain terminal.

[0023] Another embodiment provides a HEMT (high electron mobility transistor) comprising: a first drain terminal; a gate terminal; a second drain terminal; a channel layer, a portion of which forms a first element together with the first drain terminal and the gate terminal and another portion of which forms a second element together with the second drain terminal and the gate terminal; and a barrier layer that forms a two-dimensional electron gas (2DEG) region at an interface with the channel layer, wherein the two-dimensional electron gas regions having different densities are formed in the first element and the second element.

[0024] The properties of the barrier layer in the first element and the properties of the barrier layer in the second element may be different from each other.

[0025] The above barrier layer includes an AlGaN material, and the Al mole fractions of the AlGaN material in the first element and the second element may be different from each other.

[0026] The N-type doping concentration of the barrier layer in the first element and the second element may be different from each other.

[0027] The 2DEG density of the second element may be 1.5 times or more the 2DEG density of the first element.

[0028] The first element can operate as a voltage blocking element, and the second element can operate as a switching element.

[0029] Another embodiment provides a method for manufacturing a high electron mobility transistor (HEMT), comprising: forming a channel layer, a portion of which forms a first element together with a first drain terminal and a gate terminal, and another portion of which forms a second element together with a second drain terminal and the gate terminal; forming a first barrier layer having a first property on the channel layer; forming the gate terminal on the first barrier layer; forming a first protective layer on the first barrier layer and the gate terminal; removing the first protective layer and the first barrier layer from the second element through etching; and forming a barrier layer including the first barrier layer and the second barrier layer having different properties by depositing a second barrier layer having a second property on a portion of the first barrier layer that is etched.

[0030] The above HEMT manufacturing method may further include: forming a second protective layer on the second barrier layer after stacking the second barrier layer having the second property on the etched portion of the first barrier layer; forming an oxide film on the second protective layer; polishing the second protective layer with the oxide film as an endpoint; removing the first oxide film remaining on the first element among the oxide films; removing the second barrier layer and the second protective layer from an area excluding a portion protected by the second oxide film remaining on the second element among the oxide films; and removing the remaining second oxide film and the first protective layer.

[0031] The first barrier layer and the second barrier layer can be formed by metal-organic chemical vapor deposition (MOCVD).

[0032] The above oxide film can be formed by plasma-enhanced chemical vapor deposition (PECVD).

[0033] The above polishing may be chemical mechanical planarization (CMP).

[0034] As described above, the present embodiment provides a solution for improving the on-resistance (Ron) performance and provides a technology that enables expansion of bi-GaN applications and reduction of die size for better packaging density and lower die cost.

[0035] FIG. 1 is a cross-sectional view of a HEMT according to one embodiment.

[0036] FIG. 2 is a cross-sectional view of a GaN HEMT according to one embodiment, showing terminals and a channel layer in greater detail.

[0037] Fig. 3 is a drawing showing the configuration of a switching element according to one embodiment.

[0038] Fig. 4 is a drawing showing the configuration of a voltage blocking element according to one embodiment.

[0039] FIGS. 5 to 13 are drawings showing a method of forming barrier layers with different properties among the methods of manufacturing a HEMT according to one embodiment.

[0040] Figure 14 is a graph showing the relationship between 2DEG density and on-resistance.

[0041] Figure 15 is a graph showing the relationship between 2DEG density and internal pressure.

[0042] Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. When designating components in each drawing, it should be noted that, where possible, identical components will be given the same reference numbers, even if they appear in different drawings. Furthermore, when describing the present invention, detailed descriptions of known related structures or functions will be omitted if they are deemed to obscure the gist of the present invention.

[0043] Additionally, terms such as first, second, A, B, (a), (b), etc. may be used to describe components of the present invention. These terms are only intended to distinguish the components from other components, and the nature, order, or sequence of the components are not limited by the terms. When it is described that a component is "connected," "coupled," or "connected" to another component, it should be understood that the component may be directly connected or connected to the other component, but another component may also be "connected," "coupled," or "connected" between each component.

[0044] FIG. 1 is a cross-sectional view of a HEMT according to one embodiment.

[0045] Referring to FIG. 1, a high electron mobility transistor (HEMT) may include a first drain terminal (D1), a gate terminal (GT), and a second drain terminal (D2). For convenience of explanation, the side where the terminals (D1, GT, D2) are located is referred to as the upper side, and the side where the substrate layer (162) is formed is referred to as the lower side.

[0046] HEMT (100) is a semiconductor device with high electron mobility, and is known to exhibit excellent performance in high-speed switching and high-frequency regions. HEMT (100) is based on a two-dimensional electron gas (2DEG). At the interface between the barrier layer (102) and the channel layer (132) included in HEMT (100), spontaneous polarization and deformation polarization combine to form a strong electric field. This phenomenon can induce abundant electrons into the channel layer (132) to form a 2DEG.

[0047] Electrons in a 2DEG have very low effective masses and can exhibit high mobility due to minimal scattering from lattice defects or impurities. These 2DEG characteristics enable HEMTs (100) to operate at higher frequencies and also improve switching speeds.

[0048] Based on the aforementioned characteristics, HEMT (100) is known to have low noise and high energy efficiency. Furthermore, its relatively low on-resistance can enhance the efficiency of power applications. Furthermore, HEMT (100) can withstand high power densities due to the 2DEG formed by the strong electric field.

[0049] HEMT(100) can be made based on GaN (Gallium Nitride).

[0050] GaN HEMTs are high-performance electronic devices, particularly suited for high-power, high-frequency applications. GaN HEMTs are known to possess superior electrical properties compared to traditional silicon-based transistors, due to the physical and electrical properties of GaN. Below, an exemplary embodiment will be described, focusing on a GaN HEMT (100).

[0051] The barrier layer (102) may be composed of AlGaN. And, the channel layer (132) may be composed of GaN.

[0052] The GaN HEMT (100) may include a two-dimensional electron gas (2DEG). The GaN HEMT (100) may form a 2DEG at the interface between the barrier layer (102) and the channel layer (132) in the AlGaN / GaN structure. This 2DEG creates a channel through which electrons can move with very high mobility.

[0053] GaN has a very high breakdown voltage (BV). Furthermore, GaN has high thermal conductivity. Accordingly, GaN HEMTs (100) can operate stably even at high voltages and effectively dissipate heat, making them suitable for high-power applications.

[0054] GaN HEMT (100) can have a high electron channel density due to the large number of electrons provided through the barrier layer (102), thereby achieving low on-resistance (Ron) and high current capacity. In addition, GaN HEMT (100) can have a very fast switching speed due to the high electron mobility of GaN and the channel characteristics of 2DEG.

[0055] GaN itself is known to have a breakdown voltage (BV) approximately 10 times higher than silicon, and its high thermal conductivity facilitates heat management. Furthermore, GaN's high electron mobility makes it ideal for high-frequency applications, and its wide bandgap ensures stable electrical properties even at high temperatures.

[0056] The GaN HEMT (100) may further include a substrate layer (162). The substrate layer (162) may be formed of a single crystal substrate such as SiC (Silicon Carbide), Si, GaN, or AIN (Aluminum Nitride). In one embodiment, the substrate layer (162) may be composed of silicon (Si).

[0057] A buffer layer (152) may be placed on the substrate layer (162). The buffer layer (152) may be formed of AIN (Aluminum Nitride).

[0058] An AlGaN layer (142) may be placed on the buffer layer (152), and a channel layer (132) may be placed on the AlGaN layer (142).

[0059] And, a barrier layer (102) may be placed on the channel layer (132). The channel layer (132) composed of GaN and the barrier layer (102) composed of AlGaN are layers formed of different band gap semiconductor elements, so that a dense electron region (or channel) may be formed at the interface between the two layers.

[0060] A first drain terminal (D1), a gate terminal (GT), and a second drain terminal (D2) may be arranged on the channel layer (132). The GaN HEMT (100) is of a horizontal type, and in the vertical direction, the channel layer (132) may be arranged below the first drain terminal (D1), the gate terminal (GT), and the second drain terminal (D2). In addition, in the horizontal direction, the first drain terminal (D1), the gate terminal (GT), and the second drain terminal (D2) may be arranged in that order.

[0061] A p-GaN layer (112) may be further disposed between the gate terminal (GT) and the barrier layer (102) or between the gate terminal (GT) and the channel layer (132).

[0062] A ground plate (122) may be arranged between the gate terminal (GT) and the second drain terminal (D2). In the horizontal direction, the ground plate (122) may be arranged between the gate terminal (GT) and the second drain terminal (D2). In addition, the ground plate (122) may not be in direct contact with the channel layer (132), and an insulating layer may be arranged therebetween. In addition, a barrier layer (102) may be arranged between the insulating layer and the channel layer (132).

[0063] FIG. 2 is a cross-sectional view of a GaN HEMT according to one embodiment, showing terminals and a channel layer in greater detail.

[0064] Referring to FIG. 2, a first drift region (202), a second drift region (204), and a channel region (212) can be formed in the channel layer (132).

[0065] The first drift region (202) may be formed between the first drain terminal (D1) and the gate terminal (GT) in the channel layer (132). In addition, the second drift region (204) may be formed between the second drain terminal (D2) and the gate terminal (GT) in the channel layer (132). In addition, the channel region (212) may be formed at a position corresponding to the gate terminal (GT) in the channel layer (132) - for example, a position below the gate terminal (GT). When the p-GaN layer (112) is disposed below the gate terminal (GT), the p-GaN layer (112) may be disposed on the channel region (212).

[0066] When the GaN HEMT (100) is turned on, the resistance (Ron) for the current flowing from the first drain terminal (D1) to the second drain terminal (D2) may have a resistance value equal to the series combination of the first drift resistor (Ron1) formed in the first drift region (202), the channel resistor (Rch) formed in the channel region (212), and the second drift resistor (Ron2) formed in the second drift region (204). Ron = Ron1 + Rch + Ron2

[0067] The size of the first drift resistance (Ron1) may be proportional to the length (lgd1) of the first drift region (202). The length (lgd1) of the first drift region (202) may be measured as the minimum distance between the edge of the first drain terminal (D1) in contact with the upper surface of the channel layer (132) and the edge of the gate terminal (GT). The shorter the length (lgd1) of the first drift region (202), the smaller the size of the first drift resistance (Ron1) may be.

[0068] The size of the second drift resistance (Ron2) may be proportional to the length (lgd2) of the second drift region (204). The length (lgd2) of the second drift region (204) may be measured as the minimum distance between the edge of the second drain terminal (D2) in contact with the upper surface of the channel layer (132) and the edge of the gate terminal (GT). The shorter the length (lgd2) of the second drift region (204), the smaller the size of the second drift resistance (Ron2) may be.

[0069] Functionally, the GaN HEMT (100) can be configured with two devices (DEV1, DEV2).

[0070] The first element (DEV1) may be composed of a first drain terminal (D1), a gate terminal (GT), and an area corresponding to a position from the first drain terminal (D1) to the gate terminal (GT) in the channel layer (132).

[0071] And, the second element (DEV2) may be composed of a second drain terminal (D2), a gate terminal (GT), and an area corresponding to a position from the second drain terminal (D2) to the gate terminal (GT) in the channel layer (132).

[0072] In addition, the first element (DEV1) can operate as a voltage blocking element, and the second element (DEV2) can operate as a high-frequency switching element. Depending on the operation of the second element (DEV2), the on / off of the GaN HEMT (100) can be determined, and in a turned-off state, the withstand voltage characteristics of the GaN HEMT (100) can be determined by the first element (DEV1).

[0073] In the second device (DEV2), a ground plate (122) may be placed between the gate terminal (GT) and the second drain terminal (D2) to reduce HCI (Hot Carrier Injection).

[0074] Meanwhile, the barrier layer (102a, 102b) may include a first barrier layer (102a) and a second barrier layer (102b) having different physical properties.

[0075] The first barrier layer (102a) can form a first two-dimensional electron gas region at the interface with the channel layer (132) within the first element (DEV1). In addition, the second barrier layer (102b) can form a second two-dimensional electron gas region at the interface with the channel layer (132) within the second element (DEV2). In this way, by arranging barrier layers (102a, 102b) having different properties in each element (DEV1, DEV2), each element (DEV1, DEV2) can exhibit optimal performance. For example, the performance of the first element (DEV1) as a voltage blocking element can be optimized, and the performance of the second element (DEV2) as a high-frequency switching element can be optimized.

[0076] The on-resistance (Ron) may have an inverse relationship with the concentration of the 2DEG. The higher the concentration of the 2DEG, the lower the on-resistance (Ron). For example, the 2DEG density of the second two-dimensional electron gas region formed in the second element (DEV2) may be higher than the 2DEG density of the first two-dimensional electron gas region formed in the first element (DEV1). Accordingly, the on-resistance (Ron) of the second element (DEV2) may be further reduced.

[0077] When the barrier layers (102a, 102b) include AlGaN material, the Al mole fractions of the AlGaN material in the first element (DEV1) and the second element (DEV2) can be made different, thereby making the physical properties of the first barrier layer (102a) and the second barrier layer (102b) different, and making the 2DEG density different.

[0078] By varying the N-type doping concentration of the barrier layers (102a, 102b), the physical properties of the first barrier layer (102a) and the second barrier layer (102b) can be varied, and the 2DEG density can also be varied.

[0079] Due to the difference in the properties of the first barrier layer (102a) and the second barrier layer (102b), the electron densities of the first two-dimensional electron gas region and the second two-dimensional electron gas region may be different from each other. For example, the electron density of the second two-dimensional electron gas region may be higher than the electron density of the first two-dimensional electron gas region.

[0080] The doping concentrations of the first barrier layer (102a) and the second barrier layer (102b) may be different, and the 2DEG densities of the first element (DEV1) and the second element (DEV2) may be different. For example, the 2DEG density of the second element (DEV2) may be 1.5 times or more the 2DEG density of the first element (DEV1).

[0081] Fig. 3 is a drawing showing the configuration of a switching element according to one embodiment.

[0082] Referring to FIG. 3, the second element (DEV2, switching element) included in the GaN HEMT may include a second drain terminal (D2), a gate terminal (GT), a ground plate (122), a second barrier layer (102b), a channel layer (132), etc.

[0083] The on / off of the GaN HEMT can be determined depending on the magnitude of the voltage (hereinafter referred to as the gate voltage) formed between the gate terminal (GT) and the second drain terminal (D2) in the second device (DEV2). For example, if the gate voltage is higher than the threshold voltage, the GaN HEMT can be turned on. And, if the gate voltage is lower than the threshold voltage, the GaN HEMT can be turned off.

[0084] Meanwhile, if the gate voltage is higher than the threshold voltage, a channel is formed in the channel region of the GaN HEMT, and electrons can move from the second drain terminal (D2) to the first drain terminal. At this time, the electrons can have a very high energy state. This state is also called a 'hot' state. If these high-energy electrons collide with the lattice inside the GaN HEMT, various negative effects can occur. For example, the threshold voltage may change, the device may deteriorate, and a leakage current may flow through the insulator of the gate terminal (GT). The phenomenon that causes these negative effects is called Hot Carrier Injection (HCI).

[0085] The grounding plate (122) can mitigate this HCI phenomenon. The grounding plate (122) can be connected to the ground. This grounding plate (122) can reduce the peak electric field. In addition, this can mitigate the aforementioned HCI phenomenon.

[0086] A parasitic capacitance called feedback capacitance may be formed between the gate terminal (GT) and the second drain terminal (D2). This capacitance may deteriorate the voltage gain and / or frequency response of the second element (DEV2). The ground plate (122) also has the effect of alleviating this feedback capacitance.

[0087] The grounding plate (122) has the effect of reducing the second drift resistance in addition to the aforementioned HCI mitigation effect and feedback capacitance mitigation effect. However, as the length of the grounding plate (122) increases, the length of the second drift region also increases, which may increase the size of the second drift resistance.

[0088] In order to reduce the size of the second drift resistor, the designer can determine the length (lgft) of the ground plate (122) in the direction from the second drain terminal (D2) to the gate terminal (GT) as the minimum length of the predetermined design rule (DR: Design Rules).

[0089] The design rule (DR) can predetermine the smallest width or length that can be manufactured in the processes for producing the second element (DEV2). The minimum sizes of lines, gates, holes, etc. can be defined according to this design rule (DR). The length (lgft) of the ground plate (122) in the direction from the second drain terminal (D2) to the gate terminal (GT) can be determined as the minimum length of the predetermined design rule (DR), thereby minimizing the increase in the second drift resistance due to the length of the ground plate (122).

[0090] Fig. 4 is a drawing showing the configuration of a voltage blocking element according to one embodiment.

[0091] Referring to FIG. 4, the first element (DEV1, voltage blocking element) included in the GaN HEMT may include a first drain terminal (D1), a gate terminal (GT), a first barrier layer (102a), a channel layer (132), etc.

[0092] Unlike the second element, the first element (DEV1) may not include a ground plate. The ground plate may be positioned between the gate terminal and the second drain terminal, and may not be positioned between the gate terminal (GT) and the first drain terminal (D1).

[0093] To reduce the first drift resistance, the length (lgd1) of the first drift region can be designed to be short.

[0094] The length (lgd1) between the first drain terminal (D1) and the gate terminal (GT) based on the upper surface of the channel layer (132) may be equal to the minimum allowable length of a predetermined photolithography process. By minimizing the length (lgd1) of the first drift region, the first drift resistance can be reduced.

[0095] However, if the first drift region length (lgd1) is reduced, the internal pressure (BV) may decrease. The internal pressure (BV) may increase depending on the length of the drift region, and as described above, reducing the first drift region length (lgd1) may have an effect in the direction of lowering the internal pressure (BV).

[0096] To compensate for these effects, one embodiment may apply negative biases to the gate voltage.

[0097] FIGS. 5 to 13 are drawings showing a method of forming barrier layers with different properties among the methods of manufacturing a HEMT according to one embodiment.

[0098] Referring to FIG. 5, a channel layer (132) can be formed on an AlGaN layer (142).

[0099] And, a first barrier layer (102a) having a first property can be formed on the channel layer (132). The first barrier layer (102a) can be formed by metal-organic chemical vapor deposition (MOCVD). MOCVD introduces a precursor gas such as a metal-organic compound (e.g., trimethylgallium) and a reactive gas (e.g., ammonia) into a chamber, and when the gas reaches the heated substrate surface, it is decomposed by heat to cause a chemical reaction on the substrate surface to form a desired thin film. At this time, metal atoms and other atoms can be combined through the chemical reaction to form a thin and uniform thin film on the substrate. MOCVD can form a high-quality thin film because it can precisely control the thickness and composition at the nanometer level, and can deposit a uniform thin film on a large-area substrate, which is advantageous for mass production.

[0100] In addition, a gate terminal (GT) may be formed on the first barrier layer (102a). Although omitted in the drawing, a p-GaN layer may be further formed below the gate terminal (GT) depending on the embodiment.

[0101] After depositing the first barrier layer (102a), wet cleaning can be performed to remove debris.

[0102] Referring to FIG. 6, after the gate terminal (GT) is formed, a first protective layer (1210) may be formed on the first barrier layer (102a) and the gate terminal (GT). The first protective layer (1210) may be a nitride film as a hard mask for protecting the first barrier layer (102a). For example, the first protective layer (1210) may be made of silicon nitride (Si3N4) or another nitride.

[0103] Then, a photoresist according to photopatterning may be applied on the first protective layer (1210), and development may proceed. Here, the photoresist may be applied to an area corresponding to the first element (DEV1), and may not be applied to an area corresponding to the second element (DEV2).

[0104] Referring to Fig. 7, after the first protective layer (1210) is formed and photopatterning is performed, etching can be performed with the first barrier layer (102a) as an endpoint. In addition, the photoresist applied in the previous step can also be removed.

[0105] By this etching, the first protective layer (1210) and the first barrier layer (102a) formed on the second element (DEV2) can be removed.

[0106] After this etching process, a wet cleaning may be performed to remove photoresist and etching debris.

[0107] Referring to FIG. 8, after the first barrier layer (102a) is removed from the second element (DEV2), a second barrier layer (102b) having different properties from the first barrier layer (102a) may be deposited. The deposition may be metal organic chemical vapor deposition.

[0108] According to this deposition, a first barrier layer (102a) can be formed on the first element (DEV1) at the barrier layer level, and a second barrier layer (102b) can be formed on the second element (DEV2).

[0109] Several additional processes may be performed to remove unnecessary portions from the second barrier layer (102b).

[0110] First, a second protective layer (1230) may be formed on the second barrier layer (102b). The second protective layer (1230) may be a nitride film, such as the first protective layer (1210).

[0111] Referring to FIG. 9, an oxide film (1240, 1242) may be formed on the second protective layer (1230). This oxide film (1240, 1242) may be formed by plasma-enhanced chemical vapor deposition (PECVD). PECVD can form a high-quality thin film at a low temperature. In addition, PECVD can be used on heat-sensitive substrates. In order to form the oxide film (1240, 1242) by PECVD, a reactive gas such as silane (SiH4) and oxygen (O2) or nitrogen oxide (N2O) may be introduced into the chamber to generate plasma, and an oxide film may be formed on the second protective layer (1230).

[0112] After the oxide film (1240, 1242) is formed, a polishing process using the second protective layer (1230) as an endpoint may be performed. The polishing process may be a chemical mechanical planarization (CMP) process. The surface of the deposited oxide film (1240, 1242) may be planarized by chemical and mechanical polishing.

[0113] By this polishing process, the oxide film may remain separated into a first oxide film (1240) on the side of the first element (DEV1) and a second oxide film (1242) on the side of the second element (DEV2). Here, the second oxide film (1242) may play a role in protecting the second barrier layer (102b) of the second element (DEV2) in a subsequent additional process.

[0114] Referring to FIG. 10, the first oxide film (1240) remaining on the first element (DEV1) may be removed while performing photopatterning to protect the second barrier layer (102b). The first oxide film (1240) may be removed, for example, through wet etching or dry etching. After the first oxide film (1240) is removed, any remaining photoresist may also be removed.

[0115] Referring to Fig. 11, after the first oxide film (1240) is removed, the second protective layer (1230) can be removed through an etching process. At this time, some of the second protective layer (1230) may remain due to the influence of the second oxide film (1242), etc.

[0116] Referring to FIG. 12, after the second protective layer (1230) is removed, the second barrier layer (102b) on the first element (DEV1) and the gate terminal (GT) can be removed. At this time, since the second oxide film (1242) functions as a hard mask, the second barrier layer (102b) on the second element (DEV2) can remain.

[0117] Referring to Figure 13, the remaining first protective layer, second protective layer, and second oxide film can be removed through subsequent etching processes.

[0118] In addition, a first barrier layer (102a) and a second barrier layer (102b) having different properties may be formed in the barrier layer.

[0119] Figure 14 is a graph showing the relationship between 2DEG density and on-resistance, and Figure 15 is a graph showing the relationship between 2DEG density and internal pressure.

[0120] Referring to FIGS. 14 and 15, the on-resistance (Ron) may have an inverse relationship with the 2DEG density, and the breakdown voltage (BV) and the 2DEG density may have a generally inverse relationship.

[0121] One embodiment can optimize the performance of each device and the overall performance of the HEMT by making the 2DEG density of each device different for a HEMT composed of a first device and a second device. For example, by forming the 2DEG density of the second device to be higher than the 2DEG density of the first device—for example, by forming the 2DEG density of the second device to be 1.5 times or more the 2DEG density of the first device—the on-resistance and gate charge of the second device can be made low while maintaining a high breakdown voltage of the first device.

[0122] Through this fabrication, the device size of the HEMT can be minimized while maintaining high breakdown voltage and low on-resistance and gate charge.

[0123] As described above, the present embodiment provides a solution for improving the on-resistance (Ron) performance and provides a technology that enables expansion of bi-GaN applications and reduction of die size for better packaging density and lower die cost.

[0124] The terms "include," "comprise," or "have" described above, unless otherwise specifically stated, imply that the corresponding component may be included, and therefore should be interpreted to include other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in dictionaries, should be interpreted to be consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an ideal or overly formal sense, unless explicitly defined herein.

[0125] The above description is merely an illustrative illustration of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

Claims

1. As a HEMT (high electron mobility transistor), 1st drain terminal; Gate terminal; Second drain terminal; A channel layer in which a part forms a first element together with the first drain terminal and the gate terminal, and another part forms a second element together with the second drain terminal and the gate terminal; and A barrier layer comprising a first barrier layer that forms a first two-dimensional electron gas (2DEG: Two-Dimensional Electron Gas) region at an interface with the channel layer within the first device, and a second barrier layer that forms a second two-dimensional electron gas region at an interface with the channel layer within the second device, wherein the first barrier layer and the second barrier layer have different physical properties. HEMT containing .

2. In paragraph 1, A HEMT in which the first element operates as a voltage blocking element and the second element operates as a switching element.

3. In paragraph 1, A HEMT wherein the first barrier layer and the second barrier layer include an AlGaN material, and the Al molar fractions in the first barrier layer and the second barrier layer are different from each other.

4. In paragraph 1, A HEMT in which the electron densities of the first two-dimensional electron gas region and the second two-dimensional electron gas region are different due to differences in the physical properties of the first barrier layer and the second barrier layer.

5. In paragraph 4, A HEMT in which the electron density of the second two-dimensional electron gas region is higher than the electron density of the first two-dimensional electron gas region.

6. In paragraph 1, A HEMT in which the length between the first drain terminal and the gate terminal on the upper surface of the channel layer and the length between the second drain terminal and the gate terminal are different from each other.

7. In paragraph 1, A HEMT in which the doping concentrations in the first barrier layer and the second barrier layer are different from each other.

8. In paragraph 1, The above HEMT is of the horizontal type, A HEMT in which the channel layer is arranged below the first drain terminal, the gate terminal, and the second drain terminal in the vertical direction, the first drain terminal, the gate terminal, and the second drain terminal in the horizontal direction in that order, and a ground plate is arranged between the gate terminal and the second drain terminal in the horizontal direction.

9. In paragraph 8, A HEMT wherein the ground plate is disposed between the gate terminal and the second drain terminal and is not disposed between the gate terminal and the first drain terminal.

10. As a HEMT (high electron mobility transistor), 1st drain terminal; Gate terminal; Second drain terminal; A channel layer in which a part forms a first element together with the first drain terminal and the gate terminal, and another part forms a second element together with the second drain terminal and the gate terminal; and A barrier layer that forms a two-dimensional electron gas (2DEG) region at the interface with the channel layer, and forms two-dimensional electron gas regions of different densities in the first element and the second element. HEMT containing .

11. In paragraph 10, A HEMT in which the properties of the barrier layer in the first element and the properties of the barrier layer in the second element are different from each other.

12. In paragraph 11, A HEMT in which the barrier layer comprises an AlGaN material, and the Al mole fractions of the AlGaN material in the first element and the second element are different from each other.

13. In paragraph 11, A HEMT in which the N-type doping concentrations of the barrier layer in the first device and the second device are different from each other.

14. In paragraph 10, A HEMT in which the 2DEG density of the second element is at least 1.5 times the 2DEG density of the first element.

15. In paragraph 14, A HEMT in which the first element operates as a voltage blocking element and the second element operates as a switching element.

16. A method for manufacturing a HEMT (high electron mobility transistor), A step of forming a channel layer in which some of the HEMTs form a first element together with a first drain terminal and a gate terminal, and other parts form a second element together with a second drain terminal and the gate terminal; A step of forming a first barrier layer having a first property on the channel layer; A step of forming the gate terminal on the first barrier layer; A step of forming a first protective layer on the first barrier layer and the gate terminal; A step of removing the first protective layer and the first barrier layer from the second element through etching; and A step of forming a barrier layer including the first barrier layer and the second barrier layer having different properties by stacking a second barrier layer having a second property on the etched portion of the first barrier layer. A method for manufacturing a HEMT including:

17. In paragraph 16, After laminating the second barrier layer having the second property on the etched portion of the first barrier layer, A step of forming a second protective layer on the second barrier layer; A step of forming an oxide film on the second protective layer; A step of polishing the oxide film with the second protective layer as an endpoint; A step of removing the first oxide film remaining on the first element among the above oxide films; A step of removing the second barrier layer and the second protective layer from an area except for a portion protected by the second oxide film remaining on the second element among the oxide films; and A step of removing the remaining second oxide film and the first protective layer. A method for manufacturing a HEMT, further comprising:

18. In paragraph 16, A method for manufacturing a HEMT, wherein the first barrier layer and the second barrier layer are formed by metal-organic chemical vapor deposition (MOCVD).

19. In paragraph 17, A HEMT manufacturing method in which the above oxide film is formed by plasma-enhanced chemical vapor deposition (PECVD).

20. In paragraph 17, The above polishing is a HEMT manufacturing method using chemical mechanical planarization (CMP).

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